1 /* 2 * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP 26 #define CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP 27 28 private: 29 30 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 31 // 32 // Sparc load/store emission 33 // 34 // The sparc ld/st instructions cannot accomodate displacements > 13 bits long. 35 // The following "pseudo" sparc instructions (load/store) make it easier to use the indexed addressing mode 36 // by allowing 32 bit displacements: 37 // 38 // When disp <= 13 bits long, a single load or store instruction is emitted with (disp + [d]). 39 // When disp > 13 bits long, code is emitted to set the displacement into the O7 register, 40 // and then a load or store is emitted with ([O7] + [d]). 41 // 42 43 int store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned); 44 int store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide); 45 46 int load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned); 47 int load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide); 48 49 void monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no); 50 51 int shift_amount(BasicType t); 52 53 static bool is_single_instruction(LIR_Op* op); 54 55 // Record the type of the receiver in ReceiverTypeData 56 void type_profile_helper(Register mdo, int mdo_offset_bias, 57 ciMethodData *md, ciProfileData *data, 58 Register recv, Register tmp1, Label* update_done); 59 // Setup pointers to MDO, MDO slot, also compute offset bias to access the slot. 60 void setup_md_access(ciMethod* method, int bci, 61 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias); 62 public: 63 void pack64(LIR_Opr src, LIR_Opr dst); 64 void unpack64(LIR_Opr src, LIR_Opr dst); 65 66 enum { 67 #ifdef _LP64 68 call_stub_size = 68, 69 #else 70 call_stub_size = 20, 71 #endif // _LP64 72 exception_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(128), 73 deopt_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(64) }; 74 75 #endif // CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP