1 /*
2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_NATIVEINST_X86_HPP
26 #define CPU_X86_VM_NATIVEINST_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "memory/allocation.hpp"
30 #include "runtime/icache.hpp"
31 #include "runtime/os.hpp"
32
33 // We have interfaces for the following instructions:
34 // - NativeInstruction
35 // - - NativeCall
36 // - - NativeMovConstReg
37 // - - NativeMovConstRegPatching
38 // - - NativeMovRegMem
39 // - - NativeMovRegMemPatching
40 // - - NativeJump
41 // - - NativeIllegalOpCode
42 // - - NativeGeneralJump
43 // - - NativeReturn
44 // - - NativeReturnX (return with argument)
45 // - - NativePushConst
46 // - - NativeTstRegMem
47
48 // The base class for different kinds of native instruction abstractions.
49 // Provides the primitive operations to manipulate code relative to this.
50
51 class NativeInstruction VALUE_OBJ_CLASS_SPEC {
52 friend class Relocation;
53
54 public:
55 enum Intel_specific_constants {
56 nop_instruction_code = 0x90,
57 nop_instruction_size = 1
58 };
59
60 bool is_nop() { return ubyte_at(0) == nop_instruction_code; }
61 inline bool is_call();
62 inline bool is_call_reg();
63 inline bool is_illegal();
64 inline bool is_return();
65 inline bool is_jump();
66 inline bool is_cond_jump();
67 inline bool is_safepoint_poll();
68 inline bool is_mov_literal64();
69
70 protected:
71 address addr_at(int offset) const { return address(this) + offset; }
72
73 s_char sbyte_at(int offset) const { return *(s_char*) addr_at(offset); }
74 u_char ubyte_at(int offset) const { return *(u_char*) addr_at(offset); }
75
76 jint int_at(int offset) const { return *(jint*) addr_at(offset); }
77
78 intptr_t ptr_at(int offset) const { return *(intptr_t*) addr_at(offset); }
79
80 oop oop_at (int offset) const { return *(oop*) addr_at(offset); }
81
82
83 void set_char_at(int offset, char c) { *addr_at(offset) = (u_char)c; wrote(offset); }
84 void set_int_at(int offset, jint i) { *(jint*)addr_at(offset) = i; wrote(offset); }
85 void set_ptr_at (int offset, intptr_t ptr) { *(intptr_t*) addr_at(offset) = ptr; wrote(offset); }
86 void set_oop_at (int offset, oop o) { *(oop*) addr_at(offset) = o; wrote(offset); }
87
88 // This doesn't really do anything on Intel, but it is the place where
89 // cache invalidation belongs, generically:
90 void wrote(int offset);
91
92 public:
93
94 // unit test stuff
95 static void test() {} // override for testing
96
97 inline friend NativeInstruction* nativeInstruction_at(address address);
98 };
99
100 inline NativeInstruction* nativeInstruction_at(address address) {
101 NativeInstruction* inst = (NativeInstruction*)address;
102 #ifdef ASSERT
103 //inst->verify();
104 #endif
105 return inst;
106 }
107
108 inline NativeCall* nativeCall_at(address address);
109 // The NativeCall is an abstraction for accessing/manipulating native call imm32/rel32off
110 // instructions (used to manipulate inline caches, primitive & dll calls, etc.).
111
112 class NativeCall: public NativeInstruction {
113 public:
114 enum Intel_specific_constants {
115 instruction_code = 0xE8,
116 instruction_size = 5,
117 instruction_offset = 0,
118 displacement_offset = 1,
119 return_address_offset = 5
120 };
121
122 enum { cache_line_size = BytesPerWord }; // conservative estimate!
123
124 address instruction_address() const { return addr_at(instruction_offset); }
125 address next_instruction_address() const { return addr_at(return_address_offset); }
126 int displacement() const { return (jint) int_at(displacement_offset); }
127 address displacement_address() const { return addr_at(displacement_offset); }
128 address return_address() const { return addr_at(return_address_offset); }
129 address destination() const;
130 void set_destination(address dest) {
131 #ifdef AMD64
132 assert((labs((intptr_t) dest - (intptr_t) return_address()) &
133 0xFFFFFFFF00000000) == 0,
134 "must be 32bit offset");
135 #endif // AMD64
136 set_int_at(displacement_offset, dest - return_address());
137 }
138 void set_destination_mt_safe(address dest);
139
140 void verify_alignment() { assert((intptr_t)addr_at(displacement_offset) % BytesPerInt == 0, "must be aligned"); }
141 void verify();
142 void print();
143
144 // Creation
145 inline friend NativeCall* nativeCall_at(address address);
146 inline friend NativeCall* nativeCall_before(address return_address);
147
148 static bool is_call_at(address instr) {
149 return ((*instr) & 0xFF) == NativeCall::instruction_code;
150 }
151
152 static bool is_call_before(address return_address) {
153 return is_call_at(return_address - NativeCall::return_address_offset);
154 }
155
156 static bool is_call_to(address instr, address target) {
157 return nativeInstruction_at(instr)->is_call() &&
158 nativeCall_at(instr)->destination() == target;
159 }
160
161 // MT-safe patching of a call instruction.
162 static void insert(address code_pos, address entry);
163
164 static void replace_mt_safe(address instr_addr, address code_buffer);
165 };
166
167 inline NativeCall* nativeCall_at(address address) {
168 NativeCall* call = (NativeCall*)(address - NativeCall::instruction_offset);
169 #ifdef ASSERT
170 call->verify();
171 #endif
172 return call;
173 }
174
175 inline NativeCall* nativeCall_before(address return_address) {
176 NativeCall* call = (NativeCall*)(return_address - NativeCall::return_address_offset);
177 #ifdef ASSERT
178 call->verify();
179 #endif
180 return call;
181 }
182
183 class NativeCallReg: public NativeInstruction {
184 public:
185 enum Intel_specific_constants {
186 instruction_code = 0xFF,
187 instruction_offset = 0,
188 return_address_offset_norex = 2,
189 return_address_offset_rex = 3
190 };
191
192 int next_instruction_offset() const {
193 if (ubyte_at(0) == NativeCallReg::instruction_code) {
194 return return_address_offset_norex;
195 } else {
196 return return_address_offset_rex;
197 }
198 }
199 };
200
201 // An interface for accessing/manipulating native mov reg, imm32 instructions.
202 // (used to manipulate inlined 32bit data dll calls, etc.)
203 class NativeMovConstReg: public NativeInstruction {
204 #ifdef AMD64
205 static const bool has_rex = true;
206 static const int rex_size = 1;
207 #else
208 static const bool has_rex = false;
209 static const int rex_size = 0;
210 #endif // AMD64
211 public:
212 enum Intel_specific_constants {
213 instruction_code = 0xB8,
214 instruction_size = 1 + rex_size + wordSize,
215 instruction_offset = 0,
216 data_offset = 1 + rex_size,
217 next_instruction_offset = instruction_size,
218 register_mask = 0x07
219 };
220
221 address instruction_address() const { return addr_at(instruction_offset); }
222 address next_instruction_address() const { return addr_at(next_instruction_offset); }
223 intptr_t data() const { return ptr_at(data_offset); }
224 void set_data(intptr_t x) { set_ptr_at(data_offset, x); }
225
226 void verify();
227 void print();
228
229 // unit test stuff
230 static void test() {}
231
232 // Creation
233 inline friend NativeMovConstReg* nativeMovConstReg_at(address address);
234 inline friend NativeMovConstReg* nativeMovConstReg_before(address address);
235 };
236
237 inline NativeMovConstReg* nativeMovConstReg_at(address address) {
238 NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_offset);
239 #ifdef ASSERT
240 test->verify();
241 #endif
242 return test;
243 }
244
245 inline NativeMovConstReg* nativeMovConstReg_before(address address) {
246 NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset);
247 #ifdef ASSERT
248 test->verify();
249 #endif
250 return test;
251 }
252
253 class NativeMovConstRegPatching: public NativeMovConstReg {
254 private:
255 friend NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) {
256 NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_offset);
257 #ifdef ASSERT
258 test->verify();
259 #endif
260 return test;
261 }
262 };
263
264 // An interface for accessing/manipulating native moves of the form:
265 // mov[b/w/l/q] [reg + offset], reg (instruction_code_reg2mem)
266 // mov[b/w/l/q] reg, [reg+offset] (instruction_code_mem2reg
267 // mov[s/z]x[w/b/q] [reg + offset], reg
268 // fld_s [reg+offset]
269 // fld_d [reg+offset]
270 // fstp_s [reg + offset]
271 // fstp_d [reg + offset]
272 // mov_literal64 scratch,<pointer> ; mov[b/w/l/q] 0(scratch),reg | mov[b/w/l/q] reg,0(scratch)
273 //
274 // Warning: These routines must be able to handle any instruction sequences
275 // that are generated as a result of the load/store byte,word,long
276 // macros. For example: The load_unsigned_byte instruction generates
277 // an xor reg,reg inst prior to generating the movb instruction. This
278 // class must skip the xor instruction.
279
280 class NativeMovRegMem: public NativeInstruction {
281 public:
282 enum Intel_specific_constants {
283 instruction_prefix_wide_lo = Assembler::REX,
284 instruction_prefix_wide_hi = Assembler::REX_WRXB,
285 instruction_code_xor = 0x33,
286 instruction_extended_prefix = 0x0F,
287 instruction_code_mem2reg_movslq = 0x63,
288 instruction_code_mem2reg_movzxb = 0xB6,
289 instruction_code_mem2reg_movsxb = 0xBE,
290 instruction_code_mem2reg_movzxw = 0xB7,
291 instruction_code_mem2reg_movsxw = 0xBF,
292 instruction_operandsize_prefix = 0x66,
293 instruction_code_reg2mem = 0x89,
294 instruction_code_mem2reg = 0x8b,
295 instruction_code_reg2memb = 0x88,
296 instruction_code_mem2regb = 0x8a,
297 instruction_code_float_s = 0xd9,
298 instruction_code_float_d = 0xdd,
299 instruction_code_long_volatile = 0xdf,
300 instruction_code_xmm_ss_prefix = 0xf3,
301 instruction_code_xmm_sd_prefix = 0xf2,
302 instruction_code_xmm_code = 0x0f,
303 instruction_code_xmm_load = 0x10,
304 instruction_code_xmm_store = 0x11,
305 instruction_code_xmm_lpd = 0x12,
306
307 instruction_VEX_prefix_2bytes = Assembler::VEX_2bytes,
308 instruction_VEX_prefix_3bytes = Assembler::VEX_3bytes,
309
310 instruction_size = 4,
311 instruction_offset = 0,
312 data_offset = 2,
313 next_instruction_offset = 4
314 };
315
316 // helper
317 int instruction_start() const;
318
319 address instruction_address() const;
320
321 address next_instruction_address() const;
322
323 int offset() const;
324
325 void set_offset(int x);
326
327 void add_offset_in_bytes(int add_offset) { set_offset ( ( offset() + add_offset ) ); }
328
329 void verify();
330 void print ();
331
332 // unit test stuff
333 static void test() {}
334
335 private:
336 inline friend NativeMovRegMem* nativeMovRegMem_at (address address);
337 };
338
339 inline NativeMovRegMem* nativeMovRegMem_at (address address) {
340 NativeMovRegMem* test = (NativeMovRegMem*)(address - NativeMovRegMem::instruction_offset);
341 #ifdef ASSERT
342 test->verify();
343 #endif
344 return test;
345 }
346
347
348 // An interface for accessing/manipulating native leal instruction of form:
349 // leal reg, [reg + offset]
350
351 class NativeLoadAddress: public NativeMovRegMem {
352 #ifdef AMD64
353 static const bool has_rex = true;
354 static const int rex_size = 1;
355 #else
356 static const bool has_rex = false;
357 static const int rex_size = 0;
358 #endif // AMD64
359 public:
360 enum Intel_specific_constants {
361 instruction_prefix_wide = Assembler::REX_W,
362 instruction_prefix_wide_extended = Assembler::REX_WB,
363 lea_instruction_code = 0x8D,
364 mov64_instruction_code = 0xB8
365 };
366
367 void verify();
368 void print ();
369
370 // unit test stuff
371 static void test() {}
372
373 private:
374 friend NativeLoadAddress* nativeLoadAddress_at (address address) {
375 NativeLoadAddress* test = (NativeLoadAddress*)(address - instruction_offset);
376 #ifdef ASSERT
377 test->verify();
378 #endif
379 return test;
380 }
381 };
382
383 // jump rel32off
384
385 class NativeJump: public NativeInstruction {
386 public:
387 enum Intel_specific_constants {
388 instruction_code = 0xe9,
389 instruction_size = 5,
390 instruction_offset = 0,
391 data_offset = 1,
392 next_instruction_offset = 5
393 };
394
395 address instruction_address() const { return addr_at(instruction_offset); }
396 address next_instruction_address() const { return addr_at(next_instruction_offset); }
397 address jump_destination() const {
398 address dest = (int_at(data_offset)+next_instruction_address());
399 // 32bit used to encode unresolved jmp as jmp -1
400 // 64bit can't produce this so it used jump to self.
401 // Now 32bit and 64bit use jump to self as the unresolved address
402 // which the inline cache code (and relocs) know about
403
404 // return -1 if jump to self
405 dest = (dest == (address) this) ? (address) -1 : dest;
406 return dest;
407 }
408
409 void set_jump_destination(address dest) {
410 intptr_t val = dest - next_instruction_address();
411 if (dest == (address) -1) {
412 val = -5; // jump to self
413 }
414 #ifdef AMD64
415 assert((labs(val) & 0xFFFFFFFF00000000) == 0 || dest == (address)-1, "must be 32bit offset or -1");
416 #endif // AMD64
417 set_int_at(data_offset, (jint)val);
418 }
419
420 // Creation
421 inline friend NativeJump* nativeJump_at(address address);
422
423 void verify();
424
425 // Unit testing stuff
426 static void test() {}
427
428 // Insertion of native jump instruction
429 static void insert(address code_pos, address entry);
430 // MT-safe insertion of native jump at verified method entry
431 static void check_verified_entry_alignment(address entry, address verified_entry);
432 static void patch_verified_entry(address entry, address verified_entry, address dest);
433 };
434
435 inline NativeJump* nativeJump_at(address address) {
436 NativeJump* jump = (NativeJump*)(address - NativeJump::instruction_offset);
437 #ifdef ASSERT
438 jump->verify();
439 #endif
440 return jump;
441 }
442
443 // Handles all kinds of jump on Intel. Long/far, conditional/unconditional
444 class NativeGeneralJump: public NativeInstruction {
445 public:
446 enum Intel_specific_constants {
447 // Constants does not apply, since the lengths and offsets depends on the actual jump
448 // used
449 // Instruction codes:
450 // Unconditional jumps: 0xE9 (rel32off), 0xEB (rel8off)
451 // Conditional jumps: 0x0F8x (rel32off), 0x7x (rel8off)
452 unconditional_long_jump = 0xe9,
453 unconditional_short_jump = 0xeb,
454 instruction_size = 5
455 };
456
457 address instruction_address() const { return addr_at(0); }
458 address jump_destination() const;
459
460 // Creation
461 inline friend NativeGeneralJump* nativeGeneralJump_at(address address);
462
463 // Insertion of native general jump instruction
464 static void insert_unconditional(address code_pos, address entry);
465 static void replace_mt_safe(address instr_addr, address code_buffer);
466
467 void verify();
468 };
469
470 inline NativeGeneralJump* nativeGeneralJump_at(address address) {
471 NativeGeneralJump* jump = (NativeGeneralJump*)(address);
472 debug_only(jump->verify();)
473 return jump;
474 }
475
476 class NativePopReg : public NativeInstruction {
477 public:
478 enum Intel_specific_constants {
479 instruction_code = 0x58,
480 instruction_size = 1,
481 instruction_offset = 0,
482 data_offset = 1,
483 next_instruction_offset = 1
484 };
485
486 // Insert a pop instruction
487 static void insert(address code_pos, Register reg);
488 };
489
490
491 class NativeIllegalInstruction: public NativeInstruction {
492 public:
493 enum Intel_specific_constants {
494 instruction_code = 0x0B0F, // Real byte order is: 0x0F, 0x0B
495 instruction_size = 2,
496 instruction_offset = 0,
497 next_instruction_offset = 2
498 };
499
500 // Insert illegal opcode as specific address
501 static void insert(address code_pos);
502 };
503
504 // return instruction that does not pop values of the stack
505 class NativeReturn: public NativeInstruction {
506 public:
507 enum Intel_specific_constants {
508 instruction_code = 0xC3,
509 instruction_size = 1,
510 instruction_offset = 0,
511 next_instruction_offset = 1
512 };
513 };
514
515 // return instruction that does pop values of the stack
516 class NativeReturnX: public NativeInstruction {
517 public:
518 enum Intel_specific_constants {
519 instruction_code = 0xC2,
520 instruction_size = 2,
521 instruction_offset = 0,
522 next_instruction_offset = 2
523 };
524 };
525
526 // Simple test vs memory
527 class NativeTstRegMem: public NativeInstruction {
528 public:
529 enum Intel_specific_constants {
530 instruction_rex_prefix_mask = 0xF0,
531 instruction_rex_prefix = Assembler::REX,
532 instruction_code_memXregl = 0x85,
533 modrm_mask = 0x38, // select reg from the ModRM byte
534 modrm_reg = 0x00 // rax
535 };
536 };
537
538 inline bool NativeInstruction::is_illegal() { return (short)int_at(0) == (short)NativeIllegalInstruction::instruction_code; }
539 inline bool NativeInstruction::is_call() { return ubyte_at(0) == NativeCall::instruction_code; }
540 inline bool NativeInstruction::is_call_reg() { return ubyte_at(0) == NativeCallReg::instruction_code ||
541 (ubyte_at(1) == NativeCallReg::instruction_code &&
542 (ubyte_at(0) == Assembler::REX || ubyte_at(0) == Assembler::REX_B)); }
543 inline bool NativeInstruction::is_return() { return ubyte_at(0) == NativeReturn::instruction_code ||
544 ubyte_at(0) == NativeReturnX::instruction_code; }
545 inline bool NativeInstruction::is_jump() { return ubyte_at(0) == NativeJump::instruction_code ||
546 ubyte_at(0) == 0xEB; /* short jump */ }
547 inline bool NativeInstruction::is_cond_jump() { return (int_at(0) & 0xF0FF) == 0x800F /* long jump */ ||
548 (ubyte_at(0) & 0xF0) == 0x70; /* short jump */ }
549 inline bool NativeInstruction::is_safepoint_poll() {
550 #ifdef AMD64
551 // Try decoding a near safepoint first:
552 if (ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl &&
553 ubyte_at(1) == 0x05) { // 00 rax 101
554 address fault = addr_at(6) + int_at(2);
555 NOT_JVMCI(assert(!Assembler::is_polling_page_far(), "unexpected poll encoding");)
556 return os::is_poll_address(fault);
557 }
558 // Now try decoding a far safepoint:
559 // two cases, depending on the choice of the base register in the address.
560 if (((ubyte_at(0) & NativeTstRegMem::instruction_rex_prefix_mask) == NativeTstRegMem::instruction_rex_prefix &&
561 ubyte_at(1) == NativeTstRegMem::instruction_code_memXregl &&
562 (ubyte_at(2) & NativeTstRegMem::modrm_mask) == NativeTstRegMem::modrm_reg) ||
563 ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl &&
564 (ubyte_at(1) & NativeTstRegMem::modrm_mask) == NativeTstRegMem::modrm_reg) {
565 NOT_JVMCI(assert(Assembler::is_polling_page_far(), "unexpected poll encoding");)
566 return true;
567 }
568 return false;
569 #else
570 return ( ubyte_at(0) == NativeMovRegMem::instruction_code_mem2reg ||
571 ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl ) &&
572 (ubyte_at(1)&0xC7) == 0x05 && /* Mod R/M == disp32 */
573 (os::is_poll_address((address)int_at(2)));
574 #endif // AMD64
575 }
576
577 inline bool NativeInstruction::is_mov_literal64() {
578 #ifdef AMD64
579 return ((ubyte_at(0) == Assembler::REX_W || ubyte_at(0) == Assembler::REX_WB) &&
580 (ubyte_at(1) & (0xff ^ NativeMovConstReg::register_mask)) == 0xB8);
581 #else
582 return false;
583 #endif // AMD64
584 }
585
586 #endif // CPU_X86_VM_NATIVEINST_X86_HPP