1 /*
2 * Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2016 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "c1/c1_Compilation.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "c1/c1_ValueStack.hpp"
32 #include "ci/ciArrayKlass.hpp"
33 #include "ci/ciInstance.hpp"
34 #include "gc/shared/collectedHeap.hpp"
35 #include "gc/shared/barrierSet.hpp"
36 #include "gc/shared/cardTableModRefBS.hpp"
37 #include "nativeInst_s390.hpp"
38 #include "oops/objArrayKlass.hpp"
39 #include "runtime/sharedRuntime.hpp"
40 #include "vmreg_s390.inline.hpp"
41
42 #define __ _masm->
43
44 #ifndef PRODUCT
45 #undef __
46 #define __ (Verbose ? (_masm->block_comment(FILE_AND_LINE),_masm) : _masm)->
47 #endif
48
49 //------------------------------------------------------------
50
51 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
52 // Not used on ZARCH_64
53 ShouldNotCallThis();
54 return false;
55 }
56
57 LIR_Opr LIR_Assembler::receiverOpr() {
58 return FrameMap::Z_R2_oop_opr;
59 }
60
61 LIR_Opr LIR_Assembler::osrBufferPointer() {
62 return FrameMap::Z_R2_opr;
63 }
64
65 int LIR_Assembler::initial_frame_size_in_bytes() const {
66 return in_bytes(frame_map()->framesize_in_bytes());
67 }
68
69 // Inline cache check: done before the frame is built.
70 // The inline cached class is in Z_inline_cache(Z_R9).
71 // We fetch the class of the receiver and compare it with the cached class.
72 // If they do not match we jump to the slow case.
73 int LIR_Assembler::check_icache() {
74 Register receiver = receiverOpr()->as_register();
75 int offset = __ offset();
76 __ inline_cache_check(receiver, Z_inline_cache);
77 return offset;
78 }
79
80 void LIR_Assembler::osr_entry() {
81 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
82 //
83 // 1. Create a new compiled activation.
84 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
85 // at the osr_bci; it is not initialized.
86 // 3. Jump to the continuation address in compiled code to resume execution.
87
88 // OSR entry point
89 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
90 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
91 ValueStack* entry_state = osr_entry->end()->state();
92 int number_of_locks = entry_state->locks_size();
93
94 // Create a frame for the compiled activation.
95 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
96
97 // OSR buffer is
98 //
99 // locals[nlocals-1..0]
100 // monitors[number_of_locks-1..0]
101 //
102 // Locals is a direct copy of the interpreter frame so in the osr buffer
103 // the first slot in the local array is the last local from the interpreter
104 // and the last slot is local[0] (receiver) from the interpreter
105 //
106 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
107 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
108 // in the interpreter frame (the method lock if a sync method)
109
110 // Initialize monitors in the compiled activation.
111 // I0: pointer to osr buffer
112 //
113 // All other registers are dead at this point and the locals will be
114 // copied into place by code emitted in the IR.
115
116 Register OSR_buf = osrBufferPointer()->as_register();
117 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
118 int monitor_offset = BytesPerWord * method()->max_locals() +
119 (2 * BytesPerWord) * (number_of_locks - 1);
120 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
121 // the OSR buffer using 2 word entries: first the lock and then
122 // the oop.
123 for (int i = 0; i < number_of_locks; i++) {
124 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
125 // Verify the interpreter's monitor has a non-null object.
126 __ asm_assert_mem8_isnot_zero(slot_offset + 1*BytesPerWord, OSR_buf, "locked object is NULL", __LINE__);
127 // Copy the lock field into the compiled activation.
128 __ z_lg(Z_R1_scratch, slot_offset + 0, OSR_buf);
129 __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_lock(i));
130 __ z_lg(Z_R1_scratch, slot_offset + 1*BytesPerWord, OSR_buf);
131 __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_object(i));
132 }
133 }
134 }
135
136 // --------------------------------------------------------------------------------------------
137
138 address LIR_Assembler::emit_call_c(address a) {
139 __ align_call_far_patchable(__ pc());
140 address call_addr = __ call_c_opt(a);
141 if (call_addr == NULL) {
142 bailout("const section overflow");
143 }
144 return call_addr;
145 }
146
147 int LIR_Assembler::emit_exception_handler() {
148 // If the last instruction is a call (typically to do a throw which
149 // is coming at the end after block reordering) the return address
150 // must still point into the code area in order to avoid assertion
151 // failures when searching for the corresponding bci. => Add a nop.
152 // (was bug 5/14/1999 - gri)
153 __ nop();
154
155 // Generate code for exception handler.
156 address handler_base = __ start_a_stub(exception_handler_size());
157 if (handler_base == NULL) {
158 // Not enough space left for the handler.
159 bailout("exception handler overflow");
160 return -1;
161 }
162
163 int offset = code_offset();
164
165 address a = Runtime1::entry_for (Runtime1::handle_exception_from_callee_id);
166 address call_addr = emit_call_c(a);
167 CHECK_BAILOUT_(-1);
168 __ should_not_reach_here();
169 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
170 __ end_a_stub();
171
172 return offset;
173 }
174
175 // Emit the code to remove the frame from the stack in the exception
176 // unwind path.
177 int LIR_Assembler::emit_unwind_handler() {
178 #ifndef PRODUCT
179 if (CommentedAssembly) {
180 _masm->block_comment("Unwind handler");
181 }
182 #endif
183
184 int offset = code_offset();
185 Register exception_oop_callee_saved = Z_R10; // Z_R10 is callee-saved.
186 Register Rtmp1 = Z_R11;
187 Register Rtmp2 = Z_R12;
188
189 // Fetch the exception from TLS and clear out exception related thread state.
190 Address exc_oop_addr = Address(Z_thread, JavaThread::exception_oop_offset());
191 Address exc_pc_addr = Address(Z_thread, JavaThread::exception_pc_offset());
192 __ z_lg(Z_EXC_OOP, exc_oop_addr);
193 __ clear_mem(exc_oop_addr, sizeof(oop));
194 __ clear_mem(exc_pc_addr, sizeof(intptr_t));
195
196 __ bind(_unwind_handler_entry);
197 __ verify_not_null_oop(Z_EXC_OOP);
198 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
199 __ lgr_if_needed(exception_oop_callee_saved, Z_EXC_OOP); // Preserve the exception.
200 }
201
202 // Preform needed unlocking.
203 MonitorExitStub* stub = NULL;
204 if (method()->is_synchronized()) {
205 // Runtime1::monitorexit_id expects lock address in Z_R1_scratch.
206 LIR_Opr lock = FrameMap::as_opr(Z_R1_scratch);
207 monitor_address(0, lock);
208 stub = new MonitorExitStub(lock, true, 0);
209 __ unlock_object(Rtmp1, Rtmp2, lock->as_register(), *stub->entry());
210 __ bind(*stub->continuation());
211 }
212
213 if (compilation()->env()->dtrace_method_probes()) {
214 ShouldNotReachHere(); // Not supported.
215 #if 0
216 __ mov(rdi, r15_thread);
217 __ mov_metadata(rsi, method()->constant_encoding());
218 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
219 #endif
220 }
221
222 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
223 __ lgr_if_needed(Z_EXC_OOP, exception_oop_callee_saved); // Restore the exception.
224 }
225
226 // Remove the activation and dispatch to the unwind handler.
227 __ pop_frame();
228 __ z_lg(Z_EXC_PC, _z_abi16(return_pc), Z_SP);
229
230 // Z_EXC_OOP: exception oop
231 // Z_EXC_PC: exception pc
232
233 // Dispatch to the unwind logic.
234 __ load_const_optimized(Z_R5, Runtime1::entry_for (Runtime1::unwind_exception_id));
235 __ z_br(Z_R5);
236
237 // Emit the slow path assembly.
238 if (stub != NULL) {
239 stub->emit_code(this);
240 }
241
242 return offset;
243 }
244
245 int LIR_Assembler::emit_deopt_handler() {
246 // If the last instruction is a call (typically to do a throw which
247 // is coming at the end after block reordering) the return address
248 // must still point into the code area in order to avoid assertion
249 // failures when searching for the corresponding bci. => Add a nop.
250 // (was bug 5/14/1999 - gri)
251 __ nop();
252
253 // Generate code for exception handler.
254 address handler_base = __ start_a_stub(deopt_handler_size());
255 if (handler_base == NULL) {
256 // Not enough space left for the handler.
257 bailout("deopt handler overflow");
258 return -1;
259 } int offset = code_offset();
260 // Size must be constant (see HandlerImpl::emit_deopt_handler).
261 __ load_const(Z_R1_scratch, SharedRuntime::deopt_blob()->unpack());
262 __ call(Z_R1_scratch);
263 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
264 __ end_a_stub();
265
266 return offset;
267 }
268
269 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
270 if (o == NULL) {
271 __ clear_reg(reg, true/*64bit*/, false/*set cc*/); // Must not kill cc set by cmove.
272 } else {
273 AddressLiteral a = __ allocate_oop_address(o);
274 bool success = __ load_oop_from_toc(reg, a, reg);
275 if (!success) {
276 bailout("const section overflow");
277 }
278 }
279 }
280
281 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
282 // Allocate a new index in table to hold the object once it's been patched.
283 int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
284 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
285
286 AddressLiteral addrlit((intptr_t)0, oop_Relocation::spec(oop_index));
287 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
288 // The NULL will be dynamically patched later so the sequence to
289 // load the address literal must not be optimized.
290 __ load_const(reg, addrlit);
291
292 patching_epilog(patch, lir_patch_normal, reg, info);
293 }
294
295 void LIR_Assembler::metadata2reg(Metadata* md, Register reg) {
296 bool success = __ set_metadata_constant(md, reg);
297 if (!success) {
298 bailout("const section overflow");
299 return;
300 }
301 }
302
303 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
304 // Allocate a new index in table to hold the klass once it's been patched.
305 int index = __ oop_recorder()->allocate_metadata_index(NULL);
306 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
307 AddressLiteral addrlit((intptr_t)0, metadata_Relocation::spec(index));
308 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
309 // The NULL will be dynamically patched later so the sequence to
310 // load the address literal must not be optimized.
311 __ load_const(reg, addrlit);
312
313 patching_epilog(patch, lir_patch_normal, reg, info);
314 }
315
316 void LIR_Assembler::emit_op3(LIR_Op3* op) {
317 switch (op->code()) {
318 case lir_idiv:
319 case lir_irem:
320 arithmetic_idiv(op->code(),
321 op->in_opr1(),
322 op->in_opr2(),
323 op->in_opr3(),
324 op->result_opr(),
325 op->info());
326 break;
327 default: ShouldNotReachHere(); break;
328 }
329 }
330
331
332 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
333 #ifdef ASSERT
334 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
335 if (op->block() != NULL) { _branch_target_blocks.append(op->block()); }
336 if (op->ublock() != NULL) { _branch_target_blocks.append(op->ublock()); }
337 #endif
338
339 if (op->cond() == lir_cond_always) {
340 if (op->info() != NULL) { add_debug_info_for_branch(op->info()); }
341 __ branch_optimized(Assembler::bcondAlways, *(op->label()));
342 } else {
343 Assembler::branch_condition acond = Assembler::bcondZero;
344 if (op->code() == lir_cond_float_branch) {
345 assert(op->ublock() != NULL, "must have unordered successor");
346 __ branch_optimized(Assembler::bcondNotOrdered, *(op->ublock()->label()));
347 }
348 switch (op->cond()) {
349 case lir_cond_equal: acond = Assembler::bcondEqual; break;
350 case lir_cond_notEqual: acond = Assembler::bcondNotEqual; break;
351 case lir_cond_less: acond = Assembler::bcondLow; break;
352 case lir_cond_lessEqual: acond = Assembler::bcondNotHigh; break;
353 case lir_cond_greaterEqual: acond = Assembler::bcondNotLow; break;
354 case lir_cond_greater: acond = Assembler::bcondHigh; break;
355 case lir_cond_belowEqual: acond = Assembler::bcondNotHigh; break;
356 case lir_cond_aboveEqual: acond = Assembler::bcondNotLow; break;
357 default: ShouldNotReachHere();
358 }
359 __ branch_optimized(acond,*(op->label()));
360 }
361 }
362
363
364 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
365 LIR_Opr src = op->in_opr();
366 LIR_Opr dest = op->result_opr();
367
368 switch (op->bytecode()) {
369 case Bytecodes::_i2l:
370 __ move_reg_if_needed(dest->as_register_lo(), T_LONG, src->as_register(), T_INT);
371 break;
372
373 case Bytecodes::_l2i:
374 __ move_reg_if_needed(dest->as_register(), T_INT, src->as_register_lo(), T_LONG);
375 break;
376
377 case Bytecodes::_i2b:
378 __ move_reg_if_needed(dest->as_register(), T_BYTE, src->as_register(), T_INT);
379 break;
380
381 case Bytecodes::_i2c:
382 __ move_reg_if_needed(dest->as_register(), T_CHAR, src->as_register(), T_INT);
383 break;
384
385 case Bytecodes::_i2s:
386 __ move_reg_if_needed(dest->as_register(), T_SHORT, src->as_register(), T_INT);
387 break;
388
389 case Bytecodes::_f2d:
390 assert(dest->is_double_fpu(), "check");
391 __ move_freg_if_needed(dest->as_double_reg(), T_DOUBLE, src->as_float_reg(), T_FLOAT);
392 break;
393
394 case Bytecodes::_d2f:
395 assert(dest->is_single_fpu(), "check");
396 __ move_freg_if_needed(dest->as_float_reg(), T_FLOAT, src->as_double_reg(), T_DOUBLE);
397 break;
398
399 case Bytecodes::_i2f:
400 __ z_cefbr(dest->as_float_reg(), src->as_register());
401 break;
402
403 case Bytecodes::_i2d:
404 __ z_cdfbr(dest->as_double_reg(), src->as_register());
405 break;
406
407 case Bytecodes::_l2f:
408 __ z_cegbr(dest->as_float_reg(), src->as_register_lo());
409 break;
410 case Bytecodes::_l2d:
411 __ z_cdgbr(dest->as_double_reg(), src->as_register_lo());
412 break;
413
414 case Bytecodes::_f2i:
415 case Bytecodes::_f2l: {
416 Label done;
417 FloatRegister Rsrc = src->as_float_reg();
418 Register Rdst = (op->bytecode() == Bytecodes::_f2i ? dest->as_register() : dest->as_register_lo());
419 __ clear_reg(Rdst, true, false);
420 __ z_cebr(Rsrc, Rsrc);
421 __ z_brno(done); // NaN -> 0
422 if (op->bytecode() == Bytecodes::_f2i) {
423 __ z_cfebr(Rdst, Rsrc, Assembler::to_zero);
424 } else { // op->bytecode() == Bytecodes::_f2l
425 __ z_cgebr(Rdst, Rsrc, Assembler::to_zero);
426 }
427 __ bind(done);
428 }
429 break;
430
431 case Bytecodes::_d2i:
432 case Bytecodes::_d2l: {
433 Label done;
434 FloatRegister Rsrc = src->as_double_reg();
435 Register Rdst = (op->bytecode() == Bytecodes::_d2i ? dest->as_register() : dest->as_register_lo());
436 __ clear_reg(Rdst, true, false); // Don't set CC.
437 __ z_cdbr(Rsrc, Rsrc);
438 __ z_brno(done); // NaN -> 0
439 if (op->bytecode() == Bytecodes::_d2i) {
440 __ z_cfdbr(Rdst, Rsrc, Assembler::to_zero);
441 } else { // Bytecodes::_d2l
442 __ z_cgdbr(Rdst, Rsrc, Assembler::to_zero);
443 }
444 __ bind(done);
445 }
446 break;
447
448 default: ShouldNotReachHere();
449 }
450 }
451
452 void LIR_Assembler::align_call(LIR_Code code) {
453 // End of call instruction must be 4 byte aligned.
454 int offset = __ offset();
455 switch (code) {
456 case lir_icvirtual_call:
457 offset += MacroAssembler::load_const_from_toc_size();
458 // no break
459 case lir_static_call:
460 case lir_optvirtual_call:
461 case lir_dynamic_call:
462 offset += NativeCall::call_far_pcrelative_displacement_offset;
463 break;
464 case lir_virtual_call: // currently, sparc-specific for niagara
465 default: ShouldNotReachHere();
466 }
467 if ((offset & (NativeCall::call_far_pcrelative_displacement_alignment-1)) != 0) {
468 __ nop();
469 }
470 }
471
472 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
473 assert((__ offset() + NativeCall::call_far_pcrelative_displacement_offset) % NativeCall::call_far_pcrelative_displacement_alignment == 0,
474 "must be aligned (offset=%d)", __ offset());
475 assert(rtype == relocInfo::none ||
476 rtype == relocInfo::opt_virtual_call_type ||
477 rtype == relocInfo::static_call_type, "unexpected rtype");
478 // Prepend each BRASL with a nop.
479 __ relocate(rtype);
480 __ z_nop();
481 __ z_brasl(Z_R14, op->addr());
482 add_call_info(code_offset(), op->info());
483 }
484
485 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
486 address virtual_call_oop_addr = NULL;
487 AddressLiteral empty_ic((address) Universe::non_oop_word());
488 virtual_call_oop_addr = __ pc();
489 bool success = __ load_const_from_toc(Z_inline_cache, empty_ic);
490 if (!success) {
491 bailout("const section overflow");
492 return;
493 }
494
495 // CALL to fixup routine. Fixup routine uses ScopeDesc info
496 // to determine who we intended to call.
497 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
498 call(op, relocInfo::none);
499 }
500
501 // not supported
502 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
503 ShouldNotReachHere();
504 }
505
506 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
507 if (from_reg != to_reg) __ z_lgr(to_reg, from_reg);
508 }
509
510 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
511 assert(src->is_constant(), "should not call otherwise");
512 assert(dest->is_stack(), "should not call otherwise");
513 LIR_Const* c = src->as_constant_ptr();
514
515 unsigned int lmem = 0;
516 unsigned int lcon = 0;
517 int64_t cbits = 0;
518 Address dest_addr;
519 switch (c->type()) {
520 case T_INT: // fall through
521 case T_FLOAT:
522 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
523 lmem = 4; lcon = 4; cbits = c->as_jint_bits();
524 break;
525
526 case T_ADDRESS:
527 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
528 lmem = 8; lcon = 4; cbits = c->as_jint_bits();
529 break;
530
531 case T_OBJECT:
532 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
533 if (c->as_jobject() == NULL) {
534 __ store_const(dest_addr, (int64_t)NULL_WORD, 8, 8);
535 } else {
536 jobject2reg(c->as_jobject(), Z_R1_scratch);
537 __ reg2mem_opt(Z_R1_scratch, dest_addr, true);
538 }
539 return;
540
541 case T_LONG: // fall through
542 case T_DOUBLE:
543 dest_addr = frame_map()->address_for_slot(dest->double_stack_ix());
544 lmem = 8; lcon = 8; cbits = (int64_t)(c->as_jlong_bits());
545 break;
546
547 default:
548 ShouldNotReachHere();
549 }
550
551 __ store_const(dest_addr, cbits, lmem, lcon);
552 }
553
554 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
555 assert(src->is_constant(), "should not call otherwise");
556 assert(dest->is_address(), "should not call otherwise");
557 // See special case in LIRGenerator::do_StoreIndexed.
558 // T_BYTE: Special case for card mark store.
559 assert(type == T_BYTE || !dest->as_address_ptr()->index()->is_valid(), "not supported");
560 LIR_Const* c = src->as_constant_ptr();
561 Address addr = as_Address(dest->as_address_ptr());
562
563 int store_offset = -1;
564 unsigned int lmem = 0;
565 unsigned int lcon = 0;
566 int64_t cbits = 0;
567 switch (type) {
568 case T_INT: // fall through
569 case T_FLOAT:
570 lmem = 4; lcon = 4; cbits = c->as_jint_bits();
571 break;
572
573 case T_ADDRESS:
574 lmem = 8; lcon = 4; cbits = c->as_jint_bits();
575 break;
576
577 case T_OBJECT: // fall through
578 case T_ARRAY:
579 if (c->as_jobject() == NULL) {
580 if (UseCompressedOops && !wide) {
581 store_offset = __ store_const(addr, (int32_t)NULL_WORD, 4, 4);
582 } else {
583 store_offset = __ store_const(addr, (int64_t)NULL_WORD, 8, 8);
584 }
585 } else {
586 jobject2reg(c->as_jobject(), Z_R1_scratch);
587 if (UseCompressedOops && !wide) {
588 __ encode_heap_oop(Z_R1_scratch);
589 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false);
590 } else {
591 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
592 }
593 }
594 assert(store_offset >= 0, "check");
595 break;
596
597 case T_LONG: // fall through
598 case T_DOUBLE:
599 lmem = 8; lcon = 8; cbits = (int64_t)(c->as_jlong_bits());
600 break;
601
602 case T_BOOLEAN: // fall through
603 case T_BYTE:
604 lmem = 1; lcon = 1; cbits = (int8_t)(c->as_jint());
605 break;
606
607 case T_CHAR: // fall through
608 case T_SHORT:
609 lmem = 2; lcon = 2; cbits = (int16_t)(c->as_jint());
610 break;
611
612 default:
613 ShouldNotReachHere();
614 };
615
616 // Index register is normally not supported, but for
617 // LIRGenerator::CardTableModRef_post_barrier we make an exception.
618 if (type == T_BYTE && dest->as_address_ptr()->index()->is_valid()) {
619 __ load_const_optimized(Z_R0_scratch, (int8_t)(c->as_jint()));
620 store_offset = __ offset();
621 if (Immediate::is_uimm12(addr.disp())) {
622 __ z_stc(Z_R0_scratch, addr);
623 } else {
624 __ z_stcy(Z_R0_scratch, addr);
625 }
626 }
627
628 if (store_offset == -1) {
629 store_offset = __ store_const(addr, cbits, lmem, lcon);
630 assert(store_offset >= 0, "check");
631 }
632
633 if (info != NULL) {
634 add_debug_info_for_null_check(store_offset, info);
635 }
636 }
637
638 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
639 assert(src->is_constant(), "should not call otherwise");
640 assert(dest->is_register(), "should not call otherwise");
641 LIR_Const* c = src->as_constant_ptr();
642
643 switch (c->type()) {
644 case T_INT: {
645 assert(patch_code == lir_patch_none, "no patching handled here");
646 __ load_const_optimized(dest->as_register(), c->as_jint());
647 break;
648 }
649
650 case T_ADDRESS: {
651 assert(patch_code == lir_patch_none, "no patching handled here");
652 __ load_const_optimized(dest->as_register(), c->as_jint());
653 break;
654 }
655
656 case T_LONG: {
657 assert(patch_code == lir_patch_none, "no patching handled here");
658 __ load_const_optimized(dest->as_register_lo(), (intptr_t)c->as_jlong());
659 break;
660 }
661
662 case T_OBJECT: {
663 if (patch_code != lir_patch_none) {
664 jobject2reg_with_patching(dest->as_register(), info);
665 } else {
666 jobject2reg(c->as_jobject(), dest->as_register());
667 }
668 break;
669 }
670
671 case T_METADATA: {
672 if (patch_code != lir_patch_none) {
673 klass2reg_with_patching(dest->as_register(), info);
674 } else {
675 metadata2reg(c->as_metadata(), dest->as_register());
676 }
677 break;
678 }
679
680 case T_FLOAT: {
681 Register toc_reg = Z_R1_scratch;
682 __ load_toc(toc_reg);
683 address const_addr = __ float_constant(c->as_jfloat());
684 if (const_addr == NULL) {
685 bailout("const section overflow");
686 break;
687 }
688 int displ = const_addr - _masm->code()->consts()->start();
689 if (dest->is_single_fpu()) {
690 __ z_ley(dest->as_float_reg(), displ, toc_reg);
691 } else {
692 assert(dest->is_single_cpu(), "Must be a cpu register.");
693 __ z_ly(dest->as_register(), displ, toc_reg);
694 }
695 }
696 break;
697
698 case T_DOUBLE: {
699 Register toc_reg = Z_R1_scratch;
700 __ load_toc(toc_reg);
701 address const_addr = __ double_constant(c->as_jdouble());
702 if (const_addr == NULL) {
703 bailout("const section overflow");
704 break;
705 }
706 int displ = const_addr - _masm->code()->consts()->start();
707 if (dest->is_double_fpu()) {
708 __ z_ldy(dest->as_double_reg(), displ, toc_reg);
709 } else {
710 assert(dest->is_double_cpu(), "Must be a long register.");
711 __ z_lg(dest->as_register_lo(), displ, toc_reg);
712 }
713 }
714 break;
715
716 default:
717 ShouldNotReachHere();
718 }
719 }
720
721 Address LIR_Assembler::as_Address(LIR_Address* addr) {
722 if (addr->base()->is_illegal()) {
723 Unimplemented();
724 }
725
726 Register base = addr->base()->as_pointer_register();
727
728 if (addr->index()->is_illegal()) {
729 return Address(base, addr->disp());
730 } else if (addr->index()->is_cpu_register()) {
731 Register index = addr->index()->as_pointer_register();
732 return Address(base, index, addr->disp());
733 } else if (addr->index()->is_constant()) {
734 intptr_t addr_offset = addr->index()->as_constant_ptr()->as_jint() + addr->disp();
735 return Address(base, addr_offset);
736 } else {
737 ShouldNotReachHere();
738 return Address();
739 }
740 }
741
742 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
743 switch (type) {
744 case T_INT:
745 case T_FLOAT: {
746 Register tmp = Z_R1_scratch;
747 Address from = frame_map()->address_for_slot(src->single_stack_ix());
748 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
749 __ mem2reg_opt(tmp, from, false);
750 __ reg2mem_opt(tmp, to, false);
751 break;
752 }
753 case T_ADDRESS:
754 case T_OBJECT: {
755 Register tmp = Z_R1_scratch;
756 Address from = frame_map()->address_for_slot(src->single_stack_ix());
757 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
758 __ mem2reg_opt(tmp, from, true);
759 __ reg2mem_opt(tmp, to, true);
760 break;
761 }
762 case T_LONG:
763 case T_DOUBLE: {
764 Register tmp = Z_R1_scratch;
765 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
766 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
767 __ mem2reg_opt(tmp, from, true);
768 __ reg2mem_opt(tmp, to, true);
769 break;
770 }
771
772 default:
773 ShouldNotReachHere();
774 }
775 }
776
777 // 4-byte accesses only! Don't use it to access 8 bytes!
778 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
779 ShouldNotCallThis();
780 return 0; // unused
781 }
782
783 // 4-byte accesses only! Don't use it to access 8 bytes!
784 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
785 ShouldNotCallThis();
786 return 0; // unused
787 }
788
789 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code,
790 CodeEmitInfo* info, bool wide, bool unaligned) {
791
792 assert(type != T_METADATA, "load of metadata ptr not supported");
793 LIR_Address* addr = src_opr->as_address_ptr();
794 LIR_Opr to_reg = dest;
795
796 Register src = addr->base()->as_pointer_register();
797 Register disp_reg = Z_R0;
798 int disp_value = addr->disp();
799 bool needs_patching = (patch_code != lir_patch_none);
800
801 if (addr->base()->type() == T_OBJECT) {
802 __ verify_oop(src);
803 }
804
805 PatchingStub* patch = NULL;
806 if (needs_patching) {
807 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
808 assert(!to_reg->is_double_cpu() ||
809 patch_code == lir_patch_none ||
810 patch_code == lir_patch_normal, "patching doesn't match register");
811 }
812
813 if (addr->index()->is_illegal()) {
814 if (!Immediate::is_simm20(disp_value)) {
815 if (needs_patching) {
816 __ load_const(Z_R1_scratch, (intptr_t)0);
817 } else {
818 __ load_const_optimized(Z_R1_scratch, disp_value);
819 }
820 disp_reg = Z_R1_scratch;
821 disp_value = 0;
822 }
823 } else {
824 if (!Immediate::is_simm20(disp_value)) {
825 __ load_const_optimized(Z_R1_scratch, disp_value);
826 __ z_la(Z_R1_scratch, 0, Z_R1_scratch, addr->index()->as_register());
827 disp_reg = Z_R1_scratch;
828 disp_value = 0;
829 }
830 disp_reg = addr->index()->as_pointer_register();
831 }
832
833 // Remember the offset of the load. The patching_epilog must be done
834 // before the call to add_debug_info, otherwise the PcDescs don't get
835 // entered in increasing order.
836 int offset = code_offset();
837
838 assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up");
839
840 bool short_disp = Immediate::is_uimm12(disp_value);
841
842 switch (type) {
843 case T_BOOLEAN: // fall through
844 case T_BYTE : __ z_lb(dest->as_register(), disp_value, disp_reg, src); break;
845 case T_CHAR : __ z_llgh(dest->as_register(), disp_value, disp_reg, src); break;
846 case T_SHORT :
847 if (short_disp) {
848 __ z_lh(dest->as_register(), disp_value, disp_reg, src);
849 } else {
850 __ z_lhy(dest->as_register(), disp_value, disp_reg, src);
851 }
852 break;
853 case T_INT :
854 if (short_disp) {
855 __ z_l(dest->as_register(), disp_value, disp_reg, src);
856 } else {
857 __ z_ly(dest->as_register(), disp_value, disp_reg, src);
858 }
859 break;
860 case T_ADDRESS:
861 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
862 __ z_llgf(dest->as_register(), disp_value, disp_reg, src);
863 __ decode_klass_not_null(dest->as_register());
864 } else {
865 __ z_lg(dest->as_register(), disp_value, disp_reg, src);
866 }
867 break;
868 case T_ARRAY : // fall through
869 case T_OBJECT:
870 {
871 if (UseCompressedOops && !wide) {
872 __ z_llgf(dest->as_register(), disp_value, disp_reg, src);
873 __ oop_decoder(dest->as_register(), dest->as_register(), true);
874 } else {
875 __ z_lg(dest->as_register(), disp_value, disp_reg, src);
876 }
877 break;
878 }
879 case T_FLOAT:
880 if (short_disp) {
881 __ z_le(dest->as_float_reg(), disp_value, disp_reg, src);
882 } else {
883 __ z_ley(dest->as_float_reg(), disp_value, disp_reg, src);
884 }
885 break;
886 case T_DOUBLE:
887 if (short_disp) {
888 __ z_ld(dest->as_double_reg(), disp_value, disp_reg, src);
889 } else {
890 __ z_ldy(dest->as_double_reg(), disp_value, disp_reg, src);
891 }
892 break;
893 case T_LONG : __ z_lg(dest->as_register_lo(), disp_value, disp_reg, src); break;
894 default : ShouldNotReachHere();
895 }
896 if (type == T_ARRAY || type == T_OBJECT) {
897 __ verify_oop(dest->as_register());
898 }
899
900 if (patch != NULL) {
901 patching_epilog(patch, patch_code, src, info);
902 }
903 if (info != NULL) add_debug_info_for_null_check(offset, info);
904 }
905
906 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
907 assert(src->is_stack(), "should not call otherwise");
908 assert(dest->is_register(), "should not call otherwise");
909
910 if (dest->is_single_cpu()) {
911 if (type == T_ARRAY || type == T_OBJECT) {
912 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
913 __ verify_oop(dest->as_register());
914 } else if (type == T_METADATA) {
915 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
916 } else {
917 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), false);
918 }
919 } else if (dest->is_double_cpu()) {
920 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix());
921 __ mem2reg_opt(dest->as_register_lo(), src_addr_LO, true);
922 } else if (dest->is_single_fpu()) {
923 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
924 __ mem2freg_opt(dest->as_float_reg(), src_addr, false);
925 } else if (dest->is_double_fpu()) {
926 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
927 __ mem2freg_opt(dest->as_double_reg(), src_addr, true);
928 } else {
929 ShouldNotReachHere();
930 }
931 }
932
933 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
934 assert(src->is_register(), "should not call otherwise");
935 assert(dest->is_stack(), "should not call otherwise");
936
937 if (src->is_single_cpu()) {
938 const Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
939 if (type == T_OBJECT || type == T_ARRAY) {
940 __ verify_oop(src->as_register());
941 __ reg2mem_opt(src->as_register(), dst, true);
942 } else if (type == T_METADATA) {
943 __ reg2mem_opt(src->as_register(), dst, true);
944 } else {
945 __ reg2mem_opt(src->as_register(), dst, false);
946 }
947 } else if (src->is_double_cpu()) {
948 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix());
949 __ reg2mem_opt(src->as_register_lo(), dstLO, true);
950 } else if (src->is_single_fpu()) {
951 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
952 __ freg2mem_opt(src->as_float_reg(), dst_addr, false);
953 } else if (src->is_double_fpu()) {
954 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
955 __ freg2mem_opt(src->as_double_reg(), dst_addr, true);
956 } else {
957 ShouldNotReachHere();
958 }
959 }
960
961 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
962 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
963 if (from_reg->is_double_fpu()) {
964 // double to double moves
965 assert(to_reg->is_double_fpu(), "should match");
966 __ z_ldr(to_reg->as_double_reg(), from_reg->as_double_reg());
967 } else {
968 // float to float moves
969 assert(to_reg->is_single_fpu(), "should match");
970 __ z_ler(to_reg->as_float_reg(), from_reg->as_float_reg());
971 }
972 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
973 if (from_reg->is_double_cpu()) {
974 __ z_lgr(to_reg->as_pointer_register(), from_reg->as_pointer_register());
975 } else if (to_reg->is_double_cpu()) {
976 // int to int moves
977 __ z_lgr(to_reg->as_register_lo(), from_reg->as_register());
978 } else {
979 // int to int moves
980 __ z_lgr(to_reg->as_register(), from_reg->as_register());
981 }
982 } else {
983 ShouldNotReachHere();
984 }
985 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
986 __ verify_oop(to_reg->as_register());
987 }
988 }
989
990 void LIR_Assembler::reg2mem(LIR_Opr from, LIR_Opr dest_opr, BasicType type,
991 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
992 bool wide, bool unaligned) {
993 assert(type != T_METADATA, "store of metadata ptr not supported");
994 LIR_Address* addr = dest_opr->as_address_ptr();
995
996 Register dest = addr->base()->as_pointer_register();
997 Register disp_reg = Z_R0;
998 int disp_value = addr->disp();
999 bool needs_patching = (patch_code != lir_patch_none);
1000
1001 if (addr->base()->is_oop_register()) {
1002 __ verify_oop(dest);
1003 }
1004
1005 PatchingStub* patch = NULL;
1006 if (needs_patching) {
1007 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1008 assert(!from->is_double_cpu() ||
1009 patch_code == lir_patch_none ||
1010 patch_code == lir_patch_normal, "patching doesn't match register");
1011 }
1012
1013 assert(!needs_patching || (!Immediate::is_simm20(disp_value) && addr->index()->is_illegal()), "assumption");
1014 if (addr->index()->is_illegal()) {
1015 if (!Immediate::is_simm20(disp_value)) {
1016 if (needs_patching) {
1017 __ load_const(Z_R1_scratch, (intptr_t)0);
1018 } else {
1019 __ load_const_optimized(Z_R1_scratch, disp_value);
1020 }
1021 disp_reg = Z_R1_scratch;
1022 disp_value = 0;
1023 }
1024 } else {
1025 if (!Immediate::is_simm20(disp_value)) {
1026 __ load_const_optimized(Z_R1_scratch, disp_value);
1027 __ z_la(Z_R1_scratch, 0, Z_R1_scratch, addr->index()->as_register());
1028 disp_reg = Z_R1_scratch;
1029 disp_value = 0;
1030 }
1031 disp_reg = addr->index()->as_pointer_register();
1032 }
1033
1034 assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up");
1035
1036 if (type == T_ARRAY || type == T_OBJECT) {
1037 __ verify_oop(from->as_register());
1038 }
1039
1040 bool short_disp = Immediate::is_uimm12(disp_value);
1041
1042 // Remember the offset of the store. The patching_epilog must be done
1043 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1044 // entered in increasing order.
1045 int offset = code_offset();
1046 switch (type) {
1047 case T_BOOLEAN: // fall through
1048 case T_BYTE :
1049 if (short_disp) {
1050 __ z_stc(from->as_register(), disp_value, disp_reg, dest);
1051 } else {
1052 __ z_stcy(from->as_register(), disp_value, disp_reg, dest);
1053 }
1054 break;
1055 case T_CHAR : // fall through
1056 case T_SHORT :
1057 if (short_disp) {
1058 __ z_sth(from->as_register(), disp_value, disp_reg, dest);
1059 } else {
1060 __ z_sthy(from->as_register(), disp_value, disp_reg, dest);
1061 }
1062 break;
1063 case T_INT :
1064 if (short_disp) {
1065 __ z_st(from->as_register(), disp_value, disp_reg, dest);
1066 } else {
1067 __ z_sty(from->as_register(), disp_value, disp_reg, dest);
1068 }
1069 break;
1070 case T_LONG : __ z_stg(from->as_register_lo(), disp_value, disp_reg, dest); break;
1071 case T_ADDRESS: __ z_stg(from->as_register(), disp_value, disp_reg, dest); break;
1072 break;
1073 case T_ARRAY : // fall through
1074 case T_OBJECT:
1075 {
1076 if (UseCompressedOops && !wide) {
1077 Register compressed_src = Z_R14;
1078 __ z_lgr(compressed_src, from->as_register());
1079 __ encode_heap_oop(compressed_src);
1080 offset = code_offset();
1081 if (short_disp) {
1082 __ z_st(compressed_src, disp_value, disp_reg, dest);
1083 } else {
1084 __ z_sty(compressed_src, disp_value, disp_reg, dest);
1085 }
1086 } else {
1087 __ z_stg(from->as_register(), disp_value, disp_reg, dest);
1088 }
1089 break;
1090 }
1091 case T_FLOAT :
1092 if (short_disp) {
1093 __ z_ste(from->as_float_reg(), disp_value, disp_reg, dest);
1094 } else {
1095 __ z_stey(from->as_float_reg(), disp_value, disp_reg, dest);
1096 }
1097 break;
1098 case T_DOUBLE:
1099 if (short_disp) {
1100 __ z_std(from->as_double_reg(), disp_value, disp_reg, dest);
1101 } else {
1102 __ z_stdy(from->as_double_reg(), disp_value, disp_reg, dest);
1103 }
1104 break;
1105 default: ShouldNotReachHere();
1106 }
1107
1108 if (patch != NULL) {
1109 patching_epilog(patch, patch_code, dest, info);
1110 }
1111
1112 if (info != NULL) add_debug_info_for_null_check(offset, info);
1113 }
1114
1115
1116 void LIR_Assembler::return_op(LIR_Opr result) {
1117 assert(result->is_illegal() ||
1118 (result->is_single_cpu() && result->as_register() == Z_R2) ||
1119 (result->is_double_cpu() && result->as_register_lo() == Z_R2) ||
1120 (result->is_single_fpu() && result->as_float_reg() == Z_F0) ||
1121 (result->is_double_fpu() && result->as_double_reg() == Z_F0), "convention");
1122
1123 AddressLiteral pp(os::get_polling_page());
1124 __ load_const_optimized(Z_R1_scratch, pp);
1125
1126 // Pop the frame before the safepoint code.
1127 int retPC_offset = initial_frame_size_in_bytes() + _z_abi16(return_pc);
1128 if (Displacement::is_validDisp(retPC_offset)) {
1129 __ z_lg(Z_R14, retPC_offset, Z_SP);
1130 __ add2reg(Z_SP, initial_frame_size_in_bytes());
1131 } else {
1132 __ add2reg(Z_SP, initial_frame_size_in_bytes());
1133 __ restore_return_pc();
1134 }
1135
1136 // We need to mark the code position where the load from the safepoint
1137 // polling page was emitted as relocInfo::poll_return_type here.
1138 __ relocate(relocInfo::poll_return_type);
1139 __ load_from_polling_page(Z_R1_scratch);
1140
1141 __ z_br(Z_R14); // Return to caller.
1142 }
1143
1144 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1145 AddressLiteral pp(os::get_polling_page());
1146 __ load_const_optimized(tmp->as_register_lo(), pp);
1147 guarantee(info != NULL, "Shouldn't be NULL");
1148 add_debug_info_for_branch(info);
1149 int offset = __ offset();
1150 __ relocate(relocInfo::poll_type);
1151 __ load_from_polling_page(tmp->as_register_lo());
1152 return offset;
1153 }
1154
1155 void LIR_Assembler::emit_static_call_stub() {
1156
1157 // Stub is fixed up when the corresponding call is converted from calling
1158 // compiled code to calling interpreted code.
1159
1160 address call_pc = __ pc();
1161 address stub = __ start_a_stub(call_stub_size());
1162 if (stub == NULL) {
1163 bailout("static call stub overflow");
1164 return;
1165 }
1166
1167 int start = __ offset();
1168
1169 __ relocate(static_stub_Relocation::spec(call_pc));
1170
1171 // See also Matcher::interpreter_method_oop_reg().
1172 AddressLiteral meta = __ allocate_metadata_address(NULL);
1173 bool success = __ load_const_from_toc(Z_method, meta);
1174
1175 __ set_inst_mark();
1176 AddressLiteral a((address)-1);
1177 success = success && __ load_const_from_toc(Z_R1, a);
1178 if (!success) {
1179 bailout("const section overflow");
1180 return;
1181 }
1182
1183 __ z_br(Z_R1);
1184 assert(__ offset() - start <= call_stub_size(), "stub too big");
1185 __ end_a_stub(); // Update current stubs pointer and restore insts_end.
1186 }
1187
1188 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1189 bool unsigned_comp = condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual;
1190 if (opr1->is_single_cpu()) {
1191 Register reg1 = opr1->as_register();
1192 if (opr2->is_single_cpu()) {
1193 // cpu register - cpu register
1194 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
1195 __ z_clgr(reg1, opr2->as_register());
1196 } else {
1197 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
1198 if (unsigned_comp) {
1199 __ z_clr(reg1, opr2->as_register());
1200 } else {
1201 __ z_cr(reg1, opr2->as_register());
1202 }
1203 }
1204 } else if (opr2->is_stack()) {
1205 // cpu register - stack
1206 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
1207 __ z_cg(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1208 } else {
1209 if (unsigned_comp) {
1210 __ z_cly(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1211 } else {
1212 __ z_cy(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1213 }
1214 }
1215 } else if (opr2->is_constant()) {
1216 // cpu register - constant
1217 LIR_Const* c = opr2->as_constant_ptr();
1218 if (c->type() == T_INT) {
1219 if (unsigned_comp) {
1220 __ z_clfi(reg1, c->as_jint());
1221 } else {
1222 __ z_cfi(reg1, c->as_jint());
1223 }
1224 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
1225 // In 64bit oops are single register.
1226 jobject o = c->as_jobject();
1227 if (o == NULL) {
1228 __ z_ltgr(reg1, reg1);
1229 } else {
1230 jobject2reg(o, Z_R1_scratch);
1231 __ z_cgr(reg1, Z_R1_scratch);
1232 }
1233 } else {
1234 fatal("unexpected type: %s", basictype_to_str(c->type()));
1235 }
1236 // cpu register - address
1237 } else if (opr2->is_address()) {
1238 if (op->info() != NULL) {
1239 add_debug_info_for_null_check_here(op->info());
1240 }
1241 if (unsigned_comp) {
1242 __ z_cly(reg1, as_Address(opr2->as_address_ptr()));
1243 } else {
1244 __ z_cy(reg1, as_Address(opr2->as_address_ptr()));
1245 }
1246 } else {
1247 ShouldNotReachHere();
1248 }
1249
1250 } else if (opr1->is_double_cpu()) {
1251 assert(!unsigned_comp, "unexpected");
1252 Register xlo = opr1->as_register_lo();
1253 Register xhi = opr1->as_register_hi();
1254 if (opr2->is_double_cpu()) {
1255 __ z_cgr(xlo, opr2->as_register_lo());
1256 } else if (opr2->is_constant()) {
1257 // cpu register - constant 0
1258 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
1259 __ z_ltgr(xlo, xlo);
1260 } else {
1261 ShouldNotReachHere();
1262 }
1263
1264 } else if (opr1->is_single_fpu()) {
1265 if (opr2->is_single_fpu()) {
1266 __ z_cebr(opr1->as_float_reg(), opr2->as_float_reg());
1267 } else {
1268 // stack slot
1269 Address addr = frame_map()->address_for_slot(opr2->single_stack_ix());
1270 if (Immediate::is_uimm12(addr.disp())) {
1271 __ z_ceb(opr1->as_float_reg(), addr);
1272 } else {
1273 __ z_ley(Z_fscratch_1, addr);
1274 __ z_cebr(opr1->as_float_reg(), Z_fscratch_1);
1275 }
1276 }
1277 } else if (opr1->is_double_fpu()) {
1278 if (opr2->is_double_fpu()) {
1279 __ z_cdbr(opr1->as_double_reg(), opr2->as_double_reg());
1280 } else {
1281 // stack slot
1282 Address addr = frame_map()->address_for_slot(opr2->double_stack_ix());
1283 if (Immediate::is_uimm12(addr.disp())) {
1284 __ z_cdb(opr1->as_double_reg(), addr);
1285 } else {
1286 __ z_ldy(Z_fscratch_1, addr);
1287 __ z_cdbr(opr1->as_double_reg(), Z_fscratch_1);
1288 }
1289 }
1290 } else {
1291 ShouldNotReachHere();
1292 }
1293 }
1294
1295 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
1296 Label done;
1297 Register dreg = dst->as_register();
1298
1299 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1300 assert((left->is_single_fpu() && right->is_single_fpu()) ||
1301 (left->is_double_fpu() && right->is_double_fpu()), "unexpected operand types");
1302 bool is_single = left->is_single_fpu();
1303 bool is_unordered_less = (code == lir_ucmp_fd2i);
1304 FloatRegister lreg = is_single ? left->as_float_reg() : left->as_double_reg();
1305 FloatRegister rreg = is_single ? right->as_float_reg() : right->as_double_reg();
1306 if (is_single) {
1307 __ z_cebr(lreg, rreg);
1308 } else {
1309 __ z_cdbr(lreg, rreg);
1310 }
1311 if (VM_Version::has_LoadStoreConditional()) {
1312 Register one = Z_R0_scratch;
1313 Register minus_one = Z_R1_scratch;
1314 __ z_lghi(minus_one, -1);
1315 __ z_lghi(one, 1);
1316 __ z_lghi(dreg, 0);
1317 __ z_locgr(dreg, one, is_unordered_less ? Assembler::bcondHigh : Assembler::bcondHighOrNotOrdered);
1318 __ z_locgr(dreg, minus_one, is_unordered_less ? Assembler::bcondLowOrNotOrdered : Assembler::bcondLow);
1319 } else {
1320 __ clear_reg(dreg, true, false);
1321 __ z_bre(done); // if (left == right) dst = 0
1322
1323 // if (left > right || ((code ~= cmpg) && (left <> right)) dst := 1
1324 __ z_lhi(dreg, 1);
1325 __ z_brc(is_unordered_less ? Assembler::bcondHigh : Assembler::bcondHighOrNotOrdered, done);
1326
1327 // if (left < right || ((code ~= cmpl) && (left <> right)) dst := -1
1328 __ z_lhi(dreg, -1);
1329 }
1330 } else {
1331 assert(code == lir_cmp_l2i, "check");
1332 if (VM_Version::has_LoadStoreConditional()) {
1333 Register one = Z_R0_scratch;
1334 Register minus_one = Z_R1_scratch;
1335 __ z_cgr(left->as_register_lo(), right->as_register_lo());
1336 __ z_lghi(minus_one, -1);
1337 __ z_lghi(one, 1);
1338 __ z_lghi(dreg, 0);
1339 __ z_locgr(dreg, one, Assembler::bcondHigh);
1340 __ z_locgr(dreg, minus_one, Assembler::bcondLow);
1341 } else {
1342 __ z_cgr(left->as_register_lo(), right->as_register_lo());
1343 __ z_lghi(dreg, 0); // eq value
1344 __ z_bre(done);
1345 __ z_lghi(dreg, 1); // gt value
1346 __ z_brh(done);
1347 __ z_lghi(dreg, -1); // lt value
1348 }
1349 }
1350 __ bind(done);
1351 }
1352
1353 // result = condition ? opr1 : opr2
1354 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1355 Assembler::branch_condition acond = Assembler::bcondEqual, ncond = Assembler::bcondNotEqual;
1356 switch (condition) {
1357 case lir_cond_equal: acond = Assembler::bcondEqual; ncond = Assembler::bcondNotEqual; break;
1358 case lir_cond_notEqual: acond = Assembler::bcondNotEqual; ncond = Assembler::bcondEqual; break;
1359 case lir_cond_less: acond = Assembler::bcondLow; ncond = Assembler::bcondNotLow; break;
1360 case lir_cond_lessEqual: acond = Assembler::bcondNotHigh; ncond = Assembler::bcondHigh; break;
1361 case lir_cond_greaterEqual: acond = Assembler::bcondNotLow; ncond = Assembler::bcondLow; break;
1362 case lir_cond_greater: acond = Assembler::bcondHigh; ncond = Assembler::bcondNotHigh; break;
1363 case lir_cond_belowEqual: acond = Assembler::bcondNotHigh; ncond = Assembler::bcondHigh; break;
1364 case lir_cond_aboveEqual: acond = Assembler::bcondNotLow; ncond = Assembler::bcondLow; break;
1365 default: ShouldNotReachHere();
1366 }
1367
1368 if (opr1->is_cpu_register()) {
1369 reg2reg(opr1, result);
1370 } else if (opr1->is_stack()) {
1371 stack2reg(opr1, result, result->type());
1372 } else if (opr1->is_constant()) {
1373 const2reg(opr1, result, lir_patch_none, NULL);
1374 } else {
1375 ShouldNotReachHere();
1376 }
1377
1378 if (VM_Version::has_LoadStoreConditional() && !opr2->is_constant()) {
1379 // Optimized version that does not require a branch.
1380 if (opr2->is_single_cpu()) {
1381 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
1382 __ z_locgr(result->as_register(), opr2->as_register(), ncond);
1383 } else if (opr2->is_double_cpu()) {
1384 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1385 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1386 __ z_locgr(result->as_register_lo(), opr2->as_register_lo(), ncond);
1387 } else if (opr2->is_single_stack()) {
1388 __ z_loc(result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()), ncond);
1389 } else if (opr2->is_double_stack()) {
1390 __ z_locg(result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix()), ncond);
1391 } else {
1392 ShouldNotReachHere();
1393 }
1394 } else {
1395 Label skip;
1396 __ z_brc(acond, skip);
1397 if (opr2->is_cpu_register()) {
1398 reg2reg(opr2, result);
1399 } else if (opr2->is_stack()) {
1400 stack2reg(opr2, result, result->type());
1401 } else if (opr2->is_constant()) {
1402 const2reg(opr2, result, lir_patch_none, NULL);
1403 } else {
1404 ShouldNotReachHere();
1405 }
1406 __ bind(skip);
1407 }
1408 }
1409
1410 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1411 CodeEmitInfo* info, bool pop_fpu_stack) {
1412 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1413
1414 if (left->is_single_cpu()) {
1415 assert(left == dest, "left and dest must be equal");
1416 Register lreg = left->as_register();
1417
1418 if (right->is_single_cpu()) {
1419 // cpu register - cpu register
1420 Register rreg = right->as_register();
1421 switch (code) {
1422 case lir_add: __ z_ar (lreg, rreg); break;
1423 case lir_sub: __ z_sr (lreg, rreg); break;
1424 case lir_mul: __ z_msr(lreg, rreg); break;
1425 default: ShouldNotReachHere();
1426 }
1427
1428 } else if (right->is_stack()) {
1429 // cpu register - stack
1430 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1431 switch (code) {
1432 case lir_add: __ z_ay(lreg, raddr); break;
1433 case lir_sub: __ z_sy(lreg, raddr); break;
1434 default: ShouldNotReachHere();
1435 }
1436
1437 } else if (right->is_constant()) {
1438 // cpu register - constant
1439 jint c = right->as_constant_ptr()->as_jint();
1440 switch (code) {
1441 case lir_add: __ z_agfi(lreg, c); break;
1442 case lir_sub: __ z_agfi(lreg, -c); break; // note: -min_jint == min_jint
1443 case lir_mul: __ z_msfi(lreg, c); break;
1444 default: ShouldNotReachHere();
1445 }
1446
1447 } else {
1448 ShouldNotReachHere();
1449 }
1450
1451 } else if (left->is_double_cpu()) {
1452 assert(left == dest, "left and dest must be equal");
1453 Register lreg_lo = left->as_register_lo();
1454 Register lreg_hi = left->as_register_hi();
1455
1456 if (right->is_double_cpu()) {
1457 // cpu register - cpu register
1458 Register rreg_lo = right->as_register_lo();
1459 Register rreg_hi = right->as_register_hi();
1460 assert_different_registers(lreg_lo, rreg_lo);
1461 switch (code) {
1462 case lir_add:
1463 __ z_agr(lreg_lo, rreg_lo);
1464 break;
1465 case lir_sub:
1466 __ z_sgr(lreg_lo, rreg_lo);
1467 break;
1468 case lir_mul:
1469 __ z_msgr(lreg_lo, rreg_lo);
1470 break;
1471 default:
1472 ShouldNotReachHere();
1473 }
1474
1475 } else if (right->is_constant()) {
1476 // cpu register - constant
1477 jlong c = right->as_constant_ptr()->as_jlong_bits();
1478 switch (code) {
1479 case lir_add: __ z_agfi(lreg_lo, c); break;
1480 case lir_sub:
1481 if (c != min_jint) {
1482 __ z_agfi(lreg_lo, -c);
1483 } else {
1484 // -min_jint cannot be represented as simm32 in z_agfi
1485 // min_jint sign extended: 0xffffffff80000000
1486 // -min_jint as 64 bit integer: 0x0000000080000000
1487 // 0x80000000 can be represented as uimm32 in z_algfi
1488 // lreg_lo := lreg_lo + -min_jint == lreg_lo + 0x80000000
1489 __ z_algfi(lreg_lo, UCONST64(0x80000000));
1490 }
1491 break;
1492 case lir_mul: __ z_msgfi(lreg_lo, c); break;
1493 default:
1494 ShouldNotReachHere();
1495 }
1496
1497 } else {
1498 ShouldNotReachHere();
1499 }
1500
1501 } else if (left->is_single_fpu()) {
1502 assert(left == dest, "left and dest must be equal");
1503 FloatRegister lreg = left->as_float_reg();
1504 FloatRegister rreg = right->is_single_fpu() ? right->as_float_reg() : fnoreg;
1505 Address raddr;
1506
1507 if (rreg == fnoreg) {
1508 assert(right->is_single_stack(), "constants should be loaded into register");
1509 raddr = frame_map()->address_for_slot(right->single_stack_ix());
1510 if (!Immediate::is_uimm12(raddr.disp())) {
1511 __ mem2freg_opt(rreg = Z_fscratch_1, raddr, false);
1512 }
1513 }
1514
1515 if (rreg != fnoreg) {
1516 switch (code) {
1517 case lir_add: __ z_aebr(lreg, rreg); break;
1518 case lir_sub: __ z_sebr(lreg, rreg); break;
1519 case lir_mul_strictfp: // fall through
1520 case lir_mul: __ z_meebr(lreg, rreg); break;
1521 case lir_div_strictfp: // fall through
1522 case lir_div: __ z_debr(lreg, rreg); break;
1523 default: ShouldNotReachHere();
1524 }
1525 } else {
1526 switch (code) {
1527 case lir_add: __ z_aeb(lreg, raddr); break;
1528 case lir_sub: __ z_seb(lreg, raddr); break;
1529 case lir_mul_strictfp: // fall through
1530 case lir_mul: __ z_meeb(lreg, raddr); break;
1531 case lir_div_strictfp: // fall through
1532 case lir_div: __ z_deb(lreg, raddr); break;
1533 default: ShouldNotReachHere();
1534 }
1535 }
1536 } else if (left->is_double_fpu()) {
1537 assert(left == dest, "left and dest must be equal");
1538 FloatRegister lreg = left->as_double_reg();
1539 FloatRegister rreg = right->is_double_fpu() ? right->as_double_reg() : fnoreg;
1540 Address raddr;
1541
1542 if (rreg == fnoreg) {
1543 assert(right->is_double_stack(), "constants should be loaded into register");
1544 raddr = frame_map()->address_for_slot(right->double_stack_ix());
1545 if (!Immediate::is_uimm12(raddr.disp())) {
1546 __ mem2freg_opt(rreg = Z_fscratch_1, raddr, true);
1547 }
1548 }
1549
1550 if (rreg != fnoreg) {
1551 switch (code) {
1552 case lir_add: __ z_adbr(lreg, rreg); break;
1553 case lir_sub: __ z_sdbr(lreg, rreg); break;
1554 case lir_mul_strictfp: // fall through
1555 case lir_mul: __ z_mdbr(lreg, rreg); break;
1556 case lir_div_strictfp: // fall through
1557 case lir_div: __ z_ddbr(lreg, rreg); break;
1558 default: ShouldNotReachHere();
1559 }
1560 } else {
1561 switch (code) {
1562 case lir_add: __ z_adb(lreg, raddr); break;
1563 case lir_sub: __ z_sdb(lreg, raddr); break;
1564 case lir_mul_strictfp: // fall through
1565 case lir_mul: __ z_mdb(lreg, raddr); break;
1566 case lir_div_strictfp: // fall through
1567 case lir_div: __ z_ddb(lreg, raddr); break;
1568 default: ShouldNotReachHere();
1569 }
1570 }
1571 } else if (left->is_address()) {
1572 assert(left == dest, "left and dest must be equal");
1573 assert(code == lir_add, "unsupported operation");
1574 assert(right->is_constant(), "unsupported operand");
1575 jint c = right->as_constant_ptr()->as_jint();
1576 LIR_Address* lir_addr = left->as_address_ptr();
1577 Address addr = as_Address(lir_addr);
1578 switch (lir_addr->type()) {
1579 case T_INT:
1580 __ add2mem_32(addr, c, Z_R1_scratch);
1581 break;
1582 case T_LONG:
1583 __ add2mem_64(addr, c, Z_R1_scratch);
1584 break;
1585 default:
1586 ShouldNotReachHere();
1587 }
1588 } else {
1589 ShouldNotReachHere();
1590 }
1591 }
1592
1593 void LIR_Assembler::fpop() {
1594 // do nothing
1595 }
1596
1597 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1598 switch (code) {
1599 case lir_sqrt: {
1600 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1601 FloatRegister src_reg = value->as_double_reg();
1602 FloatRegister dst_reg = dest->as_double_reg();
1603 __ z_sqdbr(dst_reg, src_reg);
1604 break;
1605 }
1606 case lir_abs: {
1607 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1608 FloatRegister src_reg = value->as_double_reg();
1609 FloatRegister dst_reg = dest->as_double_reg();
1610 __ z_lpdbr(dst_reg, src_reg);
1611 break;
1612 }
1613 default: {
1614 ShouldNotReachHere();
1615 break;
1616 }
1617 }
1618 }
1619
1620 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1621 if (left->is_single_cpu()) {
1622 Register reg = left->as_register();
1623 if (right->is_constant()) {
1624 int val = right->as_constant_ptr()->as_jint();
1625 switch (code) {
1626 case lir_logic_and: __ z_nilf(reg, val); break;
1627 case lir_logic_or: __ z_oilf(reg, val); break;
1628 case lir_logic_xor: __ z_xilf(reg, val); break;
1629 default: ShouldNotReachHere();
1630 }
1631 } else if (right->is_stack()) {
1632 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1633 switch (code) {
1634 case lir_logic_and: __ z_ny(reg, raddr); break;
1635 case lir_logic_or: __ z_oy(reg, raddr); break;
1636 case lir_logic_xor: __ z_xy(reg, raddr); break;
1637 default: ShouldNotReachHere();
1638 }
1639 } else {
1640 Register rright = right->as_register();
1641 switch (code) {
1642 case lir_logic_and: __ z_nr(reg, rright); break;
1643 case lir_logic_or : __ z_or(reg, rright); break;
1644 case lir_logic_xor: __ z_xr(reg, rright); break;
1645 default: ShouldNotReachHere();
1646 }
1647 }
1648 move_regs(reg, dst->as_register());
1649 } else {
1650 Register l_lo = left->as_register_lo();
1651 if (right->is_constant()) {
1652 __ load_const_optimized(Z_R1_scratch, right->as_constant_ptr()->as_jlong());
1653 switch (code) {
1654 case lir_logic_and:
1655 __ z_ngr(l_lo, Z_R1_scratch);
1656 break;
1657 case lir_logic_or:
1658 __ z_ogr(l_lo, Z_R1_scratch);
1659 break;
1660 case lir_logic_xor:
1661 __ z_xgr(l_lo, Z_R1_scratch);
1662 break;
1663 default: ShouldNotReachHere();
1664 }
1665 } else {
1666 Register r_lo;
1667 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
1668 r_lo = right->as_register();
1669 } else {
1670 r_lo = right->as_register_lo();
1671 }
1672 switch (code) {
1673 case lir_logic_and:
1674 __ z_ngr(l_lo, r_lo);
1675 break;
1676 case lir_logic_or:
1677 __ z_ogr(l_lo, r_lo);
1678 break;
1679 case lir_logic_xor:
1680 __ z_xgr(l_lo, r_lo);
1681 break;
1682 default: ShouldNotReachHere();
1683 }
1684 }
1685
1686 Register dst_lo = dst->as_register_lo();
1687
1688 move_regs(l_lo, dst_lo);
1689 }
1690 }
1691
1692 // See operand selection in LIRGenerator::do_ArithmeticOp_Int().
1693 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
1694 if (left->is_double_cpu()) {
1695 // 64 bit integer case
1696 assert(left->is_double_cpu(), "left must be register");
1697 assert(right->is_double_cpu() || is_power_of_2_long(right->as_jlong()),
1698 "right must be register or power of 2 constant");
1699 assert(result->is_double_cpu(), "result must be register");
1700
1701 Register lreg = left->as_register_lo();
1702 Register dreg = result->as_register_lo();
1703
1704 if (right->is_constant()) {
1705 // Convert division by a power of two into some shifts and logical operations.
1706 Register treg1 = Z_R0_scratch;
1707 Register treg2 = Z_R1_scratch;
1708 jlong divisor = right->as_jlong();
1709 jlong log_divisor = log2_long(right->as_jlong());
1710
1711 if (divisor == min_jlong) {
1712 // Min_jlong is special. Result is '0' except for min_jlong/min_jlong = 1.
1713 if (dreg == lreg) {
1714 NearLabel done;
1715 __ load_const_optimized(treg2, min_jlong);
1716 __ z_cgr(lreg, treg2);
1717 __ z_lghi(dreg, 0); // Preserves condition code.
1718 __ z_brne(done);
1719 __ z_lghi(dreg, 1); // min_jlong / min_jlong = 1
1720 __ bind(done);
1721 } else {
1722 assert_different_registers(dreg, lreg);
1723 NearLabel done;
1724 __ z_lghi(dreg, 0);
1725 __ compare64_and_branch(lreg, min_jlong, Assembler::bcondNotEqual, done);
1726 __ z_lghi(dreg, 1);
1727 __ bind(done);
1728 }
1729 return;
1730 }
1731 __ move_reg_if_needed(dreg, T_LONG, lreg, T_LONG);
1732 if (divisor == 2) {
1733 __ z_srlg(treg2, dreg, 63); // dividend < 0 ? 1 : 0
1734 } else {
1735 __ z_srag(treg2, dreg, 63); // dividend < 0 ? -1 : 0
1736 __ and_imm(treg2, divisor - 1, treg1, true);
1737 }
1738 if (code == lir_idiv) {
1739 __ z_agr(dreg, treg2);
1740 __ z_srag(dreg, dreg, log_divisor);
1741 } else {
1742 assert(code == lir_irem, "check");
1743 __ z_agr(treg2, dreg);
1744 __ and_imm(treg2, ~(divisor - 1), treg1, true);
1745 __ z_sgr(dreg, treg2);
1746 }
1747 return;
1748 }
1749
1750 // Divisor is not a power of 2 constant.
1751 Register rreg = right->as_register_lo();
1752 Register treg = temp->as_register_lo();
1753 assert(right->is_double_cpu(), "right must be register");
1754 assert(lreg == Z_R11, "see ldivInOpr()");
1755 assert(rreg != lreg, "right register must not be same as left register");
1756 assert((code == lir_idiv && dreg == Z_R11 && treg == Z_R10) ||
1757 (code == lir_irem && dreg == Z_R10 && treg == Z_R11), "see ldivInOpr(), ldivOutOpr(), lremOutOpr()");
1758
1759 Register R1 = lreg->predecessor();
1760 Register R2 = rreg;
1761 assert(code != lir_idiv || lreg==dreg, "see code below");
1762 if (code == lir_idiv) {
1763 __ z_lcgr(lreg, lreg);
1764 } else {
1765 __ clear_reg(dreg, true, false);
1766 }
1767 NearLabel done;
1768 __ compare64_and_branch(R2, -1, Assembler::bcondEqual, done);
1769 if (code == lir_idiv) {
1770 __ z_lcgr(lreg, lreg); // Revert lcgr above.
1771 }
1772 if (ImplicitDiv0Checks) {
1773 // No debug info because the idiv won't trap.
1774 // Add_debug_info_for_div0 would instantiate another DivByZeroStub,
1775 // which is unnecessary, too.
1776 add_debug_info_for_div0(__ offset(), info);
1777 }
1778 __ z_dsgr(R1, R2);
1779 __ bind(done);
1780 return;
1781 }
1782
1783 // 32 bit integer case
1784
1785 assert(left->is_single_cpu(), "left must be register");
1786 assert(right->is_single_cpu() || is_power_of_2(right->as_jint()), "right must be register or power of 2 constant");
1787 assert(result->is_single_cpu(), "result must be register");
1788
1789 Register lreg = left->as_register();
1790 Register dreg = result->as_register();
1791
1792 if (right->is_constant()) {
1793 // Convert division by a power of two into some shifts and logical operations.
1794 Register treg1 = Z_R0_scratch;
1795 Register treg2 = Z_R1_scratch;
1796 jlong divisor = right->as_jint();
1797 jlong log_divisor = log2_long(right->as_jint());
1798 __ move_reg_if_needed(dreg, T_LONG, lreg, T_INT); // sign extend
1799 if (divisor == 2) {
1800 __ z_srlg(treg2, dreg, 63); // dividend < 0 ? 1 : 0
1801 } else {
1802 __ z_srag(treg2, dreg, 63); // dividend < 0 ? -1 : 0
1803 __ and_imm(treg2, divisor - 1, treg1, true);
1804 }
1805 if (code == lir_idiv) {
1806 __ z_agr(dreg, treg2);
1807 __ z_srag(dreg, dreg, log_divisor);
1808 } else {
1809 assert(code == lir_irem, "check");
1810 __ z_agr(treg2, dreg);
1811 __ and_imm(treg2, ~(divisor - 1), treg1, true);
1812 __ z_sgr(dreg, treg2);
1813 }
1814 return;
1815 }
1816
1817 // Divisor is not a power of 2 constant.
1818 Register rreg = right->as_register();
1819 Register treg = temp->as_register();
1820 assert(right->is_single_cpu(), "right must be register");
1821 assert(lreg == Z_R11, "left register must be rax,");
1822 assert(rreg != lreg, "right register must not be same as left register");
1823 assert((code == lir_idiv && dreg == Z_R11 && treg == Z_R10)
1824 || (code == lir_irem && dreg == Z_R10 && treg == Z_R11), "see divInOpr(), divOutOpr(), remOutOpr()");
1825
1826 Register R1 = lreg->predecessor();
1827 Register R2 = rreg;
1828 __ move_reg_if_needed(lreg, T_LONG, lreg, T_INT); // sign extend
1829 if (ImplicitDiv0Checks) {
1830 // No debug info because the idiv won't trap.
1831 // Add_debug_info_for_div0 would instantiate another DivByZeroStub,
1832 // which is unnecessary, too.
1833 add_debug_info_for_div0(__ offset(), info);
1834 }
1835 __ z_dsgfr(R1, R2);
1836 }
1837
1838 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1839 assert(exceptionOop->as_register() == Z_EXC_OOP, "should match");
1840 assert(exceptionPC->as_register() == Z_EXC_PC, "should match");
1841
1842 // Exception object is not added to oop map by LinearScan
1843 // (LinearScan assumes that no oops are in fixed registers).
1844 info->add_register_oop(exceptionOop);
1845
1846 // Reuse the debug info from the safepoint poll for the throw op itself.
1847 __ get_PC(Z_EXC_PC);
1848 add_call_info(__ offset(), info); // for exception handler
1849 address stub = Runtime1::entry_for (compilation()->has_fpu_code() ? Runtime1::handle_exception_id
1850 : Runtime1::handle_exception_nofpu_id);
1851 emit_call_c(stub);
1852 }
1853
1854 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1855 assert(exceptionOop->as_register() == Z_EXC_OOP, "should match");
1856
1857 __ branch_optimized(Assembler::bcondAlways, _unwind_handler_entry);
1858 }
1859
1860 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1861 ciArrayKlass* default_type = op->expected_type();
1862 Register src = op->src()->as_register();
1863 Register dst = op->dst()->as_register();
1864 Register src_pos = op->src_pos()->as_register();
1865 Register dst_pos = op->dst_pos()->as_register();
1866 Register length = op->length()->as_register();
1867 Register tmp = op->tmp()->as_register();
1868
1869 CodeStub* stub = op->stub();
1870 int flags = op->flags();
1871 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1872 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1873
1874 // If we don't know anything, just go through the generic arraycopy.
1875 if (default_type == NULL) {
1876 Label done;
1877 // Save outgoing arguments in callee saved registers (C convention) in case
1878 // a call to System.arraycopy is needed.
1879 Register callee_saved_src = Z_R10;
1880 Register callee_saved_src_pos = Z_R11;
1881 Register callee_saved_dst = Z_R12;
1882 Register callee_saved_dst_pos = Z_R13;
1883 Register callee_saved_length = Z_ARG5; // Z_ARG5 == Z_R6 is callee saved.
1884
1885 __ lgr_if_needed(callee_saved_src, src);
1886 __ lgr_if_needed(callee_saved_src_pos, src_pos);
1887 __ lgr_if_needed(callee_saved_dst, dst);
1888 __ lgr_if_needed(callee_saved_dst_pos, dst_pos);
1889 __ lgr_if_needed(callee_saved_length, length);
1890
1891 // C function requires 64 bit values.
1892 __ z_lgfr(src_pos, src_pos);
1893 __ z_lgfr(dst_pos, dst_pos);
1894 __ z_lgfr(length, length);
1895
1896 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
1897
1898 address copyfunc_addr = StubRoutines::generic_arraycopy();
1899
1900 // Pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint.
1901
1902 // The arguments are in the corresponding registers.
1903 assert(Z_ARG1 == src, "assumption");
1904 assert(Z_ARG2 == src_pos, "assumption");
1905 assert(Z_ARG3 == dst, "assumption");
1906 assert(Z_ARG4 == dst_pos, "assumption");
1907 assert(Z_ARG5 == length, "assumption");
1908 if (copyfunc_addr == NULL) { // Use C version if stub was not generated.
1909 emit_call_c(C_entry);
1910 } else {
1911 #ifndef PRODUCT
1912 if (PrintC1Statistics) {
1913 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_generic_arraycopystub_cnt);
1914 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
1915 }
1916 #endif
1917 emit_call_c(copyfunc_addr);
1918 }
1919 CHECK_BAILOUT();
1920
1921 __ compare32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondEqual, *stub->continuation());
1922
1923 if (copyfunc_addr != NULL) {
1924 __ z_lgr(tmp, Z_RET);
1925 __ z_xilf(tmp, -1);
1926 }
1927
1928 // Restore values from callee saved registers so they are where the stub
1929 // expects them.
1930 __ lgr_if_needed(src, callee_saved_src);
1931 __ lgr_if_needed(src_pos, callee_saved_src_pos);
1932 __ lgr_if_needed(dst, callee_saved_dst);
1933 __ lgr_if_needed(dst_pos, callee_saved_dst_pos);
1934 __ lgr_if_needed(length, callee_saved_length);
1935
1936 if (copyfunc_addr != NULL) {
1937 __ z_sr(length, tmp);
1938 __ z_ar(src_pos, tmp);
1939 __ z_ar(dst_pos, tmp);
1940 }
1941 __ branch_optimized(Assembler::bcondAlways, *stub->entry());
1942
1943 __ bind(*stub->continuation());
1944 return;
1945 }
1946
1947 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
1948
1949 int elem_size = type2aelembytes(basic_type);
1950 int shift_amount;
1951
1952 switch (elem_size) {
1953 case 1 :
1954 shift_amount = 0;
1955 break;
1956 case 2 :
1957 shift_amount = 1;
1958 break;
1959 case 4 :
1960 shift_amount = 2;
1961 break;
1962 case 8 :
1963 shift_amount = 3;
1964 break;
1965 default:
1966 shift_amount = -1;
1967 ShouldNotReachHere();
1968 }
1969
1970 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
1971 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
1972 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
1973 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
1974
1975 // Length and pos's are all sign extended at this point on 64bit.
1976
1977 // test for NULL
1978 if (flags & LIR_OpArrayCopy::src_null_check) {
1979 __ compareU64_and_branch(src, (intptr_t)0, Assembler::bcondZero, *stub->entry());
1980 }
1981 if (flags & LIR_OpArrayCopy::dst_null_check) {
1982 __ compareU64_and_branch(dst, (intptr_t)0, Assembler::bcondZero, *stub->entry());
1983 }
1984
1985 // Check if negative.
1986 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1987 __ compare32_and_branch(src_pos, (intptr_t)0, Assembler::bcondLow, *stub->entry());
1988 }
1989 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1990 __ compare32_and_branch(dst_pos, (intptr_t)0, Assembler::bcondLow, *stub->entry());
1991 }
1992
1993 // If the compiler was not able to prove that exact type of the source or the destination
1994 // of the arraycopy is an array type, check at runtime if the source or the destination is
1995 // an instance type.
1996 if (flags & LIR_OpArrayCopy::type_check) {
1997 assert(Klass::_lh_neutral_value == 0, "or replace z_lt instructions");
1998
1999 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2000 __ load_klass(tmp, dst);
2001 __ z_lt(tmp, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2002 __ branch_optimized(Assembler::bcondNotLow, *stub->entry());
2003 }
2004
2005 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2006 __ load_klass(tmp, src);
2007 __ z_lt(tmp, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2008 __ branch_optimized(Assembler::bcondNotLow, *stub->entry());
2009 }
2010 }
2011
2012 if (flags & LIR_OpArrayCopy::src_range_check) {
2013 __ z_la(tmp, Address(src_pos, length));
2014 __ z_cl(tmp, src_length_addr);
2015 __ branch_optimized(Assembler::bcondHigh, *stub->entry());
2016 }
2017 if (flags & LIR_OpArrayCopy::dst_range_check) {
2018 __ z_la(tmp, Address(dst_pos, length));
2019 __ z_cl(tmp, dst_length_addr);
2020 __ branch_optimized(Assembler::bcondHigh, *stub->entry());
2021 }
2022
2023 if (flags & LIR_OpArrayCopy::length_positive_check) {
2024 __ z_ltr(length, length);
2025 __ branch_optimized(Assembler::bcondNegative, *stub->entry());
2026 }
2027
2028 // Stubs require 64 bit values.
2029 __ z_lgfr(src_pos, src_pos); // int -> long
2030 __ z_lgfr(dst_pos, dst_pos); // int -> long
2031 __ z_lgfr(length, length); // int -> long
2032
2033 if (flags & LIR_OpArrayCopy::type_check) {
2034 // We don't know the array types are compatible.
2035 if (basic_type != T_OBJECT) {
2036 // Simple test for basic type arrays.
2037 if (UseCompressedClassPointers) {
2038 __ z_l(tmp, src_klass_addr);
2039 __ z_c(tmp, dst_klass_addr);
2040 } else {
2041 __ z_lg(tmp, src_klass_addr);
2042 __ z_cg(tmp, dst_klass_addr);
2043 }
2044 __ branch_optimized(Assembler::bcondNotEqual, *stub->entry());
2045 } else {
2046 // For object arrays, if src is a sub class of dst then we can
2047 // safely do the copy.
2048 NearLabel cont, slow;
2049 Register src_klass = Z_R1_scratch;
2050 Register dst_klass = Z_R10;
2051
2052 __ load_klass(src_klass, src);
2053 __ load_klass(dst_klass, dst);
2054
2055 __ check_klass_subtype_fast_path(src_klass, dst_klass, tmp, &cont, &slow, NULL);
2056
2057 store_parameter(src_klass, 0); // sub
2058 store_parameter(dst_klass, 1); // super
2059 emit_call_c(Runtime1::entry_for (Runtime1::slow_subtype_check_id));
2060 CHECK_BAILOUT();
2061 // Sets condition code 0 for match (2 otherwise).
2062 __ branch_optimized(Assembler::bcondEqual, cont);
2063
2064 __ bind(slow);
2065
2066 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2067 if (copyfunc_addr != NULL) { // use stub if available
2068 // Src is not a sub class of dst so we have to do a
2069 // per-element check.
2070
2071 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2072 if ((flags & mask) != mask) {
2073 // Check that at least both of them object arrays.
2074 assert(flags & mask, "one of the two should be known to be an object array");
2075
2076 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2077 __ load_klass(tmp, src);
2078 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2079 __ load_klass(tmp, dst);
2080 }
2081 Address klass_lh_addr(tmp, Klass::layout_helper_offset());
2082 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2083 __ load_const_optimized(Z_R1_scratch, objArray_lh);
2084 __ z_c(Z_R1_scratch, klass_lh_addr);
2085 __ branch_optimized(Assembler::bcondNotEqual, *stub->entry());
2086 }
2087
2088 // Save outgoing arguments in callee saved registers (C convention) in case
2089 // a call to System.arraycopy is needed.
2090 Register callee_saved_src = Z_R10;
2091 Register callee_saved_src_pos = Z_R11;
2092 Register callee_saved_dst = Z_R12;
2093 Register callee_saved_dst_pos = Z_R13;
2094 Register callee_saved_length = Z_ARG5; // Z_ARG5 == Z_R6 is callee saved.
2095
2096 __ lgr_if_needed(callee_saved_src, src);
2097 __ lgr_if_needed(callee_saved_src_pos, src_pos);
2098 __ lgr_if_needed(callee_saved_dst, dst);
2099 __ lgr_if_needed(callee_saved_dst_pos, dst_pos);
2100 __ lgr_if_needed(callee_saved_length, length);
2101
2102 __ z_llgfr(length, length); // Higher 32bits must be null.
2103
2104 __ z_sllg(Z_ARG1, src_pos, shift_amount); // index -> byte offset
2105 __ z_sllg(Z_ARG2, dst_pos, shift_amount); // index -> byte offset
2106
2107 __ z_la(Z_ARG1, Address(src, Z_ARG1, arrayOopDesc::base_offset_in_bytes(basic_type)));
2108 assert_different_registers(Z_ARG1, dst, dst_pos, length);
2109 __ z_la(Z_ARG2, Address(dst, Z_ARG2, arrayOopDesc::base_offset_in_bytes(basic_type)));
2110 assert_different_registers(Z_ARG2, dst, length);
2111
2112 __ z_lgr(Z_ARG3, length);
2113 assert_different_registers(Z_ARG3, dst);
2114
2115 __ load_klass(Z_ARG5, dst);
2116 __ z_lg(Z_ARG5, Address(Z_ARG5, ObjArrayKlass::element_klass_offset()));
2117 __ z_lg(Z_ARG4, Address(Z_ARG5, Klass::super_check_offset_offset()));
2118 emit_call_c(copyfunc_addr);
2119 CHECK_BAILOUT();
2120
2121 #ifndef PRODUCT
2122 if (PrintC1Statistics) {
2123 NearLabel failed;
2124 __ compareU32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondNotEqual, failed);
2125 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_arraycopy_checkcast_cnt);
2126 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2127 __ bind(failed);
2128 }
2129 #endif
2130
2131 __ compareU32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondEqual, *stub->continuation());
2132
2133 #ifndef PRODUCT
2134 if (PrintC1Statistics) {
2135 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_arraycopy_checkcast_attempt_cnt);
2136 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2137 }
2138 #endif
2139
2140 __ z_lgr(tmp, Z_RET);
2141 __ z_xilf(tmp, -1);
2142
2143 // Restore previously spilled arguments
2144 __ lgr_if_needed(src, callee_saved_src);
2145 __ lgr_if_needed(src_pos, callee_saved_src_pos);
2146 __ lgr_if_needed(dst, callee_saved_dst);
2147 __ lgr_if_needed(dst_pos, callee_saved_dst_pos);
2148 __ lgr_if_needed(length, callee_saved_length);
2149
2150 __ z_sr(length, tmp);
2151 __ z_ar(src_pos, tmp);
2152 __ z_ar(dst_pos, tmp);
2153 }
2154
2155 __ branch_optimized(Assembler::bcondAlways, *stub->entry());
2156
2157 __ bind(cont);
2158 }
2159 }
2160
2161 #ifdef ASSERT
2162 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2163 // Sanity check the known type with the incoming class. For the
2164 // primitive case the types must match exactly with src.klass and
2165 // dst.klass each exactly matching the default type. For the
2166 // object array case, if no type check is needed then either the
2167 // dst type is exactly the expected type and the src type is a
2168 // subtype which we can't check or src is the same array as dst
2169 // but not necessarily exactly of type default_type.
2170 NearLabel known_ok, halt;
2171 metadata2reg(default_type->constant_encoding(), tmp);
2172 if (UseCompressedClassPointers) {
2173 __ encode_klass_not_null(tmp);
2174 }
2175
2176 if (basic_type != T_OBJECT) {
2177 if (UseCompressedClassPointers) { __ z_c (tmp, dst_klass_addr); }
2178 else { __ z_cg(tmp, dst_klass_addr); }
2179 __ branch_optimized(Assembler::bcondNotEqual, halt);
2180 if (UseCompressedClassPointers) { __ z_c (tmp, src_klass_addr); }
2181 else { __ z_cg(tmp, src_klass_addr); }
2182 __ branch_optimized(Assembler::bcondEqual, known_ok);
2183 } else {
2184 if (UseCompressedClassPointers) { __ z_c (tmp, dst_klass_addr); }
2185 else { __ z_cg(tmp, dst_klass_addr); }
2186 __ branch_optimized(Assembler::bcondEqual, known_ok);
2187 __ compareU64_and_branch(src, dst, Assembler::bcondEqual, known_ok);
2188 }
2189 __ bind(halt);
2190 __ stop("incorrect type information in arraycopy");
2191 __ bind(known_ok);
2192 }
2193 #endif
2194
2195 #ifndef PRODUCT
2196 if (PrintC1Statistics) {
2197 __ load_const_optimized(Z_R1_scratch, Runtime1::arraycopy_count_address(basic_type));
2198 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2199 }
2200 #endif
2201
2202 __ z_sllg(tmp, src_pos, shift_amount); // index -> byte offset
2203 __ z_sllg(Z_R1_scratch, dst_pos, shift_amount); // index -> byte offset
2204
2205 assert_different_registers(Z_ARG1, dst, dst_pos, length);
2206 __ z_la(Z_ARG1, Address(src, tmp, arrayOopDesc::base_offset_in_bytes(basic_type)));
2207 assert_different_registers(Z_ARG2, length);
2208 __ z_la(Z_ARG2, Address(dst, Z_R1_scratch, arrayOopDesc::base_offset_in_bytes(basic_type)));
2209 __ lgr_if_needed(Z_ARG3, length);
2210
2211 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2212 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2213 const char *name;
2214 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2215 __ call_VM_leaf(entry);
2216
2217 __ bind(*stub->continuation());
2218 }
2219
2220 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2221 if (dest->is_single_cpu()) {
2222 if (left->type() == T_OBJECT) {
2223 switch (code) {
2224 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2225 case lir_shr: __ z_srag (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2226 case lir_ushr: __ z_srlg (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2227 default: ShouldNotReachHere();
2228 }
2229 } else {
2230 assert(code == lir_shl || left == dest, "left and dest must be equal for 2 operand form right shifts");
2231 Register masked_count = Z_R1_scratch;
2232 __ z_lr(masked_count, count->as_register());
2233 __ z_nill(masked_count, 31);
2234 switch (code) {
2235 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), 0, masked_count); break;
2236 case lir_shr: __ z_sra (dest->as_register(), 0, masked_count); break;
2237 case lir_ushr: __ z_srl (dest->as_register(), 0, masked_count); break;
2238 default: ShouldNotReachHere();
2239 }
2240 }
2241 } else {
2242 switch (code) {
2243 case lir_shl: __ z_sllg (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2244 case lir_shr: __ z_srag (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2245 case lir_ushr: __ z_srlg (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2246 default: ShouldNotReachHere();
2247 }
2248 }
2249 }
2250
2251 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2252 if (left->type() == T_OBJECT) {
2253 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t).
2254 Register l = left->as_register();
2255 Register d = dest->as_register_lo();
2256 switch (code) {
2257 case lir_shl: __ z_sllg (d, l, count); break;
2258 case lir_shr: __ z_srag (d, l, count); break;
2259 case lir_ushr: __ z_srlg (d, l, count); break;
2260 default: ShouldNotReachHere();
2261 }
2262 return;
2263 }
2264 if (dest->is_single_cpu()) {
2265 assert(code == lir_shl || left == dest, "left and dest must be equal for 2 operand form right shifts");
2266 count = count & 0x1F; // Java spec
2267 switch (code) {
2268 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), count); break;
2269 case lir_shr: __ z_sra (dest->as_register(), count); break;
2270 case lir_ushr: __ z_srl (dest->as_register(), count); break;
2271 default: ShouldNotReachHere();
2272 }
2273 } else if (dest->is_double_cpu()) {
2274 count = count & 63; // Java spec
2275 Register l = left->as_pointer_register();
2276 Register d = dest->as_pointer_register();
2277 switch (code) {
2278 case lir_shl: __ z_sllg (d, l, count); break;
2279 case lir_shr: __ z_srag (d, l, count); break;
2280 case lir_ushr: __ z_srlg (d, l, count); break;
2281 default: ShouldNotReachHere();
2282 }
2283 } else {
2284 ShouldNotReachHere();
2285 }
2286 }
2287
2288 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2289 if (op->init_check()) {
2290 // Make sure klass is initialized & doesn't have finalizer.
2291 const int state_offset = in_bytes(InstanceKlass::init_state_offset());
2292 Register iklass = op->klass()->as_register();
2293 add_debug_info_for_null_check_here(op->stub()->info());
2294 if (Immediate::is_uimm12(state_offset)) {
2295 __ z_cli(state_offset, iklass, InstanceKlass::fully_initialized);
2296 } else {
2297 __ z_cliy(state_offset, iklass, InstanceKlass::fully_initialized);
2298 }
2299 __ branch_optimized(Assembler::bcondNotEqual, *op->stub()->entry()); // Use long branch, because slow_case might be far.
2300 }
2301 __ allocate_object(op->obj()->as_register(),
2302 op->tmp1()->as_register(),
2303 op->tmp2()->as_register(),
2304 op->header_size(),
2305 op->object_size(),
2306 op->klass()->as_register(),
2307 *op->stub()->entry());
2308 __ bind(*op->stub()->continuation());
2309 __ verify_oop(op->obj()->as_register());
2310 }
2311
2312 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2313 Register len = op->len()->as_register();
2314 __ move_reg_if_needed(len, T_LONG, len, T_INT); // sign extend
2315
2316 if (UseSlowPath ||
2317 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2318 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2319 __ z_brul(*op->stub()->entry());
2320 } else {
2321 __ allocate_array(op->obj()->as_register(),
2322 op->len()->as_register(),
2323 op->tmp1()->as_register(),
2324 op->tmp2()->as_register(),
2325 arrayOopDesc::header_size(op->type()),
2326 type2aelembytes(op->type()),
2327 op->klass()->as_register(),
2328 *op->stub()->entry());
2329 }
2330 __ bind(*op->stub()->continuation());
2331 }
2332
2333 void LIR_Assembler::type_profile_helper(Register mdo, ciMethodData *md, ciProfileData *data,
2334 Register recv, Register tmp1, Label* update_done) {
2335 uint i;
2336 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2337 Label next_test;
2338 // See if the receiver is receiver[n].
2339 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
2340 __ z_cg(recv, receiver_addr);
2341 __ z_brne(next_test);
2342 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
2343 __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1);
2344 __ branch_optimized(Assembler::bcondAlways, *update_done);
2345 __ bind(next_test);
2346 }
2347
2348 // Didn't find receiver; find next empty slot and fill it in.
2349 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2350 Label next_test;
2351 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
2352 __ z_ltg(Z_R0_scratch, recv_addr);
2353 __ z_brne(next_test);
2354 __ z_stg(recv, recv_addr);
2355 __ load_const_optimized(tmp1, DataLayout::counter_increment);
2356 __ z_stg(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)), mdo);
2357 __ branch_optimized(Assembler::bcondAlways, *update_done);
2358 __ bind(next_test);
2359 }
2360 }
2361
2362 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2363 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2364 Unimplemented();
2365 }
2366
2367 void LIR_Assembler::store_parameter(Register r, int param_num) {
2368 assert(param_num >= 0, "invalid num");
2369 int offset_in_bytes = param_num * BytesPerWord + FrameMap::first_available_sp_in_frame;
2370 assert(offset_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2371 __ z_stg(r, offset_in_bytes, Z_SP);
2372 }
2373
2374 void LIR_Assembler::store_parameter(jint c, int param_num) {
2375 assert(param_num >= 0, "invalid num");
2376 int offset_in_bytes = param_num * BytesPerWord + FrameMap::first_available_sp_in_frame;
2377 assert(offset_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2378 __ store_const(Address(Z_SP, offset_in_bytes), c, Z_R1_scratch, true);
2379 }
2380
2381 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2382 // We always need a stub for the failure case.
2383 CodeStub* stub = op->stub();
2384 Register obj = op->object()->as_register();
2385 Register k_RInfo = op->tmp1()->as_register();
2386 Register klass_RInfo = op->tmp2()->as_register();
2387 Register dst = op->result_opr()->as_register();
2388 Register Rtmp1 = Z_R1_scratch;
2389 ciKlass* k = op->klass();
2390
2391 assert(!op->tmp3()->is_valid(), "tmp3's not needed");
2392
2393 // Check if it needs to be profiled.
2394 ciMethodData* md = NULL;
2395 ciProfileData* data = NULL;
2396
2397 if (op->should_profile()) {
2398 ciMethod* method = op->profiled_method();
2399 assert(method != NULL, "Should have method");
2400 int bci = op->profiled_bci();
2401 md = method->method_data_or_null();
2402 assert(md != NULL, "Sanity");
2403 data = md->bci_to_data(bci);
2404 assert(data != NULL, "need data for type check");
2405 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2406 }
2407
2408 // Temp operands do not overlap with inputs, if this is their last
2409 // use (end of range is exclusive), so a register conflict is possible.
2410 if (obj == k_RInfo) {
2411 k_RInfo = dst;
2412 } else if (obj == klass_RInfo) {
2413 klass_RInfo = dst;
2414 }
2415 assert_different_registers(obj, k_RInfo, klass_RInfo);
2416
2417 if (op->should_profile()) {
2418 NearLabel not_null;
2419 __ compareU64_and_branch(obj, (intptr_t) 0, Assembler::bcondNotEqual, not_null);
2420 // Object is null; update MDO and exit.
2421 Register mdo = klass_RInfo;
2422 metadata2reg(md->constant_encoding(), mdo);
2423 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
2424 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
2425 __ or2mem_8(data_addr, header_bits);
2426 __ branch_optimized(Assembler::bcondAlways, *obj_is_null);
2427 __ bind(not_null);
2428 } else {
2429 __ compareU64_and_branch(obj, (intptr_t) 0, Assembler::bcondEqual, *obj_is_null);
2430 }
2431
2432 NearLabel profile_cast_failure, profile_cast_success;
2433 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
2434 Label *success_target = op->should_profile() ? &profile_cast_success : success;
2435
2436 // Patching may screw with our temporaries on sparc,
2437 // so let's do it before loading the class.
2438 if (k->is_loaded()) {
2439 metadata2reg(k->constant_encoding(), k_RInfo);
2440 } else {
2441 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2442 }
2443 assert(obj != k_RInfo, "must be different");
2444
2445 __ verify_oop(obj);
2446
2447 // Get object class.
2448 // Not a safepoint as obj null check happens earlier.
2449 if (op->fast_check()) {
2450 if (UseCompressedClassPointers) {
2451 __ load_klass(klass_RInfo, obj);
2452 __ compareU64_and_branch(k_RInfo, klass_RInfo, Assembler::bcondNotEqual, *failure_target);
2453 } else {
2454 __ z_cg(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
2455 __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2456 }
2457 // Successful cast, fall through to profile or jump.
2458 } else {
2459 bool need_slow_path = !k->is_loaded() ||
2460 ((int) k->super_check_offset() == in_bytes(Klass::secondary_super_cache_offset()));
2461 intptr_t super_check_offset = k->is_loaded() ? k->super_check_offset() : -1L;
2462 __ load_klass(klass_RInfo, obj);
2463 // Perform the fast part of the checking logic.
2464 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1,
2465 (need_slow_path ? success_target : NULL),
2466 failure_target, NULL,
2467 RegisterOrConstant(super_check_offset));
2468 if (need_slow_path) {
2469 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2470 address a = Runtime1::entry_for (Runtime1::slow_subtype_check_id);
2471 store_parameter(klass_RInfo, 0); // sub
2472 store_parameter(k_RInfo, 1); // super
2473 emit_call_c(a); // Sets condition code 0 for match (2 otherwise).
2474 CHECK_BAILOUT();
2475 __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2476 // Fall through to success case.
2477 }
2478 }
2479
2480 if (op->should_profile()) {
2481 Register mdo = klass_RInfo, recv = k_RInfo;
2482 assert_different_registers(obj, mdo, recv);
2483 __ bind(profile_cast_success);
2484 metadata2reg(md->constant_encoding(), mdo);
2485 __ load_klass(recv, obj);
2486 type_profile_helper(mdo, md, data, recv, Rtmp1, success);
2487 __ branch_optimized(Assembler::bcondAlways, *success);
2488
2489 __ bind(profile_cast_failure);
2490 metadata2reg(md->constant_encoding(), mdo);
2491 __ add2mem_64(Address(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())), -(int)DataLayout::counter_increment, Rtmp1);
2492 __ branch_optimized(Assembler::bcondAlways, *failure);
2493 } else {
2494 __ branch_optimized(Assembler::bcondAlways, *success);
2495 }
2496 }
2497
2498 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2499 LIR_Code code = op->code();
2500 if (code == lir_store_check) {
2501 Register value = op->object()->as_register();
2502 Register array = op->array()->as_register();
2503 Register k_RInfo = op->tmp1()->as_register();
2504 Register klass_RInfo = op->tmp2()->as_register();
2505 Register Rtmp1 = Z_R1_scratch;
2506
2507 CodeStub* stub = op->stub();
2508
2509 // Check if it needs to be profiled.
2510 ciMethodData* md = NULL;
2511 ciProfileData* data = NULL;
2512
2513 assert_different_registers(value, k_RInfo, klass_RInfo);
2514
2515 if (op->should_profile()) {
2516 ciMethod* method = op->profiled_method();
2517 assert(method != NULL, "Should have method");
2518 int bci = op->profiled_bci();
2519 md = method->method_data_or_null();
2520 assert(md != NULL, "Sanity");
2521 data = md->bci_to_data(bci);
2522 assert(data != NULL, "need data for type check");
2523 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2524 }
2525 NearLabel profile_cast_success, profile_cast_failure, done;
2526 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
2527 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
2528
2529 if (op->should_profile()) {
2530 NearLabel not_null;
2531 __ compareU64_and_branch(value, (intptr_t) 0, Assembler::bcondNotEqual, not_null);
2532 // Object is null; update MDO and exit.
2533 Register mdo = klass_RInfo;
2534 metadata2reg(md->constant_encoding(), mdo);
2535 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
2536 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
2537 __ or2mem_8(data_addr, header_bits);
2538 __ branch_optimized(Assembler::bcondAlways, done);
2539 __ bind(not_null);
2540 } else {
2541 __ compareU64_and_branch(value, (intptr_t) 0, Assembler::bcondEqual, done);
2542 }
2543
2544 add_debug_info_for_null_check_here(op->info_for_exception());
2545 __ load_klass(k_RInfo, array);
2546 __ load_klass(klass_RInfo, value);
2547
2548 // Get instance klass (it's already uncompressed).
2549 __ z_lg(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
2550 // Perform the fast part of the checking logic.
2551 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
2552 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2553 address a = Runtime1::entry_for (Runtime1::slow_subtype_check_id);
2554 store_parameter(klass_RInfo, 0); // sub
2555 store_parameter(k_RInfo, 1); // super
2556 emit_call_c(a); // Sets condition code 0 for match (2 otherwise).
2557 CHECK_BAILOUT();
2558 __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2559 // Fall through to success case.
2560
2561 if (op->should_profile()) {
2562 Register mdo = klass_RInfo, recv = k_RInfo;
2563 assert_different_registers(value, mdo, recv);
2564 __ bind(profile_cast_success);
2565 metadata2reg(md->constant_encoding(), mdo);
2566 __ load_klass(recv, value);
2567 type_profile_helper(mdo, md, data, recv, Rtmp1, &done);
2568 __ branch_optimized(Assembler::bcondAlways, done);
2569
2570 __ bind(profile_cast_failure);
2571 metadata2reg(md->constant_encoding(), mdo);
2572 __ add2mem_64(Address(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())), -(int)DataLayout::counter_increment, Rtmp1);
2573 __ branch_optimized(Assembler::bcondAlways, *stub->entry());
2574 }
2575
2576 __ bind(done);
2577 } else {
2578 if (code == lir_checkcast) {
2579 Register obj = op->object()->as_register();
2580 Register dst = op->result_opr()->as_register();
2581 NearLabel success;
2582 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
2583 __ bind(success);
2584 __ lgr_if_needed(dst, obj);
2585 } else {
2586 if (code == lir_instanceof) {
2587 Register obj = op->object()->as_register();
2588 Register dst = op->result_opr()->as_register();
2589 NearLabel success, failure, done;
2590 emit_typecheck_helper(op, &success, &failure, &failure);
2591 __ bind(failure);
2592 __ clear_reg(dst);
2593 __ branch_optimized(Assembler::bcondAlways, done);
2594 __ bind(success);
2595 __ load_const_optimized(dst, 1);
2596 __ bind(done);
2597 } else {
2598 ShouldNotReachHere();
2599 }
2600 }
2601 }
2602 }
2603
2604 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2605 Register addr = op->addr()->as_pointer_register();
2606 Register t1_cmp = Z_R1_scratch;
2607 if (op->code() == lir_cas_long) {
2608 assert(VM_Version::supports_cx8(), "wrong machine");
2609 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2610 Register new_value_lo = op->new_value()->as_register_lo();
2611 __ z_lgr(t1_cmp, cmp_value_lo);
2612 // Perform the compare and swap operation.
2613 __ z_csg(t1_cmp, new_value_lo, 0, addr);
2614 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2615 Register cmp_value = op->cmp_value()->as_register();
2616 Register new_value = op->new_value()->as_register();
2617 if (op->code() == lir_cas_obj) {
2618 if (UseCompressedOops) {
2619 t1_cmp = op->tmp1()->as_register();
2620 Register t2_new = op->tmp2()->as_register();
2621 assert_different_registers(cmp_value, new_value, addr, t1_cmp, t2_new);
2622 __ oop_encoder(t1_cmp, cmp_value, true /*maybe null*/);
2623 __ oop_encoder(t2_new, new_value, true /*maybe null*/);
2624 __ z_cs(t1_cmp, t2_new, 0, addr);
2625 } else {
2626 __ z_lgr(t1_cmp, cmp_value);
2627 __ z_csg(t1_cmp, new_value, 0, addr);
2628 }
2629 } else {
2630 __ z_lr(t1_cmp, cmp_value);
2631 __ z_cs(t1_cmp, new_value, 0, addr);
2632 }
2633 } else {
2634 ShouldNotReachHere(); // new lir_cas_??
2635 }
2636 }
2637
2638 void LIR_Assembler::set_24bit_FPU() {
2639 ShouldNotCallThis(); // x86 only
2640 }
2641
2642 void LIR_Assembler::reset_FPU() {
2643 ShouldNotCallThis(); // x86 only
2644 }
2645
2646 void LIR_Assembler::breakpoint() {
2647 Unimplemented();
2648 // __ breakpoint_trap();
2649 }
2650
2651 void LIR_Assembler::push(LIR_Opr opr) {
2652 ShouldNotCallThis(); // unused
2653 }
2654
2655 void LIR_Assembler::pop(LIR_Opr opr) {
2656 ShouldNotCallThis(); // unused
2657 }
2658
2659 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2660 Address addr = frame_map()->address_for_monitor_lock(monitor_no);
2661 __ add2reg(dst_opr->as_register(), addr.disp(), addr.base());
2662 }
2663
2664 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2665 Register obj = op->obj_opr()->as_register(); // May not be an oop.
2666 Register hdr = op->hdr_opr()->as_register();
2667 Register lock = op->lock_opr()->as_register();
2668 if (!UseFastLocking) {
2669 __ branch_optimized(Assembler::bcondAlways, *op->stub()->entry());
2670 } else if (op->code() == lir_lock) {
2671 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2672 // Add debug info for NullPointerException only if one is possible.
2673 if (op->info() != NULL) {
2674 add_debug_info_for_null_check_here(op->info());
2675 }
2676 __ lock_object(hdr, obj, lock, *op->stub()->entry());
2677 // done
2678 } else if (op->code() == lir_unlock) {
2679 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2680 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2681 } else {
2682 ShouldNotReachHere();
2683 }
2684 __ bind(*op->stub()->continuation());
2685 }
2686
2687 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2688 ciMethod* method = op->profiled_method();
2689 int bci = op->profiled_bci();
2690 ciMethod* callee = op->profiled_callee();
2691
2692 // Update counter for all call types.
2693 ciMethodData* md = method->method_data_or_null();
2694 assert(md != NULL, "Sanity");
2695 ciProfileData* data = md->bci_to_data(bci);
2696 assert(data->is_CounterData(), "need CounterData for calls");
2697 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2698 Register mdo = op->mdo()->as_register();
2699 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2700 Register tmp1 = op->tmp1()->as_register_lo();
2701 metadata2reg(md->constant_encoding(), mdo);
2702
2703 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2704 Bytecodes::Code bc = method->java_code_at_bci(bci);
2705 const bool callee_is_static = callee->is_loaded() && callee->is_static();
2706 // Perform additional virtual call profiling for invokevirtual and
2707 // invokeinterface bytecodes.
2708 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
2709 !callee_is_static && // Required for optimized MH invokes.
2710 C1ProfileVirtualCalls) {
2711 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2712 Register recv = op->recv()->as_register();
2713 assert_different_registers(mdo, tmp1, recv);
2714 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2715 ciKlass* known_klass = op->known_holder();
2716 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2717 // We know the type that will be seen at this call site; we can
2718 // statically update the MethodData* rather than needing to do
2719 // dynamic tests on the receiver type.
2720
2721 // NOTE: we should probably put a lock around this search to
2722 // avoid collisions by concurrent compilations.
2723 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2724 uint i;
2725 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2726 ciKlass* receiver = vc_data->receiver(i);
2727 if (known_klass->equals(receiver)) {
2728 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2729 __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1);
2730 return;
2731 }
2732 }
2733
2734 // Receiver type not found in profile data. Select an empty slot.
2735
2736 // Note that this is less efficient than it should be because it
2737 // always does a write to the receiver part of the
2738 // VirtualCallData rather than just the first time.
2739 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2740 ciKlass* receiver = vc_data->receiver(i);
2741 if (receiver == NULL) {
2742 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2743 metadata2reg(known_klass->constant_encoding(), tmp1);
2744 __ z_stg(tmp1, recv_addr);
2745 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2746 __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1);
2747 return;
2748 }
2749 }
2750 } else {
2751 __ load_klass(recv, recv);
2752 NearLabel update_done;
2753 type_profile_helper(mdo, md, data, recv, tmp1, &update_done);
2754 // Receiver did not match any saved receiver and there is no empty row for it.
2755 // Increment total counter to indicate polymorphic case.
2756 __ add2mem_64(counter_addr, DataLayout::counter_increment, tmp1);
2757 __ bind(update_done);
2758 }
2759 } else {
2760 // static call
2761 __ add2mem_64(counter_addr, DataLayout::counter_increment, tmp1);
2762 }
2763 }
2764
2765 void LIR_Assembler::align_backward_branch_target() {
2766 __ align(OptoLoopAlignment);
2767 }
2768
2769 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2770 ShouldNotCallThis(); // There are no delay slots on ZARCH_64.
2771 }
2772
2773 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
2774 assert(left->is_register(), "can only handle registers");
2775
2776 if (left->is_single_cpu()) {
2777 __ z_lcr(dest->as_register(), left->as_register());
2778 } else if (left->is_single_fpu()) {
2779 __ z_lcebr(dest->as_float_reg(), left->as_float_reg());
2780 } else if (left->is_double_fpu()) {
2781 __ z_lcdbr(dest->as_double_reg(), left->as_double_reg());
2782 } else {
2783 assert(left->is_double_cpu(), "Must be a long");
2784 __ z_lcgr(dest->as_register_lo(), left->as_register_lo());
2785 }
2786 }
2787
2788 void LIR_Assembler::fxch(int i) {
2789 ShouldNotCallThis(); // x86 only
2790 }
2791
2792 void LIR_Assembler::fld(int i) {
2793 ShouldNotCallThis(); // x86 only
2794 }
2795
2796 void LIR_Assembler::ffree(int i) {
2797 ShouldNotCallThis(); // x86 only
2798 }
2799
2800 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2801 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2802 assert(!tmp->is_valid(), "don't need temporary");
2803 emit_call_c(dest);
2804 CHECK_BAILOUT();
2805 if (info != NULL) {
2806 add_call_info_here(info);
2807 }
2808 }
2809
2810 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2811 ShouldNotCallThis(); // not needed on ZARCH_64
2812 }
2813
2814 void LIR_Assembler::membar() {
2815 __ z_fence();
2816 }
2817
2818 void LIR_Assembler::membar_acquire() {
2819 __ z_acquire();
2820 }
2821
2822 void LIR_Assembler::membar_release() {
2823 __ z_release();
2824 }
2825
2826 void LIR_Assembler::membar_loadload() {
2827 __ z_acquire();
2828 }
2829
2830 void LIR_Assembler::membar_storestore() {
2831 __ z_release();
2832 }
2833
2834 void LIR_Assembler::membar_loadstore() {
2835 __ z_acquire();
2836 }
2837
2838 void LIR_Assembler::membar_storeload() {
2839 __ z_fence();
2840 }
2841
2842 void LIR_Assembler::on_spin_wait() {
2843 Unimplemented();
2844 }
2845
2846 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
2847 LIR_Address* addr = addr_opr->as_address_ptr();
2848 assert(addr->scale() == LIR_Address::times_1, "scaling unsupported");
2849 __ load_address(dest->as_pointer_register(), as_Address(addr));
2850 }
2851
2852 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2853 ShouldNotCallThis(); // unused
2854 }
2855
2856 #ifdef ASSERT
2857 // Emit run-time assertion.
2858 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2859 Unimplemented();
2860 }
2861 #endif
2862
2863 void LIR_Assembler::peephole(LIR_List*) {
2864 // Do nothing for now.
2865 }
2866
2867 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2868 assert(code == lir_xadd, "lir_xchg not supported");
2869 Address src_addr = as_Address(src->as_address_ptr());
2870 Register base = src_addr.base();
2871 intptr_t disp = src_addr.disp();
2872 if (src_addr.index()->is_valid()) {
2873 // LAA and LAAG do not support index register.
2874 __ load_address(Z_R1_scratch, src_addr);
2875 base = Z_R1_scratch;
2876 disp = 0;
2877 }
2878 if (data->type() == T_INT) {
2879 __ z_laa(dest->as_register(), data->as_register(), disp, base);
2880 } else if (data->type() == T_LONG) {
2881 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
2882 __ z_laag(dest->as_register_lo(), data->as_register_lo(), disp, base);
2883 } else {
2884 ShouldNotReachHere();
2885 }
2886 }
2887
2888 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2889 Register obj = op->obj()->as_register();
2890 Register tmp1 = op->tmp()->as_pointer_register();
2891 Register tmp2 = Z_R1_scratch;
2892 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2893 ciKlass* exact_klass = op->exact_klass();
2894 intptr_t current_klass = op->current_klass();
2895 bool not_null = op->not_null();
2896 bool no_conflict = op->no_conflict();
2897
2898 Label update, next, none, null_seen, init_klass;
2899
2900 bool do_null = !not_null;
2901 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2902 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2903
2904 assert(do_null || do_update, "why are we here?");
2905 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2906
2907 __ verify_oop(obj);
2908
2909 if (do_null || tmp1 != obj DEBUG_ONLY(|| true)) {
2910 __ z_ltgr(tmp1, obj);
2911 }
2912 if (do_null) {
2913 __ z_brnz(update);
2914 if (!TypeEntries::was_null_seen(current_klass)) {
2915 __ z_lg(tmp1, mdo_addr);
2916 __ z_oill(tmp1, TypeEntries::null_seen);
2917 __ z_stg(tmp1, mdo_addr);
2918 }
2919 if (do_update) {
2920 __ z_bru(next);
2921 }
2922 } else {
2923 __ asm_assert_ne("unexpect null obj", __LINE__);
2924 }
2925
2926 __ bind(update);
2927
2928 if (do_update) {
2929 #ifdef ASSERT
2930 if (exact_klass != NULL) {
2931 __ load_klass(tmp1, tmp1);
2932 metadata2reg(exact_klass->constant_encoding(), tmp2);
2933 __ z_cgr(tmp1, tmp2);
2934 __ asm_assert_eq("exact klass and actual klass differ", __LINE__);
2935 }
2936 #endif
2937
2938 Label do_update;
2939 __ z_lg(tmp2, mdo_addr);
2940
2941 if (!no_conflict) {
2942 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
2943 if (exact_klass != NULL) {
2944 metadata2reg(exact_klass->constant_encoding(), tmp1);
2945 } else {
2946 __ load_klass(tmp1, tmp1);
2947 }
2948
2949 // Klass seen before: nothing to do (regardless of unknown bit).
2950 __ z_lgr(Z_R0_scratch, tmp2);
2951 assert(Immediate::is_uimm(~TypeEntries::type_klass_mask, 16), "or change following instruction");
2952 __ z_nill(Z_R0_scratch, TypeEntries::type_klass_mask & 0xFFFF);
2953 __ compareU64_and_branch(Z_R0_scratch, tmp1, Assembler::bcondEqual, next);
2954
2955 // Already unknown: Nothing to do anymore.
2956 __ z_tmll(tmp2, TypeEntries::type_unknown);
2957 __ z_brc(Assembler::bcondAllOne, next);
2958
2959 if (TypeEntries::is_type_none(current_klass)) {
2960 __ z_lgr(Z_R0_scratch, tmp2);
2961 assert(Immediate::is_uimm(~TypeEntries::type_mask, 16), "or change following instruction");
2962 __ z_nill(Z_R0_scratch, TypeEntries::type_mask & 0xFFFF);
2963 __ compareU64_and_branch(Z_R0_scratch, (intptr_t)0, Assembler::bcondEqual, init_klass);
2964 }
2965 } else {
2966 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2967 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2968
2969 // Already unknown: Nothing to do anymore.
2970 __ z_tmll(tmp2, TypeEntries::type_unknown);
2971 __ z_brc(Assembler::bcondAllOne, next);
2972 }
2973
2974 // Different than before. Cannot keep accurate profile.
2975 __ z_oill(tmp2, TypeEntries::type_unknown);
2976 __ z_bru(do_update);
2977 } else {
2978 // There's a single possible klass at this profile point.
2979 assert(exact_klass != NULL, "should be");
2980 if (TypeEntries::is_type_none(current_klass)) {
2981 metadata2reg(exact_klass->constant_encoding(), tmp1);
2982 __ z_lgr(Z_R0_scratch, tmp2);
2983 assert(Immediate::is_uimm(~TypeEntries::type_klass_mask, 16), "or change following instruction");
2984 __ z_nill(Z_R0_scratch, TypeEntries::type_klass_mask & 0xFFFF);
2985 __ compareU64_and_branch(Z_R0_scratch, tmp1, Assembler::bcondEqual, next);
2986 #ifdef ASSERT
2987 {
2988 Label ok;
2989 __ z_lgr(Z_R0_scratch, tmp2);
2990 assert(Immediate::is_uimm(~TypeEntries::type_mask, 16), "or change following instruction");
2991 __ z_nill(Z_R0_scratch, TypeEntries::type_mask & 0xFFFF);
2992 __ compareU64_and_branch(Z_R0_scratch, (intptr_t)0, Assembler::bcondEqual, ok);
2993 __ stop("unexpected profiling mismatch");
2994 __ bind(ok);
2995 }
2996 #endif
2997
2998 } else {
2999 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3000 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3001
3002 // Already unknown: Nothing to do anymore.
3003 __ z_tmll(tmp2, TypeEntries::type_unknown);
3004 __ z_brc(Assembler::bcondAllOne, next);
3005 __ z_oill(tmp2, TypeEntries::type_unknown);
3006 __ z_bru(do_update);
3007 }
3008 }
3009
3010 __ bind(init_klass);
3011 // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3012 __ z_ogr(tmp2, tmp1);
3013
3014 __ bind(do_update);
3015 __ z_stg(tmp2, mdo_addr);
3016
3017 __ bind(next);
3018 }
3019 }
3020
3021 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3022 assert(op->crc()->is_single_cpu(), "crc must be register");
3023 assert(op->val()->is_single_cpu(), "byte value must be register");
3024 assert(op->result_opr()->is_single_cpu(), "result must be register");
3025 Register crc = op->crc()->as_register();
3026 Register val = op->val()->as_register();
3027 Register res = op->result_opr()->as_register();
3028
3029 assert_different_registers(val, crc, res);
3030
3031 __ load_const_optimized(res, StubRoutines::crc_table_addr());
3032 __ not_(crc, noreg, false); // ~crc
3033 __ update_byte_crc32(crc, val, res);
3034 __ not_(res, crc, false); // ~crc
3035 }
3036
3037 #undef __