1 /*
2 * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_Compilation.hpp"
27 #include "c1/c1_LIRAssembler.hpp"
28 #include "c1/c1_MacroAssembler.hpp"
29 #include "c1/c1_Runtime1.hpp"
30 #include "c1/c1_ValueStack.hpp"
31 #include "ci/ciArrayKlass.hpp"
32 #include "ci/ciInstance.hpp"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/cardTableModRefBS.hpp"
35 #include "gc/shared/collectedHeap.hpp"
36 #include "nativeInst_sparc.hpp"
37 #include "oops/objArrayKlass.hpp"
38 #include "runtime/sharedRuntime.hpp"
39
40 #define __ _masm->
41
42
43 //------------------------------------------------------------
44
45
46 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
47 if (opr->is_constant()) {
48 LIR_Const* constant = opr->as_constant_ptr();
49 switch (constant->type()) {
50 case T_INT: {
51 jint value = constant->as_jint();
52 return Assembler::is_simm13(value);
53 }
54
55 default:
56 return false;
57 }
58 }
59 return false;
60 }
61
62
63 bool LIR_Assembler::is_single_instruction(LIR_Op* op) {
64 switch (op->code()) {
65 case lir_null_check:
66 return true;
67
68
69 case lir_add:
70 case lir_ushr:
71 case lir_shr:
72 case lir_shl:
73 // integer shifts and adds are always one instruction
74 return op->result_opr()->is_single_cpu();
75
76
77 case lir_move: {
78 LIR_Op1* op1 = op->as_Op1();
79 LIR_Opr src = op1->in_opr();
80 LIR_Opr dst = op1->result_opr();
81
82 if (src == dst) {
83 NEEDS_CLEANUP;
84 // this works around a problem where moves with the same src and dst
85 // end up in the delay slot and then the assembler swallows the mov
86 // since it has no effect and then it complains because the delay slot
87 // is empty. returning false stops the optimizer from putting this in
88 // the delay slot
89 return false;
90 }
91
92 // don't put moves involving oops into the delay slot since the VerifyOops code
93 // will make it much larger than a single instruction.
94 if (VerifyOops) {
95 return false;
96 }
97
98 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
99 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
100 return false;
101 }
102
103 if (UseCompressedOops) {
104 if (dst->is_address() && !dst->is_stack() && (dst->type() == T_OBJECT || dst->type() == T_ARRAY)) return false;
105 if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false;
106 }
107
108 if (UseCompressedClassPointers) {
109 if (src->is_address() && !src->is_stack() && src->type() == T_ADDRESS &&
110 src->as_address_ptr()->disp() == oopDesc::klass_offset_in_bytes()) return false;
111 }
112
113 if (dst->is_register()) {
114 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
115 return !PatchALot;
116 } else if (src->is_single_stack()) {
117 return true;
118 }
119 }
120
121 if (src->is_register()) {
122 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {
123 return !PatchALot;
124 } else if (dst->is_single_stack()) {
125 return true;
126 }
127 }
128
129 if (dst->is_register() &&
130 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
131 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
132 return true;
133 }
134
135 return false;
136 }
137
138 default:
139 return false;
140 }
141 ShouldNotReachHere();
142 }
143
144
145 LIR_Opr LIR_Assembler::receiverOpr() {
146 return FrameMap::O0_oop_opr;
147 }
148
149
150 LIR_Opr LIR_Assembler::osrBufferPointer() {
151 return FrameMap::I0_opr;
152 }
153
154
155 int LIR_Assembler::initial_frame_size_in_bytes() const {
156 return in_bytes(frame_map()->framesize_in_bytes());
157 }
158
159
160 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
161 // we fetch the class of the receiver (O0) and compare it with the cached class.
162 // If they do not match we jump to slow case.
163 int LIR_Assembler::check_icache() {
164 int offset = __ offset();
165 __ inline_cache_check(O0, G5_inline_cache_reg);
166 return offset;
167 }
168
169
170 void LIR_Assembler::osr_entry() {
171 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
172 //
173 // 1. Create a new compiled activation.
174 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
175 // at the osr_bci; it is not initialized.
176 // 3. Jump to the continuation address in compiled code to resume execution.
177
178 // OSR entry point
179 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
180 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
181 ValueStack* entry_state = osr_entry->end()->state();
182 int number_of_locks = entry_state->locks_size();
183
184 // Create a frame for the compiled activation.
185 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
186
187 // OSR buffer is
188 //
189 // locals[nlocals-1..0]
190 // monitors[number_of_locks-1..0]
191 //
192 // locals is a direct copy of the interpreter frame so in the osr buffer
193 // so first slot in the local array is the last local from the interpreter
194 // and last slot is local[0] (receiver) from the interpreter
195 //
196 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
197 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
198 // in the interpreter frame (the method lock if a sync method)
199
200 // Initialize monitors in the compiled activation.
201 // I0: pointer to osr buffer
202 //
203 // All other registers are dead at this point and the locals will be
204 // copied into place by code emitted in the IR.
205
206 Register OSR_buf = osrBufferPointer()->as_register();
207 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
208 int monitor_offset = BytesPerWord * method()->max_locals() +
209 (2 * BytesPerWord) * (number_of_locks - 1);
210 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
211 // the OSR buffer using 2 word entries: first the lock and then
212 // the oop.
213 for (int i = 0; i < number_of_locks; i++) {
214 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
215 #ifdef ASSERT
216 // verify the interpreter's monitor has a non-null object
217 {
218 Label L;
219 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
220 __ cmp_and_br_short(O7, G0, Assembler::notEqual, Assembler::pt, L);
221 __ stop("locked object is NULL");
222 __ bind(L);
223 }
224 #endif // ASSERT
225 // Copy the lock field into the compiled activation.
226 __ ld_ptr(OSR_buf, slot_offset + 0, O7);
227 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));
228 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
229 __ st_ptr(O7, frame_map()->address_for_monitor_object(i));
230 }
231 }
232 }
233
234
235 // --------------------------------------------------------------------------------------------
236
237 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {
238 if (!GenerateSynchronizationCode) return;
239
240 Register obj_reg = obj_opr->as_register();
241 Register lock_reg = lock_opr->as_register();
242
243 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
244 Register reg = mon_addr.base();
245 int offset = mon_addr.disp();
246 // compute pointer to BasicLock
247 if (mon_addr.is_simm13()) {
248 __ add(reg, offset, lock_reg);
249 }
250 else {
251 __ set(offset, lock_reg);
252 __ add(reg, lock_reg, lock_reg);
253 }
254 // unlock object
255 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);
256 // _slow_case_stubs->append(slow_case);
257 // temporary fix: must be created after exceptionhandler, therefore as call stub
258 _slow_case_stubs->append(slow_case);
259 if (UseFastLocking) {
260 // try inlined fast unlocking first, revert to slow locking if it fails
261 // note: lock_reg points to the displaced header since the displaced header offset is 0!
262 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
263 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
264 } else {
265 // always do slow unlocking
266 // note: the slow unlocking code could be inlined here, however if we use
267 // slow unlocking, speed doesn't matter anyway and this solution is
268 // simpler and requires less duplicated code - additionally, the
269 // slow unlocking code is the same in either case which simplifies
270 // debugging
271 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());
272 __ delayed()->nop();
273 }
274 // done
275 __ bind(*slow_case->continuation());
276 }
277
278
279 int LIR_Assembler::emit_exception_handler() {
280 // if the last instruction is a call (typically to do a throw which
281 // is coming at the end after block reordering) the return address
282 // must still point into the code area in order to avoid assertion
283 // failures when searching for the corresponding bci => add a nop
284 // (was bug 5/14/1999 - gri)
285 __ nop();
286
287 // generate code for exception handler
288 ciMethod* method = compilation()->method();
289
290 address handler_base = __ start_a_stub(exception_handler_size);
291
292 if (handler_base == NULL) {
293 // not enough space left for the handler
294 bailout("exception handler overflow");
295 return -1;
296 }
297
298 int offset = code_offset();
299
300 __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type);
301 __ delayed()->nop();
302 __ should_not_reach_here();
303 guarantee(code_offset() - offset <= exception_handler_size, "overflow");
304 __ end_a_stub();
305
306 return offset;
307 }
308
309
310 // Emit the code to remove the frame from the stack in the exception
311 // unwind path.
312 int LIR_Assembler::emit_unwind_handler() {
313 #ifndef PRODUCT
314 if (CommentedAssembly) {
315 _masm->block_comment("Unwind handler");
316 }
317 #endif
318
319 int offset = code_offset();
320
321 // Fetch the exception from TLS and clear out exception related thread state
322 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0);
323 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
324 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset()));
325
326 __ bind(_unwind_handler_entry);
327 __ verify_not_null_oop(O0);
328 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
329 __ mov(O0, I0); // Preserve the exception
330 }
331
332 // Preform needed unlocking
333 MonitorExitStub* stub = NULL;
334 if (method()->is_synchronized()) {
335 monitor_address(0, FrameMap::I1_opr);
336 stub = new MonitorExitStub(FrameMap::I1_opr, true, 0);
337 __ unlock_object(I3, I2, I1, *stub->entry());
338 __ bind(*stub->continuation());
339 }
340
341 if (compilation()->env()->dtrace_method_probes()) {
342 __ mov(G2_thread, O0);
343 __ save_thread(I1); // need to preserve thread in G2 across
344 // runtime call
345 metadata2reg(method()->constant_encoding(), O1);
346 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type);
347 __ delayed()->nop();
348 __ restore_thread(I1);
349 }
350
351 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
352 __ mov(I0, O0); // Restore the exception
353 }
354
355 // dispatch to the unwind logic
356 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
357 __ delayed()->nop();
358
359 // Emit the slow path assembly
360 if (stub != NULL) {
361 stub->emit_code(this);
362 }
363
364 return offset;
365 }
366
367
368 int LIR_Assembler::emit_deopt_handler() {
369 // if the last instruction is a call (typically to do a throw which
370 // is coming at the end after block reordering) the return address
371 // must still point into the code area in order to avoid assertion
372 // failures when searching for the corresponding bci => add a nop
373 // (was bug 5/14/1999 - gri)
374 __ nop();
375
376 // generate code for deopt handler
377 ciMethod* method = compilation()->method();
378 address handler_base = __ start_a_stub(deopt_handler_size);
379 if (handler_base == NULL) {
380 // not enough space left for the handler
381 bailout("deopt handler overflow");
382 return -1;
383 }
384
385 int offset = code_offset();
386 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
387 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp
388 __ delayed()->nop();
389 guarantee(code_offset() - offset <= deopt_handler_size, "overflow");
390 __ end_a_stub();
391
392 return offset;
393 }
394
395
396 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
397 if (o == NULL) {
398 __ set(NULL_WORD, reg);
399 } else {
400 int oop_index = __ oop_recorder()->find_index(o);
401 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(o)), "should be real oop");
402 RelocationHolder rspec = oop_Relocation::spec(oop_index);
403 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created
404 }
405 }
406
407
408 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
409 // Allocate a new index in table to hold the object once it's been patched
410 int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
411 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
412
413 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));
414 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
415 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
416 // NULL will be dynamically patched later and the patched value may be large. We must
417 // therefore generate the sethi/add as a placeholders
418 __ patchable_set(addrlit, reg);
419
420 patching_epilog(patch, lir_patch_normal, reg, info);
421 }
422
423
424 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
425 __ set_metadata_constant(o, reg);
426 }
427
428 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
429 // Allocate a new index in table to hold the klass once it's been patched
430 int index = __ oop_recorder()->allocate_metadata_index(NULL);
431 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
432 AddressLiteral addrlit(NULL, metadata_Relocation::spec(index));
433 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
434 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
435 // NULL will be dynamically patched later and the patched value may be large. We must
436 // therefore generate the sethi/add as a placeholders
437 __ patchable_set(addrlit, reg);
438
439 patching_epilog(patch, lir_patch_normal, reg, info);
440 }
441
442 void LIR_Assembler::emit_op3(LIR_Op3* op) {
443 Register Rdividend = op->in_opr1()->as_register();
444 Register Rdivisor = noreg;
445 Register Rscratch = op->in_opr3()->as_register();
446 Register Rresult = op->result_opr()->as_register();
447 int divisor = -1;
448
449 if (op->in_opr2()->is_register()) {
450 Rdivisor = op->in_opr2()->as_register();
451 } else {
452 divisor = op->in_opr2()->as_constant_ptr()->as_jint();
453 assert(Assembler::is_simm13(divisor), "can only handle simm13");
454 }
455
456 assert(Rdividend != Rscratch, "");
457 assert(Rdivisor != Rscratch, "");
458 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
459
460 if (Rdivisor == noreg && is_power_of_2(divisor)) {
461 // convert division by a power of two into some shifts and logical operations
462 if (op->code() == lir_idiv) {
463 if (divisor == 2) {
464 __ srl(Rdividend, 31, Rscratch);
465 } else {
466 __ sra(Rdividend, 31, Rscratch);
467 __ and3(Rscratch, divisor - 1, Rscratch);
468 }
469 __ add(Rdividend, Rscratch, Rscratch);
470 __ sra(Rscratch, log2_intptr(divisor), Rresult);
471 return;
472 } else {
473 if (divisor == 2) {
474 __ srl(Rdividend, 31, Rscratch);
475 } else {
476 __ sra(Rdividend, 31, Rscratch);
477 __ and3(Rscratch, divisor - 1,Rscratch);
478 }
479 __ add(Rdividend, Rscratch, Rscratch);
480 __ andn(Rscratch, divisor - 1,Rscratch);
481 __ sub(Rdividend, Rscratch, Rresult);
482 return;
483 }
484 }
485
486 __ sra(Rdividend, 31, Rscratch);
487 __ wry(Rscratch);
488
489 add_debug_info_for_div0_here(op->info());
490
491 if (Rdivisor != noreg) {
492 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch));
493 } else {
494 assert(Assembler::is_simm13(divisor), "can only handle simm13");
495 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch));
496 }
497
498 Label skip;
499 __ br(Assembler::overflowSet, true, Assembler::pn, skip);
500 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch));
501 __ bind(skip);
502
503 if (op->code() == lir_irem) {
504 if (Rdivisor != noreg) {
505 __ smul(Rscratch, Rdivisor, Rscratch);
506 } else {
507 __ smul(Rscratch, divisor, Rscratch);
508 }
509 __ sub(Rdividend, Rscratch, Rresult);
510 }
511 }
512
513
514 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
515 #ifdef ASSERT
516 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
517 if (op->block() != NULL) _branch_target_blocks.append(op->block());
518 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
519 #endif
520 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
521
522 if (op->cond() == lir_cond_always) {
523 __ br(Assembler::always, false, Assembler::pt, *(op->label()));
524 } else if (op->code() == lir_cond_float_branch) {
525 assert(op->ublock() != NULL, "must have unordered successor");
526 bool is_unordered = (op->ublock() == op->block());
527 Assembler::Condition acond;
528 switch (op->cond()) {
529 case lir_cond_equal: acond = Assembler::f_equal; break;
530 case lir_cond_notEqual: acond = Assembler::f_notEqual; break;
531 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break;
532 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break;
533 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break;
534 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break;
535 default : ShouldNotReachHere();
536 }
537 __ fb( acond, false, Assembler::pn, *(op->label()));
538 } else {
539 assert (op->code() == lir_branch, "just checking");
540
541 Assembler::Condition acond;
542 switch (op->cond()) {
543 case lir_cond_equal: acond = Assembler::equal; break;
544 case lir_cond_notEqual: acond = Assembler::notEqual; break;
545 case lir_cond_less: acond = Assembler::less; break;
546 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
547 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
548 case lir_cond_greater: acond = Assembler::greater; break;
549 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
550 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
551 default: ShouldNotReachHere();
552 };
553
554 // sparc has different condition codes for testing 32-bit
555 // vs. 64-bit values. We could always test xcc is we could
556 // guarantee that 32-bit loads always sign extended but that isn't
557 // true and since sign extension isn't free, it would impose a
558 // slight cost.
559 #ifdef _LP64
560 if (op->type() == T_INT) {
561 __ br(acond, false, Assembler::pn, *(op->label()));
562 } else
563 #endif
564 __ brx(acond, false, Assembler::pn, *(op->label()));
565 }
566 // The peephole pass fills the delay slot
567 }
568
569
570 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
571 Bytecodes::Code code = op->bytecode();
572 LIR_Opr dst = op->result_opr();
573
574 switch(code) {
575 case Bytecodes::_i2l: {
576 Register rlo = dst->as_register_lo();
577 Register rhi = dst->as_register_hi();
578 Register rval = op->in_opr()->as_register();
579 #ifdef _LP64
580 __ sra(rval, 0, rlo);
581 #else
582 __ mov(rval, rlo);
583 __ sra(rval, BitsPerInt-1, rhi);
584 #endif
585 break;
586 }
587 case Bytecodes::_i2d:
588 case Bytecodes::_i2f: {
589 bool is_double = (code == Bytecodes::_i2d);
590 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
591 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
592 FloatRegister rsrc = op->in_opr()->as_float_reg();
593 if (rsrc != rdst) {
594 __ fmov(FloatRegisterImpl::S, rsrc, rdst);
595 }
596 __ fitof(w, rdst, rdst);
597 break;
598 }
599 case Bytecodes::_f2i:{
600 FloatRegister rsrc = op->in_opr()->as_float_reg();
601 Address addr = frame_map()->address_for_slot(dst->single_stack_ix());
602 Label L;
603 // result must be 0 if value is NaN; test by comparing value to itself
604 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);
605 __ fb(Assembler::f_unordered, true, Assembler::pn, L);
606 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN
607 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);
608 // move integer result from float register to int register
609 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());
610 __ bind (L);
611 break;
612 }
613 case Bytecodes::_l2i: {
614 Register rlo = op->in_opr()->as_register_lo();
615 Register rhi = op->in_opr()->as_register_hi();
616 Register rdst = dst->as_register();
617 #ifdef _LP64
618 __ sra(rlo, 0, rdst);
619 #else
620 __ mov(rlo, rdst);
621 #endif
622 break;
623 }
624 case Bytecodes::_d2f:
625 case Bytecodes::_f2d: {
626 bool is_double = (code == Bytecodes::_f2d);
627 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");
628 LIR_Opr val = op->in_opr();
629 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
630 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
631 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;
632 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
633 __ ftof(vw, dw, rval, rdst);
634 break;
635 }
636 case Bytecodes::_i2s:
637 case Bytecodes::_i2b: {
638 Register rval = op->in_opr()->as_register();
639 Register rdst = dst->as_register();
640 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);
641 __ sll (rval, shift, rdst);
642 __ sra (rdst, shift, rdst);
643 break;
644 }
645 case Bytecodes::_i2c: {
646 Register rval = op->in_opr()->as_register();
647 Register rdst = dst->as_register();
648 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
649 __ sll (rval, shift, rdst);
650 __ srl (rdst, shift, rdst);
651 break;
652 }
653
654 default: ShouldNotReachHere();
655 }
656 }
657
658
659 void LIR_Assembler::align_call(LIR_Code) {
660 // do nothing since all instructions are word aligned on sparc
661 }
662
663
664 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
665 __ call(op->addr(), rtype);
666 // The peephole pass fills the delay slot, add_call_info is done in
667 // LIR_Assembler::emit_delay.
668 }
669
670
671 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
672 __ ic_call(op->addr(), false);
673 // The peephole pass fills the delay slot, add_call_info is done in
674 // LIR_Assembler::emit_delay.
675 }
676
677
678 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
679 add_debug_info_for_null_check_here(op->info());
680 __ load_klass(O0, G3_scratch);
681 if (Assembler::is_simm13(op->vtable_offset())) {
682 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
683 } else {
684 // This will generate 2 instructions
685 __ set(op->vtable_offset(), G5_method);
686 // ld_ptr, set_hi, set
687 __ ld_ptr(G3_scratch, G5_method, G5_method);
688 }
689 __ ld_ptr(G5_method, Method::from_compiled_offset(), G3_scratch);
690 __ callr(G3_scratch, G0);
691 // the peephole pass fills the delay slot
692 }
693
694 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
695 int store_offset;
696 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
697 assert(!unaligned, "can't handle this");
698 // for offsets larger than a simm13 we setup the offset in O7
699 __ set(offset, O7);
700 store_offset = store(from_reg, base, O7, type, wide);
701 } else {
702 if (type == T_ARRAY || type == T_OBJECT) {
703 __ verify_oop(from_reg->as_register());
704 }
705 store_offset = code_offset();
706 switch (type) {
707 case T_BOOLEAN: // fall through
708 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;
709 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;
710 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
711 case T_INT : __ stw(from_reg->as_register(), base, offset); break;
712 case T_LONG :
713 #ifdef _LP64
714 if (unaligned || PatchALot) {
715 __ srax(from_reg->as_register_lo(), 32, O7);
716 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
717 __ stw(O7, base, offset + hi_word_offset_in_bytes);
718 } else {
719 __ stx(from_reg->as_register_lo(), base, offset);
720 }
721 #else
722 assert(Assembler::is_simm13(offset + 4), "must be");
723 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
724 __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes);
725 #endif
726 break;
727 case T_ADDRESS:
728 case T_METADATA:
729 __ st_ptr(from_reg->as_register(), base, offset);
730 break;
731 case T_ARRAY : // fall through
732 case T_OBJECT:
733 {
734 if (UseCompressedOops && !wide) {
735 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
736 store_offset = code_offset();
737 __ stw(G3_scratch, base, offset);
738 } else {
739 __ st_ptr(from_reg->as_register(), base, offset);
740 }
741 break;
742 }
743
744 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
745 case T_DOUBLE:
746 {
747 FloatRegister reg = from_reg->as_double_reg();
748 // split unaligned stores
749 if (unaligned || PatchALot) {
750 assert(Assembler::is_simm13(offset + 4), "must be");
751 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);
752 __ stf(FloatRegisterImpl::S, reg, base, offset);
753 } else {
754 __ stf(FloatRegisterImpl::D, reg, base, offset);
755 }
756 break;
757 }
758 default : ShouldNotReachHere();
759 }
760 }
761 return store_offset;
762 }
763
764
765 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
766 if (type == T_ARRAY || type == T_OBJECT) {
767 __ verify_oop(from_reg->as_register());
768 }
769 int store_offset = code_offset();
770 switch (type) {
771 case T_BOOLEAN: // fall through
772 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;
773 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;
774 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
775 case T_INT : __ stw(from_reg->as_register(), base, disp); break;
776 case T_LONG :
777 #ifdef _LP64
778 __ stx(from_reg->as_register_lo(), base, disp);
779 #else
780 assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match");
781 __ std(from_reg->as_register_hi(), base, disp);
782 #endif
783 break;
784 case T_ADDRESS:
785 __ st_ptr(from_reg->as_register(), base, disp);
786 break;
787 case T_ARRAY : // fall through
788 case T_OBJECT:
789 {
790 if (UseCompressedOops && !wide) {
791 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
792 store_offset = code_offset();
793 __ stw(G3_scratch, base, disp);
794 } else {
795 __ st_ptr(from_reg->as_register(), base, disp);
796 }
797 break;
798 }
799 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
800 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
801 default : ShouldNotReachHere();
802 }
803 return store_offset;
804 }
805
806
807 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
808 int load_offset;
809 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
810 assert(base != O7, "destroying register");
811 assert(!unaligned, "can't handle this");
812 // for offsets larger than a simm13 we setup the offset in O7
813 __ set(offset, O7);
814 load_offset = load(base, O7, to_reg, type, wide);
815 } else {
816 load_offset = code_offset();
817 switch(type) {
818 case T_BOOLEAN: // fall through
819 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
820 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
821 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
822 case T_INT : __ ld(base, offset, to_reg->as_register()); break;
823 case T_LONG :
824 if (!unaligned) {
825 #ifdef _LP64
826 __ ldx(base, offset, to_reg->as_register_lo());
827 #else
828 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
829 "must be sequential");
830 __ ldd(base, offset, to_reg->as_register_hi());
831 #endif
832 } else {
833 #ifdef _LP64
834 assert(base != to_reg->as_register_lo(), "can't handle this");
835 assert(O7 != to_reg->as_register_lo(), "can't handle this");
836 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
837 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
838 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
839 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
840 #else
841 if (base == to_reg->as_register_lo()) {
842 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
843 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
844 } else {
845 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
846 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
847 }
848 #endif
849 }
850 break;
851 case T_METADATA: __ ld_ptr(base, offset, to_reg->as_register()); break;
852 case T_ADDRESS:
853 #ifdef _LP64
854 if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) {
855 __ lduw(base, offset, to_reg->as_register());
856 __ decode_klass_not_null(to_reg->as_register());
857 } else
858 #endif
859 {
860 __ ld_ptr(base, offset, to_reg->as_register());
861 }
862 break;
863 case T_ARRAY : // fall through
864 case T_OBJECT:
865 {
866 if (UseCompressedOops && !wide) {
867 __ lduw(base, offset, to_reg->as_register());
868 __ decode_heap_oop(to_reg->as_register());
869 } else {
870 __ ld_ptr(base, offset, to_reg->as_register());
871 }
872 break;
873 }
874 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
875 case T_DOUBLE:
876 {
877 FloatRegister reg = to_reg->as_double_reg();
878 // split unaligned loads
879 if (unaligned || PatchALot) {
880 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor());
881 __ ldf(FloatRegisterImpl::S, base, offset, reg);
882 } else {
883 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
884 }
885 break;
886 }
887 default : ShouldNotReachHere();
888 }
889 if (type == T_ARRAY || type == T_OBJECT) {
890 __ verify_oop(to_reg->as_register());
891 }
892 }
893 return load_offset;
894 }
895
896
897 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
898 int load_offset = code_offset();
899 switch(type) {
900 case T_BOOLEAN: // fall through
901 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
902 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
903 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
904 case T_INT : __ ld(base, disp, to_reg->as_register()); break;
905 case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break;
906 case T_ARRAY : // fall through
907 case T_OBJECT:
908 {
909 if (UseCompressedOops && !wide) {
910 __ lduw(base, disp, to_reg->as_register());
911 __ decode_heap_oop(to_reg->as_register());
912 } else {
913 __ ld_ptr(base, disp, to_reg->as_register());
914 }
915 break;
916 }
917 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
918 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
919 case T_LONG :
920 #ifdef _LP64
921 __ ldx(base, disp, to_reg->as_register_lo());
922 #else
923 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
924 "must be sequential");
925 __ ldd(base, disp, to_reg->as_register_hi());
926 #endif
927 break;
928 default : ShouldNotReachHere();
929 }
930 if (type == T_ARRAY || type == T_OBJECT) {
931 __ verify_oop(to_reg->as_register());
932 }
933 return load_offset;
934 }
935
936 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
937 LIR_Const* c = src->as_constant_ptr();
938 switch (c->type()) {
939 case T_INT:
940 case T_FLOAT: {
941 Register src_reg = O7;
942 int value = c->as_jint_bits();
943 if (value == 0) {
944 src_reg = G0;
945 } else {
946 __ set(value, O7);
947 }
948 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
949 __ stw(src_reg, addr.base(), addr.disp());
950 break;
951 }
952 case T_ADDRESS: {
953 Register src_reg = O7;
954 int value = c->as_jint_bits();
955 if (value == 0) {
956 src_reg = G0;
957 } else {
958 __ set(value, O7);
959 }
960 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
961 __ st_ptr(src_reg, addr.base(), addr.disp());
962 break;
963 }
964 case T_OBJECT: {
965 Register src_reg = O7;
966 jobject2reg(c->as_jobject(), src_reg);
967 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
968 __ st_ptr(src_reg, addr.base(), addr.disp());
969 break;
970 }
971 case T_LONG:
972 case T_DOUBLE: {
973 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
974
975 Register tmp = O7;
976 int value_lo = c->as_jint_lo_bits();
977 if (value_lo == 0) {
978 tmp = G0;
979 } else {
980 __ set(value_lo, O7);
981 }
982 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);
983 int value_hi = c->as_jint_hi_bits();
984 if (value_hi == 0) {
985 tmp = G0;
986 } else {
987 __ set(value_hi, O7);
988 }
989 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);
990 break;
991 }
992 default:
993 Unimplemented();
994 }
995 }
996
997
998 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
999 LIR_Const* c = src->as_constant_ptr();
1000 LIR_Address* addr = dest->as_address_ptr();
1001 Register base = addr->base()->as_pointer_register();
1002 int offset = -1;
1003
1004 switch (c->type()) {
1005 case T_INT:
1006 case T_FLOAT:
1007 case T_ADDRESS: {
1008 LIR_Opr tmp = FrameMap::O7_opr;
1009 int value = c->as_jint_bits();
1010 if (value == 0) {
1011 tmp = FrameMap::G0_opr;
1012 } else if (Assembler::is_simm13(value)) {
1013 __ set(value, O7);
1014 }
1015 if (addr->index()->is_valid()) {
1016 assert(addr->disp() == 0, "must be zero");
1017 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1018 } else {
1019 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1020 offset = store(tmp, base, addr->disp(), type, wide, false);
1021 }
1022 break;
1023 }
1024 case T_LONG:
1025 case T_DOUBLE: {
1026 assert(!addr->index()->is_valid(), "can't handle reg reg address here");
1027 assert(Assembler::is_simm13(addr->disp()) &&
1028 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
1029
1030 LIR_Opr tmp = FrameMap::O7_opr;
1031 int value_lo = c->as_jint_lo_bits();
1032 if (value_lo == 0) {
1033 tmp = FrameMap::G0_opr;
1034 } else {
1035 __ set(value_lo, O7);
1036 }
1037 offset = store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT, wide, false);
1038 int value_hi = c->as_jint_hi_bits();
1039 if (value_hi == 0) {
1040 tmp = FrameMap::G0_opr;
1041 } else {
1042 __ set(value_hi, O7);
1043 }
1044 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT, wide, false);
1045 break;
1046 }
1047 case T_OBJECT: {
1048 jobject obj = c->as_jobject();
1049 LIR_Opr tmp;
1050 if (obj == NULL) {
1051 tmp = FrameMap::G0_opr;
1052 } else {
1053 tmp = FrameMap::O7_opr;
1054 jobject2reg(c->as_jobject(), O7);
1055 }
1056 // handle either reg+reg or reg+disp address
1057 if (addr->index()->is_valid()) {
1058 assert(addr->disp() == 0, "must be zero");
1059 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1060 } else {
1061 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1062 offset = store(tmp, base, addr->disp(), type, wide, false);
1063 }
1064
1065 break;
1066 }
1067 default:
1068 Unimplemented();
1069 }
1070 if (info != NULL) {
1071 assert(offset != -1, "offset should've been set");
1072 add_debug_info_for_null_check(offset, info);
1073 }
1074 }
1075
1076
1077 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
1078 LIR_Const* c = src->as_constant_ptr();
1079 LIR_Opr to_reg = dest;
1080
1081 switch (c->type()) {
1082 case T_INT:
1083 case T_ADDRESS:
1084 {
1085 jint con = c->as_jint();
1086 if (to_reg->is_single_cpu()) {
1087 assert(patch_code == lir_patch_none, "no patching handled here");
1088 __ set(con, to_reg->as_register());
1089 } else {
1090 ShouldNotReachHere();
1091 assert(to_reg->is_single_fpu(), "wrong register kind");
1092
1093 __ set(con, O7);
1094 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS);
1095 __ st(O7, temp_slot);
1096 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
1097 }
1098 }
1099 break;
1100
1101 case T_LONG:
1102 {
1103 jlong con = c->as_jlong();
1104
1105 if (to_reg->is_double_cpu()) {
1106 #ifdef _LP64
1107 __ set(con, to_reg->as_register_lo());
1108 #else
1109 __ set(low(con), to_reg->as_register_lo());
1110 __ set(high(con), to_reg->as_register_hi());
1111 #endif
1112 #ifdef _LP64
1113 } else if (to_reg->is_single_cpu()) {
1114 __ set(con, to_reg->as_register());
1115 #endif
1116 } else {
1117 ShouldNotReachHere();
1118 assert(to_reg->is_double_fpu(), "wrong register kind");
1119 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS);
1120 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
1121 __ set(low(con), O7);
1122 __ st(O7, temp_slot_lo);
1123 __ set(high(con), O7);
1124 __ st(O7, temp_slot_hi);
1125 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
1126 }
1127 }
1128 break;
1129
1130 case T_OBJECT:
1131 {
1132 if (patch_code == lir_patch_none) {
1133 jobject2reg(c->as_jobject(), to_reg->as_register());
1134 } else {
1135 jobject2reg_with_patching(to_reg->as_register(), info);
1136 }
1137 }
1138 break;
1139
1140 case T_METADATA:
1141 {
1142 if (patch_code == lir_patch_none) {
1143 metadata2reg(c->as_metadata(), to_reg->as_register());
1144 } else {
1145 klass2reg_with_patching(to_reg->as_register(), info);
1146 }
1147 }
1148 break;
1149
1150 case T_FLOAT:
1151 {
1152 address const_addr = __ float_constant(c->as_jfloat());
1153 if (const_addr == NULL) {
1154 bailout("const section overflow");
1155 break;
1156 }
1157 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1158 AddressLiteral const_addrlit(const_addr, rspec);
1159 if (to_reg->is_single_fpu()) {
1160 __ patchable_sethi(const_addrlit, O7);
1161 __ relocate(rspec);
1162 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
1163
1164 } else {
1165 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1166
1167 __ set(const_addrlit, O7);
1168 __ ld(O7, 0, to_reg->as_register());
1169 }
1170 }
1171 break;
1172
1173 case T_DOUBLE:
1174 {
1175 address const_addr = __ double_constant(c->as_jdouble());
1176 if (const_addr == NULL) {
1177 bailout("const section overflow");
1178 break;
1179 }
1180 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1181
1182 if (to_reg->is_double_fpu()) {
1183 AddressLiteral const_addrlit(const_addr, rspec);
1184 __ patchable_sethi(const_addrlit, O7);
1185 __ relocate(rspec);
1186 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1187 } else {
1188 assert(to_reg->is_double_cpu(), "Must be a long register.");
1189 #ifdef _LP64
1190 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
1191 #else
1192 __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo());
1193 __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi());
1194 #endif
1195 }
1196
1197 }
1198 break;
1199
1200 default:
1201 ShouldNotReachHere();
1202 }
1203 }
1204
1205 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1206 Register reg = addr->base()->as_pointer_register();
1207 LIR_Opr index = addr->index();
1208 if (index->is_illegal()) {
1209 return Address(reg, addr->disp());
1210 } else {
1211 assert (addr->disp() == 0, "unsupported address mode");
1212 return Address(reg, index->as_pointer_register());
1213 }
1214 }
1215
1216
1217 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1218 switch (type) {
1219 case T_INT:
1220 case T_FLOAT: {
1221 Register tmp = O7;
1222 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1223 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1224 __ lduw(from.base(), from.disp(), tmp);
1225 __ stw(tmp, to.base(), to.disp());
1226 break;
1227 }
1228 case T_OBJECT: {
1229 Register tmp = O7;
1230 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1231 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1232 __ ld_ptr(from.base(), from.disp(), tmp);
1233 __ st_ptr(tmp, to.base(), to.disp());
1234 break;
1235 }
1236 case T_LONG:
1237 case T_DOUBLE: {
1238 Register tmp = O7;
1239 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1240 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1241 __ lduw(from.base(), from.disp(), tmp);
1242 __ stw(tmp, to.base(), to.disp());
1243 __ lduw(from.base(), from.disp() + 4, tmp);
1244 __ stw(tmp, to.base(), to.disp() + 4);
1245 break;
1246 }
1247
1248 default:
1249 ShouldNotReachHere();
1250 }
1251 }
1252
1253
1254 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1255 Address base = as_Address(addr);
1256 return Address(base.base(), base.disp() + hi_word_offset_in_bytes);
1257 }
1258
1259
1260 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1261 Address base = as_Address(addr);
1262 return Address(base.base(), base.disp() + lo_word_offset_in_bytes);
1263 }
1264
1265
1266 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1267 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) {
1268
1269 assert(type != T_METADATA, "load of metadata ptr not supported");
1270 LIR_Address* addr = src_opr->as_address_ptr();
1271 LIR_Opr to_reg = dest;
1272
1273 Register src = addr->base()->as_pointer_register();
1274 Register disp_reg = noreg;
1275 int disp_value = addr->disp();
1276 bool needs_patching = (patch_code != lir_patch_none);
1277
1278 if (addr->base()->type() == T_OBJECT) {
1279 __ verify_oop(src);
1280 }
1281
1282 PatchingStub* patch = NULL;
1283 if (needs_patching) {
1284 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1285 assert(!to_reg->is_double_cpu() ||
1286 patch_code == lir_patch_none ||
1287 patch_code == lir_patch_normal, "patching doesn't match register");
1288 }
1289
1290 if (addr->index()->is_illegal()) {
1291 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1292 if (needs_patching) {
1293 __ patchable_set(0, O7);
1294 } else {
1295 __ set(disp_value, O7);
1296 }
1297 disp_reg = O7;
1298 }
1299 } else if (unaligned || PatchALot) {
1300 __ add(src, addr->index()->as_register(), O7);
1301 src = O7;
1302 } else {
1303 disp_reg = addr->index()->as_pointer_register();
1304 assert(disp_value == 0, "can't handle 3 operand addresses");
1305 }
1306
1307 // remember the offset of the load. The patching_epilog must be done
1308 // before the call to add_debug_info, otherwise the PcDescs don't get
1309 // entered in increasing order.
1310 int offset = code_offset();
1311
1312 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1313 if (disp_reg == noreg) {
1314 offset = load(src, disp_value, to_reg, type, wide, unaligned);
1315 } else {
1316 assert(!unaligned, "can't handle this");
1317 offset = load(src, disp_reg, to_reg, type, wide);
1318 }
1319
1320 if (patch != NULL) {
1321 patching_epilog(patch, patch_code, src, info);
1322 }
1323 if (info != NULL) add_debug_info_for_null_check(offset, info);
1324 }
1325
1326
1327 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1328 Address addr;
1329 if (src->is_single_word()) {
1330 addr = frame_map()->address_for_slot(src->single_stack_ix());
1331 } else if (src->is_double_word()) {
1332 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1333 }
1334
1335 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1336 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned);
1337 }
1338
1339
1340 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1341 Address addr;
1342 if (dest->is_single_word()) {
1343 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1344 } else if (dest->is_double_word()) {
1345 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1346 }
1347 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1348 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned);
1349 }
1350
1351
1352 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1353 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1354 if (from_reg->is_double_fpu()) {
1355 // double to double moves
1356 assert(to_reg->is_double_fpu(), "should match");
1357 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
1358 } else {
1359 // float to float moves
1360 assert(to_reg->is_single_fpu(), "should match");
1361 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
1362 }
1363 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1364 if (from_reg->is_double_cpu()) {
1365 #ifdef _LP64
1366 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
1367 #else
1368 assert(to_reg->is_double_cpu() &&
1369 from_reg->as_register_hi() != to_reg->as_register_lo() &&
1370 from_reg->as_register_lo() != to_reg->as_register_hi(),
1371 "should both be long and not overlap");
1372 // long to long moves
1373 __ mov(from_reg->as_register_hi(), to_reg->as_register_hi());
1374 __ mov(from_reg->as_register_lo(), to_reg->as_register_lo());
1375 #endif
1376 #ifdef _LP64
1377 } else if (to_reg->is_double_cpu()) {
1378 // int to int moves
1379 __ mov(from_reg->as_register(), to_reg->as_register_lo());
1380 #endif
1381 } else {
1382 // int to int moves
1383 __ mov(from_reg->as_register(), to_reg->as_register());
1384 }
1385 } else {
1386 ShouldNotReachHere();
1387 }
1388 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1389 __ verify_oop(to_reg->as_register());
1390 }
1391 }
1392
1393
1394 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1395 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1396 bool wide, bool unaligned) {
1397 assert(type != T_METADATA, "store of metadata ptr not supported");
1398 LIR_Address* addr = dest->as_address_ptr();
1399
1400 Register src = addr->base()->as_pointer_register();
1401 Register disp_reg = noreg;
1402 int disp_value = addr->disp();
1403 bool needs_patching = (patch_code != lir_patch_none);
1404
1405 if (addr->base()->is_oop_register()) {
1406 __ verify_oop(src);
1407 }
1408
1409 PatchingStub* patch = NULL;
1410 if (needs_patching) {
1411 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1412 assert(!from_reg->is_double_cpu() ||
1413 patch_code == lir_patch_none ||
1414 patch_code == lir_patch_normal, "patching doesn't match register");
1415 }
1416
1417 if (addr->index()->is_illegal()) {
1418 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1419 if (needs_patching) {
1420 __ patchable_set(0, O7);
1421 } else {
1422 __ set(disp_value, O7);
1423 }
1424 disp_reg = O7;
1425 }
1426 } else if (unaligned || PatchALot) {
1427 __ add(src, addr->index()->as_register(), O7);
1428 src = O7;
1429 } else {
1430 disp_reg = addr->index()->as_pointer_register();
1431 assert(disp_value == 0, "can't handle 3 operand addresses");
1432 }
1433
1434 // remember the offset of the store. The patching_epilog must be done
1435 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1436 // entered in increasing order.
1437 int offset;
1438
1439 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1440 if (disp_reg == noreg) {
1441 offset = store(from_reg, src, disp_value, type, wide, unaligned);
1442 } else {
1443 assert(!unaligned, "can't handle this");
1444 offset = store(from_reg, src, disp_reg, type, wide);
1445 }
1446
1447 if (patch != NULL) {
1448 patching_epilog(patch, patch_code, src, info);
1449 }
1450
1451 if (info != NULL) add_debug_info_for_null_check(offset, info);
1452 }
1453
1454
1455 void LIR_Assembler::return_op(LIR_Opr result) {
1456 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1457 __ reserved_stack_check();
1458 }
1459 // the poll may need a register so just pick one that isn't the return register
1460 #if defined(TIERED) && !defined(_LP64)
1461 if (result->type_field() == LIR_OprDesc::long_type) {
1462 // Must move the result to G1
1463 // Must leave proper result in O0,O1 and G1 (TIERED only)
1464 __ sllx(I0, 32, G1); // Shift bits into high G1
1465 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
1466 __ or3 (I1, G1, G1); // OR 64 bits into G1
1467 #ifdef ASSERT
1468 // mangle it so any problems will show up
1469 __ set(0xdeadbeef, I0);
1470 __ set(0xdeadbeef, I1);
1471 #endif
1472 }
1473 #endif // TIERED
1474 __ set((intptr_t)os::get_polling_page(), L0);
1475 __ relocate(relocInfo::poll_return_type);
1476 __ ld_ptr(L0, 0, G0);
1477 __ ret();
1478 __ delayed()->restore();
1479 }
1480
1481
1482 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1483 __ set((intptr_t)os::get_polling_page(), tmp->as_register());
1484 if (info != NULL) {
1485 add_debug_info_for_branch(info);
1486 }
1487 int offset = __ offset();
1488 __ relocate(relocInfo::poll_type);
1489 __ ld_ptr(tmp->as_register(), 0, G0);
1490 return offset;
1491 }
1492
1493
1494 void LIR_Assembler::emit_static_call_stub() {
1495 address call_pc = __ pc();
1496 address stub = __ start_a_stub(call_stub_size);
1497 if (stub == NULL) {
1498 bailout("static call stub overflow");
1499 return;
1500 }
1501
1502 int start = __ offset();
1503 __ relocate(static_stub_Relocation::spec(call_pc));
1504
1505 __ set_metadata(NULL, G5);
1506 // must be set to -1 at code generation time
1507 AddressLiteral addrlit(-1);
1508 __ jump_to(addrlit, G3);
1509 __ delayed()->nop();
1510
1511 assert(__ offset() - start <= call_stub_size, "stub too big");
1512 __ end_a_stub();
1513 }
1514
1515
1516 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1517 if (opr1->is_single_fpu()) {
1518 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg());
1519 } else if (opr1->is_double_fpu()) {
1520 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg());
1521 } else if (opr1->is_single_cpu()) {
1522 if (opr2->is_constant()) {
1523 switch (opr2->as_constant_ptr()->type()) {
1524 case T_INT:
1525 { jint con = opr2->as_constant_ptr()->as_jint();
1526 if (Assembler::is_simm13(con)) {
1527 __ cmp(opr1->as_register(), con);
1528 } else {
1529 __ set(con, O7);
1530 __ cmp(opr1->as_register(), O7);
1531 }
1532 }
1533 break;
1534
1535 case T_OBJECT:
1536 // there are only equal/notequal comparisions on objects
1537 { jobject con = opr2->as_constant_ptr()->as_jobject();
1538 if (con == NULL) {
1539 __ cmp(opr1->as_register(), 0);
1540 } else {
1541 jobject2reg(con, O7);
1542 __ cmp(opr1->as_register(), O7);
1543 }
1544 }
1545 break;
1546
1547 default:
1548 ShouldNotReachHere();
1549 break;
1550 }
1551 } else {
1552 if (opr2->is_address()) {
1553 LIR_Address * addr = opr2->as_address_ptr();
1554 BasicType type = addr->type();
1555 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1556 else __ ld(as_Address(addr), O7);
1557 __ cmp(opr1->as_register(), O7);
1558 } else {
1559 __ cmp(opr1->as_register(), opr2->as_register());
1560 }
1561 }
1562 } else if (opr1->is_double_cpu()) {
1563 Register xlo = opr1->as_register_lo();
1564 Register xhi = opr1->as_register_hi();
1565 if (opr2->is_constant() && opr2->as_jlong() == 0) {
1566 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases");
1567 #ifdef _LP64
1568 __ orcc(xhi, G0, G0);
1569 #else
1570 __ orcc(xhi, xlo, G0);
1571 #endif
1572 } else if (opr2->is_register()) {
1573 Register ylo = opr2->as_register_lo();
1574 Register yhi = opr2->as_register_hi();
1575 #ifdef _LP64
1576 __ cmp(xlo, ylo);
1577 #else
1578 __ subcc(xlo, ylo, xlo);
1579 __ subccc(xhi, yhi, xhi);
1580 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
1581 __ orcc(xhi, xlo, G0);
1582 }
1583 #endif
1584 } else {
1585 ShouldNotReachHere();
1586 }
1587 } else if (opr1->is_address()) {
1588 LIR_Address * addr = opr1->as_address_ptr();
1589 BasicType type = addr->type();
1590 assert (opr2->is_constant(), "Checking");
1591 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1592 else __ ld(as_Address(addr), O7);
1593 __ cmp(O7, opr2->as_constant_ptr()->as_jint());
1594 } else {
1595 ShouldNotReachHere();
1596 }
1597 }
1598
1599
1600 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1601 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1602 bool is_unordered_less = (code == lir_ucmp_fd2i);
1603 if (left->is_single_fpu()) {
1604 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1605 } else if (left->is_double_fpu()) {
1606 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1607 } else {
1608 ShouldNotReachHere();
1609 }
1610 } else if (code == lir_cmp_l2i) {
1611 #ifdef _LP64
1612 __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register());
1613 #else
1614 __ lcmp(left->as_register_hi(), left->as_register_lo(),
1615 right->as_register_hi(), right->as_register_lo(),
1616 dst->as_register());
1617 #endif
1618 } else {
1619 ShouldNotReachHere();
1620 }
1621 }
1622
1623
1624 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1625 Assembler::Condition acond;
1626 switch (condition) {
1627 case lir_cond_equal: acond = Assembler::equal; break;
1628 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1629 case lir_cond_less: acond = Assembler::less; break;
1630 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1631 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
1632 case lir_cond_greater: acond = Assembler::greater; break;
1633 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
1634 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
1635 default: ShouldNotReachHere();
1636 };
1637
1638 if (opr1->is_constant() && opr1->type() == T_INT) {
1639 Register dest = result->as_register();
1640 // load up first part of constant before branch
1641 // and do the rest in the delay slot.
1642 if (!Assembler::is_simm13(opr1->as_jint())) {
1643 __ sethi(opr1->as_jint(), dest);
1644 }
1645 } else if (opr1->is_constant()) {
1646 const2reg(opr1, result, lir_patch_none, NULL);
1647 } else if (opr1->is_register()) {
1648 reg2reg(opr1, result);
1649 } else if (opr1->is_stack()) {
1650 stack2reg(opr1, result, result->type());
1651 } else {
1652 ShouldNotReachHere();
1653 }
1654 Label skip;
1655 #ifdef _LP64
1656 if (type == T_INT) {
1657 __ br(acond, false, Assembler::pt, skip);
1658 } else
1659 #endif
1660 __ brx(acond, false, Assembler::pt, skip); // checks icc on 32bit and xcc on 64bit
1661 if (opr1->is_constant() && opr1->type() == T_INT) {
1662 Register dest = result->as_register();
1663 if (Assembler::is_simm13(opr1->as_jint())) {
1664 __ delayed()->or3(G0, opr1->as_jint(), dest);
1665 } else {
1666 // the sethi has been done above, so just put in the low 10 bits
1667 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
1668 }
1669 } else {
1670 // can't do anything useful in the delay slot
1671 __ delayed()->nop();
1672 }
1673 if (opr2->is_constant()) {
1674 const2reg(opr2, result, lir_patch_none, NULL);
1675 } else if (opr2->is_register()) {
1676 reg2reg(opr2, result);
1677 } else if (opr2->is_stack()) {
1678 stack2reg(opr2, result, result->type());
1679 } else {
1680 ShouldNotReachHere();
1681 }
1682 __ bind(skip);
1683 }
1684
1685
1686 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1687 assert(info == NULL, "unused on this code path");
1688 assert(left->is_register(), "wrong items state");
1689 assert(dest->is_register(), "wrong items state");
1690
1691 if (right->is_register()) {
1692 if (dest->is_float_kind()) {
1693
1694 FloatRegister lreg, rreg, res;
1695 FloatRegisterImpl::Width w;
1696 if (right->is_single_fpu()) {
1697 w = FloatRegisterImpl::S;
1698 lreg = left->as_float_reg();
1699 rreg = right->as_float_reg();
1700 res = dest->as_float_reg();
1701 } else {
1702 w = FloatRegisterImpl::D;
1703 lreg = left->as_double_reg();
1704 rreg = right->as_double_reg();
1705 res = dest->as_double_reg();
1706 }
1707
1708 switch (code) {
1709 case lir_add: __ fadd(w, lreg, rreg, res); break;
1710 case lir_sub: __ fsub(w, lreg, rreg, res); break;
1711 case lir_mul: // fall through
1712 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break;
1713 case lir_div: // fall through
1714 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break;
1715 default: ShouldNotReachHere();
1716 }
1717
1718 } else if (dest->is_double_cpu()) {
1719 #ifdef _LP64
1720 Register dst_lo = dest->as_register_lo();
1721 Register op1_lo = left->as_pointer_register();
1722 Register op2_lo = right->as_pointer_register();
1723
1724 switch (code) {
1725 case lir_add:
1726 __ add(op1_lo, op2_lo, dst_lo);
1727 break;
1728
1729 case lir_sub:
1730 __ sub(op1_lo, op2_lo, dst_lo);
1731 break;
1732
1733 default: ShouldNotReachHere();
1734 }
1735 #else
1736 Register op1_lo = left->as_register_lo();
1737 Register op1_hi = left->as_register_hi();
1738 Register op2_lo = right->as_register_lo();
1739 Register op2_hi = right->as_register_hi();
1740 Register dst_lo = dest->as_register_lo();
1741 Register dst_hi = dest->as_register_hi();
1742
1743 switch (code) {
1744 case lir_add:
1745 __ addcc(op1_lo, op2_lo, dst_lo);
1746 __ addc (op1_hi, op2_hi, dst_hi);
1747 break;
1748
1749 case lir_sub:
1750 __ subcc(op1_lo, op2_lo, dst_lo);
1751 __ subc (op1_hi, op2_hi, dst_hi);
1752 break;
1753
1754 default: ShouldNotReachHere();
1755 }
1756 #endif
1757 } else {
1758 assert (right->is_single_cpu(), "Just Checking");
1759
1760 Register lreg = left->as_register();
1761 Register res = dest->as_register();
1762 Register rreg = right->as_register();
1763 switch (code) {
1764 case lir_add: __ add (lreg, rreg, res); break;
1765 case lir_sub: __ sub (lreg, rreg, res); break;
1766 case lir_mul: __ mulx (lreg, rreg, res); break;
1767 default: ShouldNotReachHere();
1768 }
1769 }
1770 } else {
1771 assert (right->is_constant(), "must be constant");
1772
1773 if (dest->is_single_cpu()) {
1774 Register lreg = left->as_register();
1775 Register res = dest->as_register();
1776 int simm13 = right->as_constant_ptr()->as_jint();
1777
1778 switch (code) {
1779 case lir_add: __ add (lreg, simm13, res); break;
1780 case lir_sub: __ sub (lreg, simm13, res); break;
1781 case lir_mul: __ mulx (lreg, simm13, res); break;
1782 default: ShouldNotReachHere();
1783 }
1784 } else {
1785 Register lreg = left->as_pointer_register();
1786 Register res = dest->as_register_lo();
1787 long con = right->as_constant_ptr()->as_jlong();
1788 assert(Assembler::is_simm13(con), "must be simm13");
1789
1790 switch (code) {
1791 case lir_add: __ add (lreg, (int)con, res); break;
1792 case lir_sub: __ sub (lreg, (int)con, res); break;
1793 case lir_mul: __ mulx (lreg, (int)con, res); break;
1794 default: ShouldNotReachHere();
1795 }
1796 }
1797 }
1798 }
1799
1800
1801 void LIR_Assembler::fpop() {
1802 // do nothing
1803 }
1804
1805
1806 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1807 switch (code) {
1808 case lir_tan: {
1809 assert(thread->is_valid(), "preserve the thread object for performance reasons");
1810 assert(dest->as_double_reg() == F0, "the result will be in f0/f1");
1811 break;
1812 }
1813 case lir_sqrt: {
1814 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1815 FloatRegister src_reg = value->as_double_reg();
1816 FloatRegister dst_reg = dest->as_double_reg();
1817 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg);
1818 break;
1819 }
1820 case lir_abs: {
1821 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1822 FloatRegister src_reg = value->as_double_reg();
1823 FloatRegister dst_reg = dest->as_double_reg();
1824 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg);
1825 break;
1826 }
1827 default: {
1828 ShouldNotReachHere();
1829 break;
1830 }
1831 }
1832 }
1833
1834
1835 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1836 if (right->is_constant()) {
1837 if (dest->is_single_cpu()) {
1838 int simm13 = right->as_constant_ptr()->as_jint();
1839 switch (code) {
1840 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break;
1841 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break;
1842 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break;
1843 default: ShouldNotReachHere();
1844 }
1845 } else {
1846 long c = right->as_constant_ptr()->as_jlong();
1847 assert(c == (int)c && Assembler::is_simm13(c), "out of range");
1848 int simm13 = (int)c;
1849 switch (code) {
1850 case lir_logic_and:
1851 #ifndef _LP64
1852 __ and3 (left->as_register_hi(), 0, dest->as_register_hi());
1853 #endif
1854 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
1855 break;
1856
1857 case lir_logic_or:
1858 #ifndef _LP64
1859 __ or3 (left->as_register_hi(), 0, dest->as_register_hi());
1860 #endif
1861 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
1862 break;
1863
1864 case lir_logic_xor:
1865 #ifndef _LP64
1866 __ xor3 (left->as_register_hi(), 0, dest->as_register_hi());
1867 #endif
1868 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
1869 break;
1870
1871 default: ShouldNotReachHere();
1872 }
1873 }
1874 } else {
1875 assert(right->is_register(), "right should be in register");
1876
1877 if (dest->is_single_cpu()) {
1878 switch (code) {
1879 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
1880 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break;
1881 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
1882 default: ShouldNotReachHere();
1883 }
1884 } else {
1885 #ifdef _LP64
1886 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1887 left->as_register_lo();
1888 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1889 right->as_register_lo();
1890
1891 switch (code) {
1892 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
1893 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break;
1894 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
1895 default: ShouldNotReachHere();
1896 }
1897 #else
1898 switch (code) {
1899 case lir_logic_and:
1900 __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
1901 __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
1902 break;
1903
1904 case lir_logic_or:
1905 __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
1906 __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
1907 break;
1908
1909 case lir_logic_xor:
1910 __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
1911 __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
1912 break;
1913
1914 default: ShouldNotReachHere();
1915 }
1916 #endif
1917 }
1918 }
1919 }
1920
1921
1922 int LIR_Assembler::shift_amount(BasicType t) {
1923 int elem_size = type2aelembytes(t);
1924 switch (elem_size) {
1925 case 1 : return 0;
1926 case 2 : return 1;
1927 case 4 : return 2;
1928 case 8 : return 3;
1929 }
1930 ShouldNotReachHere();
1931 return -1;
1932 }
1933
1934
1935 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1936 assert(exceptionOop->as_register() == Oexception, "should match");
1937 assert(exceptionPC->as_register() == Oissuing_pc, "should match");
1938
1939 info->add_register_oop(exceptionOop);
1940
1941 // reuse the debug info from the safepoint poll for the throw op itself
1942 address pc_for_athrow = __ pc();
1943 int pc_for_athrow_offset = __ offset();
1944 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1945 __ set(pc_for_athrow, Oissuing_pc, rspec);
1946 add_call_info(pc_for_athrow_offset, info); // for exception handler
1947
1948 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
1949 __ delayed()->nop();
1950 }
1951
1952
1953 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1954 assert(exceptionOop->as_register() == Oexception, "should match");
1955
1956 __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry);
1957 __ delayed()->nop();
1958 }
1959
1960 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1961 Register src = op->src()->as_register();
1962 Register dst = op->dst()->as_register();
1963 Register src_pos = op->src_pos()->as_register();
1964 Register dst_pos = op->dst_pos()->as_register();
1965 Register length = op->length()->as_register();
1966 Register tmp = op->tmp()->as_register();
1967 Register tmp2 = O7;
1968
1969 int flags = op->flags();
1970 ciArrayKlass* default_type = op->expected_type();
1971 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1972 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1973
1974 #ifdef _LP64
1975 // higher 32bits must be null
1976 __ sra(dst_pos, 0, dst_pos);
1977 __ sra(src_pos, 0, src_pos);
1978 __ sra(length, 0, length);
1979 #endif
1980
1981 // set up the arraycopy stub information
1982 ArrayCopyStub* stub = op->stub();
1983
1984 // always do stub if no type information is available. it's ok if
1985 // the known type isn't loaded since the code sanity checks
1986 // in debug mode and the type isn't required when we know the exact type
1987 // also check that the type is an array type.
1988 if (op->expected_type() == NULL) {
1989 __ mov(src, O0);
1990 __ mov(src_pos, O1);
1991 __ mov(dst, O2);
1992 __ mov(dst_pos, O3);
1993 __ mov(length, O4);
1994 address copyfunc_addr = StubRoutines::generic_arraycopy();
1995
1996 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
1997 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy));
1998 } else {
1999 #ifndef PRODUCT
2000 if (PrintC1Statistics) {
2001 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
2002 __ inc_counter(counter, G1, G3);
2003 }
2004 #endif
2005 __ call_VM_leaf(tmp, copyfunc_addr);
2006 }
2007
2008 if (copyfunc_addr != NULL) {
2009 __ xor3(O0, -1, tmp);
2010 __ sub(length, tmp, length);
2011 __ add(src_pos, tmp, src_pos);
2012 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry());
2013 __ delayed()->add(dst_pos, tmp, dst_pos);
2014 } else {
2015 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry());
2016 __ delayed()->nop();
2017 }
2018 __ bind(*stub->continuation());
2019 return;
2020 }
2021
2022 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
2023
2024 // make sure src and dst are non-null and load array length
2025 if (flags & LIR_OpArrayCopy::src_null_check) {
2026 __ tst(src);
2027 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
2028 __ delayed()->nop();
2029 }
2030
2031 if (flags & LIR_OpArrayCopy::dst_null_check) {
2032 __ tst(dst);
2033 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
2034 __ delayed()->nop();
2035 }
2036
2037 // If the compiler was not able to prove that exact type of the source or the destination
2038 // of the arraycopy is an array type, check at runtime if the source or the destination is
2039 // an instance type.
2040 if (flags & LIR_OpArrayCopy::type_check) {
2041 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2042 __ load_klass(dst, tmp);
2043 __ lduw(tmp, in_bytes(Klass::layout_helper_offset()), tmp2);
2044 __ cmp(tmp2, Klass::_lh_neutral_value);
2045 __ br(Assembler::greaterEqual, false, Assembler::pn, *stub->entry());
2046 __ delayed()->nop();
2047 }
2048
2049 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2050 __ load_klass(src, tmp);
2051 __ lduw(tmp, in_bytes(Klass::layout_helper_offset()), tmp2);
2052 __ cmp(tmp2, Klass::_lh_neutral_value);
2053 __ br(Assembler::greaterEqual, false, Assembler::pn, *stub->entry());
2054 __ delayed()->nop();
2055 }
2056 }
2057
2058 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2059 // test src_pos register
2060 __ cmp_zero_and_br(Assembler::less, src_pos, *stub->entry());
2061 __ delayed()->nop();
2062 }
2063
2064 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2065 // test dst_pos register
2066 __ cmp_zero_and_br(Assembler::less, dst_pos, *stub->entry());
2067 __ delayed()->nop();
2068 }
2069
2070 if (flags & LIR_OpArrayCopy::length_positive_check) {
2071 // make sure length isn't negative
2072 __ cmp_zero_and_br(Assembler::less, length, *stub->entry());
2073 __ delayed()->nop();
2074 }
2075
2076 if (flags & LIR_OpArrayCopy::src_range_check) {
2077 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
2078 __ add(length, src_pos, tmp);
2079 __ cmp(tmp2, tmp);
2080 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2081 __ delayed()->nop();
2082 }
2083
2084 if (flags & LIR_OpArrayCopy::dst_range_check) {
2085 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2);
2086 __ add(length, dst_pos, tmp);
2087 __ cmp(tmp2, tmp);
2088 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2089 __ delayed()->nop();
2090 }
2091
2092 int shift = shift_amount(basic_type);
2093
2094 if (flags & LIR_OpArrayCopy::type_check) {
2095 // We don't know the array types are compatible
2096 if (basic_type != T_OBJECT) {
2097 // Simple test for basic type arrays
2098 if (UseCompressedClassPointers) {
2099 // We don't need decode because we just need to compare
2100 __ lduw(src, oopDesc::klass_offset_in_bytes(), tmp);
2101 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2102 __ cmp(tmp, tmp2);
2103 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2104 } else {
2105 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
2106 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2107 __ cmp(tmp, tmp2);
2108 __ brx(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2109 }
2110 __ delayed()->nop();
2111 } else {
2112 // For object arrays, if src is a sub class of dst then we can
2113 // safely do the copy.
2114 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2115
2116 Label cont, slow;
2117 assert_different_registers(tmp, tmp2, G3, G1);
2118
2119 __ load_klass(src, G3);
2120 __ load_klass(dst, G1);
2121
2122 __ check_klass_subtype_fast_path(G3, G1, tmp, tmp2, &cont, copyfunc_addr == NULL ? stub->entry() : &slow, NULL);
2123
2124 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2125 __ delayed()->nop();
2126
2127 __ cmp(G3, 0);
2128 if (copyfunc_addr != NULL) { // use stub if available
2129 // src is not a sub class of dst so we have to do a
2130 // per-element check.
2131 __ br(Assembler::notEqual, false, Assembler::pt, cont);
2132 __ delayed()->nop();
2133
2134 __ bind(slow);
2135
2136 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2137 if ((flags & mask) != mask) {
2138 // Check that at least both of them object arrays.
2139 assert(flags & mask, "one of the two should be known to be an object array");
2140
2141 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2142 __ load_klass(src, tmp);
2143 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2144 __ load_klass(dst, tmp);
2145 }
2146 int lh_offset = in_bytes(Klass::layout_helper_offset());
2147
2148 __ lduw(tmp, lh_offset, tmp2);
2149
2150 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2151 __ set(objArray_lh, tmp);
2152 __ cmp(tmp, tmp2);
2153 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2154 __ delayed()->nop();
2155 }
2156
2157 Register src_ptr = O0;
2158 Register dst_ptr = O1;
2159 Register len = O2;
2160 Register chk_off = O3;
2161 Register super_k = O4;
2162
2163 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2164 if (shift == 0) {
2165 __ add(src_ptr, src_pos, src_ptr);
2166 } else {
2167 __ sll(src_pos, shift, tmp);
2168 __ add(src_ptr, tmp, src_ptr);
2169 }
2170
2171 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2172 if (shift == 0) {
2173 __ add(dst_ptr, dst_pos, dst_ptr);
2174 } else {
2175 __ sll(dst_pos, shift, tmp);
2176 __ add(dst_ptr, tmp, dst_ptr);
2177 }
2178 __ mov(length, len);
2179 __ load_klass(dst, tmp);
2180
2181 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2182 __ ld_ptr(tmp, ek_offset, super_k);
2183
2184 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2185 __ lduw(super_k, sco_offset, chk_off);
2186
2187 __ call_VM_leaf(tmp, copyfunc_addr);
2188
2189 #ifndef PRODUCT
2190 if (PrintC1Statistics) {
2191 Label failed;
2192 __ br_notnull_short(O0, Assembler::pn, failed);
2193 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, G1, G3);
2194 __ bind(failed);
2195 }
2196 #endif
2197
2198 __ br_null(O0, false, Assembler::pt, *stub->continuation());
2199 __ delayed()->xor3(O0, -1, tmp);
2200
2201 #ifndef PRODUCT
2202 if (PrintC1Statistics) {
2203 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, G1, G3);
2204 }
2205 #endif
2206
2207 __ sub(length, tmp, length);
2208 __ add(src_pos, tmp, src_pos);
2209 __ br(Assembler::always, false, Assembler::pt, *stub->entry());
2210 __ delayed()->add(dst_pos, tmp, dst_pos);
2211
2212 __ bind(cont);
2213 } else {
2214 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2215 __ delayed()->nop();
2216 __ bind(cont);
2217 }
2218 }
2219 }
2220
2221 #ifdef ASSERT
2222 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2223 // Sanity check the known type with the incoming class. For the
2224 // primitive case the types must match exactly with src.klass and
2225 // dst.klass each exactly matching the default type. For the
2226 // object array case, if no type check is needed then either the
2227 // dst type is exactly the expected type and the src type is a
2228 // subtype which we can't check or src is the same array as dst
2229 // but not necessarily exactly of type default_type.
2230 Label known_ok, halt;
2231 metadata2reg(op->expected_type()->constant_encoding(), tmp);
2232 if (UseCompressedClassPointers) {
2233 // tmp holds the default type. It currently comes uncompressed after the
2234 // load of a constant, so encode it.
2235 __ encode_klass_not_null(tmp);
2236 // load the raw value of the dst klass, since we will be comparing
2237 // uncompressed values directly.
2238 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2239 if (basic_type != T_OBJECT) {
2240 __ cmp(tmp, tmp2);
2241 __ br(Assembler::notEqual, false, Assembler::pn, halt);
2242 // load the raw value of the src klass.
2243 __ delayed()->lduw(src, oopDesc::klass_offset_in_bytes(), tmp2);
2244 __ cmp_and_br_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
2245 } else {
2246 __ cmp(tmp, tmp2);
2247 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2248 __ delayed()->cmp(src, dst);
2249 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2250 __ delayed()->nop();
2251 }
2252 } else {
2253 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2254 if (basic_type != T_OBJECT) {
2255 __ cmp(tmp, tmp2);
2256 __ brx(Assembler::notEqual, false, Assembler::pn, halt);
2257 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
2258 __ cmp_and_brx_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
2259 } else {
2260 __ cmp(tmp, tmp2);
2261 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2262 __ delayed()->cmp(src, dst);
2263 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2264 __ delayed()->nop();
2265 }
2266 }
2267 __ bind(halt);
2268 __ stop("incorrect type information in arraycopy");
2269 __ bind(known_ok);
2270 }
2271 #endif
2272
2273 #ifndef PRODUCT
2274 if (PrintC1Statistics) {
2275 address counter = Runtime1::arraycopy_count_address(basic_type);
2276 __ inc_counter(counter, G1, G3);
2277 }
2278 #endif
2279
2280 Register src_ptr = O0;
2281 Register dst_ptr = O1;
2282 Register len = O2;
2283
2284 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2285 if (shift == 0) {
2286 __ add(src_ptr, src_pos, src_ptr);
2287 } else {
2288 __ sll(src_pos, shift, tmp);
2289 __ add(src_ptr, tmp, src_ptr);
2290 }
2291
2292 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2293 if (shift == 0) {
2294 __ add(dst_ptr, dst_pos, dst_ptr);
2295 } else {
2296 __ sll(dst_pos, shift, tmp);
2297 __ add(dst_ptr, tmp, dst_ptr);
2298 }
2299
2300 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2301 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2302 const char *name;
2303 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2304
2305 // arraycopy stubs takes a length in number of elements, so don't scale it.
2306 __ mov(length, len);
2307 __ call_VM_leaf(tmp, entry);
2308
2309 __ bind(*stub->continuation());
2310 }
2311
2312
2313 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2314 if (dest->is_single_cpu()) {
2315 #ifdef _LP64
2316 if (left->type() == T_OBJECT) {
2317 switch (code) {
2318 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break;
2319 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break;
2320 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2321 default: ShouldNotReachHere();
2322 }
2323 } else
2324 #endif
2325 switch (code) {
2326 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break;
2327 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break;
2328 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2329 default: ShouldNotReachHere();
2330 }
2331 } else {
2332 #ifdef _LP64
2333 switch (code) {
2334 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2335 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2336 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2337 default: ShouldNotReachHere();
2338 }
2339 #else
2340 switch (code) {
2341 case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2342 case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2343 case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2344 default: ShouldNotReachHere();
2345 }
2346 #endif
2347 }
2348 }
2349
2350
2351 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2352 #ifdef _LP64
2353 if (left->type() == T_OBJECT) {
2354 count = count & 63; // shouldn't shift by more than sizeof(intptr_t)
2355 Register l = left->as_register();
2356 Register d = dest->as_register_lo();
2357 switch (code) {
2358 case lir_shl: __ sllx (l, count, d); break;
2359 case lir_shr: __ srax (l, count, d); break;
2360 case lir_ushr: __ srlx (l, count, d); break;
2361 default: ShouldNotReachHere();
2362 }
2363 return;
2364 }
2365 #endif
2366
2367 if (dest->is_single_cpu()) {
2368 count = count & 0x1F; // Java spec
2369 switch (code) {
2370 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break;
2371 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break;
2372 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break;
2373 default: ShouldNotReachHere();
2374 }
2375 } else if (dest->is_double_cpu()) {
2376 count = count & 63; // Java spec
2377 switch (code) {
2378 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2379 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2380 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2381 default: ShouldNotReachHere();
2382 }
2383 } else {
2384 ShouldNotReachHere();
2385 }
2386 }
2387
2388
2389 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2390 assert(op->tmp1()->as_register() == G1 &&
2391 op->tmp2()->as_register() == G3 &&
2392 op->tmp3()->as_register() == G4 &&
2393 op->obj()->as_register() == O0 &&
2394 op->klass()->as_register() == G5, "must be");
2395 if (op->init_check()) {
2396 __ ldub(op->klass()->as_register(),
2397 in_bytes(InstanceKlass::init_state_offset()),
2398 op->tmp1()->as_register());
2399 add_debug_info_for_null_check_here(op->stub()->info());
2400 __ cmp(op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2401 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry());
2402 __ delayed()->nop();
2403 }
2404 __ allocate_object(op->obj()->as_register(),
2405 op->tmp1()->as_register(),
2406 op->tmp2()->as_register(),
2407 op->tmp3()->as_register(),
2408 op->header_size(),
2409 op->object_size(),
2410 op->klass()->as_register(),
2411 *op->stub()->entry());
2412 __ bind(*op->stub()->continuation());
2413 __ verify_oop(op->obj()->as_register());
2414 }
2415
2416
2417 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2418 assert(op->tmp1()->as_register() == G1 &&
2419 op->tmp2()->as_register() == G3 &&
2420 op->tmp3()->as_register() == G4 &&
2421 op->tmp4()->as_register() == O1 &&
2422 op->klass()->as_register() == G5, "must be");
2423
2424 LP64_ONLY( __ signx(op->len()->as_register()); )
2425 if (UseSlowPath ||
2426 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2427 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2428 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2429 __ delayed()->nop();
2430 } else {
2431 __ allocate_array(op->obj()->as_register(),
2432 op->len()->as_register(),
2433 op->tmp1()->as_register(),
2434 op->tmp2()->as_register(),
2435 op->tmp3()->as_register(),
2436 arrayOopDesc::header_size(op->type()),
2437 type2aelembytes(op->type()),
2438 op->klass()->as_register(),
2439 *op->stub()->entry());
2440 }
2441 __ bind(*op->stub()->continuation());
2442 }
2443
2444
2445 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2446 ciMethodData *md, ciProfileData *data,
2447 Register recv, Register tmp1, Label* update_done) {
2448 uint i;
2449 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2450 Label next_test;
2451 // See if the receiver is receiver[n].
2452 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2453 mdo_offset_bias);
2454 __ ld_ptr(receiver_addr, tmp1);
2455 __ verify_klass_ptr(tmp1);
2456 __ cmp_and_brx_short(recv, tmp1, Assembler::notEqual, Assembler::pt, next_test);
2457 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2458 mdo_offset_bias);
2459 __ ld_ptr(data_addr, tmp1);
2460 __ add(tmp1, DataLayout::counter_increment, tmp1);
2461 __ st_ptr(tmp1, data_addr);
2462 __ ba(*update_done);
2463 __ delayed()->nop();
2464 __ bind(next_test);
2465 }
2466
2467 // Didn't find receiver; find next empty slot and fill it in
2468 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2469 Label next_test;
2470 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2471 mdo_offset_bias);
2472 __ ld_ptr(recv_addr, tmp1);
2473 __ br_notnull_short(tmp1, Assembler::pt, next_test);
2474 __ st_ptr(recv, recv_addr);
2475 __ set(DataLayout::counter_increment, tmp1);
2476 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2477 mdo_offset_bias);
2478 __ ba(*update_done);
2479 __ delayed()->nop();
2480 __ bind(next_test);
2481 }
2482 }
2483
2484
2485 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2486 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2487 md = method->method_data_or_null();
2488 assert(md != NULL, "Sanity");
2489 data = md->bci_to_data(bci);
2490 assert(data != NULL, "need data for checkcast");
2491 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2492 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2493 // The offset is large so bias the mdo by the base of the slot so
2494 // that the ld can use simm13s to reference the slots of the data
2495 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2496 }
2497 }
2498
2499 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2500 // we always need a stub for the failure case.
2501 CodeStub* stub = op->stub();
2502 Register obj = op->object()->as_register();
2503 Register k_RInfo = op->tmp1()->as_register();
2504 Register klass_RInfo = op->tmp2()->as_register();
2505 Register dst = op->result_opr()->as_register();
2506 Register Rtmp1 = op->tmp3()->as_register();
2507 ciKlass* k = op->klass();
2508
2509
2510 if (obj == k_RInfo) {
2511 k_RInfo = klass_RInfo;
2512 klass_RInfo = obj;
2513 }
2514
2515 ciMethodData* md;
2516 ciProfileData* data;
2517 int mdo_offset_bias = 0;
2518 if (op->should_profile()) {
2519 ciMethod* method = op->profiled_method();
2520 assert(method != NULL, "Should have method");
2521 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2522
2523 Label not_null;
2524 __ br_notnull_short(obj, Assembler::pn, not_null);
2525 Register mdo = k_RInfo;
2526 Register data_val = Rtmp1;
2527 metadata2reg(md->constant_encoding(), mdo);
2528 if (mdo_offset_bias > 0) {
2529 __ set(mdo_offset_bias, data_val);
2530 __ add(mdo, data_val, mdo);
2531 }
2532 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2533 __ ldub(flags_addr, data_val);
2534 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2535 __ stb(data_val, flags_addr);
2536 __ ba(*obj_is_null);
2537 __ delayed()->nop();
2538 __ bind(not_null);
2539 } else {
2540 __ br_null(obj, false, Assembler::pn, *obj_is_null);
2541 __ delayed()->nop();
2542 }
2543
2544 Label profile_cast_failure, profile_cast_success;
2545 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
2546 Label *success_target = op->should_profile() ? &profile_cast_success : success;
2547
2548 // patching may screw with our temporaries on sparc,
2549 // so let's do it before loading the class
2550 if (k->is_loaded()) {
2551 metadata2reg(k->constant_encoding(), k_RInfo);
2552 } else {
2553 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2554 }
2555 assert(obj != k_RInfo, "must be different");
2556
2557 // get object class
2558 // not a safepoint as obj null check happens earlier
2559 __ load_klass(obj, klass_RInfo);
2560 if (op->fast_check()) {
2561 assert_different_registers(klass_RInfo, k_RInfo);
2562 __ cmp(k_RInfo, klass_RInfo);
2563 __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target);
2564 __ delayed()->nop();
2565 } else {
2566 bool need_slow_path = true;
2567 if (k->is_loaded()) {
2568 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset()))
2569 need_slow_path = false;
2570 // perform the fast part of the checking logic
2571 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
2572 (need_slow_path ? success_target : NULL),
2573 failure_target, NULL,
2574 RegisterOrConstant(k->super_check_offset()));
2575 } else {
2576 // perform the fast part of the checking logic
2577 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target,
2578 failure_target, NULL);
2579 }
2580 if (need_slow_path) {
2581 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2582 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2583 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2584 __ delayed()->nop();
2585 __ cmp(G3, 0);
2586 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2587 __ delayed()->nop();
2588 // Fall through to success case
2589 }
2590 }
2591
2592 if (op->should_profile()) {
2593 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2594 assert_different_registers(obj, mdo, recv, tmp1);
2595 __ bind(profile_cast_success);
2596 metadata2reg(md->constant_encoding(), mdo);
2597 if (mdo_offset_bias > 0) {
2598 __ set(mdo_offset_bias, tmp1);
2599 __ add(mdo, tmp1, mdo);
2600 }
2601 __ load_klass(obj, recv);
2602 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
2603 // Jump over the failure case
2604 __ ba(*success);
2605 __ delayed()->nop();
2606 // Cast failure case
2607 __ bind(profile_cast_failure);
2608 metadata2reg(md->constant_encoding(), mdo);
2609 if (mdo_offset_bias > 0) {
2610 __ set(mdo_offset_bias, tmp1);
2611 __ add(mdo, tmp1, mdo);
2612 }
2613 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2614 __ ld_ptr(data_addr, tmp1);
2615 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2616 __ st_ptr(tmp1, data_addr);
2617 __ ba(*failure);
2618 __ delayed()->nop();
2619 }
2620 __ ba(*success);
2621 __ delayed()->nop();
2622 }
2623
2624 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2625 LIR_Code code = op->code();
2626 if (code == lir_store_check) {
2627 Register value = op->object()->as_register();
2628 Register array = op->array()->as_register();
2629 Register k_RInfo = op->tmp1()->as_register();
2630 Register klass_RInfo = op->tmp2()->as_register();
2631 Register Rtmp1 = op->tmp3()->as_register();
2632
2633 __ verify_oop(value);
2634 CodeStub* stub = op->stub();
2635 // check if it needs to be profiled
2636 ciMethodData* md;
2637 ciProfileData* data;
2638 int mdo_offset_bias = 0;
2639 if (op->should_profile()) {
2640 ciMethod* method = op->profiled_method();
2641 assert(method != NULL, "Should have method");
2642 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2643 }
2644 Label profile_cast_success, profile_cast_failure, done;
2645 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
2646 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
2647
2648 if (op->should_profile()) {
2649 Label not_null;
2650 __ br_notnull_short(value, Assembler::pn, not_null);
2651 Register mdo = k_RInfo;
2652 Register data_val = Rtmp1;
2653 metadata2reg(md->constant_encoding(), mdo);
2654 if (mdo_offset_bias > 0) {
2655 __ set(mdo_offset_bias, data_val);
2656 __ add(mdo, data_val, mdo);
2657 }
2658 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2659 __ ldub(flags_addr, data_val);
2660 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2661 __ stb(data_val, flags_addr);
2662 __ ba_short(done);
2663 __ bind(not_null);
2664 } else {
2665 __ br_null_short(value, Assembler::pn, done);
2666 }
2667 add_debug_info_for_null_check_here(op->info_for_exception());
2668 __ load_klass(array, k_RInfo);
2669 __ load_klass(value, klass_RInfo);
2670
2671 // get instance klass
2672 __ ld_ptr(Address(k_RInfo, ObjArrayKlass::element_klass_offset()), k_RInfo);
2673 // perform the fast part of the checking logic
2674 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL);
2675
2676 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2677 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2678 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2679 __ delayed()->nop();
2680 __ cmp(G3, 0);
2681 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2682 __ delayed()->nop();
2683 // fall through to the success case
2684
2685 if (op->should_profile()) {
2686 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2687 assert_different_registers(value, mdo, recv, tmp1);
2688 __ bind(profile_cast_success);
2689 metadata2reg(md->constant_encoding(), mdo);
2690 if (mdo_offset_bias > 0) {
2691 __ set(mdo_offset_bias, tmp1);
2692 __ add(mdo, tmp1, mdo);
2693 }
2694 __ load_klass(value, recv);
2695 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2696 __ ba_short(done);
2697 // Cast failure case
2698 __ bind(profile_cast_failure);
2699 metadata2reg(md->constant_encoding(), mdo);
2700 if (mdo_offset_bias > 0) {
2701 __ set(mdo_offset_bias, tmp1);
2702 __ add(mdo, tmp1, mdo);
2703 }
2704 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2705 __ ld_ptr(data_addr, tmp1);
2706 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2707 __ st_ptr(tmp1, data_addr);
2708 __ ba(*stub->entry());
2709 __ delayed()->nop();
2710 }
2711 __ bind(done);
2712 } else if (code == lir_checkcast) {
2713 Register obj = op->object()->as_register();
2714 Register dst = op->result_opr()->as_register();
2715 Label success;
2716 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
2717 __ bind(success);
2718 __ mov(obj, dst);
2719 } else if (code == lir_instanceof) {
2720 Register obj = op->object()->as_register();
2721 Register dst = op->result_opr()->as_register();
2722 Label success, failure, done;
2723 emit_typecheck_helper(op, &success, &failure, &failure);
2724 __ bind(failure);
2725 __ set(0, dst);
2726 __ ba_short(done);
2727 __ bind(success);
2728 __ set(1, dst);
2729 __ bind(done);
2730 } else {
2731 ShouldNotReachHere();
2732 }
2733
2734 }
2735
2736
2737 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2738 if (op->code() == lir_cas_long) {
2739 assert(VM_Version::supports_cx8(), "wrong machine");
2740 Register addr = op->addr()->as_pointer_register();
2741 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2742 Register cmp_value_hi = op->cmp_value()->as_register_hi();
2743 Register new_value_lo = op->new_value()->as_register_lo();
2744 Register new_value_hi = op->new_value()->as_register_hi();
2745 Register t1 = op->tmp1()->as_register();
2746 Register t2 = op->tmp2()->as_register();
2747 #ifdef _LP64
2748 __ mov(cmp_value_lo, t1);
2749 __ mov(new_value_lo, t2);
2750 // perform the compare and swap operation
2751 __ casx(addr, t1, t2);
2752 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2753 // overwritten with the original value in "addr" and will be equal to t1.
2754 __ cmp(t1, t2);
2755 #else
2756 // move high and low halves of long values into single registers
2757 __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg
2758 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half
2759 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value
2760 __ sllx(new_value_hi, 32, t2);
2761 __ srl(new_value_lo, 0, new_value_lo);
2762 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap
2763 // perform the compare and swap operation
2764 __ casx(addr, t1, t2);
2765 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2766 // overwritten with the original value in "addr" and will be equal to t1.
2767 // Produce icc flag for 32bit.
2768 __ sub(t1, t2, t2);
2769 __ srlx(t2, 32, t1);
2770 __ orcc(t2, t1, G0);
2771 #endif
2772 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2773 Register addr = op->addr()->as_pointer_register();
2774 Register cmp_value = op->cmp_value()->as_register();
2775 Register new_value = op->new_value()->as_register();
2776 Register t1 = op->tmp1()->as_register();
2777 Register t2 = op->tmp2()->as_register();
2778 __ mov(cmp_value, t1);
2779 __ mov(new_value, t2);
2780 if (op->code() == lir_cas_obj) {
2781 if (UseCompressedOops) {
2782 __ encode_heap_oop(t1);
2783 __ encode_heap_oop(t2);
2784 __ cas(addr, t1, t2);
2785 } else {
2786 __ cas_ptr(addr, t1, t2);
2787 }
2788 } else {
2789 __ cas(addr, t1, t2);
2790 }
2791 __ cmp(t1, t2);
2792 } else {
2793 Unimplemented();
2794 }
2795 }
2796
2797 void LIR_Assembler::set_24bit_FPU() {
2798 Unimplemented();
2799 }
2800
2801
2802 void LIR_Assembler::reset_FPU() {
2803 Unimplemented();
2804 }
2805
2806
2807 void LIR_Assembler::breakpoint() {
2808 __ breakpoint_trap();
2809 }
2810
2811
2812 void LIR_Assembler::push(LIR_Opr opr) {
2813 Unimplemented();
2814 }
2815
2816
2817 void LIR_Assembler::pop(LIR_Opr opr) {
2818 Unimplemented();
2819 }
2820
2821
2822 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2823 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2824 Register dst = dst_opr->as_register();
2825 Register reg = mon_addr.base();
2826 int offset = mon_addr.disp();
2827 // compute pointer to BasicLock
2828 if (mon_addr.is_simm13()) {
2829 __ add(reg, offset, dst);
2830 } else {
2831 __ set(offset, dst);
2832 __ add(dst, reg, dst);
2833 }
2834 }
2835
2836 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2837 assert(op->crc()->is_single_cpu(), "crc must be register");
2838 assert(op->val()->is_single_cpu(), "byte value must be register");
2839 assert(op->result_opr()->is_single_cpu(), "result must be register");
2840 Register crc = op->crc()->as_register();
2841 Register val = op->val()->as_register();
2842 Register table = op->result_opr()->as_register();
2843 Register res = op->result_opr()->as_register();
2844
2845 assert_different_registers(val, crc, table);
2846
2847 __ set(ExternalAddress(StubRoutines::crc_table_addr()), table);
2848 __ not1(crc);
2849 __ clruwu(crc);
2850 __ update_byte_crc32(crc, val, table);
2851 __ not1(crc);
2852
2853 __ mov(crc, res);
2854 }
2855
2856 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2857 Register obj = op->obj_opr()->as_register();
2858 Register hdr = op->hdr_opr()->as_register();
2859 Register lock = op->lock_opr()->as_register();
2860
2861 // obj may not be an oop
2862 if (op->code() == lir_lock) {
2863 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2864 if (UseFastLocking) {
2865 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2866 // add debug info for NullPointerException only if one is possible
2867 if (op->info() != NULL) {
2868 add_debug_info_for_null_check_here(op->info());
2869 }
2870 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2871 } else {
2872 // always do slow locking
2873 // note: the slow locking code could be inlined here, however if we use
2874 // slow locking, speed doesn't matter anyway and this solution is
2875 // simpler and requires less duplicated code - additionally, the
2876 // slow locking code is the same in either case which simplifies
2877 // debugging
2878 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2879 __ delayed()->nop();
2880 }
2881 } else {
2882 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2883 if (UseFastLocking) {
2884 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2885 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2886 } else {
2887 // always do slow unlocking
2888 // note: the slow unlocking code could be inlined here, however if we use
2889 // slow unlocking, speed doesn't matter anyway and this solution is
2890 // simpler and requires less duplicated code - additionally, the
2891 // slow unlocking code is the same in either case which simplifies
2892 // debugging
2893 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2894 __ delayed()->nop();
2895 }
2896 }
2897 __ bind(*op->stub()->continuation());
2898 }
2899
2900
2901 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2902 ciMethod* method = op->profiled_method();
2903 int bci = op->profiled_bci();
2904 ciMethod* callee = op->profiled_callee();
2905
2906 // Update counter for all call types
2907 ciMethodData* md = method->method_data_or_null();
2908 assert(md != NULL, "Sanity");
2909 ciProfileData* data = md->bci_to_data(bci);
2910 assert(data->is_CounterData(), "need CounterData for calls");
2911 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2912 Register mdo = op->mdo()->as_register();
2913 #ifdef _LP64
2914 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2915 Register tmp1 = op->tmp1()->as_register_lo();
2916 #else
2917 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2918 Register tmp1 = op->tmp1()->as_register();
2919 #endif
2920 metadata2reg(md->constant_encoding(), mdo);
2921 int mdo_offset_bias = 0;
2922 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2923 data->size_in_bytes())) {
2924 // The offset is large so bias the mdo by the base of the slot so
2925 // that the ld can use simm13s to reference the slots of the data
2926 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2927 __ set(mdo_offset_bias, O7);
2928 __ add(mdo, O7, mdo);
2929 }
2930
2931 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2932 Bytecodes::Code bc = method->java_code_at_bci(bci);
2933 const bool callee_is_static = callee->is_loaded() && callee->is_static();
2934 // Perform additional virtual call profiling for invokevirtual and
2935 // invokeinterface bytecodes
2936 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
2937 !callee_is_static && // required for optimized MH invokes
2938 C1ProfileVirtualCalls) {
2939 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2940 Register recv = op->recv()->as_register();
2941 assert_different_registers(mdo, tmp1, recv);
2942 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2943 ciKlass* known_klass = op->known_holder();
2944 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2945 // We know the type that will be seen at this call site; we can
2946 // statically update the MethodData* rather than needing to do
2947 // dynamic tests on the receiver type
2948
2949 // NOTE: we should probably put a lock around this search to
2950 // avoid collisions by concurrent compilations
2951 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2952 uint i;
2953 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2954 ciKlass* receiver = vc_data->receiver(i);
2955 if (known_klass->equals(receiver)) {
2956 Address data_addr(mdo, md->byte_offset_of_slot(data,
2957 VirtualCallData::receiver_count_offset(i)) -
2958 mdo_offset_bias);
2959 __ ld_ptr(data_addr, tmp1);
2960 __ add(tmp1, DataLayout::counter_increment, tmp1);
2961 __ st_ptr(tmp1, data_addr);
2962 return;
2963 }
2964 }
2965
2966 // Receiver type not found in profile data; select an empty slot
2967
2968 // Note that this is less efficient than it should be because it
2969 // always does a write to the receiver part of the
2970 // VirtualCallData rather than just the first time
2971 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2972 ciKlass* receiver = vc_data->receiver(i);
2973 if (receiver == NULL) {
2974 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2975 mdo_offset_bias);
2976 metadata2reg(known_klass->constant_encoding(), tmp1);
2977 __ st_ptr(tmp1, recv_addr);
2978 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2979 mdo_offset_bias);
2980 __ ld_ptr(data_addr, tmp1);
2981 __ add(tmp1, DataLayout::counter_increment, tmp1);
2982 __ st_ptr(tmp1, data_addr);
2983 return;
2984 }
2985 }
2986 } else {
2987 __ load_klass(recv, recv);
2988 Label update_done;
2989 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2990 // Receiver did not match any saved receiver and there is no empty row for it.
2991 // Increment total counter to indicate polymorphic case.
2992 __ ld_ptr(counter_addr, tmp1);
2993 __ add(tmp1, DataLayout::counter_increment, tmp1);
2994 __ st_ptr(tmp1, counter_addr);
2995
2996 __ bind(update_done);
2997 }
2998 } else {
2999 // Static call
3000 __ ld_ptr(counter_addr, tmp1);
3001 __ add(tmp1, DataLayout::counter_increment, tmp1);
3002 __ st_ptr(tmp1, counter_addr);
3003 }
3004 }
3005
3006 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3007 Register obj = op->obj()->as_register();
3008 Register tmp1 = op->tmp()->as_pointer_register();
3009 Register tmp2 = G1;
3010 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3011 ciKlass* exact_klass = op->exact_klass();
3012 intptr_t current_klass = op->current_klass();
3013 bool not_null = op->not_null();
3014 bool no_conflict = op->no_conflict();
3015
3016 Label update, next, none;
3017
3018 bool do_null = !not_null;
3019 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3020 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3021
3022 assert(do_null || do_update, "why are we here?");
3023 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3024
3025 __ verify_oop(obj);
3026
3027 if (tmp1 != obj) {
3028 __ mov(obj, tmp1);
3029 }
3030 if (do_null) {
3031 __ br_notnull_short(tmp1, Assembler::pt, update);
3032 if (!TypeEntries::was_null_seen(current_klass)) {
3033 __ ld_ptr(mdo_addr, tmp1);
3034 __ or3(tmp1, TypeEntries::null_seen, tmp1);
3035 __ st_ptr(tmp1, mdo_addr);
3036 }
3037 if (do_update) {
3038 __ ba(next);
3039 __ delayed()->nop();
3040 }
3041 #ifdef ASSERT
3042 } else {
3043 __ br_notnull_short(tmp1, Assembler::pt, update);
3044 __ stop("unexpect null obj");
3045 #endif
3046 }
3047
3048 __ bind(update);
3049
3050 if (do_update) {
3051 #ifdef ASSERT
3052 if (exact_klass != NULL) {
3053 Label ok;
3054 __ load_klass(tmp1, tmp1);
3055 metadata2reg(exact_klass->constant_encoding(), tmp2);
3056 __ cmp_and_br_short(tmp1, tmp2, Assembler::equal, Assembler::pt, ok);
3057 __ stop("exact klass and actual klass differ");
3058 __ bind(ok);
3059 }
3060 #endif
3061
3062 Label do_update;
3063 __ ld_ptr(mdo_addr, tmp2);
3064
3065 if (!no_conflict) {
3066 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3067 if (exact_klass != NULL) {
3068 metadata2reg(exact_klass->constant_encoding(), tmp1);
3069 } else {
3070 __ load_klass(tmp1, tmp1);
3071 }
3072
3073 __ xor3(tmp1, tmp2, tmp1);
3074 __ btst(TypeEntries::type_klass_mask, tmp1);
3075 // klass seen before, nothing to do. The unknown bit may have been
3076 // set already but no need to check.
3077 __ brx(Assembler::zero, false, Assembler::pt, next);
3078 __ delayed()->
3079
3080 btst(TypeEntries::type_unknown, tmp1);
3081 // already unknown. Nothing to do anymore.
3082 __ brx(Assembler::notZero, false, Assembler::pt, next);
3083
3084 if (TypeEntries::is_type_none(current_klass)) {
3085 __ delayed()->btst(TypeEntries::type_mask, tmp2);
3086 __ brx(Assembler::zero, true, Assembler::pt, do_update);
3087 // first time here. Set profile type.
3088 __ delayed()->or3(tmp2, tmp1, tmp2);
3089 } else {
3090 __ delayed()->nop();
3091 }
3092 } else {
3093 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3094 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3095
3096 __ btst(TypeEntries::type_unknown, tmp2);
3097 // already unknown. Nothing to do anymore.
3098 __ brx(Assembler::notZero, false, Assembler::pt, next);
3099 __ delayed()->nop();
3100 }
3101
3102 // different than before. Cannot keep accurate profile.
3103 __ or3(tmp2, TypeEntries::type_unknown, tmp2);
3104 } else {
3105 // There's a single possible klass at this profile point
3106 assert(exact_klass != NULL, "should be");
3107 if (TypeEntries::is_type_none(current_klass)) {
3108 metadata2reg(exact_klass->constant_encoding(), tmp1);
3109 __ xor3(tmp1, tmp2, tmp1);
3110 __ btst(TypeEntries::type_klass_mask, tmp1);
3111 __ brx(Assembler::zero, false, Assembler::pt, next);
3112 #ifdef ASSERT
3113
3114 {
3115 Label ok;
3116 __ delayed()->btst(TypeEntries::type_mask, tmp2);
3117 __ brx(Assembler::zero, true, Assembler::pt, ok);
3118 __ delayed()->nop();
3119
3120 __ stop("unexpected profiling mismatch");
3121 __ bind(ok);
3122 }
3123 // first time here. Set profile type.
3124 __ or3(tmp2, tmp1, tmp2);
3125 #else
3126 // first time here. Set profile type.
3127 __ delayed()->or3(tmp2, tmp1, tmp2);
3128 #endif
3129
3130 } else {
3131 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3132 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3133
3134 // already unknown. Nothing to do anymore.
3135 __ btst(TypeEntries::type_unknown, tmp2);
3136 __ brx(Assembler::notZero, false, Assembler::pt, next);
3137 __ delayed()->or3(tmp2, TypeEntries::type_unknown, tmp2);
3138 }
3139 }
3140
3141 __ bind(do_update);
3142 __ st_ptr(tmp2, mdo_addr);
3143
3144 __ bind(next);
3145 }
3146 }
3147
3148 void LIR_Assembler::align_backward_branch_target() {
3149 __ align(OptoLoopAlignment);
3150 }
3151
3152
3153 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
3154 // make sure we are expecting a delay
3155 // this has the side effect of clearing the delay state
3156 // so we can use _masm instead of _masm->delayed() to do the
3157 // code generation.
3158 __ delayed();
3159
3160 // make sure we only emit one instruction
3161 int offset = code_offset();
3162 op->delay_op()->emit_code(this);
3163 #ifdef ASSERT
3164 if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
3165 op->delay_op()->print();
3166 }
3167 assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
3168 "only one instruction can go in a delay slot");
3169 #endif
3170
3171 // we may also be emitting the call info for the instruction
3172 // which we are the delay slot of.
3173 CodeEmitInfo* call_info = op->call_info();
3174 if (call_info) {
3175 add_call_info(code_offset(), call_info);
3176 }
3177
3178 if (VerifyStackAtCalls) {
3179 _masm->sub(FP, SP, O7);
3180 _masm->cmp(O7, initial_frame_size_in_bytes());
3181 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
3182 }
3183 }
3184
3185
3186 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3187 assert(left->is_register(), "can only handle registers");
3188
3189 if (left->is_single_cpu()) {
3190 __ neg(left->as_register(), dest->as_register());
3191 } else if (left->is_single_fpu()) {
3192 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
3193 } else if (left->is_double_fpu()) {
3194 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
3195 } else {
3196 assert (left->is_double_cpu(), "Must be a long");
3197 Register Rlow = left->as_register_lo();
3198 Register Rhi = left->as_register_hi();
3199 #ifdef _LP64
3200 __ sub(G0, Rlow, dest->as_register_lo());
3201 #else
3202 __ subcc(G0, Rlow, dest->as_register_lo());
3203 __ subc (G0, Rhi, dest->as_register_hi());
3204 #endif
3205 }
3206 }
3207
3208
3209 void LIR_Assembler::fxch(int i) {
3210 Unimplemented();
3211 }
3212
3213 void LIR_Assembler::fld(int i) {
3214 Unimplemented();
3215 }
3216
3217 void LIR_Assembler::ffree(int i) {
3218 Unimplemented();
3219 }
3220
3221 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
3222 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3223
3224 // if tmp is invalid, then the function being called doesn't destroy the thread
3225 if (tmp->is_valid()) {
3226 __ save_thread(tmp->as_pointer_register());
3227 }
3228 __ call(dest, relocInfo::runtime_call_type);
3229 __ delayed()->nop();
3230 if (info != NULL) {
3231 add_call_info_here(info);
3232 }
3233 if (tmp->is_valid()) {
3234 __ restore_thread(tmp->as_pointer_register());
3235 }
3236
3237 #ifdef ASSERT
3238 __ verify_thread();
3239 #endif // ASSERT
3240 }
3241
3242
3243 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3244 #ifdef _LP64
3245 ShouldNotReachHere();
3246 #endif
3247
3248 NEEDS_CLEANUP;
3249 if (type == T_LONG) {
3250 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
3251
3252 // (extended to allow indexed as well as constant displaced for JSR-166)
3253 Register idx = noreg; // contains either constant offset or index
3254
3255 int disp = mem_addr->disp();
3256 if (mem_addr->index() == LIR_OprFact::illegalOpr) {
3257 if (!Assembler::is_simm13(disp)) {
3258 idx = O7;
3259 __ set(disp, idx);
3260 }
3261 } else {
3262 assert(disp == 0, "not both indexed and disp");
3263 idx = mem_addr->index()->as_register();
3264 }
3265
3266 int null_check_offset = -1;
3267
3268 Register base = mem_addr->base()->as_register();
3269 if (src->is_register() && dest->is_address()) {
3270 // G4 is high half, G5 is low half
3271 // clear the top bits of G5, and scale up G4
3272 __ srl (src->as_register_lo(), 0, G5);
3273 __ sllx(src->as_register_hi(), 32, G4);
3274 // combine the two halves into the 64 bits of G4
3275 __ or3(G4, G5, G4);
3276 null_check_offset = __ offset();
3277 if (idx == noreg) {
3278 __ stx(G4, base, disp);
3279 } else {
3280 __ stx(G4, base, idx);
3281 }
3282 } else if (src->is_address() && dest->is_register()) {
3283 null_check_offset = __ offset();
3284 if (idx == noreg) {
3285 __ ldx(base, disp, G5);
3286 } else {
3287 __ ldx(base, idx, G5);
3288 }
3289 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi
3290 __ mov (G5, dest->as_register_lo()); // copy low half into lo
3291 } else {
3292 Unimplemented();
3293 }
3294 if (info != NULL) {
3295 add_debug_info_for_null_check(null_check_offset, info);
3296 }
3297
3298 } else {
3299 // use normal move for all other volatiles since they don't need
3300 // special handling to remain atomic.
3301 move_op(src, dest, type, lir_patch_none, info, false, false, false);
3302 }
3303 }
3304
3305 void LIR_Assembler::membar() {
3306 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
3307 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3308 }
3309
3310 void LIR_Assembler::membar_acquire() {
3311 // no-op on TSO
3312 }
3313
3314 void LIR_Assembler::membar_release() {
3315 // no-op on TSO
3316 }
3317
3318 void LIR_Assembler::membar_loadload() {
3319 // no-op
3320 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3321 }
3322
3323 void LIR_Assembler::membar_storestore() {
3324 // no-op
3325 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3326 }
3327
3328 void LIR_Assembler::membar_loadstore() {
3329 // no-op
3330 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3331 }
3332
3333 void LIR_Assembler::membar_storeload() {
3334 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3335 }
3336
3337 void LIR_Assembler::on_spin_wait() {
3338 Unimplemented();
3339 }
3340
3341 // Pack two sequential registers containing 32 bit values
3342 // into a single 64 bit register.
3343 // src and src->successor() are packed into dst
3344 // src and dst may be the same register.
3345 // Note: src is destroyed
3346 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
3347 Register rs = src->as_register();
3348 Register rd = dst->as_register_lo();
3349 __ sllx(rs, 32, rs);
3350 __ srl(rs->successor(), 0, rs->successor());
3351 __ or3(rs, rs->successor(), rd);
3352 }
3353
3354 // Unpack a 64 bit value in a register into
3355 // two sequential registers.
3356 // src is unpacked into dst and dst->successor()
3357 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3358 Register rs = src->as_register_lo();
3359 Register rd = dst->as_register_hi();
3360 assert_different_registers(rs, rd, rd->successor());
3361 __ srlx(rs, 32, rd);
3362 __ srl (rs, 0, rd->successor());
3363 }
3364
3365
3366 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3367 LIR_Address* addr = addr_opr->as_address_ptr();
3368 assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1, "can't handle complex addresses yet");
3369
3370 if (Assembler::is_simm13(addr->disp())) {
3371 __ add(addr->base()->as_pointer_register(), addr->disp(), dest->as_pointer_register());
3372 } else {
3373 __ set(addr->disp(), G3_scratch);
3374 __ add(addr->base()->as_pointer_register(), G3_scratch, dest->as_pointer_register());
3375 }
3376 }
3377
3378
3379 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3380 assert(result_reg->is_register(), "check");
3381 __ mov(G2_thread, result_reg->as_register());
3382 }
3383
3384 #ifdef ASSERT
3385 // emit run-time assertion
3386 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3387 assert(op->code() == lir_assert, "must be");
3388
3389 if (op->in_opr1()->is_valid()) {
3390 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3391 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3392 } else {
3393 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3394 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3395 }
3396
3397 Label ok;
3398 if (op->condition() != lir_cond_always) {
3399 Assembler::Condition acond;
3400 switch (op->condition()) {
3401 case lir_cond_equal: acond = Assembler::equal; break;
3402 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3403 case lir_cond_less: acond = Assembler::less; break;
3404 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3405 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
3406 case lir_cond_greater: acond = Assembler::greater; break;
3407 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
3408 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
3409 default: ShouldNotReachHere();
3410 };
3411 __ br(acond, false, Assembler::pt, ok);
3412 __ delayed()->nop();
3413 }
3414 if (op->halt()) {
3415 const char* str = __ code_string(op->msg());
3416 __ stop(str);
3417 } else {
3418 breakpoint();
3419 }
3420 __ bind(ok);
3421 }
3422 #endif
3423
3424 void LIR_Assembler::peephole(LIR_List* lir) {
3425 LIR_OpList* inst = lir->instructions_list();
3426 for (int i = 0; i < inst->length(); i++) {
3427 LIR_Op* op = inst->at(i);
3428 switch (op->code()) {
3429 case lir_cond_float_branch:
3430 case lir_branch: {
3431 LIR_OpBranch* branch = op->as_OpBranch();
3432 assert(branch->info() == NULL, "shouldn't be state on branches anymore");
3433 LIR_Op* delay_op = NULL;
3434 // we'd like to be able to pull following instructions into
3435 // this slot but we don't know enough to do it safely yet so
3436 // only optimize block to block control flow.
3437 if (LIRFillDelaySlots && branch->block()) {
3438 LIR_Op* prev = inst->at(i - 1);
3439 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3440 // swap previous instruction into delay slot
3441 inst->at_put(i - 1, op);
3442 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3443 #ifndef PRODUCT
3444 if (LIRTracePeephole) {
3445 tty->print_cr("delayed");
3446 inst->at(i - 1)->print();
3447 inst->at(i)->print();
3448 tty->cr();
3449 }
3450 #endif
3451 continue;
3452 }
3453 }
3454
3455 if (!delay_op) {
3456 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
3457 }
3458 inst->insert_before(i + 1, delay_op);
3459 break;
3460 }
3461 case lir_static_call:
3462 case lir_virtual_call:
3463 case lir_icvirtual_call:
3464 case lir_optvirtual_call:
3465 case lir_dynamic_call: {
3466 LIR_Op* prev = inst->at(i - 1);
3467 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
3468 (op->code() != lir_virtual_call ||
3469 !prev->result_opr()->is_single_cpu() ||
3470 prev->result_opr()->as_register() != O0) &&
3471 LIR_Assembler::is_single_instruction(prev)) {
3472 // Only moves without info can be put into the delay slot.
3473 // Also don't allow the setup of the receiver in the delay
3474 // slot for vtable calls.
3475 inst->at_put(i - 1, op);
3476 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3477 #ifndef PRODUCT
3478 if (LIRTracePeephole) {
3479 tty->print_cr("delayed");
3480 inst->at(i - 1)->print();
3481 inst->at(i)->print();
3482 tty->cr();
3483 }
3484 #endif
3485 } else {
3486 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3487 inst->insert_before(i + 1, delay_op);
3488 i++;
3489 }
3490
3491 #if defined(TIERED) && !defined(_LP64)
3492 // fixup the return value from G1 to O0/O1 for long returns.
3493 // It's done here instead of in LIRGenerator because there's
3494 // such a mismatch between the single reg and double reg
3495 // calling convention.
3496 LIR_OpJavaCall* callop = op->as_OpJavaCall();
3497 if (callop->result_opr() == FrameMap::out_long_opr) {
3498 LIR_OpJavaCall* call;
3499 LIR_OprList* arguments = new LIR_OprList(callop->arguments()->length());
3500 for (int a = 0; a < arguments->length(); a++) {
3501 arguments[a] = callop->arguments()[a];
3502 }
3503 if (op->code() == lir_virtual_call) {
3504 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
3505 callop->vtable_offset(), arguments, callop->info());
3506 } else {
3507 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
3508 callop->addr(), arguments, callop->info());
3509 }
3510 inst->at_put(i - 1, call);
3511 inst->insert_before(i + 1, new LIR_Op1(lir_unpack64, FrameMap::g1_long_single_opr, callop->result_opr(),
3512 T_LONG, lir_patch_none, NULL));
3513 }
3514 #endif
3515 break;
3516 }
3517 }
3518 }
3519 }
3520
3521 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3522 LIR_Address* addr = src->as_address_ptr();
3523
3524 assert(data == dest, "swap uses only 2 operands");
3525 assert (code == lir_xchg, "no xadd on sparc");
3526
3527 if (data->type() == T_INT) {
3528 __ swap(as_Address(addr), data->as_register());
3529 } else if (data->is_oop()) {
3530 Register obj = data->as_register();
3531 Register narrow = tmp->as_register();
3532 #ifdef _LP64
3533 assert(UseCompressedOops, "swap is 32bit only");
3534 __ encode_heap_oop(obj, narrow);
3535 __ swap(as_Address(addr), narrow);
3536 __ decode_heap_oop(narrow, obj);
3537 #else
3538 __ swap(as_Address(addr), obj);
3539 #endif
3540 } else {
3541 ShouldNotReachHere();
3542 }
3543 }
3544
3545 #undef __