1 /* 2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_X86_VM_NATIVEINST_X86_HPP 26 #define CPU_X86_VM_NATIVEINST_X86_HPP 27 28 #include "asm/assembler.hpp" 29 #include "memory/allocation.hpp" 30 #include "runtime/icache.hpp" 31 #include "runtime/os.hpp" 32 33 // We have interfaces for the following instructions: 34 // - NativeInstruction 35 // - - NativeCall 36 // - - NativeMovConstReg 37 // - - NativeMovConstRegPatching 38 // - - NativeMovRegMem 39 // - - NativeMovRegMemPatching 40 // - - NativeJump 41 // - - NativeFarJump 42 // - - NativeIllegalOpCode 43 // - - NativeGeneralJump 44 // - - NativeReturn 45 // - - NativeReturnX (return with argument) 46 // - - NativePushConst 47 // - - NativeTstRegMem 48 49 // The base class for different kinds of native instruction abstractions. 50 // Provides the primitive operations to manipulate code relative to this. 51 52 class NativeInstruction VALUE_OBJ_CLASS_SPEC { 53 friend class Relocation; 54 55 public: 56 enum Intel_specific_constants { 57 nop_instruction_code = 0x90, 58 nop_instruction_size = 1 59 }; 60 61 bool is_nop() { return ubyte_at(0) == nop_instruction_code; } 62 inline bool is_call(); 63 inline bool is_call_reg(); 64 inline bool is_illegal(); 65 inline bool is_return(); 66 inline bool is_jump(); 67 inline bool is_jump_reg(); 68 inline bool is_far_jump(); 69 inline bool is_cond_jump(); 70 inline bool is_safepoint_poll(); 71 inline bool is_mov_literal64(); 72 73 protected: 74 address addr_at(int offset) const { return address(this) + offset; } 75 76 s_char sbyte_at(int offset) const { return *(s_char*) addr_at(offset); } 77 u_char ubyte_at(int offset) const { return *(u_char*) addr_at(offset); } 78 79 jint int_at(int offset) const { return *(jint*) addr_at(offset); } 80 81 intptr_t ptr_at(int offset) const { return *(intptr_t*) addr_at(offset); } 82 83 oop oop_at (int offset) const { return *(oop*) addr_at(offset); } 84 85 86 void set_char_at(int offset, char c) { *addr_at(offset) = (u_char)c; wrote(offset); } 87 void set_int_at(int offset, jint i) { *(jint*)addr_at(offset) = i; wrote(offset); } 88 void set_ptr_at (int offset, intptr_t ptr) { *(intptr_t*) addr_at(offset) = ptr; wrote(offset); } 89 void set_oop_at (int offset, oop o) { *(oop*) addr_at(offset) = o; wrote(offset); } 90 91 // This doesn't really do anything on Intel, but it is the place where 92 // cache invalidation belongs, generically: 93 void wrote(int offset); 94 95 public: 96 97 // unit test stuff 98 static void test() {} // override for testing 99 100 inline friend NativeInstruction* nativeInstruction_at(address address); 101 }; 102 103 inline NativeInstruction* nativeInstruction_at(address address) { 104 NativeInstruction* inst = (NativeInstruction*)address; 105 #ifdef ASSERT 106 //inst->verify(); 107 #endif 108 return inst; 109 } 110 111 class NativePltCall: public NativeInstruction { 112 public: 113 enum Intel_specific_constants { 114 instruction_code = 0xE8, 115 instruction_size = 5, 116 instruction_offset = 0, 117 displacement_offset = 1, 118 return_address_offset = 5 119 }; 120 address instruction_address() const { return addr_at(instruction_offset); } 121 address next_instruction_address() const { return addr_at(return_address_offset); } 122 address displacement_address() const { return addr_at(displacement_offset); } 123 int displacement() const { return (jint) int_at(displacement_offset); } 124 address return_address() const { return addr_at(return_address_offset); } 125 address destination() const; 126 address plt_entry() const; 127 address plt_jump() const; 128 address plt_load_got() const; 129 address plt_resolve_call() const; 130 address plt_c2i_stub() const; 131 void set_stub_to_clean(); 132 133 void reset_to_plt_resolve_call(); 134 void set_destination_mt_safe(address dest); 135 136 void verify() const; 137 }; 138 139 inline NativePltCall* nativePltCall_at(address address) { 140 NativePltCall* call = (NativePltCall*) address; 141 #ifdef ASSERT 142 call->verify(); 143 #endif 144 return call; 145 } 146 147 inline NativePltCall* nativePltCall_before(address addr) { 148 address at = addr - NativePltCall::instruction_size; 149 return nativePltCall_at(at); 150 } 151 152 inline NativeCall* nativeCall_at(address address); 153 // The NativeCall is an abstraction for accessing/manipulating native call imm32/rel32off 154 // instructions (used to manipulate inline caches, primitive & dll calls, etc.). 155 156 class NativeCall: public NativeInstruction { 157 public: 158 enum Intel_specific_constants { 159 instruction_code = 0xE8, 160 instruction_size = 5, 161 instruction_offset = 0, 162 displacement_offset = 1, 163 return_address_offset = 5 164 }; 165 166 enum { cache_line_size = BytesPerWord }; // conservative estimate! 167 168 address instruction_address() const { return addr_at(instruction_offset); } 169 address next_instruction_address() const { return addr_at(return_address_offset); } 170 int displacement() const { return (jint) int_at(displacement_offset); } 171 address displacement_address() const { return addr_at(displacement_offset); } 172 address return_address() const { return addr_at(return_address_offset); } 173 address destination() const; 174 void set_destination(address dest) { 175 #ifdef AMD64 176 intptr_t disp = dest - return_address(); 177 guarantee(disp == (intptr_t)(jint)disp, "must be 32-bit offset"); 178 #endif // AMD64 179 set_int_at(displacement_offset, dest - return_address()); 180 } 181 void set_destination_mt_safe(address dest); 182 183 void verify_alignment() { assert((intptr_t)addr_at(displacement_offset) % BytesPerInt == 0, "must be aligned"); } 184 void verify(); 185 void print(); 186 187 // Creation 188 inline friend NativeCall* nativeCall_at(address address); 189 inline friend NativeCall* nativeCall_before(address return_address); 190 191 static bool is_call_at(address instr) { 192 return ((*instr) & 0xFF) == NativeCall::instruction_code; 193 } 194 195 static bool is_call_before(address return_address) { 196 return is_call_at(return_address - NativeCall::return_address_offset); 197 } 198 199 static bool is_call_to(address instr, address target) { 200 return nativeInstruction_at(instr)->is_call() && 201 nativeCall_at(instr)->destination() == target; 202 } 203 204 #if INCLUDE_AOT 205 static bool is_far_call(address instr, address target) { 206 intptr_t disp = target - (instr + sizeof(int32_t)); 207 return !Assembler::is_simm32(disp); 208 } 209 #endif 210 211 // MT-safe patching of a call instruction. 212 static void insert(address code_pos, address entry); 213 214 static void replace_mt_safe(address instr_addr, address code_buffer); 215 }; 216 217 inline NativeCall* nativeCall_at(address address) { 218 NativeCall* call = (NativeCall*)(address - NativeCall::instruction_offset); 219 #ifdef ASSERT 220 call->verify(); 221 #endif 222 return call; 223 } 224 225 inline NativeCall* nativeCall_before(address return_address) { 226 NativeCall* call = (NativeCall*)(return_address - NativeCall::return_address_offset); 227 #ifdef ASSERT 228 call->verify(); 229 #endif 230 return call; 231 } 232 233 class NativeCallReg: public NativeInstruction { 234 public: 235 enum Intel_specific_constants { 236 instruction_code = 0xFF, 237 instruction_offset = 0, 238 return_address_offset_norex = 2, 239 return_address_offset_rex = 3 240 }; 241 242 int next_instruction_offset() const { 243 if (ubyte_at(0) == NativeCallReg::instruction_code) { 244 return return_address_offset_norex; 245 } else { 246 return return_address_offset_rex; 247 } 248 } 249 }; 250 251 // An interface for accessing/manipulating native mov reg, imm32 instructions. 252 // (used to manipulate inlined 32bit data dll calls, etc.) 253 class NativeMovConstReg: public NativeInstruction { 254 #ifdef AMD64 255 static const bool has_rex = true; 256 static const int rex_size = 1; 257 #else 258 static const bool has_rex = false; 259 static const int rex_size = 0; 260 #endif // AMD64 261 public: 262 enum Intel_specific_constants { 263 instruction_code = 0xB8, 264 instruction_size = 1 + rex_size + wordSize, 265 instruction_offset = 0, 266 data_offset = 1 + rex_size, 267 next_instruction_offset = instruction_size, 268 register_mask = 0x07 269 }; 270 271 address instruction_address() const { return addr_at(instruction_offset); } 272 address next_instruction_address() const { return addr_at(next_instruction_offset); } 273 intptr_t data() const { return ptr_at(data_offset); } 274 void set_data(intptr_t x) { set_ptr_at(data_offset, x); } 275 276 void verify(); 277 void print(); 278 279 // unit test stuff 280 static void test() {} 281 282 // Creation 283 inline friend NativeMovConstReg* nativeMovConstReg_at(address address); 284 inline friend NativeMovConstReg* nativeMovConstReg_before(address address); 285 }; 286 287 inline NativeMovConstReg* nativeMovConstReg_at(address address) { 288 NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_offset); 289 #ifdef ASSERT 290 test->verify(); 291 #endif 292 return test; 293 } 294 295 inline NativeMovConstReg* nativeMovConstReg_before(address address) { 296 NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset); 297 #ifdef ASSERT 298 test->verify(); 299 #endif 300 return test; 301 } 302 303 class NativeMovConstRegPatching: public NativeMovConstReg { 304 private: 305 friend NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) { 306 NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_offset); 307 #ifdef ASSERT 308 test->verify(); 309 #endif 310 return test; 311 } 312 }; 313 314 // An interface for accessing/manipulating native moves of the form: 315 // mov[b/w/l/q] [reg + offset], reg (instruction_code_reg2mem) 316 // mov[b/w/l/q] reg, [reg+offset] (instruction_code_mem2reg 317 // mov[s/z]x[w/b/q] [reg + offset], reg 318 // fld_s [reg+offset] 319 // fld_d [reg+offset] 320 // fstp_s [reg + offset] 321 // fstp_d [reg + offset] 322 // mov_literal64 scratch,<pointer> ; mov[b/w/l/q] 0(scratch),reg | mov[b/w/l/q] reg,0(scratch) 323 // 324 // Warning: These routines must be able to handle any instruction sequences 325 // that are generated as a result of the load/store byte,word,long 326 // macros. For example: The load_unsigned_byte instruction generates 327 // an xor reg,reg inst prior to generating the movb instruction. This 328 // class must skip the xor instruction. 329 330 class NativeMovRegMem: public NativeInstruction { 331 public: 332 enum Intel_specific_constants { 333 instruction_prefix_wide_lo = Assembler::REX, 334 instruction_prefix_wide_hi = Assembler::REX_WRXB, 335 instruction_code_xor = 0x33, 336 instruction_extended_prefix = 0x0F, 337 instruction_code_mem2reg_movslq = 0x63, 338 instruction_code_mem2reg_movzxb = 0xB6, 339 instruction_code_mem2reg_movsxb = 0xBE, 340 instruction_code_mem2reg_movzxw = 0xB7, 341 instruction_code_mem2reg_movsxw = 0xBF, 342 instruction_operandsize_prefix = 0x66, 343 instruction_code_reg2mem = 0x89, 344 instruction_code_mem2reg = 0x8b, 345 instruction_code_reg2memb = 0x88, 346 instruction_code_mem2regb = 0x8a, 347 instruction_code_float_s = 0xd9, 348 instruction_code_float_d = 0xdd, 349 instruction_code_long_volatile = 0xdf, 350 instruction_code_xmm_ss_prefix = 0xf3, 351 instruction_code_xmm_sd_prefix = 0xf2, 352 instruction_code_xmm_code = 0x0f, 353 instruction_code_xmm_load = 0x10, 354 instruction_code_xmm_store = 0x11, 355 instruction_code_xmm_lpd = 0x12, 356 357 instruction_VEX_prefix_2bytes = Assembler::VEX_2bytes, 358 instruction_VEX_prefix_3bytes = Assembler::VEX_3bytes, 359 360 instruction_size = 4, 361 instruction_offset = 0, 362 data_offset = 2, 363 next_instruction_offset = 4 364 }; 365 366 // helper 367 int instruction_start() const; 368 369 address instruction_address() const; 370 371 address next_instruction_address() const; 372 373 int offset() const; 374 375 void set_offset(int x); 376 377 void add_offset_in_bytes(int add_offset) { set_offset ( ( offset() + add_offset ) ); } 378 379 void verify(); 380 void print (); 381 382 // unit test stuff 383 static void test() {} 384 385 private: 386 inline friend NativeMovRegMem* nativeMovRegMem_at (address address); 387 }; 388 389 inline NativeMovRegMem* nativeMovRegMem_at (address address) { 390 NativeMovRegMem* test = (NativeMovRegMem*)(address - NativeMovRegMem::instruction_offset); 391 #ifdef ASSERT 392 test->verify(); 393 #endif 394 return test; 395 } 396 397 398 // An interface for accessing/manipulating native leal instruction of form: 399 // leal reg, [reg + offset] 400 401 class NativeLoadAddress: public NativeMovRegMem { 402 #ifdef AMD64 403 static const bool has_rex = true; 404 static const int rex_size = 1; 405 #else 406 static const bool has_rex = false; 407 static const int rex_size = 0; 408 #endif // AMD64 409 public: 410 enum Intel_specific_constants { 411 instruction_prefix_wide = Assembler::REX_W, 412 instruction_prefix_wide_extended = Assembler::REX_WB, 413 lea_instruction_code = 0x8D, 414 mov64_instruction_code = 0xB8 415 }; 416 417 void verify(); 418 void print (); 419 420 // unit test stuff 421 static void test() {} 422 423 private: 424 friend NativeLoadAddress* nativeLoadAddress_at (address address) { 425 NativeLoadAddress* test = (NativeLoadAddress*)(address - instruction_offset); 426 #ifdef ASSERT 427 test->verify(); 428 #endif 429 return test; 430 } 431 }; 432 433 // destination is rbx or rax 434 // mov rbx, [rip + offset] 435 class NativeLoadGot: public NativeInstruction { 436 #ifdef AMD64 437 static const bool has_rex = true; 438 static const int rex_size = 1; 439 #else 440 static const bool has_rex = false; 441 static const int rex_size = 0; 442 #endif 443 public: 444 enum Intel_specific_constants { 445 rex_prefix = 0x48, 446 instruction_code = 0x8b, 447 modrm_rbx_code = 0x1d, 448 modrm_rax_code = 0x05, 449 instruction_length = 6 + rex_size, 450 offset_offset = 2 + rex_size 451 }; 452 453 address instruction_address() const { return addr_at(0); } 454 address rip_offset_address() const { return addr_at(offset_offset); } 455 int rip_offset() const { return int_at(offset_offset); } 456 address return_address() const { return addr_at(instruction_length); } 457 address got_address() const { return return_address() + rip_offset(); } 458 address next_instruction_address() const { return return_address(); } 459 intptr_t data() const; 460 void set_data(intptr_t data) { 461 intptr_t *addr = (intptr_t *) got_address(); 462 *addr = data; 463 } 464 465 void verify() const; 466 private: 467 void report_and_fail() const; 468 }; 469 470 inline NativeLoadGot* nativeLoadGot_at(address addr) { 471 NativeLoadGot* load = (NativeLoadGot*) addr; 472 #ifdef ASSERT 473 load->verify(); 474 #endif 475 return load; 476 } 477 478 // jump rel32off 479 480 class NativeJump: public NativeInstruction { 481 public: 482 enum Intel_specific_constants { 483 instruction_code = 0xe9, 484 instruction_size = 5, 485 instruction_offset = 0, 486 data_offset = 1, 487 next_instruction_offset = 5 488 }; 489 490 address instruction_address() const { return addr_at(instruction_offset); } 491 address next_instruction_address() const { return addr_at(next_instruction_offset); } 492 address jump_destination() const { 493 address dest = (int_at(data_offset)+next_instruction_address()); 494 // 32bit used to encode unresolved jmp as jmp -1 495 // 64bit can't produce this so it used jump to self. 496 // Now 32bit and 64bit use jump to self as the unresolved address 497 // which the inline cache code (and relocs) know about 498 499 // return -1 if jump to self 500 dest = (dest == (address) this) ? (address) -1 : dest; 501 return dest; 502 } 503 504 void set_jump_destination(address dest) { 505 intptr_t val = dest - next_instruction_address(); 506 if (dest == (address) -1) { 507 val = -5; // jump to self 508 } 509 #ifdef AMD64 510 assert((labs(val) & 0xFFFFFFFF00000000) == 0 || dest == (address)-1, "must be 32bit offset or -1"); 511 #endif // AMD64 512 set_int_at(data_offset, (jint)val); 513 } 514 515 // Creation 516 inline friend NativeJump* nativeJump_at(address address); 517 518 void verify(); 519 520 // Unit testing stuff 521 static void test() {} 522 523 // Insertion of native jump instruction 524 static void insert(address code_pos, address entry); 525 // MT-safe insertion of native jump at verified method entry 526 static void check_verified_entry_alignment(address entry, address verified_entry); 527 static void patch_verified_entry(address entry, address verified_entry, address dest); 528 }; 529 530 inline NativeJump* nativeJump_at(address address) { 531 NativeJump* jump = (NativeJump*)(address - NativeJump::instruction_offset); 532 #ifdef ASSERT 533 jump->verify(); 534 #endif 535 return jump; 536 } 537 538 // far jump reg 539 class NativeFarJump: public NativeInstruction { 540 public: 541 address jump_destination() const; 542 543 // Creation 544 inline friend NativeFarJump* nativeFarJump_at(address address); 545 546 void verify(); 547 548 // Unit testing stuff 549 static void test() {} 550 551 }; 552 553 inline NativeFarJump* nativeFarJump_at(address address) { 554 NativeFarJump* jump = (NativeFarJump*)(address); 555 #ifdef ASSERT 556 jump->verify(); 557 #endif 558 return jump; 559 } 560 561 // Handles all kinds of jump on Intel. Long/far, conditional/unconditional 562 class NativeGeneralJump: public NativeInstruction { 563 public: 564 enum Intel_specific_constants { 565 // Constants does not apply, since the lengths and offsets depends on the actual jump 566 // used 567 // Instruction codes: 568 // Unconditional jumps: 0xE9 (rel32off), 0xEB (rel8off) 569 // Conditional jumps: 0x0F8x (rel32off), 0x7x (rel8off) 570 unconditional_long_jump = 0xe9, 571 unconditional_short_jump = 0xeb, 572 instruction_size = 5 573 }; 574 575 address instruction_address() const { return addr_at(0); } 576 address jump_destination() const; 577 578 // Creation 579 inline friend NativeGeneralJump* nativeGeneralJump_at(address address); 580 581 // Insertion of native general jump instruction 582 static void insert_unconditional(address code_pos, address entry); 583 static void replace_mt_safe(address instr_addr, address code_buffer); 584 585 void verify(); 586 }; 587 588 inline NativeGeneralJump* nativeGeneralJump_at(address address) { 589 NativeGeneralJump* jump = (NativeGeneralJump*)(address); 590 debug_only(jump->verify();) 591 return jump; 592 } 593 594 class NativeGotJump: public NativeInstruction { 595 public: 596 enum Intel_specific_constants { 597 instruction_code = 0xff, 598 instruction_offset = 0, 599 instruction_size = 6, 600 rip_offset = 2 601 }; 602 603 void verify() const; 604 address instruction_address() const { return addr_at(instruction_offset); } 605 address destination() const; 606 address return_address() const { return addr_at(instruction_size); } 607 int got_offset() const { return (jint) int_at(rip_offset); } 608 address got_address() const { return return_address() + got_offset(); } 609 address next_instruction_address() const { return addr_at(instruction_size); } 610 bool is_GotJump() const { return ubyte_at(0) == instruction_code; } 611 612 void set_jump_destination(address dest) { 613 address *got_entry = (address *) got_address(); 614 *got_entry = dest; 615 } 616 }; 617 618 inline NativeGotJump* nativeGotJump_at(address addr) { 619 NativeGotJump* jump = (NativeGotJump*)(addr); 620 debug_only(jump->verify()); 621 return jump; 622 } 623 624 class NativePopReg : public NativeInstruction { 625 public: 626 enum Intel_specific_constants { 627 instruction_code = 0x58, 628 instruction_size = 1, 629 instruction_offset = 0, 630 data_offset = 1, 631 next_instruction_offset = 1 632 }; 633 634 // Insert a pop instruction 635 static void insert(address code_pos, Register reg); 636 }; 637 638 639 class NativeIllegalInstruction: public NativeInstruction { 640 public: 641 enum Intel_specific_constants { 642 instruction_code = 0x0B0F, // Real byte order is: 0x0F, 0x0B 643 instruction_size = 2, 644 instruction_offset = 0, 645 next_instruction_offset = 2 646 }; 647 648 // Insert illegal opcode as specific address 649 static void insert(address code_pos); 650 }; 651 652 // return instruction that does not pop values of the stack 653 class NativeReturn: public NativeInstruction { 654 public: 655 enum Intel_specific_constants { 656 instruction_code = 0xC3, 657 instruction_size = 1, 658 instruction_offset = 0, 659 next_instruction_offset = 1 660 }; 661 }; 662 663 // return instruction that does pop values of the stack 664 class NativeReturnX: public NativeInstruction { 665 public: 666 enum Intel_specific_constants { 667 instruction_code = 0xC2, 668 instruction_size = 2, 669 instruction_offset = 0, 670 next_instruction_offset = 2 671 }; 672 }; 673 674 // Simple test vs memory 675 class NativeTstRegMem: public NativeInstruction { 676 public: 677 enum Intel_specific_constants { 678 instruction_rex_prefix_mask = 0xF0, 679 instruction_rex_prefix = Assembler::REX, 680 instruction_code_memXregl = 0x85, 681 modrm_mask = 0x38, // select reg from the ModRM byte 682 modrm_reg = 0x00 // rax 683 }; 684 }; 685 686 inline bool NativeInstruction::is_illegal() { return (short)int_at(0) == (short)NativeIllegalInstruction::instruction_code; } 687 inline bool NativeInstruction::is_call() { return ubyte_at(0) == NativeCall::instruction_code; } 688 inline bool NativeInstruction::is_call_reg() { return ubyte_at(0) == NativeCallReg::instruction_code || 689 (ubyte_at(1) == NativeCallReg::instruction_code && 690 (ubyte_at(0) == Assembler::REX || ubyte_at(0) == Assembler::REX_B)); } 691 inline bool NativeInstruction::is_return() { return ubyte_at(0) == NativeReturn::instruction_code || 692 ubyte_at(0) == NativeReturnX::instruction_code; } 693 inline bool NativeInstruction::is_jump() { return ubyte_at(0) == NativeJump::instruction_code || 694 ubyte_at(0) == 0xEB; /* short jump */ } 695 inline bool NativeInstruction::is_jump_reg() { 696 int pos = 0; 697 if (ubyte_at(0) == Assembler::REX_B) pos = 1; 698 return ubyte_at(pos) == 0xFF && (ubyte_at(pos + 1) & 0xF0) == 0xE0; 699 } 700 inline bool NativeInstruction::is_far_jump() { return is_mov_literal64(); } 701 inline bool NativeInstruction::is_cond_jump() { return (int_at(0) & 0xF0FF) == 0x800F /* long jump */ || 702 (ubyte_at(0) & 0xF0) == 0x70; /* short jump */ } 703 inline bool NativeInstruction::is_safepoint_poll() { 704 #ifdef AMD64 705 // Try decoding a near safepoint first: 706 if (ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl && 707 ubyte_at(1) == 0x05) { // 00 rax 101 708 address fault = addr_at(6) + int_at(2); 709 NOT_JVMCI(assert(!Assembler::is_polling_page_far(), "unexpected poll encoding");) 710 return os::is_poll_address(fault); 711 } 712 // Now try decoding a far safepoint: 713 // two cases, depending on the choice of the base register in the address. 714 if (((ubyte_at(0) & NativeTstRegMem::instruction_rex_prefix_mask) == NativeTstRegMem::instruction_rex_prefix && 715 ubyte_at(1) == NativeTstRegMem::instruction_code_memXregl && 716 (ubyte_at(2) & NativeTstRegMem::modrm_mask) == NativeTstRegMem::modrm_reg) || 717 ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl && 718 (ubyte_at(1) & NativeTstRegMem::modrm_mask) == NativeTstRegMem::modrm_reg) { 719 NOT_JVMCI(assert(Assembler::is_polling_page_far(), "unexpected poll encoding");) 720 return true; 721 } 722 return false; 723 #else 724 return ( ubyte_at(0) == NativeMovRegMem::instruction_code_mem2reg || 725 ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl ) && 726 (ubyte_at(1)&0xC7) == 0x05 && /* Mod R/M == disp32 */ 727 (os::is_poll_address((address)int_at(2))); 728 #endif // AMD64 729 } 730 731 inline bool NativeInstruction::is_mov_literal64() { 732 #ifdef AMD64 733 return ((ubyte_at(0) == Assembler::REX_W || ubyte_at(0) == Assembler::REX_WB) && 734 (ubyte_at(1) & (0xff ^ NativeMovConstReg::register_mask)) == 0xB8); 735 #else 736 return false; 737 #endif // AMD64 738 } 739 740 #endif // CPU_X86_VM_NATIVEINST_X86_HPP