1 /*
2 * Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2016 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
5893 * @param [in,out]crc Register containing the crc.
5894 * @param [in]val Register containing the byte to fold into the CRC.
5895 * @param [in]table Register containing the table of crc constants.
5896 *
5897 * uint32_t crc;
5898 * val = crc_table[(val ^ crc) & 0xFF];
5899 * crc = val ^ (crc >> 8);
5900 */
5901 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
5902 z_xr(val, crc);
5903 fold_byte_crc32(crc, val, table, val);
5904 }
5905
5906
5907 /**
5908 * @param crc register containing existing CRC (32-bit)
5909 * @param buf register pointing to input byte buffer (byte*)
5910 * @param len register containing number of bytes
5911 * @param table register pointing to CRC table
5912 */
5913 void MacroAssembler::update_byteLoop_crc32(Register crc, Register buf, Register len, Register table,
5914 Register data, bool invertCRC) {
5915 assert_different_registers(crc, buf, len, table, data);
5916
5917 Label L_mainLoop, L_done;
5918 const int mainLoop_stepping = 1;
5919
5920 // Process all bytes in a single-byte loop.
5921 z_ltr(len, len);
5922 z_brnh(L_done);
5923
5924 if (invertCRC) {
5925 not_(crc, noreg, false); // ~c
5926 }
5927
5928 bind(L_mainLoop);
5929 z_llgc(data, Address(buf, (intptr_t)0));// Current byte of input buffer (zero extended). Avoids garbage in upper half of register.
5930 add2reg(buf, mainLoop_stepping); // Advance buffer position.
5931 update_byte_crc32(crc, data, table);
5932 z_brct(len, L_mainLoop); // Iterate.
5933
5934 if (invertCRC) {
5935 not_(crc, noreg, false); // ~c
5936 }
5937
5938 bind(L_done);
5939 }
5940
5941 /**
5942 * Emits code to update CRC-32 with a 4-byte value according to constants in table.
5943 * Implementation according to jdk/src/share/native/java/util/zip/zlib-1.2.8/crc32.c.
5944 *
5945 */
5946 void MacroAssembler::update_1word_crc32(Register crc, Register buf, Register table, int bufDisp, int bufInc,
5947 Register t0, Register t1, Register t2, Register t3) {
5948 // This is what we implement (the DOBIG4 part):
5949 //
5950 // #define DOBIG4 c ^= *++buf4; \
5951 // c = crc_table[4][c & 0xff] ^ crc_table[5][(c >> 8) & 0xff] ^ \
5952 // crc_table[6][(c >> 16) & 0xff] ^ crc_table[7][c >> 24]
5953 // #define DOBIG32 DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4
5954 const int ix0 = 4*(4*CRC32_COLUMN_SIZE);
5955 const int ix1 = 5*(4*CRC32_COLUMN_SIZE);
5956 const int ix2 = 6*(4*CRC32_COLUMN_SIZE);
5957 const int ix3 = 7*(4*CRC32_COLUMN_SIZE);
5958
5959 // XOR crc with next four bytes of buffer.
5960 lgr_if_needed(t0, crc);
5961 z_x(t0, Address(buf, bufDisp));
5962 if (bufInc != 0) {
5963 add2reg(buf, bufInc);
5964 }
5965
5966 // Chop crc into 4 single-byte pieces, shifted left 2 bits, to form the table indices.
5967 rotate_then_insert(t3, t0, 56-2, 63-2, 2, true); // ((c >> 0) & 0xff) << 2
5968 rotate_then_insert(t2, t0, 56-2, 63-2, 2-8, true); // ((c >> 8) & 0xff) << 2
5969 rotate_then_insert(t1, t0, 56-2, 63-2, 2-16, true); // ((c >> 16) & 0xff) << 2
5970 rotate_then_insert(t0, t0, 56-2, 63-2, 2-24, true); // ((c >> 24) & 0xff) << 2
5971
5972 // Load pre-calculated table values.
5973 // Use columns 4..7 for big-endian.
5974 z_ly(t3, Address(table, t3, (intptr_t)ix0));
5975 z_ly(t2, Address(table, t2, (intptr_t)ix1));
5976 z_ly(t1, Address(table, t1, (intptr_t)ix2));
5977 z_ly(t0, Address(table, t0, (intptr_t)ix3));
5978
5979 // Calculate new crc from table values.
5980 z_xr(t2, t3);
5981 z_xr(t0, t1);
5982 z_xr(t0, t2); // Now crc contains the final checksum value.
5983 lgr_if_needed(crc, t0);
5984 }
5985
5986 /**
5987 * @param crc register containing existing CRC (32-bit)
5988 * @param buf register pointing to input byte buffer (byte*)
5989 * @param len register containing number of bytes
5990 * @param table register pointing to CRC table
5991 *
5992 * uses Z_R10..Z_R13 as work register. Must be saved/restored by caller!
5993 */
5994 void MacroAssembler::kernel_crc32_2word(Register crc, Register buf, Register len, Register table,
5995 Register t0, Register t1, Register t2, Register t3) {
5996 assert_different_registers(crc, buf, len, table);
5997
5998 Label L_mainLoop, L_tail;
5999 Register data = t0;
6000 Register ctr = Z_R0;
6001 const int mainLoop_stepping = 8;
6002 const int tailLoop_stepping = 1;
6003 const int log_stepping = exact_log2(mainLoop_stepping);
6004
6005 // Don't test for len <= 0 here. This pathological case should not occur anyway.
6006 // Optimizing for it by adding a test and a branch seems to be a waste of CPU cycles.
6007 // The situation itself is detected and handled correctly by the conditional branches
6008 // following aghi(len, -stepping) and aghi(len, +stepping).
6009
6010 not_(crc, noreg, false); // 1s complement of crc
6011
6012 #if 0
6013 {
6014 // Pre-mainLoop alignment did not show any positive effect on performance.
6015 // We leave the code in for reference. Maybe the vector instructions in z13 depend on alignment.
6016
6017 z_cghi(len, mainLoop_stepping); // Alignment is useless for short data streams.
6018 z_brnh(L_tail);
6019
6020 // Align buf to word (4-byte) boundary.
6021 z_lcr(ctr, buf);
6022 rotate_then_insert(ctr, ctr, 62, 63, 0, true); // TODO: should set cc
6023 z_sgfr(len, ctr); // Remaining len after alignment.
6024
6025 update_byteLoop_crc32(crc, buf, ctr, table, data, false);
6026 }
6027 #endif
6028
6029 // Check for short (<mainLoop_stepping bytes) buffer.
6030 z_srag(ctr, len, log_stepping);
6031 z_brnh(L_tail);
6032
6033 z_lrvr(crc, crc); // Revert byte order because we are dealing with big-endian data.
6034 rotate_then_insert(len, len, 64-log_stepping, 63, 0, true); // #bytes for tailLoop
6035
6036 BIND(L_mainLoop);
6037 update_1word_crc32(crc, buf, table, 0, 0, crc, t1, t2, t3);
6038 update_1word_crc32(crc, buf, table, 4, mainLoop_stepping, crc, t1, t2, t3);
6039 z_brct(ctr, L_mainLoop); // Iterate.
6040
6041 z_lrvr(crc, crc); // Revert byte order back to original.
6042
6043 // Process last few (<8) bytes of buffer.
6044 BIND(L_tail);
6045 update_byteLoop_crc32(crc, buf, len, table, data, false);
6046
6047 not_(crc, noreg, false); // 1s complement of crc
6048 }
6049
6050 /**
6051 * @param crc register containing existing CRC (32-bit)
6052 * @param buf register pointing to input byte buffer (byte*)
6053 * @param len register containing number of bytes
6054 * @param table register pointing to CRC table
6055 *
6056 * uses Z_R10..Z_R13 as work register. Must be saved/restored by caller!
6057 */
6058 void MacroAssembler::kernel_crc32_1word(Register crc, Register buf, Register len, Register table,
6059 Register t0, Register t1, Register t2, Register t3) {
6060 assert_different_registers(crc, buf, len, table);
6061
6062 Label L_mainLoop, L_tail;
6063 Register data = t0;
6064 Register ctr = Z_R0;
6065 const int mainLoop_stepping = 4;
6066 const int log_stepping = exact_log2(mainLoop_stepping);
6067
6068 // Don't test for len <= 0 here. This pathological case should not occur anyway.
6069 // Optimizing for it by adding a test and a branch seems to be a waste of CPU cycles.
6070 // The situation itself is detected and handled correctly by the conditional branches
6071 // following aghi(len, -stepping) and aghi(len, +stepping).
6072
6073 not_(crc, noreg, false); // 1s complement of crc
6074
6075 // Check for short (<4 bytes) buffer.
6076 z_srag(ctr, len, log_stepping);
6077 z_brnh(L_tail);
6078
6079 z_lrvr(crc, crc); // Revert byte order because we are dealing with big-endian data.
6080 rotate_then_insert(len, len, 64-log_stepping, 63, 0, true); // #bytes for tailLoop
6081
6082 BIND(L_mainLoop);
6083 update_1word_crc32(crc, buf, table, 0, mainLoop_stepping, crc, t1, t2, t3);
6084 z_brct(ctr, L_mainLoop); // Iterate.
6085 z_lrvr(crc, crc); // Revert byte order back to original.
6086
6087 // Process last few (<8) bytes of buffer.
6088 BIND(L_tail);
6089 update_byteLoop_crc32(crc, buf, len, table, data, false);
6090
6091 not_(crc, noreg, false); // 1s complement of crc
6092 }
6093
6094 /**
6095 * @param crc register containing existing CRC (32-bit)
6096 * @param buf register pointing to input byte buffer (byte*)
6097 * @param len register containing number of bytes
6098 * @param table register pointing to CRC table
6099 */
6100 void MacroAssembler::kernel_crc32_1byte(Register crc, Register buf, Register len, Register table,
6101 Register t0, Register t1, Register t2, Register t3) {
6102 assert_different_registers(crc, buf, len, table);
6103 Register data = t0;
6104
6105 update_byteLoop_crc32(crc, buf, len, table, data, true);
6106 }
6107
6108 void MacroAssembler::kernel_crc32_singleByte(Register crc, Register buf, Register len, Register table, Register tmp) {
6109 assert_different_registers(crc, buf, len, table, tmp);
6110
6111 not_(crc, noreg, false); // ~c
6112
6113 z_llgc(tmp, Address(buf, (intptr_t)0)); // Current byte of input buffer (zero extended). Avoids garbage in upper half of register.
6114 update_byte_crc32(crc, tmp, table);
6115
6116 not_(crc, noreg, false); // ~c
6117 }
6118
6119 //
6120 // Code for BigInteger::multiplyToLen() intrinsic.
6121 //
6122
6123 // dest_lo += src1 + src2
6124 // dest_hi += carry1 + carry2
6125 // Z_R7 is destroyed !
6126 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo,
6127 Register src1, Register src2) {
6128 clear_reg(Z_R7);
6129 z_algr(dest_lo, src1);
6130 z_alcgr(dest_hi, Z_R7);
6131 z_algr(dest_lo, src2);
6132 z_alcgr(dest_hi, Z_R7);
6133 }
6134
6135 // Multiply 64 bit by 64 bit first loop.
6136 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart,
|
1 /*
2 * Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2016, 2017, SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
5893 * @param [in,out]crc Register containing the crc.
5894 * @param [in]val Register containing the byte to fold into the CRC.
5895 * @param [in]table Register containing the table of crc constants.
5896 *
5897 * uint32_t crc;
5898 * val = crc_table[(val ^ crc) & 0xFF];
5899 * crc = val ^ (crc >> 8);
5900 */
5901 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
5902 z_xr(val, crc);
5903 fold_byte_crc32(crc, val, table, val);
5904 }
5905
5906
5907 /**
5908 * @param crc register containing existing CRC (32-bit)
5909 * @param buf register pointing to input byte buffer (byte*)
5910 * @param len register containing number of bytes
5911 * @param table register pointing to CRC table
5912 */
5913 void MacroAssembler::update_byteLoop_crc32(Register crc, Register buf, Register len, Register table, Register data) {
5914 assert_different_registers(crc, buf, len, table, data);
5915
5916 Label L_mainLoop, L_done;
5917 const int mainLoop_stepping = 1;
5918
5919 // Process all bytes in a single-byte loop.
5920 z_ltr(len, len);
5921 z_brnh(L_done);
5922
5923 bind(L_mainLoop);
5924 z_llgc(data, Address(buf, (intptr_t)0));// Current byte of input buffer (zero extended). Avoids garbage in upper half of register.
5925 add2reg(buf, mainLoop_stepping); // Advance buffer position.
5926 update_byte_crc32(crc, data, table);
5927 z_brct(len, L_mainLoop); // Iterate.
5928
5929 bind(L_done);
5930 }
5931
5932 /**
5933 * Emits code to update CRC-32 with a 4-byte value according to constants in table.
5934 * Implementation according to jdk/src/share/native/java/util/zip/zlib-1.2.8/crc32.c.
5935 *
5936 */
5937 void MacroAssembler::update_1word_crc32(Register crc, Register buf, Register table, int bufDisp, int bufInc,
5938 Register t0, Register t1, Register t2, Register t3) {
5939 // This is what we implement (the DOBIG4 part):
5940 //
5941 // #define DOBIG4 c ^= *++buf4; \
5942 // c = crc_table[4][c & 0xff] ^ crc_table[5][(c >> 8) & 0xff] ^ \
5943 // crc_table[6][(c >> 16) & 0xff] ^ crc_table[7][c >> 24]
5944 // #define DOBIG32 DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4
5945 // Pre-calculate (constant) column offsets, use columns 4..7 for big-endian.
5946 const int ix0 = 4*(4*CRC32_COLUMN_SIZE);
5947 const int ix1 = 5*(4*CRC32_COLUMN_SIZE);
5948 const int ix2 = 6*(4*CRC32_COLUMN_SIZE);
5949 const int ix3 = 7*(4*CRC32_COLUMN_SIZE);
5950
5951 // XOR crc with next four bytes of buffer.
5952 lgr_if_needed(t0, crc);
5953 z_x(t0, Address(buf, bufDisp));
5954 if (bufInc != 0) {
5955 add2reg(buf, bufInc);
5956 }
5957
5958 // Chop crc into 4 single-byte pieces, shifted left 2 bits, to form the table indices.
5959 rotate_then_insert(t3, t0, 56-2, 63-2, 2, true); // ((c >> 0) & 0xff) << 2
5960 rotate_then_insert(t2, t0, 56-2, 63-2, 2-8, true); // ((c >> 8) & 0xff) << 2
5961 rotate_then_insert(t1, t0, 56-2, 63-2, 2-16, true); // ((c >> 16) & 0xff) << 2
5962 rotate_then_insert(t0, t0, 56-2, 63-2, 2-24, true); // ((c >> 24) & 0xff) << 2
5963
5964 // XOR indexed table values to calculate updated crc.
5965 z_ly(t2, Address(table, t2, (intptr_t)ix1));
5966 z_ly(t0, Address(table, t0, (intptr_t)ix3));
5967 z_xy(t2, Address(table, t3, (intptr_t)ix0));
5968 z_xy(t0, Address(table, t1, (intptr_t)ix2));
5969 z_xr(t0, t2); // Now t0 contains the updated CRC value.
5970 lgr_if_needed(crc, t0);
5971 }
5972
5973 /**
5974 * @param crc register containing existing CRC (32-bit)
5975 * @param buf register pointing to input byte buffer (byte*)
5976 * @param len register containing number of bytes
5977 * @param table register pointing to CRC table
5978 *
5979 * uses Z_R10..Z_R13 as work register. Must be saved/restored by caller!
5980 */
5981 void MacroAssembler::kernel_crc32_2word(Register crc, Register buf, Register len, Register table,
5982 Register t0, Register t1, Register t2, Register t3,
5983 bool invertCRC) {
5984 assert_different_registers(crc, buf, len, table);
5985
5986 Label L_mainLoop, L_tail;
5987 Register data = t0;
5988 Register ctr = Z_R0;
5989 const int mainLoop_stepping = 8;
5990 const int tailLoop_stepping = 1;
5991 const int log_stepping = exact_log2(mainLoop_stepping);
5992
5993 // Don't test for len <= 0 here. This pathological case should not occur anyway.
5994 // Optimizing for it by adding a test and a branch seems to be a waste of CPU cycles.
5995 // The situation itself is detected and handled correctly by the conditional branches
5996 // following aghi(len, -stepping) and aghi(len, +stepping).
5997
5998 if (invertCRC) {
5999 not_(crc, noreg, false); // 1s complement of crc
6000 }
6001
6002 #if 0
6003 {
6004 // Pre-mainLoop alignment did not show any positive effect on performance.
6005 // We leave the code in for reference. Maybe the vector instructions in z13 depend on alignment.
6006
6007 z_cghi(len, mainLoop_stepping); // Alignment is useless for short data streams.
6008 z_brnh(L_tail);
6009
6010 // Align buf to word (4-byte) boundary.
6011 z_lcr(ctr, buf);
6012 rotate_then_insert(ctr, ctr, 62, 63, 0, true); // TODO: should set cc
6013 z_sgfr(len, ctr); // Remaining len after alignment.
6014
6015 update_byteLoop_crc32(crc, buf, ctr, table, data);
6016 }
6017 #endif
6018
6019 // Check for short (<mainLoop_stepping bytes) buffer.
6020 z_srag(ctr, len, log_stepping);
6021 z_brnh(L_tail);
6022
6023 z_lrvr(crc, crc); // Revert byte order because we are dealing with big-endian data.
6024 rotate_then_insert(len, len, 64-log_stepping, 63, 0, true); // #bytes for tailLoop
6025
6026 BIND(L_mainLoop);
6027 update_1word_crc32(crc, buf, table, 0, 0, crc, t1, t2, t3);
6028 update_1word_crc32(crc, buf, table, 4, mainLoop_stepping, crc, t1, t2, t3);
6029 z_brct(ctr, L_mainLoop); // Iterate.
6030
6031 z_lrvr(crc, crc); // Revert byte order back to original.
6032
6033 // Process last few (<8) bytes of buffer.
6034 BIND(L_tail);
6035 update_byteLoop_crc32(crc, buf, len, table, data);
6036
6037 if (invertCRC) {
6038 not_(crc, noreg, false); // 1s complement of crc
6039 }
6040 }
6041
6042 /**
6043 * @param crc register containing existing CRC (32-bit)
6044 * @param buf register pointing to input byte buffer (byte*)
6045 * @param len register containing number of bytes
6046 * @param table register pointing to CRC table
6047 *
6048 * uses Z_R10..Z_R13 as work register. Must be saved/restored by caller!
6049 */
6050 void MacroAssembler::kernel_crc32_1word(Register crc, Register buf, Register len, Register table,
6051 Register t0, Register t1, Register t2, Register t3,
6052 bool invertCRC) {
6053 assert_different_registers(crc, buf, len, table);
6054
6055 Label L_mainLoop, L_tail;
6056 Register data = t0;
6057 Register ctr = Z_R0;
6058 const int mainLoop_stepping = 4;
6059 const int log_stepping = exact_log2(mainLoop_stepping);
6060
6061 // Don't test for len <= 0 here. This pathological case should not occur anyway.
6062 // Optimizing for it by adding a test and a branch seems to be a waste of CPU cycles.
6063 // The situation itself is detected and handled correctly by the conditional branches
6064 // following aghi(len, -stepping) and aghi(len, +stepping).
6065
6066 if (invertCRC) {
6067 not_(crc, noreg, false); // 1s complement of crc
6068 }
6069
6070 // Check for short (<4 bytes) buffer.
6071 z_srag(ctr, len, log_stepping);
6072 z_brnh(L_tail);
6073
6074 z_lrvr(crc, crc); // Revert byte order because we are dealing with big-endian data.
6075 rotate_then_insert(len, len, 64-log_stepping, 63, 0, true); // #bytes for tailLoop
6076
6077 BIND(L_mainLoop);
6078 update_1word_crc32(crc, buf, table, 0, mainLoop_stepping, crc, t1, t2, t3);
6079 z_brct(ctr, L_mainLoop); // Iterate.
6080
6081 z_lrvr(crc, crc); // Revert byte order back to original.
6082
6083 // Process last few (<8) bytes of buffer.
6084 BIND(L_tail);
6085 update_byteLoop_crc32(crc, buf, len, table, data);
6086
6087 if (invertCRC) {
6088 not_(crc, noreg, false); // 1s complement of crc
6089 }
6090 }
6091
6092 /**
6093 * @param crc register containing existing CRC (32-bit)
6094 * @param buf register pointing to input byte buffer (byte*)
6095 * @param len register containing number of bytes
6096 * @param table register pointing to CRC table
6097 */
6098 void MacroAssembler::kernel_crc32_1byte(Register crc, Register buf, Register len, Register table,
6099 Register t0, Register t1, Register t2, Register t3,
6100 bool invertCRC) {
6101 assert_different_registers(crc, buf, len, table);
6102 Register data = t0;
6103
6104 if (invertCRC) {
6105 not_(crc, noreg, false); // 1s complement of crc
6106 }
6107
6108 update_byteLoop_crc32(crc, buf, len, table, data);
6109
6110 if (invertCRC) {
6111 not_(crc, noreg, false); // 1s complement of crc
6112 }
6113 }
6114
6115 void MacroAssembler::kernel_crc32_singleByte(Register crc, Register buf, Register len, Register table, Register tmp,
6116 bool invertCRC) {
6117 assert_different_registers(crc, buf, len, table, tmp);
6118
6119 if (invertCRC) {
6120 not_(crc, noreg, false); // 1s complement of crc
6121 }
6122
6123 z_llgc(tmp, Address(buf, (intptr_t)0)); // Current byte of input buffer (zero extended). Avoids garbage in upper half of register.
6124 update_byte_crc32(crc, tmp, table);
6125
6126 if (invertCRC) {
6127 not_(crc, noreg, false); // 1s complement of crc
6128 }
6129 }
6130
6131 void MacroAssembler::kernel_crc32_singleByteReg(Register crc, Register val, Register table,
6132 bool invertCRC) {
6133 assert_different_registers(crc, val, table);
6134
6135 if (invertCRC) {
6136 not_(crc, noreg, false); // 1s complement of crc
6137 }
6138
6139 update_byte_crc32(crc, val, table);
6140
6141 if (invertCRC) {
6142 not_(crc, noreg, false); // 1s complement of crc
6143 }
6144 }
6145
6146 //
6147 // Code for BigInteger::multiplyToLen() intrinsic.
6148 //
6149
6150 // dest_lo += src1 + src2
6151 // dest_hi += carry1 + carry2
6152 // Z_R7 is destroyed !
6153 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo,
6154 Register src1, Register src2) {
6155 clear_reg(Z_R7);
6156 z_algr(dest_lo, src1);
6157 z_alcgr(dest_hi, Z_R7);
6158 z_algr(dest_lo, src2);
6159 z_alcgr(dest_hi, Z_R7);
6160 }
6161
6162 // Multiply 64 bit by 64 bit first loop.
6163 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart,
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