1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2016 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
155 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
156 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
157 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
158 } else {
159 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
160 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
161 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
162 }
163
164 assert(AllocatePrefetchLines > 0, "invalid value");
165 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
166 AllocatePrefetchLines = 1; // Conservative value.
167 }
168
169 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
170 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
171 }
172
173 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
174
175 // Implementation does not use any of the vector instructions
176 // available with Power8. Their exploitation is still pending.
177 if (!UseCRC32Intrinsics) {
178 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
179 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
180 }
181 }
182
183 if (UseCRC32CIntrinsics) {
184 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics))
185 warning("CRC32C intrinsics are not available on this CPU");
186 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
187 }
188
189 // The AES intrinsic stubs require AES instruction support.
190 #if defined(VM_LITTLE_ENDIAN)
191 if (has_vcipher()) {
192 if (FLAG_IS_DEFAULT(UseAES)) {
193 UseAES = true;
194 }
195 } else if (UseAES) {
196 if (!FLAG_IS_DEFAULT(UseAES))
197 warning("AES instructions are not available on this CPU");
198 FLAG_SET_DEFAULT(UseAES, false);
199 }
200
201 if (UseAES && has_vcipher()) {
202 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
203 UseAESIntrinsics = true;
204 }
205 } else if (UseAESIntrinsics) {
206 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
226 }
227
228 if (UseGHASHIntrinsics) {
229 warning("GHASH intrinsics are not available on this CPU");
230 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
231 }
232
233 if (FLAG_IS_DEFAULT(UseFMA)) {
234 FLAG_SET_DEFAULT(UseFMA, true);
235 }
236
237 if (UseSHA) {
238 warning("SHA instructions are not available on this CPU");
239 FLAG_SET_DEFAULT(UseSHA, false);
240 }
241 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
242 warning("SHA intrinsics are not available on this CPU");
243 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
244 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
245 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
246 }
247
248 if (UseAdler32Intrinsics) {
249 warning("Adler32Intrinsics not available on this CPU.");
250 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
251 }
252
253 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
254 UseMultiplyToLenIntrinsic = true;
255 }
256 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
257 UseMontgomeryMultiplyIntrinsic = true;
258 }
259 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
260 UseMontgomerySquareIntrinsic = true;
261 }
262
263 if (UseVectorizedMismatchIntrinsic) {
264 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
265 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
266 }
267
268
269 // Adjust RTM (Restricted Transactional Memory) flags.
270 if (UseRTMLocking) {
|
1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2017, SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
155 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
156 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
157 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
158 } else {
159 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
160 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
161 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
162 }
163
164 assert(AllocatePrefetchLines > 0, "invalid value");
165 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
166 AllocatePrefetchLines = 1; // Conservative value.
167 }
168
169 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
170 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
171 }
172
173 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
174
175 // If defined(VM_LITTLE_ENDIAN) and running on Power8 or newer hardware,
176 // the implementation uses the vector instructions available with Power8.
177 // In all other cases, the implementation uses only generally available instructions.
178 if (!UseCRC32Intrinsics) {
179 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
180 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
181 }
182 }
183
184 // Implementation does not use any of the vector instructions available with Power8.
185 // Their exploitation is still pending (aka "work in progress").
186 if (!UseCRC32CIntrinsics) {
187 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
188 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
189 }
190 }
191
192 // TODO: Provide implementation.
193 if (UseAdler32Intrinsics) {
194 warning("Adler32Intrinsics not available on this CPU.");
195 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
196 }
197
198 // The AES intrinsic stubs require AES instruction support.
199 #if defined(VM_LITTLE_ENDIAN)
200 if (has_vcipher()) {
201 if (FLAG_IS_DEFAULT(UseAES)) {
202 UseAES = true;
203 }
204 } else if (UseAES) {
205 if (!FLAG_IS_DEFAULT(UseAES))
206 warning("AES instructions are not available on this CPU");
207 FLAG_SET_DEFAULT(UseAES, false);
208 }
209
210 if (UseAES && has_vcipher()) {
211 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
212 UseAESIntrinsics = true;
213 }
214 } else if (UseAESIntrinsics) {
215 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
235 }
236
237 if (UseGHASHIntrinsics) {
238 warning("GHASH intrinsics are not available on this CPU");
239 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
240 }
241
242 if (FLAG_IS_DEFAULT(UseFMA)) {
243 FLAG_SET_DEFAULT(UseFMA, true);
244 }
245
246 if (UseSHA) {
247 warning("SHA instructions are not available on this CPU");
248 FLAG_SET_DEFAULT(UseSHA, false);
249 }
250 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
251 warning("SHA intrinsics are not available on this CPU");
252 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
253 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
254 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
255 }
256
257 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
258 UseMultiplyToLenIntrinsic = true;
259 }
260 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
261 UseMontgomeryMultiplyIntrinsic = true;
262 }
263 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
264 UseMontgomerySquareIntrinsic = true;
265 }
266
267 if (UseVectorizedMismatchIntrinsic) {
268 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
269 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
270 }
271
272
273 // Adjust RTM (Restricted Transactional Memory) flags.
274 if (UseRTMLocking) {
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