1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2016 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "runtime/java.hpp"
32 #include "runtime/os.hpp"
33 #include "runtime/stubCodeGenerator.hpp"
34 #include "utilities/defaultStream.hpp"
35 #include "utilities/globalDefinitions.hpp"
36 #include "vm_version_ppc.hpp"
37
38 # include <sys/sysinfo.h>
39
40 bool VM_Version::_is_determine_features_test_running = false;
41 uint64_t VM_Version::_dscr_val = 0;
42
43 #define MSG(flag) \
44 if (flag && !FLAG_IS_DEFAULT(flag)) \
45 jio_fprintf(defaultStream::error_stream(), \
46 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
47 " -XX:+" #flag " will be disabled!\n");
48
49 void VM_Version::initialize() {
50
51 // Test which instructions are supported and measure cache line size.
52 determine_features();
53
54 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
55 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
56 if (VM_Version::has_lqarx()) {
57 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
58 } else if (VM_Version::has_popcntw()) {
59 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
60 } else if (VM_Version::has_cmpb()) {
61 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
62 } else if (VM_Version::has_popcntb()) {
63 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
64 } else {
65 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
66 }
67 }
68
69 bool PowerArchitecturePPC64_ok = false;
70 switch (PowerArchitecturePPC64) {
71 case 8: if (!VM_Version::has_lqarx() ) break;
72 case 7: if (!VM_Version::has_popcntw()) break;
73 case 6: if (!VM_Version::has_cmpb() ) break;
74 case 5: if (!VM_Version::has_popcntb()) break;
75 case 0: PowerArchitecturePPC64_ok = true; break;
76 default: break;
77 }
78 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
79 UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
80
81 // Power 8: Configure Data Stream Control Register.
82 if (has_mfdscr()) {
83 config_dscr();
84 }
85
86 if (!UseSIGTRAP) {
87 MSG(TrapBasedICMissChecks);
88 MSG(TrapBasedNotEntrantChecks);
89 MSG(TrapBasedNullChecks);
90 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
91 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false);
92 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false);
93 }
94
95 #ifdef COMPILER2
96 if (!UseSIGTRAP) {
97 MSG(TrapBasedRangeChecks);
98 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
99 }
100
101 // On Power6 test for section size.
102 if (PowerArchitecturePPC64 == 6) {
103 determine_section_size();
104 // TODO: PPC port } else {
105 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
106 }
107
108 MaxVectorSize = 8;
109 #endif
110
111 // Create and print feature-string.
112 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
113 jio_snprintf(buf, sizeof(buf),
114 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
115 (has_fsqrt() ? " fsqrt" : ""),
116 (has_isel() ? " isel" : ""),
117 (has_lxarxeh() ? " lxarxeh" : ""),
118 (has_cmpb() ? " cmpb" : ""),
119 //(has_mftgpr()? " mftgpr" : ""),
120 (has_popcntb() ? " popcntb" : ""),
121 (has_popcntw() ? " popcntw" : ""),
122 (has_fcfids() ? " fcfids" : ""),
123 (has_vand() ? " vand" : ""),
124 (has_lqarx() ? " lqarx" : ""),
125 (has_vcipher() ? " aes" : ""),
126 (has_vpmsumb() ? " vpmsumb" : ""),
127 (has_tcheck() ? " tcheck" : ""),
128 (has_mfdscr() ? " mfdscr" : ""),
129 (has_vsx() ? " vsx" : "")
130 // Make sure number of %s matches num_features!
131 );
132 _features_string = os::strdup(buf);
133 if (Verbose) {
134 print_features();
135 }
136
137 // PPC64 supports 8-byte compare-exchange operations (see
138 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)
139 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
140 _supports_cx8 = true;
141
142 // Used by C1.
143 _supports_atomic_getset4 = true;
144 _supports_atomic_getadd4 = true;
145 _supports_atomic_getset8 = true;
146 _supports_atomic_getadd8 = true;
147
148 UseSSE = 0; // Only on x86 and x64
149
150 intx cache_line_size = L1_data_cache_line_size();
151
152 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
153
154 if (AllocatePrefetchStyle == 4) {
155 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
156 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
157 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
158 } else {
159 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
160 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
161 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
162 }
163
164 assert(AllocatePrefetchLines > 0, "invalid value");
165 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
166 AllocatePrefetchLines = 1; // Conservative value.
167 }
168
169 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
170 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
171 }
172
173 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
174
175 // Implementation does not use any of the vector instructions
176 // available with Power8. Their exploitation is still pending.
177 if (!UseCRC32Intrinsics) {
178 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
179 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
180 }
181 }
182
183 if (UseCRC32CIntrinsics) {
184 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics))
185 warning("CRC32C intrinsics are not available on this CPU");
186 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
187 }
188
189 // The AES intrinsic stubs require AES instruction support.
190 #if defined(VM_LITTLE_ENDIAN)
191 if (has_vcipher()) {
192 if (FLAG_IS_DEFAULT(UseAES)) {
193 UseAES = true;
194 }
195 } else if (UseAES) {
196 if (!FLAG_IS_DEFAULT(UseAES))
197 warning("AES instructions are not available on this CPU");
198 FLAG_SET_DEFAULT(UseAES, false);
199 }
200
201 if (UseAES && has_vcipher()) {
202 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
203 UseAESIntrinsics = true;
204 }
205 } else if (UseAESIntrinsics) {
206 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
207 warning("AES intrinsics are not available on this CPU");
208 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
209 }
210
211 #else
212 if (UseAES) {
213 warning("AES instructions are not available on this CPU");
214 FLAG_SET_DEFAULT(UseAES, false);
215 }
216 if (UseAESIntrinsics) {
217 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
218 warning("AES intrinsics are not available on this CPU");
219 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
220 }
221 #endif
222
223 if (UseAESCTRIntrinsics) {
224 warning("AES/CTR intrinsics are not available on this CPU");
225 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
226 }
227
228 if (UseGHASHIntrinsics) {
229 warning("GHASH intrinsics are not available on this CPU");
230 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
231 }
232
233 if (FLAG_IS_DEFAULT(UseFMA)) {
234 FLAG_SET_DEFAULT(UseFMA, true);
235 }
236
237 if (UseSHA) {
238 warning("SHA instructions are not available on this CPU");
239 FLAG_SET_DEFAULT(UseSHA, false);
240 }
241 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
242 warning("SHA intrinsics are not available on this CPU");
243 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
244 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
245 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
246 }
247
248 if (UseAdler32Intrinsics) {
249 warning("Adler32Intrinsics not available on this CPU.");
250 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
251 }
252
253 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
254 UseMultiplyToLenIntrinsic = true;
255 }
256 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
257 UseMontgomeryMultiplyIntrinsic = true;
258 }
259 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
260 UseMontgomerySquareIntrinsic = true;
261 }
262
263 if (UseVectorizedMismatchIntrinsic) {
264 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
265 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
266 }
267
268
269 // Adjust RTM (Restricted Transactional Memory) flags.
270 if (UseRTMLocking) {
271 // If CPU or OS are too old:
272 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
273 // setting during arguments processing. See use_biased_locking().
274 // VM_Version_init() is executed after UseBiasedLocking is used
275 // in Thread::allocate().
276 if (!has_tcheck()) {
277 vm_exit_during_initialization("RTM instructions are not available on this CPU");
278 }
279 bool os_too_old = true;
280 #ifdef AIX
281 // Actually, this is supported since AIX 7.1.. Unfortunately, this first
282 // contained bugs, so that it can only be enabled after AIX 7.1.3.30.
283 // The Java property os.version, which is used in RTM tests to decide
284 // whether the feature is available, only knows major and minor versions.
285 // We don't want to change this property, as user code might depend on it.
286 // So the tests can not check on subversion 3.30, and we only enable RTM
287 // with AIX 7.2.
288 if (os::Aix::os_version() >= 0x07020000) { // At least AIX 7.2.
289 os_too_old = false;
290 }
291 #endif
292 #ifdef LINUX
293 // At least Linux kernel 4.2, as the problematic behavior of syscalls
294 // being called in the middle of a transaction has been addressed.
295 // Please, refer to commit b4b56f9ecab40f3b4ef53e130c9f6663be491894
296 // in Linux kernel source tree: https://goo.gl/Kc5i7A
297 if (os::Linux::os_version_is_known()) {
298 if (os::Linux::os_version() >= 0x040200)
299 os_too_old = false;
300 } else {
301 vm_exit_during_initialization("RTM can not be enabled: kernel version is unknown.");
302 }
303 #endif
304 if (os_too_old) {
305 vm_exit_during_initialization("RTM is not supported on this OS version.");
306 }
307 }
308
309 if (UseRTMLocking) {
310 #if INCLUDE_RTM_OPT
311 if (!UnlockExperimentalVMOptions) {
312 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. "
313 "It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
314 } else {
315 warning("UseRTMLocking is only available as experimental option on this platform.");
316 }
317 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
318 // RTM locking should be used only for applications with
319 // high lock contention. For now we do not use it by default.
320 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
321 }
322 if (!is_power_of_2(RTMTotalCountIncrRate)) {
323 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64");
324 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64);
325 }
326 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) {
327 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50");
328 FLAG_SET_DEFAULT(RTMAbortRatio, 50);
329 }
330 if (RTMSpinLoopCount < 0) {
331 warning("RTMSpinLoopCount must not be a negative value, resetting it to 0");
332 FLAG_SET_DEFAULT(RTMSpinLoopCount, 0);
333 }
334 #else
335 // Only C2 does RTM locking optimization.
336 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
337 // setting during arguments processing. See use_biased_locking().
338 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
339 #endif
340 } else { // !UseRTMLocking
341 if (UseRTMForStackLocks) {
342 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
343 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
344 }
345 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
346 }
347 if (UseRTMDeopt) {
348 FLAG_SET_DEFAULT(UseRTMDeopt, false);
349 }
350 if (PrintPreciseRTMLockingStatistics) {
351 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
352 }
353 }
354
355 // This machine allows unaligned memory accesses
356 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
357 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
358 }
359 }
360
361 bool VM_Version::use_biased_locking() {
362 #if INCLUDE_RTM_OPT
363 // RTM locking is most useful when there is high lock contention and
364 // low data contention. With high lock contention the lock is usually
365 // inflated and biased locking is not suitable for that case.
366 // RTM locking code requires that biased locking is off.
367 // Note: we can't switch off UseBiasedLocking in get_processor_features()
368 // because it is used by Thread::allocate() which is called before
369 // VM_Version::initialize().
370 if (UseRTMLocking && UseBiasedLocking) {
371 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
372 FLAG_SET_DEFAULT(UseBiasedLocking, false);
373 } else {
374 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
375 UseBiasedLocking = false;
376 }
377 }
378 #endif
379 return UseBiasedLocking;
380 }
381
382 void VM_Version::print_features() {
383 tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size());
384 }
385
386 #ifdef COMPILER2
387 // Determine section size on power6: If section size is 8 instructions,
388 // there should be a difference between the two testloops of ~15 %. If
389 // no difference is detected the section is assumed to be 32 instructions.
390 void VM_Version::determine_section_size() {
391
392 int unroll = 80;
393
394 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
395
396 // Allocate space for the code.
397 ResourceMark rm;
398 CodeBuffer cb("detect_section_size", code_size, 0);
399 MacroAssembler* a = new MacroAssembler(&cb);
400
401 uint32_t *code = (uint32_t *)a->pc();
402 // Emit code.
403 void (*test1)() = (void(*)())(void *)a->function_entry();
404
405 Label l1;
406
407 a->li(R4, 1);
408 a->sldi(R4, R4, 28);
409 a->b(l1);
410 a->align(CodeEntryAlignment);
411
412 a->bind(l1);
413
414 for (int i = 0; i < unroll; i++) {
415 // Schleife 1
416 // ------- sector 0 ------------
417 // ;; 0
418 a->nop(); // 1
419 a->fpnop0(); // 2
420 a->fpnop1(); // 3
421 a->addi(R4,R4, -1); // 4
422
423 // ;; 1
424 a->nop(); // 5
425 a->fmr(F6, F6); // 6
426 a->fmr(F7, F7); // 7
427 a->endgroup(); // 8
428 // ------- sector 8 ------------
429
430 // ;; 2
431 a->nop(); // 9
432 a->nop(); // 10
433 a->fmr(F8, F8); // 11
434 a->fmr(F9, F9); // 12
435
436 // ;; 3
437 a->nop(); // 13
438 a->fmr(F10, F10); // 14
439 a->fmr(F11, F11); // 15
440 a->endgroup(); // 16
441 // -------- sector 16 -------------
442
443 // ;; 4
444 a->nop(); // 17
445 a->nop(); // 18
446 a->fmr(F15, F15); // 19
447 a->fmr(F16, F16); // 20
448
449 // ;; 5
450 a->nop(); // 21
451 a->fmr(F17, F17); // 22
452 a->fmr(F18, F18); // 23
453 a->endgroup(); // 24
454 // ------- sector 24 ------------
455
456 // ;; 6
457 a->nop(); // 25
458 a->nop(); // 26
459 a->fmr(F19, F19); // 27
460 a->fmr(F20, F20); // 28
461
462 // ;; 7
463 a->nop(); // 29
464 a->fmr(F21, F21); // 30
465 a->fmr(F22, F22); // 31
466 a->brnop0(); // 32
467
468 // ------- sector 32 ------------
469 }
470
471 // ;; 8
472 a->cmpdi(CCR0, R4, unroll); // 33
473 a->bge(CCR0, l1); // 34
474 a->blr();
475
476 // Emit code.
477 void (*test2)() = (void(*)())(void *)a->function_entry();
478 // uint32_t *code = (uint32_t *)a->pc();
479
480 Label l2;
481
482 a->li(R4, 1);
483 a->sldi(R4, R4, 28);
484 a->b(l2);
485 a->align(CodeEntryAlignment);
486
487 a->bind(l2);
488
489 for (int i = 0; i < unroll; i++) {
490 // Schleife 2
491 // ------- sector 0 ------------
492 // ;; 0
493 a->brnop0(); // 1
494 a->nop(); // 2
495 //a->cmpdi(CCR0, R4, unroll);
496 a->fpnop0(); // 3
497 a->fpnop1(); // 4
498 a->addi(R4,R4, -1); // 5
499
500 // ;; 1
501
502 a->nop(); // 6
503 a->fmr(F6, F6); // 7
504 a->fmr(F7, F7); // 8
505 // ------- sector 8 ---------------
506
507 // ;; 2
508 a->endgroup(); // 9
509
510 // ;; 3
511 a->nop(); // 10
512 a->nop(); // 11
513 a->fmr(F8, F8); // 12
514
515 // ;; 4
516 a->fmr(F9, F9); // 13
517 a->nop(); // 14
518 a->fmr(F10, F10); // 15
519
520 // ;; 5
521 a->fmr(F11, F11); // 16
522 // -------- sector 16 -------------
523
524 // ;; 6
525 a->endgroup(); // 17
526
527 // ;; 7
528 a->nop(); // 18
529 a->nop(); // 19
530 a->fmr(F15, F15); // 20
531
532 // ;; 8
533 a->fmr(F16, F16); // 21
534 a->nop(); // 22
535 a->fmr(F17, F17); // 23
536
537 // ;; 9
538 a->fmr(F18, F18); // 24
539 // -------- sector 24 -------------
540
541 // ;; 10
542 a->endgroup(); // 25
543
544 // ;; 11
545 a->nop(); // 26
546 a->nop(); // 27
547 a->fmr(F19, F19); // 28
548
549 // ;; 12
550 a->fmr(F20, F20); // 29
551 a->nop(); // 30
552 a->fmr(F21, F21); // 31
553
554 // ;; 13
555 a->fmr(F22, F22); // 32
556 }
557
558 // -------- sector 32 -------------
559 // ;; 14
560 a->cmpdi(CCR0, R4, unroll); // 33
561 a->bge(CCR0, l2); // 34
562
563 a->blr();
564 uint32_t *code_end = (uint32_t *)a->pc();
565 a->flush();
566
567 double loop1_seconds,loop2_seconds, rel_diff;
568 uint64_t start1, stop1;
569
570 start1 = os::current_thread_cpu_time(false);
571 (*test1)();
572 stop1 = os::current_thread_cpu_time(false);
573 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
574
575
576 start1 = os::current_thread_cpu_time(false);
577 (*test2)();
578 stop1 = os::current_thread_cpu_time(false);
579
580 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
581
582 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
583
584 if (PrintAssembly) {
585 ttyLocker ttyl;
586 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
587 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
588 tty->print_cr("Time loop1 :%f", loop1_seconds);
589 tty->print_cr("Time loop2 :%f", loop2_seconds);
590 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
591
592 if (rel_diff > 12.0) {
593 tty->print_cr("Section Size 8 Instructions");
594 } else{
595 tty->print_cr("Section Size 32 Instructions or Power5");
596 }
597 }
598
599 #if 0 // TODO: PPC port
600 // Set sector size (if not set explicitly).
601 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
602 if (rel_diff > 12.0) {
603 PdScheduling::power6SectorSize = 0x20;
604 } else {
605 PdScheduling::power6SectorSize = 0x80;
606 }
607 } else if (Power6SectorSize128PPC64) {
608 PdScheduling::power6SectorSize = 0x80;
609 } else {
610 PdScheduling::power6SectorSize = 0x20;
611 }
612 #endif
613 if (UsePower6SchedulerPPC64) Unimplemented();
614 }
615 #endif // COMPILER2
616
617 void VM_Version::determine_features() {
618 #if defined(ABI_ELFv2)
619 // 1 InstWord per call for the blr instruction.
620 const int code_size = (num_features+1+2*1)*BytesPerInstWord;
621 #else
622 // 7 InstWords for each call (function descriptor + blr instruction).
623 const int code_size = (num_features+1+2*7)*BytesPerInstWord;
624 #endif
625 int features = 0;
626
627 // create test area
628 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
629 char test_area[BUFFER_SIZE];
630 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
631
632 // Allocate space for the code.
633 ResourceMark rm;
634 CodeBuffer cb("detect_cpu_features", code_size, 0);
635 MacroAssembler* a = new MacroAssembler(&cb);
636
637 // Must be set to true so we can generate the test code.
638 _features = VM_Version::all_features_m;
639
640 // Emit code.
641 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
642 uint32_t *code = (uint32_t *)a->pc();
643 // Don't use R0 in ldarx.
644 // Keep R3_ARG1 unmodified, it contains &field (see below).
645 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
646 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
647 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
648 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
649 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
650 a->cmpb(R7, R5, R6); // code[4] -> cmpb
651 a->popcntb(R7, R5); // code[5] -> popcntb
652 a->popcntw(R7, R5); // code[6] -> popcntw
653 a->fcfids(F3, F4); // code[7] -> fcfids
654 a->vand(VR0, VR0, VR0); // code[8] -> vand
655 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
656 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
657 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
658 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
659 a->tcheck(0); // code[12] -> tcheck
660 a->mfdscr(R0); // code[13] -> mfdscr
661 a->lxvd2x(VSR0, R3_ARG1); // code[14] -> vsx
662 a->blr();
663
664 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
665 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
666 a->dcbz(R3_ARG1); // R3_ARG1 = addr
667 a->blr();
668
669 uint32_t *code_end = (uint32_t *)a->pc();
670 a->flush();
671 _features = VM_Version::unknown_m;
672
673 // Print the detection code.
674 if (PrintAssembly) {
675 ttyLocker ttyl;
676 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
677 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
678 }
679
680 // Measure cache line size.
681 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
682 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
683 int count = 0; // count zeroed bytes
684 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
685 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
686 _L1_data_cache_line_size = count;
687
688 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
689 VM_Version::_is_determine_features_test_running = true;
690 // We must align the first argument to 16 bytes because of the lqarx check.
691 (*test)((address)align_size_up((intptr_t)mid_of_test_area, 16), (uint64_t)0);
692 VM_Version::_is_determine_features_test_running = false;
693
694 // determine which instructions are legal.
695 int feature_cntr = 0;
696 if (code[feature_cntr++]) features |= fsqrt_m;
697 if (code[feature_cntr++]) features |= fsqrts_m;
698 if (code[feature_cntr++]) features |= isel_m;
699 if (code[feature_cntr++]) features |= lxarxeh_m;
700 if (code[feature_cntr++]) features |= cmpb_m;
701 if (code[feature_cntr++]) features |= popcntb_m;
702 if (code[feature_cntr++]) features |= popcntw_m;
703 if (code[feature_cntr++]) features |= fcfids_m;
704 if (code[feature_cntr++]) features |= vand_m;
705 if (code[feature_cntr++]) features |= lqarx_m;
706 if (code[feature_cntr++]) features |= vcipher_m;
707 if (code[feature_cntr++]) features |= vpmsumb_m;
708 if (code[feature_cntr++]) features |= tcheck_m;
709 if (code[feature_cntr++]) features |= mfdscr_m;
710 if (code[feature_cntr++]) features |= vsx_m;
711
712 // Print the detection code.
713 if (PrintAssembly) {
714 ttyLocker ttyl;
715 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
716 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
717 }
718
719 _features = features;
720 }
721
722 // Power 8: Configure Data Stream Control Register.
723 void VM_Version::config_dscr() {
724 // 7 InstWords for each call (function descriptor + blr instruction).
725 const int code_size = (2+2*7)*BytesPerInstWord;
726
727 // Allocate space for the code.
728 ResourceMark rm;
729 CodeBuffer cb("config_dscr", code_size, 0);
730 MacroAssembler* a = new MacroAssembler(&cb);
731
732 // Emit code.
733 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
734 uint32_t *code = (uint32_t *)a->pc();
735 a->mfdscr(R3);
736 a->blr();
737
738 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
739 a->mtdscr(R3);
740 a->blr();
741
742 uint32_t *code_end = (uint32_t *)a->pc();
743 a->flush();
744
745 // Print the detection code.
746 if (PrintAssembly) {
747 ttyLocker ttyl;
748 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
749 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
750 }
751
752 // Apply the configuration if needed.
753 _dscr_val = (*get_dscr)();
754 if (Verbose) {
755 tty->print_cr("dscr value was 0x%lx" , _dscr_val);
756 }
757 bool change_requested = false;
758 if (DSCR_PPC64 != (uintx)-1) {
759 _dscr_val = DSCR_PPC64;
760 change_requested = true;
761 }
762 if (DSCR_DPFD_PPC64 <= 7) {
763 uint64_t mask = 0x7;
764 if ((_dscr_val & mask) != DSCR_DPFD_PPC64) {
765 _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64);
766 change_requested = true;
767 }
768 }
769 if (DSCR_URG_PPC64 <= 7) {
770 uint64_t mask = 0x7 << 6;
771 if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
772 _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
773 change_requested = true;
774 }
775 }
776 if (change_requested) {
777 (*set_dscr)(_dscr_val);
778 if (Verbose) {
779 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
780 }
781 }
782 }
783
784 static uint64_t saved_features = 0;
785
786 void VM_Version::allow_all() {
787 saved_features = _features;
788 _features = all_features_m;
789 }
790
791 void VM_Version::revert() {
792 _features = saved_features;
793 }