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src/hotspot/cpu/s390/assembler_s390.hpp

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   1 /*
   2  * Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2016 SAP SE. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *


 233     return a;
 234   }
 235 
 236   // A call to this is generated by adlc for replacement variable $xxx$$Address.
 237   static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
 238 
 239   bool is_same_address(Address a) const {
 240     return _base == a._base && _index == a._index && _disp == a._disp;
 241   }
 242 
 243   // testers
 244   bool has_base()  const { return _base  != noreg; }
 245   bool has_index() const { return _index != noreg; }
 246   bool has_disp()  const { return true; } // There is no "invalid" value.
 247 
 248   bool is_disp12() const { return Immediate::is_uimm12(disp()); }
 249   bool is_disp20() const { return Immediate::is_simm20(disp()); }
 250   bool is_RSform()  { return has_base() && !has_index() && is_disp12(); }
 251   bool is_RSYform() { return has_base() && !has_index() && is_disp20(); }
 252   bool is_RXform()  { return has_base() &&  has_index() && is_disp12(); }
 253   bool is_RXEform() { return has_base() &&  has_index() && is_disp12(); }
 254   bool is_RXYform() { return has_base() &&  has_index() && is_disp20(); }
 255 
 256   bool uses(Register r) { return _base == r || _index == r; };
 257 
 258   // accessors
 259   Register base()      const { return _base; }
 260   Register baseOrR0()  const { assert(_base  != Z_R0, ""); return _base  == noreg ? Z_R0 : _base; }
 261   Register index()     const { return _index; }
 262   Register indexOrR0() const { assert(_index != Z_R0, ""); return _index == noreg ? Z_R0 : _index; }
 263   intptr_t disp() const { return _disp; }
 264   // Specific version for short displacement instructions.
 265   int      disp12() const {
 266     assert(is_disp12(), "displacement out of range for uimm12");
 267     return _disp;
 268   }
 269   // Specific version for long displacement instructions.
 270   int      disp20() const {
 271     assert(is_disp20(), "displacement out of range for simm20");
 272     return _disp;
 273   }


1076 #define OI_ZOPC     (unsigned  int)(0x96  << 24)
1077 #define OIY_ZOPC    (unsigned long)(0xebL << 40 | 0x56L)
1078 #define OC_ZOPC     (unsigned long)(0xd6L << 40)
1079 
1080 // XOR
1081 #define XI_ZOPC     (unsigned  int)(0x97  << 24)
1082 #define XIY_ZOPC    (unsigned long)(0xebL << 40 | 0x57L)
1083 #define XC_ZOPC     (unsigned long)(0xd7L << 40)
1084 
1085 // Search String
1086 #define SRST_ZOPC   (unsigned  int)(178 << 24 | 94 << 16)
1087 #define SRSTU_ZOPC  (unsigned  int)(185 << 24 | 190 << 16)
1088 
1089 // Translate characters
1090 #define TROO_ZOPC   (unsigned  int)(0xb9 << 24 | 0x93 << 16)
1091 #define TROT_ZOPC   (unsigned  int)(0xb9 << 24 | 0x92 << 16)
1092 #define TRTO_ZOPC   (unsigned  int)(0xb9 << 24 | 0x91 << 16)
1093 #define TRTT_ZOPC   (unsigned  int)(0xb9 << 24 | 0x90 << 16)
1094 
1095 
1096 // Miscellaneous Operations



























































































































































































1097 
1098 // Execute
1099 #define EX_ZOPC     (unsigned  int)(68L << 24)
1100 #define EXRL_ZOPC   (unsigned long)(0xc6L << 40 | 0x00L << 32)  // z10
1101 
1102 // Compare and Swap
1103 #define CS_ZOPC     (unsigned  int)(0xba << 24)
1104 #define CSY_ZOPC    (unsigned long)(0xebL << 40 | 0x14L)
1105 #define CSG_ZOPC    (unsigned long)(0xebL << 40 | 0x30L)
1106 
1107 // Interlocked-Update
1108 #define LAA_ZOPC    (unsigned long)(0xebL << 40 | 0xf8L)         // z196
1109 #define LAAG_ZOPC   (unsigned long)(0xebL << 40 | 0xe8L)         // z196
1110 #define LAAL_ZOPC   (unsigned long)(0xebL << 40 | 0xfaL)         // z196
1111 #define LAALG_ZOPC  (unsigned long)(0xebL << 40 | 0xeaL)         // z196
1112 #define LAN_ZOPC    (unsigned long)(0xebL << 40 | 0xf4L)         // z196
1113 #define LANG_ZOPC   (unsigned long)(0xebL << 40 | 0xe4L)         // z196
1114 #define LAX_ZOPC    (unsigned long)(0xebL << 40 | 0xf7L)         // z196
1115 #define LAXG_ZOPC   (unsigned long)(0xebL << 40 | 0xe7L)         // z196
1116 #define LAO_ZOPC    (unsigned long)(0xebL << 40 | 0xf6L)         // z196


1263     // z/Architecture
1264     negative         = 0,
1265     less             = 0,
1266     positive         = 1,
1267     greater          = 1,
1268     zero             = 2,
1269     equal            = 2,
1270     summary_overflow = 3,
1271   };
1272 
1273   // Rounding mode for float-2-int conversions.
1274   enum RoundingMode {
1275     current_mode      = 0,   // Mode taken from FPC register.
1276     biased_to_nearest = 1,
1277     to_nearest        = 4,
1278     to_zero           = 5,
1279     to_plus_infinity  = 6,
1280     to_minus_infinity = 7
1281   };
1282 















1283   // Inverse condition code, i.e. determine "15 - cc" for a given condition code cc.
1284   static branch_condition inverse_condition(branch_condition cc);
1285   static branch_condition inverse_float_condition(branch_condition cc);
1286 
1287 
1288   //-----------------------------------------------
1289   // instruction property getter methods
1290   //-----------------------------------------------
1291 
1292   // Calculate length of instruction.
1293   static int instr_len(unsigned char *instr);
1294 
1295   // Longest instructions are 6 bytes on z/Architecture.
1296   static int instr_maxlen() { return 6; }
1297 
1298   // Average instruction is 4 bytes on z/Architecture (just a guess).
1299   static int instr_avglen() { return 4; }
1300 
1301   // Shortest instructions are 2 bytes on z/Architecture.
1302   static int instr_minlen() { return 2; }


1359   static int z_inv_op(int  x) { return inv_u_field(x, 31, 24); }
1360   static int z_inv_op(long x) { return inv_u_field(x, 47, 40); }
1361 
1362   static int inv_reg( long x, int s, int len) { return inv_u_field(x, (len-s)-1, (len-s)-4); }  // Regs are encoded in 4 bits.
1363   static int inv_mask(long x, int s, int len) { return inv_u_field(x, (len-s)-1, (len-s)-8); }  // Mask is 8 bits long.
1364   static int inv_simm16_48(long x) { return (inv_s_field(x, 31, 16)); }                         // 6-byte instructions only
1365   static int inv_simm16(long x)    { return (inv_s_field(x, 15,  0)); }                         // 4-byte instructions only
1366   static int inv_simm20(long x)    { return (inv_u_field(x, 27, 16) |                           // 6-byte instructions only
1367                                              inv_s_field(x, 15, 8)<<12); }
1368   static int inv_simm32(long x)    { return (inv_s_field(x, 31,  0)); }                         // 6-byte instructions only
1369   static int inv_uimm12(long x)    { return (inv_u_field(x, 11,  0)); }                         // 4-byte instructions only
1370 
1371   // Encode u_field from long value.
1372   static long u_field(long x, int hi_bit, int lo_bit) {
1373     long r = x << lo_bit;
1374     assert((r & ~fmask(hi_bit, lo_bit))   == 0, "value out of range");
1375     assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
1376     return r;
1377   }
1378 






















































1379  public:
1380 
1381   //--------------------------------------------------
1382   // instruction field construction methods
1383   //--------------------------------------------------
1384 
1385   // Compute relative address (32 bit) for branch.
1386   // Only used once in nativeInst_s390.cpp.
1387   static intptr_t z_pcrel_off(address dest, address pc) {
1388     return RelAddr::pcrel_off32(dest, pc);
1389   }
1390 
1391   // Extract 20-bit signed displacement.
1392   // Only used in disassembler_s390.cpp for temp enhancements.
1393   static int inv_simm20_xx(address iLoc) {
1394     unsigned long instr = 0;
1395     unsigned long iLen  = get_instruction(iLoc, &instr);
1396     return inv_simm20(instr);
1397   }
1398 


1436 
1437   static long uimm4( int64_t ui4,  int s, int len) { return uimm(ui4,   4) << (len-s-4);  }
1438   static long uimm6( int64_t ui6,  int s, int len) { return uimm(ui6,   6) << (len-s-6);  }
1439   static long uimm8( int64_t ui8,  int s, int len) { return uimm(ui8,   8) << (len-s-8);  }
1440   static long uimm12(int64_t ui12, int s, int len) { return uimm(ui12, 12) << (len-s-12); }
1441   static long uimm16(int64_t ui16, int s, int len) { return uimm(ui16, 16) << (len-s-16); }
1442   static long uimm32(int64_t ui32, int s, int len) { return uimm((unsigned)ui32, 32) << (len-s-32); } // prevent sign extension
1443 
1444   static long simm8( int64_t si8,  int s, int len) { return simm(si8,   8) << (len-s-8);  }
1445   static long simm12(int64_t si12, int s, int len) { return simm(si12, 12) << (len-s-12); }
1446   static long simm16(int64_t si16, int s, int len) { return simm(si16, 16) << (len-s-16); }
1447   static long simm24(int64_t si24, int s, int len) { return simm(si24, 24) << (len-s-24); }
1448   static long simm32(int64_t si32, int s, int len) { return simm(si32, 32) << (len-s-32); }
1449 
1450   static long imm8( int64_t i8,  int s, int len)   { return imm(i8,   8) << (len-s-8);  }
1451   static long imm12(int64_t i12, int s, int len)   { return imm(i12, 12) << (len-s-12); }
1452   static long imm16(int64_t i16, int s, int len)   { return imm(i16, 16) << (len-s-16); }
1453   static long imm24(int64_t i24, int s, int len)   { return imm(i24, 24) << (len-s-24); }
1454   static long imm32(int64_t i32, int s, int len)   { return imm(i32, 32) << (len-s-32); }
1455 


1456   static long fregt(FloatRegister r, int s, int len) { return freg(r,s,len); }
1457   static long freg( FloatRegister r, int s, int len) { return u_field(r->encoding(), (len-s)-1, (len-s)-4); }
1458 
1459   // Rounding mode for float-2-int conversions.
1460   static long rounding_mode(RoundingMode m, int s, int len) {
1461     assert(m != 2 && m != 3, "invalid mode");
1462     return uimm(m, 4) << (len-s-4);
1463   }
1464 
1465   //--------------------------------------------
1466   // instruction field getter methods
1467   //--------------------------------------------
1468 
1469   static int get_imm32(address a, int instruction_number) {
1470     int imm;
1471     int *p =((int *)(a + 2 + 6 * instruction_number));
1472     imm = *p;
1473     return imm;
1474   }
1475 


2106 
2107   inline void z_stfle(int64_t d2, Register b2);                            // store facility list extended
2108 
2109   inline void z_nc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);// and *(d1+b1) = *(d1+l+b1) & *(d2+b2) ; d1, d2: uimm12, ands l+1 bytes
2110   inline void z_oc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);//  or *(d1+b1) = *(d1+l+b1) | *(d2+b2) ; d1, d2: uimm12,  ors l+1 bytes
2111   inline void z_xc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);// xor *(d1+b1) = *(d1+l+b1) ^ *(d2+b2) ; d1, d2: uimm12, xors l+1 bytes
2112   inline void z_nc(Address dst, int64_t len, Address src2);                     // and *dst = *dst & *src2, ands len bytes in memory
2113   inline void z_oc(Address dst, int64_t len, Address src2);                     //  or *dst = *dst | *src2,  ors len bytes in memory
2114   inline void z_xc(Address dst, int64_t len, Address src2);                     // xor *dst = *dst ^ *src2, xors len bytes in memory
2115 
2116   // compare instructions
2117   inline void z_clc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);  // compare (*(d1_uimm12+b1), *(d1_uimm12+b1)) ; compare l bytes
2118   inline void z_clcle(Register r1, Register r3, int64_t d2, Register b2);  // compare logical long extended, see docu
2119   inline void z_clclu(Register r1, Register r3, int64_t d2, Register b2);  // compare logical long unicode, see docu
2120 
2121   // Translate characters
2122   inline void z_troo(Register r1, Register r2, int64_t m3);
2123   inline void z_trot(Register r1, Register r2, int64_t m3);
2124   inline void z_trto(Register r1, Register r2, int64_t m3);
2125   inline void z_trtt(Register r1, Register r2, int64_t m3);







































































































































































































































































































































































































2126 
2127 
2128   // Floatingpoint instructions
2129   // ==========================
2130 
2131   // compare instructions
2132   inline void z_cebr(FloatRegister r1, FloatRegister r2);                     // compare (r1, r2)                ; float
2133   inline void z_ceb(FloatRegister r1, int64_t d2, Register x2, Register b2);  // compare (r1, *(d2_imm12+x2+b2)) ; float
2134   inline void z_ceb(FloatRegister r1, const Address &a);                      // compare (r1, *(d2_imm12+x2+b2)) ; float
2135   inline void z_cdbr(FloatRegister r1, FloatRegister r2);                     // compare (r1, r2)                ; double
2136   inline void z_cdb(FloatRegister r1, int64_t d2, Register x2, Register b2);  // compare (r1, *(d2_imm12+x2+b2)) ; double
2137   inline void z_cdb(FloatRegister r1, const Address &a);                      // compare (r1, *(d2_imm12+x2+b2)) ; double
2138 
2139   // load instructions
2140   inline void z_le( FloatRegister r1, int64_t d2, Register x2, Register b2);   // load r1 = *(d2_uimm12+x2+b2) ; float
2141   inline void z_ley(FloatRegister r1, int64_t d2, Register x2, Register b2);   // load r1 = *(d2_imm20+x2+b2)  ; float
2142   inline void z_ld( FloatRegister r1, int64_t d2, Register x2, Register b2);   // load r1 = *(d2_uimm12+x2+b2) ; double
2143   inline void z_ldy(FloatRegister r1, int64_t d2, Register x2, Register b2);   // load r1 = *(d2_imm20+x2+b2)  ; double
2144   inline void z_le( FloatRegister r1, const Address &a);                       // load r1 = *(a)               ; float
2145   inline void z_ley(FloatRegister r1, const Address &a);                       // load r1 = *(a)               ; float


   1 /*
   2  * Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2016, 2017 SAP SE. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *


 233     return a;
 234   }
 235 
 236   // A call to this is generated by adlc for replacement variable $xxx$$Address.
 237   static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
 238 
 239   bool is_same_address(Address a) const {
 240     return _base == a._base && _index == a._index && _disp == a._disp;
 241   }
 242 
 243   // testers
 244   bool has_base()  const { return _base  != noreg; }
 245   bool has_index() const { return _index != noreg; }
 246   bool has_disp()  const { return true; } // There is no "invalid" value.
 247 
 248   bool is_disp12() const { return Immediate::is_uimm12(disp()); }
 249   bool is_disp20() const { return Immediate::is_simm20(disp()); }
 250   bool is_RSform()  { return has_base() && !has_index() && is_disp12(); }
 251   bool is_RSYform() { return has_base() && !has_index() && is_disp20(); }
 252   bool is_RXform()  { return has_base() &&  has_index() && is_disp12(); }

 253   bool is_RXYform() { return has_base() &&  has_index() && is_disp20(); }
 254 
 255   bool uses(Register r) { return _base == r || _index == r; };
 256 
 257   // accessors
 258   Register base()      const { return _base; }
 259   Register baseOrR0()  const { assert(_base  != Z_R0, ""); return _base  == noreg ? Z_R0 : _base; }
 260   Register index()     const { return _index; }
 261   Register indexOrR0() const { assert(_index != Z_R0, ""); return _index == noreg ? Z_R0 : _index; }
 262   intptr_t disp() const { return _disp; }
 263   // Specific version for short displacement instructions.
 264   int      disp12() const {
 265     assert(is_disp12(), "displacement out of range for uimm12");
 266     return _disp;
 267   }
 268   // Specific version for long displacement instructions.
 269   int      disp20() const {
 270     assert(is_disp20(), "displacement out of range for simm20");
 271     return _disp;
 272   }


1075 #define OI_ZOPC     (unsigned  int)(0x96  << 24)
1076 #define OIY_ZOPC    (unsigned long)(0xebL << 40 | 0x56L)
1077 #define OC_ZOPC     (unsigned long)(0xd6L << 40)
1078 
1079 // XOR
1080 #define XI_ZOPC     (unsigned  int)(0x97  << 24)
1081 #define XIY_ZOPC    (unsigned long)(0xebL << 40 | 0x57L)
1082 #define XC_ZOPC     (unsigned long)(0xd7L << 40)
1083 
1084 // Search String
1085 #define SRST_ZOPC   (unsigned  int)(178 << 24 | 94 << 16)
1086 #define SRSTU_ZOPC  (unsigned  int)(185 << 24 | 190 << 16)
1087 
1088 // Translate characters
1089 #define TROO_ZOPC   (unsigned  int)(0xb9 << 24 | 0x93 << 16)
1090 #define TROT_ZOPC   (unsigned  int)(0xb9 << 24 | 0x92 << 16)
1091 #define TRTO_ZOPC   (unsigned  int)(0xb9 << 24 | 0x91 << 16)
1092 #define TRTT_ZOPC   (unsigned  int)(0xb9 << 24 | 0x90 << 16)
1093 
1094 
1095 //---------------------------
1096 //--  Vector Instructions  --
1097 //---------------------------
1098 
1099 //---<  Vector Support Instructions  >---
1100 
1101 //---  Load (memory)  ---
1102 
1103 #define VLM_ZOPC    (unsigned long)(0xe7L << 40 | 0x36L << 0)   // load full vreg range (n * 128 bit)
1104 #define VL_ZOPC     (unsigned long)(0xe7L << 40 | 0x06L << 0)   // load full vreg (128 bit)
1105 #define VLEB_ZOPC   (unsigned long)(0xe7L << 40 | 0x00L << 0)   // load vreg element (8 bit)
1106 #define VLEH_ZOPC   (unsigned long)(0xe7L << 40 | 0x01L << 0)   // load vreg element (16 bit)
1107 #define VLEF_ZOPC   (unsigned long)(0xe7L << 40 | 0x03L << 0)   // load vreg element (32 bit)
1108 #define VLEG_ZOPC   (unsigned long)(0xe7L << 40 | 0x02L << 0)   // load vreg element (64 bit)
1109 
1110 #define VLREP_ZOPC  (unsigned long)(0xe7L << 40 | 0x05L << 0)   // load and replicate into all vector elements
1111 #define VLLEZ_ZOPC  (unsigned long)(0xe7L << 40 | 0x04L << 0)   // load logical element and zero.
1112 
1113 // vector register gather
1114 #define VGEF_ZOPC   (unsigned long)(0xe7L << 40 | 0x13L << 0)   // gather element (32 bit), V1(M3) = [D2(V2(M3),B2)]
1115 #define VGEG_ZOPC   (unsigned long)(0xe7L << 40 | 0x12L << 0)   // gather element (64 bit), V1(M3) = [D2(V2(M3),B2)]
1116 // vector register scatter
1117 #define VSCEF_ZOPC  (unsigned long)(0xe7L << 40 | 0x1bL << 0)   // vector scatter element FW
1118 #define VSCEG_ZOPC  (unsigned long)(0xe7L << 40 | 0x1aL << 0)   // vector scatter element DW
1119 
1120 #define VLBB_ZOPC   (unsigned long)(0xe7L << 40 | 0x07L << 0)   // load vreg to block boundary (load to alignment).
1121 #define VLL_ZOPC    (unsigned long)(0xe7L << 40 | 0x37L << 0)   // load vreg with length.
1122 
1123 //---  Load (register)  ---
1124 
1125 #define VLR_ZOPC    (unsigned long)(0xe7L << 40 | 0x56L << 0)   // copy full vreg (128 bit)
1126 #define VLGV_ZOPC   (unsigned long)(0xe7L << 40 | 0x21L << 0)   // copy vreg element -> GR
1127 #define VLVG_ZOPC   (unsigned long)(0xe7L << 40 | 0x22L << 0)   // copy GR -> vreg element
1128 #define VLVGP_ZOPC  (unsigned long)(0xe7L << 40 | 0x62L << 0)   // copy GR2, GR3 (disjoint pair) -> vreg
1129 
1130 // vector register pack: cut in half the size the source vector elements
1131 #define VPK_ZOPC    (unsigned long)(0xe7L << 40 | 0x94L << 0)   // just cut
1132 #define VPKS_ZOPC   (unsigned long)(0xe7L << 40 | 0x97L << 0)   // saturate as signed values
1133 #define VPKLS_ZOPC  (unsigned long)(0xe7L << 40 | 0x95L << 0)   // saturate as unsigned values
1134 
1135 // vector register unpack: double in size the source vector elements
1136 #define VUPH_ZOPC   (unsigned long)(0xe7L << 40 | 0xd7L << 0)   // signed, left half of the source vector elements
1137 #define VUPLH_ZOPC  (unsigned long)(0xe7L << 40 | 0xd5L << 0)   // unsigned, left half of the source vector elements
1138 #define VUPL_ZOPC   (unsigned long)(0xe7L << 40 | 0xd6L << 0)   // signed, right half of the source vector elements
1139 #define VUPLL_ZOPC  (unsigned long)(0xe7L << 40 | 0xd4L << 0)   // unsigned, right half of the source vector element
1140 
1141 // vector register merge
1142 #define VMRH_ZOPC   (unsigned long)(0xe7L << 40 | 0x61L << 0)   // register merge high (left half of source registers)
1143 #define VMRL_ZOPC   (unsigned long)(0xe7L << 40 | 0x60L << 0)   // register merge low (right half of source registers)
1144 
1145 // vector register permute
1146 #define VPERM_ZOPC  (unsigned long)(0xe7L << 40 | 0x8cL << 0)   // vector permute
1147 #define VPDI_ZOPC   (unsigned long)(0xe7L << 40 | 0x84L << 0)   // vector permute DW immediate
1148 
1149 // vector register replicate
1150 #define VREP_ZOPC   (unsigned long)(0xe7L << 40 | 0x4dL << 0)   // vector replicate
1151 #define VREPI_ZOPC  (unsigned long)(0xe7L << 40 | 0x45L << 0)   // vector replicate immediate
1152 #define VSEL_ZOPC   (unsigned long)(0xe7L << 40 | 0x8dL << 0)   // vector select
1153 
1154 #define VSEG_ZOPC   (unsigned long)(0xe7L << 40 | 0x5fL << 0)   // vector sign-extend to DW (rightmost element in each DW).
1155 
1156 //---  Load (immediate)  ---
1157 
1158 #define VLEIB_ZOPC  (unsigned long)(0xe7L << 40 | 0x40L << 0)   // load vreg element (16 bit imm to 8 bit)
1159 #define VLEIH_ZOPC  (unsigned long)(0xe7L << 40 | 0x41L << 0)   // load vreg element (16 bit imm to 16 bit)
1160 #define VLEIF_ZOPC  (unsigned long)(0xe7L << 40 | 0x43L << 0)   // load vreg element (16 bit imm to 32 bit)
1161 #define VLEIG_ZOPC  (unsigned long)(0xe7L << 40 | 0x42L << 0)   // load vreg element (16 bit imm to 64 bit)
1162 
1163 //---  Store  ---
1164 
1165 #define VSTM_ZOPC   (unsigned long)(0xe7L << 40 | 0x3eL << 0)   // store full vreg range (n * 128 bit)
1166 #define VST_ZOPC    (unsigned long)(0xe7L << 40 | 0x0eL << 0)   // store full vreg (128 bit)
1167 #define VSTEB_ZOPC  (unsigned long)(0xe7L << 40 | 0x08L << 0)   // store vreg element (8 bit)
1168 #define VSTEH_ZOPC  (unsigned long)(0xe7L << 40 | 0x09L << 0)   // store vreg element (16 bit)
1169 #define VSTEF_ZOPC  (unsigned long)(0xe7L << 40 | 0x0bL << 0)   // store vreg element (32 bit)
1170 #define VSTEG_ZOPC  (unsigned long)(0xe7L << 40 | 0x0aL << 0)   // store vreg element (64 bit)
1171 #define VSTL_ZOPC   (unsigned long)(0xe7L << 40 | 0x3fL << 0)   // store vreg with length.
1172 
1173 //---  Misc  ---
1174 
1175 #define VGM_ZOPC    (unsigned long)(0xe7L << 40 | 0x46L << 0)   // generate bit  mask, [start..end] = '1', else '0'
1176 #define VGBM_ZOPC   (unsigned long)(0xe7L << 40 | 0x44L << 0)   // generate byte mask, bits(imm16) -> bytes
1177 
1178 //---<  Vector Arithmetic Instructions  >---
1179 
1180 // Load
1181 #define VLC_ZOPC    (unsigned long)(0xe7L << 40 | 0xdeL << 0)   // V1 := -V2,   element size = 2**m
1182 #define VLP_ZOPC    (unsigned long)(0xe7L << 40 | 0xdfL << 0)   // V1 := |V2|,  element size = 2**m
1183 
1184 // ADD
1185 #define VA_ZOPC     (unsigned long)(0xe7L << 40 | 0xf3L << 0)   // V1 := V2 + V3, element size = 2**m
1186 #define VACC_ZOPC   (unsigned long)(0xe7L << 40 | 0xf1L << 0)   // V1 := carry(V2 + V3), element size = 2**m
1187 
1188 // SUB
1189 #define VS_ZOPC     (unsigned long)(0xe7L << 40 | 0xf7L << 0)   // V1 := V2 - V3, element size = 2**m
1190 #define VSCBI_ZOPC  (unsigned long)(0xe7L << 40 | 0xf5L << 0)   // V1 := borrow(V2 - V3), element size = 2**m
1191 
1192 // MUL
1193 #define VML_ZOPC    (unsigned long)(0xe7L << 40 | 0xa2L << 0)   // V1 := V2 * V3, element size = 2**m
1194 #define VMH_ZOPC    (unsigned long)(0xe7L << 40 | 0xa3L << 0)   // V1 := V2 * V3, element size = 2**m
1195 #define VMLH_ZOPC   (unsigned long)(0xe7L << 40 | 0xa1L << 0)   // V1 := V2 * V3, element size = 2**m, unsigned
1196 #define VME_ZOPC    (unsigned long)(0xe7L << 40 | 0xa6L << 0)   // V1 := V2 * V3, element size = 2**m
1197 #define VMLE_ZOPC   (unsigned long)(0xe7L << 40 | 0xa4L << 0)   // V1 := V2 * V3, element size = 2**m, unsigned
1198 #define VMO_ZOPC    (unsigned long)(0xe7L << 40 | 0xa7L << 0)   // V1 := V2 * V3, element size = 2**m
1199 #define VMLO_ZOPC   (unsigned long)(0xe7L << 40 | 0xa5L << 0)   // V1 := V2 * V3, element size = 2**m, unsigned
1200 
1201 // MUL & ADD
1202 #define VMAL_ZOPC   (unsigned long)(0xe7L << 40 | 0xaaL << 0)   // V1 := V2 * V3 + V4, element size = 2**m
1203 #define VMAH_ZOPC   (unsigned long)(0xe7L << 40 | 0xabL << 0)   // V1 := V2 * V3 + V4, element size = 2**m
1204 #define VMALH_ZOPC  (unsigned long)(0xe7L << 40 | 0xa9L << 0)   // V1 := V2 * V3 + V4, element size = 2**m, unsigned
1205 #define VMAE_ZOPC   (unsigned long)(0xe7L << 40 | 0xaeL << 0)   // V1 := V2 * V3 + V4, element size = 2**m
1206 #define VMALE_ZOPC  (unsigned long)(0xe7L << 40 | 0xacL << 0)   // V1 := V2 * V3 + V4, element size = 2**m, unsigned
1207 #define VMAO_ZOPC   (unsigned long)(0xe7L << 40 | 0xafL << 0)   // V1 := V2 * V3 + V4, element size = 2**m
1208 #define VMALO_ZOPC  (unsigned long)(0xe7L << 40 | 0xadL << 0)   // V1 := V2 * V3 + V4, element size = 2**m, unsigned
1209 
1210 // Vector SUM
1211 #define VSUM_ZOPC   (unsigned long)(0xe7L << 40 | 0x64L << 0)   // V1[j] := toFW(sum(V2[i]) + V3[j]), subelements: byte or HW
1212 #define VSUMG_ZOPC  (unsigned long)(0xe7L << 40 | 0x65L << 0)   // V1[j] := toDW(sum(V2[i]) + V3[j]), subelements: HW or FW
1213 #define VSUMQ_ZOPC  (unsigned long)(0xe7L << 40 | 0x67L << 0)   // V1[j] := toQW(sum(V2[i]) + V3[j]), subelements: FW or DW
1214 
1215 // Average
1216 #define VAVG_ZOPC   (unsigned long)(0xe7L << 40 | 0xf2L << 0)   // V1 := (V2+V3+1)/2, signed,   element size = 2**m
1217 #define VAVGL_ZOPC  (unsigned long)(0xe7L << 40 | 0xf0L << 0)   // V1 := (V2+V3+1)/2, unsigned, element size = 2**m
1218 
1219 // VECTOR Galois Field Multiply Sum
1220 #define VGFM_ZOPC   (unsigned long)(0xe7L << 40 | 0xb4L << 0)
1221 #define VGFMA_ZOPC  (unsigned long)(0xe7L << 40 | 0xbcL << 0)
1222 
1223 //---<  Vector Logical Instructions  >---
1224 
1225 // AND
1226 #define VN_ZOPC     (unsigned long)(0xe7L << 40 | 0x68L << 0)   // V1 := V2 & V3,  element size = 2**m
1227 #define VNC_ZOPC    (unsigned long)(0xe7L << 40 | 0x69L << 0)   // V1 := V2 & ~V3, element size = 2**m
1228 
1229 // XOR
1230 #define VX_ZOPC     (unsigned long)(0xe7L << 40 | 0x6dL << 0)   // V1 := V2 ^ V3,  element size = 2**m
1231 
1232 // NOR
1233 #define VNO_ZOPC    (unsigned long)(0xe7L << 40 | 0x6bL << 0)   // V1 := !(V2 | V3),  element size = 2**m
1234 
1235 // OR
1236 #define VO_ZOPC     (unsigned long)(0xe7L << 40 | 0x6aL << 0)   // V1 := V2 | V3,  element size = 2**m
1237 
1238 // Comparison (element-wise)
1239 #define VCEQ_ZOPC   (unsigned long)(0xe7L << 40 | 0xf8L << 0)   // V1 := (V2 == V3) ? 0xffff : 0x0000, element size = 2**m
1240 #define VCH_ZOPC    (unsigned long)(0xe7L << 40 | 0xfbL << 0)   // V1 := (V2  > V3) ? 0xffff : 0x0000, element size = 2**m, signed
1241 #define VCHL_ZOPC   (unsigned long)(0xe7L << 40 | 0xf9L << 0)   // V1 := (V2  > V3) ? 0xffff : 0x0000, element size = 2**m, unsigned
1242 
1243 // Max/Min (element-wise)
1244 #define VMX_ZOPC    (unsigned long)(0xe7L << 40 | 0xffL << 0)   // V1 := (V2 > V3) ? V2 : V3, element size = 2**m, signed
1245 #define VMXL_ZOPC   (unsigned long)(0xe7L << 40 | 0xfdL << 0)   // V1 := (V2 > V3) ? V2 : V3, element size = 2**m, unsigned
1246 #define VMN_ZOPC    (unsigned long)(0xe7L << 40 | 0xfeL << 0)   // V1 := (V2 < V3) ? V2 : V3, element size = 2**m, signed
1247 #define VMNL_ZOPC   (unsigned long)(0xe7L << 40 | 0xfcL << 0)   // V1 := (V2 < V3) ? V2 : V3, element size = 2**m, unsigned
1248 
1249 // Leading/Trailing Zeros, population count
1250 #define VCLZ_ZOPC   (unsigned long)(0xe7L << 40 | 0x53L << 0)   // V1 := leadingzeros(V2),  element size = 2**m
1251 #define VCTZ_ZOPC   (unsigned long)(0xe7L << 40 | 0x52L << 0)   // V1 := trailingzeros(V2), element size = 2**m
1252 #define VPOPCT_ZOPC (unsigned long)(0xe7L << 40 | 0x50L << 0)   // V1 := popcount(V2), bytewise!!
1253 
1254 // Rotate/Shift
1255 #define VERLLV_ZOPC (unsigned long)(0xe7L << 40 | 0x73L << 0)   // V1 := rotateleft(V2), rotate count in V3 element
1256 #define VERLL_ZOPC  (unsigned long)(0xe7L << 40 | 0x33L << 0)   // V1 := rotateleft(V3), rotate count from d2(b2).
1257 #define VERIM_ZOPC  (unsigned long)(0xe7L << 40 | 0x72L << 0)   // Rotate then insert under mask. Read Principles of Operation!!
1258 
1259 #define VESLV_ZOPC  (unsigned long)(0xe7L << 40 | 0x70L << 0)   // V1 := SLL(V2, V3), unsigned, element-wise
1260 #define VESL_ZOPC   (unsigned long)(0xe7L << 40 | 0x30L << 0)   // V1 := SLL(V3), unsigned, shift count from d2(b2).
1261 
1262 #define VESRAV_ZOPC (unsigned long)(0xe7L << 40 | 0x7AL << 0)   // V1 := SRA(V2, V3), signed, element-wise
1263 #define VESRA_ZOPC  (unsigned long)(0xe7L << 40 | 0x3AL << 0)   // V1 := SRA(V3), signed, shift count from d2(b2).
1264 #define VESRLV_ZOPC (unsigned long)(0xe7L << 40 | 0x78L << 0)   // V1 := SRL(V2, V3), unsigned, element-wise
1265 #define VESRL_ZOPC  (unsigned long)(0xe7L << 40 | 0x38L << 0)   // V1 := SRL(V3), unsigned, shift count from d2(b2).
1266 
1267 #define VSL_ZOPC    (unsigned long)(0xe7L << 40 | 0x74L << 0)   // V1 := SLL(V2), unsigned, bit-count
1268 #define VSLB_ZOPC   (unsigned long)(0xe7L << 40 | 0x75L << 0)   // V1 := SLL(V2), unsigned, byte-count
1269 #define VSLDB_ZOPC  (unsigned long)(0xe7L << 40 | 0x77L << 0)   // V1 := SLL((V2,V3)), unsigned, byte-count
1270 
1271 #define VSRA_ZOPC   (unsigned long)(0xe7L << 40 | 0x7eL << 0)   // V1 := SRA(V2), signed, bit-count
1272 #define VSRAB_ZOPC  (unsigned long)(0xe7L << 40 | 0x7fL << 0)   // V1 := SRA(V2), signed, byte-count
1273 #define VSRL_ZOPC   (unsigned long)(0xe7L << 40 | 0x7cL << 0)   // V1 := SRL(V2), unsigned, bit-count
1274 #define VSRLB_ZOPC  (unsigned long)(0xe7L << 40 | 0x7dL << 0)   // V1 := SRL(V2), unsigned, byte-count
1275 
1276 // Test under Mask
1277 #define VTM_ZOPC    (unsigned long)(0xe7L << 40 | 0xd8L << 0)   // Like TM, set CC according to state of selected bits.
1278 
1279 
1280 //--------------------------------
1281 //--  Miscellaneous Operations  --
1282 //--------------------------------
1283 
1284 // Execute
1285 #define EX_ZOPC     (unsigned  int)(68L << 24)
1286 #define EXRL_ZOPC   (unsigned long)(0xc6L << 40 | 0x00L << 32)  // z10
1287 
1288 // Compare and Swap
1289 #define CS_ZOPC     (unsigned  int)(0xba << 24)
1290 #define CSY_ZOPC    (unsigned long)(0xebL << 40 | 0x14L)
1291 #define CSG_ZOPC    (unsigned long)(0xebL << 40 | 0x30L)
1292 
1293 // Interlocked-Update
1294 #define LAA_ZOPC    (unsigned long)(0xebL << 40 | 0xf8L)         // z196
1295 #define LAAG_ZOPC   (unsigned long)(0xebL << 40 | 0xe8L)         // z196
1296 #define LAAL_ZOPC   (unsigned long)(0xebL << 40 | 0xfaL)         // z196
1297 #define LAALG_ZOPC  (unsigned long)(0xebL << 40 | 0xeaL)         // z196
1298 #define LAN_ZOPC    (unsigned long)(0xebL << 40 | 0xf4L)         // z196
1299 #define LANG_ZOPC   (unsigned long)(0xebL << 40 | 0xe4L)         // z196
1300 #define LAX_ZOPC    (unsigned long)(0xebL << 40 | 0xf7L)         // z196
1301 #define LAXG_ZOPC   (unsigned long)(0xebL << 40 | 0xe7L)         // z196
1302 #define LAO_ZOPC    (unsigned long)(0xebL << 40 | 0xf6L)         // z196


1449     // z/Architecture
1450     negative         = 0,
1451     less             = 0,
1452     positive         = 1,
1453     greater          = 1,
1454     zero             = 2,
1455     equal            = 2,
1456     summary_overflow = 3,
1457   };
1458 
1459   // Rounding mode for float-2-int conversions.
1460   enum RoundingMode {
1461     current_mode      = 0,   // Mode taken from FPC register.
1462     biased_to_nearest = 1,
1463     to_nearest        = 4,
1464     to_zero           = 5,
1465     to_plus_infinity  = 6,
1466     to_minus_infinity = 7
1467   };
1468 
1469   // Vector Register Element Type.
1470   enum VRegElemType {
1471     VRET_BYTE   = 0,
1472     VRET_HW     = 1,
1473     VRET_FW     = 2,
1474     VRET_DW     = 3,
1475     VRET_QW     = 4
1476   };
1477 
1478   // Vector Operation Condition Code Control.
1479   enum VOpCCC {
1480     VOP_CCIGN   = 0, // ignore, don't set CC
1481     VOP_CCSET   = 1  // set the CC
1482   };
1483 
1484   // Inverse condition code, i.e. determine "15 - cc" for a given condition code cc.
1485   static branch_condition inverse_condition(branch_condition cc);
1486   static branch_condition inverse_float_condition(branch_condition cc);
1487 
1488 
1489   //-----------------------------------------------
1490   // instruction property getter methods
1491   //-----------------------------------------------
1492 
1493   // Calculate length of instruction.
1494   static int instr_len(unsigned char *instr);
1495 
1496   // Longest instructions are 6 bytes on z/Architecture.
1497   static int instr_maxlen() { return 6; }
1498 
1499   // Average instruction is 4 bytes on z/Architecture (just a guess).
1500   static int instr_avglen() { return 4; }
1501 
1502   // Shortest instructions are 2 bytes on z/Architecture.
1503   static int instr_minlen() { return 2; }


1560   static int z_inv_op(int  x) { return inv_u_field(x, 31, 24); }
1561   static int z_inv_op(long x) { return inv_u_field(x, 47, 40); }
1562 
1563   static int inv_reg( long x, int s, int len) { return inv_u_field(x, (len-s)-1, (len-s)-4); }  // Regs are encoded in 4 bits.
1564   static int inv_mask(long x, int s, int len) { return inv_u_field(x, (len-s)-1, (len-s)-8); }  // Mask is 8 bits long.
1565   static int inv_simm16_48(long x) { return (inv_s_field(x, 31, 16)); }                         // 6-byte instructions only
1566   static int inv_simm16(long x)    { return (inv_s_field(x, 15,  0)); }                         // 4-byte instructions only
1567   static int inv_simm20(long x)    { return (inv_u_field(x, 27, 16) |                           // 6-byte instructions only
1568                                              inv_s_field(x, 15, 8)<<12); }
1569   static int inv_simm32(long x)    { return (inv_s_field(x, 31,  0)); }                         // 6-byte instructions only
1570   static int inv_uimm12(long x)    { return (inv_u_field(x, 11,  0)); }                         // 4-byte instructions only
1571 
1572   // Encode u_field from long value.
1573   static long u_field(long x, int hi_bit, int lo_bit) {
1574     long r = x << lo_bit;
1575     assert((r & ~fmask(hi_bit, lo_bit))   == 0, "value out of range");
1576     assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
1577     return r;
1578   }
1579 
1580   static int64_t rsmask_48( Address a) { assert(a.is_RSform(),  "bad address format"); return rsmask_48( a.disp12(), a.base()); }
1581   static int64_t rxmask_48( Address a) {      if (a.is_RXform())  { return rxmask_48( a.disp12(), a.index(), a.base()); }
1582                                          else if (a.is_RSform())  { return rsmask_48( a.disp12(),            a.base()); }
1583                                          else                     { guarantee(false, "bad address format");  return 0;  }
1584                                        }
1585   static int64_t rsymask_48(Address a) { assert(a.is_RSYform(), "bad address format"); return rsymask_48(a.disp20(), a.base()); }
1586   static int64_t rxymask_48(Address a) {      if (a.is_RXYform()) { return rxymask_48( a.disp20(), a.index(), a.base()); }
1587                                          else if (a.is_RSYform()) { return rsymask_48( a.disp20(),            a.base()); }
1588                                          else                     { guarantee(false, "bad address format");  return 0;   }
1589                                        }
1590 
1591   static int64_t rsmask_48( int64_t d2, Register b2)              { return uimm12(d2, 20, 48)                   | regz(b2, 16, 48); }
1592   static int64_t rxmask_48( int64_t d2, Register x2, Register b2) { return uimm12(d2, 20, 48) | reg(x2, 12, 48) | regz(b2, 16, 48); }
1593   static int64_t rsymask_48(int64_t d2, Register b2)              { return simm20(d2)                           | regz(b2, 16, 48); }
1594   static int64_t rxymask_48(int64_t d2, Register x2, Register b2) { return simm20(d2)         | reg(x2, 12, 48) | regz(b2, 16, 48); }
1595 
1596   // Address calculated from d12(vx,b) - vx is vector index register.
1597   static int64_t rvmask_48( int64_t d2, VectorRegister x2, Register b2) { return uimm12(d2, 20, 48) | vreg(x2, 12) | regz(b2, 16, 48); }
1598 
1599   static int64_t vreg_mask(VectorRegister v, int pos) {
1600     return vreg(v, pos) | v->RXB_mask(pos);
1601   }
1602 
1603   // Vector Element Size Control. 4-bit field which indicates the size of the vector elements.
1604   static int64_t vesc_mask(int64_t size, int min_size, int max_size, int pos) {
1605     // min_size - minimum element size. Not all instructions support element sizes beginning with "byte".
1606     // max_size - maximum element size. Not all instructions support element sizes up to "QW".
1607     assert((min_size <= size) && (size <= max_size), "element size control out of range");
1608     return uimm4(size, pos, 48);
1609   }
1610 
1611   // Vector Element IndeX. 4-bit field which indexes the target vector element.
1612   static int64_t veix_mask(int64_t ix, int el_size, int pos) {
1613     // el_size - size of the vector element. This is a VRegElemType enum value.
1614     // ix      - vector element index.
1615     int max_ix = -1;
1616     switch (el_size) {
1617       case VRET_BYTE: max_ix = 15; break;
1618       case VRET_HW:   max_ix =  7; break;
1619       case VRET_FW:   max_ix =  3; break;
1620       case VRET_DW:   max_ix =  1; break;
1621       case VRET_QW:   max_ix =  0; break;
1622       default:        guarantee(false, "bad vector element size %d", el_size); break;
1623     }
1624     assert((0 <= ix) && (ix <= max_ix), "element size out of range (0 <= %ld <= %d)", ix, max_ix);
1625     return uimm4(ix, pos, 48);
1626   }
1627 
1628   // Vector Operation Condition Code Control. 4-bit field, one bit of which indicates if the condition code is to be set by the operation.
1629   static int64_t vccc_mask(int64_t flag, int pos) {
1630     assert((flag == VOP_CCIGN) || (flag == VOP_CCSET), "VCCC flag value out of range");
1631     return uimm4(flag, pos, 48);
1632   }
1633 
1634  public:
1635 
1636   //--------------------------------------------------
1637   // instruction field construction methods
1638   //--------------------------------------------------
1639 
1640   // Compute relative address (32 bit) for branch.
1641   // Only used once in nativeInst_s390.cpp.
1642   static intptr_t z_pcrel_off(address dest, address pc) {
1643     return RelAddr::pcrel_off32(dest, pc);
1644   }
1645 
1646   // Extract 20-bit signed displacement.
1647   // Only used in disassembler_s390.cpp for temp enhancements.
1648   static int inv_simm20_xx(address iLoc) {
1649     unsigned long instr = 0;
1650     unsigned long iLen  = get_instruction(iLoc, &instr);
1651     return inv_simm20(instr);
1652   }
1653 


1691 
1692   static long uimm4( int64_t ui4,  int s, int len) { return uimm(ui4,   4) << (len-s-4);  }
1693   static long uimm6( int64_t ui6,  int s, int len) { return uimm(ui6,   6) << (len-s-6);  }
1694   static long uimm8( int64_t ui8,  int s, int len) { return uimm(ui8,   8) << (len-s-8);  }
1695   static long uimm12(int64_t ui12, int s, int len) { return uimm(ui12, 12) << (len-s-12); }
1696   static long uimm16(int64_t ui16, int s, int len) { return uimm(ui16, 16) << (len-s-16); }
1697   static long uimm32(int64_t ui32, int s, int len) { return uimm((unsigned)ui32, 32) << (len-s-32); } // prevent sign extension
1698 
1699   static long simm8( int64_t si8,  int s, int len) { return simm(si8,   8) << (len-s-8);  }
1700   static long simm12(int64_t si12, int s, int len) { return simm(si12, 12) << (len-s-12); }
1701   static long simm16(int64_t si16, int s, int len) { return simm(si16, 16) << (len-s-16); }
1702   static long simm24(int64_t si24, int s, int len) { return simm(si24, 24) << (len-s-24); }
1703   static long simm32(int64_t si32, int s, int len) { return simm(si32, 32) << (len-s-32); }
1704 
1705   static long imm8( int64_t i8,  int s, int len)   { return imm(i8,   8) << (len-s-8);  }
1706   static long imm12(int64_t i12, int s, int len)   { return imm(i12, 12) << (len-s-12); }
1707   static long imm16(int64_t i16, int s, int len)   { return imm(i16, 16) << (len-s-16); }
1708   static long imm24(int64_t i24, int s, int len)   { return imm(i24, 24) << (len-s-24); }
1709   static long imm32(int64_t i32, int s, int len)   { return imm(i32, 32) << (len-s-32); }
1710 
1711   static long vreg(VectorRegister v, int pos)      { const int len = 48; return u_field(v->encoding()&0x0f, (len-pos)-1, (len-pos)-4) | v->RXB_mask(pos); }
1712 
1713   static long fregt(FloatRegister r, int s, int len) { return freg(r,s,len); }
1714   static long freg( FloatRegister r, int s, int len) { return u_field(r->encoding(), (len-s)-1, (len-s)-4); }
1715 
1716   // Rounding mode for float-2-int conversions.
1717   static long rounding_mode(RoundingMode m, int s, int len) {
1718     assert(m != 2 && m != 3, "invalid mode");
1719     return uimm(m, 4) << (len-s-4);
1720   }
1721 
1722   //--------------------------------------------
1723   // instruction field getter methods
1724   //--------------------------------------------
1725 
1726   static int get_imm32(address a, int instruction_number) {
1727     int imm;
1728     int *p =((int *)(a + 2 + 6 * instruction_number));
1729     imm = *p;
1730     return imm;
1731   }
1732 


2363 
2364   inline void z_stfle(int64_t d2, Register b2);                            // store facility list extended
2365 
2366   inline void z_nc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);// and *(d1+b1) = *(d1+l+b1) & *(d2+b2) ; d1, d2: uimm12, ands l+1 bytes
2367   inline void z_oc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);//  or *(d1+b1) = *(d1+l+b1) | *(d2+b2) ; d1, d2: uimm12,  ors l+1 bytes
2368   inline void z_xc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);// xor *(d1+b1) = *(d1+l+b1) ^ *(d2+b2) ; d1, d2: uimm12, xors l+1 bytes
2369   inline void z_nc(Address dst, int64_t len, Address src2);                     // and *dst = *dst & *src2, ands len bytes in memory
2370   inline void z_oc(Address dst, int64_t len, Address src2);                     //  or *dst = *dst | *src2,  ors len bytes in memory
2371   inline void z_xc(Address dst, int64_t len, Address src2);                     // xor *dst = *dst ^ *src2, xors len bytes in memory
2372 
2373   // compare instructions
2374   inline void z_clc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);  // compare (*(d1_uimm12+b1), *(d1_uimm12+b1)) ; compare l bytes
2375   inline void z_clcle(Register r1, Register r3, int64_t d2, Register b2);  // compare logical long extended, see docu
2376   inline void z_clclu(Register r1, Register r3, int64_t d2, Register b2);  // compare logical long unicode, see docu
2377 
2378   // Translate characters
2379   inline void z_troo(Register r1, Register r2, int64_t m3);
2380   inline void z_trot(Register r1, Register r2, int64_t m3);
2381   inline void z_trto(Register r1, Register r2, int64_t m3);
2382   inline void z_trtt(Register r1, Register r2, int64_t m3);
2383 
2384 
2385   //---------------------------
2386   //--  Vector Instructions  --
2387   //---------------------------
2388 
2389   //---<  Vector Support Instructions  >---
2390 
2391   // Load (transfer from memory)
2392   inline void z_vlm(   VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2393   inline void z_vl(    VectorRegister v1, int64_t d2, Register x2, Register b2);
2394   inline void z_vleb(  VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
2395   inline void z_vleh(  VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
2396   inline void z_vlef(  VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
2397   inline void z_vleg(  VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
2398 
2399   // Gather/Scatter
2400   inline void z_vgef(  VectorRegister v1, int64_t d2, VectorRegister vx2, Register b2, int64_t m3);
2401   inline void z_vgeg(  VectorRegister v1, int64_t d2, VectorRegister vx2, Register b2, int64_t m3);
2402 
2403   inline void z_vscef( VectorRegister v1, int64_t d2, VectorRegister vx2, Register b2, int64_t m3);
2404   inline void z_vsceg( VectorRegister v1, int64_t d2, VectorRegister vx2, Register b2, int64_t m3);
2405 
2406   // load and replicate
2407   inline void z_vlrep( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
2408   inline void z_vlrepb(VectorRegister v1, int64_t d2, Register x2, Register b2);
2409   inline void z_vlreph(VectorRegister v1, int64_t d2, Register x2, Register b2);
2410   inline void z_vlrepf(VectorRegister v1, int64_t d2, Register x2, Register b2);
2411   inline void z_vlrepg(VectorRegister v1, int64_t d2, Register x2, Register b2);
2412 
2413   inline void z_vllez( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
2414   inline void z_vllezb(VectorRegister v1, int64_t d2, Register x2, Register b2);
2415   inline void z_vllezh(VectorRegister v1, int64_t d2, Register x2, Register b2);
2416   inline void z_vllezf(VectorRegister v1, int64_t d2, Register x2, Register b2);
2417   inline void z_vllezg(VectorRegister v1, int64_t d2, Register x2, Register b2);
2418 
2419   inline void z_vlbb(  VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
2420   inline void z_vll(   VectorRegister v1, Register r3, int64_t d2, Register b2);
2421 
2422   // Load (register to register)
2423   inline void z_vlr(   VectorRegister v1, VectorRegister v2);
2424 
2425   inline void z_vlgv(  Register r1, VectorRegister v3, int64_t d2, Register b2, int64_t m4);
2426   inline void z_vlgvb( Register r1, VectorRegister v3, int64_t d2, Register b2);
2427   inline void z_vlgvh( Register r1, VectorRegister v3, int64_t d2, Register b2);
2428   inline void z_vlgvf( Register r1, VectorRegister v3, int64_t d2, Register b2);
2429   inline void z_vlgvg( Register r1, VectorRegister v3, int64_t d2, Register b2);
2430 
2431   inline void z_vlvg(  VectorRegister v1, Register r3, int64_t d2, Register b2, int64_t m4);
2432   inline void z_vlvgb( VectorRegister v1, Register r3, int64_t d2, Register b2);
2433   inline void z_vlvgh( VectorRegister v1, Register r3, int64_t d2, Register b2);
2434   inline void z_vlvgf( VectorRegister v1, Register r3, int64_t d2, Register b2);
2435   inline void z_vlvgg( VectorRegister v1, Register r3, int64_t d2, Register b2);
2436 
2437   inline void z_vlvgp( VectorRegister v1, Register r2, Register r3);
2438 
2439   // vector register pack
2440   inline void z_vpk(   VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2441   inline void z_vpkh(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2442   inline void z_vpkf(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2443   inline void z_vpkg(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2444 
2445   inline void z_vpks(  VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4, int64_t cc5);
2446   inline void z_vpksh( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2447   inline void z_vpksf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2448   inline void z_vpksg( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2449   inline void z_vpkshs(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2450   inline void z_vpksfs(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2451   inline void z_vpksgs(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2452 
2453   inline void z_vpkls(  VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4, int64_t cc5);
2454   inline void z_vpklsh( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2455   inline void z_vpklsf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2456   inline void z_vpklsg( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2457   inline void z_vpklshs(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2458   inline void z_vpklsfs(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2459   inline void z_vpklsgs(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2460 
2461   // vector register unpack (sign-extended)
2462   inline void z_vuph(   VectorRegister v1, VectorRegister v2, int64_t m3);
2463   inline void z_vuphb(  VectorRegister v1, VectorRegister v2);
2464   inline void z_vuphh(  VectorRegister v1, VectorRegister v2);
2465   inline void z_vuphf(  VectorRegister v1, VectorRegister v2);
2466   inline void z_vupl(   VectorRegister v1, VectorRegister v2, int64_t m3);
2467   inline void z_vuplb(  VectorRegister v1, VectorRegister v2);
2468   inline void z_vuplh(  VectorRegister v1, VectorRegister v2);
2469   inline void z_vuplf(  VectorRegister v1, VectorRegister v2);
2470 
2471   // vector register unpack (zero-extended)
2472   inline void z_vuplh(  VectorRegister v1, VectorRegister v2, int64_t m3);
2473   inline void z_vuplhb( VectorRegister v1, VectorRegister v2);
2474   inline void z_vuplhh( VectorRegister v1, VectorRegister v2);
2475   inline void z_vuplhf( VectorRegister v1, VectorRegister v2);
2476   inline void z_vupll(  VectorRegister v1, VectorRegister v2, int64_t m3);
2477   inline void z_vupllb( VectorRegister v1, VectorRegister v2);
2478   inline void z_vupllh( VectorRegister v1, VectorRegister v2);
2479   inline void z_vupllf( VectorRegister v1, VectorRegister v2);
2480 
2481   // vector register merge high/low
2482   inline void z_vmrh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2483   inline void z_vmrhb(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2484   inline void z_vmrhh(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2485   inline void z_vmrhf(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2486   inline void z_vmrhg(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2487 
2488   inline void z_vmrl( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2489   inline void z_vmrlb(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2490   inline void z_vmrlh(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2491   inline void z_vmrlf(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2492   inline void z_vmrlg(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2493 
2494   // vector register permute
2495   inline void z_vperm( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4);
2496   inline void z_vpdi(  VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t        m4);
2497 
2498   // vector register replicate
2499   inline void z_vrep(  VectorRegister v1, VectorRegister v3, int64_t imm2, int64_t m4);
2500   inline void z_vrepb( VectorRegister v1, VectorRegister v3, int64_t imm2);
2501   inline void z_vreph( VectorRegister v1, VectorRegister v3, int64_t imm2);
2502   inline void z_vrepf( VectorRegister v1, VectorRegister v3, int64_t imm2);
2503   inline void z_vrepg( VectorRegister v1, VectorRegister v3, int64_t imm2);
2504   inline void z_vrepi( VectorRegister v1, int64_t imm2,      int64_t m3);
2505   inline void z_vrepib(VectorRegister v1, int64_t imm2);
2506   inline void z_vrepih(VectorRegister v1, int64_t imm2);
2507   inline void z_vrepif(VectorRegister v1, int64_t imm2);
2508   inline void z_vrepig(VectorRegister v1, int64_t imm2);
2509 
2510   inline void z_vsel(  VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4);
2511   inline void z_vseg(  VectorRegister v1, VectorRegister v2, int64_t imm3);
2512 
2513   // Load (immediate)
2514   inline void z_vleib( VectorRegister v1, int64_t imm2, int64_t m3);
2515   inline void z_vleih( VectorRegister v1, int64_t imm2, int64_t m3);
2516   inline void z_vleif( VectorRegister v1, int64_t imm2, int64_t m3);
2517   inline void z_vleig( VectorRegister v1, int64_t imm2, int64_t m3);
2518 
2519   // Store
2520   inline void z_vstm(  VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2521   inline void z_vst(   VectorRegister v1, int64_t d2, Register x2, Register b2);
2522   inline void z_vsteb( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
2523   inline void z_vsteh( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
2524   inline void z_vstef( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
2525   inline void z_vsteg( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
2526   inline void z_vstl(  VectorRegister v1, Register r3, int64_t d2, Register b2);
2527 
2528   // Misc
2529   inline void z_vgm(   VectorRegister v1, int64_t imm2, int64_t imm3, int64_t m4);
2530   inline void z_vgmb(  VectorRegister v1, int64_t imm2, int64_t imm3);
2531   inline void z_vgmh(  VectorRegister v1, int64_t imm2, int64_t imm3);
2532   inline void z_vgmf(  VectorRegister v1, int64_t imm2, int64_t imm3);
2533   inline void z_vgmg(  VectorRegister v1, int64_t imm2, int64_t imm3);
2534 
2535   inline void z_vgbm(  VectorRegister v1, int64_t imm2);
2536   inline void z_vzero( VectorRegister v1); // preferred method to set vreg to all zeroes
2537   inline void z_vone(  VectorRegister v1); // preferred method to set vreg to all ones
2538 
2539   //---<  Vector Arithmetic Instructions  >---
2540 
2541   // Load
2542   inline void z_vlc(    VectorRegister v1, VectorRegister v2, int64_t m3);
2543   inline void z_vlcb(   VectorRegister v1, VectorRegister v2);
2544   inline void z_vlch(   VectorRegister v1, VectorRegister v2);
2545   inline void z_vlcf(   VectorRegister v1, VectorRegister v2);
2546   inline void z_vlcg(   VectorRegister v1, VectorRegister v2);
2547   inline void z_vlp(    VectorRegister v1, VectorRegister v2, int64_t m3);
2548   inline void z_vlpb(   VectorRegister v1, VectorRegister v2);
2549   inline void z_vlph(   VectorRegister v1, VectorRegister v2);
2550   inline void z_vlpf(   VectorRegister v1, VectorRegister v2);
2551   inline void z_vlpg(   VectorRegister v1, VectorRegister v2);
2552 
2553   // ADD
2554   inline void z_va(     VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2555   inline void z_vab(    VectorRegister v1, VectorRegister v2, VectorRegister v3);
2556   inline void z_vah(    VectorRegister v1, VectorRegister v2, VectorRegister v3);
2557   inline void z_vaf(    VectorRegister v1, VectorRegister v2, VectorRegister v3);
2558   inline void z_vag(    VectorRegister v1, VectorRegister v2, VectorRegister v3);
2559   inline void z_vaq(    VectorRegister v1, VectorRegister v2, VectorRegister v3);
2560   inline void z_vacc(   VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2561   inline void z_vaccb(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2562   inline void z_vacch(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2563   inline void z_vaccf(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2564   inline void z_vaccg(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2565   inline void z_vaccq(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2566 
2567   // SUB
2568   inline void z_vs(     VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2569   inline void z_vsb(    VectorRegister v1, VectorRegister v2, VectorRegister v3);
2570   inline void z_vsh(    VectorRegister v1, VectorRegister v2, VectorRegister v3);
2571   inline void z_vsf(    VectorRegister v1, VectorRegister v2, VectorRegister v3);
2572   inline void z_vsg(    VectorRegister v1, VectorRegister v2, VectorRegister v3);
2573   inline void z_vsq(    VectorRegister v1, VectorRegister v2, VectorRegister v3);
2574   inline void z_vscbi(  VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2575   inline void z_vscbib( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2576   inline void z_vscbih( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2577   inline void z_vscbif( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2578   inline void z_vscbig( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2579   inline void z_vscbiq( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2580 
2581   // MULTIPLY
2582   inline void z_vml(    VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2583   inline void z_vmh(    VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2584   inline void z_vmlh(   VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2585   inline void z_vme(    VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2586   inline void z_vmle(   VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2587   inline void z_vmo(    VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2588   inline void z_vmlo(   VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2589 
2590   // MULTIPLY & ADD
2591   inline void z_vmal(   VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5);
2592   inline void z_vmah(   VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5);
2593   inline void z_vmalh(  VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5);
2594   inline void z_vmae(   VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5);
2595   inline void z_vmale(  VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5);
2596   inline void z_vmao(   VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5);
2597   inline void z_vmalo(  VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5);
2598 
2599   // VECTOR SUM
2600   inline void z_vsum(   VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2601   inline void z_vsumb(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2602   inline void z_vsumh(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2603   inline void z_vsumg(  VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2604   inline void z_vsumgh( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2605   inline void z_vsumgf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2606   inline void z_vsumq(  VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2607   inline void z_vsumqf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2608   inline void z_vsumqg( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2609 
2610   // Average
2611   inline void z_vavg(   VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2612   inline void z_vavgb(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2613   inline void z_vavgh(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2614   inline void z_vavgf(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2615   inline void z_vavgg(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2616   inline void z_vavgl(  VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2617   inline void z_vavglb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2618   inline void z_vavglh( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2619   inline void z_vavglf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2620   inline void z_vavglg( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2621 
2622   // VECTOR Galois Field Multiply Sum
2623   inline void z_vgfm(   VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2624   inline void z_vgfmb(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2625   inline void z_vgfmh(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2626   inline void z_vgfmf(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2627   inline void z_vgfmg(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2628   // VECTOR Galois Field Multiply Sum and Accumulate
2629   inline void z_vgfma(  VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5);
2630   inline void z_vgfmab( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4);
2631   inline void z_vgfmah( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4);
2632   inline void z_vgfmaf( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4);
2633   inline void z_vgfmag( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4);
2634 
2635   //---<  Vector Logical Instructions  >---
2636 
2637   // AND
2638   inline void z_vn(     VectorRegister v1, VectorRegister v2, VectorRegister v3);
2639   inline void z_vnc(    VectorRegister v1, VectorRegister v2, VectorRegister v3);
2640 
2641   // XOR
2642   inline void z_vx(     VectorRegister v1, VectorRegister v2, VectorRegister v3);
2643 
2644   // NOR
2645   inline void z_vno(    VectorRegister v1, VectorRegister v2, VectorRegister v3);
2646 
2647   // OR
2648   inline void z_vo(     VectorRegister v1, VectorRegister v2, VectorRegister v3);
2649 
2650   // Comparison (element-wise)
2651   inline void z_vceq(   VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4, int64_t cc5);
2652   inline void z_vceqb(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2653   inline void z_vceqh(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2654   inline void z_vceqf(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2655   inline void z_vceqg(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2656   inline void z_vceqbs( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2657   inline void z_vceqhs( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2658   inline void z_vceqfs( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2659   inline void z_vceqgs( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2660   inline void z_vch(    VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4, int64_t cc5);
2661   inline void z_vchb(   VectorRegister v1, VectorRegister v2, VectorRegister v3);
2662   inline void z_vchh(   VectorRegister v1, VectorRegister v2, VectorRegister v3);
2663   inline void z_vchf(   VectorRegister v1, VectorRegister v2, VectorRegister v3);
2664   inline void z_vchg(   VectorRegister v1, VectorRegister v2, VectorRegister v3);
2665   inline void z_vchbs(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2666   inline void z_vchhs(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2667   inline void z_vchfs(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2668   inline void z_vchgs(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2669   inline void z_vchl(   VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4, int64_t cc5);
2670   inline void z_vchlb(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2671   inline void z_vchlh(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2672   inline void z_vchlf(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2673   inline void z_vchlg(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2674   inline void z_vchlbs( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2675   inline void z_vchlhs( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2676   inline void z_vchlfs( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2677   inline void z_vchlgs( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2678 
2679   // Max/Min (element-wise)
2680   inline void z_vmx(    VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2681   inline void z_vmxb(   VectorRegister v1, VectorRegister v2, VectorRegister v3);
2682   inline void z_vmxh(   VectorRegister v1, VectorRegister v2, VectorRegister v3);
2683   inline void z_vmxf(   VectorRegister v1, VectorRegister v2, VectorRegister v3);
2684   inline void z_vmxg(   VectorRegister v1, VectorRegister v2, VectorRegister v3);
2685   inline void z_vmxl(   VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2686   inline void z_vmxlb(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2687   inline void z_vmxlh(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2688   inline void z_vmxlf(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2689   inline void z_vmxlg(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2690   inline void z_vmn(    VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2691   inline void z_vmnb(   VectorRegister v1, VectorRegister v2, VectorRegister v3);
2692   inline void z_vmnh(   VectorRegister v1, VectorRegister v2, VectorRegister v3);
2693   inline void z_vmnf(   VectorRegister v1, VectorRegister v2, VectorRegister v3);
2694   inline void z_vmng(   VectorRegister v1, VectorRegister v2, VectorRegister v3);
2695   inline void z_vmnl(   VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2696   inline void z_vmnlb(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2697   inline void z_vmnlh(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2698   inline void z_vmnlf(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2699   inline void z_vmnlg(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2700 
2701   // Leading/Trailing Zeros, population count
2702   inline void z_vclz(   VectorRegister v1, VectorRegister v2, int64_t m3);
2703   inline void z_vclzb(  VectorRegister v1, VectorRegister v2);
2704   inline void z_vclzh(  VectorRegister v1, VectorRegister v2);
2705   inline void z_vclzf(  VectorRegister v1, VectorRegister v2);
2706   inline void z_vclzg(  VectorRegister v1, VectorRegister v2);
2707   inline void z_vctz(   VectorRegister v1, VectorRegister v2, int64_t m3);
2708   inline void z_vctzb(  VectorRegister v1, VectorRegister v2);
2709   inline void z_vctzh(  VectorRegister v1, VectorRegister v2);
2710   inline void z_vctzf(  VectorRegister v1, VectorRegister v2);
2711   inline void z_vctzg(  VectorRegister v1, VectorRegister v2);
2712   inline void z_vpopct( VectorRegister v1, VectorRegister v2, int64_t m3);
2713 
2714   // Rotate/Shift
2715   inline void z_verllv( VectorRegister v1, VectorRegister v2, VectorRegister v3,               int64_t m4);
2716   inline void z_verllvb(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2717   inline void z_verllvh(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2718   inline void z_verllvf(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2719   inline void z_verllvg(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2720   inline void z_verll(  VectorRegister v1, VectorRegister v3, int64_t d2, Register b2,         int64_t m4);
2721   inline void z_verllb( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2722   inline void z_verllh( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2723   inline void z_verllf( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2724   inline void z_verllg( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2725   inline void z_verim(  VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4, int64_t m5);
2726   inline void z_verimb( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4);
2727   inline void z_verimh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4);
2728   inline void z_verimf( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4);
2729   inline void z_verimg( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4);
2730 
2731   inline void z_veslv(  VectorRegister v1, VectorRegister v2, VectorRegister v3,               int64_t m4);
2732   inline void z_veslvb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2733   inline void z_veslvh( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2734   inline void z_veslvf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2735   inline void z_veslvg( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2736   inline void z_vesl(   VectorRegister v1, VectorRegister v3, int64_t d2, Register b2,         int64_t m4);
2737   inline void z_veslb(  VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2738   inline void z_veslh(  VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2739   inline void z_veslf(  VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2740   inline void z_veslg(  VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2741 
2742   inline void z_vesrav( VectorRegister v1, VectorRegister v2, VectorRegister v3,               int64_t m4);
2743   inline void z_vesravb(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2744   inline void z_vesravh(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2745   inline void z_vesravf(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2746   inline void z_vesravg(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2747   inline void z_vesra(  VectorRegister v1, VectorRegister v3, int64_t d2, Register b2,         int64_t m4);
2748   inline void z_vesrab( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2749   inline void z_vesrah( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2750   inline void z_vesraf( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2751   inline void z_vesrag( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2752   inline void z_vesrlv( VectorRegister v1, VectorRegister v2, VectorRegister v3,               int64_t m4);
2753   inline void z_vesrlvb(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2754   inline void z_vesrlvh(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2755   inline void z_vesrlvf(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2756   inline void z_vesrlvg(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2757   inline void z_vesrl(  VectorRegister v1, VectorRegister v3, int64_t d2, Register b2,         int64_t m4);
2758   inline void z_vesrlb( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2759   inline void z_vesrlh( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2760   inline void z_vesrlf( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2761   inline void z_vesrlg( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
2762 
2763   inline void z_vsl(    VectorRegister v1, VectorRegister v2, VectorRegister v3);
2764   inline void z_vslb(   VectorRegister v1, VectorRegister v2, VectorRegister v3);
2765   inline void z_vsldb(  VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4);
2766 
2767   inline void z_vsra(   VectorRegister v1, VectorRegister v2, VectorRegister v3);
2768   inline void z_vsrab(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2769   inline void z_vsrl(   VectorRegister v1, VectorRegister v2, VectorRegister v3);
2770   inline void z_vsrlb(  VectorRegister v1, VectorRegister v2, VectorRegister v3);
2771 
2772   // Test under Mask
2773   inline void z_vtm(    VectorRegister v1, VectorRegister v2);
2774 
2775 
2776   // Floatingpoint instructions
2777   // ==========================
2778 
2779   // compare instructions
2780   inline void z_cebr(FloatRegister r1, FloatRegister r2);                     // compare (r1, r2)                ; float
2781   inline void z_ceb(FloatRegister r1, int64_t d2, Register x2, Register b2);  // compare (r1, *(d2_imm12+x2+b2)) ; float
2782   inline void z_ceb(FloatRegister r1, const Address &a);                      // compare (r1, *(d2_imm12+x2+b2)) ; float
2783   inline void z_cdbr(FloatRegister r1, FloatRegister r2);                     // compare (r1, r2)                ; double
2784   inline void z_cdb(FloatRegister r1, int64_t d2, Register x2, Register b2);  // compare (r1, *(d2_imm12+x2+b2)) ; double
2785   inline void z_cdb(FloatRegister r1, const Address &a);                      // compare (r1, *(d2_imm12+x2+b2)) ; double
2786 
2787   // load instructions
2788   inline void z_le( FloatRegister r1, int64_t d2, Register x2, Register b2);   // load r1 = *(d2_uimm12+x2+b2) ; float
2789   inline void z_ley(FloatRegister r1, int64_t d2, Register x2, Register b2);   // load r1 = *(d2_imm20+x2+b2)  ; float
2790   inline void z_ld( FloatRegister r1, int64_t d2, Register x2, Register b2);   // load r1 = *(d2_uimm12+x2+b2) ; double
2791   inline void z_ldy(FloatRegister r1, int64_t d2, Register x2, Register b2);   // load r1 = *(d2_imm20+x2+b2)  ; double
2792   inline void z_le( FloatRegister r1, const Address &a);                       // load r1 = *(a)               ; float
2793   inline void z_ley(FloatRegister r1, const Address &a);                       // load r1 = *(a)               ; float


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