1 /* 2 * Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2016, 2017 SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef CPU_S390_VM_ASSEMBLER_S390_HPP 27 #define CPU_S390_VM_ASSEMBLER_S390_HPP 28 29 #undef LUCY_DBG 30 31 // Immediate is an abstraction to represent the various immediate 32 // operands which exist on z/Architecture. Neither this class nor 33 // instances hereof have an own state. It consists of methods only. 34 class Immediate VALUE_OBJ_CLASS_SPEC { 35 36 public: 37 static bool is_simm(int64_t x, unsigned int nbits) { 38 // nbits < 2 --> false 39 // nbits >= 64 --> true 40 assert(2 <= nbits && nbits < 64, "Don't call, use statically known result."); 41 const int64_t min = -(1L << (nbits-1)); 42 const int64_t maxplus1 = (1L << (nbits-1)); 43 return min <= x && x < maxplus1; 44 } 45 static bool is_simm32(int64_t x) { 46 return is_simm(x, 32); 47 } 48 static bool is_simm20(int64_t x) { 49 return is_simm(x, 20); 50 } 51 static bool is_simm16(int64_t x) { 52 return is_simm(x, 16); 53 } 54 static bool is_simm8(int64_t x) { 55 return is_simm(x, 8); 56 } 57 58 // Test if x is within signed immediate range for nbits. 59 static bool is_uimm(int64_t x, unsigned int nbits) { 60 // nbits == 0 --> false 61 // nbits >= 64 --> true 62 assert(1 <= nbits && nbits < 64, "don't call, use statically known result"); 63 const uint64_t xu = (unsigned long)x; 64 const uint64_t maxplus1 = 1UL << nbits; 65 return xu < maxplus1; // Unsigned comparison. Negative inputs appear to be very large. 66 } 67 static bool is_uimm32(int64_t x) { 68 return is_uimm(x, 32); 69 } 70 static bool is_uimm16(int64_t x) { 71 return is_uimm(x, 16); 72 } 73 static bool is_uimm12(int64_t x) { 74 return is_uimm(x, 12); 75 } 76 static bool is_uimm8(int64_t x) { 77 return is_uimm(x, 8); 78 } 79 }; 80 81 // Displacement is an abstraction to represent the various 82 // displacements which exist with addresses on z/ArchiTecture. 83 // Neither this class nor instances hereof have an own state. It 84 // consists of methods only. 85 class Displacement VALUE_OBJ_CLASS_SPEC { 86 87 public: // These tests are used outside the (Macro)Assembler world, e.g. in ad-file. 88 89 static bool is_longDisp(int64_t x) { // Fits in a 20-bit displacement field. 90 return Immediate::is_simm20(x); 91 } 92 static bool is_shortDisp(int64_t x) { // Fits in a 12-bit displacement field. 93 return Immediate::is_uimm12(x); 94 } 95 static bool is_validDisp(int64_t x) { // Is a valid displacement, regardless of length constraints. 96 return is_longDisp(x); 97 } 98 }; 99 100 // RelAddr is an abstraction to represent relative addresses in the 101 // form they are used on z/Architecture for instructions which access 102 // their operand with pc-relative addresses. Neither this class nor 103 // instances hereof have an own state. It consists of methods only. 104 class RelAddr VALUE_OBJ_CLASS_SPEC { 105 106 private: // No public use at all. Solely for (Macro)Assembler. 107 108 static bool is_in_range_of_RelAddr(address target, address pc, bool shortForm) { 109 // Guard against illegal branch targets, e.g. -1. Occurrences in 110 // CompiledStaticCall and ad-file. Do not assert (it's a test 111 // function!). Just return false in case of illegal operands. 112 if ((((uint64_t)target) & 0x0001L) != 0) return false; 113 if ((((uint64_t)pc) & 0x0001L) != 0) return false; 114 115 if (shortForm) { 116 return Immediate::is_simm((int64_t)(target-pc), 17); // Relative short addresses can reach +/- 2**16 bytes. 117 } else { 118 return Immediate::is_simm((int64_t)(target-pc), 33); // Relative long addresses can reach +/- 2**32 bytes. 119 } 120 } 121 122 static bool is_in_range_of_RelAddr16(address target, address pc) { 123 return is_in_range_of_RelAddr(target, pc, true); 124 } 125 static bool is_in_range_of_RelAddr16(ptrdiff_t distance) { 126 return is_in_range_of_RelAddr((address)distance, 0, true); 127 } 128 129 static bool is_in_range_of_RelAddr32(address target, address pc) { 130 return is_in_range_of_RelAddr(target, pc, false); 131 } 132 static bool is_in_range_of_RelAddr32(ptrdiff_t distance) { 133 return is_in_range_of_RelAddr((address)distance, 0, false); 134 } 135 136 static int pcrel_off(address target, address pc, bool shortForm) { 137 assert(((uint64_t)target & 0x0001L) == 0, "target of a relative address must be aligned"); 138 assert(((uint64_t)pc & 0x0001L) == 0, "origin of a relative address must be aligned"); 139 140 if ((target == NULL) || (target == pc)) { 141 return 0; // Yet unknown branch destination. 142 } else { 143 guarantee(is_in_range_of_RelAddr(target, pc, shortForm), "target not within reach"); 144 return (int)((target - pc)>>1); 145 } 146 } 147 148 static int pcrel_off16(address target, address pc) { 149 return pcrel_off(target, pc, true); 150 } 151 static int pcrel_off16(ptrdiff_t distance) { 152 return pcrel_off((address)distance, 0, true); 153 } 154 155 static int pcrel_off32(address target, address pc) { 156 return pcrel_off(target, pc, false); 157 } 158 static int pcrel_off32(ptrdiff_t distance) { 159 return pcrel_off((address)distance, 0, false); 160 } 161 162 static ptrdiff_t inv_pcrel_off16(int offset) { 163 return ((ptrdiff_t)offset)<<1; 164 } 165 166 static ptrdiff_t inv_pcrel_off32(int offset) { 167 return ((ptrdiff_t)offset)<<1; 168 } 169 170 friend class Assembler; 171 friend class MacroAssembler; 172 friend class NativeGeneralJump; 173 }; 174 175 // Address is an abstraction used to represent a memory location 176 // as passed to Z assembler instructions. 177 // 178 // Note: A register location is represented via a Register, not 179 // via an address for efficiency & simplicity reasons. 180 class Address VALUE_OBJ_CLASS_SPEC { 181 private: 182 Register _base; // Base register. 183 Register _index; // Index register 184 intptr_t _disp; // Constant displacement. 185 186 public: 187 Address() : 188 _base(noreg), 189 _index(noreg), 190 _disp(0) {} 191 192 Address(Register base, Register index, intptr_t disp = 0) : 193 _base(base), 194 _index(index), 195 _disp(disp) {} 196 197 Address(Register base, intptr_t disp = 0) : 198 _base(base), 199 _index(noreg), 200 _disp(disp) {} 201 202 Address(Register base, RegisterOrConstant roc, intptr_t disp = 0) : 203 _base(base), 204 _index(noreg), 205 _disp(disp) { 206 if (roc.is_constant()) _disp += roc.as_constant(); else _index = roc.as_register(); 207 } 208 209 #ifdef ASSERT 210 // ByteSize is only a class when ASSERT is defined, otherwise it's an int. 211 Address(Register base, ByteSize disp) : 212 _base(base), 213 _index(noreg), 214 _disp(in_bytes(disp)) {} 215 216 Address(Register base, Register index, ByteSize disp) : 217 _base(base), 218 _index(index), 219 _disp(in_bytes(disp)) {} 220 #endif 221 222 // Aborts if disp is a register and base and index are set already. 223 Address plus_disp(RegisterOrConstant disp) const { 224 Address a = (*this); 225 a._disp += disp.constant_or_zero(); 226 if (disp.is_register()) { 227 if (a._index == noreg) { 228 a._index = disp.as_register(); 229 } else { 230 guarantee(_base == noreg, "can not encode"); a._base = disp.as_register(); 231 } 232 } 233 return a; 234 } 235 236 // A call to this is generated by adlc for replacement variable $xxx$$Address. 237 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc); 238 239 bool is_same_address(Address a) const { 240 return _base == a._base && _index == a._index && _disp == a._disp; 241 } 242 243 // testers 244 bool has_base() const { return _base != noreg; } 245 bool has_index() const { return _index != noreg; } 246 bool has_disp() const { return true; } // There is no "invalid" value. 247 248 bool is_disp12() const { return Immediate::is_uimm12(disp()); } 249 bool is_disp20() const { return Immediate::is_simm20(disp()); } 250 bool is_RSform() { return has_base() && !has_index() && is_disp12(); } 251 bool is_RSYform() { return has_base() && !has_index() && is_disp20(); } 252 bool is_RXform() { return has_base() && has_index() && is_disp12(); } 253 bool is_RXYform() { return has_base() && has_index() && is_disp20(); } 254 255 bool uses(Register r) { return _base == r || _index == r; }; 256 257 // accessors 258 Register base() const { return _base; } 259 Register baseOrR0() const { assert(_base != Z_R0, ""); return _base == noreg ? Z_R0 : _base; } 260 Register index() const { return _index; } 261 Register indexOrR0() const { assert(_index != Z_R0, ""); return _index == noreg ? Z_R0 : _index; } 262 intptr_t disp() const { return _disp; } 263 // Specific version for short displacement instructions. 264 int disp12() const { 265 assert(is_disp12(), "displacement out of range for uimm12"); 266 return _disp; 267 } 268 // Specific version for long displacement instructions. 269 int disp20() const { 270 assert(is_disp20(), "displacement out of range for simm20"); 271 return _disp; 272 } 273 intptr_t value() const { return _disp; } 274 275 friend class Assembler; 276 }; 277 278 class AddressLiteral VALUE_OBJ_CLASS_SPEC { 279 private: 280 address _address; 281 RelocationHolder _rspec; 282 283 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) { 284 switch (rtype) { 285 case relocInfo::external_word_type: 286 return external_word_Relocation::spec(addr); 287 case relocInfo::internal_word_type: 288 return internal_word_Relocation::spec(addr); 289 case relocInfo::opt_virtual_call_type: 290 return opt_virtual_call_Relocation::spec(); 291 case relocInfo::static_call_type: 292 return static_call_Relocation::spec(); 293 case relocInfo::runtime_call_w_cp_type: 294 return runtime_call_w_cp_Relocation::spec(); 295 case relocInfo::none: 296 return RelocationHolder(); 297 default: 298 ShouldNotReachHere(); 299 return RelocationHolder(); 300 } 301 } 302 303 protected: 304 // creation 305 AddressLiteral() : _address(NULL), _rspec(NULL) {} 306 307 public: 308 AddressLiteral(address addr, RelocationHolder const& rspec) 309 : _address(addr), 310 _rspec(rspec) {} 311 312 // Some constructors to avoid casting at the call site. 313 AddressLiteral(jobject obj, RelocationHolder const& rspec) 314 : _address((address) obj), 315 _rspec(rspec) {} 316 317 AddressLiteral(intptr_t value, RelocationHolder const& rspec) 318 : _address((address) value), 319 _rspec(rspec) {} 320 321 AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none) 322 : _address((address) addr), 323 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 324 325 // Some constructors to avoid casting at the call site. 326 AddressLiteral(address* addr, relocInfo::relocType rtype = relocInfo::none) 327 : _address((address) addr), 328 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 329 330 AddressLiteral(bool* addr, relocInfo::relocType rtype = relocInfo::none) 331 : _address((address) addr), 332 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 333 334 AddressLiteral(const bool* addr, relocInfo::relocType rtype = relocInfo::none) 335 : _address((address) addr), 336 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 337 338 AddressLiteral(signed char* addr, relocInfo::relocType rtype = relocInfo::none) 339 : _address((address) addr), 340 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 341 342 AddressLiteral(int* addr, relocInfo::relocType rtype = relocInfo::none) 343 : _address((address) addr), 344 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 345 346 AddressLiteral(intptr_t addr, relocInfo::relocType rtype = relocInfo::none) 347 : _address((address) addr), 348 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 349 350 AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none) 351 : _address((address) addr), 352 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 353 354 AddressLiteral(oop addr, relocInfo::relocType rtype = relocInfo::none) 355 : _address((address) addr), 356 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 357 358 AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none) 359 : _address((address) addr), 360 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 361 362 AddressLiteral(float* addr, relocInfo::relocType rtype = relocInfo::none) 363 : _address((address) addr), 364 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 365 366 AddressLiteral(double* addr, relocInfo::relocType rtype = relocInfo::none) 367 : _address((address) addr), 368 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 369 370 intptr_t value() const { return (intptr_t) _address; } 371 372 const relocInfo::relocType rtype() const { return _rspec.type(); } 373 const RelocationHolder& rspec() const { return _rspec; } 374 375 RelocationHolder rspec(int offset) const { 376 return offset == 0 ? _rspec : _rspec.plus(offset); 377 } 378 }; 379 380 // Convenience classes 381 class ExternalAddress: public AddressLiteral { 382 private: 383 static relocInfo::relocType reloc_for_target(address target) { 384 // Sometimes ExternalAddress is used for values which aren't 385 // exactly addresses, like the card table base. 386 // External_word_type can't be used for values in the first page 387 // so just skip the reloc in that case. 388 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; 389 } 390 391 public: 392 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target( target)) {} 393 ExternalAddress(oop* target) : AddressLiteral(target, reloc_for_target((address) target)) {} 394 }; 395 396 // Argument is an abstraction used to represent an outgoing actual 397 // argument or an incoming formal parameter, whether it resides in 398 // memory or in a register, in a manner consistent with the 399 // z/Architecture Application Binary Interface, or ABI. This is often 400 // referred to as the native or C calling convention. 401 class Argument VALUE_OBJ_CLASS_SPEC { 402 private: 403 int _number; 404 bool _is_in; 405 406 public: 407 enum { 408 // Only 5 registers may contain integer parameters. 409 n_register_parameters = 5, 410 // Can have up to 4 floating registers. 411 n_float_register_parameters = 4 412 }; 413 414 // creation 415 Argument(int number, bool is_in) : _number(number), _is_in(is_in) {} 416 Argument(int number) : _number(number) {} 417 418 int number() const { return _number; } 419 420 Argument successor() const { return Argument(number() + 1); } 421 422 // Locating register-based arguments: 423 bool is_register() const { return _number < n_register_parameters; } 424 425 // Locating Floating Point register-based arguments: 426 bool is_float_register() const { return _number < n_float_register_parameters; } 427 428 FloatRegister as_float_register() const { 429 assert(is_float_register(), "must be a register argument"); 430 return as_FloatRegister((number() *2) + 1); 431 } 432 433 FloatRegister as_double_register() const { 434 assert(is_float_register(), "must be a register argument"); 435 return as_FloatRegister((number() *2)); 436 } 437 438 Register as_register() const { 439 assert(is_register(), "must be a register argument"); 440 return as_Register(number() + Z_ARG1->encoding()); 441 } 442 443 // debugging 444 const char* name() const; 445 446 friend class Assembler; 447 }; 448 449 450 // The z/Architecture Assembler: Pure assembler doing NO optimizations 451 // on the instruction level; i.e., what you write is what you get. The 452 // Assembler is generating code into a CodeBuffer. 453 class Assembler : public AbstractAssembler { 454 protected: 455 456 friend class AbstractAssembler; 457 friend class AddressLiteral; 458 459 // Code patchers need various routines like inv_wdisp(). 460 friend class NativeInstruction; 461 #ifndef COMPILER2 462 friend class NativeGeneralJump; 463 #endif 464 friend class Relocation; 465 466 public: 467 468 // Addressing 469 470 // address calculation 471 #define LA_ZOPC (unsigned int)(0x41 << 24) 472 #define LAY_ZOPC (unsigned long)(0xe3L << 40 | 0x71L) 473 #define LARL_ZOPC (unsigned long)(0xc0L << 40 | 0x00L << 32) 474 475 476 // Data Transfer 477 478 // register to register transfer 479 #define LR_ZOPC (unsigned int)(24 << 8) 480 #define LBR_ZOPC (unsigned int)(0xb926 << 16) 481 #define LHR_ZOPC (unsigned int)(0xb927 << 16) 482 #define LGBR_ZOPC (unsigned int)(0xb906 << 16) 483 #define LGHR_ZOPC (unsigned int)(0xb907 << 16) 484 #define LGFR_ZOPC (unsigned int)(0xb914 << 16) 485 #define LGR_ZOPC (unsigned int)(0xb904 << 16) 486 487 #define LLHR_ZOPC (unsigned int)(0xb995 << 16) 488 #define LLGCR_ZOPC (unsigned int)(0xb984 << 16) 489 #define LLGHR_ZOPC (unsigned int)(0xb985 << 16) 490 #define LLGTR_ZOPC (unsigned int)(185 << 24 | 23 << 16) 491 #define LLGFR_ZOPC (unsigned int)(185 << 24 | 22 << 16) 492 493 #define LTR_ZOPC (unsigned int)(18 << 8) 494 #define LTGFR_ZOPC (unsigned int)(185 << 24 | 18 << 16) 495 #define LTGR_ZOPC (unsigned int)(185 << 24 | 2 << 16) 496 497 #define LER_ZOPC (unsigned int)(56 << 8) 498 #define LEDBR_ZOPC (unsigned int)(179 << 24 | 68 << 16) 499 #define LEXBR_ZOPC (unsigned int)(179 << 24 | 70 << 16) 500 #define LDEBR_ZOPC (unsigned int)(179 << 24 | 4 << 16) 501 #define LDR_ZOPC (unsigned int)(40 << 8) 502 #define LDXBR_ZOPC (unsigned int)(179 << 24 | 69 << 16) 503 #define LXEBR_ZOPC (unsigned int)(179 << 24 | 6 << 16) 504 #define LXDBR_ZOPC (unsigned int)(179 << 24 | 5 << 16) 505 #define LXR_ZOPC (unsigned int)(179 << 24 | 101 << 16) 506 #define LTEBR_ZOPC (unsigned int)(179 << 24 | 2 << 16) 507 #define LTDBR_ZOPC (unsigned int)(179 << 24 | 18 << 16) 508 #define LTXBR_ZOPC (unsigned int)(179 << 24 | 66 << 16) 509 510 #define LRVR_ZOPC (unsigned int)(0xb91f << 16) 511 #define LRVGR_ZOPC (unsigned int)(0xb90f << 16) 512 513 #define LDGR_ZOPC (unsigned int)(0xb3c1 << 16) // z10 514 #define LGDR_ZOPC (unsigned int)(0xb3cd << 16) // z10 515 516 #define LOCR_ZOPC (unsigned int)(0xb9f2 << 16) // z196 517 #define LOCGR_ZOPC (unsigned int)(0xb9e2 << 16) // z196 518 519 // immediate to register transfer 520 #define IIHH_ZOPC (unsigned int)(165 << 24) 521 #define IIHL_ZOPC (unsigned int)(165 << 24 | 1 << 16) 522 #define IILH_ZOPC (unsigned int)(165 << 24 | 2 << 16) 523 #define IILL_ZOPC (unsigned int)(165 << 24 | 3 << 16) 524 #define IIHF_ZOPC (unsigned long)(0xc0L << 40 | 8L << 32) 525 #define IILF_ZOPC (unsigned long)(0xc0L << 40 | 9L << 32) 526 #define LLIHH_ZOPC (unsigned int)(165 << 24 | 12 << 16) 527 #define LLIHL_ZOPC (unsigned int)(165 << 24 | 13 << 16) 528 #define LLILH_ZOPC (unsigned int)(165 << 24 | 14 << 16) 529 #define LLILL_ZOPC (unsigned int)(165 << 24 | 15 << 16) 530 #define LLIHF_ZOPC (unsigned long)(0xc0L << 40 | 14L << 32) 531 #define LLILF_ZOPC (unsigned long)(0xc0L << 40 | 15L << 32) 532 #define LHI_ZOPC (unsigned int)(167 << 24 | 8 << 16) 533 #define LGHI_ZOPC (unsigned int)(167 << 24 | 9 << 16) 534 #define LGFI_ZOPC (unsigned long)(0xc0L << 40 | 1L << 32) 535 536 #define LZER_ZOPC (unsigned int)(0xb374 << 16) 537 #define LZDR_ZOPC (unsigned int)(0xb375 << 16) 538 539 // LOAD: memory to register transfer 540 #define LB_ZOPC (unsigned long)(227L << 40 | 118L) 541 #define LH_ZOPC (unsigned int)(72 << 24) 542 #define LHY_ZOPC (unsigned long)(227L << 40 | 120L) 543 #define L_ZOPC (unsigned int)(88 << 24) 544 #define LY_ZOPC (unsigned long)(227L << 40 | 88L) 545 #define LT_ZOPC (unsigned long)(0xe3L << 40 | 0x12L) 546 #define LGB_ZOPC (unsigned long)(227L << 40 | 119L) 547 #define LGH_ZOPC (unsigned long)(227L << 40 | 21L) 548 #define LGF_ZOPC (unsigned long)(227L << 40 | 20L) 549 #define LG_ZOPC (unsigned long)(227L << 40 | 4L) 550 #define LTG_ZOPC (unsigned long)(0xe3L << 40 | 0x02L) 551 #define LTGF_ZOPC (unsigned long)(0xe3L << 40 | 0x32L) 552 553 #define LLC_ZOPC (unsigned long)(0xe3L << 40 | 0x94L) 554 #define LLH_ZOPC (unsigned long)(0xe3L << 40 | 0x95L) 555 #define LLGT_ZOPC (unsigned long)(227L << 40 | 23L) 556 #define LLGC_ZOPC (unsigned long)(227L << 40 | 144L) 557 #define LLGH_ZOPC (unsigned long)(227L << 40 | 145L) 558 #define LLGF_ZOPC (unsigned long)(227L << 40 | 22L) 559 560 #define IC_ZOPC (unsigned int)(0x43 << 24) 561 #define ICY_ZOPC (unsigned long)(0xe3L << 40 | 0x73L) 562 #define ICM_ZOPC (unsigned int)(0xbf << 24) 563 #define ICMY_ZOPC (unsigned long)(0xebL << 40 | 0x81L) 564 #define ICMH_ZOPC (unsigned long)(0xebL << 40 | 0x80L) 565 566 #define LRVH_ZOPC (unsigned long)(0xe3L << 40 | 0x1fL) 567 #define LRV_ZOPC (unsigned long)(0xe3L << 40 | 0x1eL) 568 #define LRVG_ZOPC (unsigned long)(0xe3L << 40 | 0x0fL) 569 570 571 // LOAD relative: memory to register transfer 572 #define LHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x05L << 32) // z10 573 #define LRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0dL << 32) // z10 574 #define LGHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x04L << 32) // z10 575 #define LGFRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0cL << 32) // z10 576 #define LGRL_ZOPC (unsigned long)(0xc4L << 40 | 0x08L << 32) // z10 577 578 #define LLHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x02L << 32) // z10 579 #define LLGHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x06L << 32) // z10 580 #define LLGFRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0eL << 32) // z10 581 582 #define LOC_ZOPC (unsigned long)(0xebL << 40 | 0xf2L) // z196 583 #define LOCG_ZOPC (unsigned long)(0xebL << 40 | 0xe2L) // z196 584 585 #define LMG_ZOPC (unsigned long)(235L << 40 | 4L) 586 587 #define LE_ZOPC (unsigned int)(0x78 << 24) 588 #define LEY_ZOPC (unsigned long)(237L << 40 | 100L) 589 #define LDEB_ZOPC (unsigned long)(237L << 40 | 4) 590 #define LD_ZOPC (unsigned int)(0x68 << 24) 591 #define LDY_ZOPC (unsigned long)(237L << 40 | 101L) 592 #define LXEB_ZOPC (unsigned long)(237L << 40 | 6) 593 #define LXDB_ZOPC (unsigned long)(237L << 40 | 5) 594 595 // STORE: register to memory transfer 596 #define STC_ZOPC (unsigned int)(0x42 << 24) 597 #define STCY_ZOPC (unsigned long)(227L << 40 | 114L) 598 #define STH_ZOPC (unsigned int)(64 << 24) 599 #define STHY_ZOPC (unsigned long)(227L << 40 | 112L) 600 #define ST_ZOPC (unsigned int)(80 << 24) 601 #define STY_ZOPC (unsigned long)(227L << 40 | 80L) 602 #define STG_ZOPC (unsigned long)(227L << 40 | 36L) 603 604 #define STCM_ZOPC (unsigned long)(0xbeL << 24) 605 #define STCMY_ZOPC (unsigned long)(0xebL << 40 | 0x2dL) 606 #define STCMH_ZOPC (unsigned long)(0xebL << 40 | 0x2cL) 607 608 // STORE relative: memory to register transfer 609 #define STHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x07L << 32) // z10 610 #define STRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0fL << 32) // z10 611 #define STGRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0bL << 32) // z10 612 613 #define STOC_ZOPC (unsigned long)(0xebL << 40 | 0xf3L) // z196 614 #define STOCG_ZOPC (unsigned long)(0xebL << 40 | 0xe3L) // z196 615 616 #define STMG_ZOPC (unsigned long)(235L << 40 | 36L) 617 618 #define STE_ZOPC (unsigned int)(0x70 << 24) 619 #define STEY_ZOPC (unsigned long)(237L << 40 | 102L) 620 #define STD_ZOPC (unsigned int)(0x60 << 24) 621 #define STDY_ZOPC (unsigned long)(237L << 40 | 103L) 622 623 // MOVE: immediate to memory transfer 624 #define MVHHI_ZOPC (unsigned long)(0xe5L << 40 | 0x44L << 32) // z10 625 #define MVHI_ZOPC (unsigned long)(0xe5L << 40 | 0x4cL << 32) // z10 626 #define MVGHI_ZOPC (unsigned long)(0xe5L << 40 | 0x48L << 32) // z10 627 628 629 // ALU operations 630 631 // Load Positive 632 #define LPR_ZOPC (unsigned int)(16 << 8) 633 #define LPGFR_ZOPC (unsigned int)(185 << 24 | 16 << 16) 634 #define LPGR_ZOPC (unsigned int)(185 << 24) 635 #define LPEBR_ZOPC (unsigned int)(179 << 24) 636 #define LPDBR_ZOPC (unsigned int)(179 << 24 | 16 << 16) 637 #define LPXBR_ZOPC (unsigned int)(179 << 24 | 64 << 16) 638 639 // Load Negative 640 #define LNR_ZOPC (unsigned int)(17 << 8) 641 #define LNGFR_ZOPC (unsigned int)(185 << 24 | 17 << 16) 642 #define LNGR_ZOPC (unsigned int)(185 << 24 | 1 << 16) 643 #define LNEBR_ZOPC (unsigned int)(179 << 24 | 1 << 16) 644 #define LNDBR_ZOPC (unsigned int)(179 << 24 | 17 << 16) 645 #define LNXBR_ZOPC (unsigned int)(179 << 24 | 65 << 16) 646 647 // Load Complement 648 #define LCR_ZOPC (unsigned int)(19 << 8) 649 #define LCGFR_ZOPC (unsigned int)(185 << 24 | 19 << 16) 650 #define LCGR_ZOPC (unsigned int)(185 << 24 | 3 << 16) 651 #define LCEBR_ZOPC (unsigned int)(179 << 24 | 3 << 16) 652 #define LCDBR_ZOPC (unsigned int)(179 << 24 | 19 << 16) 653 #define LCXBR_ZOPC (unsigned int)(179 << 24 | 67 << 16) 654 655 // Add 656 // RR, signed 657 #define AR_ZOPC (unsigned int)(26 << 8) 658 #define AGFR_ZOPC (unsigned int)(0xb9 << 24 | 0x18 << 16) 659 #define AGR_ZOPC (unsigned int)(0xb9 << 24 | 0x08 << 16) 660 // RRF, signed 661 #define ARK_ZOPC (unsigned int)(0xb9 << 24 | 0x00f8 << 16) 662 #define AGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00e8 << 16) 663 // RI, signed 664 #define AHI_ZOPC (unsigned int)(167 << 24 | 10 << 16) 665 #define AFI_ZOPC (unsigned long)(0xc2L << 40 | 9L << 32) 666 #define AGHI_ZOPC (unsigned int)(167 << 24 | 11 << 16) 667 #define AGFI_ZOPC (unsigned long)(0xc2L << 40 | 8L << 32) 668 // RIE, signed 669 #define AHIK_ZOPC (unsigned long)(0xecL << 40 | 0x00d8L) 670 #define AGHIK_ZOPC (unsigned long)(0xecL << 40 | 0x00d9L) 671 #define AIH_ZOPC (unsigned long)(0xccL << 40 | 0x08L << 32) 672 // RM, signed 673 #define AHY_ZOPC (unsigned long)(227L << 40 | 122L) 674 #define A_ZOPC (unsigned int)(90 << 24) 675 #define AY_ZOPC (unsigned long)(227L << 40 | 90L) 676 #define AGF_ZOPC (unsigned long)(227L << 40 | 24L) 677 #define AG_ZOPC (unsigned long)(227L << 40 | 8L) 678 // In-memory arithmetic (add signed, add logical with signed immediate). 679 // MI, signed 680 #define ASI_ZOPC (unsigned long)(0xebL << 40 | 0x6aL) 681 #define AGSI_ZOPC (unsigned long)(0xebL << 40 | 0x7aL) 682 683 // RR, Logical 684 #define ALR_ZOPC (unsigned int)(30 << 8) 685 #define ALGFR_ZOPC (unsigned int)(185 << 24 | 26 << 16) 686 #define ALGR_ZOPC (unsigned int)(185 << 24 | 10 << 16) 687 #define ALCGR_ZOPC (unsigned int)(185 << 24 | 136 << 16) 688 // RRF, Logical 689 #define ALRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00fa << 16) 690 #define ALGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00ea << 16) 691 // RI, Logical 692 #define ALFI_ZOPC (unsigned long)(0xc2L << 40 | 0x0bL << 32) 693 #define ALGFI_ZOPC (unsigned long)(0xc2L << 40 | 0x0aL << 32) 694 // RIE, Logical 695 #define ALHSIK_ZOPC (unsigned long)(0xecL << 40 | 0x00daL) 696 #define ALGHSIK_ZOPC (unsigned long)(0xecL << 40 | 0x00dbL) 697 // RM, Logical 698 #define AL_ZOPC (unsigned int)(0x5e << 24) 699 #define ALY_ZOPC (unsigned long)(227L << 40 | 94L) 700 #define ALGF_ZOPC (unsigned long)(227L << 40 | 26L) 701 #define ALG_ZOPC (unsigned long)(227L << 40 | 10L) 702 // In-memory arithmetic (add signed, add logical with signed immediate). 703 // MI, Logical 704 #define ALSI_ZOPC (unsigned long)(0xebL << 40 | 0x6eL) 705 #define ALGSI_ZOPC (unsigned long)(0xebL << 40 | 0x7eL) 706 707 // RR, BFP 708 #define AEBR_ZOPC (unsigned int)(179 << 24 | 10 << 16) 709 #define ADBR_ZOPC (unsigned int)(179 << 24 | 26 << 16) 710 #define AXBR_ZOPC (unsigned int)(179 << 24 | 74 << 16) 711 // RM, BFP 712 #define AEB_ZOPC (unsigned long)(237L << 40 | 10) 713 #define ADB_ZOPC (unsigned long)(237L << 40 | 26) 714 715 // Subtract 716 // RR, signed 717 #define SR_ZOPC (unsigned int)(27 << 8) 718 #define SGFR_ZOPC (unsigned int)(185 << 24 | 25 << 16) 719 #define SGR_ZOPC (unsigned int)(185 << 24 | 9 << 16) 720 // RRF, signed 721 #define SRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00f9 << 16) 722 #define SGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00e9 << 16) 723 // RM, signed 724 #define SH_ZOPC (unsigned int)(0x4b << 24) 725 #define SHY_ZOPC (unsigned long)(227L << 40 | 123L) 726 #define S_ZOPC (unsigned int)(0x5B << 24) 727 #define SY_ZOPC (unsigned long)(227L << 40 | 91L) 728 #define SGF_ZOPC (unsigned long)(227L << 40 | 25) 729 #define SG_ZOPC (unsigned long)(227L << 40 | 9) 730 // RR, Logical 731 #define SLR_ZOPC (unsigned int)(31 << 8) 732 #define SLGFR_ZOPC (unsigned int)(185 << 24 | 27 << 16) 733 #define SLGR_ZOPC (unsigned int)(185 << 24 | 11 << 16) 734 // RIL, Logical 735 #define SLFI_ZOPC (unsigned long)(0xc2L << 40 | 0x05L << 32) 736 #define SLGFI_ZOPC (unsigned long)(0xc2L << 40 | 0x04L << 32) 737 // RRF, Logical 738 #define SLRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00fb << 16) 739 #define SLGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00eb << 16) 740 // RM, Logical 741 #define SLY_ZOPC (unsigned long)(227L << 40 | 95L) 742 #define SLGF_ZOPC (unsigned long)(227L << 40 | 27L) 743 #define SLG_ZOPC (unsigned long)(227L << 40 | 11L) 744 745 // RR, BFP 746 #define SEBR_ZOPC (unsigned int)(179 << 24 | 11 << 16) 747 #define SDBR_ZOPC (unsigned int)(179 << 24 | 27 << 16) 748 #define SXBR_ZOPC (unsigned int)(179 << 24 | 75 << 16) 749 // RM, BFP 750 #define SEB_ZOPC (unsigned long)(237L << 40 | 11) 751 #define SDB_ZOPC (unsigned long)(237L << 40 | 27) 752 753 // Multiply 754 // RR, signed 755 #define MR_ZOPC (unsigned int)(28 << 8) 756 #define MSR_ZOPC (unsigned int)(178 << 24 | 82 << 16) 757 #define MSGFR_ZOPC (unsigned int)(185 << 24 | 28 << 16) 758 #define MSGR_ZOPC (unsigned int)(185 << 24 | 12 << 16) 759 // RI, signed 760 #define MHI_ZOPC (unsigned int)(167 << 24 | 12 << 16) 761 #define MGHI_ZOPC (unsigned int)(167 << 24 | 13 << 16) 762 #define MSFI_ZOPC (unsigned long)(0xc2L << 40 | 0x01L << 32) // z10 763 #define MSGFI_ZOPC (unsigned long)(0xc2L << 40 | 0x00L << 32) // z10 764 // RM, signed 765 #define M_ZOPC (unsigned int)(92 << 24) 766 #define MS_ZOPC (unsigned int)(0x71 << 24) 767 #define MHY_ZOPC (unsigned long)(0xe3L<< 40 | 0x7cL) 768 #define MSY_ZOPC (unsigned long)(227L << 40 | 81L) 769 #define MSGF_ZOPC (unsigned long)(227L << 40 | 28L) 770 #define MSG_ZOPC (unsigned long)(227L << 40 | 12L) 771 // RR, unsigned 772 #define MLR_ZOPC (unsigned int)(185 << 24 | 150 << 16) 773 #define MLGR_ZOPC (unsigned int)(185 << 24 | 134 << 16) 774 // RM, unsigned 775 #define ML_ZOPC (unsigned long)(227L << 40 | 150L) 776 #define MLG_ZOPC (unsigned long)(227L << 40 | 134L) 777 778 // RR, BFP 779 #define MEEBR_ZOPC (unsigned int)(179 << 24 | 23 << 16) 780 #define MDEBR_ZOPC (unsigned int)(179 << 24 | 12 << 16) 781 #define MDBR_ZOPC (unsigned int)(179 << 24 | 28 << 16) 782 #define MXDBR_ZOPC (unsigned int)(179 << 24 | 7 << 16) 783 #define MXBR_ZOPC (unsigned int)(179 << 24 | 76 << 16) 784 // RM, BFP 785 #define MEEB_ZOPC (unsigned long)(237L << 40 | 23) 786 #define MDEB_ZOPC (unsigned long)(237L << 40 | 12) 787 #define MDB_ZOPC (unsigned long)(237L << 40 | 28) 788 #define MXDB_ZOPC (unsigned long)(237L << 40 | 7) 789 790 // Multiply-Add 791 #define MAEBR_ZOPC (unsigned int)(179 << 24 | 14 << 16) 792 #define MADBR_ZOPC (unsigned int)(179 << 24 | 30 << 16) 793 #define MSEBR_ZOPC (unsigned int)(179 << 24 | 15 << 16) 794 #define MSDBR_ZOPC (unsigned int)(179 << 24 | 31 << 16) 795 #define MAEB_ZOPC (unsigned long)(237L << 40 | 14) 796 #define MADB_ZOPC (unsigned long)(237L << 40 | 30) 797 #define MSEB_ZOPC (unsigned long)(237L << 40 | 15) 798 #define MSDB_ZOPC (unsigned long)(237L << 40 | 31) 799 800 // Divide 801 // RR, signed 802 #define DSGFR_ZOPC (unsigned int)(0xb91d << 16) 803 #define DSGR_ZOPC (unsigned int)(0xb90d << 16) 804 // RM, signed 805 #define D_ZOPC (unsigned int)(93 << 24) 806 #define DSGF_ZOPC (unsigned long)(227L << 40 | 29L) 807 #define DSG_ZOPC (unsigned long)(227L << 40 | 13L) 808 // RR, unsigned 809 #define DLR_ZOPC (unsigned int)(185 << 24 | 151 << 16) 810 #define DLGR_ZOPC (unsigned int)(185 << 24 | 135 << 16) 811 // RM, unsigned 812 #define DL_ZOPC (unsigned long)(227L << 40 | 151L) 813 #define DLG_ZOPC (unsigned long)(227L << 40 | 135L) 814 815 // RR, BFP 816 #define DEBR_ZOPC (unsigned int)(179 << 24 | 13 << 16) 817 #define DDBR_ZOPC (unsigned int)(179 << 24 | 29 << 16) 818 #define DXBR_ZOPC (unsigned int)(179 << 24 | 77 << 16) 819 // RM, BFP 820 #define DEB_ZOPC (unsigned long)(237L << 40 | 13) 821 #define DDB_ZOPC (unsigned long)(237L << 40 | 29) 822 823 // Square Root 824 // RR, BFP 825 #define SQEBR_ZOPC (unsigned int)(0xb314 << 16) 826 #define SQDBR_ZOPC (unsigned int)(0xb315 << 16) 827 #define SQXBR_ZOPC (unsigned int)(0xb316 << 16) 828 // RM, BFP 829 #define SQEB_ZOPC (unsigned long)(237L << 40 | 20) 830 #define SQDB_ZOPC (unsigned long)(237L << 40 | 21) 831 832 // Compare and Test 833 // RR, signed 834 #define CR_ZOPC (unsigned int)(25 << 8) 835 #define CGFR_ZOPC (unsigned int)(185 << 24 | 48 << 16) 836 #define CGR_ZOPC (unsigned int)(185 << 24 | 32 << 16) 837 // RI, signed 838 #define CHI_ZOPC (unsigned int)(167 << 24 | 14 << 16) 839 #define CFI_ZOPC (unsigned long)(0xc2L << 40 | 0xdL << 32) 840 #define CGHI_ZOPC (unsigned int)(167 << 24 | 15 << 16) 841 #define CGFI_ZOPC (unsigned long)(0xc2L << 40 | 0xcL << 32) 842 // RM, signed 843 #define CH_ZOPC (unsigned int)(0x49 << 24) 844 #define CHY_ZOPC (unsigned long)(227L << 40 | 121L) 845 #define C_ZOPC (unsigned int)(0x59 << 24) 846 #define CY_ZOPC (unsigned long)(227L << 40 | 89L) 847 #define CGF_ZOPC (unsigned long)(227L << 40 | 48L) 848 #define CG_ZOPC (unsigned long)(227L << 40 | 32L) 849 // RR, unsigned 850 #define CLR_ZOPC (unsigned int)(21 << 8) 851 #define CLGFR_ZOPC (unsigned int)(185 << 24 | 49 << 16) 852 #define CLGR_ZOPC (unsigned int)(185 << 24 | 33 << 16) 853 // RIL, unsigned 854 #define CLFI_ZOPC (unsigned long)(0xc2L << 40 | 0xfL << 32) 855 #define CLGFI_ZOPC (unsigned long)(0xc2L << 40 | 0xeL << 32) 856 // RM, unsigned 857 #define CL_ZOPC (unsigned int)(0x55 << 24) 858 #define CLY_ZOPC (unsigned long)(227L << 40 | 85L) 859 #define CLGF_ZOPC (unsigned long)(227L << 40 | 49L) 860 #define CLG_ZOPC (unsigned long)(227L << 40 | 33L) 861 // RI, unsigned 862 #define TMHH_ZOPC (unsigned int)(167 << 24 | 2 << 16) 863 #define TMHL_ZOPC (unsigned int)(167 << 24 | 3 << 16) 864 #define TMLH_ZOPC (unsigned int)(167 << 24) 865 #define TMLL_ZOPC (unsigned int)(167 << 24 | 1 << 16) 866 867 // RR, BFP 868 #define CEBR_ZOPC (unsigned int)(179 << 24 | 9 << 16) 869 #define CDBR_ZOPC (unsigned int)(179 << 24 | 25 << 16) 870 #define CXBR_ZOPC (unsigned int)(179 << 24 | 73 << 16) 871 // RM, BFP 872 #define CEB_ZOPC (unsigned long)(237L << 40 | 9) 873 #define CDB_ZOPC (unsigned long)(237L << 40 | 25) 874 875 // Shift 876 // arithmetic 877 #define SLA_ZOPC (unsigned int)(139 << 24) 878 #define SLAG_ZOPC (unsigned long)(235L << 40 | 11L) 879 #define SRA_ZOPC (unsigned int)(138 << 24) 880 #define SRAG_ZOPC (unsigned long)(235L << 40 | 10L) 881 // logical 882 #define SLL_ZOPC (unsigned int)(137 << 24) 883 #define SLLG_ZOPC (unsigned long)(235L << 40 | 13L) 884 #define SRL_ZOPC (unsigned int)(136 << 24) 885 #define SRLG_ZOPC (unsigned long)(235L << 40 | 12L) 886 887 // Rotate, then AND/XOR/OR/insert 888 // rotate 889 #define RLL_ZOPC (unsigned long)(0xebL << 40 | 0x1dL) // z10 890 #define RLLG_ZOPC (unsigned long)(0xebL << 40 | 0x1cL) // z10 891 // rotate and {AND|XOR|OR|INS} 892 #define RNSBG_ZOPC (unsigned long)(0xecL << 40 | 0x54L) // z196 893 #define RXSBG_ZOPC (unsigned long)(0xecL << 40 | 0x57L) // z196 894 #define ROSBG_ZOPC (unsigned long)(0xecL << 40 | 0x56L) // z196 895 #define RISBG_ZOPC (unsigned long)(0xecL << 40 | 0x55L) // z196 896 897 // AND 898 // RR, signed 899 #define NR_ZOPC (unsigned int)(20 << 8) 900 #define NGR_ZOPC (unsigned int)(185 << 24 | 128 << 16) 901 // RRF, signed 902 #define NRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00f4 << 16) 903 #define NGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00e4 << 16) 904 // RI, signed 905 #define NIHH_ZOPC (unsigned int)(165 << 24 | 4 << 16) 906 #define NIHL_ZOPC (unsigned int)(165 << 24 | 5 << 16) 907 #define NILH_ZOPC (unsigned int)(165 << 24 | 6 << 16) 908 #define NILL_ZOPC (unsigned int)(165 << 24 | 7 << 16) 909 #define NIHF_ZOPC (unsigned long)(0xc0L << 40 | 10L << 32) 910 #define NILF_ZOPC (unsigned long)(0xc0L << 40 | 11L << 32) 911 // RM, signed 912 #define N_ZOPC (unsigned int)(0x54 << 24) 913 #define NY_ZOPC (unsigned long)(227L << 40 | 84L) 914 #define NG_ZOPC (unsigned long)(227L << 40 | 128L) 915 916 // OR 917 // RR, signed 918 #define OR_ZOPC (unsigned int)(22 << 8) 919 #define OGR_ZOPC (unsigned int)(185 << 24 | 129 << 16) 920 // RRF, signed 921 #define ORK_ZOPC (unsigned int)(0xb9 << 24 | 0x00f6 << 16) 922 #define OGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00e6 << 16) 923 // RI, signed 924 #define OIHH_ZOPC (unsigned int)(165 << 24 | 8 << 16) 925 #define OIHL_ZOPC (unsigned int)(165 << 24 | 9 << 16) 926 #define OILH_ZOPC (unsigned int)(165 << 24 | 10 << 16) 927 #define OILL_ZOPC (unsigned int)(165 << 24 | 11 << 16) 928 #define OIHF_ZOPC (unsigned long)(0xc0L << 40 | 12L << 32) 929 #define OILF_ZOPC (unsigned long)(0xc0L << 40 | 13L << 32) 930 // RM, signed 931 #define O_ZOPC (unsigned int)(0x56 << 24) 932 #define OY_ZOPC (unsigned long)(227L << 40 | 86L) 933 #define OG_ZOPC (unsigned long)(227L << 40 | 129L) 934 935 // XOR 936 // RR, signed 937 #define XR_ZOPC (unsigned int)(23 << 8) 938 #define XGR_ZOPC (unsigned int)(185 << 24 | 130 << 16) 939 // RRF, signed 940 #define XRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00f7 << 16) 941 #define XGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00e7 << 16) 942 // RI, signed 943 #define XIHF_ZOPC (unsigned long)(0xc0L << 40 | 6L << 32) 944 #define XILF_ZOPC (unsigned long)(0xc0L << 40 | 7L << 32) 945 // RM, signed 946 #define X_ZOPC (unsigned int)(0x57 << 24) 947 #define XY_ZOPC (unsigned long)(227L << 40 | 87L) 948 #define XG_ZOPC (unsigned long)(227L << 40 | 130L) 949 950 951 // Data Conversion 952 953 // INT to BFP 954 #define CEFBR_ZOPC (unsigned int)(179 << 24 | 148 << 16) 955 #define CDFBR_ZOPC (unsigned int)(179 << 24 | 149 << 16) 956 #define CXFBR_ZOPC (unsigned int)(179 << 24 | 150 << 16) 957 #define CEGBR_ZOPC (unsigned int)(179 << 24 | 164 << 16) 958 #define CDGBR_ZOPC (unsigned int)(179 << 24 | 165 << 16) 959 #define CXGBR_ZOPC (unsigned int)(179 << 24 | 166 << 16) 960 // BFP to INT 961 #define CFEBR_ZOPC (unsigned int)(179 << 24 | 152 << 16) 962 #define CFDBR_ZOPC (unsigned int)(179 << 24 | 153 << 16) 963 #define CFXBR_ZOPC (unsigned int)(179 << 24 | 154 << 16) 964 #define CGEBR_ZOPC (unsigned int)(179 << 24 | 168 << 16) 965 #define CGDBR_ZOPC (unsigned int)(179 << 24 | 169 << 16) 966 #define CGXBR_ZOPC (unsigned int)(179 << 24 | 170 << 16) 967 // INT to DEC 968 #define CVD_ZOPC (unsigned int)(0x4e << 24) 969 #define CVDY_ZOPC (unsigned long)(0xe3L << 40 | 0x26L) 970 #define CVDG_ZOPC (unsigned long)(0xe3L << 40 | 0x2eL) 971 972 973 // BFP Control 974 975 #define SRNM_ZOPC (unsigned int)(178 << 24 | 153 << 16) 976 #define EFPC_ZOPC (unsigned int)(179 << 24 | 140 << 16) 977 #define SFPC_ZOPC (unsigned int)(179 << 24 | 132 << 16) 978 #define STFPC_ZOPC (unsigned int)(178 << 24 | 156 << 16) 979 #define LFPC_ZOPC (unsigned int)(178 << 24 | 157 << 16) 980 981 982 // Branch Instructions 983 984 // Register 985 #define BCR_ZOPC (unsigned int)(7 << 8) 986 #define BALR_ZOPC (unsigned int)(5 << 8) 987 #define BASR_ZOPC (unsigned int)(13 << 8) 988 #define BCTGR_ZOPC (unsigned long)(0xb946 << 16) 989 // Absolute 990 #define BC_ZOPC (unsigned int)(71 << 24) 991 #define BAL_ZOPC (unsigned int)(69 << 24) 992 #define BAS_ZOPC (unsigned int)(77 << 24) 993 #define BXH_ZOPC (unsigned int)(134 << 24) 994 #define BXHG_ZOPC (unsigned long)(235L << 40 | 68) 995 // Relative 996 #define BRC_ZOPC (unsigned int)(167 << 24 | 4 << 16) 997 #define BRCL_ZOPC (unsigned long)(192L << 40 | 4L << 32) 998 #define BRAS_ZOPC (unsigned int)(167 << 24 | 5 << 16) 999 #define BRASL_ZOPC (unsigned long)(192L << 40 | 5L << 32) 1000 #define BRCT_ZOPC (unsigned int)(167 << 24 | 6 << 16) 1001 #define BRCTG_ZOPC (unsigned int)(167 << 24 | 7 << 16) 1002 #define BRXH_ZOPC (unsigned int)(132 << 24) 1003 #define BRXHG_ZOPC (unsigned long)(236L << 40 | 68) 1004 #define BRXLE_ZOPC (unsigned int)(133 << 24) 1005 #define BRXLG_ZOPC (unsigned long)(236L << 40 | 69) 1006 1007 1008 // Compare and Branch Instructions 1009 1010 // signed comp reg/reg, branch Absolute 1011 #define CRB_ZOPC (unsigned long)(0xecL << 40 | 0xf6L) // z10 1012 #define CGRB_ZOPC (unsigned long)(0xecL << 40 | 0xe4L) // z10 1013 // signed comp reg/reg, branch Relative 1014 #define CRJ_ZOPC (unsigned long)(0xecL << 40 | 0x76L) // z10 1015 #define CGRJ_ZOPC (unsigned long)(0xecL << 40 | 0x64L) // z10 1016 // signed comp reg/imm, branch absolute 1017 #define CIB_ZOPC (unsigned long)(0xecL << 40 | 0xfeL) // z10 1018 #define CGIB_ZOPC (unsigned long)(0xecL << 40 | 0xfcL) // z10 1019 // signed comp reg/imm, branch relative 1020 #define CIJ_ZOPC (unsigned long)(0xecL << 40 | 0x7eL) // z10 1021 #define CGIJ_ZOPC (unsigned long)(0xecL << 40 | 0x7cL) // z10 1022 1023 // unsigned comp reg/reg, branch Absolute 1024 #define CLRB_ZOPC (unsigned long)(0xecL << 40 | 0xf7L) // z10 1025 #define CLGRB_ZOPC (unsigned long)(0xecL << 40 | 0xe5L) // z10 1026 // unsigned comp reg/reg, branch Relative 1027 #define CLRJ_ZOPC (unsigned long)(0xecL << 40 | 0x77L) // z10 1028 #define CLGRJ_ZOPC (unsigned long)(0xecL << 40 | 0x65L) // z10 1029 // unsigned comp reg/imm, branch absolute 1030 #define CLIB_ZOPC (unsigned long)(0xecL << 40 | 0xffL) // z10 1031 #define CLGIB_ZOPC (unsigned long)(0xecL << 40 | 0xfdL) // z10 1032 // unsigned comp reg/imm, branch relative 1033 #define CLIJ_ZOPC (unsigned long)(0xecL << 40 | 0x7fL) // z10 1034 #define CLGIJ_ZOPC (unsigned long)(0xecL << 40 | 0x7dL) // z10 1035 1036 // comp reg/reg, trap 1037 #define CRT_ZOPC (unsigned int)(0xb972 << 16) // z10 1038 #define CGRT_ZOPC (unsigned int)(0xb960 << 16) // z10 1039 #define CLRT_ZOPC (unsigned int)(0xb973 << 16) // z10 1040 #define CLGRT_ZOPC (unsigned int)(0xb961 << 16) // z10 1041 // comp reg/imm, trap 1042 #define CIT_ZOPC (unsigned long)(0xecL << 40 | 0x72L) // z10 1043 #define CGIT_ZOPC (unsigned long)(0xecL << 40 | 0x70L) // z10 1044 #define CLFIT_ZOPC (unsigned long)(0xecL << 40 | 0x73L) // z10 1045 #define CLGIT_ZOPC (unsigned long)(0xecL << 40 | 0x71L) // z10 1046 1047 1048 // Direct Memory Operations 1049 1050 // Compare 1051 #define CLI_ZOPC (unsigned int)(0x95 << 24) 1052 #define CLIY_ZOPC (unsigned long)(0xebL << 40 | 0x55L) 1053 #define CLC_ZOPC (unsigned long)(0xd5L << 40) 1054 #define CLCL_ZOPC (unsigned int)(0x0f << 8) 1055 #define CLCLE_ZOPC (unsigned int)(0xa9 << 24) 1056 #define CLCLU_ZOPC (unsigned long)(0xebL << 40 | 0x8fL) 1057 1058 // Move 1059 #define MVI_ZOPC (unsigned int)(0x92 << 24) 1060 #define MVIY_ZOPC (unsigned long)(0xebL << 40 | 0x52L) 1061 #define MVC_ZOPC (unsigned long)(0xd2L << 40) 1062 #define MVCL_ZOPC (unsigned int)(0x0e << 8) 1063 #define MVCLE_ZOPC (unsigned int)(0xa8 << 24) 1064 1065 // Test 1066 #define TM_ZOPC (unsigned int)(0x91 << 24) 1067 #define TMY_ZOPC (unsigned long)(0xebL << 40 | 0x51L) 1068 1069 // AND 1070 #define NI_ZOPC (unsigned int)(0x94 << 24) 1071 #define NIY_ZOPC (unsigned long)(0xebL << 40 | 0x54L) 1072 #define NC_ZOPC (unsigned long)(0xd4L << 40) 1073 1074 // OR 1075 #define OI_ZOPC (unsigned int)(0x96 << 24) 1076 #define OIY_ZOPC (unsigned long)(0xebL << 40 | 0x56L) 1077 #define OC_ZOPC (unsigned long)(0xd6L << 40) 1078 1079 // XOR 1080 #define XI_ZOPC (unsigned int)(0x97 << 24) 1081 #define XIY_ZOPC (unsigned long)(0xebL << 40 | 0x57L) 1082 #define XC_ZOPC (unsigned long)(0xd7L << 40) 1083 1084 // Search String 1085 #define SRST_ZOPC (unsigned int)(178 << 24 | 94 << 16) 1086 #define SRSTU_ZOPC (unsigned int)(185 << 24 | 190 << 16) 1087 1088 // Translate characters 1089 #define TROO_ZOPC (unsigned int)(0xb9 << 24 | 0x93 << 16) 1090 #define TROT_ZOPC (unsigned int)(0xb9 << 24 | 0x92 << 16) 1091 #define TRTO_ZOPC (unsigned int)(0xb9 << 24 | 0x91 << 16) 1092 #define TRTT_ZOPC (unsigned int)(0xb9 << 24 | 0x90 << 16) 1093 1094 1095 //--------------------------- 1096 //-- Vector Instructions -- 1097 //--------------------------- 1098 1099 //---< Vector Support Instructions >--- 1100 1101 //--- Load (memory) --- 1102 1103 #define VLM_ZOPC (unsigned long)(0xe7L << 40 | 0x36L << 0) // load full vreg range (n * 128 bit) 1104 #define VL_ZOPC (unsigned long)(0xe7L << 40 | 0x06L << 0) // load full vreg (128 bit) 1105 #define VLEB_ZOPC (unsigned long)(0xe7L << 40 | 0x00L << 0) // load vreg element (8 bit) 1106 #define VLEH_ZOPC (unsigned long)(0xe7L << 40 | 0x01L << 0) // load vreg element (16 bit) 1107 #define VLEF_ZOPC (unsigned long)(0xe7L << 40 | 0x03L << 0) // load vreg element (32 bit) 1108 #define VLEG_ZOPC (unsigned long)(0xe7L << 40 | 0x02L << 0) // load vreg element (64 bit) 1109 1110 #define VLREP_ZOPC (unsigned long)(0xe7L << 40 | 0x05L << 0) // load and replicate into all vector elements 1111 #define VLLEZ_ZOPC (unsigned long)(0xe7L << 40 | 0x04L << 0) // load logical element and zero. 1112 1113 // vector register gather 1114 #define VGEF_ZOPC (unsigned long)(0xe7L << 40 | 0x13L << 0) // gather element (32 bit), V1(M3) = [D2(V2(M3),B2)] 1115 #define VGEG_ZOPC (unsigned long)(0xe7L << 40 | 0x12L << 0) // gather element (64 bit), V1(M3) = [D2(V2(M3),B2)] 1116 // vector register scatter 1117 #define VSCEF_ZOPC (unsigned long)(0xe7L << 40 | 0x1bL << 0) // vector scatter element FW 1118 #define VSCEG_ZOPC (unsigned long)(0xe7L << 40 | 0x1aL << 0) // vector scatter element DW 1119 1120 #define VLBB_ZOPC (unsigned long)(0xe7L << 40 | 0x07L << 0) // load vreg to block boundary (load to alignment). 1121 #define VLL_ZOPC (unsigned long)(0xe7L << 40 | 0x37L << 0) // load vreg with length. 1122 1123 //--- Load (register) --- 1124 1125 #define VLR_ZOPC (unsigned long)(0xe7L << 40 | 0x56L << 0) // copy full vreg (128 bit) 1126 #define VLGV_ZOPC (unsigned long)(0xe7L << 40 | 0x21L << 0) // copy vreg element -> GR 1127 #define VLVG_ZOPC (unsigned long)(0xe7L << 40 | 0x22L << 0) // copy GR -> vreg element 1128 #define VLVGP_ZOPC (unsigned long)(0xe7L << 40 | 0x62L << 0) // copy GR2, GR3 (disjoint pair) -> vreg 1129 1130 // vector register pack: cut in half the size the source vector elements 1131 #define VPK_ZOPC (unsigned long)(0xe7L << 40 | 0x94L << 0) // just cut 1132 #define VPKS_ZOPC (unsigned long)(0xe7L << 40 | 0x97L << 0) // saturate as signed values 1133 #define VPKLS_ZOPC (unsigned long)(0xe7L << 40 | 0x95L << 0) // saturate as unsigned values 1134 1135 // vector register unpack: double in size the source vector elements 1136 #define VUPH_ZOPC (unsigned long)(0xe7L << 40 | 0xd7L << 0) // signed, left half of the source vector elements 1137 #define VUPLH_ZOPC (unsigned long)(0xe7L << 40 | 0xd5L << 0) // unsigned, left half of the source vector elements 1138 #define VUPL_ZOPC (unsigned long)(0xe7L << 40 | 0xd6L << 0) // signed, right half of the source vector elements 1139 #define VUPLL_ZOPC (unsigned long)(0xe7L << 40 | 0xd4L << 0) // unsigned, right half of the source vector element 1140 1141 // vector register merge 1142 #define VMRH_ZOPC (unsigned long)(0xe7L << 40 | 0x61L << 0) // register merge high (left half of source registers) 1143 #define VMRL_ZOPC (unsigned long)(0xe7L << 40 | 0x60L << 0) // register merge low (right half of source registers) 1144 1145 // vector register permute 1146 #define VPERM_ZOPC (unsigned long)(0xe7L << 40 | 0x8cL << 0) // vector permute 1147 #define VPDI_ZOPC (unsigned long)(0xe7L << 40 | 0x84L << 0) // vector permute DW immediate 1148 1149 // vector register replicate 1150 #define VREP_ZOPC (unsigned long)(0xe7L << 40 | 0x4dL << 0) // vector replicate 1151 #define VREPI_ZOPC (unsigned long)(0xe7L << 40 | 0x45L << 0) // vector replicate immediate 1152 #define VSEL_ZOPC (unsigned long)(0xe7L << 40 | 0x8dL << 0) // vector select 1153 1154 #define VSEG_ZOPC (unsigned long)(0xe7L << 40 | 0x5fL << 0) // vector sign-extend to DW (rightmost element in each DW). 1155 1156 //--- Load (immediate) --- 1157 1158 #define VLEIB_ZOPC (unsigned long)(0xe7L << 40 | 0x40L << 0) // load vreg element (16 bit imm to 8 bit) 1159 #define VLEIH_ZOPC (unsigned long)(0xe7L << 40 | 0x41L << 0) // load vreg element (16 bit imm to 16 bit) 1160 #define VLEIF_ZOPC (unsigned long)(0xe7L << 40 | 0x43L << 0) // load vreg element (16 bit imm to 32 bit) 1161 #define VLEIG_ZOPC (unsigned long)(0xe7L << 40 | 0x42L << 0) // load vreg element (16 bit imm to 64 bit) 1162 1163 //--- Store --- 1164 1165 #define VSTM_ZOPC (unsigned long)(0xe7L << 40 | 0x3eL << 0) // store full vreg range (n * 128 bit) 1166 #define VST_ZOPC (unsigned long)(0xe7L << 40 | 0x0eL << 0) // store full vreg (128 bit) 1167 #define VSTEB_ZOPC (unsigned long)(0xe7L << 40 | 0x08L << 0) // store vreg element (8 bit) 1168 #define VSTEH_ZOPC (unsigned long)(0xe7L << 40 | 0x09L << 0) // store vreg element (16 bit) 1169 #define VSTEF_ZOPC (unsigned long)(0xe7L << 40 | 0x0bL << 0) // store vreg element (32 bit) 1170 #define VSTEG_ZOPC (unsigned long)(0xe7L << 40 | 0x0aL << 0) // store vreg element (64 bit) 1171 #define VSTL_ZOPC (unsigned long)(0xe7L << 40 | 0x3fL << 0) // store vreg with length. 1172 1173 //--- Misc --- 1174 1175 #define VGM_ZOPC (unsigned long)(0xe7L << 40 | 0x46L << 0) // generate bit mask, [start..end] = '1', else '0' 1176 #define VGBM_ZOPC (unsigned long)(0xe7L << 40 | 0x44L << 0) // generate byte mask, bits(imm16) -> bytes 1177 1178 //---< Vector Arithmetic Instructions >--- 1179 1180 // Load 1181 #define VLC_ZOPC (unsigned long)(0xe7L << 40 | 0xdeL << 0) // V1 := -V2, element size = 2**m 1182 #define VLP_ZOPC (unsigned long)(0xe7L << 40 | 0xdfL << 0) // V1 := |V2|, element size = 2**m 1183 1184 // ADD 1185 #define VA_ZOPC (unsigned long)(0xe7L << 40 | 0xf3L << 0) // V1 := V2 + V3, element size = 2**m 1186 #define VACC_ZOPC (unsigned long)(0xe7L << 40 | 0xf1L << 0) // V1 := carry(V2 + V3), element size = 2**m 1187 1188 // SUB 1189 #define VS_ZOPC (unsigned long)(0xe7L << 40 | 0xf7L << 0) // V1 := V2 - V3, element size = 2**m 1190 #define VSCBI_ZOPC (unsigned long)(0xe7L << 40 | 0xf5L << 0) // V1 := borrow(V2 - V3), element size = 2**m 1191 1192 // MUL 1193 #define VML_ZOPC (unsigned long)(0xe7L << 40 | 0xa2L << 0) // V1 := V2 * V3, element size = 2**m 1194 #define VMH_ZOPC (unsigned long)(0xe7L << 40 | 0xa3L << 0) // V1 := V2 * V3, element size = 2**m 1195 #define VMLH_ZOPC (unsigned long)(0xe7L << 40 | 0xa1L << 0) // V1 := V2 * V3, element size = 2**m, unsigned 1196 #define VME_ZOPC (unsigned long)(0xe7L << 40 | 0xa6L << 0) // V1 := V2 * V3, element size = 2**m 1197 #define VMLE_ZOPC (unsigned long)(0xe7L << 40 | 0xa4L << 0) // V1 := V2 * V3, element size = 2**m, unsigned 1198 #define VMO_ZOPC (unsigned long)(0xe7L << 40 | 0xa7L << 0) // V1 := V2 * V3, element size = 2**m 1199 #define VMLO_ZOPC (unsigned long)(0xe7L << 40 | 0xa5L << 0) // V1 := V2 * V3, element size = 2**m, unsigned 1200 1201 // MUL & ADD 1202 #define VMAL_ZOPC (unsigned long)(0xe7L << 40 | 0xaaL << 0) // V1 := V2 * V3 + V4, element size = 2**m 1203 #define VMAH_ZOPC (unsigned long)(0xe7L << 40 | 0xabL << 0) // V1 := V2 * V3 + V4, element size = 2**m 1204 #define VMALH_ZOPC (unsigned long)(0xe7L << 40 | 0xa9L << 0) // V1 := V2 * V3 + V4, element size = 2**m, unsigned 1205 #define VMAE_ZOPC (unsigned long)(0xe7L << 40 | 0xaeL << 0) // V1 := V2 * V3 + V4, element size = 2**m 1206 #define VMALE_ZOPC (unsigned long)(0xe7L << 40 | 0xacL << 0) // V1 := V2 * V3 + V4, element size = 2**m, unsigned 1207 #define VMAO_ZOPC (unsigned long)(0xe7L << 40 | 0xafL << 0) // V1 := V2 * V3 + V4, element size = 2**m 1208 #define VMALO_ZOPC (unsigned long)(0xe7L << 40 | 0xadL << 0) // V1 := V2 * V3 + V4, element size = 2**m, unsigned 1209 1210 // Vector SUM 1211 #define VSUM_ZOPC (unsigned long)(0xe7L << 40 | 0x64L << 0) // V1[j] := toFW(sum(V2[i]) + V3[j]), subelements: byte or HW 1212 #define VSUMG_ZOPC (unsigned long)(0xe7L << 40 | 0x65L << 0) // V1[j] := toDW(sum(V2[i]) + V3[j]), subelements: HW or FW 1213 #define VSUMQ_ZOPC (unsigned long)(0xe7L << 40 | 0x67L << 0) // V1[j] := toQW(sum(V2[i]) + V3[j]), subelements: FW or DW 1214 1215 // Average 1216 #define VAVG_ZOPC (unsigned long)(0xe7L << 40 | 0xf2L << 0) // V1 := (V2+V3+1)/2, signed, element size = 2**m 1217 #define VAVGL_ZOPC (unsigned long)(0xe7L << 40 | 0xf0L << 0) // V1 := (V2+V3+1)/2, unsigned, element size = 2**m 1218 1219 // VECTOR Galois Field Multiply Sum 1220 #define VGFM_ZOPC (unsigned long)(0xe7L << 40 | 0xb4L << 0) 1221 #define VGFMA_ZOPC (unsigned long)(0xe7L << 40 | 0xbcL << 0) 1222 1223 //---< Vector Logical Instructions >--- 1224 1225 // AND 1226 #define VN_ZOPC (unsigned long)(0xe7L << 40 | 0x68L << 0) // V1 := V2 & V3, element size = 2**m 1227 #define VNC_ZOPC (unsigned long)(0xe7L << 40 | 0x69L << 0) // V1 := V2 & ~V3, element size = 2**m 1228 1229 // XOR 1230 #define VX_ZOPC (unsigned long)(0xe7L << 40 | 0x6dL << 0) // V1 := V2 ^ V3, element size = 2**m 1231 1232 // NOR 1233 #define VNO_ZOPC (unsigned long)(0xe7L << 40 | 0x6bL << 0) // V1 := !(V2 | V3), element size = 2**m 1234 1235 // OR 1236 #define VO_ZOPC (unsigned long)(0xe7L << 40 | 0x6aL << 0) // V1 := V2 | V3, element size = 2**m 1237 1238 // Comparison (element-wise) 1239 #define VCEQ_ZOPC (unsigned long)(0xe7L << 40 | 0xf8L << 0) // V1 := (V2 == V3) ? 0xffff : 0x0000, element size = 2**m 1240 #define VCH_ZOPC (unsigned long)(0xe7L << 40 | 0xfbL << 0) // V1 := (V2 > V3) ? 0xffff : 0x0000, element size = 2**m, signed 1241 #define VCHL_ZOPC (unsigned long)(0xe7L << 40 | 0xf9L << 0) // V1 := (V2 > V3) ? 0xffff : 0x0000, element size = 2**m, unsigned 1242 1243 // Max/Min (element-wise) 1244 #define VMX_ZOPC (unsigned long)(0xe7L << 40 | 0xffL << 0) // V1 := (V2 > V3) ? V2 : V3, element size = 2**m, signed 1245 #define VMXL_ZOPC (unsigned long)(0xe7L << 40 | 0xfdL << 0) // V1 := (V2 > V3) ? V2 : V3, element size = 2**m, unsigned 1246 #define VMN_ZOPC (unsigned long)(0xe7L << 40 | 0xfeL << 0) // V1 := (V2 < V3) ? V2 : V3, element size = 2**m, signed 1247 #define VMNL_ZOPC (unsigned long)(0xe7L << 40 | 0xfcL << 0) // V1 := (V2 < V3) ? V2 : V3, element size = 2**m, unsigned 1248 1249 // Leading/Trailing Zeros, population count 1250 #define VCLZ_ZOPC (unsigned long)(0xe7L << 40 | 0x53L << 0) // V1 := leadingzeros(V2), element size = 2**m 1251 #define VCTZ_ZOPC (unsigned long)(0xe7L << 40 | 0x52L << 0) // V1 := trailingzeros(V2), element size = 2**m 1252 #define VPOPCT_ZOPC (unsigned long)(0xe7L << 40 | 0x50L << 0) // V1 := popcount(V2), bytewise!! 1253 1254 // Rotate/Shift 1255 #define VERLLV_ZOPC (unsigned long)(0xe7L << 40 | 0x73L << 0) // V1 := rotateleft(V2), rotate count in V3 element 1256 #define VERLL_ZOPC (unsigned long)(0xe7L << 40 | 0x33L << 0) // V1 := rotateleft(V3), rotate count from d2(b2). 1257 #define VERIM_ZOPC (unsigned long)(0xe7L << 40 | 0x72L << 0) // Rotate then insert under mask. Read Principles of Operation!! 1258 1259 #define VESLV_ZOPC (unsigned long)(0xe7L << 40 | 0x70L << 0) // V1 := SLL(V2, V3), unsigned, element-wise 1260 #define VESL_ZOPC (unsigned long)(0xe7L << 40 | 0x30L << 0) // V1 := SLL(V3), unsigned, shift count from d2(b2). 1261 1262 #define VESRAV_ZOPC (unsigned long)(0xe7L << 40 | 0x7AL << 0) // V1 := SRA(V2, V3), signed, element-wise 1263 #define VESRA_ZOPC (unsigned long)(0xe7L << 40 | 0x3AL << 0) // V1 := SRA(V3), signed, shift count from d2(b2). 1264 #define VESRLV_ZOPC (unsigned long)(0xe7L << 40 | 0x78L << 0) // V1 := SRL(V2, V3), unsigned, element-wise 1265 #define VESRL_ZOPC (unsigned long)(0xe7L << 40 | 0x38L << 0) // V1 := SRL(V3), unsigned, shift count from d2(b2). 1266 1267 #define VSL_ZOPC (unsigned long)(0xe7L << 40 | 0x74L << 0) // V1 := SLL(V2), unsigned, bit-count 1268 #define VSLB_ZOPC (unsigned long)(0xe7L << 40 | 0x75L << 0) // V1 := SLL(V2), unsigned, byte-count 1269 #define VSLDB_ZOPC (unsigned long)(0xe7L << 40 | 0x77L << 0) // V1 := SLL((V2,V3)), unsigned, byte-count 1270 1271 #define VSRA_ZOPC (unsigned long)(0xe7L << 40 | 0x7eL << 0) // V1 := SRA(V2), signed, bit-count 1272 #define VSRAB_ZOPC (unsigned long)(0xe7L << 40 | 0x7fL << 0) // V1 := SRA(V2), signed, byte-count 1273 #define VSRL_ZOPC (unsigned long)(0xe7L << 40 | 0x7cL << 0) // V1 := SRL(V2), unsigned, bit-count 1274 #define VSRLB_ZOPC (unsigned long)(0xe7L << 40 | 0x7dL << 0) // V1 := SRL(V2), unsigned, byte-count 1275 1276 // Test under Mask 1277 #define VTM_ZOPC (unsigned long)(0xe7L << 40 | 0xd8L << 0) // Like TM, set CC according to state of selected bits. 1278 1279 //---< Vector String Instructions >--- 1280 #define VFAE_ZOPC (unsigned long)(0xe7L << 40 | 0x82L << 0) // Find any element 1281 #define VFEE_ZOPC (unsigned long)(0xe7L << 40 | 0x80L << 0) // Find element equal 1282 #define VFENE_ZOPC (unsigned long)(0xe7L << 40 | 0x81L << 0) // Find element not equal 1283 #define VSTRC_ZOPC (unsigned long)(0xe7L << 40 | 0x8aL << 0) // String range compare 1284 #define VISTR_ZOPC (unsigned long)(0xe7L << 40 | 0x5cL << 0) // Isolate String 1285 1286 1287 //-------------------------------- 1288 //-- Miscellaneous Operations -- 1289 //-------------------------------- 1290 1291 // Execute 1292 #define EX_ZOPC (unsigned int)(68L << 24) 1293 #define EXRL_ZOPC (unsigned long)(0xc6L << 40 | 0x00L << 32) // z10 1294 1295 // Compare and Swap 1296 #define CS_ZOPC (unsigned int)(0xba << 24) 1297 #define CSY_ZOPC (unsigned long)(0xebL << 40 | 0x14L) 1298 #define CSG_ZOPC (unsigned long)(0xebL << 40 | 0x30L) 1299 1300 // Interlocked-Update 1301 #define LAA_ZOPC (unsigned long)(0xebL << 40 | 0xf8L) // z196 1302 #define LAAG_ZOPC (unsigned long)(0xebL << 40 | 0xe8L) // z196 1303 #define LAAL_ZOPC (unsigned long)(0xebL << 40 | 0xfaL) // z196 1304 #define LAALG_ZOPC (unsigned long)(0xebL << 40 | 0xeaL) // z196 1305 #define LAN_ZOPC (unsigned long)(0xebL << 40 | 0xf4L) // z196 1306 #define LANG_ZOPC (unsigned long)(0xebL << 40 | 0xe4L) // z196 1307 #define LAX_ZOPC (unsigned long)(0xebL << 40 | 0xf7L) // z196 1308 #define LAXG_ZOPC (unsigned long)(0xebL << 40 | 0xe7L) // z196 1309 #define LAO_ZOPC (unsigned long)(0xebL << 40 | 0xf6L) // z196 1310 #define LAOG_ZOPC (unsigned long)(0xebL << 40 | 0xe6L) // z196 1311 1312 // System Functions 1313 #define STCKF_ZOPC (unsigned int)(0xb2 << 24 | 0x7c << 16) 1314 #define STFLE_ZOPC (unsigned int)(0xb2 << 24 | 0xb0 << 16) 1315 #define ECTG_ZOPC (unsigned long)(0xc8L <<40 | 0x01L << 32) // z10 1316 #define ECAG_ZOPC (unsigned long)(0xebL <<40 | 0x4cL) // z10 1317 1318 // Execution Prediction 1319 #define PFD_ZOPC (unsigned long)(0xe3L <<40 | 0x36L) // z10 1320 #define PFDRL_ZOPC (unsigned long)(0xc6L <<40 | 0x02L << 32) // z10 1321 #define BPP_ZOPC (unsigned long)(0xc7L <<40) // branch prediction preload -- EC12 1322 #define BPRP_ZOPC (unsigned long)(0xc5L <<40) // branch prediction preload -- EC12 1323 1324 // Transaction Control 1325 #define TBEGIN_ZOPC (unsigned long)(0xe560L << 32) // tx begin -- EC12 1326 #define TBEGINC_ZOPC (unsigned long)(0xe561L << 32) // tx begin (constrained) -- EC12 1327 #define TEND_ZOPC (unsigned int)(0xb2f8 << 16) // tx end -- EC12 1328 #define TABORT_ZOPC (unsigned int)(0xb2fc << 16) // tx abort -- EC12 1329 #define ETND_ZOPC (unsigned int)(0xb2ec << 16) // tx nesting depth -- EC12 1330 #define PPA_ZOPC (unsigned int)(0xb2e8 << 16) // tx processor assist -- EC12 1331 1332 // Crypto and Checksum 1333 #define CKSM_ZOPC (unsigned int)(0xb2 << 24 | 0x41 << 16) // checksum. This is NOT CRC32 1334 #define KM_ZOPC (unsigned int)(0xb9 << 24 | 0x2e << 16) // cipher 1335 #define KMC_ZOPC (unsigned int)(0xb9 << 24 | 0x2f << 16) // cipher 1336 #define KIMD_ZOPC (unsigned int)(0xb9 << 24 | 0x3e << 16) // SHA (msg digest) 1337 #define KLMD_ZOPC (unsigned int)(0xb9 << 24 | 0x3f << 16) // SHA (msg digest) 1338 #define KMAC_ZOPC (unsigned int)(0xb9 << 24 | 0x1e << 16) // Message Authentication Code 1339 1340 // Various 1341 #define TCEB_ZOPC (unsigned long)(237L << 40 | 16) 1342 #define TCDB_ZOPC (unsigned long)(237L << 40 | 17) 1343 #define TAM_ZOPC (unsigned long)(267) 1344 1345 #define FLOGR_ZOPC (unsigned int)(0xb9 << 24 | 0x83 << 16) 1346 #define POPCNT_ZOPC (unsigned int)(0xb9e1 << 16) 1347 #define AHHHR_ZOPC (unsigned int)(0xb9c8 << 16) 1348 #define AHHLR_ZOPC (unsigned int)(0xb9d8 << 16) 1349 1350 1351 // OpCode field masks 1352 1353 #define RI_MASK (unsigned int)(0xff << 24 | 0x0f << 16) 1354 #define RRE_MASK (unsigned int)(0xff << 24 | 0xff << 16) 1355 #define RSI_MASK (unsigned int)(0xff << 24) 1356 #define RIE_MASK (unsigned long)(0xffL << 40 | 0xffL) 1357 #define RIL_MASK (unsigned long)(0xffL << 40 | 0x0fL << 32) 1358 1359 #define BASR_MASK (unsigned int)(0xff << 8) 1360 #define BCR_MASK (unsigned int)(0xff << 8) 1361 #define BRC_MASK (unsigned int)(0xff << 24 | 0x0f << 16) 1362 #define LGHI_MASK (unsigned int)(0xff << 24 | 0x0f << 16) 1363 #define LLI_MASK (unsigned int)(0xff << 24 | 0x0f << 16) 1364 #define II_MASK (unsigned int)(0xff << 24 | 0x0f << 16) 1365 #define LLIF_MASK (unsigned long)(0xffL << 40 | 0x0fL << 32) 1366 #define IIF_MASK (unsigned long)(0xffL << 40 | 0x0fL << 32) 1367 #define BRASL_MASK (unsigned long)(0xffL << 40 | 0x0fL << 32) 1368 #define TM_MASK (unsigned int)(0xff << 24) 1369 #define TMY_MASK (unsigned long)(0xffL << 40 | 0xffL) 1370 #define LB_MASK (unsigned long)(0xffL << 40 | 0xffL) 1371 #define LH_MASK (unsigned int)(0xff << 24) 1372 #define L_MASK (unsigned int)(0xff << 24) 1373 #define LY_MASK (unsigned long)(0xffL << 40 | 0xffL) 1374 #define LG_MASK (unsigned long)(0xffL << 40 | 0xffL) 1375 #define LLGH_MASK (unsigned long)(0xffL << 40 | 0xffL) 1376 #define LLGF_MASK (unsigned long)(0xffL << 40 | 0xffL) 1377 #define SLAG_MASK (unsigned long)(0xffL << 40 | 0xffL) 1378 #define LARL_MASK (unsigned long)(0xff0fL << 32) 1379 #define LGRL_MASK (unsigned long)(0xff0fL << 32) 1380 #define LE_MASK (unsigned int)(0xff << 24) 1381 #define LD_MASK (unsigned int)(0xff << 24) 1382 #define ST_MASK (unsigned int)(0xff << 24) 1383 #define STC_MASK (unsigned int)(0xff << 24) 1384 #define STG_MASK (unsigned long)(0xffL << 40 | 0xffL) 1385 #define STH_MASK (unsigned int)(0xff << 24) 1386 #define STE_MASK (unsigned int)(0xff << 24) 1387 #define STD_MASK (unsigned int)(0xff << 24) 1388 #define CMPBRANCH_MASK (unsigned long)(0xffL << 40 | 0xffL) 1389 #define REL_LONG_MASK (unsigned long)(0xff0fL << 32) 1390 1391 public: 1392 // Condition code masks. Details: 1393 // - Mask bit#3 must be zero for all compare and branch/trap instructions to ensure 1394 // future compatibility. 1395 // - For all arithmetic instructions which set the condition code, mask bit#3 1396 // indicates overflow ("unordered" in float operations). 1397 // - "unordered" float comparison results have to be treated as low. 1398 // - When overflow/unordered is detected, none of the branch conditions is true, 1399 // except for bcondOverflow/bcondNotOrdered and bcondAlways. 1400 // - For INT comparisons, the inverse condition can be calculated as (14-cond). 1401 // - For FLOAT comparisons, the inverse condition can be calculated as (15-cond). 1402 enum branch_condition { 1403 bcondNever = 0, 1404 bcondAlways = 15, 1405 1406 // Specific names. Make use of lightweight sync. 1407 // Full and lightweight sync operation. 1408 bcondFullSync = 15, 1409 bcondLightSync = 14, 1410 bcondNop = 0, 1411 1412 // arithmetic compare instructions 1413 // arithmetic load and test, insert instructions 1414 // Mask bit#3 must be zero for future compatibility. 1415 bcondEqual = 8, 1416 bcondNotEqual = 6, 1417 bcondLow = 4, 1418 bcondNotLow = 10, 1419 bcondHigh = 2, 1420 bcondNotHigh = 12, 1421 // arithmetic calculation instructions 1422 // Mask bit#3 indicates overflow if detected by instr. 1423 // Mask bit#3 = 0 (overflow is not handled by compiler). 1424 bcondOverflow = 1, 1425 bcondNotOverflow = 14, 1426 bcondZero = bcondEqual, 1427 bcondNotZero = bcondNotEqual, 1428 bcondNegative = bcondLow, 1429 bcondNotNegative = bcondNotLow, 1430 bcondPositive = bcondHigh, 1431 bcondNotPositive = bcondNotHigh, 1432 bcondNotOrdered = 1, // float comparisons 1433 bcondOrdered = 14, // float comparisons 1434 bcondLowOrNotOrdered = bcondLow|bcondNotOrdered, // float comparisons 1435 bcondHighOrNotOrdered = bcondHigh|bcondNotOrdered, // float comparisons 1436 // unsigned arithmetic calculation instructions 1437 // Mask bit#0 is not used by these instructions. 1438 // There is no indication of overflow for these instr. 1439 bcondLogZero_NoCarry = 8, 1440 bcondLogZero_Carry = 2, 1441 // bcondLogZero_Borrow = 8, // This CC is never generated. 1442 bcondLogZero_NoBorrow = 2, 1443 bcondLogZero = bcondLogZero_Carry | bcondLogZero_NoCarry, 1444 bcondLogNotZero_NoCarry = 4, 1445 bcondLogNotZero_Carry = 1, 1446 bcondLogNotZero_Borrow = 4, 1447 bcondLogNotZero_NoBorrow = 1, 1448 bcondLogNotZero = bcondLogNotZero_Carry | bcondLogNotZero_NoCarry, 1449 bcondLogCarry = bcondLogZero_Carry | bcondLogNotZero_Carry, 1450 bcondLogBorrow = /* bcondLogZero_Borrow | */ bcondLogNotZero_Borrow, 1451 // string search instructions 1452 bcondFound = 4, 1453 bcondNotFound = 2, 1454 bcondInterrupted = 1, 1455 // bit test instructions 1456 bcondAllZero = 8, 1457 bcondMixed = 6, 1458 bcondAllOne = 1, 1459 bcondNotAllZero = 7 // for tmll 1460 }; 1461 1462 enum Condition { 1463 // z/Architecture 1464 negative = 0, 1465 less = 0, 1466 positive = 1, 1467 greater = 1, 1468 zero = 2, 1469 equal = 2, 1470 summary_overflow = 3, 1471 }; 1472 1473 // Rounding mode for float-2-int conversions. 1474 enum RoundingMode { 1475 current_mode = 0, // Mode taken from FPC register. 1476 biased_to_nearest = 1, 1477 to_nearest = 4, 1478 to_zero = 5, 1479 to_plus_infinity = 6, 1480 to_minus_infinity = 7 1481 }; 1482 1483 // Vector Register Element Type. 1484 enum VRegElemType { 1485 VRET_BYTE = 0, 1486 VRET_HW = 1, 1487 VRET_FW = 2, 1488 VRET_DW = 3, 1489 VRET_QW = 4 1490 }; 1491 1492 // Vector Operation Result Control. 1493 // This is a set of flags used in some vector instructions to control 1494 // the result (side) effects of instruction execution. 1495 enum VOpRC { 1496 VOPRC_CCSET = 0b0001, // set the CC. 1497 VOPRC_CCIGN = 0b0000, // ignore, don't set CC. 1498 VOPRC_ZS = 0b0010, // Zero Search. Additional, elementwise, comparison against zero. 1499 VOPRC_NOZS = 0b0000, // No Zero Search. 1500 VOPRC_RTBYTEIX = 0b0100, // generate byte index to lowest element with true comparison. 1501 VOPRC_RTBITVEC = 0b0000, // generate bit vector, all 1s for true, all 0s for false element comparisons. 1502 VOPRC_INVERT = 0b1000, // invert comparison results. 1503 VOPRC_NOINVERT = 0b0000 // use comparison results as is, do not invert. 1504 }; 1505 1506 // Inverse condition code, i.e. determine "15 - cc" for a given condition code cc. 1507 static branch_condition inverse_condition(branch_condition cc); 1508 static branch_condition inverse_float_condition(branch_condition cc); 1509 1510 1511 //----------------------------------------------- 1512 // instruction property getter methods 1513 //----------------------------------------------- 1514 1515 // Calculate length of instruction. 1516 static int instr_len(unsigned char *instr); 1517 1518 // Longest instructions are 6 bytes on z/Architecture. 1519 static int instr_maxlen() { return 6; } 1520 1521 // Average instruction is 4 bytes on z/Architecture (just a guess). 1522 static int instr_avglen() { return 4; } 1523 1524 // Shortest instructions are 2 bytes on z/Architecture. 1525 static int instr_minlen() { return 2; } 1526 1527 // Move instruction at pc right-justified into passed long int. 1528 // Return instr len in bytes as function result. 1529 static unsigned int get_instruction(unsigned char *pc, unsigned long *instr); 1530 1531 // Move instruction in passed (long int) into storage at pc. 1532 // This code is _NOT_ MT-safe!! 1533 static void set_instruction(unsigned char *pc, unsigned long instr, unsigned int len) { 1534 memcpy(pc, ((unsigned char *)&instr)+sizeof(unsigned long)-len, len); 1535 } 1536 1537 1538 //------------------------------------------ 1539 // instruction field test methods 1540 //------------------------------------------ 1541 1542 // Only used once in s390.ad to implement Matcher::is_short_branch_offset(). 1543 static bool is_within_range_of_RelAddr16(address target, address origin) { 1544 return RelAddr::is_in_range_of_RelAddr16(target, origin); 1545 } 1546 1547 1548 //---------------------------------- 1549 // some diagnostic output 1550 //---------------------------------- 1551 1552 static void print_dbg_msg(outputStream* out, unsigned long inst, const char* msg, int ilen) PRODUCT_RETURN; 1553 static void dump_code_range(outputStream* out, address pc, const unsigned int range, const char* msg = " ") PRODUCT_RETURN; 1554 1555 protected: 1556 1557 //------------------------------------------------------- 1558 // instruction field helper methods (internal) 1559 //------------------------------------------------------- 1560 1561 // Return a mask of 1s between hi_bit and lo_bit (inclusive). 1562 static long fmask(unsigned int hi_bit, unsigned int lo_bit) { 1563 assert(hi_bit >= lo_bit && hi_bit < 48, "bad bits"); 1564 return ((1L<<(hi_bit-lo_bit+1)) - 1) << lo_bit; 1565 } 1566 1567 // extract u_field 1568 // unsigned value 1569 static long inv_u_field(long x, int hi_bit, int lo_bit) { 1570 return (x & fmask(hi_bit, lo_bit)) >> lo_bit; 1571 } 1572 1573 // extract s_field 1574 // Signed value, may need sign extension. 1575 static long inv_s_field(long x, int hi_bit, int lo_bit) { 1576 x = inv_u_field(x, hi_bit, lo_bit); 1577 // Highest extracted bit set -> sign extension. 1578 return (x >= (1L<<(hi_bit-lo_bit)) ? x | ((-1L)<<(hi_bit-lo_bit)) : x); 1579 } 1580 1581 // Extract primary opcode from instruction. 1582 static int z_inv_op(int x) { return inv_u_field(x, 31, 24); } 1583 static int z_inv_op(long x) { return inv_u_field(x, 47, 40); } 1584 1585 static int inv_reg( long x, int s, int len) { return inv_u_field(x, (len-s)-1, (len-s)-4); } // Regs are encoded in 4 bits. 1586 static int inv_mask(long x, int s, int len) { return inv_u_field(x, (len-s)-1, (len-s)-8); } // Mask is 8 bits long. 1587 static int inv_simm16_48(long x) { return (inv_s_field(x, 31, 16)); } // 6-byte instructions only 1588 static int inv_simm16(long x) { return (inv_s_field(x, 15, 0)); } // 4-byte instructions only 1589 static int inv_simm20(long x) { return (inv_u_field(x, 27, 16) | // 6-byte instructions only 1590 inv_s_field(x, 15, 8)<<12); } 1591 static int inv_simm32(long x) { return (inv_s_field(x, 31, 0)); } // 6-byte instructions only 1592 static int inv_uimm12(long x) { return (inv_u_field(x, 11, 0)); } // 4-byte instructions only 1593 1594 // Encode u_field from long value. 1595 static long u_field(long x, int hi_bit, int lo_bit) { 1596 long r = x << lo_bit; 1597 assert((r & ~fmask(hi_bit, lo_bit)) == 0, "value out of range"); 1598 assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking"); 1599 return r; 1600 } 1601 1602 static int64_t rsmask_48( Address a) { assert(a.is_RSform(), "bad address format"); return rsmask_48( a.disp12(), a.base()); } 1603 static int64_t rxmask_48( Address a) { if (a.is_RXform()) { return rxmask_48( a.disp12(), a.index(), a.base()); } 1604 else if (a.is_RSform()) { return rsmask_48( a.disp12(), a.base()); } 1605 else { guarantee(false, "bad address format"); return 0; } 1606 } 1607 static int64_t rsymask_48(Address a) { assert(a.is_RSYform(), "bad address format"); return rsymask_48(a.disp20(), a.base()); } 1608 static int64_t rxymask_48(Address a) { if (a.is_RXYform()) { return rxymask_48( a.disp20(), a.index(), a.base()); } 1609 else if (a.is_RSYform()) { return rsymask_48( a.disp20(), a.base()); } 1610 else { guarantee(false, "bad address format"); return 0; } 1611 } 1612 1613 static int64_t rsmask_48( int64_t d2, Register b2) { return uimm12(d2, 20, 48) | regz(b2, 16, 48); } 1614 static int64_t rxmask_48( int64_t d2, Register x2, Register b2) { return uimm12(d2, 20, 48) | reg(x2, 12, 48) | regz(b2, 16, 48); } 1615 static int64_t rsymask_48(int64_t d2, Register b2) { return simm20(d2) | regz(b2, 16, 48); } 1616 static int64_t rxymask_48(int64_t d2, Register x2, Register b2) { return simm20(d2) | reg(x2, 12, 48) | regz(b2, 16, 48); } 1617 1618 // Address calculated from d12(vx,b) - vx is vector index register. 1619 static int64_t rvmask_48( int64_t d2, VectorRegister x2, Register b2) { return uimm12(d2, 20, 48) | vreg(x2, 12) | regz(b2, 16, 48); } 1620 1621 static int64_t vreg_mask(VectorRegister v, int pos) { 1622 return vreg(v, pos) | v->RXB_mask(pos); 1623 } 1624 1625 // Vector Element Size Control. 4-bit field which indicates the size of the vector elements. 1626 static int64_t vesc_mask(int64_t size, int min_size, int max_size, int pos) { 1627 // min_size - minimum element size. Not all instructions support element sizes beginning with "byte". 1628 // max_size - maximum element size. Not all instructions support element sizes up to "QW". 1629 assert((min_size <= size) && (size <= max_size), "element size control out of range"); 1630 return uimm4(size, pos, 48); 1631 } 1632 1633 // Vector Element IndeX. 4-bit field which indexes the target vector element. 1634 static int64_t veix_mask(int64_t ix, int el_size, int pos) { 1635 // el_size - size of the vector element. This is a VRegElemType enum value. 1636 // ix - vector element index. 1637 int max_ix = -1; 1638 switch (el_size) { 1639 case VRET_BYTE: max_ix = 15; break; 1640 case VRET_HW: max_ix = 7; break; 1641 case VRET_FW: max_ix = 3; break; 1642 case VRET_DW: max_ix = 1; break; 1643 case VRET_QW: max_ix = 0; break; 1644 default: guarantee(false, "bad vector element size %d", el_size); break; 1645 } 1646 assert((0 <= ix) && (ix <= max_ix), "element size out of range (0 <= %ld <= %d)", ix, max_ix); 1647 return uimm4(ix, pos, 48); 1648 } 1649 1650 // Vector Operation Result Control. 4-bit field. 1651 static int64_t voprc_any(int64_t flags, int pos, int64_t allowed_flags = 0b1111) { 1652 assert((flags & allowed_flags) == flags, "Invalid VOPRC_* flag combination: %d", (int)flags); 1653 return uimm4(flags, pos, 48); 1654 } 1655 1656 // Vector Operation Result Control. Condition code setting. 1657 static int64_t voprc_ccmask(int64_t flags, int pos) { 1658 return voprc_any(flags, pos, VOPRC_CCIGN | VOPRC_CCSET); 1659 } 1660 1661 public: 1662 1663 //-------------------------------------------------- 1664 // instruction field construction methods 1665 //-------------------------------------------------- 1666 1667 // Compute relative address (32 bit) for branch. 1668 // Only used once in nativeInst_s390.cpp. 1669 static intptr_t z_pcrel_off(address dest, address pc) { 1670 return RelAddr::pcrel_off32(dest, pc); 1671 } 1672 1673 // Extract 20-bit signed displacement. 1674 // Only used in disassembler_s390.cpp for temp enhancements. 1675 static int inv_simm20_xx(address iLoc) { 1676 unsigned long instr = 0; 1677 unsigned long iLen = get_instruction(iLoc, &instr); 1678 return inv_simm20(instr); 1679 } 1680 1681 // unsigned immediate, in low bits, nbits long 1682 static long uimm(long x, int nbits) { 1683 assert(Immediate::is_uimm(x, nbits), "unsigned constant out of range"); 1684 return x & fmask(nbits - 1, 0); 1685 } 1686 1687 // Cast '1' to long to avoid sign extension if nbits = 32. 1688 // signed immediate, in low bits, nbits long 1689 static long simm(long x, int nbits) { 1690 assert(Immediate::is_simm(x, nbits), "value out of range"); 1691 return x & fmask(nbits - 1, 0); 1692 } 1693 1694 static long imm(int64_t x, int nbits) { 1695 // Assert that x can be represented with nbits bits ignoring the sign bits, 1696 // i.e. the more higher bits should all be 0 or 1. 1697 assert((x >> nbits) == 0 || (x >> nbits) == -1, "value out of range"); 1698 return x & fmask(nbits-1, 0); 1699 } 1700 1701 // A 20-bit displacement is only in instructions of the 1702 // RSY, RXY, or SIY format. In these instructions, the D 1703 // field consists of a DL (low) field in bit positions 20-31 1704 // and of a DH (high) field in bit positions 32-39. The 1705 // value of the displacement is formed by appending the 1706 // contents of the DH field to the left of the contents of 1707 // the DL field. 1708 static long simm20(int64_t ui20) { 1709 assert(Immediate::is_simm(ui20, 20), "value out of range"); 1710 return ( ((ui20 & 0xfffL) << (48-32)) | // DL 1711 (((ui20 >> 12) & 0xffL) << (48-40))); // DH 1712 } 1713 1714 static long reg(Register r, int s, int len) { return u_field(r->encoding(), (len-s)-1, (len-s)-4); } 1715 static long reg(int r, int s, int len) { return u_field(r, (len-s)-1, (len-s)-4); } 1716 static long regt(Register r, int s, int len) { return reg(r, s, len); } 1717 static long regz(Register r, int s, int len) { assert(r != Z_R0, "cannot use register R0 in memory access"); return reg(r, s, len); } 1718 1719 static long uimm4( int64_t ui4, int s, int len) { return uimm(ui4, 4) << (len-s-4); } 1720 static long uimm6( int64_t ui6, int s, int len) { return uimm(ui6, 6) << (len-s-6); } 1721 static long uimm8( int64_t ui8, int s, int len) { return uimm(ui8, 8) << (len-s-8); } 1722 static long uimm12(int64_t ui12, int s, int len) { return uimm(ui12, 12) << (len-s-12); } 1723 static long uimm16(int64_t ui16, int s, int len) { return uimm(ui16, 16) << (len-s-16); } 1724 static long uimm32(int64_t ui32, int s, int len) { return uimm((unsigned)ui32, 32) << (len-s-32); } // prevent sign extension 1725 1726 static long simm8( int64_t si8, int s, int len) { return simm(si8, 8) << (len-s-8); } 1727 static long simm12(int64_t si12, int s, int len) { return simm(si12, 12) << (len-s-12); } 1728 static long simm16(int64_t si16, int s, int len) { return simm(si16, 16) << (len-s-16); } 1729 static long simm24(int64_t si24, int s, int len) { return simm(si24, 24) << (len-s-24); } 1730 static long simm32(int64_t si32, int s, int len) { return simm(si32, 32) << (len-s-32); } 1731 1732 static long imm8( int64_t i8, int s, int len) { return imm(i8, 8) << (len-s-8); } 1733 static long imm12(int64_t i12, int s, int len) { return imm(i12, 12) << (len-s-12); } 1734 static long imm16(int64_t i16, int s, int len) { return imm(i16, 16) << (len-s-16); } 1735 static long imm24(int64_t i24, int s, int len) { return imm(i24, 24) << (len-s-24); } 1736 static long imm32(int64_t i32, int s, int len) { return imm(i32, 32) << (len-s-32); } 1737 1738 static long vreg(VectorRegister v, int pos) { const int len = 48; return u_field(v->encoding()&0x0f, (len-pos)-1, (len-pos)-4) | v->RXB_mask(pos); } 1739 1740 static long fregt(FloatRegister r, int s, int len) { return freg(r,s,len); } 1741 static long freg( FloatRegister r, int s, int len) { return u_field(r->encoding(), (len-s)-1, (len-s)-4); } 1742 1743 // Rounding mode for float-2-int conversions. 1744 static long rounding_mode(RoundingMode m, int s, int len) { 1745 assert(m != 2 && m != 3, "invalid mode"); 1746 return uimm(m, 4) << (len-s-4); 1747 } 1748 1749 //-------------------------------------------- 1750 // instruction field getter methods 1751 //-------------------------------------------- 1752 1753 static int get_imm32(address a, int instruction_number) { 1754 int imm; 1755 int *p =((int *)(a + 2 + 6 * instruction_number)); 1756 imm = *p; 1757 return imm; 1758 } 1759 1760 static short get_imm16(address a, int instruction_number) { 1761 short imm; 1762 short *p =((short *)a) + 2 * instruction_number + 1; 1763 imm = *p; 1764 return imm; 1765 } 1766 1767 1768 //-------------------------------------------- 1769 // instruction field setter methods 1770 //-------------------------------------------- 1771 1772 static void set_imm32(address a, int64_t s) { 1773 assert(Immediate::is_simm32(s) || Immediate::is_uimm32(s), "to big"); 1774 int* p = (int *) (a + 2); 1775 *p = s; 1776 } 1777 1778 static void set_imm16(int* instr, int64_t s) { 1779 assert(Immediate::is_simm16(s) || Immediate::is_uimm16(s), "to big"); 1780 short* p = ((short *)instr) + 1; 1781 *p = s; 1782 } 1783 1784 public: 1785 1786 static unsigned int align(unsigned int x, unsigned int a) { return ((x + (a - 1)) & ~(a - 1)); } 1787 static bool is_aligned(unsigned int x, unsigned int a) { return (0 == x % a); } 1788 1789 inline void emit_16(int x); 1790 inline void emit_32(int x); 1791 inline void emit_48(long x); 1792 1793 // Compare and control flow instructions 1794 // ===================================== 1795 1796 // See also commodity routines compare64_and_branch(), compare32_and_branch(). 1797 1798 // compare instructions 1799 // compare register 1800 inline void z_cr( Register r1, Register r2); // compare (r1, r2) ; int32 1801 inline void z_cgr( Register r1, Register r2); // compare (r1, r2) ; int64 1802 inline void z_cgfr(Register r1, Register r2); // compare (r1, r2) ; int64 <--> int32 1803 // compare immediate 1804 inline void z_chi( Register r1, int64_t i2); // compare (r1, i2_imm16) ; int32 1805 inline void z_cfi( Register r1, int64_t i2); // compare (r1, i2_imm32) ; int32 1806 inline void z_cghi(Register r1, int64_t i2); // compare (r1, i2_imm16) ; int64 1807 inline void z_cgfi(Register r1, int64_t i2); // compare (r1, i2_imm32) ; int64 1808 // compare memory 1809 inline void z_ch( Register r1, const Address &a); // compare (r1, *(a)) ; int32 <--> int16 1810 inline void z_ch( Register r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_uimm12+x2+b2)) ; int32 <--> int16 1811 inline void z_c( Register r1, const Address &a); // compare (r1, *(a)) ; int32 1812 inline void z_c( Register r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_uimm12+x2+b2)) ; int32 1813 inline void z_cy( Register r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_uimm20+x2+b2)) ; int32 1814 inline void z_cy( Register r1, int64_t d2, Register b2); // compare (r1, *(d2_uimm20+x2+b2)) ; int32 1815 inline void z_cy( Register r1, const Address& a); // compare (r1, *(a)) ; int32 1816 //inline void z_cgf(Register r1,const Address &a); // compare (r1, *(a)) ; int64 <--> int32 1817 //inline void z_cgf(Register r1,int64_t d2, Register x2, Register b2);// compare (r1, *(d2_uimm12+x2+b2)) ; int64 <--> int32 1818 inline void z_cg( Register r1, const Address &a); // compare (r1, *(a)) ; int64 1819 inline void z_cg( Register r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_imm20+x2+b2)) ; int64 1820 1821 // compare logical instructions 1822 // compare register 1823 inline void z_clr( Register r1, Register r2); // compare (r1, r2) ; uint32 1824 inline void z_clgr( Register r1, Register r2); // compare (r1, r2) ; uint64 1825 // compare immediate 1826 inline void z_clfi( Register r1, int64_t i2); // compare (r1, i2_uimm32) ; uint32 1827 inline void z_clgfi(Register r1, int64_t i2); // compare (r1, i2_uimm32) ; uint64 1828 inline void z_cl( Register r1, const Address &a); // compare (r1, *(a) ; uint32 1829 inline void z_cl( Register r1, int64_t d2, Register x2, Register b2);// compare (r1, *(d2_uimm12+x2+b2) ; uint32 1830 inline void z_cly( Register r1, int64_t d2, Register x2, Register b2);// compare (r1, *(d2_uimm20+x2+b2)) ; uint32 1831 inline void z_cly( Register r1, int64_t d2, Register b2); // compare (r1, *(d2_uimm20+x2+b2)) ; uint32 1832 inline void z_cly( Register r1, const Address& a); // compare (r1, *(a)) ; uint32 1833 inline void z_clg( Register r1, const Address &a); // compare (r1, *(a) ; uint64 1834 inline void z_clg( Register r1, int64_t d2, Register x2, Register b2);// compare (r1, *(d2_imm20+x2+b2) ; uint64 1835 1836 // test under mask 1837 inline void z_tmll(Register r1, int64_t i2); // test under mask, see docu 1838 inline void z_tmlh(Register r1, int64_t i2); // test under mask, see docu 1839 inline void z_tmhl(Register r1, int64_t i2); // test under mask, see docu 1840 inline void z_tmhh(Register r1, int64_t i2); // test under mask, see docu 1841 1842 // branch instructions 1843 inline void z_bc( branch_condition m1, int64_t d2, Register x2, Register b2);// branch m1 ? pc = (d2_uimm12+x2+b2) 1844 inline void z_bcr( branch_condition m1, Register r2); // branch (m1 && r2!=R0) ? pc = r2 1845 inline void z_brc( branch_condition i1, int64_t i2); // branch i1 ? pc = pc + i2_imm16 1846 inline void z_brc( branch_condition i1, address a); // branch i1 ? pc = a 1847 inline void z_brc( branch_condition i1, Label& L); // branch i1 ? pc = Label 1848 //inline void z_brcl(branch_condition i1, int64_t i2); // branch i1 ? pc = pc + i2_imm32 1849 inline void z_brcl(branch_condition i1, address a); // branch i1 ? pc = a 1850 inline void z_brcl(branch_condition i1, Label& L); // branch i1 ? pc = Label 1851 inline void z_bctgr(Register r1, Register r2); // branch on count r1 -= 1; (r1!=0) ? pc = r2 ; r1 is int64 1852 1853 // branch unconditional / always 1854 inline void z_br(Register r2); // branch to r2, nop if r2 == Z_R0 1855 1856 1857 // See also commodity routines compare64_and_branch(), compare32_and_branch(). 1858 // signed comparison and branch 1859 inline void z_crb( Register r1, Register r2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 r2) ? goto b4+d4 ; int32 -- z10 1860 inline void z_cgrb(Register r1, Register r2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 r2) ? goto b4+d4 ; int64 -- z10 1861 inline void z_crj( Register r1, Register r2, branch_condition m3, Label& L); // (r1 m3 r2) ? goto L ; int32 -- z10 1862 inline void z_crj( Register r1, Register r2, branch_condition m3, address a4); // (r1 m3 r2) ? goto (pc+a4<<1) ; int32 -- z10 1863 inline void z_cgrj(Register r1, Register r2, branch_condition m3, Label& L); // (r1 m3 r2) ? goto L ; int64 -- z10 1864 inline void z_cgrj(Register r1, Register r2, branch_condition m3, address a4); // (r1 m3 r2) ? goto (pc+a4<<1) ; int64 -- z10 1865 inline void z_cib( Register r1, int64_t i2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 i2_imm8) ? goto b4+d4 ; int32 -- z10 1866 inline void z_cgib(Register r1, int64_t i2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 i2_imm8) ? goto b4+d4 ; int64 -- z10 1867 inline void z_cij( Register r1, int64_t i2, branch_condition m3, Label& L); // (r1 m3 i2_imm8) ? goto L ; int32 -- z10 1868 inline void z_cij( Register r1, int64_t i2, branch_condition m3, address a4); // (r1 m3 i2_imm8) ? goto (pc+a4<<1) ; int32 -- z10 1869 inline void z_cgij(Register r1, int64_t i2, branch_condition m3, Label& L); // (r1 m3 i2_imm8) ? goto L ; int64 -- z10 1870 inline void z_cgij(Register r1, int64_t i2, branch_condition m3, address a4); // (r1 m3 i2_imm8) ? goto (pc+a4<<1) ; int64 -- z10 1871 // unsigned comparison and branch 1872 inline void z_clrb( Register r1, Register r2, branch_condition m3, int64_t d4, Register b4);// (r1 m3 r2) ? goto b4+d4 ; uint32 -- z10 1873 inline void z_clgrb(Register r1, Register r2, branch_condition m3, int64_t d4, Register b4);// (r1 m3 r2) ? goto b4+d4 ; uint64 -- z10 1874 inline void z_clrj( Register r1, Register r2, branch_condition m3, Label& L); // (r1 m3 r2) ? goto L ; uint32 -- z10 1875 inline void z_clrj( Register r1, Register r2, branch_condition m3, address a4); // (r1 m3 r2) ? goto (pc+a4<<1) ; uint32 -- z10 1876 inline void z_clgrj(Register r1, Register r2, branch_condition m3, Label& L); // (r1 m3 r2) ? goto L ; uint64 -- z10 1877 inline void z_clgrj(Register r1, Register r2, branch_condition m3, address a4); // (r1 m3 r2) ? goto (pc+a4<<1) ; uint64 -- z10 1878 inline void z_clib( Register r1, int64_t i2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 i2_uimm8) ? goto b4+d4 ; uint32 -- z10 1879 inline void z_clgib(Register r1, int64_t i2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 i2_uimm8) ? goto b4+d4 ; uint64 -- z10 1880 inline void z_clij( Register r1, int64_t i2, branch_condition m3, Label& L); // (r1 m3 i2_uimm8) ? goto L ; uint32 -- z10 1881 inline void z_clij( Register r1, int64_t i2, branch_condition m3, address a4); // (r1 m3 i2_uimm8) ? goto (pc+a4<<1) ; uint32 -- z10 1882 inline void z_clgij(Register r1, int64_t i2, branch_condition m3, Label& L); // (r1 m3 i2_uimm8) ? goto L ; uint64 -- z10 1883 inline void z_clgij(Register r1, int64_t i2, branch_condition m3, address a4); // (r1 m3 i2_uimm8) ? goto (pc+a4<<1) ; uint64 -- z10 1884 1885 // Compare and trap instructions. 1886 // signed comparison 1887 inline void z_crt(Register r1, Register r2, int64_t m3); // (r1 m3 r2) ? trap ; int32 -- z10 1888 inline void z_cgrt(Register r1, Register r2, int64_t m3); // (r1 m3 r2) ? trap ; int64 -- z10 1889 inline void z_cit(Register r1, int64_t i2, int64_t m3); // (r1 m3 i2_imm16) ? trap ; int32 -- z10 1890 inline void z_cgit(Register r1, int64_t i2, int64_t m3); // (r1 m3 i2_imm16) ? trap ; int64 -- z10 1891 // unsigned comparison 1892 inline void z_clrt(Register r1, Register r2, int64_t m3); // (r1 m3 r2) ? trap ; uint32 -- z10 1893 inline void z_clgrt(Register r1, Register r2, int64_t m3); // (r1 m3 r2) ? trap ; uint64 -- z10 1894 inline void z_clfit(Register r1, int64_t i2, int64_t m3); // (r1 m3 i2_uimm16) ? trap ; uint32 -- z10 1895 inline void z_clgit(Register r1, int64_t i2, int64_t m3); // (r1 m3 i2_uimm16) ? trap ; uint64 -- z10 1896 1897 inline void z_illtrap(); 1898 inline void z_illtrap(int id); 1899 inline void z_illtrap_eyecatcher(unsigned short xpattern, unsigned short pattern); 1900 1901 1902 // load address, add for addresses 1903 // =============================== 1904 1905 // The versions without suffix z assert that the base reg is != Z_R0. 1906 // Z_R0 is interpreted as constant '0'. The variants with Address operand 1907 // check this automatically, so no two versions are needed. 1908 inline void z_layz(Register r1, int64_t d2, Register x2, Register b2); // Special version. Allows Z_R0 as base reg. 1909 inline void z_lay(Register r1, const Address &a); // r1 = a 1910 inline void z_lay(Register r1, int64_t d2, Register x2, Register b2); // r1 = d2_imm20+x2+b2 1911 inline void z_laz(Register r1, int64_t d2, Register x2, Register b2); // Special version. Allows Z_R0 as base reg. 1912 inline void z_la(Register r1, const Address &a); // r1 = a ; unsigned immediate! 1913 inline void z_la(Register r1, int64_t d2, Register x2, Register b2); // r1 = d2_uimm12+x2+b2 ; unsigned immediate! 1914 inline void z_larl(Register r1, int64_t i2); // r1 = pc + i2_imm32<<1; 1915 inline void z_larl(Register r1, address a2); // r1 = pc + i2_imm32<<1; 1916 1917 // Load instructions for integers 1918 // ============================== 1919 1920 // Address as base + index + offset 1921 inline void z_lb( Register r1, const Address &a); // load r1 = *(a) ; int32 <- int8 1922 inline void z_lb( Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int32 <- int8 1923 inline void z_lh( Register r1, const Address &a); // load r1 = *(a) ; int32 <- int16 1924 inline void z_lh( Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_uimm12+x2+b2); int32 <- int16 1925 inline void z_lhy(Register r1, const Address &a); // load r1 = *(a) ; int32 <- int16 1926 inline void z_lhy(Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int32 <- int16 1927 inline void z_l( Register r1, const Address& a); // load r1 = *(a) ; int32 1928 inline void z_l( Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_uimm12+x2+b2); int32 1929 inline void z_ly( Register r1, const Address& a); // load r1 = *(a) ; int32 1930 inline void z_ly( Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int32 1931 1932 inline void z_lgb(Register r1, const Address &a); // load r1 = *(a) ; int64 <- int8 1933 inline void z_lgb(Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int64 <- int8 1934 inline void z_lgh(Register r1, const Address &a); // load r1 = *(a) ; int64 <- int16 1935 inline void z_lgh(Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm12+x2+b2) ; int64 <- int16 1936 inline void z_lgf(Register r1, const Address &a); // load r1 = *(a) ; int64 <- int32 1937 inline void z_lgf(Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int64 <- int32 1938 inline void z_lg( Register r1, const Address& a); // load r1 = *(a) ; int64 <- int64 1939 inline void z_lg( Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int64 <- int64 1940 1941 // load and test 1942 inline void z_lt( Register r1, const Address &a); // load and test r1 = *(a) ; int32 1943 inline void z_lt( Register r1, int64_t d2, Register x2, Register b2);// load and test r1 = *(d2_imm20+x2+b2) ; int32 1944 inline void z_ltg( Register r1, const Address &a); // load and test r1 = *(a) ; int64 1945 inline void z_ltg( Register r1, int64_t d2, Register x2, Register b2);// load and test r1 = *(d2_imm20+x2+b2) ; int64 1946 inline void z_ltgf(Register r1, const Address &a); // load and test r1 = *(a) ; int64 <- int32 1947 inline void z_ltgf(Register r1, int64_t d2, Register x2, Register b2);// load and test r1 = *(d2_imm20+x2+b2) ; int64 <- int32 1948 1949 // load unsigned integer - zero extended 1950 inline void z_llc( Register r1, const Address& a); // load r1 = *(a) ; uint32 <- uint8 1951 inline void z_llc( Register r1, int64_t d2, Register x2, Register b2);// load r1 = *(d2_imm20+x2+b2) ; uint32 <- uint8 1952 inline void z_llh( Register r1, const Address& a); // load r1 = *(a) ; uint32 <- uint16 1953 inline void z_llh( Register r1, int64_t d2, Register x2, Register b2);// load r1 = *(d2_imm20+x2+b2) ; uint32 <- uint16 1954 inline void z_llgc(Register r1, const Address& a); // load r1 = *(a) ; uint64 <- uint8 1955 inline void z_llgc(Register r1, int64_t d2, Register x2, Register b2);// load r1 = *(d2_imm20+x2+b2) ; uint64 <- uint8 1956 inline void z_llgc( Register r1, int64_t d2, Register b2); // load r1 = *(d2_imm20+b2) ; uint64 <- uint8 1957 inline void z_llgh(Register r1, const Address& a); // load r1 = *(a) ; uint64 <- uint16 1958 inline void z_llgh(Register r1, int64_t d2, Register x2, Register b2);// load r1 = *(d2_imm20+x2+b2) ; uint64 <- uint16 1959 inline void z_llgf(Register r1, const Address& a); // load r1 = *(a) ; uint64 <- uint32 1960 inline void z_llgf(Register r1, int64_t d2, Register x2, Register b2);// load r1 = *(d2_imm20+x2+b2) ; uint64 <- uint32 1961 1962 // pc relative addressing 1963 inline void z_lhrl( Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; int32 <- int16 -- z10 1964 inline void z_lrl( Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; int32 -- z10 1965 inline void z_lghrl(Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; int64 <- int16 -- z10 1966 inline void z_lgfrl(Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; int64 <- int32 -- z10 1967 inline void z_lgrl( Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; int64 -- z10 1968 1969 inline void z_llhrl( Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; uint32 <- uint16 -- z10 1970 inline void z_llghrl(Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; uint64 <- uint16 -- z10 1971 inline void z_llgfrl(Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; uint64 <- uint32 -- z10 1972 1973 // Store instructions for integers 1974 // =============================== 1975 1976 // Address as base + index + offset 1977 inline void z_stc( Register r1, const Address &d); // store *(a) = r1 ; int8 1978 inline void z_stc( Register r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; int8 1979 inline void z_stcy(Register r1, const Address &d); // store *(a) = r1 ; int8 1980 inline void z_stcy(Register r1, int64_t d2, Register x2, Register b2); // store *(d2_imm20+x2+b2) = r1 ; int8 1981 inline void z_sth( Register r1, const Address &d); // store *(a) = r1 ; int16 1982 inline void z_sth( Register r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; int16 1983 inline void z_sthy(Register r1, const Address &d); // store *(a) = r1 ; int16 1984 inline void z_sthy(Register r1, int64_t d2, Register x2, Register b2); // store *(d2_imm20+x2+b2) = r1 ; int16 1985 inline void z_st( Register r1, const Address &d); // store *(a) = r1 ; int32 1986 inline void z_st( Register r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; int32 1987 inline void z_sty( Register r1, const Address &d); // store *(a) = r1 ; int32 1988 inline void z_sty( Register r1, int64_t d2, Register x2, Register b2); // store *(d2_imm20+x2+b2) = r1 ; int32 1989 inline void z_stg( Register r1, const Address &d); // store *(a) = r1 ; int64 1990 inline void z_stg( Register r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; int64 1991 1992 inline void z_stcm( Register r1, int64_t m3, int64_t d2, Register b2); // store character under mask 1993 inline void z_stcmy(Register r1, int64_t m3, int64_t d2, Register b2); // store character under mask 1994 inline void z_stcmh(Register r1, int64_t m3, int64_t d2, Register b2); // store character under mask 1995 1996 // pc relative addressing 1997 inline void z_sthrl(Register r1, int64_t i2); // store *(pc + i2_imm32<<1) = r1 ; int16 -- z10 1998 inline void z_strl( Register r1, int64_t i2); // store *(pc + i2_imm32<<1) = r1 ; int32 -- z10 1999 inline void z_stgrl(Register r1, int64_t i2); // store *(pc + i2_imm32<<1) = r1 ; int64 -- z10 2000 2001 2002 // Load and store immediates 2003 // ========================= 2004 2005 // load immediate 2006 inline void z_lhi( Register r1, int64_t i2); // r1 = i2_imm16 ; int32 <- int16 2007 inline void z_lghi(Register r1, int64_t i2); // r1 = i2_imm16 ; int64 <- int16 2008 inline void z_lgfi(Register r1, int64_t i2); // r1 = i2_imm32 ; int64 <- int32 2009 2010 inline void z_llihf(Register r1, int64_t i2); // r1 = i2_imm32 ; uint64 <- (uint32<<32) 2011 inline void z_llilf(Register r1, int64_t i2); // r1 = i2_imm32 ; uint64 <- uint32 2012 inline void z_llihh(Register r1, int64_t i2); // r1 = i2_imm16 ; uint64 <- (uint16<<48) 2013 inline void z_llihl(Register r1, int64_t i2); // r1 = i2_imm16 ; uint64 <- (uint16<<32) 2014 inline void z_llilh(Register r1, int64_t i2); // r1 = i2_imm16 ; uint64 <- (uint16<<16) 2015 inline void z_llill(Register r1, int64_t i2); // r1 = i2_imm16 ; uint64 <- uint16 2016 2017 // insert immediate 2018 inline void z_ic( Register r1, int64_t d2, Register x2, Register b2); // insert character 2019 inline void z_icy( Register r1, int64_t d2, Register x2, Register b2); // insert character 2020 inline void z_icm( Register r1, int64_t m3, int64_t d2, Register b2); // insert character under mask 2021 inline void z_icmy(Register r1, int64_t m3, int64_t d2, Register b2); // insert character under mask 2022 inline void z_icmh(Register r1, int64_t m3, int64_t d2, Register b2); // insert character under mask 2023 2024 inline void z_iihh(Register r1, int64_t i2); // insert immediate r1[ 0-15] = i2_imm16 2025 inline void z_iihl(Register r1, int64_t i2); // insert immediate r1[16-31] = i2_imm16 2026 inline void z_iilh(Register r1, int64_t i2); // insert immediate r1[32-47] = i2_imm16 2027 inline void z_iill(Register r1, int64_t i2); // insert immediate r1[48-63] = i2_imm16 2028 inline void z_iihf(Register r1, int64_t i2); // insert immediate r1[32-63] = i2_imm32 2029 inline void z_iilf(Register r1, int64_t i2); // insert immediate r1[ 0-31] = i2_imm32 2030 2031 // store immediate 2032 inline void z_mvhhi(const Address &d, int64_t i2); // store *(d) = i2_imm16 ; int16 2033 inline void z_mvhhi(int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) = i2_imm16 ; int16 2034 inline void z_mvhi( const Address &d, int64_t i2); // store *(d) = i2_imm16 ; int32 2035 inline void z_mvhi( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) = i2_imm16 ; int32 2036 inline void z_mvghi(const Address &d, int64_t i2); // store *(d) = i2_imm16 ; int64 2037 inline void z_mvghi(int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) = i2_imm16 ; int64 2038 2039 // Move and Convert instructions 2040 // ============================= 2041 2042 // move, sign extend 2043 inline void z_lbr(Register r1, Register r2); // move r1 = r2 ; int32 <- int8 2044 inline void z_lhr( Register r1, Register r2); // move r1 = r2 ; int32 <- int16 2045 inline void z_lr(Register r1, Register r2); // move r1 = r2 ; int32, no sign extension 2046 inline void z_lgbr(Register r1, Register r2); // move r1 = r2 ; int64 <- int8 2047 inline void z_lghr(Register r1, Register r2); // move r1 = r2 ; int64 <- int16 2048 inline void z_lgfr(Register r1, Register r2); // move r1 = r2 ; int64 <- int32 2049 inline void z_lgr(Register r1, Register r2); // move r1 = r2 ; int64 2050 // move, zero extend 2051 inline void z_llhr( Register r1, Register r2); // move r1 = r2 ; uint32 <- uint16 2052 inline void z_llgcr(Register r1, Register r2); // move r1 = r2 ; uint64 <- uint8 2053 inline void z_llghr(Register r1, Register r2); // move r1 = r2 ; uint64 <- uint16 2054 inline void z_llgfr(Register r1, Register r2); // move r1 = r2 ; uint64 <- uint32 2055 2056 // move and test register 2057 inline void z_ltr(Register r1, Register r2); // load/move and test r1 = r2; int32 2058 inline void z_ltgr(Register r1, Register r2); // load/move and test r1 = r2; int64 2059 inline void z_ltgfr(Register r1, Register r2); // load/move and test r1 = r2; int64 <-- int32 2060 2061 // move and byte-reverse 2062 inline void z_lrvr( Register r1, Register r2); // move and reverse byte order r1 = r2; int32 2063 inline void z_lrvgr(Register r1, Register r2); // move and reverse byte order r1 = r2; int64 2064 2065 2066 // Arithmetic instructions (Integer only) 2067 // ====================================== 2068 // For float arithmetic instructions scroll further down 2069 // Add logical differs in the condition codes set! 2070 2071 // add registers 2072 inline void z_ar( Register r1, Register r2); // add r1 = r1 + r2 ; int32 2073 inline void z_agr( Register r1, Register r2); // add r1 = r1 + r2 ; int64 2074 inline void z_agfr( Register r1, Register r2); // add r1 = r1 + r2 ; int64 <- int32 2075 inline void z_ark( Register r1, Register r2, Register r3); // add r1 = r2 + r3 ; int32 2076 inline void z_agrk( Register r1, Register r2, Register r3); // add r1 = r2 + r3 ; int64 2077 2078 inline void z_alr( Register r1, Register r2); // add logical r1 = r1 + r2 ; int32 2079 inline void z_algr( Register r1, Register r2); // add logical r1 = r1 + r2 ; int64 2080 inline void z_algfr(Register r1, Register r2); // add logical r1 = r1 + r2 ; int64 <- int32 2081 inline void z_alrk( Register r1, Register r2, Register r3); // add logical r1 = r2 + r3 ; int32 2082 inline void z_algrk(Register r1, Register r2, Register r3); // add logical r1 = r2 + r3 ; int64 2083 inline void z_alcgr(Register r1, Register r2); // add logical with carry r1 = r1 + r2 + c ; int64 2084 2085 // add immediate 2086 inline void z_ahi( Register r1, int64_t i2); // add r1 = r1 + i2_imm16 ; int32 2087 inline void z_afi( Register r1, int64_t i2); // add r1 = r1 + i2_imm32 ; int32 2088 inline void z_alfi( Register r1, int64_t i2); // add r1 = r1 + i2_imm32 ; int32 2089 inline void z_aghi( Register r1, int64_t i2); // add logical r1 = r1 + i2_imm16 ; int64 2090 inline void z_agfi( Register r1, int64_t i2); // add r1 = r1 + i2_imm32 ; int64 2091 inline void z_algfi(Register r1, int64_t i2); // add logical r1 = r1 + i2_imm32 ; int64 2092 inline void z_ahik( Register r1, Register r3, int64_t i2); // add r1 = r3 + i2_imm16 ; int32 2093 inline void z_aghik(Register r1, Register r3, int64_t i2); // add r1 = r3 + i2_imm16 ; int64 2094 inline void z_aih( Register r1, int64_t i2); // add r1 = r1 + i2_imm32 ; int32 (HiWord) 2095 2096 // add memory 2097 inline void z_a( Register r1, int64_t d2, Register x2, Register b2); // add r1 = r1 + *(d2_uimm12+s2+b2) ; int32 2098 inline void z_ay( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+s2+b2) ; int32 2099 inline void z_ag( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+s2+b2) ; int64 2100 inline void z_agf( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+x2+b2) ; int64 <- int32 2101 inline void z_al( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_uimm12+x2+b2) ; int32 2102 inline void z_aly( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+x2+b2) ; int32 2103 inline void z_alg( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+x2+b2) ; int64 2104 inline void z_algf(Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+x2+b2) ; int64 <- int32 2105 inline void z_a( Register r1, const Address& a); // add r1 = r1 + *(a) ; int32 2106 inline void z_ay( Register r1, const Address& a); // add r1 = r1 + *(a) ; int32 2107 inline void z_al( Register r1, const Address& a); // add r1 = r1 + *(a) ; int32 2108 inline void z_aly( Register r1, const Address& a); // add r1 = r1 + *(a) ; int32 2109 inline void z_ag( Register r1, const Address& a); // add r1 = r1 + *(a) ; int64 2110 inline void z_agf( Register r1, const Address& a); // add r1 = r1 + *(a) ; int64 <- int32 2111 inline void z_alg( Register r1, const Address& a); // add r1 = r1 + *(a) ; int64 2112 inline void z_algf(Register r1, const Address& a); // add r1 = r1 + *(a) ; int64 <- int32 2113 2114 2115 inline void z_alhsik( Register r1, Register r3, int64_t i2); // add logical r1 = r3 + i2_imm16 ; int32 2116 inline void z_alghsik(Register r1, Register r3, int64_t i2); // add logical r1 = r3 + i2_imm16 ; int64 2117 2118 inline void z_asi( int64_t d1, Register b1, int64_t i2); // add *(d1_imm20+b1) += i2_imm8 ; int32 -- z10 2119 inline void z_agsi( int64_t d1, Register b1, int64_t i2); // add *(d1_imm20+b1) += i2_imm8 ; int64 -- z10 2120 inline void z_alsi( int64_t d1, Register b1, int64_t i2); // add logical *(d1_imm20+b1) += i2_imm8 ; uint32 -- z10 2121 inline void z_algsi(int64_t d1, Register b1, int64_t i2); // add logical *(d1_imm20+b1) += i2_imm8 ; uint64 -- z10 2122 inline void z_asi( const Address& d, int64_t i2); // add *(d) += i2_imm8 ; int32 -- z10 2123 inline void z_agsi( const Address& d, int64_t i2); // add *(d) += i2_imm8 ; int64 -- z10 2124 inline void z_alsi( const Address& d, int64_t i2); // add logical *(d) += i2_imm8 ; uint32 -- z10 2125 inline void z_algsi(const Address& d, int64_t i2); // add logical *(d) += i2_imm8 ; uint64 -- z10 2126 2127 // sign adjustment 2128 inline void z_lcr( Register r1, Register r2 = noreg); // neg r1 = -r2 ; int32 2129 inline void z_lcgr( Register r1, Register r2 = noreg); // neg r1 = -r2 ; int64 2130 inline void z_lcgfr(Register r1, Register r2); // neg r1 = -r2 ; int64 <- int32 2131 inline void z_lnr( Register r1, Register r2 = noreg); // neg r1 = -|r2| ; int32 2132 inline void z_lngr( Register r1, Register r2 = noreg); // neg r1 = -|r2| ; int64 2133 inline void z_lngfr(Register r1, Register r2); // neg r1 = -|r2| ; int64 <- int32 2134 inline void z_lpr( Register r1, Register r2 = noreg); // r1 = |r2| ; int32 2135 inline void z_lpgr( Register r1, Register r2 = noreg); // r1 = |r2| ; int64 2136 inline void z_lpgfr(Register r1, Register r2); // r1 = |r2| ; int64 <- int32 2137 2138 // subtract intstructions 2139 // sub registers 2140 inline void z_sr( Register r1, Register r2); // sub r1 = r1 - r2 ; int32 2141 inline void z_sgr( Register r1, Register r2); // sub r1 = r1 - r2 ; int64 2142 inline void z_sgfr( Register r1, Register r2); // sub r1 = r1 - r2 ; int64 <- int32 2143 inline void z_srk( Register r1, Register r2, Register r3); // sub r1 = r2 - r3 ; int32 2144 inline void z_sgrk( Register r1, Register r2, Register r3); // sub r1 = r2 - r3 ; int64 2145 2146 inline void z_slr( Register r1, Register r2); // sub logical r1 = r1 - r2 ; int32 2147 inline void z_slgr( Register r1, Register r2); // sub logical r1 = r1 - r2 ; int64 2148 inline void z_slgfr(Register r1, Register r2); // sub logical r1 = r1 - r2 ; int64 <- int32 2149 inline void z_slrk( Register r1, Register r2, Register r3); // sub logical r1 = r2 - r3 ; int32 2150 inline void z_slgrk(Register r1, Register r2, Register r3); // sub logical r1 = r2 - r3 ; int64 2151 inline void z_slfi( Register r1, int64_t i2); // sub logical r1 = r1 - i2_uimm32 ; int32 2152 inline void z_slgfi(Register r1, int64_t i2); // add logical r1 = r1 - i2_uimm32 ; int64 2153 2154 // sub memory 2155 inline void z_s( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 - *(d2_imm12+x2+b2) ; int32 2156 inline void z_sy( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 + *(d2_imm20+s2+b2) ; int32 2157 inline void z_sg( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 - *(d2_imm12+x2+b2) ; int64 2158 inline void z_sgf( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 - *(d2_imm12+x2+b2) ; int64 - int32 2159 inline void z_slg( Register r1, int64_t d2, Register x2, Register b2); // sub logical r1 = r1 - *(d2_imm20+x2+b2) ; uint64 2160 inline void z_slgf(Register r1, int64_t d2, Register x2, Register b2); // sub logical r1 = r1 - *(d2_imm20+x2+b2) ; uint64 - uint32 2161 inline void z_s( Register r1, const Address& a); // sub r1 = r1 - *(a) ; int32 2162 inline void z_sy( Register r1, const Address& a); // sub r1 = r1 - *(a) ; int32 2163 inline void z_sg( Register r1, const Address& a); // sub r1 = r1 - *(a) ; int64 2164 inline void z_sgf( Register r1, const Address& a); // sub r1 = r1 - *(a) ; int64 - int32 2165 inline void z_slg( Register r1, const Address& a); // sub r1 = r1 - *(a) ; uint64 2166 inline void z_slgf(Register r1, const Address& a); // sub r1 = r1 - *(a) ; uint64 - uint32 2167 2168 inline void z_sh( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 - *(d2_imm12+x2+b2) ; int32 - int16 2169 inline void z_shy( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 - *(d2_imm20+x2+b2) ; int32 - int16 2170 inline void z_sh( Register r1, const Address &a); // sub r1 = r1 - *(d2_imm12+x2+b2) ; int32 - int16 2171 inline void z_shy( Register r1, const Address &a); // sub r1 = r1 - *(d2_imm20+x2+b2) ; int32 - int16 2172 2173 // Multiplication instructions 2174 // mul registers 2175 inline void z_msr( Register r1, Register r2); // mul r1 = r1 * r2 ; int32 2176 inline void z_msgr( Register r1, Register r2); // mul r1 = r1 * r2 ; int64 2177 inline void z_msgfr(Register r1, Register r2); // mul r1 = r1 * r2 ; int64 <- int32 2178 inline void z_mlr( Register r1, Register r2); // mul r1 = r1 * r2 ; int32 unsigned 2179 inline void z_mlgr( Register r1, Register r2); // mul r1 = r1 * r2 ; int64 unsigned 2180 // mul register - memory 2181 inline void z_mhy( Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2) 2182 inline void z_msy( Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2) 2183 inline void z_msg( Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2) 2184 inline void z_msgf(Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2) 2185 inline void z_ml( Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2) 2186 inline void z_mlg( Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2) 2187 inline void z_mhy( Register r1, const Address& a); // mul r1 = r1 * *(a) 2188 inline void z_msy( Register r1, const Address& a); // mul r1 = r1 * *(a) 2189 inline void z_msg( Register r1, const Address& a); // mul r1 = r1 * *(a) 2190 inline void z_msgf(Register r1, const Address& a); // mul r1 = r1 * *(a) 2191 inline void z_ml( Register r1, const Address& a); // mul r1 = r1 * *(a) 2192 inline void z_mlg( Register r1, const Address& a); // mul r1 = r1 * *(a) 2193 2194 inline void z_msfi( Register r1, int64_t i2); // mult r1 = r1 * i2_imm32; int32 -- z10 2195 inline void z_msgfi(Register r1, int64_t i2); // mult r1 = r1 * i2_imm32; int64 -- z10 2196 inline void z_mhi( Register r1, int64_t i2); // mult r1 = r1 * i2_imm16; int32 2197 inline void z_mghi( Register r1, int64_t i2); // mult r1 = r1 * i2_imm16; int64 2198 2199 // Division instructions 2200 inline void z_dsgr( Register r1, Register r2); // div r1 = r1 / r2 ; int64/int32 needs reg pair! 2201 inline void z_dsgfr(Register r1, Register r2); // div r1 = r1 / r2 ; int64/int32 needs reg pair! 2202 2203 2204 // Logic instructions 2205 // =================== 2206 2207 // and 2208 inline void z_n( Register r1, int64_t d2, Register x2, Register b2); 2209 inline void z_ny( Register r1, int64_t d2, Register x2, Register b2); 2210 inline void z_ng( Register r1, int64_t d2, Register x2, Register b2); 2211 inline void z_n( Register r1, const Address& a); 2212 inline void z_ny( Register r1, const Address& a); 2213 inline void z_ng( Register r1, const Address& a); 2214 2215 inline void z_nr( Register r1, Register r2); // and r1 = r1 & r2 ; int32 2216 inline void z_ngr( Register r1, Register r2); // and r1 = r1 & r2 ; int64 2217 inline void z_nrk( Register r1, Register r2, Register r3); // and r1 = r2 & r3 ; int32 2218 inline void z_ngrk(Register r1, Register r2, Register r3); // and r1 = r2 & r3 ; int64 2219 2220 inline void z_nihh(Register r1, int64_t i2); // and r1 = r1 & i2_imm16 ; and only for bits 0-15 2221 inline void z_nihl(Register r1, int64_t i2); // and r1 = r1 & i2_imm16 ; and only for bits 16-31 2222 inline void z_nilh(Register r1, int64_t i2); // and r1 = r1 & i2_imm16 ; and only for bits 32-47 2223 inline void z_nill(Register r1, int64_t i2); // and r1 = r1 & i2_imm16 ; and only for bits 48-63 2224 inline void z_nihf(Register r1, int64_t i2); // and r1 = r1 & i2_imm32 ; and only for bits 0-31 2225 inline void z_nilf(Register r1, int64_t i2); // and r1 = r1 & i2_imm32 ; and only for bits 32-63 see also MacroAssembler::nilf. 2226 2227 // or 2228 inline void z_o( Register r1, int64_t d2, Register x2, Register b2); 2229 inline void z_oy( Register r1, int64_t d2, Register x2, Register b2); 2230 inline void z_og( Register r1, int64_t d2, Register x2, Register b2); 2231 inline void z_o( Register r1, const Address& a); 2232 inline void z_oy( Register r1, const Address& a); 2233 inline void z_og( Register r1, const Address& a); 2234 2235 inline void z_or( Register r1, Register r2); // or r1 = r1 | r2; int32 2236 inline void z_ogr( Register r1, Register r2); // or r1 = r1 | r2; int64 2237 inline void z_ork( Register r1, Register r2, Register r3); // or r1 = r2 | r3 ; int32 2238 inline void z_ogrk(Register r1, Register r2, Register r3); // or r1 = r2 | r3 ; int64 2239 2240 inline void z_oihh(Register r1, int64_t i2); // or r1 = r1 | i2_imm16 ; or only for bits 0-15 2241 inline void z_oihl(Register r1, int64_t i2); // or r1 = r1 | i2_imm16 ; or only for bits 16-31 2242 inline void z_oilh(Register r1, int64_t i2); // or r1 = r1 | i2_imm16 ; or only for bits 32-47 2243 inline void z_oill(Register r1, int64_t i2); // or r1 = r1 | i2_imm16 ; or only for bits 48-63 2244 inline void z_oihf(Register r1, int64_t i2); // or r1 = r1 | i2_imm32 ; or only for bits 0-31 2245 inline void z_oilf(Register r1, int64_t i2); // or r1 = r1 | i2_imm32 ; or only for bits 32-63 2246 2247 // xor 2248 inline void z_x( Register r1, int64_t d2, Register x2, Register b2); 2249 inline void z_xy( Register r1, int64_t d2, Register x2, Register b2); 2250 inline void z_xg( Register r1, int64_t d2, Register x2, Register b2); 2251 inline void z_x( Register r1, const Address& a); 2252 inline void z_xy( Register r1, const Address& a); 2253 inline void z_xg( Register r1, const Address& a); 2254 2255 inline void z_xr( Register r1, Register r2); // xor r1 = r1 ^ r2 ; int32 2256 inline void z_xgr( Register r1, Register r2); // xor r1 = r1 ^ r2 ; int64 2257 inline void z_xrk( Register r1, Register r2, Register r3); // xor r1 = r2 ^ r3 ; int32 2258 inline void z_xgrk(Register r1, Register r2, Register r3); // xor r1 = r2 ^ r3 ; int64 2259 2260 inline void z_xihf(Register r1, int64_t i2); // xor r1 = r1 ^ i2_imm32 ; or only for bits 0-31 2261 inline void z_xilf(Register r1, int64_t i2); // xor r1 = r1 ^ i2_imm32 ; or only for bits 32-63 2262 2263 // shift 2264 inline void z_sla( Register r1, int64_t d2, Register b2=Z_R0); // shift left r1 = r1 << ((d2+b2)&0x3f) ; int32, only 31 bits shifted, sign preserved! 2265 inline void z_slag(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int64, only 63 bits shifted, sign preserved! 2266 inline void z_sra( Register r1, int64_t d2, Register b2=Z_R0); // shift right r1 = r1 >> ((d2+b2)&0x3f) ; int32, sign extended 2267 inline void z_srag(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int64, sign extended 2268 inline void z_sll( Register r1, int64_t d2, Register b2=Z_R0); // shift left r1 = r1 << ((d2+b2)&0x3f) ; int32, zeros added 2269 inline void z_sllg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int64, zeros added 2270 inline void z_srl( Register r1, int64_t d2, Register b2=Z_R0); // shift right r1 = r1 >> ((d2+b2)&0x3f) ; int32, zero extended 2271 inline void z_srlg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int64, zero extended 2272 2273 // rotate 2274 inline void z_rll( Register r1, Register r3, int64_t d2, Register b2=Z_R0); // rot r1 = r3 << (d2+b2 & 0x3f) ; int32 -- z10 2275 inline void z_rllg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // rot r1 = r3 << (d2+b2 & 0x3f) ; int64 -- z10 2276 2277 // rotate the AND/XOR/OR/insert 2278 inline void z_rnsbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool test_only = false); // rotate then AND selected bits -- z196 2279 inline void z_rxsbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool test_only = false); // rotate then XOR selected bits -- z196 2280 inline void z_rosbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool test_only = false); // rotate then OR selected bits -- z196 2281 inline void z_risbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool zero_rest = false); // rotate then INS selected bits -- z196 2282 2283 2284 // memory-immediate instructions (8-bit immediate) 2285 // =============================================== 2286 2287 inline void z_cli( int64_t d1, Register b1, int64_t i2); // compare *(d1_imm12+b1) ^= i2_imm8 ; int8 2288 inline void z_mvi( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) = i2_imm8 ; int8 2289 inline void z_tm( int64_t d1, Register b1, int64_t i2); // test *(d1_imm12+b1) against mask i2_imm8 ; int8 2290 inline void z_ni( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) &= i2_imm8 ; int8 2291 inline void z_oi( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) |= i2_imm8 ; int8 2292 inline void z_xi( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) ^= i2_imm8 ; int8 2293 inline void z_cliy(int64_t d1, Register b1, int64_t i2); // compare *(d1_imm12+b1) ^= i2_imm8 ; int8 2294 inline void z_mviy(int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) = i2_imm8 ; int8 2295 inline void z_tmy( int64_t d1, Register b1, int64_t i2); // test *(d1_imm12+b1) against mask i2_imm8 ; int8 2296 inline void z_niy( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) &= i2_imm8 ; int8 2297 inline void z_oiy( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) |= i2_imm8 ; int8 2298 inline void z_xiy( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) ^= i2_imm8 ; int8 2299 inline void z_cli( const Address& a, int64_t imm8); // compare *(a) ^= imm8 ; int8 2300 inline void z_mvi( const Address& a, int64_t imm8); // store *(a) = imm8 ; int8 2301 inline void z_tm( const Address& a, int64_t imm8); // test *(a) against mask imm8 ; int8 2302 inline void z_ni( const Address& a, int64_t imm8); // store *(a) &= imm8 ; int8 2303 inline void z_oi( const Address& a, int64_t imm8); // store *(a) |= imm8 ; int8 2304 inline void z_xi( const Address& a, int64_t imm8); // store *(a) ^= imm8 ; int8 2305 inline void z_cliy(const Address& a, int64_t imm8); // compare *(a) ^= imm8 ; int8 2306 inline void z_mviy(const Address& a, int64_t imm8); // store *(a) = imm8 ; int8 2307 inline void z_tmy( const Address& a, int64_t imm8); // test *(a) against mask imm8 ; int8 2308 inline void z_niy( const Address& a, int64_t imm8); // store *(a) &= imm8 ; int8 2309 inline void z_oiy( const Address& a, int64_t imm8); // store *(a) |= imm8 ; int8 2310 inline void z_xiy( const Address& a, int64_t imm8); // store *(a) ^= imm8 ; int8 2311 2312 2313 //------------------------------ 2314 // Interlocked-Update 2315 //------------------------------ 2316 inline void z_laa( Register r1, Register r3, int64_t d2, Register b2); // load and add int32, signed -- z196 2317 inline void z_laag( Register r1, Register r3, int64_t d2, Register b2); // load and add int64, signed -- z196 2318 inline void z_laal( Register r1, Register r3, int64_t d2, Register b2); // load and add int32, unsigned -- z196 2319 inline void z_laalg(Register r1, Register r3, int64_t d2, Register b2); // load and add int64, unsigned -- z196 2320 inline void z_lan( Register r1, Register r3, int64_t d2, Register b2); // load and and int32 -- z196 2321 inline void z_lang( Register r1, Register r3, int64_t d2, Register b2); // load and and int64 -- z196 2322 inline void z_lax( Register r1, Register r3, int64_t d2, Register b2); // load and xor int32 -- z196 2323 inline void z_laxg( Register r1, Register r3, int64_t d2, Register b2); // load and xor int64 -- z196 2324 inline void z_lao( Register r1, Register r3, int64_t d2, Register b2); // load and or int32 -- z196 2325 inline void z_laog( Register r1, Register r3, int64_t d2, Register b2); // load and or int64 -- z196 2326 2327 inline void z_laa( Register r1, Register r3, const Address& a); // load and add int32, signed -- z196 2328 inline void z_laag( Register r1, Register r3, const Address& a); // load and add int64, signed -- z196 2329 inline void z_laal( Register r1, Register r3, const Address& a); // load and add int32, unsigned -- z196 2330 inline void z_laalg(Register r1, Register r3, const Address& a); // load and add int64, unsigned -- z196 2331 inline void z_lan( Register r1, Register r3, const Address& a); // load and and int32 -- z196 2332 inline void z_lang( Register r1, Register r3, const Address& a); // load and and int64 -- z196 2333 inline void z_lax( Register r1, Register r3, const Address& a); // load and xor int32 -- z196 2334 inline void z_laxg( Register r1, Register r3, const Address& a); // load and xor int64 -- z196 2335 inline void z_lao( Register r1, Register r3, const Address& a); // load and or int32 -- z196 2336 inline void z_laog( Register r1, Register r3, const Address& a); // load and or int64 -- z196 2337 2338 //-------------------------------- 2339 // Execution Prediction 2340 //-------------------------------- 2341 inline void z_pfd( int64_t m1, int64_t d2, Register x2, Register b2); // prefetch 2342 inline void z_pfd( int64_t m1, Address a); 2343 inline void z_pfdrl(int64_t m1, int64_t i2); // prefetch 2344 inline void z_bpp( int64_t m1, int64_t i2, int64_t d3, Register b3); // branch prediction -- EC12 2345 inline void z_bprp( int64_t m1, int64_t i2, int64_t i3); // branch prediction -- EC12 2346 2347 //------------------------------- 2348 // Transaction Control 2349 //------------------------------- 2350 inline void z_tbegin(int64_t d1, Register b1, int64_t i2); // begin transaction -- EC12 2351 inline void z_tbeginc(int64_t d1, Register b1, int64_t i2); // begin transaction (constrained) -- EC12 2352 inline void z_tend(); // end transaction -- EC12 2353 inline void z_tabort(int64_t d2, Register b2); // abort transaction -- EC12 2354 inline void z_etnd(Register r1); // extract tx nesting depth -- EC12 2355 inline void z_ppa(Register r1, Register r2, int64_t m3); // perform processor assist -- EC12 2356 2357 //--------------------------------- 2358 // Conditional Execution 2359 //--------------------------------- 2360 inline void z_locr( Register r1, Register r2, branch_condition cc); // if (cc) load r1 = r2 ; int32 -- z196 2361 inline void z_locgr(Register r1, Register r2, branch_condition cc); // if (cc) load r1 = r2 ; int64 -- z196 2362 inline void z_loc( Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) load r1 = *(d2_simm20+b2) ; int32 -- z196 2363 inline void z_locg( Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) load r1 = *(d2_simm20+b2) ; int64 -- z196 2364 inline void z_loc( Register r1, const Address& a, branch_condition cc); // if (cc) load r1 = *(a) ; int32 -- z196 2365 inline void z_locg( Register r1, const Address& a, branch_condition cc); // if (cc) load r1 = *(a) ; int64 -- z196 2366 inline void z_stoc( Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) store *(d2_simm20+b2) = r1 ; int32 -- z196 2367 inline void z_stocg(Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) store *(d2_simm20+b2) = r1 ; int64 -- z196 2368 2369 2370 // Complex CISC instructions 2371 // ========================== 2372 2373 inline void z_cksm(Register r1, Register r2); // checksum. This is NOT CRC32 2374 inline void z_km( Register r1, Register r2); // cipher message 2375 inline void z_kmc( Register r1, Register r2); // cipher message with chaining 2376 inline void z_kimd(Register r1, Register r2); // msg digest (SHA) 2377 inline void z_klmd(Register r1, Register r2); // msg digest (SHA) 2378 inline void z_kmac(Register r1, Register r2); // msg authentication code 2379 2380 inline void z_ex(Register r1, int64_t d2, Register x2, Register b2);// execute 2381 inline void z_exrl(Register r1, int64_t i2); // execute relative long -- z10 2382 inline void z_exrl(Register r1, address a2); // execute relative long -- z10 2383 2384 inline void z_ectg(int64_t d1, Register b1, int64_t d2, Register b2, Register r3); // extract cpu time 2385 inline void z_ecag(Register r1, Register r3, int64_t d2, Register b2); // extract CPU attribute 2386 2387 inline void z_srst(Register r1, Register r2); // search string 2388 inline void z_srstu(Register r1, Register r2); // search string unicode 2389 2390 inline void z_mvc(const Address& d, const Address& s, int64_t l); // move l bytes 2391 inline void z_mvc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2); // move l+1 bytes 2392 inline void z_mvcle(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // move region of memory 2393 2394 inline void z_stfle(int64_t d2, Register b2); // store facility list extended 2395 2396 inline void z_nc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);// and *(d1+b1) = *(d1+l+b1) & *(d2+b2) ; d1, d2: uimm12, ands l+1 bytes 2397 inline void z_oc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);// or *(d1+b1) = *(d1+l+b1) | *(d2+b2) ; d1, d2: uimm12, ors l+1 bytes 2398 inline void z_xc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);// xor *(d1+b1) = *(d1+l+b1) ^ *(d2+b2) ; d1, d2: uimm12, xors l+1 bytes 2399 inline void z_nc(Address dst, int64_t len, Address src2); // and *dst = *dst & *src2, ands len bytes in memory 2400 inline void z_oc(Address dst, int64_t len, Address src2); // or *dst = *dst | *src2, ors len bytes in memory 2401 inline void z_xc(Address dst, int64_t len, Address src2); // xor *dst = *dst ^ *src2, xors len bytes in memory 2402 2403 // compare instructions 2404 inline void z_clc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2); // compare (*(d1_uimm12+b1), *(d1_uimm12+b1)) ; compare l bytes 2405 inline void z_clcle(Register r1, Register r3, int64_t d2, Register b2); // compare logical long extended, see docu 2406 inline void z_clclu(Register r1, Register r3, int64_t d2, Register b2); // compare logical long unicode, see docu 2407 2408 // Translate characters 2409 inline void z_troo(Register r1, Register r2, int64_t m3); 2410 inline void z_trot(Register r1, Register r2, int64_t m3); 2411 inline void z_trto(Register r1, Register r2, int64_t m3); 2412 inline void z_trtt(Register r1, Register r2, int64_t m3); 2413 2414 2415 //--------------------------- 2416 //-- Vector Instructions -- 2417 //--------------------------- 2418 2419 //---< Vector Support Instructions >--- 2420 2421 // Load (transfer from memory) 2422 inline void z_vlm( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2); 2423 inline void z_vl( VectorRegister v1, int64_t d2, Register x2, Register b2); 2424 inline void z_vleb( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3); 2425 inline void z_vleh( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3); 2426 inline void z_vlef( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3); 2427 inline void z_vleg( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3); 2428 2429 // Gather/Scatter 2430 inline void z_vgef( VectorRegister v1, int64_t d2, VectorRegister vx2, Register b2, int64_t m3); 2431 inline void z_vgeg( VectorRegister v1, int64_t d2, VectorRegister vx2, Register b2, int64_t m3); 2432 2433 inline void z_vscef( VectorRegister v1, int64_t d2, VectorRegister vx2, Register b2, int64_t m3); 2434 inline void z_vsceg( VectorRegister v1, int64_t d2, VectorRegister vx2, Register b2, int64_t m3); 2435 2436 // load and replicate 2437 inline void z_vlrep( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3); 2438 inline void z_vlrepb(VectorRegister v1, int64_t d2, Register x2, Register b2); 2439 inline void z_vlreph(VectorRegister v1, int64_t d2, Register x2, Register b2); 2440 inline void z_vlrepf(VectorRegister v1, int64_t d2, Register x2, Register b2); 2441 inline void z_vlrepg(VectorRegister v1, int64_t d2, Register x2, Register b2); 2442 2443 inline void z_vllez( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3); 2444 inline void z_vllezb(VectorRegister v1, int64_t d2, Register x2, Register b2); 2445 inline void z_vllezh(VectorRegister v1, int64_t d2, Register x2, Register b2); 2446 inline void z_vllezf(VectorRegister v1, int64_t d2, Register x2, Register b2); 2447 inline void z_vllezg(VectorRegister v1, int64_t d2, Register x2, Register b2); 2448 2449 inline void z_vlbb( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3); 2450 inline void z_vll( VectorRegister v1, Register r3, int64_t d2, Register b2); 2451 2452 // Load (register to register) 2453 inline void z_vlr( VectorRegister v1, VectorRegister v2); 2454 2455 inline void z_vlgv( Register r1, VectorRegister v3, int64_t d2, Register b2, int64_t m4); 2456 inline void z_vlgvb( Register r1, VectorRegister v3, int64_t d2, Register b2); 2457 inline void z_vlgvh( Register r1, VectorRegister v3, int64_t d2, Register b2); 2458 inline void z_vlgvf( Register r1, VectorRegister v3, int64_t d2, Register b2); 2459 inline void z_vlgvg( Register r1, VectorRegister v3, int64_t d2, Register b2); 2460 2461 inline void z_vlvg( VectorRegister v1, Register r3, int64_t d2, Register b2, int64_t m4); 2462 inline void z_vlvgb( VectorRegister v1, Register r3, int64_t d2, Register b2); 2463 inline void z_vlvgh( VectorRegister v1, Register r3, int64_t d2, Register b2); 2464 inline void z_vlvgf( VectorRegister v1, Register r3, int64_t d2, Register b2); 2465 inline void z_vlvgg( VectorRegister v1, Register r3, int64_t d2, Register b2); 2466 2467 inline void z_vlvgp( VectorRegister v1, Register r2, Register r3); 2468 2469 // vector register pack 2470 inline void z_vpk( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2471 inline void z_vpkh( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2472 inline void z_vpkf( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2473 inline void z_vpkg( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2474 2475 inline void z_vpks( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4, int64_t cc5); 2476 inline void z_vpksh( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2477 inline void z_vpksf( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2478 inline void z_vpksg( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2479 inline void z_vpkshs(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2480 inline void z_vpksfs(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2481 inline void z_vpksgs(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2482 2483 inline void z_vpkls( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4, int64_t cc5); 2484 inline void z_vpklsh( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2485 inline void z_vpklsf( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2486 inline void z_vpklsg( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2487 inline void z_vpklshs(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2488 inline void z_vpklsfs(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2489 inline void z_vpklsgs(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2490 2491 // vector register unpack (sign-extended) 2492 inline void z_vuph( VectorRegister v1, VectorRegister v2, int64_t m3); 2493 inline void z_vuphb( VectorRegister v1, VectorRegister v2); 2494 inline void z_vuphh( VectorRegister v1, VectorRegister v2); 2495 inline void z_vuphf( VectorRegister v1, VectorRegister v2); 2496 inline void z_vupl( VectorRegister v1, VectorRegister v2, int64_t m3); 2497 inline void z_vuplb( VectorRegister v1, VectorRegister v2); 2498 inline void z_vuplh( VectorRegister v1, VectorRegister v2); 2499 inline void z_vuplf( VectorRegister v1, VectorRegister v2); 2500 2501 // vector register unpack (zero-extended) 2502 inline void z_vuplh( VectorRegister v1, VectorRegister v2, int64_t m3); 2503 inline void z_vuplhb( VectorRegister v1, VectorRegister v2); 2504 inline void z_vuplhh( VectorRegister v1, VectorRegister v2); 2505 inline void z_vuplhf( VectorRegister v1, VectorRegister v2); 2506 inline void z_vupll( VectorRegister v1, VectorRegister v2, int64_t m3); 2507 inline void z_vupllb( VectorRegister v1, VectorRegister v2); 2508 inline void z_vupllh( VectorRegister v1, VectorRegister v2); 2509 inline void z_vupllf( VectorRegister v1, VectorRegister v2); 2510 2511 // vector register merge high/low 2512 inline void z_vmrh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2513 inline void z_vmrhb(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2514 inline void z_vmrhh(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2515 inline void z_vmrhf(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2516 inline void z_vmrhg(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2517 2518 inline void z_vmrl( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2519 inline void z_vmrlb(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2520 inline void z_vmrlh(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2521 inline void z_vmrlf(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2522 inline void z_vmrlg(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2523 2524 // vector register permute 2525 inline void z_vperm( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4); 2526 inline void z_vpdi( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2527 2528 // vector register replicate 2529 inline void z_vrep( VectorRegister v1, VectorRegister v3, int64_t imm2, int64_t m4); 2530 inline void z_vrepb( VectorRegister v1, VectorRegister v3, int64_t imm2); 2531 inline void z_vreph( VectorRegister v1, VectorRegister v3, int64_t imm2); 2532 inline void z_vrepf( VectorRegister v1, VectorRegister v3, int64_t imm2); 2533 inline void z_vrepg( VectorRegister v1, VectorRegister v3, int64_t imm2); 2534 inline void z_vrepi( VectorRegister v1, int64_t imm2, int64_t m3); 2535 inline void z_vrepib(VectorRegister v1, int64_t imm2); 2536 inline void z_vrepih(VectorRegister v1, int64_t imm2); 2537 inline void z_vrepif(VectorRegister v1, int64_t imm2); 2538 inline void z_vrepig(VectorRegister v1, int64_t imm2); 2539 2540 inline void z_vsel( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4); 2541 inline void z_vseg( VectorRegister v1, VectorRegister v2, int64_t imm3); 2542 2543 // Load (immediate) 2544 inline void z_vleib( VectorRegister v1, int64_t imm2, int64_t m3); 2545 inline void z_vleih( VectorRegister v1, int64_t imm2, int64_t m3); 2546 inline void z_vleif( VectorRegister v1, int64_t imm2, int64_t m3); 2547 inline void z_vleig( VectorRegister v1, int64_t imm2, int64_t m3); 2548 2549 // Store 2550 inline void z_vstm( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2); 2551 inline void z_vst( VectorRegister v1, int64_t d2, Register x2, Register b2); 2552 inline void z_vsteb( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3); 2553 inline void z_vsteh( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3); 2554 inline void z_vstef( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3); 2555 inline void z_vsteg( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3); 2556 inline void z_vstl( VectorRegister v1, Register r3, int64_t d2, Register b2); 2557 2558 // Misc 2559 inline void z_vgm( VectorRegister v1, int64_t imm2, int64_t imm3, int64_t m4); 2560 inline void z_vgmb( VectorRegister v1, int64_t imm2, int64_t imm3); 2561 inline void z_vgmh( VectorRegister v1, int64_t imm2, int64_t imm3); 2562 inline void z_vgmf( VectorRegister v1, int64_t imm2, int64_t imm3); 2563 inline void z_vgmg( VectorRegister v1, int64_t imm2, int64_t imm3); 2564 2565 inline void z_vgbm( VectorRegister v1, int64_t imm2); 2566 inline void z_vzero( VectorRegister v1); // preferred method to set vreg to all zeroes 2567 inline void z_vone( VectorRegister v1); // preferred method to set vreg to all ones 2568 2569 //---< Vector Arithmetic Instructions >--- 2570 2571 // Load 2572 inline void z_vlc( VectorRegister v1, VectorRegister v2, int64_t m3); 2573 inline void z_vlcb( VectorRegister v1, VectorRegister v2); 2574 inline void z_vlch( VectorRegister v1, VectorRegister v2); 2575 inline void z_vlcf( VectorRegister v1, VectorRegister v2); 2576 inline void z_vlcg( VectorRegister v1, VectorRegister v2); 2577 inline void z_vlp( VectorRegister v1, VectorRegister v2, int64_t m3); 2578 inline void z_vlpb( VectorRegister v1, VectorRegister v2); 2579 inline void z_vlph( VectorRegister v1, VectorRegister v2); 2580 inline void z_vlpf( VectorRegister v1, VectorRegister v2); 2581 inline void z_vlpg( VectorRegister v1, VectorRegister v2); 2582 2583 // ADD 2584 inline void z_va( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2585 inline void z_vab( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2586 inline void z_vah( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2587 inline void z_vaf( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2588 inline void z_vag( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2589 inline void z_vaq( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2590 inline void z_vacc( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2591 inline void z_vaccb( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2592 inline void z_vacch( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2593 inline void z_vaccf( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2594 inline void z_vaccg( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2595 inline void z_vaccq( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2596 2597 // SUB 2598 inline void z_vs( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2599 inline void z_vsb( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2600 inline void z_vsh( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2601 inline void z_vsf( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2602 inline void z_vsg( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2603 inline void z_vsq( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2604 inline void z_vscbi( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2605 inline void z_vscbib( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2606 inline void z_vscbih( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2607 inline void z_vscbif( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2608 inline void z_vscbig( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2609 inline void z_vscbiq( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2610 2611 // MULTIPLY 2612 inline void z_vml( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2613 inline void z_vmh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2614 inline void z_vmlh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2615 inline void z_vme( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2616 inline void z_vmle( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2617 inline void z_vmo( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2618 inline void z_vmlo( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2619 2620 // MULTIPLY & ADD 2621 inline void z_vmal( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5); 2622 inline void z_vmah( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5); 2623 inline void z_vmalh( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5); 2624 inline void z_vmae( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5); 2625 inline void z_vmale( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5); 2626 inline void z_vmao( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5); 2627 inline void z_vmalo( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5); 2628 2629 // VECTOR SUM 2630 inline void z_vsum( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2631 inline void z_vsumb( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2632 inline void z_vsumh( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2633 inline void z_vsumg( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2634 inline void z_vsumgh( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2635 inline void z_vsumgf( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2636 inline void z_vsumq( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2637 inline void z_vsumqf( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2638 inline void z_vsumqg( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2639 2640 // Average 2641 inline void z_vavg( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2642 inline void z_vavgb( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2643 inline void z_vavgh( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2644 inline void z_vavgf( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2645 inline void z_vavgg( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2646 inline void z_vavgl( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2647 inline void z_vavglb( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2648 inline void z_vavglh( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2649 inline void z_vavglf( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2650 inline void z_vavglg( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2651 2652 // VECTOR Galois Field Multiply Sum 2653 inline void z_vgfm( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2654 inline void z_vgfmb( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2655 inline void z_vgfmh( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2656 inline void z_vgfmf( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2657 inline void z_vgfmg( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2658 // VECTOR Galois Field Multiply Sum and Accumulate 2659 inline void z_vgfma( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5); 2660 inline void z_vgfmab( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4); 2661 inline void z_vgfmah( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4); 2662 inline void z_vgfmaf( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4); 2663 inline void z_vgfmag( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4); 2664 2665 //---< Vector Logical Instructions >--- 2666 2667 // AND 2668 inline void z_vn( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2669 inline void z_vnc( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2670 2671 // XOR 2672 inline void z_vx( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2673 2674 // NOR 2675 inline void z_vno( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2676 2677 // OR 2678 inline void z_vo( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2679 2680 // Comparison (element-wise) 2681 inline void z_vceq( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4, int64_t cc5); 2682 inline void z_vceqb( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2683 inline void z_vceqh( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2684 inline void z_vceqf( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2685 inline void z_vceqg( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2686 inline void z_vceqbs( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2687 inline void z_vceqhs( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2688 inline void z_vceqfs( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2689 inline void z_vceqgs( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2690 inline void z_vch( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4, int64_t cc5); 2691 inline void z_vchb( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2692 inline void z_vchh( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2693 inline void z_vchf( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2694 inline void z_vchg( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2695 inline void z_vchbs( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2696 inline void z_vchhs( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2697 inline void z_vchfs( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2698 inline void z_vchgs( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2699 inline void z_vchl( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4, int64_t cc5); 2700 inline void z_vchlb( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2701 inline void z_vchlh( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2702 inline void z_vchlf( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2703 inline void z_vchlg( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2704 inline void z_vchlbs( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2705 inline void z_vchlhs( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2706 inline void z_vchlfs( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2707 inline void z_vchlgs( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2708 2709 // Max/Min (element-wise) 2710 inline void z_vmx( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2711 inline void z_vmxb( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2712 inline void z_vmxh( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2713 inline void z_vmxf( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2714 inline void z_vmxg( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2715 inline void z_vmxl( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2716 inline void z_vmxlb( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2717 inline void z_vmxlh( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2718 inline void z_vmxlf( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2719 inline void z_vmxlg( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2720 inline void z_vmn( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2721 inline void z_vmnb( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2722 inline void z_vmnh( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2723 inline void z_vmnf( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2724 inline void z_vmng( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2725 inline void z_vmnl( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2726 inline void z_vmnlb( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2727 inline void z_vmnlh( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2728 inline void z_vmnlf( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2729 inline void z_vmnlg( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2730 2731 // Leading/Trailing Zeros, population count 2732 inline void z_vclz( VectorRegister v1, VectorRegister v2, int64_t m3); 2733 inline void z_vclzb( VectorRegister v1, VectorRegister v2); 2734 inline void z_vclzh( VectorRegister v1, VectorRegister v2); 2735 inline void z_vclzf( VectorRegister v1, VectorRegister v2); 2736 inline void z_vclzg( VectorRegister v1, VectorRegister v2); 2737 inline void z_vctz( VectorRegister v1, VectorRegister v2, int64_t m3); 2738 inline void z_vctzb( VectorRegister v1, VectorRegister v2); 2739 inline void z_vctzh( VectorRegister v1, VectorRegister v2); 2740 inline void z_vctzf( VectorRegister v1, VectorRegister v2); 2741 inline void z_vctzg( VectorRegister v1, VectorRegister v2); 2742 inline void z_vpopct( VectorRegister v1, VectorRegister v2, int64_t m3); 2743 2744 // Rotate/Shift 2745 inline void z_verllv( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2746 inline void z_verllvb(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2747 inline void z_verllvh(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2748 inline void z_verllvf(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2749 inline void z_verllvg(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2750 inline void z_verll( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2, int64_t m4); 2751 inline void z_verllb( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2); 2752 inline void z_verllh( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2); 2753 inline void z_verllf( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2); 2754 inline void z_verllg( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2); 2755 inline void z_verim( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4, int64_t m5); 2756 inline void z_verimb( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4); 2757 inline void z_verimh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4); 2758 inline void z_verimf( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4); 2759 inline void z_verimg( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4); 2760 2761 inline void z_veslv( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2762 inline void z_veslvb( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2763 inline void z_veslvh( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2764 inline void z_veslvf( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2765 inline void z_veslvg( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2766 inline void z_vesl( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2, int64_t m4); 2767 inline void z_veslb( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2); 2768 inline void z_veslh( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2); 2769 inline void z_veslf( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2); 2770 inline void z_veslg( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2); 2771 2772 inline void z_vesrav( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2773 inline void z_vesravb(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2774 inline void z_vesravh(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2775 inline void z_vesravf(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2776 inline void z_vesravg(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2777 inline void z_vesra( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2, int64_t m4); 2778 inline void z_vesrab( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2); 2779 inline void z_vesrah( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2); 2780 inline void z_vesraf( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2); 2781 inline void z_vesrag( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2); 2782 inline void z_vesrlv( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4); 2783 inline void z_vesrlvb(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2784 inline void z_vesrlvh(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2785 inline void z_vesrlvf(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2786 inline void z_vesrlvg(VectorRegister v1, VectorRegister v2, VectorRegister v3); 2787 inline void z_vesrl( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2, int64_t m4); 2788 inline void z_vesrlb( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2); 2789 inline void z_vesrlh( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2); 2790 inline void z_vesrlf( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2); 2791 inline void z_vesrlg( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2); 2792 2793 inline void z_vsl( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2794 inline void z_vslb( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2795 inline void z_vsldb( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4); 2796 2797 inline void z_vsra( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2798 inline void z_vsrab( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2799 inline void z_vsrl( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2800 inline void z_vsrlb( VectorRegister v1, VectorRegister v2, VectorRegister v3); 2801 2802 // Test under Mask 2803 inline void z_vtm( VectorRegister v1, VectorRegister v2); 2804 2805 //---< Vector String Instructions >--- 2806 inline void z_vfae( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4, int64_t cc5); // Find any element 2807 inline void z_vfaeb( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t cc5); 2808 inline void z_vfaeh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t cc5); 2809 inline void z_vfaef( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t cc5); 2810 inline void z_vfee( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4, int64_t cc5); // Find element equal 2811 inline void z_vfeeb( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t cc5); 2812 inline void z_vfeeh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t cc5); 2813 inline void z_vfeef( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t cc5); 2814 inline void z_vfene( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4, int64_t cc5); // Find element not equal 2815 inline void z_vfeneb( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t cc5); 2816 inline void z_vfeneh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t cc5); 2817 inline void z_vfenef( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t cc5); 2818 inline void z_vstrc( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t imm5, int64_t cc6); // String range compare 2819 inline void z_vstrcb( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t cc6); 2820 inline void z_vstrch( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t cc6); 2821 inline void z_vstrcf( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t cc6); 2822 inline void z_vistr( VectorRegister v1, VectorRegister v2, int64_t imm3, int64_t cc5); // Isolate String 2823 inline void z_vistrb( VectorRegister v1, VectorRegister v2, int64_t cc5); 2824 inline void z_vistrh( VectorRegister v1, VectorRegister v2, int64_t cc5); 2825 inline void z_vistrf( VectorRegister v1, VectorRegister v2, int64_t cc5); 2826 inline void z_vistrbs(VectorRegister v1, VectorRegister v2); 2827 inline void z_vistrhs(VectorRegister v1, VectorRegister v2); 2828 inline void z_vistrfs(VectorRegister v1, VectorRegister v2); 2829 2830 2831 // Floatingpoint instructions 2832 // ========================== 2833 2834 // compare instructions 2835 inline void z_cebr(FloatRegister r1, FloatRegister r2); // compare (r1, r2) ; float 2836 inline void z_ceb(FloatRegister r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_imm12+x2+b2)) ; float 2837 inline void z_ceb(FloatRegister r1, const Address &a); // compare (r1, *(d2_imm12+x2+b2)) ; float 2838 inline void z_cdbr(FloatRegister r1, FloatRegister r2); // compare (r1, r2) ; double 2839 inline void z_cdb(FloatRegister r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_imm12+x2+b2)) ; double 2840 inline void z_cdb(FloatRegister r1, const Address &a); // compare (r1, *(d2_imm12+x2+b2)) ; double 2841 2842 // load instructions 2843 inline void z_le( FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_uimm12+x2+b2) ; float 2844 inline void z_ley(FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; float 2845 inline void z_ld( FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_uimm12+x2+b2) ; double 2846 inline void z_ldy(FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; double 2847 inline void z_le( FloatRegister r1, const Address &a); // load r1 = *(a) ; float 2848 inline void z_ley(FloatRegister r1, const Address &a); // load r1 = *(a) ; float 2849 inline void z_ld( FloatRegister r1, const Address &a); // load r1 = *(a) ; double 2850 inline void z_ldy(FloatRegister r1, const Address &a); // load r1 = *(a) ; double 2851 2852 // store instructions 2853 inline void z_ste( FloatRegister r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; float 2854 inline void z_stey(FloatRegister r1, int64_t d2, Register x2, Register b2); // store *(d2_imm20+x2+b2) = r1 ; float 2855 inline void z_std( FloatRegister r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; double 2856 inline void z_stdy(FloatRegister r1, int64_t d2, Register x2, Register b2); // store *(d2_imm20+x2+b2) = r1 ; double 2857 inline void z_ste( FloatRegister r1, const Address &a); // store *(a) = r1 ; float 2858 inline void z_stey(FloatRegister r1, const Address &a); // store *(a) = r1 ; float 2859 inline void z_std( FloatRegister r1, const Address &a); // store *(a) = r1 ; double 2860 inline void z_stdy(FloatRegister r1, const Address &a); // store *(a) = r1 ; double 2861 2862 // load and store immediates 2863 inline void z_lzer(FloatRegister r1); // r1 = 0 ; single 2864 inline void z_lzdr(FloatRegister r1); // r1 = 0 ; double 2865 2866 // Move and Convert instructions 2867 inline void z_ler(FloatRegister r1, FloatRegister r2); // move r1 = r2 ; float 2868 inline void z_ldr(FloatRegister r1, FloatRegister r2); // move r1 = r2 ; double 2869 inline void z_ledbr(FloatRegister r1, FloatRegister r2); // conv / round r1 = r2 ; float <- double 2870 inline void z_ldebr(FloatRegister r1, FloatRegister r2); // conv r1 = r2 ; double <- float 2871 2872 // move between integer and float registers 2873 inline void z_cefbr( FloatRegister r1, Register r2); // r1 = r2; float <-- int32 2874 inline void z_cdfbr( FloatRegister r1, Register r2); // r1 = r2; double <-- int32 2875 inline void z_cegbr( FloatRegister r1, Register r2); // r1 = r2; float <-- int64 2876 inline void z_cdgbr( FloatRegister r1, Register r2); // r1 = r2; double <-- int64 2877 2878 // rounding mode for float-2-int conversions 2879 inline void z_cfebr(Register r1, FloatRegister r2, RoundingMode m); // conv r1 = r2 ; int32 <-- float 2880 inline void z_cfdbr(Register r1, FloatRegister r2, RoundingMode m); // conv r1 = r2 ; int32 <-- double 2881 inline void z_cgebr(Register r1, FloatRegister r2, RoundingMode m); // conv r1 = r2 ; int64 <-- float 2882 inline void z_cgdbr(Register r1, FloatRegister r2, RoundingMode m); // conv r1 = r2 ; int64 <-- double 2883 2884 inline void z_ldgr(FloatRegister r1, Register r2); // fr1 = r2 ; what kind of conversion? -- z10 2885 inline void z_lgdr(Register r1, FloatRegister r2); // r1 = fr2 ; what kind of conversion? -- z10 2886 2887 2888 // ADD 2889 inline void z_aebr(FloatRegister f1, FloatRegister f2); // f1 = f1 + f2 ; float 2890 inline void z_adbr(FloatRegister f1, FloatRegister f2); // f1 = f1 + f2 ; double 2891 inline void z_aeb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 + *(d2+x2+b2) ; float 2892 inline void z_adb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 + *(d2+x2+b2) ; double 2893 inline void z_aeb( FloatRegister f1, const Address& a); // f1 = f1 + *(a) ; float 2894 inline void z_adb( FloatRegister f1, const Address& a); // f1 = f1 + *(a) ; double 2895 2896 // SUB 2897 inline void z_sebr(FloatRegister f1, FloatRegister f2); // f1 = f1 - f2 ; float 2898 inline void z_sdbr(FloatRegister f1, FloatRegister f2); // f1 = f1 - f2 ; double 2899 inline void z_seb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 - *(d2+x2+b2) ; float 2900 inline void z_sdb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 - *(d2+x2+b2) ; double 2901 inline void z_seb( FloatRegister f1, const Address& a); // f1 = f1 - *(a) ; float 2902 inline void z_sdb( FloatRegister f1, const Address& a); // f1 = f1 - *(a) ; double 2903 // negate 2904 inline void z_lcebr(FloatRegister r1, FloatRegister r2); // neg r1 = -r2 ; float 2905 inline void z_lcdbr(FloatRegister r1, FloatRegister r2); // neg r1 = -r2 ; double 2906 2907 // Absolute value, monadic if fr2 == noreg. 2908 inline void z_lpdbr( FloatRegister fr1, FloatRegister fr2 = fnoreg); // fr1 = |fr2| 2909 2910 2911 // MUL 2912 inline void z_meebr(FloatRegister f1, FloatRegister f2); // f1 = f1 * f2 ; float 2913 inline void z_mdbr( FloatRegister f1, FloatRegister f2); // f1 = f1 * f2 ; double 2914 inline void z_meeb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 * *(d2+x2+b2) ; float 2915 inline void z_mdb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 * *(d2+x2+b2) ; double 2916 inline void z_meeb( FloatRegister f1, const Address& a); 2917 inline void z_mdb( FloatRegister f1, const Address& a); 2918 2919 // MUL-ADD 2920 inline void z_maebr(FloatRegister f1, FloatRegister f3, FloatRegister f2); // f1 = f3 * f2 + f1 ; float 2921 inline void z_madbr(FloatRegister f1, FloatRegister f3, FloatRegister f2); // f1 = f3 * f2 + f1 ; double 2922 inline void z_msebr(FloatRegister f1, FloatRegister f3, FloatRegister f2); // f1 = f3 * f2 - f1 ; float 2923 inline void z_msdbr(FloatRegister f1, FloatRegister f3, FloatRegister f2); // f1 = f3 * f2 - f1 ; double 2924 inline void z_maeb(FloatRegister f1, FloatRegister f3, int64_t d2, Register x2, Register b2); // f1 = f3 * *(d2+x2+b2) + f1 ; float 2925 inline void z_madb(FloatRegister f1, FloatRegister f3, int64_t d2, Register x2, Register b2); // f1 = f3 * *(d2+x2+b2) + f1 ; double 2926 inline void z_mseb(FloatRegister f1, FloatRegister f3, int64_t d2, Register x2, Register b2); // f1 = f3 * *(d2+x2+b2) - f1 ; float 2927 inline void z_msdb(FloatRegister f1, FloatRegister f3, int64_t d2, Register x2, Register b2); // f1 = f3 * *(d2+x2+b2) - f1 ; double 2928 inline void z_maeb(FloatRegister f1, FloatRegister f3, const Address& a); 2929 inline void z_madb(FloatRegister f1, FloatRegister f3, const Address& a); 2930 inline void z_mseb(FloatRegister f1, FloatRegister f3, const Address& a); 2931 inline void z_msdb(FloatRegister f1, FloatRegister f3, const Address& a); 2932 2933 // DIV 2934 inline void z_debr( FloatRegister f1, FloatRegister f2); // f1 = f1 / f2 ; float 2935 inline void z_ddbr( FloatRegister f1, FloatRegister f2); // f1 = f1 / f2 ; double 2936 inline void z_deb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 / *(d2+x2+b2) ; float 2937 inline void z_ddb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 / *(d2+x2+b2) ; double 2938 inline void z_deb( FloatRegister f1, const Address& a); // f1 = f1 / *(a) ; float 2939 inline void z_ddb( FloatRegister f1, const Address& a); // f1 = f1 / *(a) ; double 2940 2941 // square root 2942 inline void z_sqdbr(FloatRegister fr1, FloatRegister fr2); // fr1 = sqrt(fr2) ; double 2943 inline void z_sqdb( FloatRegister fr1, int64_t d2, Register x2, Register b2); // fr1 = srqt( *(d2+x2+b2) 2944 inline void z_sqdb( FloatRegister fr1, int64_t d2, Register b2); // fr1 = srqt( *(d2+b2) 2945 2946 // Nop instruction 2947 // =============== 2948 2949 // branch never (nop) 2950 inline void z_nop(); 2951 2952 // =============================================================================================== 2953 2954 // Simplified emitters: 2955 // ==================== 2956 2957 2958 // Some memory instructions without index register (just convenience). 2959 inline void z_layz(Register r1, int64_t d2, Register b2 = Z_R0); 2960 inline void z_lay(Register r1, int64_t d2, Register b2); 2961 inline void z_laz(Register r1, int64_t d2, Register b2); 2962 inline void z_la(Register r1, int64_t d2, Register b2); 2963 inline void z_l(Register r1, int64_t d2, Register b2); 2964 inline void z_ly(Register r1, int64_t d2, Register b2); 2965 inline void z_lg(Register r1, int64_t d2, Register b2); 2966 inline void z_st(Register r1, int64_t d2, Register b2); 2967 inline void z_sty(Register r1, int64_t d2, Register b2); 2968 inline void z_stg(Register r1, int64_t d2, Register b2); 2969 inline void z_lgf(Register r1, int64_t d2, Register b2); 2970 inline void z_lgh(Register r1, int64_t d2, Register b2); 2971 inline void z_llgh(Register r1, int64_t d2, Register b2); 2972 inline void z_llgf(Register r1, int64_t d2, Register b2); 2973 inline void z_lgb(Register r1, int64_t d2, Register b2); 2974 inline void z_cl( Register r1, int64_t d2, Register b2); 2975 inline void z_c(Register r1, int64_t d2, Register b2); 2976 inline void z_cg(Register r1, int64_t d2, Register b2); 2977 inline void z_sh(Register r1, int64_t d2, Register b2); 2978 inline void z_shy(Register r1, int64_t d2, Register b2); 2979 inline void z_ste(FloatRegister r1, int64_t d2, Register b2); 2980 inline void z_std(FloatRegister r1, int64_t d2, Register b2); 2981 inline void z_stdy(FloatRegister r1, int64_t d2, Register b2); 2982 inline void z_stey(FloatRegister r1, int64_t d2, Register b2); 2983 inline void z_ld(FloatRegister r1, int64_t d2, Register b2); 2984 inline void z_ldy(FloatRegister r1, int64_t d2, Register b2); 2985 inline void z_le(FloatRegister r1, int64_t d2, Register b2); 2986 inline void z_ley(FloatRegister r1, int64_t d2, Register b2); 2987 2988 inline void z_agf(Register r1, int64_t d2, Register b2); 2989 2990 inline void z_exrl(Register r1, Label& L); 2991 inline void z_larl(Register r1, Label& L); 2992 inline void z_bru( Label& L); 2993 inline void z_brul(Label& L); 2994 inline void z_brul(address a); 2995 inline void z_brh( Label& L); 2996 inline void z_brl( Label& L); 2997 inline void z_bre( Label& L); 2998 inline void z_brnh(Label& L); 2999 inline void z_brnl(Label& L); 3000 inline void z_brne(Label& L); 3001 inline void z_brz( Label& L); 3002 inline void z_brnz(Label& L); 3003 inline void z_brnaz(Label& L); 3004 inline void z_braz(Label& L); 3005 inline void z_brnp(Label& L); 3006 3007 inline void z_btrue( Label& L); 3008 inline void z_bfalse(Label& L); 3009 3010 inline void z_brno( Label& L); 3011 3012 3013 inline void z_basr(Register r1, Register r2); 3014 inline void z_brasl(Register r1, address a); 3015 inline void z_brct(Register r1, address a); 3016 inline void z_brct(Register r1, Label& L); 3017 3018 inline void z_brxh(Register r1, Register r3, address a); 3019 inline void z_brxh(Register r1, Register r3, Label& L); 3020 3021 inline void z_brxle(Register r1, Register r3, address a); 3022 inline void z_brxle(Register r1, Register r3, Label& L); 3023 3024 inline void z_brxhg(Register r1, Register r3, address a); 3025 inline void z_brxhg(Register r1, Register r3, Label& L); 3026 3027 inline void z_brxlg(Register r1, Register r3, address a); 3028 inline void z_brxlg(Register r1, Register r3, Label& L); 3029 3030 // Ppopulation count intrinsics. 3031 inline void z_flogr(Register r1, Register r2); // find leftmost one 3032 inline void z_popcnt(Register r1, Register r2); // population count 3033 inline void z_ahhhr(Register r1, Register r2, Register r3); // ADD halfword high high 3034 inline void z_ahhlr(Register r1, Register r2, Register r3); // ADD halfword high low 3035 3036 inline void z_tam(); 3037 inline void z_stckf(int64_t d2, Register b2); 3038 inline void z_stmg(Register r1, Register r3, int64_t d2, Register b2); 3039 inline void z_lmg(Register r1, Register r3, int64_t d2, Register b2); 3040 3041 inline void z_cs( Register r1, Register r3, int64_t d2, Register b2); 3042 inline void z_csy(Register r1, Register r3, int64_t d2, Register b2); 3043 inline void z_csg(Register r1, Register r3, int64_t d2, Register b2); 3044 inline void z_cs( Register r1, Register r3, const Address& a); 3045 inline void z_csy(Register r1, Register r3, const Address& a); 3046 inline void z_csg(Register r1, Register r3, const Address& a); 3047 3048 inline void z_cvd(Register r1, int64_t d2, Register x2, Register b2); 3049 inline void z_cvdg(Register r1, int64_t d2, Register x2, Register b2); 3050 inline void z_cvd(Register r1, int64_t d2, Register b2); 3051 inline void z_cvdg(Register r1, int64_t d2, Register b2); 3052 3053 // Instruction queries: 3054 // instruction properties and recognize emitted instructions 3055 // =========================================================== 3056 3057 static int nop_size() { return 2; } 3058 3059 static int z_brul_size() { return 6; } 3060 3061 static bool is_z_basr(short x) { 3062 return (BASR_ZOPC == (x & BASR_MASK)); 3063 } 3064 static bool is_z_algr(long x) { 3065 return (ALGR_ZOPC == (x & RRE_MASK)); 3066 } 3067 static bool is_z_lb(long x) { 3068 return (LB_ZOPC == (x & LB_MASK)); 3069 } 3070 static bool is_z_lh(int x) { 3071 return (LH_ZOPC == (x & LH_MASK)); 3072 } 3073 static bool is_z_l(int x) { 3074 return (L_ZOPC == (x & L_MASK)); 3075 } 3076 static bool is_z_lgr(long x) { 3077 return (LGR_ZOPC == (x & RRE_MASK)); 3078 } 3079 static bool is_z_ly(long x) { 3080 return (LY_ZOPC == (x & LY_MASK)); 3081 } 3082 static bool is_z_lg(long x) { 3083 return (LG_ZOPC == (x & LG_MASK)); 3084 } 3085 static bool is_z_llgh(long x) { 3086 return (LLGH_ZOPC == (x & LLGH_MASK)); 3087 } 3088 static bool is_z_llgf(long x) { 3089 return (LLGF_ZOPC == (x & LLGF_MASK)); 3090 } 3091 static bool is_z_le(int x) { 3092 return (LE_ZOPC == (x & LE_MASK)); 3093 } 3094 static bool is_z_ld(int x) { 3095 return (LD_ZOPC == (x & LD_MASK)); 3096 } 3097 static bool is_z_st(int x) { 3098 return (ST_ZOPC == (x & ST_MASK)); 3099 } 3100 static bool is_z_stc(int x) { 3101 return (STC_ZOPC == (x & STC_MASK)); 3102 } 3103 static bool is_z_stg(long x) { 3104 return (STG_ZOPC == (x & STG_MASK)); 3105 } 3106 static bool is_z_sth(int x) { 3107 return (STH_ZOPC == (x & STH_MASK)); 3108 } 3109 static bool is_z_ste(int x) { 3110 return (STE_ZOPC == (x & STE_MASK)); 3111 } 3112 static bool is_z_std(int x) { 3113 return (STD_ZOPC == (x & STD_MASK)); 3114 } 3115 static bool is_z_slag(long x) { 3116 return (SLAG_ZOPC == (x & SLAG_MASK)); 3117 } 3118 static bool is_z_tmy(long x) { 3119 return (TMY_ZOPC == (x & TMY_MASK)); 3120 } 3121 static bool is_z_tm(long x) { 3122 return ((unsigned int)TM_ZOPC == (x & (unsigned int)TM_MASK)); 3123 } 3124 static bool is_z_bcr(long x) { 3125 return (BCR_ZOPC == (x & BCR_MASK)); 3126 } 3127 static bool is_z_nop(long x) { 3128 return is_z_bcr(x) && ((x & 0x00ff) == 0); 3129 } 3130 static bool is_z_nop(address x) { 3131 return is_z_nop(* (short *) x); 3132 } 3133 static bool is_z_br(long x) { 3134 return is_z_bcr(x) && ((x & 0x00f0) == 0x00f0); 3135 } 3136 static bool is_z_brc(long x, int cond) { 3137 return ((unsigned int)BRC_ZOPC == (x & BRC_MASK)) && ((cond<<20) == (x & 0x00f00000U)); 3138 } 3139 // Make use of lightweight sync. 3140 static bool is_z_sync_full(long x) { 3141 return is_z_bcr(x) && (((x & 0x00f0)>>4)==bcondFullSync) && ((x & 0x000f)==0x0000); 3142 } 3143 static bool is_z_sync_light(long x) { 3144 return is_z_bcr(x) && (((x & 0x00f0)>>4)==bcondLightSync) && ((x & 0x000f)==0x0000); 3145 } 3146 static bool is_z_sync(long x) { 3147 return is_z_sync_full(x) || is_z_sync_light(x); 3148 } 3149 3150 static bool is_z_brasl(long x) { 3151 return (BRASL_ZOPC == (x & BRASL_MASK)); 3152 } 3153 static bool is_z_brasl(address a) { 3154 long x = (*((long *)a))>>16; 3155 return is_z_brasl(x); 3156 } 3157 static bool is_z_larl(long x) { 3158 return (LARL_ZOPC == (x & LARL_MASK)); 3159 } 3160 static bool is_z_lgrl(long x) { 3161 return (LGRL_ZOPC == (x & LGRL_MASK)); 3162 } 3163 static bool is_z_lgrl(address a) { 3164 long x = (*((long *)a))>>16; 3165 return is_z_lgrl(x); 3166 } 3167 3168 static bool is_z_lghi(unsigned long x) { 3169 return (unsigned int)LGHI_ZOPC == (x & (unsigned int)LGHI_MASK); 3170 } 3171 3172 static bool is_z_llill(unsigned long x) { 3173 return (unsigned int)LLILL_ZOPC == (x & (unsigned int)LLI_MASK); 3174 } 3175 static bool is_z_llilh(unsigned long x) { 3176 return (unsigned int)LLILH_ZOPC == (x & (unsigned int)LLI_MASK); 3177 } 3178 static bool is_z_llihl(unsigned long x) { 3179 return (unsigned int)LLIHL_ZOPC == (x & (unsigned int)LLI_MASK); 3180 } 3181 static bool is_z_llihh(unsigned long x) { 3182 return (unsigned int)LLIHH_ZOPC == (x & (unsigned int)LLI_MASK); 3183 } 3184 static bool is_z_llilf(unsigned long x) { 3185 return LLILF_ZOPC == (x & LLIF_MASK); 3186 } 3187 static bool is_z_llihf(unsigned long x) { 3188 return LLIHF_ZOPC == (x & LLIF_MASK); 3189 } 3190 3191 static bool is_z_iill(unsigned long x) { 3192 return (unsigned int)IILL_ZOPC == (x & (unsigned int)II_MASK); 3193 } 3194 static bool is_z_iilh(unsigned long x) { 3195 return (unsigned int)IILH_ZOPC == (x & (unsigned int)II_MASK); 3196 } 3197 static bool is_z_iihl(unsigned long x) { 3198 return (unsigned int)IIHL_ZOPC == (x & (unsigned int)II_MASK); 3199 } 3200 static bool is_z_iihh(unsigned long x) { 3201 return (unsigned int)IIHH_ZOPC == (x & (unsigned int)II_MASK); 3202 } 3203 static bool is_z_iilf(unsigned long x) { 3204 return IILF_ZOPC == (x & IIF_MASK); 3205 } 3206 static bool is_z_iihf(unsigned long x) { 3207 return IIHF_ZOPC == (x & IIF_MASK); 3208 } 3209 3210 static inline bool is_equal(unsigned long inst, unsigned long idef); 3211 static inline bool is_equal(unsigned long inst, unsigned long idef, unsigned long imask); 3212 static inline bool is_equal(address iloc, unsigned long idef); 3213 static inline bool is_equal(address iloc, unsigned long idef, unsigned long imask); 3214 3215 static inline bool is_sigtrap_range_check(address pc); 3216 static inline bool is_sigtrap_zero_check(address pc); 3217 3218 //----------------- 3219 // memory barriers 3220 //----------------- 3221 // machine barrier instructions: 3222 // 3223 // - z_sync Two-way memory barrier, aka fence. 3224 // Only load-after-store-order is not guaranteed in the 3225 // z/Architecture memory model, i.e. only 'fence' is needed. 3226 // 3227 // semantic barrier instructions: 3228 // (as defined in orderAccess.hpp) 3229 // 3230 // - z_release orders Store|Store, empty implementation 3231 // Load|Store 3232 // - z_acquire orders Load|Store, empty implementation 3233 // Load|Load 3234 // - z_fence orders Store|Store, implemented as z_sync. 3235 // Load|Store, 3236 // Load|Load, 3237 // Store|Load 3238 // 3239 // For this implementation to be correct, we need H/W fixes on (very) old H/W: 3240 // For z990, it is Driver-55: MCL232 in the J13484 (i390/ML) Stream. 3241 // For z9, it is Driver-67: MCL065 in the G40963 (i390/ML) Stream. 3242 // These drivers are a prereq. Otherwise, memory synchronization will not work. 3243 3244 inline void z_sync(); 3245 inline void z_release(); 3246 inline void z_acquire(); 3247 inline void z_fence(); 3248 3249 // Creation 3250 Assembler(CodeBuffer* code) : AbstractAssembler(code) { } 3251 3252 }; 3253 3254 #endif // CPU_S390_VM_ASSEMBLER_S390_HPP