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src/hotspot/cpu/s390/assembler_s390.hpp
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@@ -580,11 +580,15 @@
#define LLGFRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0eL << 32) // z10
#define LOC_ZOPC (unsigned long)(0xebL << 40 | 0xf2L) // z196
#define LOCG_ZOPC (unsigned long)(0xebL << 40 | 0xe2L) // z196
-#define LMG_ZOPC (unsigned long)(235L << 40 | 4L)
+
+// LOAD multiple registers at once
+#define LM_ZOPC (unsigned int)(0x98 << 24)
+#define LMY_ZOPC (unsigned long)(0xebL << 40 | 0x98L)
+#define LMG_ZOPC (unsigned long)(0xebL << 40 | 0x04L)
#define LE_ZOPC (unsigned int)(0x78 << 24)
#define LEY_ZOPC (unsigned long)(237L << 40 | 100L)
#define LDEB_ZOPC (unsigned long)(237L << 40 | 4)
#define LD_ZOPC (unsigned int)(0x68 << 24)
@@ -611,11 +615,14 @@
#define STGRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0bL << 32) // z10
#define STOC_ZOPC (unsigned long)(0xebL << 40 | 0xf3L) // z196
#define STOCG_ZOPC (unsigned long)(0xebL << 40 | 0xe3L) // z196
-#define STMG_ZOPC (unsigned long)(235L << 40 | 36L)
+// STORE multiple registers at once
+#define STM_ZOPC (unsigned int)(0x90 << 24)
+#define STMY_ZOPC (unsigned long)(0xebL << 40 | 0x90L)
+#define STMG_ZOPC (unsigned long)(0xebL << 40 | 0x24L)
#define STE_ZOPC (unsigned int)(0x70 << 24)
#define STEY_ZOPC (unsigned long)(237L << 40 | 102L)
#define STD_ZOPC (unsigned int)(0x60 << 24)
#define STDY_ZOPC (unsigned long)(237L << 40 | 103L)
@@ -872,19 +879,23 @@
#define CEB_ZOPC (unsigned long)(237L << 40 | 9)
#define CDB_ZOPC (unsigned long)(237L << 40 | 25)
// Shift
// arithmetic
-#define SLA_ZOPC (unsigned int)(139 << 24)
-#define SLAG_ZOPC (unsigned long)(235L << 40 | 11L)
-#define SRA_ZOPC (unsigned int)(138 << 24)
-#define SRAG_ZOPC (unsigned long)(235L << 40 | 10L)
+#define SLA_ZOPC (unsigned int)(0x8b << 24)
+#define SLAK_ZOPC (unsigned long)(0xebL << 40 | 0xddL)
+#define SLAG_ZOPC (unsigned long)(0xebL << 40 | 0x0bL)
+#define SRA_ZOPC (unsigned int)(0x8a << 24)
+#define SRAK_ZOPC (unsigned long)(0xebL << 40 | 0xdcL)
+#define SRAG_ZOPC (unsigned long)(0xebL << 40 | 0x0aL)
// logical
-#define SLL_ZOPC (unsigned int)(137 << 24)
-#define SLLG_ZOPC (unsigned long)(235L << 40 | 13L)
-#define SRL_ZOPC (unsigned int)(136 << 24)
-#define SRLG_ZOPC (unsigned long)(235L << 40 | 12L)
+#define SLL_ZOPC (unsigned int)(0x89 << 24)
+#define SLLK_ZOPC (unsigned long)(0xebL << 40 | 0xdfL)
+#define SLLG_ZOPC (unsigned long)(0xebL << 40 | 0x0dL)
+#define SRL_ZOPC (unsigned int)(0x88 << 24)
+#define SRLK_ZOPC (unsigned long)(0xebL << 40 | 0xdeL)
+#define SRLG_ZOPC (unsigned long)(0xebL << 40 | 0x0cL)
// Rotate, then AND/XOR/OR/insert
// rotate
#define RLL_ZOPC (unsigned long)(0xebL << 40 | 0x1dL) // z10
#define RLLG_ZOPC (unsigned long)(0xebL << 40 | 0x1cL) // z10
@@ -2260,16 +2271,20 @@
inline void z_xihf(Register r1, int64_t i2); // xor r1 = r1 ^ i2_imm32 ; or only for bits 0-31
inline void z_xilf(Register r1, int64_t i2); // xor r1 = r1 ^ i2_imm32 ; or only for bits 32-63
// shift
inline void z_sla( Register r1, int64_t d2, Register b2=Z_R0); // shift left r1 = r1 << ((d2+b2)&0x3f) ; int32, only 31 bits shifted, sign preserved!
+ inline void z_slak(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int32, only 31 bits shifted, sign preserved!
inline void z_slag(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int64, only 63 bits shifted, sign preserved!
inline void z_sra( Register r1, int64_t d2, Register b2=Z_R0); // shift right r1 = r1 >> ((d2+b2)&0x3f) ; int32, sign extended
+ inline void z_srak(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int32, sign extended
inline void z_srag(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int64, sign extended
inline void z_sll( Register r1, int64_t d2, Register b2=Z_R0); // shift left r1 = r1 << ((d2+b2)&0x3f) ; int32, zeros added
+ inline void z_sllk(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int32, zeros added
inline void z_sllg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int64, zeros added
inline void z_srl( Register r1, int64_t d2, Register b2=Z_R0); // shift right r1 = r1 >> ((d2+b2)&0x3f) ; int32, zero extended
+ inline void z_srlk(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int32, zero extended
inline void z_srlg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int64, zero extended
// rotate
inline void z_rll( Register r1, Register r3, int64_t d2, Register b2=Z_R0); // rot r1 = r3 << (d2+b2 & 0x3f) ; int32 -- z10
inline void z_rllg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // rot r1 = r3 << (d2+b2 & 0x3f) ; int64 -- z10
@@ -3033,11 +3048,15 @@
inline void z_ahhhr(Register r1, Register r2, Register r3); // ADD halfword high high
inline void z_ahhlr(Register r1, Register r2, Register r3); // ADD halfword high low
inline void z_tam();
inline void z_stckf(int64_t d2, Register b2);
+ inline void z_stm( Register r1, Register r3, int64_t d2, Register b2);
+ inline void z_stmy(Register r1, Register r3, int64_t d2, Register b2);
inline void z_stmg(Register r1, Register r3, int64_t d2, Register b2);
+ inline void z_lm( Register r1, Register r3, int64_t d2, Register b2);
+ inline void z_lmy(Register r1, Register r3, int64_t d2, Register b2);
inline void z_lmg(Register r1, Register r3, int64_t d2, Register b2);
inline void z_cs( Register r1, Register r3, int64_t d2, Register b2);
inline void z_csy(Register r1, Register r3, int64_t d2, Register b2);
inline void z_csg(Register r1, Register r3, int64_t d2, Register b2);
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