565
566 #define LRVH_ZOPC (unsigned long)(0xe3L << 40 | 0x1fL)
567 #define LRV_ZOPC (unsigned long)(0xe3L << 40 | 0x1eL)
568 #define LRVG_ZOPC (unsigned long)(0xe3L << 40 | 0x0fL)
569
570
571 // LOAD relative: memory to register transfer
572 #define LHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x05L << 32) // z10
573 #define LRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0dL << 32) // z10
574 #define LGHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x04L << 32) // z10
575 #define LGFRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0cL << 32) // z10
576 #define LGRL_ZOPC (unsigned long)(0xc4L << 40 | 0x08L << 32) // z10
577
578 #define LLHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x02L << 32) // z10
579 #define LLGHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x06L << 32) // z10
580 #define LLGFRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0eL << 32) // z10
581
582 #define LOC_ZOPC (unsigned long)(0xebL << 40 | 0xf2L) // z196
583 #define LOCG_ZOPC (unsigned long)(0xebL << 40 | 0xe2L) // z196
584
585 #define LMG_ZOPC (unsigned long)(235L << 40 | 4L)
586
587 #define LE_ZOPC (unsigned int)(0x78 << 24)
588 #define LEY_ZOPC (unsigned long)(237L << 40 | 100L)
589 #define LDEB_ZOPC (unsigned long)(237L << 40 | 4)
590 #define LD_ZOPC (unsigned int)(0x68 << 24)
591 #define LDY_ZOPC (unsigned long)(237L << 40 | 101L)
592 #define LXEB_ZOPC (unsigned long)(237L << 40 | 6)
593 #define LXDB_ZOPC (unsigned long)(237L << 40 | 5)
594
595 // STORE: register to memory transfer
596 #define STC_ZOPC (unsigned int)(0x42 << 24)
597 #define STCY_ZOPC (unsigned long)(227L << 40 | 114L)
598 #define STH_ZOPC (unsigned int)(64 << 24)
599 #define STHY_ZOPC (unsigned long)(227L << 40 | 112L)
600 #define ST_ZOPC (unsigned int)(80 << 24)
601 #define STY_ZOPC (unsigned long)(227L << 40 | 80L)
602 #define STG_ZOPC (unsigned long)(227L << 40 | 36L)
603
604 #define STCM_ZOPC (unsigned long)(0xbeL << 24)
605 #define STCMY_ZOPC (unsigned long)(0xebL << 40 | 0x2dL)
606 #define STCMH_ZOPC (unsigned long)(0xebL << 40 | 0x2cL)
607
608 // STORE relative: memory to register transfer
609 #define STHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x07L << 32) // z10
610 #define STRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0fL << 32) // z10
611 #define STGRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0bL << 32) // z10
612
613 #define STOC_ZOPC (unsigned long)(0xebL << 40 | 0xf3L) // z196
614 #define STOCG_ZOPC (unsigned long)(0xebL << 40 | 0xe3L) // z196
615
616 #define STMG_ZOPC (unsigned long)(235L << 40 | 36L)
617
618 #define STE_ZOPC (unsigned int)(0x70 << 24)
619 #define STEY_ZOPC (unsigned long)(237L << 40 | 102L)
620 #define STD_ZOPC (unsigned int)(0x60 << 24)
621 #define STDY_ZOPC (unsigned long)(237L << 40 | 103L)
622
623 // MOVE: immediate to memory transfer
624 #define MVHHI_ZOPC (unsigned long)(0xe5L << 40 | 0x44L << 32) // z10
625 #define MVHI_ZOPC (unsigned long)(0xe5L << 40 | 0x4cL << 32) // z10
626 #define MVGHI_ZOPC (unsigned long)(0xe5L << 40 | 0x48L << 32) // z10
627
628
629 // ALU operations
630
631 // Load Positive
632 #define LPR_ZOPC (unsigned int)(16 << 8)
633 #define LPGFR_ZOPC (unsigned int)(185 << 24 | 16 << 16)
634 #define LPGR_ZOPC (unsigned int)(185 << 24)
635 #define LPEBR_ZOPC (unsigned int)(179 << 24)
636 #define LPDBR_ZOPC (unsigned int)(179 << 24 | 16 << 16)
857 #define CL_ZOPC (unsigned int)(0x55 << 24)
858 #define CLY_ZOPC (unsigned long)(227L << 40 | 85L)
859 #define CLGF_ZOPC (unsigned long)(227L << 40 | 49L)
860 #define CLG_ZOPC (unsigned long)(227L << 40 | 33L)
861 // RI, unsigned
862 #define TMHH_ZOPC (unsigned int)(167 << 24 | 2 << 16)
863 #define TMHL_ZOPC (unsigned int)(167 << 24 | 3 << 16)
864 #define TMLH_ZOPC (unsigned int)(167 << 24)
865 #define TMLL_ZOPC (unsigned int)(167 << 24 | 1 << 16)
866
867 // RR, BFP
868 #define CEBR_ZOPC (unsigned int)(179 << 24 | 9 << 16)
869 #define CDBR_ZOPC (unsigned int)(179 << 24 | 25 << 16)
870 #define CXBR_ZOPC (unsigned int)(179 << 24 | 73 << 16)
871 // RM, BFP
872 #define CEB_ZOPC (unsigned long)(237L << 40 | 9)
873 #define CDB_ZOPC (unsigned long)(237L << 40 | 25)
874
875 // Shift
876 // arithmetic
877 #define SLA_ZOPC (unsigned int)(139 << 24)
878 #define SLAG_ZOPC (unsigned long)(235L << 40 | 11L)
879 #define SRA_ZOPC (unsigned int)(138 << 24)
880 #define SRAG_ZOPC (unsigned long)(235L << 40 | 10L)
881 // logical
882 #define SLL_ZOPC (unsigned int)(137 << 24)
883 #define SLLG_ZOPC (unsigned long)(235L << 40 | 13L)
884 #define SRL_ZOPC (unsigned int)(136 << 24)
885 #define SRLG_ZOPC (unsigned long)(235L << 40 | 12L)
886
887 // Rotate, then AND/XOR/OR/insert
888 // rotate
889 #define RLL_ZOPC (unsigned long)(0xebL << 40 | 0x1dL) // z10
890 #define RLLG_ZOPC (unsigned long)(0xebL << 40 | 0x1cL) // z10
891 // rotate and {AND|XOR|OR|INS}
892 #define RNSBG_ZOPC (unsigned long)(0xecL << 40 | 0x54L) // z196
893 #define RXSBG_ZOPC (unsigned long)(0xecL << 40 | 0x57L) // z196
894 #define ROSBG_ZOPC (unsigned long)(0xecL << 40 | 0x56L) // z196
895 #define RISBG_ZOPC (unsigned long)(0xecL << 40 | 0x55L) // z196
896
897 // AND
898 // RR, signed
899 #define NR_ZOPC (unsigned int)(20 << 8)
900 #define NGR_ZOPC (unsigned int)(185 << 24 | 128 << 16)
901 // RRF, signed
902 #define NRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00f4 << 16)
903 #define NGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00e4 << 16)
904 // RI, signed
905 #define NIHH_ZOPC (unsigned int)(165 << 24 | 4 << 16)
2245 inline void z_oilf(Register r1, int64_t i2); // or r1 = r1 | i2_imm32 ; or only for bits 32-63
2246
2247 // xor
2248 inline void z_x( Register r1, int64_t d2, Register x2, Register b2);
2249 inline void z_xy( Register r1, int64_t d2, Register x2, Register b2);
2250 inline void z_xg( Register r1, int64_t d2, Register x2, Register b2);
2251 inline void z_x( Register r1, const Address& a);
2252 inline void z_xy( Register r1, const Address& a);
2253 inline void z_xg( Register r1, const Address& a);
2254
2255 inline void z_xr( Register r1, Register r2); // xor r1 = r1 ^ r2 ; int32
2256 inline void z_xgr( Register r1, Register r2); // xor r1 = r1 ^ r2 ; int64
2257 inline void z_xrk( Register r1, Register r2, Register r3); // xor r1 = r2 ^ r3 ; int32
2258 inline void z_xgrk(Register r1, Register r2, Register r3); // xor r1 = r2 ^ r3 ; int64
2259
2260 inline void z_xihf(Register r1, int64_t i2); // xor r1 = r1 ^ i2_imm32 ; or only for bits 0-31
2261 inline void z_xilf(Register r1, int64_t i2); // xor r1 = r1 ^ i2_imm32 ; or only for bits 32-63
2262
2263 // shift
2264 inline void z_sla( Register r1, int64_t d2, Register b2=Z_R0); // shift left r1 = r1 << ((d2+b2)&0x3f) ; int32, only 31 bits shifted, sign preserved!
2265 inline void z_slag(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int64, only 63 bits shifted, sign preserved!
2266 inline void z_sra( Register r1, int64_t d2, Register b2=Z_R0); // shift right r1 = r1 >> ((d2+b2)&0x3f) ; int32, sign extended
2267 inline void z_srag(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int64, sign extended
2268 inline void z_sll( Register r1, int64_t d2, Register b2=Z_R0); // shift left r1 = r1 << ((d2+b2)&0x3f) ; int32, zeros added
2269 inline void z_sllg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int64, zeros added
2270 inline void z_srl( Register r1, int64_t d2, Register b2=Z_R0); // shift right r1 = r1 >> ((d2+b2)&0x3f) ; int32, zero extended
2271 inline void z_srlg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int64, zero extended
2272
2273 // rotate
2274 inline void z_rll( Register r1, Register r3, int64_t d2, Register b2=Z_R0); // rot r1 = r3 << (d2+b2 & 0x3f) ; int32 -- z10
2275 inline void z_rllg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // rot r1 = r3 << (d2+b2 & 0x3f) ; int64 -- z10
2276
2277 // rotate the AND/XOR/OR/insert
2278 inline void z_rnsbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool test_only = false); // rotate then AND selected bits -- z196
2279 inline void z_rxsbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool test_only = false); // rotate then XOR selected bits -- z196
2280 inline void z_rosbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool test_only = false); // rotate then OR selected bits -- z196
2281 inline void z_risbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool zero_rest = false); // rotate then INS selected bits -- z196
2282
2283
2284 // memory-immediate instructions (8-bit immediate)
2285 // ===============================================
2286
2287 inline void z_cli( int64_t d1, Register b1, int64_t i2); // compare *(d1_imm12+b1) ^= i2_imm8 ; int8
2288 inline void z_mvi( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) = i2_imm8 ; int8
2289 inline void z_tm( int64_t d1, Register b1, int64_t i2); // test *(d1_imm12+b1) against mask i2_imm8 ; int8
2290 inline void z_ni( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) &= i2_imm8 ; int8
3018 inline void z_brxh(Register r1, Register r3, address a);
3019 inline void z_brxh(Register r1, Register r3, Label& L);
3020
3021 inline void z_brxle(Register r1, Register r3, address a);
3022 inline void z_brxle(Register r1, Register r3, Label& L);
3023
3024 inline void z_brxhg(Register r1, Register r3, address a);
3025 inline void z_brxhg(Register r1, Register r3, Label& L);
3026
3027 inline void z_brxlg(Register r1, Register r3, address a);
3028 inline void z_brxlg(Register r1, Register r3, Label& L);
3029
3030 // Ppopulation count intrinsics.
3031 inline void z_flogr(Register r1, Register r2); // find leftmost one
3032 inline void z_popcnt(Register r1, Register r2); // population count
3033 inline void z_ahhhr(Register r1, Register r2, Register r3); // ADD halfword high high
3034 inline void z_ahhlr(Register r1, Register r2, Register r3); // ADD halfword high low
3035
3036 inline void z_tam();
3037 inline void z_stckf(int64_t d2, Register b2);
3038 inline void z_stmg(Register r1, Register r3, int64_t d2, Register b2);
3039 inline void z_lmg(Register r1, Register r3, int64_t d2, Register b2);
3040
3041 inline void z_cs( Register r1, Register r3, int64_t d2, Register b2);
3042 inline void z_csy(Register r1, Register r3, int64_t d2, Register b2);
3043 inline void z_csg(Register r1, Register r3, int64_t d2, Register b2);
3044 inline void z_cs( Register r1, Register r3, const Address& a);
3045 inline void z_csy(Register r1, Register r3, const Address& a);
3046 inline void z_csg(Register r1, Register r3, const Address& a);
3047
3048 inline void z_cvd(Register r1, int64_t d2, Register x2, Register b2);
3049 inline void z_cvdg(Register r1, int64_t d2, Register x2, Register b2);
3050 inline void z_cvd(Register r1, int64_t d2, Register b2);
3051 inline void z_cvdg(Register r1, int64_t d2, Register b2);
3052
3053 // Instruction queries:
3054 // instruction properties and recognize emitted instructions
3055 // ===========================================================
3056
3057 static int nop_size() { return 2; }
3058
|
565
566 #define LRVH_ZOPC (unsigned long)(0xe3L << 40 | 0x1fL)
567 #define LRV_ZOPC (unsigned long)(0xe3L << 40 | 0x1eL)
568 #define LRVG_ZOPC (unsigned long)(0xe3L << 40 | 0x0fL)
569
570
571 // LOAD relative: memory to register transfer
572 #define LHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x05L << 32) // z10
573 #define LRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0dL << 32) // z10
574 #define LGHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x04L << 32) // z10
575 #define LGFRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0cL << 32) // z10
576 #define LGRL_ZOPC (unsigned long)(0xc4L << 40 | 0x08L << 32) // z10
577
578 #define LLHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x02L << 32) // z10
579 #define LLGHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x06L << 32) // z10
580 #define LLGFRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0eL << 32) // z10
581
582 #define LOC_ZOPC (unsigned long)(0xebL << 40 | 0xf2L) // z196
583 #define LOCG_ZOPC (unsigned long)(0xebL << 40 | 0xe2L) // z196
584
585
586 // LOAD multiple registers at once
587 #define LM_ZOPC (unsigned int)(0x98 << 24)
588 #define LMY_ZOPC (unsigned long)(0xebL << 40 | 0x98L)
589 #define LMG_ZOPC (unsigned long)(0xebL << 40 | 0x04L)
590
591 #define LE_ZOPC (unsigned int)(0x78 << 24)
592 #define LEY_ZOPC (unsigned long)(237L << 40 | 100L)
593 #define LDEB_ZOPC (unsigned long)(237L << 40 | 4)
594 #define LD_ZOPC (unsigned int)(0x68 << 24)
595 #define LDY_ZOPC (unsigned long)(237L << 40 | 101L)
596 #define LXEB_ZOPC (unsigned long)(237L << 40 | 6)
597 #define LXDB_ZOPC (unsigned long)(237L << 40 | 5)
598
599 // STORE: register to memory transfer
600 #define STC_ZOPC (unsigned int)(0x42 << 24)
601 #define STCY_ZOPC (unsigned long)(227L << 40 | 114L)
602 #define STH_ZOPC (unsigned int)(64 << 24)
603 #define STHY_ZOPC (unsigned long)(227L << 40 | 112L)
604 #define ST_ZOPC (unsigned int)(80 << 24)
605 #define STY_ZOPC (unsigned long)(227L << 40 | 80L)
606 #define STG_ZOPC (unsigned long)(227L << 40 | 36L)
607
608 #define STCM_ZOPC (unsigned long)(0xbeL << 24)
609 #define STCMY_ZOPC (unsigned long)(0xebL << 40 | 0x2dL)
610 #define STCMH_ZOPC (unsigned long)(0xebL << 40 | 0x2cL)
611
612 // STORE relative: memory to register transfer
613 #define STHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x07L << 32) // z10
614 #define STRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0fL << 32) // z10
615 #define STGRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0bL << 32) // z10
616
617 #define STOC_ZOPC (unsigned long)(0xebL << 40 | 0xf3L) // z196
618 #define STOCG_ZOPC (unsigned long)(0xebL << 40 | 0xe3L) // z196
619
620 // STORE multiple registers at once
621 #define STM_ZOPC (unsigned int)(0x90 << 24)
622 #define STMY_ZOPC (unsigned long)(0xebL << 40 | 0x90L)
623 #define STMG_ZOPC (unsigned long)(0xebL << 40 | 0x24L)
624
625 #define STE_ZOPC (unsigned int)(0x70 << 24)
626 #define STEY_ZOPC (unsigned long)(237L << 40 | 102L)
627 #define STD_ZOPC (unsigned int)(0x60 << 24)
628 #define STDY_ZOPC (unsigned long)(237L << 40 | 103L)
629
630 // MOVE: immediate to memory transfer
631 #define MVHHI_ZOPC (unsigned long)(0xe5L << 40 | 0x44L << 32) // z10
632 #define MVHI_ZOPC (unsigned long)(0xe5L << 40 | 0x4cL << 32) // z10
633 #define MVGHI_ZOPC (unsigned long)(0xe5L << 40 | 0x48L << 32) // z10
634
635
636 // ALU operations
637
638 // Load Positive
639 #define LPR_ZOPC (unsigned int)(16 << 8)
640 #define LPGFR_ZOPC (unsigned int)(185 << 24 | 16 << 16)
641 #define LPGR_ZOPC (unsigned int)(185 << 24)
642 #define LPEBR_ZOPC (unsigned int)(179 << 24)
643 #define LPDBR_ZOPC (unsigned int)(179 << 24 | 16 << 16)
864 #define CL_ZOPC (unsigned int)(0x55 << 24)
865 #define CLY_ZOPC (unsigned long)(227L << 40 | 85L)
866 #define CLGF_ZOPC (unsigned long)(227L << 40 | 49L)
867 #define CLG_ZOPC (unsigned long)(227L << 40 | 33L)
868 // RI, unsigned
869 #define TMHH_ZOPC (unsigned int)(167 << 24 | 2 << 16)
870 #define TMHL_ZOPC (unsigned int)(167 << 24 | 3 << 16)
871 #define TMLH_ZOPC (unsigned int)(167 << 24)
872 #define TMLL_ZOPC (unsigned int)(167 << 24 | 1 << 16)
873
874 // RR, BFP
875 #define CEBR_ZOPC (unsigned int)(179 << 24 | 9 << 16)
876 #define CDBR_ZOPC (unsigned int)(179 << 24 | 25 << 16)
877 #define CXBR_ZOPC (unsigned int)(179 << 24 | 73 << 16)
878 // RM, BFP
879 #define CEB_ZOPC (unsigned long)(237L << 40 | 9)
880 #define CDB_ZOPC (unsigned long)(237L << 40 | 25)
881
882 // Shift
883 // arithmetic
884 #define SLA_ZOPC (unsigned int)(0x8b << 24)
885 #define SLAK_ZOPC (unsigned long)(0xebL << 40 | 0xddL)
886 #define SLAG_ZOPC (unsigned long)(0xebL << 40 | 0x0bL)
887 #define SRA_ZOPC (unsigned int)(0x8a << 24)
888 #define SRAK_ZOPC (unsigned long)(0xebL << 40 | 0xdcL)
889 #define SRAG_ZOPC (unsigned long)(0xebL << 40 | 0x0aL)
890 // logical
891 #define SLL_ZOPC (unsigned int)(0x89 << 24)
892 #define SLLK_ZOPC (unsigned long)(0xebL << 40 | 0xdfL)
893 #define SLLG_ZOPC (unsigned long)(0xebL << 40 | 0x0dL)
894 #define SRL_ZOPC (unsigned int)(0x88 << 24)
895 #define SRLK_ZOPC (unsigned long)(0xebL << 40 | 0xdeL)
896 #define SRLG_ZOPC (unsigned long)(0xebL << 40 | 0x0cL)
897
898 // Rotate, then AND/XOR/OR/insert
899 // rotate
900 #define RLL_ZOPC (unsigned long)(0xebL << 40 | 0x1dL) // z10
901 #define RLLG_ZOPC (unsigned long)(0xebL << 40 | 0x1cL) // z10
902 // rotate and {AND|XOR|OR|INS}
903 #define RNSBG_ZOPC (unsigned long)(0xecL << 40 | 0x54L) // z196
904 #define RXSBG_ZOPC (unsigned long)(0xecL << 40 | 0x57L) // z196
905 #define ROSBG_ZOPC (unsigned long)(0xecL << 40 | 0x56L) // z196
906 #define RISBG_ZOPC (unsigned long)(0xecL << 40 | 0x55L) // z196
907
908 // AND
909 // RR, signed
910 #define NR_ZOPC (unsigned int)(20 << 8)
911 #define NGR_ZOPC (unsigned int)(185 << 24 | 128 << 16)
912 // RRF, signed
913 #define NRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00f4 << 16)
914 #define NGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00e4 << 16)
915 // RI, signed
916 #define NIHH_ZOPC (unsigned int)(165 << 24 | 4 << 16)
2256 inline void z_oilf(Register r1, int64_t i2); // or r1 = r1 | i2_imm32 ; or only for bits 32-63
2257
2258 // xor
2259 inline void z_x( Register r1, int64_t d2, Register x2, Register b2);
2260 inline void z_xy( Register r1, int64_t d2, Register x2, Register b2);
2261 inline void z_xg( Register r1, int64_t d2, Register x2, Register b2);
2262 inline void z_x( Register r1, const Address& a);
2263 inline void z_xy( Register r1, const Address& a);
2264 inline void z_xg( Register r1, const Address& a);
2265
2266 inline void z_xr( Register r1, Register r2); // xor r1 = r1 ^ r2 ; int32
2267 inline void z_xgr( Register r1, Register r2); // xor r1 = r1 ^ r2 ; int64
2268 inline void z_xrk( Register r1, Register r2, Register r3); // xor r1 = r2 ^ r3 ; int32
2269 inline void z_xgrk(Register r1, Register r2, Register r3); // xor r1 = r2 ^ r3 ; int64
2270
2271 inline void z_xihf(Register r1, int64_t i2); // xor r1 = r1 ^ i2_imm32 ; or only for bits 0-31
2272 inline void z_xilf(Register r1, int64_t i2); // xor r1 = r1 ^ i2_imm32 ; or only for bits 32-63
2273
2274 // shift
2275 inline void z_sla( Register r1, int64_t d2, Register b2=Z_R0); // shift left r1 = r1 << ((d2+b2)&0x3f) ; int32, only 31 bits shifted, sign preserved!
2276 inline void z_slak(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int32, only 31 bits shifted, sign preserved!
2277 inline void z_slag(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int64, only 63 bits shifted, sign preserved!
2278 inline void z_sra( Register r1, int64_t d2, Register b2=Z_R0); // shift right r1 = r1 >> ((d2+b2)&0x3f) ; int32, sign extended
2279 inline void z_srak(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int32, sign extended
2280 inline void z_srag(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int64, sign extended
2281 inline void z_sll( Register r1, int64_t d2, Register b2=Z_R0); // shift left r1 = r1 << ((d2+b2)&0x3f) ; int32, zeros added
2282 inline void z_sllk(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int32, zeros added
2283 inline void z_sllg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int64, zeros added
2284 inline void z_srl( Register r1, int64_t d2, Register b2=Z_R0); // shift right r1 = r1 >> ((d2+b2)&0x3f) ; int32, zero extended
2285 inline void z_srlk(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int32, zero extended
2286 inline void z_srlg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int64, zero extended
2287
2288 // rotate
2289 inline void z_rll( Register r1, Register r3, int64_t d2, Register b2=Z_R0); // rot r1 = r3 << (d2+b2 & 0x3f) ; int32 -- z10
2290 inline void z_rllg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // rot r1 = r3 << (d2+b2 & 0x3f) ; int64 -- z10
2291
2292 // rotate the AND/XOR/OR/insert
2293 inline void z_rnsbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool test_only = false); // rotate then AND selected bits -- z196
2294 inline void z_rxsbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool test_only = false); // rotate then XOR selected bits -- z196
2295 inline void z_rosbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool test_only = false); // rotate then OR selected bits -- z196
2296 inline void z_risbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool zero_rest = false); // rotate then INS selected bits -- z196
2297
2298
2299 // memory-immediate instructions (8-bit immediate)
2300 // ===============================================
2301
2302 inline void z_cli( int64_t d1, Register b1, int64_t i2); // compare *(d1_imm12+b1) ^= i2_imm8 ; int8
2303 inline void z_mvi( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) = i2_imm8 ; int8
2304 inline void z_tm( int64_t d1, Register b1, int64_t i2); // test *(d1_imm12+b1) against mask i2_imm8 ; int8
2305 inline void z_ni( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) &= i2_imm8 ; int8
3033 inline void z_brxh(Register r1, Register r3, address a);
3034 inline void z_brxh(Register r1, Register r3, Label& L);
3035
3036 inline void z_brxle(Register r1, Register r3, address a);
3037 inline void z_brxle(Register r1, Register r3, Label& L);
3038
3039 inline void z_brxhg(Register r1, Register r3, address a);
3040 inline void z_brxhg(Register r1, Register r3, Label& L);
3041
3042 inline void z_brxlg(Register r1, Register r3, address a);
3043 inline void z_brxlg(Register r1, Register r3, Label& L);
3044
3045 // Ppopulation count intrinsics.
3046 inline void z_flogr(Register r1, Register r2); // find leftmost one
3047 inline void z_popcnt(Register r1, Register r2); // population count
3048 inline void z_ahhhr(Register r1, Register r2, Register r3); // ADD halfword high high
3049 inline void z_ahhlr(Register r1, Register r2, Register r3); // ADD halfword high low
3050
3051 inline void z_tam();
3052 inline void z_stckf(int64_t d2, Register b2);
3053 inline void z_stm( Register r1, Register r3, int64_t d2, Register b2);
3054 inline void z_stmy(Register r1, Register r3, int64_t d2, Register b2);
3055 inline void z_stmg(Register r1, Register r3, int64_t d2, Register b2);
3056 inline void z_lm( Register r1, Register r3, int64_t d2, Register b2);
3057 inline void z_lmy(Register r1, Register r3, int64_t d2, Register b2);
3058 inline void z_lmg(Register r1, Register r3, int64_t d2, Register b2);
3059
3060 inline void z_cs( Register r1, Register r3, int64_t d2, Register b2);
3061 inline void z_csy(Register r1, Register r3, int64_t d2, Register b2);
3062 inline void z_csg(Register r1, Register r3, int64_t d2, Register b2);
3063 inline void z_cs( Register r1, Register r3, const Address& a);
3064 inline void z_csy(Register r1, Register r3, const Address& a);
3065 inline void z_csg(Register r1, Register r3, const Address& a);
3066
3067 inline void z_cvd(Register r1, int64_t d2, Register x2, Register b2);
3068 inline void z_cvdg(Register r1, int64_t d2, Register x2, Register b2);
3069 inline void z_cvd(Register r1, int64_t d2, Register b2);
3070 inline void z_cvdg(Register r1, int64_t d2, Register b2);
3071
3072 // Instruction queries:
3073 // instruction properties and recognize emitted instructions
3074 // ===========================================================
3075
3076 static int nop_size() { return 2; }
3077
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