1 // 2 // Copyright (c) 2017, Oracle and/or its affiliates. All rights reserved. 3 // Copyright (c) 2017, SAP SE. All rights reserved. 4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 // 6 // This code is free software; you can redistribute it and/or modify it 7 // under the terms of the GNU General Public License version 2 only, as 8 // published by the Free Software Foundation. 9 // 10 // This code is distributed in the hope that it will be useful, but WITHOUT 11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 // version 2 for more details (a copy is included in the LICENSE file that 14 // accompanied this code). 15 // 16 // You should have received a copy of the GNU General Public License version 17 // 2 along with this work; if not, write to the Free Software Foundation, 18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 // 20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 // or visit www.oracle.com if you need additional information or have any 22 // questions. 23 // 24 25 // z/Architecture Architecture Description File 26 27 // Major contributions by AS, JL, LS. 28 29 // 30 // Following information is derived from private mail communication 31 // (Oct. 2011). 32 // 33 // General branch target alignment considerations 34 // 35 // z/Architecture does not imply a general branch target alignment requirement. 36 // There are side effects and side considerations, though, which may 37 // provide some performance benefit. These are: 38 // - Align branch target on octoword (32-byte) boundary 39 // On more recent models (from z9 on), I-fetch is done on a Octoword 40 // (32 bytes at a time) basis. To avoid I-fetching unnecessary 41 // instructions, branch targets should be 32-byte aligend. If this 42 // exact alingment cannot be achieved, having the branch target in 43 // the first doubleword still provides some benefit. 44 // - Avoid branch targets at the end of cache lines (> 64 bytes distance). 45 // Sequential instruction prefetching after the branch target starts 46 // immediately after having fetched the octoword containing the 47 // branch target. When I-fetching crosses a cache line, there may be 48 // a small stall. The worst case: the branch target (at the end of 49 // a cache line) is a L1 I-cache miss and the next line as well. 50 // Then, the entire target line must be filled first (to contine at the 51 // branch target). Only then can the next sequential line be filled. 52 // - Avoid multiple poorly predicted branches in a row. 53 // 54 55 //----------REGISTER DEFINITION BLOCK------------------------------------------ 56 // This information is used by the matcher and the register allocator to 57 // describe individual registers and classes of registers within the target 58 // architecture. 59 60 register %{ 61 62 //----------Architecture Description Register Definitions---------------------- 63 // General Registers 64 // "reg_def" name (register save type, C convention save type, 65 // ideal register type, encoding); 66 // 67 // Register Save Types: 68 // 69 // NS = No-Save: The register allocator assumes that these registers 70 // can be used without saving upon entry to the method, & 71 // that they do not need to be saved at call sites. 72 // 73 // SOC = Save-On-Call: The register allocator assumes that these registers 74 // can be used without saving upon entry to the method, 75 // but that they must be saved at call sites. 76 // 77 // SOE = Save-On-Entry: The register allocator assumes that these registers 78 // must be saved before using them upon entry to the 79 // method, but they do not need to be saved at call sites. 80 // 81 // AS = Always-Save: The register allocator assumes that these registers 82 // must be saved before using them upon entry to the 83 // method, & that they must be saved at call sites. 84 // 85 // Ideal Register Type is used to determine how to save & restore a 86 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 87 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 88 // 89 // The encoding number is the actual bit-pattern placed into the opcodes. 90 91 // z/Architecture register definitions, based on the z/Architecture Principles 92 // of Operation, 5th Edition, September 2005, and z/Linux Elf ABI Supplement, 93 // 5th Edition, March 2001. 94 // 95 // For each 64-bit register we must define two registers: the register 96 // itself, e.g. Z_R3, and a corresponding virtual other (32-bit-)'half', 97 // e.g. Z_R3_H, which is needed by the allocator, but is not used 98 // for stores, loads, etc. 99 100 // Integer/Long Registers 101 // ---------------------------- 102 103 // z/Architecture has 16 64-bit integer registers. 104 105 // types: v = volatile, nv = non-volatile, s = system 106 reg_def Z_R0 (SOC, SOC, Op_RegI, 0, Z_R0->as_VMReg()); // v scratch1 107 reg_def Z_R0_H (SOC, SOC, Op_RegI, 99, Z_R0->as_VMReg()->next()); 108 reg_def Z_R1 (SOC, SOC, Op_RegI, 1, Z_R1->as_VMReg()); // v scratch2 109 reg_def Z_R1_H (SOC, SOC, Op_RegI, 99, Z_R1->as_VMReg()->next()); 110 reg_def Z_R2 (SOC, SOC, Op_RegI, 2, Z_R2->as_VMReg()); // v iarg1 & iret 111 reg_def Z_R2_H (SOC, SOC, Op_RegI, 99, Z_R2->as_VMReg()->next()); 112 reg_def Z_R3 (SOC, SOC, Op_RegI, 3, Z_R3->as_VMReg()); // v iarg2 113 reg_def Z_R3_H (SOC, SOC, Op_RegI, 99, Z_R3->as_VMReg()->next()); 114 reg_def Z_R4 (SOC, SOC, Op_RegI, 4, Z_R4->as_VMReg()); // v iarg3 115 reg_def Z_R4_H (SOC, SOC, Op_RegI, 99, Z_R4->as_VMReg()->next()); 116 reg_def Z_R5 (SOC, SOC, Op_RegI, 5, Z_R5->as_VMReg()); // v iarg4 117 reg_def Z_R5_H (SOC, SOC, Op_RegI, 99, Z_R5->as_VMReg()->next()); 118 reg_def Z_R6 (SOC, SOE, Op_RegI, 6, Z_R6->as_VMReg()); // v iarg5 119 reg_def Z_R6_H (SOC, SOE, Op_RegI, 99, Z_R6->as_VMReg()->next()); 120 reg_def Z_R7 (SOC, SOE, Op_RegI, 7, Z_R7->as_VMReg()); 121 reg_def Z_R7_H (SOC, SOE, Op_RegI, 99, Z_R7->as_VMReg()->next()); 122 reg_def Z_R8 (SOC, SOE, Op_RegI, 8, Z_R8->as_VMReg()); 123 reg_def Z_R8_H (SOC, SOE, Op_RegI, 99, Z_R8->as_VMReg()->next()); 124 reg_def Z_R9 (SOC, SOE, Op_RegI, 9, Z_R9->as_VMReg()); 125 reg_def Z_R9_H (SOC, SOE, Op_RegI, 99, Z_R9->as_VMReg()->next()); 126 reg_def Z_R10 (SOC, SOE, Op_RegI, 10, Z_R10->as_VMReg()); 127 reg_def Z_R10_H(SOC, SOE, Op_RegI, 99, Z_R10->as_VMReg()->next()); 128 reg_def Z_R11 (SOC, SOE, Op_RegI, 11, Z_R11->as_VMReg()); 129 reg_def Z_R11_H(SOC, SOE, Op_RegI, 99, Z_R11->as_VMReg()->next()); 130 reg_def Z_R12 (SOC, SOE, Op_RegI, 12, Z_R12->as_VMReg()); 131 reg_def Z_R12_H(SOC, SOE, Op_RegI, 99, Z_R12->as_VMReg()->next()); 132 reg_def Z_R13 (SOC, SOE, Op_RegI, 13, Z_R13->as_VMReg()); 133 reg_def Z_R13_H(SOC, SOE, Op_RegI, 99, Z_R13->as_VMReg()->next()); 134 reg_def Z_R14 (NS, NS, Op_RegI, 14, Z_R14->as_VMReg()); // s return_pc 135 reg_def Z_R14_H(NS, NS, Op_RegI, 99, Z_R14->as_VMReg()->next()); 136 reg_def Z_R15 (NS, NS, Op_RegI, 15, Z_R15->as_VMReg()); // s SP 137 reg_def Z_R15_H(NS, NS, Op_RegI, 99, Z_R15->as_VMReg()->next()); 138 139 // Float/Double Registers 140 141 // The rules of ADL require that double registers be defined in pairs. 142 // Each pair must be two 32-bit values, but not necessarily a pair of 143 // single float registers. In each pair, ADLC-assigned register numbers 144 // must be adjacent, with the lower number even. Finally, when the 145 // CPU stores such a register pair to memory, the word associated with 146 // the lower ADLC-assigned number must be stored to the lower address. 147 148 // z/Architecture has 16 64-bit floating-point registers. Each can store a single 149 // or double precision floating-point value. 150 151 // types: v = volatile, nv = non-volatile, s = system 152 reg_def Z_F0 (SOC, SOC, Op_RegF, 0, Z_F0->as_VMReg()); // v farg1 & fret 153 reg_def Z_F0_H (SOC, SOC, Op_RegF, 99, Z_F0->as_VMReg()->next()); 154 reg_def Z_F1 (SOC, SOC, Op_RegF, 1, Z_F1->as_VMReg()); 155 reg_def Z_F1_H (SOC, SOC, Op_RegF, 99, Z_F1->as_VMReg()->next()); 156 reg_def Z_F2 (SOC, SOC, Op_RegF, 2, Z_F2->as_VMReg()); // v farg2 157 reg_def Z_F2_H (SOC, SOC, Op_RegF, 99, Z_F2->as_VMReg()->next()); 158 reg_def Z_F3 (SOC, SOC, Op_RegF, 3, Z_F3->as_VMReg()); 159 reg_def Z_F3_H (SOC, SOC, Op_RegF, 99, Z_F3->as_VMReg()->next()); 160 reg_def Z_F4 (SOC, SOC, Op_RegF, 4, Z_F4->as_VMReg()); // v farg3 161 reg_def Z_F4_H (SOC, SOC, Op_RegF, 99, Z_F4->as_VMReg()->next()); 162 reg_def Z_F5 (SOC, SOC, Op_RegF, 5, Z_F5->as_VMReg()); 163 reg_def Z_F5_H (SOC, SOC, Op_RegF, 99, Z_F5->as_VMReg()->next()); 164 reg_def Z_F6 (SOC, SOC, Op_RegF, 6, Z_F6->as_VMReg()); 165 reg_def Z_F6_H (SOC, SOC, Op_RegF, 99, Z_F6->as_VMReg()->next()); 166 reg_def Z_F7 (SOC, SOC, Op_RegF, 7, Z_F7->as_VMReg()); 167 reg_def Z_F7_H (SOC, SOC, Op_RegF, 99, Z_F7->as_VMReg()->next()); 168 reg_def Z_F8 (SOC, SOE, Op_RegF, 8, Z_F8->as_VMReg()); 169 reg_def Z_F8_H (SOC, SOE, Op_RegF, 99, Z_F8->as_VMReg()->next()); 170 reg_def Z_F9 (SOC, SOE, Op_RegF, 9, Z_F9->as_VMReg()); 171 reg_def Z_F9_H (SOC, SOE, Op_RegF, 99, Z_F9->as_VMReg()->next()); 172 reg_def Z_F10 (SOC, SOE, Op_RegF, 10, Z_F10->as_VMReg()); 173 reg_def Z_F10_H(SOC, SOE, Op_RegF, 99, Z_F10->as_VMReg()->next()); 174 reg_def Z_F11 (SOC, SOE, Op_RegF, 11, Z_F11->as_VMReg()); 175 reg_def Z_F11_H(SOC, SOE, Op_RegF, 99, Z_F11->as_VMReg()->next()); 176 reg_def Z_F12 (SOC, SOE, Op_RegF, 12, Z_F12->as_VMReg()); 177 reg_def Z_F12_H(SOC, SOE, Op_RegF, 99, Z_F12->as_VMReg()->next()); 178 reg_def Z_F13 (SOC, SOE, Op_RegF, 13, Z_F13->as_VMReg()); 179 reg_def Z_F13_H(SOC, SOE, Op_RegF, 99, Z_F13->as_VMReg()->next()); 180 reg_def Z_F14 (SOC, SOE, Op_RegF, 14, Z_F14->as_VMReg()); 181 reg_def Z_F14_H(SOC, SOE, Op_RegF, 99, Z_F14->as_VMReg()->next()); 182 reg_def Z_F15 (SOC, SOE, Op_RegF, 15, Z_F15->as_VMReg()); 183 reg_def Z_F15_H(SOC, SOE, Op_RegF, 99, Z_F15->as_VMReg()->next()); 184 185 186 // Special Registers 187 188 // Condition Codes Flag Registers 189 190 // z/Architecture has the PSW (program status word) that contains 191 // (among other information) the condition code. We treat this 192 // part of the PSW as a condition register CR. It consists of 4 193 // bits. Floating point instructions influence the same condition register CR. 194 195 reg_def Z_CR(SOC, SOC, Op_RegFlags, 0, Z_CR->as_VMReg()); // volatile 196 197 198 // Specify priority of register selection within phases of register 199 // allocation. Highest priority is first. A useful heuristic is to 200 // give registers a low priority when they are required by machine 201 // instructions, and choose no-save registers before save-on-call, and 202 // save-on-call before save-on-entry. Registers which participate in 203 // fix calling sequences should come last. Registers which are used 204 // as pairs must fall on an even boundary. 205 206 // It's worth about 1% on SPEC geomean to get this right. 207 208 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration 209 // in adGlobals_s390.hpp which defines the <register>_num values, e.g. 210 // Z_R3_num. Therefore, Z_R3_num may not be (and in reality is not) 211 // the same as Z_R3->encoding()! Furthermore, we cannot make any 212 // assumptions on ordering, e.g. Z_R3_num may be less than Z_R2_num. 213 // Additionally, the function 214 // static enum RC rc_class(OptoReg::Name reg) 215 // maps a given <register>_num value to its chunk type (except for flags) 216 // and its current implementation relies on chunk0 and chunk1 having a 217 // size of 64 each. 218 219 alloc_class chunk0( 220 // chunk0 contains *all* 32 integer registers halves. 221 222 // potential SOE regs 223 Z_R13,Z_R13_H, 224 Z_R12,Z_R12_H, 225 Z_R11,Z_R11_H, 226 Z_R10,Z_R10_H, 227 228 Z_R9,Z_R9_H, 229 Z_R8,Z_R8_H, 230 Z_R7,Z_R7_H, 231 232 Z_R1,Z_R1_H, 233 Z_R0,Z_R0_H, 234 235 // argument registers 236 Z_R6,Z_R6_H, 237 Z_R5,Z_R5_H, 238 Z_R4,Z_R4_H, 239 Z_R3,Z_R3_H, 240 Z_R2,Z_R2_H, 241 242 // special registers 243 Z_R14,Z_R14_H, 244 Z_R15,Z_R15_H 245 ); 246 247 alloc_class chunk1( 248 // Chunk1 contains *all* 64 floating-point registers halves. 249 250 Z_F15,Z_F15_H, 251 Z_F14,Z_F14_H, 252 Z_F13,Z_F13_H, 253 Z_F12,Z_F12_H, 254 Z_F11,Z_F11_H, 255 Z_F10,Z_F10_H, 256 Z_F9,Z_F9_H, 257 Z_F8,Z_F8_H, 258 // scratch register 259 Z_F7,Z_F7_H, 260 Z_F5,Z_F5_H, 261 Z_F3,Z_F3_H, 262 Z_F1,Z_F1_H, 263 // argument registers 264 Z_F6,Z_F6_H, 265 Z_F4,Z_F4_H, 266 Z_F2,Z_F2_H, 267 Z_F0,Z_F0_H 268 ); 269 270 alloc_class chunk2( 271 Z_CR 272 ); 273 274 275 //-------Architecture Description Register Classes----------------------- 276 277 // Several register classes are automatically defined based upon 278 // information in this architecture description. 279 280 // 1) reg_class inline_cache_reg (as defined in frame section) 281 // 2) reg_class compiler_method_oop_reg (as defined in frame section) 282 // 2) reg_class interpreter_method_oop_reg (as defined in frame section) 283 // 3) reg_class stack_slots(/* one chunk of stack-based "registers" */) 284 285 // Integer Register Classes 286 reg_class z_int_reg( 287 /*Z_R0*/ // R0 288 /*Z_R1*/ 289 Z_R2, 290 Z_R3, 291 Z_R4, 292 Z_R5, 293 Z_R6, 294 Z_R7, 295 /*Z_R8,*/ // Z_thread 296 Z_R9, 297 Z_R10, 298 Z_R11, 299 Z_R12, 300 Z_R13 301 /*Z_R14*/ // return_pc 302 /*Z_R15*/ // SP 303 ); 304 305 reg_class z_no_odd_int_reg( 306 /*Z_R0*/ // R0 307 /*Z_R1*/ 308 Z_R2, 309 Z_R3, 310 Z_R4, 311 /*Z_R5,*/ // odd part of fix register pair 312 Z_R6, 313 Z_R7, 314 /*Z_R8,*/ // Z_thread 315 Z_R9, 316 Z_R10, 317 Z_R11, 318 Z_R12, 319 Z_R13 320 /*Z_R14*/ // return_pc 321 /*Z_R15*/ // SP 322 ); 323 324 reg_class z_no_arg_int_reg( 325 /*Z_R0*/ // R0 326 /*Z_R1*/ // scratch 327 /*Z_R2*/ 328 /*Z_R3*/ 329 /*Z_R4*/ 330 /*Z_R5*/ 331 /*Z_R6*/ 332 Z_R7, 333 /*Z_R8*/ // Z_thread 334 Z_R9, 335 Z_R10, 336 Z_R11, 337 Z_R12, 338 Z_R13 339 /*Z_R14*/ // return_pc 340 /*Z_R15*/ // SP 341 ); 342 343 reg_class z_rarg1_int_reg(Z_R2); 344 reg_class z_rarg2_int_reg(Z_R3); 345 reg_class z_rarg3_int_reg(Z_R4); 346 reg_class z_rarg4_int_reg(Z_R5); 347 reg_class z_rarg5_int_reg(Z_R6); 348 349 // Pointer Register Classes 350 351 // 64-bit build means 64-bit pointers means hi/lo pairs. 352 353 reg_class z_rarg5_ptrN_reg(Z_R6); 354 355 reg_class z_rarg1_ptr_reg(Z_R2_H,Z_R2); 356 reg_class z_rarg2_ptr_reg(Z_R3_H,Z_R3); 357 reg_class z_rarg3_ptr_reg(Z_R4_H,Z_R4); 358 reg_class z_rarg4_ptr_reg(Z_R5_H,Z_R5); 359 reg_class z_rarg5_ptr_reg(Z_R6_H,Z_R6); 360 reg_class z_thread_ptr_reg(Z_R8_H,Z_R8); 361 362 reg_class z_ptr_reg( 363 /*Z_R0_H,Z_R0*/ // R0 364 /*Z_R1_H,Z_R1*/ 365 Z_R2_H,Z_R2, 366 Z_R3_H,Z_R3, 367 Z_R4_H,Z_R4, 368 Z_R5_H,Z_R5, 369 Z_R6_H,Z_R6, 370 Z_R7_H,Z_R7, 371 /*Z_R8_H,Z_R8,*/ // Z_thread 372 Z_R9_H,Z_R9, 373 Z_R10_H,Z_R10, 374 Z_R11_H,Z_R11, 375 Z_R12_H,Z_R12, 376 Z_R13_H,Z_R13 377 /*Z_R14_H,Z_R14*/ // return_pc 378 /*Z_R15_H,Z_R15*/ // SP 379 ); 380 381 reg_class z_lock_ptr_reg( 382 /*Z_R0_H,Z_R0*/ // R0 383 /*Z_R1_H,Z_R1*/ 384 Z_R2_H,Z_R2, 385 Z_R3_H,Z_R3, 386 Z_R4_H,Z_R4, 387 /*Z_R5_H,Z_R5,*/ 388 /*Z_R6_H,Z_R6,*/ 389 Z_R7_H,Z_R7, 390 /*Z_R8_H,Z_R8,*/ // Z_thread 391 Z_R9_H,Z_R9, 392 Z_R10_H,Z_R10, 393 Z_R11_H,Z_R11, 394 Z_R12_H,Z_R12, 395 Z_R13_H,Z_R13 396 /*Z_R14_H,Z_R14*/ // return_pc 397 /*Z_R15_H,Z_R15*/ // SP 398 ); 399 400 reg_class z_no_arg_ptr_reg( 401 /*Z_R0_H,Z_R0*/ // R0 402 /*Z_R1_H,Z_R1*/ // scratch 403 /*Z_R2_H,Z_R2*/ 404 /*Z_R3_H,Z_R3*/ 405 /*Z_R4_H,Z_R4*/ 406 /*Z_R5_H,Z_R5*/ 407 /*Z_R6_H,Z_R6*/ 408 Z_R7_H, Z_R7, 409 /*Z_R8_H,Z_R8*/ // Z_thread 410 Z_R9_H,Z_R9, 411 Z_R10_H,Z_R10, 412 Z_R11_H,Z_R11, 413 Z_R12_H,Z_R12, 414 Z_R13_H,Z_R13 415 /*Z_R14_H,Z_R14*/ // return_pc 416 /*Z_R15_H,Z_R15*/ // SP 417 ); 418 419 // Special class for storeP instructions, which can store SP or RPC to 420 // TLS. (Note: Do not generalize this to "any_reg". If you add 421 // another register, such as FP, to this mask, the allocator may try 422 // to put a temp in it.) 423 // Register class for memory access base registers, 424 // This class is a superset of z_ptr_reg including Z_thread. 425 reg_class z_memory_ptr_reg( 426 /*Z_R0_H,Z_R0*/ // R0 427 /*Z_R1_H,Z_R1*/ 428 Z_R2_H,Z_R2, 429 Z_R3_H,Z_R3, 430 Z_R4_H,Z_R4, 431 Z_R5_H,Z_R5, 432 Z_R6_H,Z_R6, 433 Z_R7_H,Z_R7, 434 Z_R8_H,Z_R8, // Z_thread 435 Z_R9_H,Z_R9, 436 Z_R10_H,Z_R10, 437 Z_R11_H,Z_R11, 438 Z_R12_H,Z_R12, 439 Z_R13_H,Z_R13 440 /*Z_R14_H,Z_R14*/ // return_pc 441 /*Z_R15_H,Z_R15*/ // SP 442 ); 443 444 // Other special pointer regs. 445 reg_class z_r1_regP(Z_R1_H,Z_R1); 446 reg_class z_r9_regP(Z_R9_H,Z_R9); 447 448 449 // Long Register Classes 450 451 reg_class z_rarg1_long_reg(Z_R2_H,Z_R2); 452 reg_class z_rarg2_long_reg(Z_R3_H,Z_R3); 453 reg_class z_rarg3_long_reg(Z_R4_H,Z_R4); 454 reg_class z_rarg4_long_reg(Z_R5_H,Z_R5); 455 reg_class z_rarg5_long_reg(Z_R6_H,Z_R6); 456 457 // Longs in 1 register. Aligned adjacent hi/lo pairs. 458 reg_class z_long_reg( 459 /*Z_R0_H,Z_R0*/ // R0 460 /*Z_R1_H,Z_R1*/ 461 Z_R2_H,Z_R2, 462 Z_R3_H,Z_R3, 463 Z_R4_H,Z_R4, 464 Z_R5_H,Z_R5, 465 Z_R6_H,Z_R6, 466 Z_R7_H,Z_R7, 467 /*Z_R8_H,Z_R8,*/ // Z_thread 468 Z_R9_H,Z_R9, 469 Z_R10_H,Z_R10, 470 Z_R11_H,Z_R11, 471 Z_R12_H,Z_R12, 472 Z_R13_H,Z_R13 473 /*Z_R14_H,Z_R14,*/ // return_pc 474 /*Z_R15_H,Z_R15*/ // SP 475 ); 476 477 478 // Special Class for Condition Code Flags Register 479 480 reg_class z_condition_reg( 481 Z_CR 482 ); 483 484 // Scratch register for late profiling. Callee saved. 485 reg_class z_rscratch2_bits64_reg(Z_R2_H, Z_R2); 486 487 488 // Float Register Classes 489 490 reg_class z_flt_reg( 491 Z_F0, 492 /*Z_F1,*/ // scratch 493 Z_F2, 494 Z_F3, 495 Z_F4, 496 Z_F5, 497 Z_F6, 498 Z_F7, 499 Z_F8, 500 Z_F9, 501 Z_F10, 502 Z_F11, 503 Z_F12, 504 Z_F13, 505 Z_F14, 506 Z_F15 507 ); 508 reg_class z_rscratch1_flt_reg(Z_F1); 509 510 // Double precision float registers have virtual `high halves' that 511 // are needed by the allocator. 512 reg_class z_dbl_reg( 513 Z_F0,Z_F0_H, 514 /*Z_F1,Z_F1_H,*/ // scratch 515 Z_F2,Z_F2_H, 516 Z_F3,Z_F3_H, 517 Z_F4,Z_F4_H, 518 Z_F5,Z_F5_H, 519 Z_F6,Z_F6_H, 520 Z_F7,Z_F7_H, 521 Z_F8,Z_F8_H, 522 Z_F9,Z_F9_H, 523 Z_F10,Z_F10_H, 524 Z_F11,Z_F11_H, 525 Z_F12,Z_F12_H, 526 Z_F13,Z_F13_H, 527 Z_F14,Z_F14_H, 528 Z_F15,Z_F15_H 529 ); 530 reg_class z_rscratch1_dbl_reg(Z_F1,Z_F1_H); 531 532 %} 533 534 //----------DEFINITION BLOCK--------------------------------------------------- 535 // Define 'name --> value' mappings to inform the ADLC of an integer valued name. 536 // Current support includes integer values in the range [0, 0x7FFFFFFF]. 537 // Format: 538 // int_def <name> (<int_value>, <expression>); 539 // Generated Code in ad_<arch>.hpp 540 // #define <name> (<expression>) 541 // // value == <int_value> 542 // Generated code in ad_<arch>.cpp adlc_verification() 543 // assert(<name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 544 // 545 definitions %{ 546 // The default cost (of an ALU instruction). 547 int_def DEFAULT_COST ( 100, 100); 548 int_def DEFAULT_COST_LOW ( 80, 80); 549 int_def DEFAULT_COST_HIGH ( 120, 120); 550 int_def HUGE_COST (1000000, 1000000); 551 552 // Put an advantage on REG_MEM vs. MEM+REG_REG operations. 553 int_def ALU_REG_COST ( 100, DEFAULT_COST); 554 int_def ALU_MEMORY_COST ( 150, 150); 555 556 // Memory refs are twice as expensive as run-of-the-mill. 557 int_def MEMORY_REF_COST_HI ( 220, 2 * DEFAULT_COST+20); 558 int_def MEMORY_REF_COST ( 200, 2 * DEFAULT_COST); 559 int_def MEMORY_REF_COST_LO ( 180, 2 * DEFAULT_COST-20); 560 561 // Branches are even more expensive. 562 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); 563 int_def CALL_COST ( 300, DEFAULT_COST * 3); 564 %} 565 566 source %{ 567 568 #ifdef PRODUCT 569 #define BLOCK_COMMENT(str) 570 #define BIND(label) __ bind(label) 571 #else 572 #define BLOCK_COMMENT(str) __ block_comment(str) 573 #define BIND(label) __ bind(label); BLOCK_COMMENT(#label ":") 574 #endif 575 576 #define __ _masm. 577 578 #define Z_DISP_SIZE Immediate::is_uimm12((long)opnd_array(1)->disp(ra_,this,2)) ? 4 : 6 579 #define Z_DISP3_SIZE 6 580 581 // Tertiary op of a LoadP or StoreP encoding. 582 #define REGP_OP true 583 584 // Given a register encoding, produce an Integer Register object. 585 static Register reg_to_register_object(int register_encoding); 586 587 // **************************************************************************** 588 589 // REQUIRED FUNCTIONALITY 590 591 // !!!!! Special hack to get all type of calls to specify the byte offset 592 // from the start of the call to the point where the return address 593 // will point. 594 595 int MachCallStaticJavaNode::ret_addr_offset() { 596 if (_method) { 597 return 8; 598 } else { 599 return MacroAssembler::call_far_patchable_ret_addr_offset(); 600 } 601 } 602 603 int MachCallDynamicJavaNode::ret_addr_offset() { 604 // Consider size of receiver type profiling (C2 tiers). 605 int profile_receiver_type_size = 0; 606 607 int vtable_index = this->_vtable_index; 608 if (vtable_index == -4) { 609 return 14 + profile_receiver_type_size; 610 } else { 611 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 612 return 36 + profile_receiver_type_size; 613 } 614 } 615 616 int MachCallRuntimeNode::ret_addr_offset() { 617 return 12 + MacroAssembler::call_far_patchable_ret_addr_offset(); 618 } 619 620 // Compute padding required for nodes which need alignment 621 // 622 // The addresses of the call instructions needs to be 4-byte aligned to 623 // ensure that they don't span a cache line so that they are atomically patchable. 624 // The actual calls get emitted at different offsets within the node emitters. 625 // ins_alignment needs to be set to 2 which means that up to 1 nop may get inserted. 626 627 int CallStaticJavaDirect_dynTOCNode::compute_padding(int current_offset) const { 628 return (0 - current_offset) & 2; 629 } 630 631 int CallDynamicJavaDirect_dynTOCNode::compute_padding(int current_offset) const { 632 return (6 - current_offset) & 2; 633 } 634 635 int CallRuntimeDirectNode::compute_padding(int current_offset) const { 636 return (12 - current_offset) & 2; 637 } 638 639 int CallLeafDirectNode::compute_padding(int current_offset) const { 640 return (12 - current_offset) & 2; 641 } 642 643 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const { 644 return (12 - current_offset) & 2; 645 } 646 647 // Indicate if the safepoint node needs the polling page as an input. 648 // Since z/Architecture does not have absolute addressing, it does. 649 bool SafePointNode::needs_polling_address_input() { 650 return true; 651 } 652 653 void emit_nop(CodeBuffer &cbuf) { 654 MacroAssembler _masm(&cbuf); 655 __ z_nop(); 656 } 657 658 // Emit an interrupt that is caught by the debugger (for debugging compiler). 659 void emit_break(CodeBuffer &cbuf) { 660 MacroAssembler _masm(&cbuf); 661 __ z_illtrap(); 662 } 663 664 #if !defined(PRODUCT) 665 void MachBreakpointNode::format(PhaseRegAlloc *, outputStream *os) const { 666 os->print("TA"); 667 } 668 #endif 669 670 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 671 emit_break(cbuf); 672 } 673 674 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 675 return MachNode::size(ra_); 676 } 677 678 static inline void z_emit16(CodeBuffer &cbuf, long value) { 679 // 32bit instructions may become sign extended. 680 assert(value >= 0, "unintended sign extension (int->long)"); 681 assert(value < (1L << 16), "instruction too large"); 682 *((unsigned short*)(cbuf.insts_end())) = (unsigned short)value; 683 cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned short)); 684 } 685 686 static inline void z_emit32(CodeBuffer &cbuf, long value) { 687 // 32bit instructions may become sign extended. 688 assert(value < (1L << 32), "instruction too large"); 689 *((unsigned int*)(cbuf.insts_end())) = (unsigned int)value; 690 cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned int)); 691 } 692 693 static inline void z_emit48(CodeBuffer &cbuf, long value) { 694 // 32bit instructions may become sign extended. 695 assert(value >= 0, "unintended sign extension (int->long)"); 696 assert(value < (1L << 48), "instruction too large"); 697 value = value<<16; 698 memcpy(cbuf.insts_end(), (unsigned char*)&value, 6); 699 cbuf.set_insts_end(cbuf.insts_end() + 6); 700 } 701 702 static inline unsigned int z_emit_inst(CodeBuffer &cbuf, long value) { 703 if (value < 0) { 704 // There obviously has been an unintended sign extension (int->long). Revert it. 705 value = (long)((unsigned long)((unsigned int)value)); 706 } 707 708 if (value < (1L << 16)) { // 2-byte instruction 709 z_emit16(cbuf, value); 710 return 2; 711 } 712 713 if (value < (1L << 32)) { // 4-byte instruction, might be unaligned store 714 z_emit32(cbuf, value); 715 return 4; 716 } 717 718 // 6-byte instruction, probably unaligned store. 719 z_emit48(cbuf, value); 720 return 6; 721 } 722 723 // Check effective address (at runtime) for required alignment. 724 static inline void z_assert_aligned(CodeBuffer &cbuf, int disp, Register index, Register base, int alignment) { 725 MacroAssembler _masm(&cbuf); 726 727 __ z_lay(Z_R0, disp, index, base); 728 __ z_nill(Z_R0, alignment-1); 729 __ z_brc(Assembler::bcondEqual, +3); 730 __ z_illtrap(); 731 } 732 733 int emit_call_reloc(MacroAssembler &_masm, intptr_t entry_point, relocInfo::relocType rtype, 734 PhaseRegAlloc* ra_, bool is_native_call = false) { 735 __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp(). 736 address old_mark = __ inst_mark(); 737 unsigned int start_off = __ offset(); 738 739 if (is_native_call) { 740 ShouldNotReachHere(); 741 } 742 743 if (rtype == relocInfo::runtime_call_w_cp_type) { 744 assert((__ offset() & 2) == 0, "misaligned emit_call_reloc"); 745 address call_addr = __ call_c_opt((address)entry_point); 746 if (call_addr == NULL) { 747 Compile::current()->env()->record_out_of_memory_failure(); 748 return -1; 749 } 750 } else { 751 assert(rtype == relocInfo::none || rtype == relocInfo::opt_virtual_call_type || 752 rtype == relocInfo::static_call_type, "unexpected rtype"); 753 __ relocate(rtype); 754 // BRASL must be prepended with a nop to identify it in the instruction stream. 755 __ z_nop(); 756 __ z_brasl(Z_R14, (address)entry_point); 757 } 758 759 unsigned int ret_off = __ offset(); 760 761 return (ret_off - start_off); 762 } 763 764 static int emit_call_reloc(MacroAssembler &_masm, intptr_t entry_point, RelocationHolder const& rspec) { 765 __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp(). 766 address old_mark = __ inst_mark(); 767 unsigned int start_off = __ offset(); 768 769 relocInfo::relocType rtype = rspec.type(); 770 assert(rtype == relocInfo::opt_virtual_call_type || rtype == relocInfo::static_call_type, 771 "unexpected rtype"); 772 773 __ relocate(rspec); 774 __ z_nop(); 775 __ z_brasl(Z_R14, (address)entry_point); 776 777 unsigned int ret_off = __ offset(); 778 779 return (ret_off - start_off); 780 } 781 782 //============================================================================= 783 784 const RegMask& MachConstantBaseNode::_out_RegMask = _Z_PTR_REG_mask; 785 int Compile::ConstantTable::calculate_table_base_offset() const { 786 return 0; // absolute addressing, no offset 787 } 788 789 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } 790 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { 791 ShouldNotReachHere(); 792 } 793 794 // Even with PC-relative TOC addressing, we still need this node. 795 // Float loads/stores do not support PC-relative addresses. 796 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 797 MacroAssembler _masm(&cbuf); 798 Register Rtoc = as_Register(ra_->get_encode(this)); 799 __ load_toc(Rtoc); 800 } 801 802 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { 803 // PCrelative TOC access. 804 return 6; // sizeof(LARL) 805 } 806 807 #if !defined(PRODUCT) 808 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 809 Register r = as_Register(ra_->get_encode(this)); 810 st->print("LARL %s,&constant_pool # MachConstantBaseNode", r->name()); 811 } 812 #endif 813 814 //============================================================================= 815 816 #if !defined(PRODUCT) 817 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 818 Compile* C = ra_->C; 819 st->print_cr("--- MachPrologNode ---"); 820 st->print("\t"); 821 for (int i = 0; i < OptoPrologueNops; i++) { 822 st->print_cr("NOP"); st->print("\t"); 823 } 824 825 if (VerifyThread) { 826 st->print_cr("Verify_Thread"); 827 st->print("\t"); 828 } 829 830 long framesize = C->frame_size_in_bytes(); 831 int bangsize = C->bang_size_in_bytes(); 832 833 // Calls to C2R adapters often do not accept exceptional returns. 834 // We require that their callers must bang for them. But be 835 // careful, because some VM calls (such as call site linkage) can 836 // use several kilobytes of stack. But the stack safety zone should 837 // account for that. See bugs 4446381, 4468289, 4497237. 838 if (C->need_stack_bang(bangsize) && UseStackBanging) { 839 st->print_cr("# stack bang"); st->print("\t"); 840 } 841 st->print_cr("push_frame %d", (int)-framesize); 842 st->print("\t"); 843 } 844 #endif 845 846 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 847 Compile* C = ra_->C; 848 MacroAssembler _masm(&cbuf); 849 850 __ verify_thread(); 851 852 size_t framesize = C->frame_size_in_bytes(); 853 size_t bangsize = C->bang_size_in_bytes(); 854 855 assert(framesize % wordSize == 0, "must preserve wordSize alignment"); 856 857 // Calls to C2R adapters often do not accept exceptional returns. 858 // We require that their callers must bang for them. But be 859 // careful, because some VM calls (such as call site linkage) can 860 // use several kilobytes of stack. But the stack safety zone should 861 // account for that. See bugs 4446381, 4468289, 4497237. 862 if (C->need_stack_bang(bangsize) && UseStackBanging) { 863 __ generate_stack_overflow_check(bangsize); 864 } 865 866 assert(Immediate::is_uimm32((long)framesize), "to do: choose suitable types!"); 867 __ save_return_pc(); 868 869 // The z/Architecture abi is already accounted for in `framesize' via the 870 // 'out_preserve_stack_slots' declaration. 871 __ push_frame((unsigned int)framesize/*includes JIT ABI*/); 872 873 if (C->has_mach_constant_base_node()) { 874 // NOTE: We set the table base offset here because users might be 875 // emitted before MachConstantBaseNode. 876 Compile::ConstantTable& constant_table = C->constant_table(); 877 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); 878 } 879 } 880 881 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 882 // Variable size. Determine dynamically. 883 return MachNode::size(ra_); 884 } 885 886 int MachPrologNode::reloc() const { 887 // Return number of relocatable values contained in this instruction. 888 return 1; // One reloc entry for load_const(toc). 889 } 890 891 //============================================================================= 892 893 #if !defined(PRODUCT) 894 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *os) const { 895 os->print_cr("epilog"); 896 os->print("\t"); 897 if (do_polling() && ra_->C->is_method_compilation()) { 898 os->print_cr("load_from_polling_page Z_R1_scratch"); 899 os->print("\t"); 900 } 901 } 902 #endif 903 904 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 905 MacroAssembler _masm(&cbuf); 906 Compile* C = ra_->C; 907 __ verify_thread(); 908 909 // If this does safepoint polling, then do it here. 910 bool need_polling = do_polling() && C->is_method_compilation(); 911 912 // Pop frame, restore return_pc, and all stuff needed by interpreter. 913 int frame_size_in_bytes = Assembler::align((C->frame_slots() << LogBytesPerInt), frame::alignment_in_bytes); 914 __ pop_frame_restore_retPC(frame_size_in_bytes); 915 916 if (StackReservedPages > 0 && C->has_reserved_stack_access()) { 917 __ reserved_stack_check(Z_R14); 918 } 919 920 // Touch the polling page. 921 if (need_polling) { 922 AddressLiteral pp(os::get_polling_page()); 923 __ load_const_optimized(Z_R1_scratch, pp); 924 // We need to mark the code position where the load from the safepoint 925 // polling page was emitted as relocInfo::poll_return_type here. 926 __ relocate(relocInfo::poll_return_type); 927 __ load_from_polling_page(Z_R1_scratch); 928 } 929 } 930 931 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 932 // Variable size. determine dynamically. 933 return MachNode::size(ra_); 934 } 935 936 int MachEpilogNode::reloc() const { 937 // Return number of relocatable values contained in this instruction. 938 return 1; // One for load_from_polling_page. 939 } 940 941 const Pipeline * MachEpilogNode::pipeline() const { 942 return MachNode::pipeline_class(); 943 } 944 945 int MachEpilogNode::safepoint_offset() const { 946 assert(do_polling(), "no return for this epilog node"); 947 return 0; 948 } 949 950 //============================================================================= 951 952 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack. 953 enum RC { rc_bad, rc_int, rc_float, rc_stack }; 954 955 static enum RC rc_class(OptoReg::Name reg) { 956 // Return the register class for the given register. The given register 957 // reg is a <register>_num value, which is an index into the MachRegisterNumbers 958 // enumeration in adGlobals_s390.hpp. 959 960 if (reg == OptoReg::Bad) { 961 return rc_bad; 962 } 963 964 // We have 32 integer register halves, starting at index 0. 965 if (reg < 32) { 966 return rc_int; 967 } 968 969 // We have 32 floating-point register halves, starting at index 32. 970 if (reg < 32+32) { 971 return rc_float; 972 } 973 974 // Between float regs & stack are the flags regs. 975 assert(reg >= OptoReg::stack0(), "blow up if spilling flags"); 976 return rc_stack; 977 } 978 979 // Returns size as obtained from z_emit_instr. 980 static unsigned int z_ld_st_helper(CodeBuffer *cbuf, const char *op_str, unsigned long opcode, 981 int reg, int offset, bool do_print, outputStream *os) { 982 983 if (cbuf) { 984 if (opcode > (1L<<32)) { 985 return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 48) | 986 Assembler::simm20(offset) | Assembler::reg(Z_R0, 12, 48) | Assembler::regz(Z_SP, 16, 48)); 987 } else { 988 return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 32) | 989 Assembler::uimm12(offset, 20, 32) | Assembler::reg(Z_R0, 12, 32) | Assembler::regz(Z_SP, 16, 32)); 990 } 991 } 992 993 #if !defined(PRODUCT) 994 if (do_print) { 995 os->print("%s %s,#%d[,SP]\t # MachCopy spill code",op_str, Matcher::regName[reg], offset); 996 } 997 #endif 998 return (opcode > (1L << 32)) ? 6 : 4; 999 } 1000 1001 static unsigned int z_mvc_helper(CodeBuffer *cbuf, int len, int dst_off, int src_off, bool do_print, outputStream *os) { 1002 if (cbuf) { 1003 MacroAssembler _masm(cbuf); 1004 __ z_mvc(dst_off, len-1, Z_SP, src_off, Z_SP); 1005 } 1006 1007 #if !defined(PRODUCT) 1008 else if (do_print) { 1009 os->print("MVC %d(%d,SP),%d(SP)\t # MachCopy spill code",dst_off, len, src_off); 1010 } 1011 #endif 1012 1013 return 6; 1014 } 1015 1016 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *os) const { 1017 // Get registers to move. 1018 OptoReg::Name src_hi = ra_->get_reg_second(in(1)); 1019 OptoReg::Name src_lo = ra_->get_reg_first(in(1)); 1020 OptoReg::Name dst_hi = ra_->get_reg_second(this); 1021 OptoReg::Name dst_lo = ra_->get_reg_first(this); 1022 1023 enum RC src_hi_rc = rc_class(src_hi); 1024 enum RC src_lo_rc = rc_class(src_lo); 1025 enum RC dst_hi_rc = rc_class(dst_hi); 1026 enum RC dst_lo_rc = rc_class(dst_lo); 1027 1028 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register"); 1029 bool is64 = (src_hi_rc != rc_bad); 1030 assert(!is64 || 1031 ((src_lo&1) == 0 && src_lo+1 == src_hi && (dst_lo&1) == 0 && dst_lo+1 == dst_hi), 1032 "expected aligned-adjacent pairs"); 1033 1034 // Generate spill code! 1035 1036 if (src_lo == dst_lo && src_hi == dst_hi) { 1037 return 0; // Self copy, no move. 1038 } 1039 1040 int src_offset = ra_->reg2offset(src_lo); 1041 int dst_offset = ra_->reg2offset(dst_lo); 1042 bool print = !do_size; 1043 bool src12 = Immediate::is_uimm12(src_offset); 1044 bool dst12 = Immediate::is_uimm12(dst_offset); 1045 1046 const char *mnemo = NULL; 1047 unsigned long opc = 0; 1048 1049 // Memory->Memory Spill. Use Z_R0 to hold the value. 1050 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { 1051 1052 assert(!is64 || (src_hi_rc==rc_stack && dst_hi_rc==rc_stack), 1053 "expected same type of move for high parts"); 1054 1055 if (src12 && dst12) { 1056 return z_mvc_helper(cbuf, is64 ? 8 : 4, dst_offset, src_offset, print, os); 1057 } 1058 1059 int r0 = Z_R0_num; 1060 if (is64) { 1061 return z_ld_st_helper(cbuf, "LG ", LG_ZOPC, r0, src_offset, print, os) + 1062 z_ld_st_helper(cbuf, "STG ", STG_ZOPC, r0, dst_offset, print, os); 1063 } 1064 1065 return z_ld_st_helper(cbuf, "LY ", LY_ZOPC, r0, src_offset, print, os) + 1066 z_ld_st_helper(cbuf, "STY ", STY_ZOPC, r0, dst_offset, print, os); 1067 } 1068 1069 // Check for float->int copy. Requires a trip through memory. 1070 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) { 1071 Unimplemented(); // Unsafe, do not remove! 1072 } 1073 1074 // Check for integer reg-reg copy. 1075 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) { 1076 if (cbuf) { 1077 MacroAssembler _masm(cbuf); 1078 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); 1079 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); 1080 __ z_lgr(Rdst, Rsrc); 1081 return 4; 1082 } 1083 #if !defined(PRODUCT) 1084 // else 1085 if (print) { 1086 os->print("LGR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1087 } 1088 #endif 1089 return 4; 1090 } 1091 1092 // Check for integer store. 1093 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) { 1094 assert(!is64 || (src_hi_rc==rc_int && dst_hi_rc==rc_stack), 1095 "expected same type of move for high parts"); 1096 1097 if (is64) { 1098 return z_ld_st_helper(cbuf, "STG ", STG_ZOPC, src_lo, dst_offset, print, os); 1099 } 1100 1101 // else 1102 mnemo = dst12 ? "ST " : "STY "; 1103 opc = dst12 ? ST_ZOPC : STY_ZOPC; 1104 1105 return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os); 1106 } 1107 1108 // Check for integer load 1109 // Always load cOops zero-extended. That doesn't hurt int loads. 1110 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) { 1111 1112 assert(!is64 || (dst_hi_rc==rc_int && src_hi_rc==rc_stack), 1113 "expected same type of move for high parts"); 1114 1115 mnemo = is64 ? "LG " : "LLGF"; 1116 opc = is64 ? LG_ZOPC : LLGF_ZOPC; 1117 1118 return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os); 1119 } 1120 1121 // Check for float reg-reg copy. 1122 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { 1123 if (cbuf) { 1124 MacroAssembler _masm(cbuf); 1125 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]); 1126 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]); 1127 __ z_ldr(Rdst, Rsrc); 1128 return 2; 1129 } 1130 #if !defined(PRODUCT) 1131 // else 1132 if (print) { 1133 os->print("LDR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1134 } 1135 #endif 1136 return 2; 1137 } 1138 1139 // Check for float store. 1140 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { 1141 assert(!is64 || (src_hi_rc==rc_float && dst_hi_rc==rc_stack), 1142 "expected same type of move for high parts"); 1143 1144 if (is64) { 1145 mnemo = dst12 ? "STD " : "STDY "; 1146 opc = dst12 ? STD_ZOPC : STDY_ZOPC; 1147 return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os); 1148 } 1149 // else 1150 1151 mnemo = dst12 ? "STE " : "STEY "; 1152 opc = dst12 ? STE_ZOPC : STEY_ZOPC; 1153 return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os); 1154 } 1155 1156 // Check for float load. 1157 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) { 1158 assert(!is64 || (dst_hi_rc==rc_float && src_hi_rc==rc_stack), 1159 "expected same type of move for high parts"); 1160 1161 if (is64) { 1162 mnemo = src12 ? "LD " : "LDY "; 1163 opc = src12 ? LD_ZOPC : LDY_ZOPC; 1164 return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os); 1165 } 1166 // else 1167 1168 mnemo = src12 ? "LE " : "LEY "; 1169 opc = src12 ? LE_ZOPC : LEY_ZOPC; 1170 return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os); 1171 } 1172 1173 // -------------------------------------------------------------------- 1174 // Check for hi bits still needing moving. Only happens for misaligned 1175 // arguments to native calls. 1176 if (src_hi == dst_hi) { 1177 return 0; // Self copy, no move. 1178 } 1179 1180 assert(is64 && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad"); 1181 Unimplemented(); // Unsafe, do not remove! 1182 1183 return 0; // never reached, but make the compiler shut up! 1184 } 1185 1186 #if !defined(PRODUCT) 1187 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *os) const { 1188 if (ra_ && ra_->node_regs_max_index() > 0) { 1189 implementation(NULL, ra_, false, os); 1190 } else { 1191 if (req() == 2 && in(1)) { 1192 os->print("N%d = N%d\n", _idx, in(1)->_idx); 1193 } else { 1194 const char *c = "("; 1195 os->print("N%d = ", _idx); 1196 for (uint i = 1; i < req(); ++i) { 1197 os->print("%sN%d", c, in(i)->_idx); 1198 c = ", "; 1199 } 1200 os->print(")"); 1201 } 1202 } 1203 } 1204 #endif 1205 1206 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1207 implementation(&cbuf, ra_, false, NULL); 1208 } 1209 1210 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1211 return implementation(NULL, ra_, true, NULL); 1212 } 1213 1214 //============================================================================= 1215 1216 #if !defined(PRODUCT) 1217 void MachNopNode::format(PhaseRegAlloc *, outputStream *os) const { 1218 os->print("NOP # pad for alignment (%d nops, %d bytes)", _count, _count*MacroAssembler::nop_size()); 1219 } 1220 #endif 1221 1222 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ra_) const { 1223 MacroAssembler _masm(&cbuf); 1224 1225 int rem_space = 0; 1226 if (!(ra_->C->in_scratch_emit_size())) { 1227 rem_space = cbuf.insts()->remaining(); 1228 if (rem_space <= _count*2 + 8) { 1229 tty->print("NopNode: _count = %3.3d, remaining space before = %d", _count, rem_space); 1230 } 1231 } 1232 1233 for (int i = 0; i < _count; i++) { 1234 __ z_nop(); 1235 } 1236 1237 if (!(ra_->C->in_scratch_emit_size())) { 1238 if (rem_space <= _count*2 + 8) { 1239 int rem_space2 = cbuf.insts()->remaining(); 1240 tty->print_cr(", after = %d", rem_space2); 1241 } 1242 } 1243 } 1244 1245 uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1246 return 2 * _count; 1247 } 1248 1249 #if !defined(PRODUCT) 1250 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *os) const { 1251 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1252 if (ra_ && ra_->node_regs_max_index() > 0) { 1253 int reg = ra_->get_reg_first(this); 1254 os->print("ADDHI %s, SP, %d\t//box node", Matcher::regName[reg], offset); 1255 } else { 1256 os->print("ADDHI N%d = SP + %d\t// box node", _idx, offset); 1257 } 1258 } 1259 #endif 1260 1261 // Take care of the size function, if you make changes here! 1262 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1263 MacroAssembler _masm(&cbuf); 1264 1265 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1266 int reg = ra_->get_encode(this); 1267 __ z_lay(as_Register(reg), offset, Z_SP); 1268 } 1269 1270 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1271 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) 1272 return 6; 1273 } 1274 1275 %} // end source section 1276 1277 //----------SOURCE BLOCK------------------------------------------------------- 1278 // This is a block of C++ code which provides values, functions, and 1279 // definitions necessary in the rest of the architecture description 1280 1281 source_hpp %{ 1282 1283 // Header information of the source block. 1284 // Method declarations/definitions which are used outside 1285 // the ad-scope can conveniently be defined here. 1286 // 1287 // To keep related declarations/definitions/uses close together, 1288 // we switch between source %{ }% and source_hpp %{ }% freely as needed. 1289 1290 //-------------------------------------------------------------- 1291 // Used for optimization in Compile::Shorten_branches 1292 //-------------------------------------------------------------- 1293 1294 class CallStubImpl { 1295 public: 1296 1297 // call trampolines 1298 // Size of call trampoline stub. For add'l comments, see size_java_to_interp(). 1299 static uint size_call_trampoline() { 1300 return 0; // no call trampolines on this platform 1301 } 1302 1303 // call trampolines 1304 // Number of relocations needed by a call trampoline stub. 1305 static uint reloc_call_trampoline() { 1306 return 0; // No call trampolines on this platform. 1307 } 1308 }; 1309 1310 %} // end source_hpp section 1311 1312 source %{ 1313 1314 #if !defined(PRODUCT) 1315 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *os) const { 1316 os->print_cr("---- MachUEPNode ----"); 1317 os->print_cr("\tTA"); 1318 os->print_cr("\tload_const Z_R1, SharedRuntime::get_ic_miss_stub()"); 1319 os->print_cr("\tBR(Z_R1)"); 1320 os->print_cr("\tTA # pad with illtraps"); 1321 os->print_cr("\t..."); 1322 os->print_cr("\tTA"); 1323 os->print_cr("\tLTGR Z_R2, Z_R2"); 1324 os->print_cr("\tBRU ic_miss"); 1325 } 1326 #endif 1327 1328 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1329 MacroAssembler _masm(&cbuf); 1330 const int ic_miss_offset = 2; 1331 1332 // Inline_cache contains a klass. 1333 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode()); 1334 // ARG1 is the receiver oop. 1335 Register R2_receiver = Z_ARG1; 1336 int klass_offset = oopDesc::klass_offset_in_bytes(); 1337 AddressLiteral icmiss(SharedRuntime::get_ic_miss_stub()); 1338 Register R1_ic_miss_stub_addr = Z_R1_scratch; 1339 1340 // Null check of receiver. 1341 // This is the null check of the receiver that actually should be 1342 // done in the caller. It's here because in case of implicit null 1343 // checks we get it for free. 1344 assert(!MacroAssembler::needs_explicit_null_check(oopDesc::klass_offset_in_bytes()), 1345 "second word in oop should not require explicit null check."); 1346 if (!ImplicitNullChecks) { 1347 Label valid; 1348 if (VM_Version::has_CompareBranch()) { 1349 __ z_cgij(R2_receiver, 0, Assembler::bcondNotEqual, valid); 1350 } else { 1351 __ z_ltgr(R2_receiver, R2_receiver); 1352 __ z_bre(valid); 1353 } 1354 // The ic_miss_stub will handle the null pointer exception. 1355 __ load_const_optimized(R1_ic_miss_stub_addr, icmiss); 1356 __ z_br(R1_ic_miss_stub_addr); 1357 __ bind(valid); 1358 } 1359 1360 // Check whether this method is the proper implementation for the class of 1361 // the receiver (ic miss check). 1362 { 1363 Label valid; 1364 // Compare cached class against klass from receiver. 1365 // This also does an implicit null check! 1366 __ compare_klass_ptr(ic_klass, klass_offset, R2_receiver, false); 1367 __ z_bre(valid); 1368 // The inline cache points to the wrong method. Call the 1369 // ic_miss_stub to find the proper method. 1370 __ load_const_optimized(R1_ic_miss_stub_addr, icmiss); 1371 __ z_br(R1_ic_miss_stub_addr); 1372 __ bind(valid); 1373 } 1374 1375 } 1376 1377 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1378 // Determine size dynamically. 1379 return MachNode::size(ra_); 1380 } 1381 1382 //============================================================================= 1383 1384 %} // interrupt source section 1385 1386 source_hpp %{ // Header information of the source block. 1387 1388 class HandlerImpl { 1389 public: 1390 1391 static int emit_exception_handler(CodeBuffer &cbuf); 1392 static int emit_deopt_handler(CodeBuffer& cbuf); 1393 1394 static uint size_exception_handler() { 1395 return NativeJump::max_instruction_size(); 1396 } 1397 1398 static uint size_deopt_handler() { 1399 return NativeCall::max_instruction_size(); 1400 } 1401 }; 1402 1403 %} // end source_hpp section 1404 1405 source %{ 1406 1407 // This exception handler code snippet is placed after the method's 1408 // code. It is the return point if an exception occurred. it jumps to 1409 // the exception blob. 1410 // 1411 // If the method gets deoptimized, the method and this code snippet 1412 // get patched. 1413 // 1414 // 1) Trampoline code gets patched into the end of this exception 1415 // handler. the trampoline code jumps to the deoptimization blob. 1416 // 1417 // 2) The return address in the method's code will get patched such 1418 // that it jumps to the trampoline. 1419 // 1420 // 3) The handler will get patched such that it does not jump to the 1421 // exception blob, but to an entry in the deoptimization blob being 1422 // aware of the exception. 1423 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) { 1424 Register temp_reg = Z_R1; 1425 MacroAssembler _masm(&cbuf); 1426 1427 address base = __ start_a_stub(size_exception_handler()); 1428 if (base == NULL) { 1429 return 0; // CodeBuffer::expand failed 1430 } 1431 1432 int offset = __ offset(); 1433 // Use unconditional pc-relative jump with 32-bit range here. 1434 __ load_const_optimized(temp_reg, (address)OptoRuntime::exception_blob()->content_begin()); 1435 __ z_br(temp_reg); 1436 1437 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1438 1439 __ end_a_stub(); 1440 1441 return offset; 1442 } 1443 1444 // Emit deopt handler code. 1445 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { 1446 MacroAssembler _masm(&cbuf); 1447 address base = __ start_a_stub(size_deopt_handler()); 1448 1449 if (base == NULL) { 1450 return 0; // CodeBuffer::expand failed 1451 } 1452 1453 int offset = __ offset(); 1454 1455 // Size_deopt_handler() must be exact on zarch, so for simplicity 1456 // we do not use load_const_opt here. 1457 __ load_const(Z_R1, SharedRuntime::deopt_blob()->unpack()); 1458 __ call(Z_R1); 1459 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size"); 1460 1461 __ end_a_stub(); 1462 return offset; 1463 } 1464 1465 //============================================================================= 1466 1467 1468 // Given a register encoding, produce an Integer Register object. 1469 static Register reg_to_register_object(int register_encoding) { 1470 assert(Z_R12->encoding() == Z_R12_enc, "wrong coding"); 1471 return as_Register(register_encoding); 1472 } 1473 1474 const bool Matcher::match_rule_supported(int opcode) { 1475 if (!has_match_rule(opcode)) return false; 1476 1477 switch (opcode) { 1478 case Op_CountLeadingZerosI: 1479 case Op_CountLeadingZerosL: 1480 case Op_CountTrailingZerosI: 1481 case Op_CountTrailingZerosL: 1482 // Implementation requires FLOGR instruction, which is available since z9. 1483 return true; 1484 1485 case Op_ReverseBytesI: 1486 case Op_ReverseBytesL: 1487 return UseByteReverseInstruction; 1488 1489 // PopCount supported by H/W from z/Architecture G5 (z196) on. 1490 case Op_PopCountI: 1491 case Op_PopCountL: 1492 return UsePopCountInstruction && VM_Version::has_PopCount(); 1493 1494 case Op_StrComp: 1495 return SpecialStringCompareTo; 1496 case Op_StrEquals: 1497 return SpecialStringEquals; 1498 case Op_StrIndexOf: 1499 case Op_StrIndexOfChar: 1500 return SpecialStringIndexOf; 1501 1502 case Op_GetAndAddI: 1503 case Op_GetAndAddL: 1504 return true; 1505 // return VM_Version::has_AtomicMemWithImmALUOps(); 1506 case Op_GetAndSetI: 1507 case Op_GetAndSetL: 1508 case Op_GetAndSetP: 1509 case Op_GetAndSetN: 1510 return true; // General CAS implementation, always available. 1511 1512 default: 1513 return true; // Per default match rules are supported. 1514 // BUT: make sure match rule is not disabled by a false predicate! 1515 } 1516 1517 return true; // Per default match rules are supported. 1518 // BUT: make sure match rule is not disabled by a false predicate! 1519 } 1520 1521 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) { 1522 // TODO 1523 // Identify extra cases that we might want to provide match rules for 1524 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen. 1525 bool ret_value = match_rule_supported(opcode); 1526 // Add rules here. 1527 1528 return ret_value; // Per default match rules are supported. 1529 } 1530 1531 int Matcher::regnum_to_fpu_offset(int regnum) { 1532 ShouldNotReachHere(); 1533 return regnum - 32; // The FP registers are in the second chunk. 1534 } 1535 1536 const bool Matcher::has_predicated_vectors(void) { 1537 return false; 1538 } 1539 1540 const int Matcher::float_pressure(int default_pressure_threshold) { 1541 return default_pressure_threshold; 1542 } 1543 1544 const bool Matcher::convL2FSupported(void) { 1545 return true; // False means that conversion is done by runtime call. 1546 } 1547 1548 //----------SUPERWORD HELPERS---------------------------------------- 1549 1550 // Vector width in bytes. 1551 const int Matcher::vector_width_in_bytes(BasicType bt) { 1552 assert(MaxVectorSize == 8, ""); 1553 return 8; 1554 } 1555 1556 // Vector ideal reg. 1557 const uint Matcher::vector_ideal_reg(int size) { 1558 assert(MaxVectorSize == 8 && size == 8, ""); 1559 return Op_RegL; 1560 } 1561 1562 // Limits on vector size (number of elements) loaded into vector. 1563 const int Matcher::max_vector_size(const BasicType bt) { 1564 assert(is_java_primitive(bt), "only primitive type vectors"); 1565 return vector_width_in_bytes(bt)/type2aelembytes(bt); 1566 } 1567 1568 const int Matcher::min_vector_size(const BasicType bt) { 1569 return max_vector_size(bt); // Same as max. 1570 } 1571 1572 const uint Matcher::vector_shift_count_ideal_reg(int size) { 1573 fatal("vector shift is not supported"); 1574 return Node::NotAMachineReg; 1575 } 1576 1577 // z/Architecture does support misaligned store/load at minimal extra cost. 1578 const bool Matcher::misaligned_vectors_ok() { 1579 return true; 1580 } 1581 1582 // Not yet ported to z/Architecture. 1583 const bool Matcher::pass_original_key_for_aes() { 1584 return false; 1585 } 1586 1587 // RETURNS: whether this branch offset is short enough that a short 1588 // branch can be used. 1589 // 1590 // If the platform does not provide any short branch variants, then 1591 // this method should return `false' for offset 0. 1592 // 1593 // `Compile::Fill_buffer' will decide on basis of this information 1594 // whether to do the pass `Compile::Shorten_branches' at all. 1595 // 1596 // And `Compile::Shorten_branches' will decide on basis of this 1597 // information whether to replace particular branch sites by short 1598 // ones. 1599 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 1600 // On zarch short branches use a 16 bit signed immediate that 1601 // is the pc-relative offset in halfword (= 2 bytes) units. 1602 return Assembler::is_within_range_of_RelAddr16((address)((long)offset), (address)0); 1603 } 1604 1605 const bool Matcher::isSimpleConstant64(jlong value) { 1606 // Probably always true, even if a temp register is required. 1607 return true; 1608 } 1609 1610 // Should correspond to setting above 1611 const bool Matcher::init_array_count_is_in_bytes = false; 1612 1613 // Suppress CMOVL. Conditional move available on z/Architecture only from z196 onwards. Not exploited yet. 1614 const int Matcher::long_cmove_cost() { return ConditionalMoveLimit; } 1615 1616 // Suppress CMOVF. Conditional move available on z/Architecture only from z196 onwards. Not exploited yet. 1617 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; } 1618 1619 // Does the CPU require postalloc expand (see block.cpp for description of postalloc expand)? 1620 const bool Matcher::require_postalloc_expand = false; 1621 1622 // Do we need to mask the count passed to shift instructions or does 1623 // the cpu only look at the lower 5/6 bits anyway? 1624 // 32bit shifts mask in emitter, 64bit shifts need no mask. 1625 // Constant shift counts are handled in Ideal phase. 1626 const bool Matcher::need_masked_shift_count = false; 1627 1628 // Set this as clone_shift_expressions. 1629 bool Matcher::narrow_oop_use_complex_address() { 1630 if (Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0) return true; 1631 return false; 1632 } 1633 1634 bool Matcher::narrow_klass_use_complex_address() { 1635 NOT_LP64(ShouldNotCallThis()); 1636 assert(UseCompressedClassPointers, "only for compressed klass code"); 1637 // TODO HS25: z port if (MatchDecodeNodes) return true; 1638 return false; 1639 } 1640 1641 bool Matcher::const_oop_prefer_decode() { 1642 // Prefer ConN+DecodeN over ConP in simple compressed oops mode. 1643 return Universe::narrow_oop_base() == NULL; 1644 } 1645 1646 bool Matcher::const_klass_prefer_decode() { 1647 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode. 1648 return Universe::narrow_klass_base() == NULL; 1649 } 1650 1651 // Is it better to copy float constants, or load them directly from memory? 1652 // Most RISCs will have to materialize an address into a 1653 // register first, so they would do better to copy the constant from stack. 1654 const bool Matcher::rematerialize_float_constants = false; 1655 1656 // If CPU can load and store mis-aligned doubles directly then no fixup is 1657 // needed. Else we split the double into 2 integer pieces and move it 1658 // piece-by-piece. Only happens when passing doubles into C code as the 1659 // Java calling convention forces doubles to be aligned. 1660 const bool Matcher::misaligned_doubles_ok = true; 1661 1662 // Advertise here if the CPU requires explicit rounding operations 1663 // to implement the UseStrictFP mode. 1664 const bool Matcher::strict_fp_requires_explicit_rounding = false; 1665 1666 // Do floats take an entire double register or just half? 1667 // 1668 // A float in resides in a zarch double register. When storing it by 1669 // z_std, it cannot be restored in C-code by reloading it as a double 1670 // and casting it into a float afterwards. 1671 bool Matcher::float_in_double() { return false; } 1672 1673 // Do ints take an entire long register or just half? 1674 // The relevant question is how the int is callee-saved: 1675 // the whole long is written but de-opt'ing will have to extract 1676 // the relevant 32 bits. 1677 const bool Matcher::int_in_long = true; 1678 1679 // Constants for c2c and c calling conventions. 1680 1681 const MachRegisterNumbers z_iarg_reg[5] = { 1682 Z_R2_num, Z_R3_num, Z_R4_num, Z_R5_num, Z_R6_num 1683 }; 1684 1685 const MachRegisterNumbers z_farg_reg[4] = { 1686 Z_F0_num, Z_F2_num, Z_F4_num, Z_F6_num 1687 }; 1688 1689 const int z_num_iarg_registers = sizeof(z_iarg_reg) / sizeof(z_iarg_reg[0]); 1690 1691 const int z_num_farg_registers = sizeof(z_farg_reg) / sizeof(z_farg_reg[0]); 1692 1693 // Return whether or not this register is ever used as an argument. This 1694 // function is used on startup to build the trampoline stubs in generateOptoStub. 1695 // Registers not mentioned will be killed by the VM call in the trampoline, and 1696 // arguments in those registers not be available to the callee. 1697 bool Matcher::can_be_java_arg(int reg) { 1698 // We return true for all registers contained in z_iarg_reg[] and 1699 // z_farg_reg[] and their virtual halves. 1700 // We must include the virtual halves in order to get STDs and LDs 1701 // instead of STWs and LWs in the trampoline stubs. 1702 1703 if (reg == Z_R2_num || reg == Z_R2_H_num || 1704 reg == Z_R3_num || reg == Z_R3_H_num || 1705 reg == Z_R4_num || reg == Z_R4_H_num || 1706 reg == Z_R5_num || reg == Z_R5_H_num || 1707 reg == Z_R6_num || reg == Z_R6_H_num) { 1708 return true; 1709 } 1710 1711 if (reg == Z_F0_num || reg == Z_F0_H_num || 1712 reg == Z_F2_num || reg == Z_F2_H_num || 1713 reg == Z_F4_num || reg == Z_F4_H_num || 1714 reg == Z_F6_num || reg == Z_F6_H_num) { 1715 return true; 1716 } 1717 1718 return false; 1719 } 1720 1721 bool Matcher::is_spillable_arg(int reg) { 1722 return can_be_java_arg(reg); 1723 } 1724 1725 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) { 1726 return false; 1727 } 1728 1729 // Register for DIVI projection of divmodI 1730 RegMask Matcher::divI_proj_mask() { 1731 return _Z_RARG4_INT_REG_mask; 1732 } 1733 1734 // Register for MODI projection of divmodI 1735 RegMask Matcher::modI_proj_mask() { 1736 return _Z_RARG3_INT_REG_mask; 1737 } 1738 1739 // Register for DIVL projection of divmodL 1740 RegMask Matcher::divL_proj_mask() { 1741 return _Z_RARG4_LONG_REG_mask; 1742 } 1743 1744 // Register for MODL projection of divmodL 1745 RegMask Matcher::modL_proj_mask() { 1746 return _Z_RARG3_LONG_REG_mask; 1747 } 1748 1749 // Copied from sparc. 1750 const RegMask Matcher::method_handle_invoke_SP_save_mask() { 1751 return RegMask(); 1752 } 1753 1754 const bool Matcher::convi2l_type_required = true; 1755 1756 // Should the Matcher clone shifts on addressing modes, expecting them 1757 // to be subsumed into complex addressing expressions or compute them 1758 // into registers? 1759 bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) { 1760 return clone_base_plus_offset_address(m, mstack, address_visited); 1761 } 1762 1763 void Compile::reshape_address(AddPNode* addp) { 1764 } 1765 1766 %} // source 1767 1768 //----------ENCODING BLOCK----------------------------------------------------- 1769 // This block specifies the encoding classes used by the compiler to output 1770 // byte streams. Encoding classes are parameterized macros used by 1771 // Machine Instruction Nodes in order to generate the bit encoding of the 1772 // instruction. Operands specify their base encoding interface with the 1773 // interface keyword. There are currently supported four interfaces, 1774 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 1775 // operand to generate a function which returns its register number when 1776 // queried. CONST_INTER causes an operand to generate a function which 1777 // returns the value of the constant when queried. MEMORY_INTER causes an 1778 // operand to generate four functions which return the Base Register, the 1779 // Index Register, the Scale Value, and the Offset Value of the operand when 1780 // queried. COND_INTER causes an operand to generate six functions which 1781 // return the encoding code (ie - encoding bits for the instruction) 1782 // associated with each basic boolean condition for a conditional instruction. 1783 // 1784 // Instructions specify two basic values for encoding. Again, a function 1785 // is available to check if the constant displacement is an oop. They use the 1786 // ins_encode keyword to specify their encoding classes (which must be 1787 // a sequence of enc_class names, and their parameters, specified in 1788 // the encoding block), and they use the 1789 // opcode keyword to specify, in order, their primary, secondary, and 1790 // tertiary opcode. Only the opcode sections which a particular instruction 1791 // needs for encoding need to be specified. 1792 encode %{ 1793 enc_class enc_unimplemented %{ 1794 MacroAssembler _masm(&cbuf); 1795 __ unimplemented("Unimplemented mach node encoding in AD file.", 13); 1796 %} 1797 1798 enc_class enc_untested %{ 1799 #ifdef ASSERT 1800 MacroAssembler _masm(&cbuf); 1801 __ untested("Untested mach node encoding in AD file."); 1802 #endif 1803 %} 1804 1805 enc_class z_rrform(iRegI dst, iRegI src) %{ 1806 assert((($primary >> 14) & 0x03) == 0, "Instruction format error"); 1807 assert( ($primary >> 16) == 0, "Instruction format error"); 1808 z_emit16(cbuf, $primary | 1809 Assembler::reg($dst$$reg,8,16) | 1810 Assembler::reg($src$$reg,12,16)); 1811 %} 1812 1813 enc_class z_rreform(iRegI dst1, iRegI src2) %{ 1814 assert((($primary >> 30) & 0x03) == 2, "Instruction format error"); 1815 z_emit32(cbuf, $primary | 1816 Assembler::reg($dst1$$reg,24,32) | 1817 Assembler::reg($src2$$reg,28,32)); 1818 %} 1819 1820 enc_class z_rrfform(iRegI dst1, iRegI src2, iRegI src3) %{ 1821 assert((($primary >> 30) & 0x03) == 2, "Instruction format error"); 1822 z_emit32(cbuf, $primary | 1823 Assembler::reg($dst1$$reg,24,32) | 1824 Assembler::reg($src2$$reg,28,32) | 1825 Assembler::reg($src3$$reg,16,32)); 1826 %} 1827 1828 enc_class z_riform_signed(iRegI dst, immI16 src) %{ 1829 assert((($primary>>30) & 0x03) == 2, "Instruction format error"); 1830 z_emit32(cbuf, $primary | 1831 Assembler::reg($dst$$reg,8,32) | 1832 Assembler::simm16($src$$constant,16,32)); 1833 %} 1834 1835 enc_class z_riform_unsigned(iRegI dst, uimmI16 src) %{ 1836 assert((($primary>>30) & 0x03) == 2, "Instruction format error"); 1837 z_emit32(cbuf, $primary | 1838 Assembler::reg($dst$$reg,8,32) | 1839 Assembler::uimm16($src$$constant,16,32)); 1840 %} 1841 1842 enc_class z_rieform_d(iRegI dst1, iRegI src3, immI src2) %{ 1843 assert((($primary>>46) & 0x03) == 3, "Instruction format error"); 1844 z_emit48(cbuf, $primary | 1845 Assembler::reg($dst1$$reg,8,48) | 1846 Assembler::reg($src3$$reg,12,48) | 1847 Assembler::simm16($src2$$constant,16,48)); 1848 %} 1849 1850 enc_class z_rilform_signed(iRegI dst, immL32 src) %{ 1851 assert((($primary>>46) & 0x03) == 3, "Instruction format error"); 1852 z_emit48(cbuf, $primary | 1853 Assembler::reg($dst$$reg,8,48) | 1854 Assembler::simm32($src$$constant,16,48)); 1855 %} 1856 1857 enc_class z_rilform_unsigned(iRegI dst, uimmL32 src) %{ 1858 assert((($primary>>46) & 0x03) == 3, "Instruction format error"); 1859 z_emit48(cbuf, $primary | 1860 Assembler::reg($dst$$reg,8,48) | 1861 Assembler::uimm32($src$$constant,16,48)); 1862 %} 1863 1864 enc_class z_rsyform_const(iRegI dst, iRegI src1, immI src2) %{ 1865 z_emit48(cbuf, $primary | 1866 Assembler::reg($dst$$reg,8,48) | 1867 Assembler::reg($src1$$reg,12,48) | 1868 Assembler::simm20($src2$$constant)); 1869 %} 1870 1871 enc_class z_rsyform_reg_reg(iRegI dst, iRegI src, iRegI shft) %{ 1872 z_emit48(cbuf, $primary | 1873 Assembler::reg($dst$$reg,8,48) | 1874 Assembler::reg($src$$reg,12,48) | 1875 Assembler::reg($shft$$reg,16,48) | 1876 Assembler::simm20(0)); 1877 %} 1878 1879 enc_class z_rxform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{ 1880 assert((($primary>>30) & 0x03) == 1, "Instruction format error"); 1881 z_emit32(cbuf, $primary | 1882 Assembler::reg($dst$$reg,8,32) | 1883 Assembler::reg($src1$$reg,12,32) | 1884 Assembler::reg($src2$$reg,16,32) | 1885 Assembler::uimm12($con$$constant,20,32)); 1886 %} 1887 1888 enc_class z_rxform_imm_reg(iRegL dst, immL con, iRegL src) %{ 1889 assert((($primary>>30) & 0x03) == 1, "Instruction format error"); 1890 z_emit32(cbuf, $primary | 1891 Assembler::reg($dst$$reg,8,32) | 1892 Assembler::reg($src$$reg,16,32) | 1893 Assembler::uimm12($con$$constant,20,32)); 1894 %} 1895 1896 enc_class z_rxyform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{ 1897 z_emit48(cbuf, $primary | 1898 Assembler::reg($dst$$reg,8,48) | 1899 Assembler::reg($src1$$reg,12,48) | 1900 Assembler::reg($src2$$reg,16,48) | 1901 Assembler::simm20($con$$constant)); 1902 %} 1903 1904 enc_class z_rxyform_imm_reg(iRegL dst, immL con, iRegL src) %{ 1905 z_emit48(cbuf, $primary | 1906 Assembler::reg($dst$$reg,8,48) | 1907 Assembler::reg($src$$reg,16,48) | 1908 Assembler::simm20($con$$constant)); 1909 %} 1910 1911 // Direct memory arithmetic. 1912 enc_class z_siyform(memoryRSY mem, immI8 src) %{ 1913 int disp = $mem$$disp; 1914 Register base = reg_to_register_object($mem$$base); 1915 int con = $src$$constant; 1916 1917 assert(VM_Version::has_MemWithImmALUOps(), "unsupported CPU"); 1918 z_emit_inst(cbuf, $primary | 1919 Assembler::regz(base,16,48) | 1920 Assembler::simm20(disp) | 1921 Assembler::simm8(con,8,48)); 1922 %} 1923 1924 enc_class z_silform(memoryRS mem, immI16 src) %{ 1925 z_emit_inst(cbuf, $primary | 1926 Assembler::regz(reg_to_register_object($mem$$base),16,48) | 1927 Assembler::uimm12($mem$$disp,20,48) | 1928 Assembler::simm16($src$$constant,32,48)); 1929 %} 1930 1931 // Encoder for FP ALU reg/mem instructions (support only short displacements). 1932 enc_class z_form_rt_memFP(RegF dst, memoryRX mem) %{ 1933 Register Ridx = $mem$$index$$Register; 1934 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0. 1935 if ($primary > (1L << 32)) { 1936 z_emit_inst(cbuf, $primary | 1937 Assembler::reg($dst$$reg, 8, 48) | 1938 Assembler::uimm12($mem$$disp, 20, 48) | 1939 Assembler::reg(Ridx, 12, 48) | 1940 Assembler::regz(reg_to_register_object($mem$$base), 16, 48)); 1941 } else { 1942 z_emit_inst(cbuf, $primary | 1943 Assembler::reg($dst$$reg, 8, 32) | 1944 Assembler::uimm12($mem$$disp, 20, 32) | 1945 Assembler::reg(Ridx, 12, 32) | 1946 Assembler::regz(reg_to_register_object($mem$$base), 16, 32)); 1947 } 1948 %} 1949 1950 enc_class z_form_rt_mem(iRegI dst, memory mem) %{ 1951 Register Ridx = $mem$$index$$Register; 1952 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0. 1953 if ($primary > (1L<<32)) { 1954 z_emit_inst(cbuf, $primary | 1955 Assembler::reg($dst$$reg, 8, 48) | 1956 Assembler::simm20($mem$$disp) | 1957 Assembler::reg(Ridx, 12, 48) | 1958 Assembler::regz(reg_to_register_object($mem$$base), 16, 48)); 1959 } else { 1960 z_emit_inst(cbuf, $primary | 1961 Assembler::reg($dst$$reg, 8, 32) | 1962 Assembler::uimm12($mem$$disp, 20, 32) | 1963 Assembler::reg(Ridx, 12, 32) | 1964 Assembler::regz(reg_to_register_object($mem$$base), 16, 32)); 1965 } 1966 %} 1967 1968 enc_class z_form_rt_mem_opt(iRegI dst, memory mem) %{ 1969 int isize = $secondary > 1L << 32 ? 48 : 32; 1970 Register Ridx = $mem$$index$$Register; 1971 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0. 1972 1973 if (Displacement::is_shortDisp((long)$mem$$disp)) { 1974 z_emit_inst(cbuf, $secondary | 1975 Assembler::reg($dst$$reg, 8, isize) | 1976 Assembler::uimm12($mem$$disp, 20, isize) | 1977 Assembler::reg(Ridx, 12, isize) | 1978 Assembler::regz(reg_to_register_object($mem$$base), 16, isize)); 1979 } else if (Displacement::is_validDisp((long)$mem$$disp)) { 1980 z_emit_inst(cbuf, $primary | 1981 Assembler::reg($dst$$reg, 8, 48) | 1982 Assembler::simm20($mem$$disp) | 1983 Assembler::reg(Ridx, 12, 48) | 1984 Assembler::regz(reg_to_register_object($mem$$base), 16, 48)); 1985 } else { 1986 MacroAssembler _masm(&cbuf); 1987 __ load_const_optimized(Z_R1_scratch, $mem$$disp); 1988 if (Ridx != Z_R0) { __ z_agr(Z_R1_scratch, Ridx); } 1989 z_emit_inst(cbuf, $secondary | 1990 Assembler::reg($dst$$reg, 8, isize) | 1991 Assembler::uimm12(0, 20, isize) | 1992 Assembler::reg(Z_R1_scratch, 12, isize) | 1993 Assembler::regz(reg_to_register_object($mem$$base), 16, isize)); 1994 } 1995 %} 1996 1997 enc_class z_enc_brul(Label lbl) %{ 1998 MacroAssembler _masm(&cbuf); 1999 Label* p = $lbl$$label; 2000 2001 // 'p' is `NULL' when this encoding class is used only to 2002 // determine the size of the encoded instruction. 2003 // Use a bound dummy label in that case. 2004 Label d; 2005 __ bind(d); 2006 Label& l = (NULL == p) ? d : *(p); 2007 __ z_brul(l); 2008 %} 2009 2010 enc_class z_enc_bru(Label lbl) %{ 2011 MacroAssembler _masm(&cbuf); 2012 Label* p = $lbl$$label; 2013 2014 // 'p' is `NULL' when this encoding class is used only to 2015 // determine the size of the encoded instruction. 2016 // Use a bound dummy label in that case. 2017 Label d; 2018 __ bind(d); 2019 Label& l = (NULL == p) ? d : *(p); 2020 __ z_bru(l); 2021 %} 2022 2023 enc_class z_enc_branch_con_far(cmpOp cmp, Label lbl) %{ 2024 MacroAssembler _masm(&cbuf); 2025 Label* p = $lbl$$label; 2026 2027 // 'p' is `NULL' when this encoding class is used only to 2028 // determine the size of the encoded instruction. 2029 // Use a bound dummy label in that case. 2030 Label d; 2031 __ bind(d); 2032 Label& l = (NULL == p) ? d : *(p); 2033 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l); 2034 %} 2035 2036 enc_class z_enc_branch_con_short(cmpOp cmp, Label lbl) %{ 2037 MacroAssembler _masm(&cbuf); 2038 Label* p = $lbl$$label; 2039 2040 // 'p' is `NULL' when this encoding class is used only to 2041 // determine the size of the encoded instruction. 2042 // Use a bound dummy label in that case. 2043 Label d; 2044 __ bind(d); 2045 Label& l = (NULL == p) ? d : *(p); 2046 __ z_brc((Assembler::branch_condition)$cmp$$cmpcode, l); 2047 %} 2048 2049 enc_class z_enc_cmpb_regreg(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{ 2050 MacroAssembler _masm(&cbuf); 2051 Label* p = $lbl$$label; 2052 2053 // 'p' is `NULL' when this encoding class is used only to 2054 // determine the size of the encoded instruction. 2055 // Use a bound dummy label in that case. 2056 Label d; 2057 __ bind(d); 2058 Label& l = (NULL == p) ? d : *(p); 2059 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode; 2060 unsigned long instr = $primary; 2061 if (instr == CRJ_ZOPC) { 2062 __ z_crj($src1$$Register, $src2$$Register, cc, l); 2063 } else if (instr == CLRJ_ZOPC) { 2064 __ z_clrj($src1$$Register, $src2$$Register, cc, l); 2065 } else if (instr == CGRJ_ZOPC) { 2066 __ z_cgrj($src1$$Register, $src2$$Register, cc, l); 2067 } else { 2068 guarantee(instr == CLGRJ_ZOPC, "opcode not implemented"); 2069 __ z_clgrj($src1$$Register, $src2$$Register, cc, l); 2070 } 2071 %} 2072 2073 enc_class z_enc_cmpb_regregFar(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{ 2074 MacroAssembler _masm(&cbuf); 2075 Label* p = $lbl$$label; 2076 2077 // 'p' is `NULL' when this encoding class is used only to 2078 // determine the size of the encoded instruction. 2079 // Use a bound dummy label in that case. 2080 Label d; 2081 __ bind(d); 2082 Label& l = (NULL == p) ? d : *(p); 2083 2084 unsigned long instr = $primary; 2085 if (instr == CR_ZOPC) { 2086 __ z_cr($src1$$Register, $src2$$Register); 2087 } else if (instr == CLR_ZOPC) { 2088 __ z_clr($src1$$Register, $src2$$Register); 2089 } else if (instr == CGR_ZOPC) { 2090 __ z_cgr($src1$$Register, $src2$$Register); 2091 } else { 2092 guarantee(instr == CLGR_ZOPC, "opcode not implemented"); 2093 __ z_clgr($src1$$Register, $src2$$Register); 2094 } 2095 2096 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l); 2097 %} 2098 2099 enc_class z_enc_cmpb_regimm(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{ 2100 MacroAssembler _masm(&cbuf); 2101 Label* p = $lbl$$label; 2102 2103 // 'p' is `NULL' when this encoding class is used only to 2104 // determine the size of the encoded instruction. 2105 // Use a bound dummy label in that case. 2106 Label d; 2107 __ bind(d); 2108 Label& l = (NULL == p) ? d : *(p); 2109 2110 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode; 2111 unsigned long instr = $primary; 2112 if (instr == CIJ_ZOPC) { 2113 __ z_cij($src1$$Register, $src2$$constant, cc, l); 2114 } else if (instr == CLIJ_ZOPC) { 2115 __ z_clij($src1$$Register, $src2$$constant, cc, l); 2116 } else if (instr == CGIJ_ZOPC) { 2117 __ z_cgij($src1$$Register, $src2$$constant, cc, l); 2118 } else { 2119 guarantee(instr == CLGIJ_ZOPC, "opcode not implemented"); 2120 __ z_clgij($src1$$Register, $src2$$constant, cc, l); 2121 } 2122 %} 2123 2124 enc_class z_enc_cmpb_regimmFar(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{ 2125 MacroAssembler _masm(&cbuf); 2126 Label* p = $lbl$$label; 2127 2128 // 'p' is `NULL' when this encoding class is used only to 2129 // determine the size of the encoded instruction. 2130 // Use a bound dummy label in that case. 2131 Label d; 2132 __ bind(d); 2133 Label& l = (NULL == p) ? d : *(p); 2134 2135 unsigned long instr = $primary; 2136 if (instr == CHI_ZOPC) { 2137 __ z_chi($src1$$Register, $src2$$constant); 2138 } else if (instr == CLFI_ZOPC) { 2139 __ z_clfi($src1$$Register, $src2$$constant); 2140 } else if (instr == CGHI_ZOPC) { 2141 __ z_cghi($src1$$Register, $src2$$constant); 2142 } else { 2143 guarantee(instr == CLGFI_ZOPC, "opcode not implemented"); 2144 __ z_clgfi($src1$$Register, $src2$$constant); 2145 } 2146 2147 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l); 2148 %} 2149 2150 // Call from Java to runtime. 2151 enc_class z_enc_java_to_runtime_call(method meth) %{ 2152 MacroAssembler _masm(&cbuf); 2153 2154 // Save return pc before call to the place where we need it, since 2155 // callee doesn't. 2156 unsigned int start_off = __ offset(); 2157 // Compute size of "larl + stg + call_c_opt". 2158 const int size_of_code = 6 + 6 + MacroAssembler::call_far_patchable_size(); 2159 __ get_PC(Z_R14, size_of_code); 2160 __ save_return_pc(); 2161 assert(__ offset() - start_off == 12, "bad prelude len: %d", __ offset() - start_off); 2162 2163 assert((__ offset() & 2) == 0, "misaligned z_enc_java_to_runtime_call"); 2164 address call_addr = __ call_c_opt((address)$meth$$method); 2165 if (call_addr == NULL) { 2166 Compile::current()->env()->record_out_of_memory_failure(); 2167 return; 2168 } 2169 2170 #ifdef ASSERT 2171 // Plausibility check for size_of_code assumptions. 2172 unsigned int actual_ret_off = __ offset(); 2173 assert(start_off + size_of_code == actual_ret_off, "wrong return_pc"); 2174 #endif 2175 %} 2176 2177 enc_class z_enc_java_static_call(method meth) %{ 2178 // Call to fixup routine. Fixup routine uses ScopeDesc info to determine 2179 // whom we intended to call. 2180 MacroAssembler _masm(&cbuf); 2181 int ret_offset = 0; 2182 2183 if (!_method) { 2184 ret_offset = emit_call_reloc(_masm, $meth$$method, 2185 relocInfo::runtime_call_w_cp_type, ra_); 2186 } else { 2187 int method_index = resolved_method_index(cbuf); 2188 if (_optimized_virtual) { 2189 ret_offset = emit_call_reloc(_masm, $meth$$method, 2190 opt_virtual_call_Relocation::spec(method_index)); 2191 } else { 2192 ret_offset = emit_call_reloc(_masm, $meth$$method, 2193 static_call_Relocation::spec(method_index)); 2194 } 2195 } 2196 assert(__ inst_mark() != NULL, "emit_call_reloc must set_inst_mark()"); 2197 2198 if (_method) { // Emit stub for static call. 2199 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf); 2200 if (stub == NULL) { 2201 ciEnv::current()->record_failure("CodeCache is full"); 2202 return; 2203 } 2204 } 2205 %} 2206 2207 // Java dynamic call 2208 enc_class z_enc_java_dynamic_call(method meth) %{ 2209 MacroAssembler _masm(&cbuf); 2210 unsigned int start_off = __ offset(); 2211 2212 int vtable_index = this->_vtable_index; 2213 if (vtable_index == -4) { 2214 Register ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2215 address virtual_call_oop_addr = NULL; 2216 2217 AddressLiteral empty_ic((address) Universe::non_oop_word()); 2218 virtual_call_oop_addr = __ pc(); 2219 bool success = __ load_const_from_toc(ic_reg, empty_ic); 2220 if (!success) { 2221 Compile::current()->env()->record_out_of_memory_failure(); 2222 return; 2223 } 2224 2225 // Call to fixup routine. Fixup routine uses ScopeDesc info 2226 // to determine who we intended to call. 2227 int method_index = resolved_method_index(cbuf); 2228 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index)); 2229 unsigned int ret_off = __ offset(); 2230 assert(__ offset() - start_off == 6, "bad prelude len: %d", __ offset() - start_off); 2231 ret_off += emit_call_reloc(_masm, $meth$$method, relocInfo::none, ra_); 2232 assert(_method, "lazy_constant may be wrong when _method==null"); 2233 } else { 2234 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 2235 // Go through the vtable. Get receiver klass. Receiver already 2236 // checked for non-null. If we'll go thru a C2I adapter, the 2237 // interpreter expects method in Z_method. 2238 // Use Z_method to temporarily hold the klass oop. Z_R1_scratch is destroyed 2239 // by load_heap_oop_not_null. 2240 __ load_klass(Z_method, Z_R2); 2241 2242 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index * vtableEntry::size_in_bytes(); 2243 int v_off = entry_offset + vtableEntry::method_offset_in_bytes(); 2244 2245 if (Displacement::is_validDisp(v_off) ) { 2246 // Can use load instruction with large offset. 2247 __ z_lg(Z_method, Address(Z_method /*class oop*/, v_off /*method offset*/)); 2248 } else { 2249 // Worse case, must load offset into register. 2250 __ load_const(Z_R1_scratch, v_off); 2251 __ z_lg(Z_method, Address(Z_method /*class oop*/, Z_R1_scratch /*method offset*/)); 2252 } 2253 // NOTE: for vtable dispatches, the vtable entry will never be 2254 // null. However it may very well end up in handle_wrong_method 2255 // if the method is abstract for the particular class. 2256 __ z_lg(Z_R1_scratch, Address(Z_method, Method::from_compiled_offset())); 2257 // Call target. Either compiled code or C2I adapter. 2258 __ z_basr(Z_R14, Z_R1_scratch); 2259 unsigned int ret_off = __ offset(); 2260 } 2261 %} 2262 2263 enc_class z_enc_cmov_reg(cmpOp cmp, iRegI dst, iRegI src) %{ 2264 MacroAssembler _masm(&cbuf); 2265 Register Rdst = reg_to_register_object($dst$$reg); 2266 Register Rsrc = reg_to_register_object($src$$reg); 2267 2268 // Don't emit code if operands are identical (same register). 2269 if (Rsrc != Rdst) { 2270 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode; 2271 2272 if (VM_Version::has_LoadStoreConditional()) { 2273 __ z_locgr(Rdst, Rsrc, cc); 2274 } else { 2275 // Branch if not (cmp cr). 2276 Label done; 2277 __ z_brc(Assembler::inverse_condition(cc), done); 2278 __ z_lgr(Rdst, Rsrc); // Used for int and long+ptr. 2279 __ bind(done); 2280 } 2281 } 2282 %} 2283 2284 enc_class z_enc_cmov_imm(cmpOp cmp, iRegI dst, immI16 src) %{ 2285 MacroAssembler _masm(&cbuf); 2286 Register Rdst = reg_to_register_object($dst$$reg); 2287 int Csrc = $src$$constant; 2288 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode; 2289 Label done; 2290 // Branch if not (cmp cr). 2291 __ z_brc(Assembler::inverse_condition(cc), done); 2292 if (Csrc == 0) { 2293 // Don't set CC. 2294 __ clear_reg(Rdst, true, false); // Use for int, long & ptr. 2295 } else { 2296 __ z_lghi(Rdst, Csrc); // Use for int, long & ptr. 2297 } 2298 __ bind(done); 2299 %} 2300 2301 enc_class z_enc_cctobool(iRegI res) %{ 2302 MacroAssembler _masm(&cbuf); 2303 Register Rres = reg_to_register_object($res$$reg); 2304 2305 if (VM_Version::has_LoadStoreConditional()) { 2306 __ load_const_optimized(Z_R0_scratch, 0L); // false (failed) 2307 __ load_const_optimized(Rres, 1L); // true (succeed) 2308 __ z_locgr(Rres, Z_R0_scratch, Assembler::bcondNotEqual); 2309 } else { 2310 Label done; 2311 __ load_const_optimized(Rres, 0L); // false (failed) 2312 __ z_brne(done); // Assume true to be the common case. 2313 __ load_const_optimized(Rres, 1L); // true (succeed) 2314 __ bind(done); 2315 } 2316 %} 2317 2318 enc_class z_enc_casI(iRegI compare_value, iRegI exchange_value, iRegP addr_ptr) %{ 2319 MacroAssembler _masm(&cbuf); 2320 Register Rcomp = reg_to_register_object($compare_value$$reg); 2321 Register Rnew = reg_to_register_object($exchange_value$$reg); 2322 Register Raddr = reg_to_register_object($addr_ptr$$reg); 2323 2324 __ z_cs(Rcomp, Rnew, 0, Raddr); 2325 %} 2326 2327 enc_class z_enc_casL(iRegL compare_value, iRegL exchange_value, iRegP addr_ptr) %{ 2328 MacroAssembler _masm(&cbuf); 2329 Register Rcomp = reg_to_register_object($compare_value$$reg); 2330 Register Rnew = reg_to_register_object($exchange_value$$reg); 2331 Register Raddr = reg_to_register_object($addr_ptr$$reg); 2332 2333 __ z_csg(Rcomp, Rnew, 0, Raddr); 2334 %} 2335 2336 enc_class z_enc_SwapI(memoryRSY mem, iRegI dst, iRegI tmp) %{ 2337 MacroAssembler _masm(&cbuf); 2338 Register Rdst = reg_to_register_object($dst$$reg); 2339 Register Rtmp = reg_to_register_object($tmp$$reg); 2340 guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF"); 2341 Label retry; 2342 2343 // Iterate until swap succeeds. 2344 __ z_llgf(Rtmp, $mem$$Address); // current contents 2345 __ bind(retry); 2346 // Calculate incremented value. 2347 __ z_csy(Rtmp, Rdst, $mem$$Address); // Try to store new value. 2348 __ z_brne(retry); // Yikes, concurrent update, need to retry. 2349 __ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value. 2350 %} 2351 2352 enc_class z_enc_SwapL(memoryRSY mem, iRegL dst, iRegL tmp) %{ 2353 MacroAssembler _masm(&cbuf); 2354 Register Rdst = reg_to_register_object($dst$$reg); 2355 Register Rtmp = reg_to_register_object($tmp$$reg); 2356 guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF"); 2357 Label retry; 2358 2359 // Iterate until swap succeeds. 2360 __ z_lg(Rtmp, $mem$$Address); // current contents 2361 __ bind(retry); 2362 // Calculate incremented value. 2363 __ z_csg(Rtmp, Rdst, $mem$$Address); // Try to store new value. 2364 __ z_brne(retry); // Yikes, concurrent update, need to retry. 2365 __ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value. 2366 %} 2367 2368 %} // encode 2369 2370 source %{ 2371 2372 // Check whether outs are all Stores. If so, we can omit clearing the upper 2373 // 32 bits after encoding. 2374 static bool all_outs_are_Stores(const Node *n) { 2375 for (DUIterator_Fast imax, k = n->fast_outs(imax); k < imax; k++) { 2376 Node *out = n->fast_out(k); 2377 if (!out->is_Mach() || out->as_Mach()->ideal_Opcode() != Op_StoreN) { 2378 // Most other outs are SpillCopy, but there are various other. 2379 // jvm98 has arond 9% Encodes where we return false. 2380 return false; 2381 } 2382 } 2383 return true; 2384 } 2385 2386 %} // source 2387 2388 2389 //----------FRAME-------------------------------------------------------------- 2390 // Definition of frame structure and management information. 2391 2392 frame %{ 2393 // What direction does stack grow in (assumed to be same for native & Java). 2394 stack_direction(TOWARDS_LOW); 2395 2396 // These two registers define part of the calling convention between 2397 // compiled code and the interpreter. 2398 2399 // Inline Cache Register 2400 inline_cache_reg(Z_R9); // Z_inline_cache 2401 2402 // Argument pointer for I2C adapters 2403 // 2404 // Tos is loaded in run_compiled_code to Z_ARG5=Z_R6. 2405 // interpreter_arg_ptr_reg(Z_R6); 2406 2407 // Temporary in compiled entry-points 2408 // compiler_method_oop_reg(Z_R1);//Z_R1_scratch 2409 2410 // Method Oop Register when calling interpreter 2411 interpreter_method_oop_reg(Z_R9);//Z_method 2412 2413 // Optional: name the operand used by cisc-spilling to access 2414 // [stack_pointer + offset]. 2415 cisc_spilling_operand_name(indOffset12); 2416 2417 // Number of stack slots consumed by a Monitor enter. 2418 sync_stack_slots(frame::jit_monitor_size_in_4_byte_units); 2419 2420 // Compiled code's Frame Pointer 2421 // 2422 // z/Architecture stack pointer 2423 frame_pointer(Z_R15); // Z_SP 2424 2425 // Interpreter stores its frame pointer in a register which is 2426 // stored to the stack by I2CAdaptors. I2CAdaptors convert from 2427 // interpreted java to compiled java. 2428 // 2429 // Z_state holds pointer to caller's cInterpreter. 2430 interpreter_frame_pointer(Z_R7); // Z_state 2431 2432 // Use alignment_in_bytes instead of log_2_of_alignment_in_bits. 2433 stack_alignment(frame::alignment_in_bytes); 2434 2435 in_preserve_stack_slots(frame::jit_in_preserve_size_in_4_byte_units); 2436 2437 // A `slot' is assumed 4 bytes here! 2438 // out_preserve_stack_slots(frame::jit_out_preserve_size_in_4_byte_units); 2439 2440 // Number of outgoing stack slots killed above the 2441 // out_preserve_stack_slots for calls to C. Supports the var-args 2442 // backing area for register parms. 2443 varargs_C_out_slots_killed(((frame::z_abi_160_size - frame::z_jit_out_preserve_size) / VMRegImpl::stack_slot_size)); 2444 2445 // The after-PROLOG location of the return address. Location of 2446 // return address specifies a type (REG or STACK) and a number 2447 // representing the register number (i.e. - use a register name) or 2448 // stack slot. 2449 return_addr(REG Z_R14); 2450 2451 // This is the body of the function 2452 // 2453 // void Matcher::calling_convention(OptoRegPair* sig /* array of ideal regs */, 2454 // uint length /* length of array */, 2455 // bool is_outgoing) 2456 // 2457 // The `sig' array is to be updated. Sig[j] represents the location 2458 // of the j-th argument, either a register or a stack slot. 2459 2460 // Body of function which returns an integer array locating 2461 // arguments either in registers or in stack slots. Passed an array 2462 // of ideal registers called "sig" and a "length" count. Stack-slot 2463 // offsets are based on outgoing arguments, i.e. a CALLER setting up 2464 // arguments for a CALLEE. Incoming stack arguments are 2465 // automatically biased by the preserve_stack_slots field above. 2466 calling_convention %{ 2467 // No difference between ingoing/outgoing just pass false. 2468 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); 2469 %} 2470 2471 // Body of function which returns an integer array locating 2472 // arguments either in registers or in stack slots. Passed an array 2473 // of ideal registers called "sig" and a "length" count. Stack-slot 2474 // offsets are based on outgoing arguments, i.e. a CALLER setting up 2475 // arguments for a CALLEE. Incoming stack arguments are 2476 // automatically biased by the preserve_stack_slots field above. 2477 c_calling_convention %{ 2478 // This is obviously always outgoing. 2479 // C argument must be in register AND stack slot. 2480 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); 2481 %} 2482 2483 // Location of native (C/C++) and interpreter return values. This 2484 // is specified to be the same as Java. In the 32-bit VM, long 2485 // values are actually returned from native calls in O0:O1 and 2486 // returned to the interpreter in I0:I1. The copying to and from 2487 // the register pairs is done by the appropriate call and epilog 2488 // opcodes. This simplifies the register allocator. 2489 // 2490 // Use register pair for c return value. 2491 c_return_value %{ 2492 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values"); 2493 static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num }; 2494 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num }; 2495 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); 2496 %} 2497 2498 // Use register pair for return value. 2499 // Location of compiled Java return values. Same as C 2500 return_value %{ 2501 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values"); 2502 static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num }; 2503 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num }; 2504 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); 2505 %} 2506 %} 2507 2508 2509 //----------ATTRIBUTES--------------------------------------------------------- 2510 2511 //----------Operand Attributes------------------------------------------------- 2512 op_attrib op_cost(1); // Required cost attribute 2513 2514 //----------Instruction Attributes--------------------------------------------- 2515 2516 // Cost attribute. required. 2517 ins_attrib ins_cost(DEFAULT_COST); 2518 2519 // Is this instruction a non-matching short branch variant of some 2520 // long branch? Not required. 2521 ins_attrib ins_short_branch(0); 2522 2523 // Indicates this is a trap based check node and final control-flow fixup 2524 // must generate a proper fall through. 2525 ins_attrib ins_is_TrapBasedCheckNode(true); 2526 2527 // Attribute of instruction to tell how many constants the instruction will generate. 2528 // (optional attribute). Default: 0. 2529 ins_attrib ins_num_consts(0); 2530 2531 // Required alignment attribute (must be a power of 2) 2532 // specifies the alignment that some part of the instruction (not 2533 // necessarily the start) requires. If > 1, a compute_padding() 2534 // function must be provided for the instruction. 2535 // 2536 // WARNING: Don't use size(FIXED_SIZE) or size(VARIABLE_SIZE) in 2537 // instructions which depend on the proper alignment, because the 2538 // desired alignment isn't guaranteed for the call to "emit()" during 2539 // the size computation. 2540 ins_attrib ins_alignment(1); 2541 2542 // Enforce/prohibit rematerializations. 2543 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)' 2544 // then rematerialization of that instruction is prohibited and the 2545 // instruction's value will be spilled if necessary. 2546 // - If an instruction is attributed with 'ins_should_rematerialize(true)' 2547 // then rematerialization is enforced and the instruction's value will 2548 // never get spilled. a copy of the instruction will be inserted if 2549 // necessary. 2550 // Note: this may result in rematerializations in front of every use. 2551 // (optional attribute) 2552 ins_attrib ins_cannot_rematerialize(false); 2553 ins_attrib ins_should_rematerialize(false); 2554 2555 //----------OPERANDS----------------------------------------------------------- 2556 // Operand definitions must precede instruction definitions for correct 2557 // parsing in the ADLC because operands constitute user defined types 2558 // which are used in instruction definitions. 2559 2560 //----------Simple Operands---------------------------------------------------- 2561 // Immediate Operands 2562 // Please note: 2563 // Formats are generated automatically for constants and base registers. 2564 2565 //---------------------------------------------- 2566 // SIGNED (shorter than INT) immediate operands 2567 //---------------------------------------------- 2568 2569 // Byte Immediate: constant 'int -1' 2570 operand immB_minus1() %{ 2571 // sign-ext constant zero-ext constant 2572 predicate((n->get_int() == -1) || ((n->get_int()&0x000000ff) == 0x000000ff)); 2573 match(ConI); 2574 op_cost(1); 2575 format %{ %} 2576 interface(CONST_INTER); 2577 %} 2578 2579 // Byte Immediate: constant, but not 'int 0' nor 'int -1'. 2580 operand immB_n0m1() %{ 2581 // sign-ext constant zero-ext constant 2582 predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x000000ff) != 0x000000ff); 2583 match(ConI); 2584 op_cost(1); 2585 format %{ %} 2586 interface(CONST_INTER); 2587 %} 2588 2589 // Short Immediate: constant 'int -1' 2590 operand immS_minus1() %{ 2591 // sign-ext constant zero-ext constant 2592 predicate((n->get_int() == -1) || ((n->get_int()&0x0000ffff) == 0x0000ffff)); 2593 match(ConI); 2594 op_cost(1); 2595 format %{ %} 2596 interface(CONST_INTER); 2597 %} 2598 2599 // Short Immediate: constant, but not 'int 0' nor 'int -1'. 2600 operand immS_n0m1() %{ 2601 // sign-ext constant zero-ext constant 2602 predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x0000ffff) != 0x0000ffff); 2603 match(ConI); 2604 op_cost(1); 2605 format %{ %} 2606 interface(CONST_INTER); 2607 %} 2608 2609 //----------------------------------------- 2610 // SIGNED INT immediate operands 2611 //----------------------------------------- 2612 2613 // Integer Immediate: 32-bit 2614 operand immI() %{ 2615 match(ConI); 2616 op_cost(1); 2617 format %{ %} 2618 interface(CONST_INTER); 2619 %} 2620 2621 // Int Immediate: 20-bit 2622 operand immI20() %{ 2623 predicate(Immediate::is_simm20(n->get_int())); 2624 match(ConI); 2625 op_cost(1); 2626 format %{ %} 2627 interface(CONST_INTER); 2628 %} 2629 2630 // Integer Immediate: 16-bit 2631 operand immI16() %{ 2632 predicate(Immediate::is_simm16(n->get_int())); 2633 match(ConI); 2634 op_cost(1); 2635 format %{ %} 2636 interface(CONST_INTER); 2637 %} 2638 2639 // Integer Immediate: 8-bit 2640 operand immI8() %{ 2641 predicate(Immediate::is_simm8(n->get_int())); 2642 match(ConI); 2643 op_cost(1); 2644 format %{ %} 2645 interface(CONST_INTER); 2646 %} 2647 2648 // Integer Immediate: constant 'int 0' 2649 operand immI_0() %{ 2650 predicate(n->get_int() == 0); 2651 match(ConI); 2652 op_cost(1); 2653 format %{ %} 2654 interface(CONST_INTER); 2655 %} 2656 2657 // Integer Immediate: constant 'int -1' 2658 operand immI_minus1() %{ 2659 predicate(n->get_int() == -1); 2660 match(ConI); 2661 op_cost(1); 2662 format %{ %} 2663 interface(CONST_INTER); 2664 %} 2665 2666 // Integer Immediate: constant, but not 'int 0' nor 'int -1'. 2667 operand immI_n0m1() %{ 2668 predicate(n->get_int() != 0 && n->get_int() != -1); 2669 match(ConI); 2670 op_cost(1); 2671 format %{ %} 2672 interface(CONST_INTER); 2673 %} 2674 2675 //------------------------------------------- 2676 // UNSIGNED INT immediate operands 2677 //------------------------------------------- 2678 2679 // Unsigned Integer Immediate: 32-bit 2680 operand uimmI() %{ 2681 match(ConI); 2682 op_cost(1); 2683 format %{ %} 2684 interface(CONST_INTER); 2685 %} 2686 2687 // Unsigned Integer Immediate: 16-bit 2688 operand uimmI16() %{ 2689 predicate(Immediate::is_uimm16(n->get_int())); 2690 match(ConI); 2691 op_cost(1); 2692 format %{ %} 2693 interface(CONST_INTER); 2694 %} 2695 2696 // Unsigned Integer Immediate: 12-bit 2697 operand uimmI12() %{ 2698 predicate(Immediate::is_uimm12(n->get_int())); 2699 match(ConI); 2700 op_cost(1); 2701 format %{ %} 2702 interface(CONST_INTER); 2703 %} 2704 2705 // Unsigned Integer Immediate: 12-bit 2706 operand uimmI8() %{ 2707 predicate(Immediate::is_uimm8(n->get_int())); 2708 match(ConI); 2709 op_cost(1); 2710 format %{ %} 2711 interface(CONST_INTER); 2712 %} 2713 2714 // Integer Immediate: 6-bit 2715 operand uimmI6() %{ 2716 predicate(Immediate::is_uimm(n->get_int(), 6)); 2717 match(ConI); 2718 op_cost(1); 2719 format %{ %} 2720 interface(CONST_INTER); 2721 %} 2722 2723 // Integer Immediate: 5-bit 2724 operand uimmI5() %{ 2725 predicate(Immediate::is_uimm(n->get_int(), 5)); 2726 match(ConI); 2727 op_cost(1); 2728 format %{ %} 2729 interface(CONST_INTER); 2730 %} 2731 2732 // Length for SS instructions, given in DWs, 2733 // possible range [1..512], i.e. [8..4096] Bytes 2734 // used range [1..256], i.e. [8..2048] Bytes 2735 // operand type int 2736 // Unsigned Integer Immediate: 9-bit 2737 operand SSlenDW() %{ 2738 predicate(Immediate::is_uimm8(n->get_long()-1)); 2739 match(ConL); 2740 op_cost(1); 2741 format %{ %} 2742 interface(CONST_INTER); 2743 %} 2744 2745 //------------------------------------------ 2746 // (UN)SIGNED INT specific values 2747 //------------------------------------------ 2748 2749 // Integer Immediate: the value 1 2750 operand immI_1() %{ 2751 predicate(n->get_int() == 1); 2752 match(ConI); 2753 op_cost(1); 2754 format %{ %} 2755 interface(CONST_INTER); 2756 %} 2757 2758 // Integer Immediate: the value 16. 2759 operand immI_16() %{ 2760 predicate(n->get_int() == 16); 2761 match(ConI); 2762 op_cost(1); 2763 format %{ %} 2764 interface(CONST_INTER); 2765 %} 2766 2767 // Integer Immediate: the value 24. 2768 operand immI_24() %{ 2769 predicate(n->get_int() == 24); 2770 match(ConI); 2771 op_cost(1); 2772 format %{ %} 2773 interface(CONST_INTER); 2774 %} 2775 2776 // Integer Immediate: the value 255 2777 operand immI_255() %{ 2778 predicate(n->get_int() == 255); 2779 match(ConI); 2780 op_cost(1); 2781 format %{ %} 2782 interface(CONST_INTER); 2783 %} 2784 2785 // Integer Immediate: the values 32-63 2786 operand immI_32_63() %{ 2787 predicate(n->get_int() >= 32 && n->get_int() <= 63); 2788 match(ConI); 2789 op_cost(1); 2790 format %{ %} 2791 interface(CONST_INTER); 2792 %} 2793 2794 // Unsigned Integer Immediate: LL-part, extended by 1s. 2795 operand uimmI_LL1() %{ 2796 predicate((n->get_int() & 0xFFFF0000) == 0xFFFF0000); 2797 match(ConI); 2798 op_cost(1); 2799 format %{ %} 2800 interface(CONST_INTER); 2801 %} 2802 2803 // Unsigned Integer Immediate: LH-part, extended by 1s. 2804 operand uimmI_LH1() %{ 2805 predicate((n->get_int() & 0xFFFF) == 0xFFFF); 2806 match(ConI); 2807 op_cost(1); 2808 format %{ %} 2809 interface(CONST_INTER); 2810 %} 2811 2812 //------------------------------------------ 2813 // SIGNED LONG immediate operands 2814 //------------------------------------------ 2815 2816 operand immL() %{ 2817 match(ConL); 2818 op_cost(1); 2819 format %{ %} 2820 interface(CONST_INTER); 2821 %} 2822 2823 // Long Immediate: 32-bit 2824 operand immL32() %{ 2825 predicate(Immediate::is_simm32(n->get_long())); 2826 match(ConL); 2827 op_cost(1); 2828 format %{ %} 2829 interface(CONST_INTER); 2830 %} 2831 2832 // Long Immediate: 20-bit 2833 operand immL20() %{ 2834 predicate(Immediate::is_simm20(n->get_long())); 2835 match(ConL); 2836 op_cost(1); 2837 format %{ %} 2838 interface(CONST_INTER); 2839 %} 2840 2841 // Long Immediate: 16-bit 2842 operand immL16() %{ 2843 predicate(Immediate::is_simm16(n->get_long())); 2844 match(ConL); 2845 op_cost(1); 2846 format %{ %} 2847 interface(CONST_INTER); 2848 %} 2849 2850 // Long Immediate: 8-bit 2851 operand immL8() %{ 2852 predicate(Immediate::is_simm8(n->get_long())); 2853 match(ConL); 2854 op_cost(1); 2855 format %{ %} 2856 interface(CONST_INTER); 2857 %} 2858 2859 //-------------------------------------------- 2860 // UNSIGNED LONG immediate operands 2861 //-------------------------------------------- 2862 2863 operand uimmL32() %{ 2864 predicate(Immediate::is_uimm32(n->get_long())); 2865 match(ConL); 2866 op_cost(1); 2867 format %{ %} 2868 interface(CONST_INTER); 2869 %} 2870 2871 // Unsigned Long Immediate: 16-bit 2872 operand uimmL16() %{ 2873 predicate(Immediate::is_uimm16(n->get_long())); 2874 match(ConL); 2875 op_cost(1); 2876 format %{ %} 2877 interface(CONST_INTER); 2878 %} 2879 2880 // Unsigned Long Immediate: 12-bit 2881 operand uimmL12() %{ 2882 predicate(Immediate::is_uimm12(n->get_long())); 2883 match(ConL); 2884 op_cost(1); 2885 format %{ %} 2886 interface(CONST_INTER); 2887 %} 2888 2889 // Unsigned Long Immediate: 8-bit 2890 operand uimmL8() %{ 2891 predicate(Immediate::is_uimm8(n->get_long())); 2892 match(ConL); 2893 op_cost(1); 2894 format %{ %} 2895 interface(CONST_INTER); 2896 %} 2897 2898 //------------------------------------------- 2899 // (UN)SIGNED LONG specific values 2900 //------------------------------------------- 2901 2902 // Long Immediate: the value FF 2903 operand immL_FF() %{ 2904 predicate(n->get_long() == 0xFFL); 2905 match(ConL); 2906 op_cost(1); 2907 format %{ %} 2908 interface(CONST_INTER); 2909 %} 2910 2911 // Long Immediate: the value FFFF 2912 operand immL_FFFF() %{ 2913 predicate(n->get_long() == 0xFFFFL); 2914 match(ConL); 2915 op_cost(1); 2916 format %{ %} 2917 interface(CONST_INTER); 2918 %} 2919 2920 // Long Immediate: the value FFFFFFFF 2921 operand immL_FFFFFFFF() %{ 2922 predicate(n->get_long() == 0xFFFFFFFFL); 2923 match(ConL); 2924 op_cost(1); 2925 format %{ %} 2926 interface(CONST_INTER); 2927 %} 2928 2929 operand immL_0() %{ 2930 predicate(n->get_long() == 0L); 2931 match(ConL); 2932 op_cost(1); 2933 format %{ %} 2934 interface(CONST_INTER); 2935 %} 2936 2937 // Unsigned Long Immediate: LL-part, extended by 1s. 2938 operand uimmL_LL1() %{ 2939 predicate((n->get_long() & 0xFFFFFFFFFFFF0000L) == 0xFFFFFFFFFFFF0000L); 2940 match(ConL); 2941 op_cost(1); 2942 format %{ %} 2943 interface(CONST_INTER); 2944 %} 2945 2946 // Unsigned Long Immediate: LH-part, extended by 1s. 2947 operand uimmL_LH1() %{ 2948 predicate((n->get_long() & 0xFFFFFFFF0000FFFFL) == 0xFFFFFFFF0000FFFFL); 2949 match(ConL); 2950 op_cost(1); 2951 format %{ %} 2952 interface(CONST_INTER); 2953 %} 2954 2955 // Unsigned Long Immediate: HL-part, extended by 1s. 2956 operand uimmL_HL1() %{ 2957 predicate((n->get_long() & 0xFFFF0000FFFFFFFFL) == 0xFFFF0000FFFFFFFFL); 2958 match(ConL); 2959 op_cost(1); 2960 format %{ %} 2961 interface(CONST_INTER); 2962 %} 2963 2964 // Unsigned Long Immediate: HH-part, extended by 1s. 2965 operand uimmL_HH1() %{ 2966 predicate((n->get_long() & 0xFFFFFFFFFFFFL) == 0xFFFFFFFFFFFFL); 2967 match(ConL); 2968 op_cost(1); 2969 format %{ %} 2970 interface(CONST_INTER); 2971 %} 2972 2973 // Long Immediate: low 32-bit mask 2974 operand immL_32bits() %{ 2975 predicate(n->get_long() == 0xFFFFFFFFL); 2976 match(ConL); 2977 op_cost(1); 2978 format %{ %} 2979 interface(CONST_INTER); 2980 %} 2981 2982 //-------------------------------------- 2983 // POINTER immediate operands 2984 //-------------------------------------- 2985 2986 // Pointer Immediate: 64-bit 2987 operand immP() %{ 2988 match(ConP); 2989 op_cost(1); 2990 format %{ %} 2991 interface(CONST_INTER); 2992 %} 2993 2994 // Pointer Immediate: 32-bit 2995 operand immP32() %{ 2996 predicate(Immediate::is_uimm32(n->get_ptr())); 2997 match(ConP); 2998 op_cost(1); 2999 format %{ %} 3000 interface(CONST_INTER); 3001 %} 3002 3003 // Pointer Immediate: 16-bit 3004 operand immP16() %{ 3005 predicate(Immediate::is_uimm16(n->get_ptr())); 3006 match(ConP); 3007 op_cost(1); 3008 format %{ %} 3009 interface(CONST_INTER); 3010 %} 3011 3012 // Pointer Immediate: 8-bit 3013 operand immP8() %{ 3014 predicate(Immediate::is_uimm8(n->get_ptr())); 3015 match(ConP); 3016 op_cost(1); 3017 format %{ %} 3018 interface(CONST_INTER); 3019 %} 3020 3021 //----------------------------------- 3022 // POINTER specific values 3023 //----------------------------------- 3024 3025 // Pointer Immediate: NULL 3026 operand immP0() %{ 3027 predicate(n->get_ptr() == 0); 3028 match(ConP); 3029 op_cost(1); 3030 format %{ %} 3031 interface(CONST_INTER); 3032 %} 3033 3034 //--------------------------------------------- 3035 // NARROW POINTER immediate operands 3036 //--------------------------------------------- 3037 3038 // Narrow Pointer Immediate 3039 operand immN() %{ 3040 match(ConN); 3041 op_cost(1); 3042 format %{ %} 3043 interface(CONST_INTER); 3044 %} 3045 3046 operand immNKlass() %{ 3047 match(ConNKlass); 3048 op_cost(1); 3049 format %{ %} 3050 interface(CONST_INTER); 3051 %} 3052 3053 // Narrow Pointer Immediate 3054 operand immN8() %{ 3055 predicate(Immediate::is_uimm8(n->get_narrowcon())); 3056 match(ConN); 3057 op_cost(1); 3058 format %{ %} 3059 interface(CONST_INTER); 3060 %} 3061 3062 // Narrow NULL Pointer Immediate 3063 operand immN0() %{ 3064 predicate(n->get_narrowcon() == 0); 3065 match(ConN); 3066 op_cost(1); 3067 format %{ %} 3068 interface(CONST_INTER); 3069 %} 3070 3071 // FLOAT and DOUBLE immediate operands 3072 3073 // Double Immediate 3074 operand immD() %{ 3075 match(ConD); 3076 op_cost(1); 3077 format %{ %} 3078 interface(CONST_INTER); 3079 %} 3080 3081 // Double Immediate: +-0 3082 operand immDpm0() %{ 3083 predicate(n->getd() == 0); 3084 match(ConD); 3085 op_cost(1); 3086 format %{ %} 3087 interface(CONST_INTER); 3088 %} 3089 3090 // Double Immediate: +0 3091 operand immDp0() %{ 3092 predicate(jlong_cast(n->getd()) == 0); 3093 match(ConD); 3094 op_cost(1); 3095 format %{ %} 3096 interface(CONST_INTER); 3097 %} 3098 3099 // Float Immediate 3100 operand immF() %{ 3101 match(ConF); 3102 op_cost(1); 3103 format %{ %} 3104 interface(CONST_INTER); 3105 %} 3106 3107 // Float Immediate: +-0 3108 operand immFpm0() %{ 3109 predicate(n->getf() == 0); 3110 match(ConF); 3111 op_cost(1); 3112 format %{ %} 3113 interface(CONST_INTER); 3114 %} 3115 3116 // Float Immediate: +0 3117 operand immFp0() %{ 3118 predicate(jint_cast(n->getf()) == 0); 3119 match(ConF); 3120 op_cost(1); 3121 format %{ %} 3122 interface(CONST_INTER); 3123 %} 3124 3125 // End of Immediate Operands 3126 3127 // Integer Register Operands 3128 // Integer Register 3129 operand iRegI() %{ 3130 constraint(ALLOC_IN_RC(z_int_reg)); 3131 match(RegI); 3132 match(noArg_iRegI); 3133 match(rarg1RegI); 3134 match(rarg2RegI); 3135 match(rarg3RegI); 3136 match(rarg4RegI); 3137 match(rarg5RegI); 3138 match(noOdd_iRegI); 3139 match(revenRegI); 3140 match(roddRegI); 3141 format %{ %} 3142 interface(REG_INTER); 3143 %} 3144 3145 operand noArg_iRegI() %{ 3146 constraint(ALLOC_IN_RC(z_no_arg_int_reg)); 3147 match(RegI); 3148 format %{ %} 3149 interface(REG_INTER); 3150 %} 3151 3152 // revenRegI and roddRegI constitute and even-odd-pair. 3153 operand revenRegI() %{ 3154 constraint(ALLOC_IN_RC(z_rarg3_int_reg)); 3155 match(iRegI); 3156 format %{ %} 3157 interface(REG_INTER); 3158 %} 3159 3160 // revenRegI and roddRegI constitute and even-odd-pair. 3161 operand roddRegI() %{ 3162 constraint(ALLOC_IN_RC(z_rarg4_int_reg)); 3163 match(iRegI); 3164 format %{ %} 3165 interface(REG_INTER); 3166 %} 3167 3168 operand rarg1RegI() %{ 3169 constraint(ALLOC_IN_RC(z_rarg1_int_reg)); 3170 match(iRegI); 3171 format %{ %} 3172 interface(REG_INTER); 3173 %} 3174 3175 operand rarg2RegI() %{ 3176 constraint(ALLOC_IN_RC(z_rarg2_int_reg)); 3177 match(iRegI); 3178 format %{ %} 3179 interface(REG_INTER); 3180 %} 3181 3182 operand rarg3RegI() %{ 3183 constraint(ALLOC_IN_RC(z_rarg3_int_reg)); 3184 match(iRegI); 3185 format %{ %} 3186 interface(REG_INTER); 3187 %} 3188 3189 operand rarg4RegI() %{ 3190 constraint(ALLOC_IN_RC(z_rarg4_int_reg)); 3191 match(iRegI); 3192 format %{ %} 3193 interface(REG_INTER); 3194 %} 3195 3196 operand rarg5RegI() %{ 3197 constraint(ALLOC_IN_RC(z_rarg5_int_reg)); 3198 match(iRegI); 3199 format %{ %} 3200 interface(REG_INTER); 3201 %} 3202 3203 operand noOdd_iRegI() %{ 3204 constraint(ALLOC_IN_RC(z_no_odd_int_reg)); 3205 match(RegI); 3206 match(revenRegI); 3207 format %{ %} 3208 interface(REG_INTER); 3209 %} 3210 3211 // Pointer Register 3212 operand iRegP() %{ 3213 constraint(ALLOC_IN_RC(z_ptr_reg)); 3214 match(RegP); 3215 match(noArg_iRegP); 3216 match(rarg1RegP); 3217 match(rarg2RegP); 3218 match(rarg3RegP); 3219 match(rarg4RegP); 3220 match(rarg5RegP); 3221 match(revenRegP); 3222 match(roddRegP); 3223 format %{ %} 3224 interface(REG_INTER); 3225 %} 3226 3227 // thread operand 3228 operand threadRegP() %{ 3229 constraint(ALLOC_IN_RC(z_thread_ptr_reg)); 3230 match(RegP); 3231 format %{ "Z_THREAD" %} 3232 interface(REG_INTER); 3233 %} 3234 3235 operand noArg_iRegP() %{ 3236 constraint(ALLOC_IN_RC(z_no_arg_ptr_reg)); 3237 match(iRegP); 3238 format %{ %} 3239 interface(REG_INTER); 3240 %} 3241 3242 operand rarg1RegP() %{ 3243 constraint(ALLOC_IN_RC(z_rarg1_ptr_reg)); 3244 match(iRegP); 3245 format %{ %} 3246 interface(REG_INTER); 3247 %} 3248 3249 operand rarg2RegP() %{ 3250 constraint(ALLOC_IN_RC(z_rarg2_ptr_reg)); 3251 match(iRegP); 3252 format %{ %} 3253 interface(REG_INTER); 3254 %} 3255 3256 operand rarg3RegP() %{ 3257 constraint(ALLOC_IN_RC(z_rarg3_ptr_reg)); 3258 match(iRegP); 3259 format %{ %} 3260 interface(REG_INTER); 3261 %} 3262 3263 operand rarg4RegP() %{ 3264 constraint(ALLOC_IN_RC(z_rarg4_ptr_reg)); 3265 match(iRegP); 3266 format %{ %} 3267 interface(REG_INTER); 3268 %} 3269 3270 operand rarg5RegP() %{ 3271 constraint(ALLOC_IN_RC(z_rarg5_ptr_reg)); 3272 match(iRegP); 3273 format %{ %} 3274 interface(REG_INTER); 3275 %} 3276 3277 operand memoryRegP() %{ 3278 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3279 match(RegP); 3280 match(iRegP); 3281 match(threadRegP); 3282 format %{ %} 3283 interface(REG_INTER); 3284 %} 3285 3286 // revenRegP and roddRegP constitute and even-odd-pair. 3287 operand revenRegP() %{ 3288 constraint(ALLOC_IN_RC(z_rarg3_ptr_reg)); 3289 match(iRegP); 3290 format %{ %} 3291 interface(REG_INTER); 3292 %} 3293 3294 // revenRegP and roddRegP constitute and even-odd-pair. 3295 operand roddRegP() %{ 3296 constraint(ALLOC_IN_RC(z_rarg4_ptr_reg)); 3297 match(iRegP); 3298 format %{ %} 3299 interface(REG_INTER); 3300 %} 3301 3302 operand lock_ptr_RegP() %{ 3303 constraint(ALLOC_IN_RC(z_lock_ptr_reg)); 3304 match(RegP); 3305 format %{ %} 3306 interface(REG_INTER); 3307 %} 3308 3309 operand rscratch2RegP() %{ 3310 constraint(ALLOC_IN_RC(z_rscratch2_bits64_reg)); 3311 match(RegP); 3312 format %{ %} 3313 interface(REG_INTER); 3314 %} 3315 3316 operand iRegN() %{ 3317 constraint(ALLOC_IN_RC(z_int_reg)); 3318 match(RegN); 3319 match(noArg_iRegN); 3320 match(rarg1RegN); 3321 match(rarg2RegN); 3322 match(rarg3RegN); 3323 match(rarg4RegN); 3324 match(rarg5RegN); 3325 format %{ %} 3326 interface(REG_INTER); 3327 %} 3328 3329 operand noArg_iRegN() %{ 3330 constraint(ALLOC_IN_RC(z_no_arg_int_reg)); 3331 match(iRegN); 3332 format %{ %} 3333 interface(REG_INTER); 3334 %} 3335 3336 operand rarg1RegN() %{ 3337 constraint(ALLOC_IN_RC(z_rarg1_int_reg)); 3338 match(iRegN); 3339 format %{ %} 3340 interface(REG_INTER); 3341 %} 3342 3343 operand rarg2RegN() %{ 3344 constraint(ALLOC_IN_RC(z_rarg2_int_reg)); 3345 match(iRegN); 3346 format %{ %} 3347 interface(REG_INTER); 3348 %} 3349 3350 operand rarg3RegN() %{ 3351 constraint(ALLOC_IN_RC(z_rarg3_int_reg)); 3352 match(iRegN); 3353 format %{ %} 3354 interface(REG_INTER); 3355 %} 3356 3357 operand rarg4RegN() %{ 3358 constraint(ALLOC_IN_RC(z_rarg4_int_reg)); 3359 match(iRegN); 3360 format %{ %} 3361 interface(REG_INTER); 3362 %} 3363 3364 operand rarg5RegN() %{ 3365 constraint(ALLOC_IN_RC(z_rarg5_ptrN_reg)); 3366 match(iRegN); 3367 format %{ %} 3368 interface(REG_INTER); 3369 %} 3370 3371 // Long Register 3372 operand iRegL() %{ 3373 constraint(ALLOC_IN_RC(z_long_reg)); 3374 match(RegL); 3375 match(revenRegL); 3376 match(roddRegL); 3377 match(rarg1RegL); 3378 match(rarg5RegL); 3379 format %{ %} 3380 interface(REG_INTER); 3381 %} 3382 3383 // revenRegL and roddRegL constitute and even-odd-pair. 3384 operand revenRegL() %{ 3385 constraint(ALLOC_IN_RC(z_rarg3_long_reg)); 3386 match(iRegL); 3387 format %{ %} 3388 interface(REG_INTER); 3389 %} 3390 3391 // revenRegL and roddRegL constitute and even-odd-pair. 3392 operand roddRegL() %{ 3393 constraint(ALLOC_IN_RC(z_rarg4_long_reg)); 3394 match(iRegL); 3395 format %{ %} 3396 interface(REG_INTER); 3397 %} 3398 3399 operand rarg1RegL() %{ 3400 constraint(ALLOC_IN_RC(z_rarg1_long_reg)); 3401 match(iRegL); 3402 format %{ %} 3403 interface(REG_INTER); 3404 %} 3405 3406 operand rarg5RegL() %{ 3407 constraint(ALLOC_IN_RC(z_rarg5_long_reg)); 3408 match(iRegL); 3409 format %{ %} 3410 interface(REG_INTER); 3411 %} 3412 3413 // Condition Code Flag Registers 3414 operand flagsReg() %{ 3415 constraint(ALLOC_IN_RC(z_condition_reg)); 3416 match(RegFlags); 3417 format %{ "CR" %} 3418 interface(REG_INTER); 3419 %} 3420 3421 // Condition Code Flag Registers for rules with result tuples 3422 operand TD_flagsReg() %{ 3423 constraint(ALLOC_IN_RC(z_condition_reg)); 3424 match(RegFlags); 3425 format %{ "CR" %} 3426 interface(REG_TUPLE_DEST_INTER); 3427 %} 3428 3429 operand regD() %{ 3430 constraint(ALLOC_IN_RC(z_dbl_reg)); 3431 match(RegD); 3432 format %{ %} 3433 interface(REG_INTER); 3434 %} 3435 3436 operand rscratchRegD() %{ 3437 constraint(ALLOC_IN_RC(z_rscratch1_dbl_reg)); 3438 match(RegD); 3439 format %{ %} 3440 interface(REG_INTER); 3441 %} 3442 3443 operand regF() %{ 3444 constraint(ALLOC_IN_RC(z_flt_reg)); 3445 match(RegF); 3446 format %{ %} 3447 interface(REG_INTER); 3448 %} 3449 3450 operand rscratchRegF() %{ 3451 constraint(ALLOC_IN_RC(z_rscratch1_flt_reg)); 3452 match(RegF); 3453 format %{ %} 3454 interface(REG_INTER); 3455 %} 3456 3457 // Special Registers 3458 3459 // Method Register 3460 operand inline_cache_regP(iRegP reg) %{ 3461 constraint(ALLOC_IN_RC(z_r9_regP)); // inline_cache_reg 3462 match(reg); 3463 format %{ %} 3464 interface(REG_INTER); 3465 %} 3466 3467 operand compiler_method_oop_regP(iRegP reg) %{ 3468 constraint(ALLOC_IN_RC(z_r1_RegP)); // compiler_method_oop_reg 3469 match(reg); 3470 format %{ %} 3471 interface(REG_INTER); 3472 %} 3473 3474 operand interpreter_method_oop_regP(iRegP reg) %{ 3475 constraint(ALLOC_IN_RC(z_r9_regP)); // interpreter_method_oop_reg 3476 match(reg); 3477 format %{ %} 3478 interface(REG_INTER); 3479 %} 3480 3481 // Operands to remove register moves in unscaled mode. 3482 // Match read/write registers with an EncodeP node if neither shift nor add are required. 3483 operand iRegP2N(iRegP reg) %{ 3484 predicate(Universe::narrow_oop_shift() == 0 && _leaf->as_EncodeP()->in(0) == NULL); 3485 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3486 match(EncodeP reg); 3487 format %{ "$reg" %} 3488 interface(REG_INTER) 3489 %} 3490 3491 operand iRegN2P(iRegN reg) %{ 3492 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0 && 3493 _leaf->as_DecodeN()->in(0) == NULL); 3494 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3495 match(DecodeN reg); 3496 format %{ "$reg" %} 3497 interface(REG_INTER) 3498 %} 3499 3500 3501 //----------Complex Operands--------------------------------------------------- 3502 3503 // Indirect Memory Reference 3504 operand indirect(memoryRegP base) %{ 3505 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3506 match(base); 3507 op_cost(1); 3508 format %{ "#0[,$base]" %} 3509 interface(MEMORY_INTER) %{ 3510 base($base); 3511 index(0xffffFFFF); // noreg 3512 scale(0x0); 3513 disp(0x0); 3514 %} 3515 %} 3516 3517 // Indirect with Offset (long) 3518 operand indOffset20(memoryRegP base, immL20 offset) %{ 3519 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3520 match(AddP base offset); 3521 op_cost(1); 3522 format %{ "$offset[,$base]" %} 3523 interface(MEMORY_INTER) %{ 3524 base($base); 3525 index(0xffffFFFF); // noreg 3526 scale(0x0); 3527 disp($offset); 3528 %} 3529 %} 3530 3531 operand indOffset20Narrow(iRegN base, immL20 offset) %{ 3532 predicate(Matcher::narrow_oop_use_complex_address()); 3533 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3534 match(AddP (DecodeN base) offset); 3535 op_cost(1); 3536 format %{ "$offset[,$base]" %} 3537 interface(MEMORY_INTER) %{ 3538 base($base); 3539 index(0xffffFFFF); // noreg 3540 scale(0x0); 3541 disp($offset); 3542 %} 3543 %} 3544 3545 // Indirect with Offset (short) 3546 operand indOffset12(memoryRegP base, uimmL12 offset) %{ 3547 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3548 match(AddP base offset); 3549 op_cost(1); 3550 format %{ "$offset[[,$base]]" %} 3551 interface(MEMORY_INTER) %{ 3552 base($base); 3553 index(0xffffFFFF); // noreg 3554 scale(0x0); 3555 disp($offset); 3556 %} 3557 %} 3558 3559 operand indOffset12Narrow(iRegN base, uimmL12 offset) %{ 3560 predicate(Matcher::narrow_oop_use_complex_address()); 3561 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3562 match(AddP (DecodeN base) offset); 3563 op_cost(1); 3564 format %{ "$offset[[,$base]]" %} 3565 interface(MEMORY_INTER) %{ 3566 base($base); 3567 index(0xffffFFFF); // noreg 3568 scale(0x0); 3569 disp($offset); 3570 %} 3571 %} 3572 3573 // Indirect with Register Index 3574 operand indIndex(memoryRegP base, iRegL index) %{ 3575 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3576 match(AddP base index); 3577 op_cost(1); 3578 format %{ "#0[($index,$base)]" %} 3579 interface(MEMORY_INTER) %{ 3580 base($base); 3581 index($index); 3582 scale(0x0); 3583 disp(0x0); 3584 %} 3585 %} 3586 3587 // Indirect with Offset (long) and index 3588 operand indOffset20index(memoryRegP base, immL20 offset, iRegL index) %{ 3589 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3590 match(AddP (AddP base index) offset); 3591 op_cost(1); 3592 format %{ "$offset[($index,$base)]" %} 3593 interface(MEMORY_INTER) %{ 3594 base($base); 3595 index($index); 3596 scale(0x0); 3597 disp($offset); 3598 %} 3599 %} 3600 3601 operand indOffset20indexNarrow(iRegN base, immL20 offset, iRegL index) %{ 3602 predicate(Matcher::narrow_oop_use_complex_address()); 3603 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3604 match(AddP (AddP (DecodeN base) index) offset); 3605 op_cost(1); 3606 format %{ "$offset[($index,$base)]" %} 3607 interface(MEMORY_INTER) %{ 3608 base($base); 3609 index($index); 3610 scale(0x0); 3611 disp($offset); 3612 %} 3613 %} 3614 3615 // Indirect with Offset (short) and index 3616 operand indOffset12index(memoryRegP base, uimmL12 offset, iRegL index) %{ 3617 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3618 match(AddP (AddP base index) offset); 3619 op_cost(1); 3620 format %{ "$offset[[($index,$base)]]" %} 3621 interface(MEMORY_INTER) %{ 3622 base($base); 3623 index($index); 3624 scale(0x0); 3625 disp($offset); 3626 %} 3627 %} 3628 3629 operand indOffset12indexNarrow(iRegN base, uimmL12 offset, iRegL index) %{ 3630 predicate(Matcher::narrow_oop_use_complex_address()); 3631 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3632 match(AddP (AddP (DecodeN base) index) offset); 3633 op_cost(1); 3634 format %{ "$offset[[($index,$base)]]" %} 3635 interface(MEMORY_INTER) %{ 3636 base($base); 3637 index($index); 3638 scale(0x0); 3639 disp($offset); 3640 %} 3641 %} 3642 3643 //----------Special Memory Operands-------------------------------------------- 3644 3645 // Stack Slot Operand 3646 // This operand is used for loading and storing temporary values on 3647 // the stack where a match requires a value to flow through memory. 3648 operand stackSlotI(sRegI reg) %{ 3649 constraint(ALLOC_IN_RC(stack_slots)); 3650 op_cost(1); 3651 format %{ "[$reg(stackSlotI)]" %} 3652 interface(MEMORY_INTER) %{ 3653 base(0xf); // Z_SP 3654 index(0xffffFFFF); // noreg 3655 scale(0x0); 3656 disp($reg); // stack offset 3657 %} 3658 %} 3659 3660 operand stackSlotP(sRegP reg) %{ 3661 constraint(ALLOC_IN_RC(stack_slots)); 3662 op_cost(1); 3663 format %{ "[$reg(stackSlotP)]" %} 3664 interface(MEMORY_INTER) %{ 3665 base(0xf); // Z_SP 3666 index(0xffffFFFF); // noreg 3667 scale(0x0); 3668 disp($reg); // Stack Offset 3669 %} 3670 %} 3671 3672 operand stackSlotF(sRegF reg) %{ 3673 constraint(ALLOC_IN_RC(stack_slots)); 3674 op_cost(1); 3675 format %{ "[$reg(stackSlotF)]" %} 3676 interface(MEMORY_INTER) %{ 3677 base(0xf); // Z_SP 3678 index(0xffffFFFF); // noreg 3679 scale(0x0); 3680 disp($reg); // Stack Offset 3681 %} 3682 %} 3683 3684 operand stackSlotD(sRegD reg) %{ 3685 constraint(ALLOC_IN_RC(stack_slots)); 3686 op_cost(1); 3687 //match(RegD); 3688 format %{ "[$reg(stackSlotD)]" %} 3689 interface(MEMORY_INTER) %{ 3690 base(0xf); // Z_SP 3691 index(0xffffFFFF); // noreg 3692 scale(0x0); 3693 disp($reg); // Stack Offset 3694 %} 3695 %} 3696 3697 operand stackSlotL(sRegL reg) %{ 3698 constraint(ALLOC_IN_RC(stack_slots)); 3699 op_cost(1); //match(RegL); 3700 format %{ "[$reg(stackSlotL)]" %} 3701 interface(MEMORY_INTER) %{ 3702 base(0xf); // Z_SP 3703 index(0xffffFFFF); // noreg 3704 scale(0x0); 3705 disp($reg); // Stack Offset 3706 %} 3707 %} 3708 3709 // Operands for expressing Control Flow 3710 // NOTE: Label is a predefined operand which should not be redefined in 3711 // the AD file. It is generically handled within the ADLC. 3712 3713 //----------Conditional Branch Operands---------------------------------------- 3714 // Comparison Op - This is the operation of the comparison, and is limited to 3715 // the following set of codes: 3716 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 3717 // 3718 // Other attributes of the comparison, such as unsignedness, are specified 3719 // by the comparison instruction that sets a condition code flags register. 3720 // That result is represented by a flags operand whose subtype is appropriate 3721 // to the unsignedness (etc.) of the comparison. 3722 // 3723 // Later, the instruction which matches both the Comparison Op (a Bool) and 3724 // the flags (produced by the Cmp) specifies the coding of the comparison op 3725 // by matching a specific subtype of Bool operand below. 3726 3727 // INT cmpOps for CompareAndBranch and CompareAndTrap instructions should not 3728 // have mask bit #3 set. 3729 operand cmpOpT() %{ 3730 match(Bool); 3731 format %{ "" %} 3732 interface(COND_INTER) %{ 3733 equal(0x8); // Assembler::bcondEqual 3734 not_equal(0x6); // Assembler::bcondNotEqual 3735 less(0x4); // Assembler::bcondLow 3736 greater_equal(0xa); // Assembler::bcondNotLow 3737 less_equal(0xc); // Assembler::bcondNotHigh 3738 greater(0x2); // Assembler::bcondHigh 3739 overflow(0x1); // Assembler::bcondOverflow 3740 no_overflow(0xe); // Assembler::bcondNotOverflow 3741 %} 3742 %} 3743 3744 // When used for floating point comparisons: unordered is treated as less. 3745 operand cmpOpF() %{ 3746 match(Bool); 3747 format %{ "" %} 3748 interface(COND_INTER) %{ 3749 equal(0x8); 3750 not_equal(0x7); // Includes 'unordered'. 3751 less(0x5); // Includes 'unordered'. 3752 greater_equal(0xa); 3753 less_equal(0xd); // Includes 'unordered'. 3754 greater(0x2); 3755 overflow(0x0); // Not meaningful on z/Architecture. 3756 no_overflow(0x0); // leave unchanged (zero) therefore 3757 %} 3758 %} 3759 3760 // "Regular" cmpOp for int comparisons, includes bit #3 (overflow). 3761 operand cmpOp() %{ 3762 match(Bool); 3763 format %{ "" %} 3764 interface(COND_INTER) %{ 3765 equal(0x8); 3766 not_equal(0x7); // Includes 'unordered'. 3767 less(0x5); // Includes 'unordered'. 3768 greater_equal(0xa); 3769 less_equal(0xd); // Includes 'unordered'. 3770 greater(0x2); 3771 overflow(0x1); // Assembler::bcondOverflow 3772 no_overflow(0xe); // Assembler::bcondNotOverflow 3773 %} 3774 %} 3775 3776 //----------OPERAND CLASSES---------------------------------------------------- 3777 // Operand Classes are groups of operands that are used to simplify 3778 // instruction definitions by not requiring the AD writer to specify 3779 // seperate instructions for every form of operand when the 3780 // instruction accepts multiple operand types with the same basic 3781 // encoding and format. The classic case of this is memory operands. 3782 // Indirect is not included since its use is limited to Compare & Swap 3783 3784 // Most general memory operand, allows base, index, and long displacement. 3785 opclass memory(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow); 3786 opclass memoryRXY(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow); 3787 3788 // General memory operand, allows base, index, and short displacement. 3789 opclass memoryRX(indirect, indIndex, indOffset12, indOffset12Narrow, indOffset12index, indOffset12indexNarrow); 3790 3791 // Memory operand, allows only base and long displacement. 3792 opclass memoryRSY(indirect, indOffset20, indOffset20Narrow); 3793 3794 // Memory operand, allows only base and short displacement. 3795 opclass memoryRS(indirect, indOffset12, indOffset12Narrow); 3796 3797 // Operand classes to match encode and decode. 3798 opclass iRegN_P2N(iRegN); 3799 opclass iRegP_N2P(iRegP); 3800 3801 3802 //----------PIPELINE----------------------------------------------------------- 3803 pipeline %{ 3804 3805 //----------ATTRIBUTES--------------------------------------------------------- 3806 attributes %{ 3807 // z/Architecture instructions are of length 2, 4, or 6 bytes. 3808 variable_size_instructions; 3809 instruction_unit_size = 2; 3810 3811 // Meaningless on z/Architecture. 3812 max_instructions_per_bundle = 1; 3813 3814 // The z/Architecture processor fetches 64 bytes... 3815 instruction_fetch_unit_size = 64; 3816 3817 // ...in one line. 3818 instruction_fetch_units = 1 3819 %} 3820 3821 //----------RESOURCES---------------------------------------------------------- 3822 // Resources are the functional units available to the machine. 3823 resources( 3824 Z_BR, // branch unit 3825 Z_CR, // condition unit 3826 Z_FX1, // integer arithmetic unit 1 3827 Z_FX2, // integer arithmetic unit 2 3828 Z_LDST1, // load/store unit 1 3829 Z_LDST2, // load/store unit 2 3830 Z_FP1, // float arithmetic unit 1 3831 Z_FP2, // float arithmetic unit 2 3832 Z_LDST = Z_LDST1 | Z_LDST2, 3833 Z_FX = Z_FX1 | Z_FX2, 3834 Z_FP = Z_FP1 | Z_FP2 3835 ); 3836 3837 //----------PIPELINE DESCRIPTION----------------------------------------------- 3838 // Pipeline Description specifies the stages in the machine's pipeline. 3839 pipe_desc( 3840 // TODO: adapt 3841 Z_IF, // instruction fetch 3842 Z_IC, 3843 Z_D0, // decode 3844 Z_D1, // decode 3845 Z_D2, // decode 3846 Z_D3, // decode 3847 Z_Xfer1, 3848 Z_GD, // group definition 3849 Z_MP, // map 3850 Z_ISS, // issue 3851 Z_RF, // resource fetch 3852 Z_EX1, // execute (all units) 3853 Z_EX2, // execute (FP, LDST) 3854 Z_EX3, // execute (FP, LDST) 3855 Z_EX4, // execute (FP) 3856 Z_EX5, // execute (FP) 3857 Z_EX6, // execute (FP) 3858 Z_WB, // write back 3859 Z_Xfer2, 3860 Z_CP 3861 ); 3862 3863 //----------PIPELINE CLASSES--------------------------------------------------- 3864 // Pipeline Classes describe the stages in which input and output are 3865 // referenced by the hardware pipeline. 3866 3867 // Providing the `ins_pipe' declarations in the instruction 3868 // specifications seems to be of little use. So we use 3869 // `pipe_class_dummy' for all our instructions at present. 3870 pipe_class pipe_class_dummy() %{ 3871 single_instruction; 3872 fixed_latency(4); 3873 %} 3874 3875 // SIGTRAP based implicit range checks in compiled code. 3876 // Currently, no pipe classes are used on z/Architecture. 3877 pipe_class pipe_class_trap() %{ 3878 single_instruction; 3879 %} 3880 3881 pipe_class pipe_class_fx_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 3882 single_instruction; 3883 dst : Z_EX1(write); 3884 src1 : Z_RF(read); 3885 src2 : Z_RF(read); 3886 Z_FX : Z_RF; 3887 %} 3888 3889 pipe_class pipe_class_ldst(iRegP dst, memory mem) %{ 3890 single_instruction; 3891 mem : Z_RF(read); 3892 dst : Z_WB(write); 3893 Z_LDST : Z_RF; 3894 %} 3895 3896 define %{ 3897 MachNop = pipe_class_dummy; 3898 %} 3899 3900 %} 3901 3902 //----------INSTRUCTIONS------------------------------------------------------- 3903 3904 //---------- Chain stack slots between similar types -------- 3905 3906 // Load integer from stack slot. 3907 instruct stkI_to_regI(iRegI dst, stackSlotI src) %{ 3908 match(Set dst src); 3909 ins_cost(MEMORY_REF_COST); 3910 // TODO: s390 port size(FIXED_SIZE); 3911 format %{ "L $dst,$src\t # stk reload int" %} 3912 opcode(L_ZOPC); 3913 ins_encode(z_form_rt_mem(dst, src)); 3914 ins_pipe(pipe_class_dummy); 3915 %} 3916 3917 // Store integer to stack slot. 3918 instruct regI_to_stkI(stackSlotI dst, iRegI src) %{ 3919 match(Set dst src); 3920 ins_cost(MEMORY_REF_COST); 3921 // TODO: s390 port size(FIXED_SIZE); 3922 format %{ "ST $src,$dst\t # stk spill int" %} 3923 opcode(ST_ZOPC); 3924 ins_encode(z_form_rt_mem(src, dst)); // rs=rt 3925 ins_pipe(pipe_class_dummy); 3926 %} 3927 3928 // Load long from stack slot. 3929 instruct stkL_to_regL(iRegL dst, stackSlotL src) %{ 3930 match(Set dst src); 3931 ins_cost(MEMORY_REF_COST); 3932 // TODO: s390 port size(FIXED_SIZE); 3933 format %{ "LG $dst,$src\t # stk reload long" %} 3934 opcode(LG_ZOPC); 3935 ins_encode(z_form_rt_mem(dst, src)); 3936 ins_pipe(pipe_class_dummy); 3937 %} 3938 3939 // Store long to stack slot. 3940 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ 3941 match(Set dst src); 3942 ins_cost(MEMORY_REF_COST); 3943 size(6); 3944 format %{ "STG $src,$dst\t # stk spill long" %} 3945 opcode(STG_ZOPC); 3946 ins_encode(z_form_rt_mem(src, dst)); // rs=rt 3947 ins_pipe(pipe_class_dummy); 3948 %} 3949 3950 // Load pointer from stack slot, 64-bit encoding. 3951 instruct stkP_to_regP(iRegP dst, stackSlotP src) %{ 3952 match(Set dst src); 3953 ins_cost(MEMORY_REF_COST); 3954 // TODO: s390 port size(FIXED_SIZE); 3955 format %{ "LG $dst,$src\t # stk reload ptr" %} 3956 opcode(LG_ZOPC); 3957 ins_encode(z_form_rt_mem(dst, src)); 3958 ins_pipe(pipe_class_dummy); 3959 %} 3960 3961 // Store pointer to stack slot. 3962 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 3963 match(Set dst src); 3964 ins_cost(MEMORY_REF_COST); 3965 // TODO: s390 port size(FIXED_SIZE); 3966 format %{ "STG $src,$dst\t # stk spill ptr" %} 3967 opcode(STG_ZOPC); 3968 ins_encode(z_form_rt_mem(src, dst)); // rs=rt 3969 ins_pipe(pipe_class_dummy); 3970 %} 3971 3972 // Float types 3973 3974 // Load float value from stack slot. 3975 instruct stkF_to_regF(regF dst, stackSlotF src) %{ 3976 match(Set dst src); 3977 ins_cost(MEMORY_REF_COST); 3978 size(4); 3979 format %{ "LE(Y) $dst,$src\t # stk reload float" %} 3980 opcode(LE_ZOPC); 3981 ins_encode(z_form_rt_mem(dst, src)); 3982 ins_pipe(pipe_class_dummy); 3983 %} 3984 3985 // Store float value to stack slot. 3986 instruct regF_to_stkF(stackSlotF dst, regF src) %{ 3987 match(Set dst src); 3988 ins_cost(MEMORY_REF_COST); 3989 size(4); 3990 format %{ "STE(Y) $src,$dst\t # stk spill float" %} 3991 opcode(STE_ZOPC); 3992 ins_encode(z_form_rt_mem(src, dst)); 3993 ins_pipe(pipe_class_dummy); 3994 %} 3995 3996 // Load double value from stack slot. 3997 instruct stkD_to_regD(regD dst, stackSlotD src) %{ 3998 match(Set dst src); 3999 ins_cost(MEMORY_REF_COST); 4000 // TODO: s390 port size(FIXED_SIZE); 4001 format %{ "LD(Y) $dst,$src\t # stk reload double" %} 4002 opcode(LD_ZOPC); 4003 ins_encode(z_form_rt_mem(dst, src)); 4004 ins_pipe(pipe_class_dummy); 4005 %} 4006 4007 // Store double value to stack slot. 4008 instruct regD_to_stkD(stackSlotD dst, regD src) %{ 4009 match(Set dst src); 4010 ins_cost(MEMORY_REF_COST); 4011 size(4); 4012 format %{ "STD(Y) $src,$dst\t # stk spill double" %} 4013 opcode(STD_ZOPC); 4014 ins_encode(z_form_rt_mem(src, dst)); 4015 ins_pipe(pipe_class_dummy); 4016 %} 4017 4018 //----------Load/Store/Move Instructions--------------------------------------- 4019 4020 //----------Load Instructions-------------------------------------------------- 4021 4022 //------------------ 4023 // MEMORY 4024 //------------------ 4025 4026 // BYTE 4027 // Load Byte (8bit signed) 4028 instruct loadB(iRegI dst, memory mem) %{ 4029 match(Set dst (LoadB mem)); 4030 ins_cost(MEMORY_REF_COST); 4031 size(Z_DISP3_SIZE); 4032 format %{ "LB $dst, $mem\t # sign-extend byte to int" %} 4033 opcode(LB_ZOPC, LB_ZOPC); 4034 ins_encode(z_form_rt_mem_opt(dst, mem)); 4035 ins_pipe(pipe_class_dummy); 4036 %} 4037 4038 // Load Byte (8bit signed) 4039 instruct loadB2L(iRegL dst, memory mem) %{ 4040 match(Set dst (ConvI2L (LoadB mem))); 4041 ins_cost(MEMORY_REF_COST); 4042 size(Z_DISP3_SIZE); 4043 format %{ "LGB $dst, $mem\t # sign-extend byte to long" %} 4044 opcode(LGB_ZOPC, LGB_ZOPC); 4045 ins_encode(z_form_rt_mem_opt(dst, mem)); 4046 ins_pipe(pipe_class_dummy); 4047 %} 4048 4049 // Load Unsigned Byte (8bit UNsigned) into an int reg. 4050 instruct loadUB(iRegI dst, memory mem) %{ 4051 match(Set dst (LoadUB mem)); 4052 ins_cost(MEMORY_REF_COST); 4053 size(Z_DISP3_SIZE); 4054 format %{ "LLGC $dst,$mem\t # zero-extend byte to int" %} 4055 opcode(LLGC_ZOPC, LLGC_ZOPC); 4056 ins_encode(z_form_rt_mem_opt(dst, mem)); 4057 ins_pipe(pipe_class_dummy); 4058 %} 4059 4060 // Load Unsigned Byte (8bit UNsigned) into a Long Register. 4061 instruct loadUB2L(iRegL dst, memory mem) %{ 4062 match(Set dst (ConvI2L (LoadUB mem))); 4063 ins_cost(MEMORY_REF_COST); 4064 size(Z_DISP3_SIZE); 4065 format %{ "LLGC $dst,$mem\t # zero-extend byte to long" %} 4066 opcode(LLGC_ZOPC, LLGC_ZOPC); 4067 ins_encode(z_form_rt_mem_opt(dst, mem)); 4068 ins_pipe(pipe_class_dummy); 4069 %} 4070 4071 // CHAR/SHORT 4072 4073 // Load Short (16bit signed) 4074 instruct loadS(iRegI dst, memory mem) %{ 4075 match(Set dst (LoadS mem)); 4076 ins_cost(MEMORY_REF_COST); 4077 size(Z_DISP_SIZE); 4078 format %{ "LH(Y) $dst,$mem\t # sign-extend short to int" %} 4079 opcode(LHY_ZOPC, LH_ZOPC); 4080 ins_encode(z_form_rt_mem_opt(dst, mem)); 4081 ins_pipe(pipe_class_dummy); 4082 %} 4083 4084 // Load Short (16bit signed) 4085 instruct loadS2L(iRegL dst, memory mem) %{ 4086 match(Set dst (ConvI2L (LoadS mem))); 4087 ins_cost(MEMORY_REF_COST); 4088 size(Z_DISP3_SIZE); 4089 format %{ "LGH $dst,$mem\t # sign-extend short to long" %} 4090 opcode(LGH_ZOPC, LGH_ZOPC); 4091 ins_encode(z_form_rt_mem_opt(dst, mem)); 4092 ins_pipe(pipe_class_dummy); 4093 %} 4094 4095 // Load Char (16bit Unsigned) 4096 instruct loadUS(iRegI dst, memory mem) %{ 4097 match(Set dst (LoadUS mem)); 4098 ins_cost(MEMORY_REF_COST); 4099 size(Z_DISP3_SIZE); 4100 format %{ "LLGH $dst,$mem\t # zero-extend short to int" %} 4101 opcode(LLGH_ZOPC, LLGH_ZOPC); 4102 ins_encode(z_form_rt_mem_opt(dst, mem)); 4103 ins_pipe(pipe_class_dummy); 4104 %} 4105 4106 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register. 4107 instruct loadUS2L(iRegL dst, memory mem) %{ 4108 match(Set dst (ConvI2L (LoadUS mem))); 4109 ins_cost(MEMORY_REF_COST); 4110 size(Z_DISP3_SIZE); 4111 format %{ "LLGH $dst,$mem\t # zero-extend short to long" %} 4112 opcode(LLGH_ZOPC, LLGH_ZOPC); 4113 ins_encode(z_form_rt_mem_opt(dst, mem)); 4114 ins_pipe(pipe_class_dummy); 4115 %} 4116 4117 // INT 4118 4119 // Load Integer 4120 instruct loadI(iRegI dst, memory mem) %{ 4121 match(Set dst (LoadI mem)); 4122 ins_cost(MEMORY_REF_COST); 4123 size(Z_DISP_SIZE); 4124 format %{ "L(Y) $dst,$mem\t #" %} 4125 opcode(LY_ZOPC, L_ZOPC); 4126 ins_encode(z_form_rt_mem_opt(dst, mem)); 4127 ins_pipe(pipe_class_dummy); 4128 %} 4129 4130 // Load and convert to long. 4131 instruct loadI2L(iRegL dst, memory mem) %{ 4132 match(Set dst (ConvI2L (LoadI mem))); 4133 ins_cost(MEMORY_REF_COST); 4134 size(Z_DISP3_SIZE); 4135 format %{ "LGF $dst,$mem\t #" %} 4136 opcode(LGF_ZOPC, LGF_ZOPC); 4137 ins_encode(z_form_rt_mem_opt(dst, mem)); 4138 ins_pipe(pipe_class_dummy); 4139 %} 4140 4141 // Load Unsigned Integer into a Long Register 4142 instruct loadUI2L(iRegL dst, memory mem, immL_FFFFFFFF mask) %{ 4143 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); 4144 ins_cost(MEMORY_REF_COST); 4145 size(Z_DISP3_SIZE); 4146 format %{ "LLGF $dst,$mem\t # zero-extend int to long" %} 4147 opcode(LLGF_ZOPC, LLGF_ZOPC); 4148 ins_encode(z_form_rt_mem_opt(dst, mem)); 4149 ins_pipe(pipe_class_dummy); 4150 %} 4151 4152 // range = array length (=jint) 4153 // Load Range 4154 instruct loadRange(iRegI dst, memory mem) %{ 4155 match(Set dst (LoadRange mem)); 4156 ins_cost(MEMORY_REF_COST); 4157 size(Z_DISP_SIZE); 4158 format %{ "L(Y) $dst,$mem\t # range" %} 4159 opcode(LY_ZOPC, L_ZOPC); 4160 ins_encode(z_form_rt_mem_opt(dst, mem)); 4161 ins_pipe(pipe_class_dummy); 4162 %} 4163 4164 // LONG 4165 4166 // Load Long - aligned 4167 instruct loadL(iRegL dst, memory mem) %{ 4168 match(Set dst (LoadL mem)); 4169 ins_cost(MEMORY_REF_COST); 4170 size(Z_DISP3_SIZE); 4171 format %{ "LG $dst,$mem\t # long" %} 4172 opcode(LG_ZOPC, LG_ZOPC); 4173 ins_encode(z_form_rt_mem_opt(dst, mem)); 4174 ins_pipe(pipe_class_dummy); 4175 %} 4176 4177 // Load Long - UNaligned 4178 instruct loadL_unaligned(iRegL dst, memory mem) %{ 4179 match(Set dst (LoadL_unaligned mem)); 4180 ins_cost(MEMORY_REF_COST); 4181 size(Z_DISP3_SIZE); 4182 format %{ "LG $dst,$mem\t # unaligned long" %} 4183 opcode(LG_ZOPC, LG_ZOPC); 4184 ins_encode(z_form_rt_mem_opt(dst, mem)); 4185 ins_pipe(pipe_class_dummy); 4186 %} 4187 4188 4189 // PTR 4190 4191 // Load Pointer 4192 instruct loadP(iRegP dst, memory mem) %{ 4193 match(Set dst (LoadP mem)); 4194 ins_cost(MEMORY_REF_COST); 4195 size(Z_DISP3_SIZE); 4196 format %{ "LG $dst,$mem\t # ptr" %} 4197 opcode(LG_ZOPC, LG_ZOPC); 4198 ins_encode(z_form_rt_mem_opt(dst, mem)); 4199 ins_pipe(pipe_class_dummy); 4200 %} 4201 4202 // LoadP + CastP2L 4203 instruct castP2X_loadP(iRegL dst, memory mem) %{ 4204 match(Set dst (CastP2X (LoadP mem))); 4205 ins_cost(MEMORY_REF_COST); 4206 size(Z_DISP3_SIZE); 4207 format %{ "LG $dst,$mem\t # ptr + p2x" %} 4208 opcode(LG_ZOPC, LG_ZOPC); 4209 ins_encode(z_form_rt_mem_opt(dst, mem)); 4210 ins_pipe(pipe_class_dummy); 4211 %} 4212 4213 // Load Klass Pointer 4214 instruct loadKlass(iRegP dst, memory mem) %{ 4215 match(Set dst (LoadKlass mem)); 4216 ins_cost(MEMORY_REF_COST); 4217 size(Z_DISP3_SIZE); 4218 format %{ "LG $dst,$mem\t # klass ptr" %} 4219 opcode(LG_ZOPC, LG_ZOPC); 4220 ins_encode(z_form_rt_mem_opt(dst, mem)); 4221 ins_pipe(pipe_class_dummy); 4222 %} 4223 4224 instruct loadTOC(iRegL dst) %{ 4225 effect(DEF dst); 4226 ins_cost(DEFAULT_COST); 4227 // TODO: s390 port size(FIXED_SIZE); 4228 // TODO: check why this attribute causes many unnecessary rematerializations. 4229 // 4230 // The graphs I saw just had high register pressure. Further the 4231 // register TOC is loaded to is overwritten by the constant short 4232 // after. Here something as round robin register allocation might 4233 // help. But rematerializing seems not to hurt, jack even seems to 4234 // improve slightly. 4235 // 4236 // Without this flag we get spill-split recycle sanity check 4237 // failures in 4238 // spec.benchmarks._228_jack.NfaState::GenerateCode. This happens in 4239 // a block with three loadConP_dynTOC nodes and a tlsLoadP. The 4240 // tlsLoadP has a huge amount of outs and forces the TOC down to the 4241 // stack. Later tlsLoadP is rematerialized, leaving the register 4242 // allocator with TOC on the stack and a badly placed reload. 4243 ins_should_rematerialize(true); 4244 format %{ "LARL $dst, &constant_pool\t; load dynTOC" %} 4245 ins_encode %{ __ load_toc($dst$$Register); %} 4246 ins_pipe(pipe_class_dummy); 4247 %} 4248 4249 // FLOAT 4250 4251 // Load Float 4252 instruct loadF(regF dst, memory mem) %{ 4253 match(Set dst (LoadF mem)); 4254 ins_cost(MEMORY_REF_COST); 4255 size(Z_DISP_SIZE); 4256 format %{ "LE(Y) $dst,$mem" %} 4257 opcode(LEY_ZOPC, LE_ZOPC); 4258 ins_encode(z_form_rt_mem_opt(dst, mem)); 4259 ins_pipe(pipe_class_dummy); 4260 %} 4261 4262 // DOUBLE 4263 4264 // Load Double 4265 instruct loadD(regD dst, memory mem) %{ 4266 match(Set dst (LoadD mem)); 4267 ins_cost(MEMORY_REF_COST); 4268 size(Z_DISP_SIZE); 4269 format %{ "LD(Y) $dst,$mem" %} 4270 opcode(LDY_ZOPC, LD_ZOPC); 4271 ins_encode(z_form_rt_mem_opt(dst, mem)); 4272 ins_pipe(pipe_class_dummy); 4273 %} 4274 4275 // Load Double - UNaligned 4276 instruct loadD_unaligned(regD dst, memory mem) %{ 4277 match(Set dst (LoadD_unaligned mem)); 4278 ins_cost(MEMORY_REF_COST); 4279 size(Z_DISP_SIZE); 4280 format %{ "LD(Y) $dst,$mem" %} 4281 opcode(LDY_ZOPC, LD_ZOPC); 4282 ins_encode(z_form_rt_mem_opt(dst, mem)); 4283 ins_pipe(pipe_class_dummy); 4284 %} 4285 4286 4287 //---------------------- 4288 // IMMEDIATES 4289 //---------------------- 4290 4291 instruct loadConI(iRegI dst, immI src) %{ 4292 match(Set dst src); 4293 ins_cost(DEFAULT_COST); 4294 size(6); 4295 format %{ "LGFI $dst,$src\t # (int)" %} 4296 ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost. 4297 ins_pipe(pipe_class_dummy); 4298 %} 4299 4300 instruct loadConI16(iRegI dst, immI16 src) %{ 4301 match(Set dst src); 4302 ins_cost(DEFAULT_COST_LOW); 4303 size(4); 4304 format %{ "LGHI $dst,$src\t # (int)" %} 4305 ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost. 4306 ins_pipe(pipe_class_dummy); 4307 %} 4308 4309 instruct loadConI_0(iRegI dst, immI_0 src, flagsReg cr) %{ 4310 match(Set dst src); 4311 effect(KILL cr); 4312 ins_cost(DEFAULT_COST_LOW); 4313 size(4); 4314 format %{ "loadConI $dst,$src\t # (int) XGR because ZERO is loaded" %} 4315 opcode(XGR_ZOPC); 4316 ins_encode(z_rreform(dst, dst)); 4317 ins_pipe(pipe_class_dummy); 4318 %} 4319 4320 instruct loadConUI16(iRegI dst, uimmI16 src) %{ 4321 match(Set dst src); 4322 // TODO: s390 port size(FIXED_SIZE); 4323 format %{ "LLILL $dst,$src" %} 4324 opcode(LLILL_ZOPC); 4325 ins_encode(z_riform_unsigned(dst, src) ); 4326 ins_pipe(pipe_class_dummy); 4327 %} 4328 4329 // Load long constant from TOC with pcrelative address. 4330 instruct loadConL_pcrelTOC(iRegL dst, immL src) %{ 4331 match(Set dst src); 4332 ins_cost(MEMORY_REF_COST_LO); 4333 size(6); 4334 format %{ "LGRL $dst,[pcrelTOC]\t # load long $src from table" %} 4335 ins_encode %{ 4336 address long_address = __ long_constant($src$$constant); 4337 if (long_address == NULL) { 4338 Compile::current()->env()->record_out_of_memory_failure(); 4339 return; 4340 } 4341 __ load_long_pcrelative($dst$$Register, long_address); 4342 %} 4343 ins_pipe(pipe_class_dummy); 4344 %} 4345 4346 instruct loadConL32(iRegL dst, immL32 src) %{ 4347 match(Set dst src); 4348 ins_cost(DEFAULT_COST); 4349 size(6); 4350 format %{ "LGFI $dst,$src\t # (long)" %} 4351 ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost. 4352 ins_pipe(pipe_class_dummy); 4353 %} 4354 4355 instruct loadConL16(iRegL dst, immL16 src) %{ 4356 match(Set dst src); 4357 ins_cost(DEFAULT_COST_LOW); 4358 size(4); 4359 format %{ "LGHI $dst,$src\t # (long)" %} 4360 ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost. 4361 ins_pipe(pipe_class_dummy); 4362 %} 4363 4364 instruct loadConL_0(iRegL dst, immL_0 src, flagsReg cr) %{ 4365 match(Set dst src); 4366 effect(KILL cr); 4367 ins_cost(DEFAULT_COST_LOW); 4368 format %{ "LoadConL $dst,$src\t # (long) XGR because ZERO is loaded" %} 4369 opcode(XGR_ZOPC); 4370 ins_encode(z_rreform(dst, dst)); 4371 ins_pipe(pipe_class_dummy); 4372 %} 4373 4374 // Load ptr constant from TOC with pc relative address. 4375 // Special handling for oop constants required. 4376 instruct loadConP_pcrelTOC(iRegP dst, immP src) %{ 4377 match(Set dst src); 4378 ins_cost(MEMORY_REF_COST_LO); 4379 size(6); 4380 format %{ "LGRL $dst,[pcrelTOC]\t # load ptr $src from table" %} 4381 ins_encode %{ 4382 relocInfo::relocType constant_reloc = $src->constant_reloc(); 4383 if (constant_reloc == relocInfo::oop_type) { 4384 AddressLiteral a = __ allocate_oop_address((jobject)$src$$constant); 4385 bool success = __ load_oop_from_toc($dst$$Register, a); 4386 if (!success) { 4387 Compile::current()->env()->record_out_of_memory_failure(); 4388 return; 4389 } 4390 } else if (constant_reloc == relocInfo::metadata_type) { 4391 AddressLiteral a = __ constant_metadata_address((Metadata *)$src$$constant); 4392 address const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 4393 if (const_toc_addr == NULL) { 4394 Compile::current()->env()->record_out_of_memory_failure(); 4395 return; 4396 } 4397 __ load_long_pcrelative($dst$$Register, const_toc_addr); 4398 } else { // Non-oop pointers, e.g. card mark base, heap top. 4399 address long_address = __ long_constant((jlong)$src$$constant); 4400 if (long_address == NULL) { 4401 Compile::current()->env()->record_out_of_memory_failure(); 4402 return; 4403 } 4404 __ load_long_pcrelative($dst$$Register, long_address); 4405 } 4406 %} 4407 ins_pipe(pipe_class_dummy); 4408 %} 4409 4410 // We don't use immP16 to avoid problems with oops. 4411 instruct loadConP0(iRegP dst, immP0 src, flagsReg cr) %{ 4412 match(Set dst src); 4413 effect(KILL cr); 4414 size(4); 4415 format %{ "XGR $dst,$dst\t # NULL ptr" %} 4416 opcode(XGR_ZOPC); 4417 ins_encode(z_rreform(dst, dst)); 4418 ins_pipe(pipe_class_dummy); 4419 %} 4420 4421 //----------Load Float Constant Instructions------------------------------------------------- 4422 4423 // We may not specify this instruction via an `expand' rule. If we do, 4424 // code selection will forget that this instruction needs a floating 4425 // point constant inserted into the code buffer. So `Shorten_branches' 4426 // will fail. 4427 instruct loadConF_dynTOC(regF dst, immF src, flagsReg cr) %{ 4428 match(Set dst src); 4429 effect(KILL cr); 4430 ins_cost(MEMORY_REF_COST); 4431 size(6); 4432 // If this instruction rematerializes, it prolongs the live range 4433 // of the toc node, causing illegal graphs. 4434 ins_cannot_rematerialize(true); 4435 format %{ "LE(Y) $dst,$constantoffset[,$constanttablebase]\t # load FLOAT $src from table" %} 4436 ins_encode %{ 4437 __ load_float_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch); 4438 %} 4439 ins_pipe(pipe_class_dummy); 4440 %} 4441 4442 // E may not specify this instruction via an `expand' rule. If we do, 4443 // code selection will forget that this instruction needs a floating 4444 // point constant inserted into the code buffer. So `Shorten_branches' 4445 // will fail. 4446 instruct loadConD_dynTOC(regD dst, immD src, flagsReg cr) %{ 4447 match(Set dst src); 4448 effect(KILL cr); 4449 ins_cost(MEMORY_REF_COST); 4450 size(6); 4451 // If this instruction rematerializes, it prolongs the live range 4452 // of the toc node, causing illegal graphs. 4453 ins_cannot_rematerialize(true); 4454 format %{ "LD(Y) $dst,$constantoffset[,$constanttablebase]\t # load DOUBLE $src from table" %} 4455 ins_encode %{ 4456 __ load_double_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch); 4457 %} 4458 ins_pipe(pipe_class_dummy); 4459 %} 4460 4461 // Special case: Load Const 0.0F 4462 4463 // There's a special instr to clear a FP register. 4464 instruct loadConF0(regF dst, immFp0 src) %{ 4465 match(Set dst src); 4466 ins_cost(DEFAULT_COST_LOW); 4467 size(4); 4468 format %{ "LZER $dst,$src\t # clear to zero" %} 4469 opcode(LZER_ZOPC); 4470 ins_encode(z_rreform(dst, Z_F0)); 4471 ins_pipe(pipe_class_dummy); 4472 %} 4473 4474 // There's a special instr to clear a FP register. 4475 instruct loadConD0(regD dst, immDp0 src) %{ 4476 match(Set dst src); 4477 ins_cost(DEFAULT_COST_LOW); 4478 size(4); 4479 format %{ "LZDR $dst,$src\t # clear to zero" %} 4480 opcode(LZDR_ZOPC); 4481 ins_encode(z_rreform(dst, Z_F0)); 4482 ins_pipe(pipe_class_dummy); 4483 %} 4484 4485 4486 //----------Store Instructions------------------------------------------------- 4487 4488 // BYTE 4489 4490 // Store Byte 4491 instruct storeB(memory mem, iRegI src) %{ 4492 match(Set mem (StoreB mem src)); 4493 ins_cost(MEMORY_REF_COST); 4494 size(Z_DISP_SIZE); 4495 format %{ "STC(Y) $src,$mem\t # byte" %} 4496 opcode(STCY_ZOPC, STC_ZOPC); 4497 ins_encode(z_form_rt_mem_opt(src, mem)); 4498 ins_pipe(pipe_class_dummy); 4499 %} 4500 4501 instruct storeCM(memory mem, immI_0 src) %{ 4502 match(Set mem (StoreCM mem src)); 4503 ins_cost(MEMORY_REF_COST); 4504 // TODO: s390 port size(VARIABLE_SIZE); 4505 format %{ "STC(Y) $src,$mem\t # CMS card-mark byte (must be 0!)" %} 4506 ins_encode %{ 4507 guarantee($mem$$index$$Register != Z_R0, "content will not be used."); 4508 if ($mem$$index$$Register != noreg) { 4509 // Can't use clear_mem --> load const zero and store character. 4510 __ load_const_optimized(Z_R0_scratch, (long)0); 4511 if (Immediate::is_uimm12($mem$$disp)) { 4512 __ z_stc(Z_R0_scratch, $mem$$Address); 4513 } else { 4514 __ z_stcy(Z_R0_scratch, $mem$$Address); 4515 } 4516 } else { 4517 __ clear_mem(Address($mem$$Address), 1); 4518 } 4519 %} 4520 ins_pipe(pipe_class_dummy); 4521 %} 4522 4523 // CHAR/SHORT 4524 4525 // Store Char/Short 4526 instruct storeC(memory mem, iRegI src) %{ 4527 match(Set mem (StoreC mem src)); 4528 ins_cost(MEMORY_REF_COST); 4529 size(Z_DISP_SIZE); 4530 format %{ "STH(Y) $src,$mem\t # short" %} 4531 opcode(STHY_ZOPC, STH_ZOPC); 4532 ins_encode(z_form_rt_mem_opt(src, mem)); 4533 ins_pipe(pipe_class_dummy); 4534 %} 4535 4536 // INT 4537 4538 // Store Integer 4539 instruct storeI(memory mem, iRegI src) %{ 4540 match(Set mem (StoreI mem src)); 4541 ins_cost(MEMORY_REF_COST); 4542 size(Z_DISP_SIZE); 4543 format %{ "ST(Y) $src,$mem\t # int" %} 4544 opcode(STY_ZOPC, ST_ZOPC); 4545 ins_encode(z_form_rt_mem_opt(src, mem)); 4546 ins_pipe(pipe_class_dummy); 4547 %} 4548 4549 // LONG 4550 4551 // Store Long 4552 instruct storeL(memory mem, iRegL src) %{ 4553 match(Set mem (StoreL mem src)); 4554 ins_cost(MEMORY_REF_COST); 4555 size(Z_DISP3_SIZE); 4556 format %{ "STG $src,$mem\t # long" %} 4557 opcode(STG_ZOPC, STG_ZOPC); 4558 ins_encode(z_form_rt_mem_opt(src, mem)); 4559 ins_pipe(pipe_class_dummy); 4560 %} 4561 4562 // PTR 4563 4564 // Store Pointer 4565 instruct storeP(memory dst, memoryRegP src) %{ 4566 match(Set dst (StoreP dst src)); 4567 ins_cost(MEMORY_REF_COST); 4568 size(Z_DISP3_SIZE); 4569 format %{ "STG $src,$dst\t # ptr" %} 4570 opcode(STG_ZOPC, STG_ZOPC); 4571 ins_encode(z_form_rt_mem_opt(src, dst)); 4572 ins_pipe(pipe_class_dummy); 4573 %} 4574 4575 // FLOAT 4576 4577 // Store Float 4578 instruct storeF(memory mem, regF src) %{ 4579 match(Set mem (StoreF mem src)); 4580 ins_cost(MEMORY_REF_COST); 4581 size(Z_DISP_SIZE); 4582 format %{ "STE(Y) $src,$mem\t # float" %} 4583 opcode(STEY_ZOPC, STE_ZOPC); 4584 ins_encode(z_form_rt_mem_opt(src, mem)); 4585 ins_pipe(pipe_class_dummy); 4586 %} 4587 4588 // DOUBLE 4589 4590 // Store Double 4591 instruct storeD(memory mem, regD src) %{ 4592 match(Set mem (StoreD mem src)); 4593 ins_cost(MEMORY_REF_COST); 4594 size(Z_DISP_SIZE); 4595 format %{ "STD(Y) $src,$mem\t # double" %} 4596 opcode(STDY_ZOPC, STD_ZOPC); 4597 ins_encode(z_form_rt_mem_opt(src, mem)); 4598 ins_pipe(pipe_class_dummy); 4599 %} 4600 4601 // Prefetch instructions. Must be safe to execute with invalid address (cannot fault). 4602 4603 // Should support match rule for PrefetchAllocation. 4604 // Still needed after 8068977 for PrefetchAllocate. 4605 instruct prefetchAlloc(memory mem) %{ 4606 match(PrefetchAllocation mem); 4607 predicate(VM_Version::has_Prefetch()); 4608 ins_cost(DEFAULT_COST); 4609 format %{ "PREFETCH 2, $mem\t # Prefetch allocation, z10 only" %} 4610 ins_encode %{ __ z_pfd(0x02, $mem$$Address); %} 4611 ins_pipe(pipe_class_dummy); 4612 %} 4613 4614 //----------Memory init instructions------------------------------------------ 4615 4616 // Move Immediate to 1-byte memory. 4617 instruct memInitB(memoryRSY mem, immI8 src) %{ 4618 match(Set mem (StoreB mem src)); 4619 ins_cost(MEMORY_REF_COST); 4620 // TODO: s390 port size(VARIABLE_SIZE); 4621 format %{ "MVI $mem,$src\t # direct mem init 1" %} 4622 ins_encode %{ 4623 if (Immediate::is_uimm12((long)$mem$$disp)) { 4624 __ z_mvi($mem$$Address, $src$$constant); 4625 } else { 4626 __ z_mviy($mem$$Address, $src$$constant); 4627 } 4628 %} 4629 ins_pipe(pipe_class_dummy); 4630 %} 4631 4632 // Move Immediate to 2-byte memory. 4633 instruct memInitC(memoryRS mem, immI16 src) %{ 4634 match(Set mem (StoreC mem src)); 4635 ins_cost(MEMORY_REF_COST); 4636 size(6); 4637 format %{ "MVHHI $mem,$src\t # direct mem init 2" %} 4638 opcode(MVHHI_ZOPC); 4639 ins_encode(z_silform(mem, src)); 4640 ins_pipe(pipe_class_dummy); 4641 %} 4642 4643 // Move Immediate to 4-byte memory. 4644 instruct memInitI(memoryRS mem, immI16 src) %{ 4645 match(Set mem (StoreI mem src)); 4646 ins_cost(MEMORY_REF_COST); 4647 size(6); 4648 format %{ "MVHI $mem,$src\t # direct mem init 4" %} 4649 opcode(MVHI_ZOPC); 4650 ins_encode(z_silform(mem, src)); 4651 ins_pipe(pipe_class_dummy); 4652 %} 4653 4654 4655 // Move Immediate to 8-byte memory. 4656 instruct memInitL(memoryRS mem, immL16 src) %{ 4657 match(Set mem (StoreL mem src)); 4658 ins_cost(MEMORY_REF_COST); 4659 size(6); 4660 format %{ "MVGHI $mem,$src\t # direct mem init 8" %} 4661 opcode(MVGHI_ZOPC); 4662 ins_encode(z_silform(mem, src)); 4663 ins_pipe(pipe_class_dummy); 4664 %} 4665 4666 // Move Immediate to 8-byte memory. 4667 instruct memInitP(memoryRS mem, immP16 src) %{ 4668 match(Set mem (StoreP mem src)); 4669 ins_cost(MEMORY_REF_COST); 4670 size(6); 4671 format %{ "MVGHI $mem,$src\t # direct mem init 8" %} 4672 opcode(MVGHI_ZOPC); 4673 ins_encode(z_silform(mem, src)); 4674 ins_pipe(pipe_class_dummy); 4675 %} 4676 4677 4678 //----------Instructions for compressed pointers (cOop and NKlass)------------- 4679 4680 // See cOop encoding classes for elaborate comment. 4681 4682 // Moved here because it is needed in expand rules for encode. 4683 // Long negation. 4684 instruct negL_reg_reg(iRegL dst, immL_0 zero, iRegL src, flagsReg cr) %{ 4685 match(Set dst (SubL zero src)); 4686 effect(KILL cr); 4687 size(4); 4688 format %{ "NEG $dst, $src\t # long" %} 4689 ins_encode %{ __ z_lcgr($dst$$Register, $src$$Register); %} 4690 ins_pipe(pipe_class_dummy); 4691 %} 4692 4693 // Load Compressed Pointer 4694 4695 // Load narrow oop 4696 instruct loadN(iRegN dst, memory mem) %{ 4697 match(Set dst (LoadN mem)); 4698 ins_cost(MEMORY_REF_COST); 4699 size(Z_DISP3_SIZE); 4700 format %{ "LoadN $dst,$mem\t# (cOop)" %} 4701 opcode(LLGF_ZOPC, LLGF_ZOPC); 4702 ins_encode(z_form_rt_mem_opt(dst, mem)); 4703 ins_pipe(pipe_class_dummy); 4704 %} 4705 4706 // Load narrow Klass Pointer 4707 instruct loadNKlass(iRegN dst, memory mem) %{ 4708 match(Set dst (LoadNKlass mem)); 4709 ins_cost(MEMORY_REF_COST); 4710 size(Z_DISP3_SIZE); 4711 format %{ "LoadNKlass $dst,$mem\t# (klass cOop)" %} 4712 opcode(LLGF_ZOPC, LLGF_ZOPC); 4713 ins_encode(z_form_rt_mem_opt(dst, mem)); 4714 ins_pipe(pipe_class_dummy); 4715 %} 4716 4717 // Load constant Compressed Pointer 4718 4719 instruct loadConN(iRegN dst, immN src) %{ 4720 match(Set dst src); 4721 ins_cost(DEFAULT_COST); 4722 size(6); 4723 format %{ "loadConN $dst,$src\t # (cOop)" %} 4724 ins_encode %{ 4725 AddressLiteral cOop = __ constant_oop_address((jobject)$src$$constant); 4726 __ relocate(cOop.rspec(), 1); 4727 __ load_narrow_oop($dst$$Register, (narrowOop)cOop.value()); 4728 %} 4729 ins_pipe(pipe_class_dummy); 4730 %} 4731 4732 instruct loadConN0(iRegN dst, immN0 src, flagsReg cr) %{ 4733 match(Set dst src); 4734 effect(KILL cr); 4735 ins_cost(DEFAULT_COST_LOW); 4736 size(4); 4737 format %{ "loadConN $dst,$src\t # (cOop) XGR because ZERO is loaded" %} 4738 opcode(XGR_ZOPC); 4739 ins_encode(z_rreform(dst, dst)); 4740 ins_pipe(pipe_class_dummy); 4741 %} 4742 4743 instruct loadConNKlass(iRegN dst, immNKlass src) %{ 4744 match(Set dst src); 4745 ins_cost(DEFAULT_COST); 4746 size(6); 4747 format %{ "loadConNKlass $dst,$src\t # (cKlass)" %} 4748 ins_encode %{ 4749 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant); 4750 __ relocate(NKlass.rspec(), 1); 4751 __ load_narrow_klass($dst$$Register, (Klass*)NKlass.value()); 4752 %} 4753 ins_pipe(pipe_class_dummy); 4754 %} 4755 4756 // Load and Decode Compressed Pointer 4757 // optimized variants for Unscaled cOops 4758 4759 instruct decodeLoadN(iRegP dst, memory mem) %{ 4760 match(Set dst (DecodeN (LoadN mem))); 4761 predicate(false && (Universe::narrow_oop_base()==NULL)&&(Universe::narrow_oop_shift()==0)); 4762 ins_cost(MEMORY_REF_COST); 4763 size(Z_DISP3_SIZE); 4764 format %{ "DecodeLoadN $dst,$mem\t# (cOop Load+Decode)" %} 4765 opcode(LLGF_ZOPC, LLGF_ZOPC); 4766 ins_encode(z_form_rt_mem_opt(dst, mem)); 4767 ins_pipe(pipe_class_dummy); 4768 %} 4769 4770 instruct decodeLoadNKlass(iRegP dst, memory mem) %{ 4771 match(Set dst (DecodeNKlass (LoadNKlass mem))); 4772 predicate(false && (Universe::narrow_klass_base()==NULL)&&(Universe::narrow_klass_shift()==0)); 4773 ins_cost(MEMORY_REF_COST); 4774 size(Z_DISP3_SIZE); 4775 format %{ "DecodeLoadNKlass $dst,$mem\t# (load/decode NKlass)" %} 4776 opcode(LLGF_ZOPC, LLGF_ZOPC); 4777 ins_encode(z_form_rt_mem_opt(dst, mem)); 4778 ins_pipe(pipe_class_dummy); 4779 %} 4780 4781 instruct decodeLoadConNKlass(iRegP dst, immNKlass src) %{ 4782 match(Set dst (DecodeNKlass src)); 4783 ins_cost(3 * DEFAULT_COST); 4784 size(12); 4785 format %{ "DecodeLoadConNKlass $dst,$src\t # decode(cKlass)" %} 4786 ins_encode %{ 4787 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant); 4788 __ relocate(NKlass.rspec(), 1); 4789 __ load_const($dst$$Register, (Klass*)NKlass.value()); 4790 %} 4791 ins_pipe(pipe_class_dummy); 4792 %} 4793 4794 // Decode Compressed Pointer 4795 4796 // General decoder 4797 instruct decodeN(iRegP dst, iRegN src, flagsReg cr) %{ 4798 match(Set dst (DecodeN src)); 4799 effect(KILL cr); 4800 predicate(Universe::narrow_oop_base() == NULL || !ExpandLoadingBaseDecode); 4801 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST); 4802 // TODO: s390 port size(VARIABLE_SIZE); 4803 format %{ "decodeN $dst,$src\t# (decode cOop)" %} 4804 ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, true); %} 4805 ins_pipe(pipe_class_dummy); 4806 %} 4807 4808 // General Klass decoder 4809 instruct decodeKlass(iRegP dst, iRegN src, flagsReg cr) %{ 4810 match(Set dst (DecodeNKlass src)); 4811 effect(KILL cr); 4812 ins_cost(3 * DEFAULT_COST); 4813 format %{ "decode_klass $dst,$src" %} 4814 ins_encode %{ __ decode_klass_not_null($dst$$Register, $src$$Register); %} 4815 ins_pipe(pipe_class_dummy); 4816 %} 4817 4818 // General decoder 4819 instruct decodeN_NN(iRegP dst, iRegN src, flagsReg cr) %{ 4820 match(Set dst (DecodeN src)); 4821 effect(KILL cr); 4822 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull || 4823 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && 4824 (Universe::narrow_oop_base()== NULL || !ExpandLoadingBaseDecode_NN)); 4825 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); 4826 // TODO: s390 port size(VARIABLE_SIZE); 4827 format %{ "decodeN $dst,$src\t# (decode cOop NN)" %} 4828 ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, false); %} 4829 ins_pipe(pipe_class_dummy); 4830 %} 4831 4832 instruct loadBase(iRegL dst, immL baseImm) %{ 4833 effect(DEF dst, USE baseImm); 4834 predicate(false); 4835 format %{ "llihl $dst=$baseImm \t// load heap base" %} 4836 ins_encode %{ __ get_oop_base($dst$$Register, $baseImm$$constant); %} 4837 ins_pipe(pipe_class_dummy); 4838 %} 4839 4840 // Decoder for heapbased mode peeling off loading the base. 4841 instruct decodeN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{ 4842 match(Set dst (DecodeN src base)); 4843 // Note: Effect TEMP dst was used with the intention to get 4844 // different regs for dst and base, but this has caused ADLC to 4845 // generate wrong code. Oop_decoder generates additional lgr when 4846 // dst==base. 4847 effect(KILL cr); 4848 predicate(false); 4849 // TODO: s390 port size(VARIABLE_SIZE); 4850 format %{ "decodeN $dst = ($src == 0) ? NULL : ($src << 3) + $base + pow2_offset\t# (decode cOop)" %} 4851 ins_encode %{ 4852 __ oop_decoder($dst$$Register, $src$$Register, true, $base$$Register, 4853 (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)Universe::narrow_oop_base())); 4854 %} 4855 ins_pipe(pipe_class_dummy); 4856 %} 4857 4858 // Decoder for heapbased mode peeling off loading the base. 4859 instruct decodeN_NN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{ 4860 match(Set dst (DecodeN src base)); 4861 effect(KILL cr); 4862 predicate(false); 4863 // TODO: s390 port size(VARIABLE_SIZE); 4864 format %{ "decodeN $dst = ($src << 3) + $base + pow2_offset\t# (decode cOop)" %} 4865 ins_encode %{ 4866 __ oop_decoder($dst$$Register, $src$$Register, false, $base$$Register, 4867 (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)Universe::narrow_oop_base())); 4868 %} 4869 ins_pipe(pipe_class_dummy); 4870 %} 4871 4872 // Decoder for heapbased mode peeling off loading the base. 4873 instruct decodeN_Ex(iRegP dst, iRegN src, flagsReg cr) %{ 4874 match(Set dst (DecodeN src)); 4875 predicate(Universe::narrow_oop_base() != NULL && ExpandLoadingBaseDecode); 4876 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST); 4877 // TODO: s390 port size(VARIABLE_SIZE); 4878 expand %{ 4879 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_oop_base() %} 4880 iRegL base; 4881 loadBase(base, baseImm); 4882 decodeN_base(dst, src, base, cr); 4883 %} 4884 %} 4885 4886 // Decoder for heapbased mode peeling off loading the base. 4887 instruct decodeN_NN_Ex(iRegP dst, iRegN src, flagsReg cr) %{ 4888 match(Set dst (DecodeN src)); 4889 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull || 4890 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && 4891 Universe::narrow_oop_base() != NULL && ExpandLoadingBaseDecode_NN); 4892 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); 4893 // TODO: s390 port size(VARIABLE_SIZE); 4894 expand %{ 4895 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_oop_base() %} 4896 iRegL base; 4897 loadBase(base, baseImm); 4898 decodeN_NN_base(dst, src, base, cr); 4899 %} 4900 %} 4901 4902 // Encode Compressed Pointer 4903 4904 // General encoder 4905 instruct encodeP(iRegN dst, iRegP src, flagsReg cr) %{ 4906 match(Set dst (EncodeP src)); 4907 effect(KILL cr); 4908 predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) && 4909 (Universe::narrow_oop_base() == 0 || 4910 Universe::narrow_oop_base_disjoint() || 4911 !ExpandLoadingBaseEncode)); 4912 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); 4913 // TODO: s390 port size(VARIABLE_SIZE); 4914 format %{ "encodeP $dst,$src\t# (encode cOop)" %} 4915 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, true, Z_R1_scratch, -1, all_outs_are_Stores(this)); %} 4916 ins_pipe(pipe_class_dummy); 4917 %} 4918 4919 // General class encoder 4920 instruct encodeKlass(iRegN dst, iRegP src, flagsReg cr) %{ 4921 match(Set dst (EncodePKlass src)); 4922 effect(KILL cr); 4923 format %{ "encode_klass $dst,$src" %} 4924 ins_encode %{ __ encode_klass_not_null($dst$$Register, $src$$Register); %} 4925 ins_pipe(pipe_class_dummy); 4926 %} 4927 4928 instruct encodeP_NN(iRegN dst, iRegP src, flagsReg cr) %{ 4929 match(Set dst (EncodeP src)); 4930 effect(KILL cr); 4931 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) && 4932 (Universe::narrow_oop_base() == 0 || 4933 Universe::narrow_oop_base_disjoint() || 4934 !ExpandLoadingBaseEncode_NN)); 4935 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); 4936 // TODO: s390 port size(VARIABLE_SIZE); 4937 format %{ "encodeP $dst,$src\t# (encode cOop)" %} 4938 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, Z_R1_scratch, -1, all_outs_are_Stores(this)); %} 4939 ins_pipe(pipe_class_dummy); 4940 %} 4941 4942 // Encoder for heapbased mode peeling off loading the base. 4943 instruct encodeP_base(iRegN dst, iRegP src, iRegL base) %{ 4944 match(Set dst (EncodeP src (Binary base dst))); 4945 effect(TEMP_DEF dst); 4946 predicate(false); 4947 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); 4948 // TODO: s390 port size(VARIABLE_SIZE); 4949 format %{ "encodeP $dst = ($src>>3) +$base + pow2_offset\t# (encode cOop)" %} 4950 ins_encode %{ 4951 jlong offset = -(jlong)MacroAssembler::get_oop_base_pow2_offset 4952 (((uint64_t)(intptr_t)Universe::narrow_oop_base()) >> Universe::narrow_oop_shift()); 4953 __ oop_encoder($dst$$Register, $src$$Register, true, $base$$Register, offset); 4954 %} 4955 ins_pipe(pipe_class_dummy); 4956 %} 4957 4958 // Encoder for heapbased mode peeling off loading the base. 4959 instruct encodeP_NN_base(iRegN dst, iRegP src, iRegL base, immL pow2_offset) %{ 4960 match(Set dst (EncodeP src base)); 4961 effect(USE pow2_offset); 4962 predicate(false); 4963 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); 4964 // TODO: s390 port size(VARIABLE_SIZE); 4965 format %{ "encodeP $dst = ($src>>3) +$base + $pow2_offset\t# (encode cOop)" %} 4966 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, $base$$Register, $pow2_offset$$constant); %} 4967 ins_pipe(pipe_class_dummy); 4968 %} 4969 4970 // Encoder for heapbased mode peeling off loading the base. 4971 instruct encodeP_Ex(iRegN dst, iRegP src, flagsReg cr) %{ 4972 match(Set dst (EncodeP src)); 4973 effect(KILL cr); 4974 predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) && 4975 (Universe::narrow_oop_base_overlaps() && ExpandLoadingBaseEncode)); 4976 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); 4977 // TODO: s390 port size(VARIABLE_SIZE); 4978 expand %{ 4979 immL baseImm %{ ((jlong)(intptr_t)Universe::narrow_oop_base()) >> Universe::narrow_oop_shift() %} 4980 immL_0 zero %{ (0) %} 4981 flagsReg ccr; 4982 iRegL base; 4983 iRegL negBase; 4984 loadBase(base, baseImm); 4985 negL_reg_reg(negBase, zero, base, ccr); 4986 encodeP_base(dst, src, negBase); 4987 %} 4988 %} 4989 4990 // Encoder for heapbased mode peeling off loading the base. 4991 instruct encodeP_NN_Ex(iRegN dst, iRegP src, flagsReg cr) %{ 4992 match(Set dst (EncodeP src)); 4993 effect(KILL cr); 4994 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) && 4995 (Universe::narrow_oop_base_overlaps() && ExpandLoadingBaseEncode_NN)); 4996 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); 4997 // TODO: s390 port size(VARIABLE_SIZE); 4998 expand %{ 4999 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_oop_base() %} 5000 immL pow2_offset %{ -(jlong)MacroAssembler::get_oop_base_pow2_offset(((uint64_t)(intptr_t)Universe::narrow_oop_base())) %} 5001 immL_0 zero %{ 0 %} 5002 flagsReg ccr; 5003 iRegL base; 5004 iRegL negBase; 5005 loadBase(base, baseImm); 5006 negL_reg_reg(negBase, zero, base, ccr); 5007 encodeP_NN_base(dst, src, negBase, pow2_offset); 5008 %} 5009 %} 5010 5011 // Store Compressed Pointer 5012 5013 // Store Compressed Pointer 5014 instruct storeN(memory mem, iRegN_P2N src) %{ 5015 match(Set mem (StoreN mem src)); 5016 ins_cost(MEMORY_REF_COST); 5017 size(Z_DISP_SIZE); 5018 format %{ "ST $src,$mem\t# (cOop)" %} 5019 opcode(STY_ZOPC, ST_ZOPC); 5020 ins_encode(z_form_rt_mem_opt(src, mem)); 5021 ins_pipe(pipe_class_dummy); 5022 %} 5023 5024 // Store Compressed Klass pointer 5025 instruct storeNKlass(memory mem, iRegN src) %{ 5026 match(Set mem (StoreNKlass mem src)); 5027 ins_cost(MEMORY_REF_COST); 5028 size(Z_DISP_SIZE); 5029 format %{ "ST $src,$mem\t# (cKlass)" %} 5030 opcode(STY_ZOPC, ST_ZOPC); 5031 ins_encode(z_form_rt_mem_opt(src, mem)); 5032 ins_pipe(pipe_class_dummy); 5033 %} 5034 5035 // Compare Compressed Pointers 5036 5037 instruct compN_iRegN(iRegN_P2N src1, iRegN_P2N src2, flagsReg cr) %{ 5038 match(Set cr (CmpN src1 src2)); 5039 ins_cost(DEFAULT_COST); 5040 size(2); 5041 format %{ "CLR $src1,$src2\t# (cOop)" %} 5042 opcode(CLR_ZOPC); 5043 ins_encode(z_rrform(src1, src2)); 5044 ins_pipe(pipe_class_dummy); 5045 %} 5046 5047 instruct compN_iRegN_immN(iRegN_P2N src1, immN src2, flagsReg cr) %{ 5048 match(Set cr (CmpN src1 src2)); 5049 ins_cost(DEFAULT_COST); 5050 size(6); 5051 format %{ "CLFI $src1,$src2\t# (cOop) compare immediate narrow" %} 5052 ins_encode %{ 5053 AddressLiteral cOop = __ constant_oop_address((jobject)$src2$$constant); 5054 __ relocate(cOop.rspec(), 1); 5055 __ compare_immediate_narrow_oop($src1$$Register, (narrowOop)cOop.value()); 5056 %} 5057 ins_pipe(pipe_class_dummy); 5058 %} 5059 5060 instruct compNKlass_iRegN_immN(iRegN src1, immNKlass src2, flagsReg cr) %{ 5061 match(Set cr (CmpN src1 src2)); 5062 ins_cost(DEFAULT_COST); 5063 size(6); 5064 format %{ "CLFI $src1,$src2\t# (NKlass) compare immediate narrow" %} 5065 ins_encode %{ 5066 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src2$$constant); 5067 __ relocate(NKlass.rspec(), 1); 5068 __ compare_immediate_narrow_klass($src1$$Register, (Klass*)NKlass.value()); 5069 %} 5070 ins_pipe(pipe_class_dummy); 5071 %} 5072 5073 instruct compN_iRegN_immN0(iRegN_P2N src1, immN0 src2, flagsReg cr) %{ 5074 match(Set cr (CmpN src1 src2)); 5075 ins_cost(DEFAULT_COST); 5076 size(2); 5077 format %{ "LTR $src1,$src2\t# (cOop) LTR because comparing against zero" %} 5078 opcode(LTR_ZOPC); 5079 ins_encode(z_rrform(src1, src1)); 5080 ins_pipe(pipe_class_dummy); 5081 %} 5082 5083 5084 //----------MemBar Instructions----------------------------------------------- 5085 5086 // Memory barrier flavors 5087 5088 instruct membar_acquire() %{ 5089 match(MemBarAcquire); 5090 match(LoadFence); 5091 ins_cost(4*MEMORY_REF_COST); 5092 size(0); 5093 format %{ "MEMBAR-acquire" %} 5094 ins_encode %{ __ z_acquire(); %} 5095 ins_pipe(pipe_class_dummy); 5096 %} 5097 5098 instruct membar_acquire_lock() %{ 5099 match(MemBarAcquireLock); 5100 ins_cost(0); 5101 size(0); 5102 format %{ "MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} 5103 ins_encode(/*empty*/); 5104 ins_pipe(pipe_class_dummy); 5105 %} 5106 5107 instruct membar_release() %{ 5108 match(MemBarRelease); 5109 match(StoreFence); 5110 ins_cost(4 * MEMORY_REF_COST); 5111 size(0); 5112 format %{ "MEMBAR-release" %} 5113 ins_encode %{ __ z_release(); %} 5114 ins_pipe(pipe_class_dummy); 5115 %} 5116 5117 instruct membar_release_lock() %{ 5118 match(MemBarReleaseLock); 5119 ins_cost(0); 5120 size(0); 5121 format %{ "MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} 5122 ins_encode(/*empty*/); 5123 ins_pipe(pipe_class_dummy); 5124 %} 5125 5126 instruct membar_volatile() %{ 5127 match(MemBarVolatile); 5128 ins_cost(4 * MEMORY_REF_COST); 5129 size(2); 5130 format %{ "MEMBAR-volatile" %} 5131 ins_encode %{ __ z_fence(); %} 5132 ins_pipe(pipe_class_dummy); 5133 %} 5134 5135 instruct unnecessary_membar_volatile() %{ 5136 match(MemBarVolatile); 5137 predicate(Matcher::post_store_load_barrier(n)); 5138 ins_cost(0); 5139 size(0); 5140 format %{ "# MEMBAR-volatile (empty)" %} 5141 ins_encode(/*empty*/); 5142 ins_pipe(pipe_class_dummy); 5143 %} 5144 5145 instruct membar_CPUOrder() %{ 5146 match(MemBarCPUOrder); 5147 ins_cost(0); 5148 // TODO: s390 port size(FIXED_SIZE); 5149 format %{ "MEMBAR-CPUOrder (empty)" %} 5150 ins_encode(/*empty*/); 5151 ins_pipe(pipe_class_dummy); 5152 %} 5153 5154 instruct membar_storestore() %{ 5155 match(MemBarStoreStore); 5156 ins_cost(0); 5157 size(0); 5158 format %{ "MEMBAR-storestore (empty)" %} 5159 ins_encode(); 5160 ins_pipe(pipe_class_dummy); 5161 %} 5162 5163 5164 //----------Register Move Instructions----------------------------------------- 5165 instruct roundDouble_nop(regD dst) %{ 5166 match(Set dst (RoundDouble dst)); 5167 ins_cost(0); 5168 // TODO: s390 port size(FIXED_SIZE); 5169 // z/Architecture results are already "rounded" (i.e., normal-format IEEE). 5170 ins_encode(); 5171 ins_pipe(pipe_class_dummy); 5172 %} 5173 5174 instruct roundFloat_nop(regF dst) %{ 5175 match(Set dst (RoundFloat dst)); 5176 ins_cost(0); 5177 // TODO: s390 port size(FIXED_SIZE); 5178 // z/Architecture results are already "rounded" (i.e., normal-format IEEE). 5179 ins_encode(); 5180 ins_pipe(pipe_class_dummy); 5181 %} 5182 5183 // Cast Long to Pointer for unsafe natives. 5184 instruct castX2P(iRegP dst, iRegL src) %{ 5185 match(Set dst (CastX2P src)); 5186 // TODO: s390 port size(VARIABLE_SIZE); 5187 format %{ "LGR $dst,$src\t # CastX2P" %} 5188 ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %} 5189 ins_pipe(pipe_class_dummy); 5190 %} 5191 5192 // Cast Pointer to Long for unsafe natives. 5193 instruct castP2X(iRegL dst, iRegP_N2P src) %{ 5194 match(Set dst (CastP2X src)); 5195 // TODO: s390 port size(VARIABLE_SIZE); 5196 format %{ "LGR $dst,$src\t # CastP2X" %} 5197 ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %} 5198 ins_pipe(pipe_class_dummy); 5199 %} 5200 5201 instruct stfSSD(stackSlotD stkSlot, regD src) %{ 5202 // %%%% TODO: Tell the coalescer that this kind of node is a copy! 5203 match(Set stkSlot src); // chain rule 5204 ins_cost(MEMORY_REF_COST); 5205 // TODO: s390 port size(FIXED_SIZE); 5206 format %{ " STD $src,$stkSlot\t # stk" %} 5207 opcode(STD_ZOPC); 5208 ins_encode(z_form_rt_mem(src, stkSlot)); 5209 ins_pipe(pipe_class_dummy); 5210 %} 5211 5212 instruct stfSSF(stackSlotF stkSlot, regF src) %{ 5213 // %%%% TODO: Tell the coalescer that this kind of node is a copy! 5214 match(Set stkSlot src); // chain rule 5215 ins_cost(MEMORY_REF_COST); 5216 // TODO: s390 port size(FIXED_SIZE); 5217 format %{ "STE $src,$stkSlot\t # stk" %} 5218 opcode(STE_ZOPC); 5219 ins_encode(z_form_rt_mem(src, stkSlot)); 5220 ins_pipe(pipe_class_dummy); 5221 %} 5222 5223 //----------Conditional Move--------------------------------------------------- 5224 5225 instruct cmovN_reg(cmpOp cmp, flagsReg cr, iRegN dst, iRegN_P2N src) %{ 5226 match(Set dst (CMoveN (Binary cmp cr) (Binary dst src))); 5227 ins_cost(DEFAULT_COST + BRANCH_COST); 5228 // TODO: s390 port size(VARIABLE_SIZE); 5229 format %{ "CMoveN,$cmp $dst,$src" %} 5230 ins_encode(z_enc_cmov_reg(cmp,dst,src)); 5231 ins_pipe(pipe_class_dummy); 5232 %} 5233 5234 instruct cmovN_imm(cmpOp cmp, flagsReg cr, iRegN dst, immN0 src) %{ 5235 match(Set dst (CMoveN (Binary cmp cr) (Binary dst src))); 5236 ins_cost(DEFAULT_COST + BRANCH_COST); 5237 // TODO: s390 port size(VARIABLE_SIZE); 5238 format %{ "CMoveN,$cmp $dst,$src" %} 5239 ins_encode(z_enc_cmov_imm(cmp,dst,src)); 5240 ins_pipe(pipe_class_dummy); 5241 %} 5242 5243 instruct cmovI_reg(cmpOp cmp, flagsReg cr, iRegI dst, iRegI src) %{ 5244 match(Set dst (CMoveI (Binary cmp cr) (Binary dst src))); 5245 ins_cost(DEFAULT_COST + BRANCH_COST); 5246 // TODO: s390 port size(VARIABLE_SIZE); 5247 format %{ "CMoveI,$cmp $dst,$src" %} 5248 ins_encode(z_enc_cmov_reg(cmp,dst,src)); 5249 ins_pipe(pipe_class_dummy); 5250 %} 5251 5252 instruct cmovI_imm(cmpOp cmp, flagsReg cr, iRegI dst, immI16 src) %{ 5253 match(Set dst (CMoveI (Binary cmp cr) (Binary dst src))); 5254 ins_cost(DEFAULT_COST + BRANCH_COST); 5255 // TODO: s390 port size(VARIABLE_SIZE); 5256 format %{ "CMoveI,$cmp $dst,$src" %} 5257 ins_encode(z_enc_cmov_imm(cmp,dst,src)); 5258 ins_pipe(pipe_class_dummy); 5259 %} 5260 5261 instruct cmovP_reg(cmpOp cmp, flagsReg cr, iRegP dst, iRegP_N2P src) %{ 5262 match(Set dst (CMoveP (Binary cmp cr) (Binary dst src))); 5263 ins_cost(DEFAULT_COST + BRANCH_COST); 5264 // TODO: s390 port size(VARIABLE_SIZE); 5265 format %{ "CMoveP,$cmp $dst,$src" %} 5266 ins_encode(z_enc_cmov_reg(cmp,dst,src)); 5267 ins_pipe(pipe_class_dummy); 5268 %} 5269 5270 instruct cmovP_imm(cmpOp cmp, flagsReg cr, iRegP dst, immP0 src) %{ 5271 match(Set dst (CMoveP (Binary cmp cr) (Binary dst src))); 5272 ins_cost(DEFAULT_COST + BRANCH_COST); 5273 // TODO: s390 port size(VARIABLE_SIZE); 5274 format %{ "CMoveP,$cmp $dst,$src" %} 5275 ins_encode(z_enc_cmov_imm(cmp,dst,src)); 5276 ins_pipe(pipe_class_dummy); 5277 %} 5278 5279 instruct cmovF_reg(cmpOpF cmp, flagsReg cr, regF dst, regF src) %{ 5280 match(Set dst (CMoveF (Binary cmp cr) (Binary dst src))); 5281 ins_cost(DEFAULT_COST + BRANCH_COST); 5282 // TODO: s390 port size(VARIABLE_SIZE); 5283 format %{ "CMoveF,$cmp $dst,$src" %} 5284 ins_encode %{ 5285 // Don't emit code if operands are identical (same register). 5286 if ($dst$$FloatRegister != $src$$FloatRegister) { 5287 Label done; 5288 __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done); 5289 __ z_ler($dst$$FloatRegister, $src$$FloatRegister); 5290 __ bind(done); 5291 } 5292 %} 5293 ins_pipe(pipe_class_dummy); 5294 %} 5295 5296 instruct cmovD_reg(cmpOpF cmp, flagsReg cr, regD dst, regD src) %{ 5297 match(Set dst (CMoveD (Binary cmp cr) (Binary dst src))); 5298 ins_cost(DEFAULT_COST + BRANCH_COST); 5299 // TODO: s390 port size(VARIABLE_SIZE); 5300 format %{ "CMoveD,$cmp $dst,$src" %} 5301 ins_encode %{ 5302 // Don't emit code if operands are identical (same register). 5303 if ($dst$$FloatRegister != $src$$FloatRegister) { 5304 Label done; 5305 __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done); 5306 __ z_ldr($dst$$FloatRegister, $src$$FloatRegister); 5307 __ bind(done); 5308 } 5309 %} 5310 ins_pipe(pipe_class_dummy); 5311 %} 5312 5313 instruct cmovL_reg(cmpOp cmp, flagsReg cr, iRegL dst, iRegL src) %{ 5314 match(Set dst (CMoveL (Binary cmp cr) (Binary dst src))); 5315 ins_cost(DEFAULT_COST + BRANCH_COST); 5316 // TODO: s390 port size(VARIABLE_SIZE); 5317 format %{ "CMoveL,$cmp $dst,$src" %} 5318 ins_encode(z_enc_cmov_reg(cmp,dst,src)); 5319 ins_pipe(pipe_class_dummy); 5320 %} 5321 5322 instruct cmovL_imm(cmpOp cmp, flagsReg cr, iRegL dst, immL16 src) %{ 5323 match(Set dst (CMoveL (Binary cmp cr) (Binary dst src))); 5324 ins_cost(DEFAULT_COST + BRANCH_COST); 5325 // TODO: s390 port size(VARIABLE_SIZE); 5326 format %{ "CMoveL,$cmp $dst,$src" %} 5327 ins_encode(z_enc_cmov_imm(cmp,dst,src)); 5328 ins_pipe(pipe_class_dummy); 5329 %} 5330 5331 //----------OS and Locking Instructions---------------------------------------- 5332 5333 // This name is KNOWN by the ADLC and cannot be changed. 5334 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type 5335 // for this guy. 5336 instruct tlsLoadP(threadRegP dst) %{ 5337 match(Set dst (ThreadLocal)); 5338 ins_cost(0); 5339 size(0); 5340 ins_should_rematerialize(true); 5341 format %{ "# $dst=ThreadLocal" %} 5342 ins_encode(/* empty */); 5343 ins_pipe(pipe_class_dummy); 5344 %} 5345 5346 instruct checkCastPP(iRegP dst) %{ 5347 match(Set dst (CheckCastPP dst)); 5348 size(0); 5349 format %{ "# checkcastPP of $dst" %} 5350 ins_encode(/*empty*/); 5351 ins_pipe(pipe_class_dummy); 5352 %} 5353 5354 instruct castPP(iRegP dst) %{ 5355 match(Set dst (CastPP dst)); 5356 size(0); 5357 format %{ "# castPP of $dst" %} 5358 ins_encode(/*empty*/); 5359 ins_pipe(pipe_class_dummy); 5360 %} 5361 5362 instruct castII(iRegI dst) %{ 5363 match(Set dst (CastII dst)); 5364 size(0); 5365 format %{ "# castII of $dst" %} 5366 ins_encode(/*empty*/); 5367 ins_pipe(pipe_class_dummy); 5368 %} 5369 5370 5371 //----------Conditional_store-------------------------------------------------- 5372 // Conditional-store of the updated heap-top. 5373 // Used during allocation of the shared heap. 5374 // Sets flags (EQ) on success. 5375 5376 // Implement LoadPLocked. Must be ordered against changes of the memory location 5377 // by storePConditional. 5378 // Don't know whether this is ever used. 5379 instruct loadPLocked(iRegP dst, memory mem) %{ 5380 match(Set dst (LoadPLocked mem)); 5381 ins_cost(MEMORY_REF_COST); 5382 size(Z_DISP3_SIZE); 5383 format %{ "LG $dst,$mem\t # LoadPLocked" %} 5384 opcode(LG_ZOPC, LG_ZOPC); 5385 ins_encode(z_form_rt_mem_opt(dst, mem)); 5386 ins_pipe(pipe_class_dummy); 5387 %} 5388 5389 // As compareAndSwapP, but return flag register instead of boolean value in 5390 // int register. 5391 // This instruction is matched if UseTLAB is off. Needed to pass 5392 // option tests. Mem_ptr must be a memory operand, else this node 5393 // does not get Flag_needs_anti_dependence_check set by adlc. If this 5394 // is not set this node can be rematerialized which leads to errors. 5395 instruct storePConditional(indirect mem_ptr, rarg5RegP oldval, iRegP_N2P newval, flagsReg cr) %{ 5396 match(Set cr (StorePConditional mem_ptr (Binary oldval newval))); 5397 effect(KILL oldval); 5398 // TODO: s390 port size(FIXED_SIZE); 5399 format %{ "storePConditional $oldval,$newval,$mem_ptr" %} 5400 ins_encode(z_enc_casL(oldval, newval, mem_ptr)); 5401 ins_pipe(pipe_class_dummy); 5402 %} 5403 5404 // As compareAndSwapL, but return flag register instead of boolean value in 5405 // int register. 5406 // Used by sun/misc/AtomicLongCSImpl.java. Mem_ptr must be a memory 5407 // operand, else this node does not get 5408 // Flag_needs_anti_dependence_check set by adlc. If this is not set 5409 // this node can be rematerialized which leads to errors. 5410 instruct storeLConditional(indirect mem_ptr, rarg5RegL oldval, iRegL newval, flagsReg cr) %{ 5411 match(Set cr (StoreLConditional mem_ptr (Binary oldval newval))); 5412 effect(KILL oldval); 5413 // TODO: s390 port size(FIXED_SIZE); 5414 format %{ "storePConditional $oldval,$newval,$mem_ptr" %} 5415 ins_encode(z_enc_casL(oldval, newval, mem_ptr)); 5416 ins_pipe(pipe_class_dummy); 5417 %} 5418 5419 // No flag versions for CompareAndSwap{P,I,L,N} because matcher can't match them. 5420 5421 instruct compareAndSwapI_bool(iRegP mem_ptr, rarg5RegI oldval, iRegI newval, iRegI res, flagsReg cr) %{ 5422 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 5423 effect(USE mem_ptr, USE_KILL oldval, KILL cr); 5424 size(16); 5425 format %{ "$res = CompareAndSwapI $oldval,$newval,$mem_ptr" %} 5426 ins_encode(z_enc_casI(oldval, newval, mem_ptr), 5427 z_enc_cctobool(res)); 5428 ins_pipe(pipe_class_dummy); 5429 %} 5430 5431 instruct compareAndSwapL_bool(iRegP mem_ptr, rarg5RegL oldval, iRegL newval, iRegI res, flagsReg cr) %{ 5432 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 5433 effect(USE mem_ptr, USE_KILL oldval, KILL cr); 5434 size(18); 5435 format %{ "$res = CompareAndSwapL $oldval,$newval,$mem_ptr" %} 5436 ins_encode(z_enc_casL(oldval, newval, mem_ptr), 5437 z_enc_cctobool(res)); 5438 ins_pipe(pipe_class_dummy); 5439 %} 5440 5441 instruct compareAndSwapP_bool(iRegP mem_ptr, rarg5RegP oldval, iRegP_N2P newval, iRegI res, flagsReg cr) %{ 5442 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 5443 effect(USE mem_ptr, USE_KILL oldval, KILL cr); 5444 size(18); 5445 format %{ "$res = CompareAndSwapP $oldval,$newval,$mem_ptr" %} 5446 ins_encode(z_enc_casL(oldval, newval, mem_ptr), 5447 z_enc_cctobool(res)); 5448 ins_pipe(pipe_class_dummy); 5449 %} 5450 5451 instruct compareAndSwapN_bool(iRegP mem_ptr, rarg5RegN oldval, iRegN_P2N newval, iRegI res, flagsReg cr) %{ 5452 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); 5453 effect(USE mem_ptr, USE_KILL oldval, KILL cr); 5454 size(16); 5455 format %{ "$res = CompareAndSwapN $oldval,$newval,$mem_ptr" %} 5456 ins_encode(z_enc_casI(oldval, newval, mem_ptr), 5457 z_enc_cctobool(res)); 5458 ins_pipe(pipe_class_dummy); 5459 %} 5460 5461 //----------Atomic operations on memory (GetAndSet*, GetAndAdd*)--------------- 5462 5463 // Exploit: direct memory arithmetic 5464 // Prereqs: - instructions available 5465 // - instructions guarantee atomicity 5466 // - immediate operand to be added 5467 // - immediate operand is small enough (8-bit signed). 5468 // - result of instruction is not used 5469 instruct addI_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immI8 src, flagsReg cr) %{ 5470 match(Set dummy (GetAndAddI mem src)); 5471 effect(KILL cr); 5472 predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used()); 5473 ins_cost(MEMORY_REF_COST); 5474 size(6); 5475 format %{ "ASI [$mem],$src\t # GetAndAddI (atomic)" %} 5476 opcode(ASI_ZOPC); 5477 ins_encode(z_siyform(mem, src)); 5478 ins_pipe(pipe_class_dummy); 5479 %} 5480 5481 // Fallback: direct memory arithmetic not available 5482 // Disadvantages: - CS-Loop required, very expensive. 5483 // - more code generated (26 to xx bytes vs. 6 bytes) 5484 instruct addI_mem_imm16_atomic(memoryRSY mem, iRegI dst, immI16 src, iRegI tmp, flagsReg cr) %{ 5485 match(Set dst (GetAndAddI mem src)); 5486 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5487 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); 5488 format %{ "BEGIN ATOMIC {\n\t" 5489 " LGF $dst,[$mem]\n\t" 5490 " AHIK $tmp,$dst,$src\n\t" 5491 " CSY $dst,$tmp,$mem\n\t" 5492 " retry if failed\n\t" 5493 "} END ATOMIC" 5494 %} 5495 ins_encode %{ 5496 Register Rdst = $dst$$Register; 5497 Register Rtmp = $tmp$$Register; 5498 int Isrc = $src$$constant; 5499 Label retry; 5500 5501 // Iterate until update with incremented value succeeds. 5502 __ z_lgf(Rdst, $mem$$Address); // current contents 5503 __ bind(retry); 5504 // Calculate incremented value. 5505 if (VM_Version::has_DistinctOpnds()) { 5506 __ z_ahik(Rtmp, Rdst, Isrc); 5507 } else { 5508 __ z_lr(Rtmp, Rdst); 5509 __ z_ahi(Rtmp, Isrc); 5510 } 5511 // Swap into memory location. 5512 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5513 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5514 %} 5515 ins_pipe(pipe_class_dummy); 5516 %} 5517 5518 instruct addI_mem_imm32_atomic(memoryRSY mem, iRegI dst, immI src, iRegI tmp, flagsReg cr) %{ 5519 match(Set dst (GetAndAddI mem src)); 5520 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5521 ins_cost(MEMORY_REF_COST+200*DEFAULT_COST); 5522 format %{ "BEGIN ATOMIC {\n\t" 5523 " LGF $dst,[$mem]\n\t" 5524 " LGR $tmp,$dst\n\t" 5525 " AFI $tmp,$src\n\t" 5526 " CSY $dst,$tmp,$mem\n\t" 5527 " retry if failed\n\t" 5528 "} END ATOMIC" 5529 %} 5530 ins_encode %{ 5531 Register Rdst = $dst$$Register; 5532 Register Rtmp = $tmp$$Register; 5533 int Isrc = $src$$constant; 5534 Label retry; 5535 5536 // Iterate until update with incremented value succeeds. 5537 __ z_lgf(Rdst, $mem$$Address); // current contents 5538 __ bind(retry); 5539 // Calculate incremented value. 5540 __ z_lr(Rtmp, Rdst); 5541 __ z_afi(Rtmp, Isrc); 5542 // Swap into memory location. 5543 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5544 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5545 %} 5546 ins_pipe(pipe_class_dummy); 5547 %} 5548 5549 instruct addI_mem_reg_atomic(memoryRSY mem, iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ 5550 match(Set dst (GetAndAddI mem src)); 5551 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5552 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); 5553 format %{ "BEGIN ATOMIC {\n\t" 5554 " LGF $dst,[$mem]\n\t" 5555 " ARK $tmp,$dst,$src\n\t" 5556 " CSY $dst,$tmp,$mem\n\t" 5557 " retry if failed\n\t" 5558 "} END ATOMIC" 5559 %} 5560 ins_encode %{ 5561 Register Rsrc = $src$$Register; 5562 Register Rdst = $dst$$Register; 5563 Register Rtmp = $tmp$$Register; 5564 Label retry; 5565 5566 // Iterate until update with incremented value succeeds. 5567 __ z_lgf(Rdst, $mem$$Address); // current contents 5568 __ bind(retry); 5569 // Calculate incremented value. 5570 if (VM_Version::has_DistinctOpnds()) { 5571 __ z_ark(Rtmp, Rdst, Rsrc); 5572 } else { 5573 __ z_lr(Rtmp, Rdst); 5574 __ z_ar(Rtmp, Rsrc); 5575 } 5576 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5577 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5578 %} 5579 ins_pipe(pipe_class_dummy); 5580 %} 5581 5582 5583 // Exploit: direct memory arithmetic 5584 // Prereqs: - instructions available 5585 // - instructions guarantee atomicity 5586 // - immediate operand to be added 5587 // - immediate operand is small enough (8-bit signed). 5588 // - result of instruction is not used 5589 instruct addL_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immL8 src, flagsReg cr) %{ 5590 match(Set dummy (GetAndAddL mem src)); 5591 effect(KILL cr); 5592 predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used()); 5593 ins_cost(MEMORY_REF_COST); 5594 size(6); 5595 format %{ "AGSI [$mem],$src\t # GetAndAddL (atomic)" %} 5596 opcode(AGSI_ZOPC); 5597 ins_encode(z_siyform(mem, src)); 5598 ins_pipe(pipe_class_dummy); 5599 %} 5600 5601 // Fallback: direct memory arithmetic not available 5602 // Disadvantages: - CS-Loop required, very expensive. 5603 // - more code generated (26 to xx bytes vs. 6 bytes) 5604 instruct addL_mem_imm16_atomic(memoryRSY mem, iRegL dst, immL16 src, iRegL tmp, flagsReg cr) %{ 5605 match(Set dst (GetAndAddL mem src)); 5606 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5607 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); 5608 format %{ "BEGIN ATOMIC {\n\t" 5609 " LG $dst,[$mem]\n\t" 5610 " AGHIK $tmp,$dst,$src\n\t" 5611 " CSG $dst,$tmp,$mem\n\t" 5612 " retry if failed\n\t" 5613 "} END ATOMIC" 5614 %} 5615 ins_encode %{ 5616 Register Rdst = $dst$$Register; 5617 Register Rtmp = $tmp$$Register; 5618 int Isrc = $src$$constant; 5619 Label retry; 5620 5621 // Iterate until update with incremented value succeeds. 5622 __ z_lg(Rdst, $mem$$Address); // current contents 5623 __ bind(retry); 5624 // Calculate incremented value. 5625 if (VM_Version::has_DistinctOpnds()) { 5626 __ z_aghik(Rtmp, Rdst, Isrc); 5627 } else { 5628 __ z_lgr(Rtmp, Rdst); 5629 __ z_aghi(Rtmp, Isrc); 5630 } 5631 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5632 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5633 %} 5634 ins_pipe(pipe_class_dummy); 5635 %} 5636 5637 instruct addL_mem_imm32_atomic(memoryRSY mem, iRegL dst, immL32 src, iRegL tmp, flagsReg cr) %{ 5638 match(Set dst (GetAndAddL mem src)); 5639 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5640 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); 5641 format %{ "BEGIN ATOMIC {\n\t" 5642 " LG $dst,[$mem]\n\t" 5643 " LGR $tmp,$dst\n\t" 5644 " AGFI $tmp,$src\n\t" 5645 " CSG $dst,$tmp,$mem\n\t" 5646 " retry if failed\n\t" 5647 "} END ATOMIC" 5648 %} 5649 ins_encode %{ 5650 Register Rdst = $dst$$Register; 5651 Register Rtmp = $tmp$$Register; 5652 int Isrc = $src$$constant; 5653 Label retry; 5654 5655 // Iterate until update with incremented value succeeds. 5656 __ z_lg(Rdst, $mem$$Address); // current contents 5657 __ bind(retry); 5658 // Calculate incremented value. 5659 __ z_lgr(Rtmp, Rdst); 5660 __ z_agfi(Rtmp, Isrc); 5661 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5662 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5663 %} 5664 ins_pipe(pipe_class_dummy); 5665 %} 5666 5667 instruct addL_mem_reg_atomic(memoryRSY mem, iRegL dst, iRegL src, iRegL tmp, flagsReg cr) %{ 5668 match(Set dst (GetAndAddL mem src)); 5669 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5670 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); 5671 format %{ "BEGIN ATOMIC {\n\t" 5672 " LG $dst,[$mem]\n\t" 5673 " AGRK $tmp,$dst,$src\n\t" 5674 " CSG $dst,$tmp,$mem\n\t" 5675 " retry if failed\n\t" 5676 "} END ATOMIC" 5677 %} 5678 ins_encode %{ 5679 Register Rsrc = $src$$Register; 5680 Register Rdst = $dst$$Register; 5681 Register Rtmp = $tmp$$Register; 5682 Label retry; 5683 5684 // Iterate until update with incremented value succeeds. 5685 __ z_lg(Rdst, $mem$$Address); // current contents 5686 __ bind(retry); 5687 // Calculate incremented value. 5688 if (VM_Version::has_DistinctOpnds()) { 5689 __ z_agrk(Rtmp, Rdst, Rsrc); 5690 } else { 5691 __ z_lgr(Rtmp, Rdst); 5692 __ z_agr(Rtmp, Rsrc); 5693 } 5694 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5695 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5696 %} 5697 ins_pipe(pipe_class_dummy); 5698 %} 5699 5700 // Increment value in memory, save old value in dst. 5701 instruct addI_mem_reg_atomic_z196(memoryRSY mem, iRegI dst, iRegI src) %{ 5702 match(Set dst (GetAndAddI mem src)); 5703 predicate(VM_Version::has_LoadAndALUAtomicV1()); 5704 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5705 size(6); 5706 format %{ "LAA $dst,$src,[$mem]" %} 5707 ins_encode %{ __ z_laa($dst$$Register, $src$$Register, $mem$$Address); %} 5708 ins_pipe(pipe_class_dummy); 5709 %} 5710 5711 // Increment value in memory, save old value in dst. 5712 instruct addL_mem_reg_atomic_z196(memoryRSY mem, iRegL dst, iRegL src) %{ 5713 match(Set dst (GetAndAddL mem src)); 5714 predicate(VM_Version::has_LoadAndALUAtomicV1()); 5715 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5716 size(6); 5717 format %{ "LAAG $dst,$src,[$mem]" %} 5718 ins_encode %{ __ z_laag($dst$$Register, $src$$Register, $mem$$Address); %} 5719 ins_pipe(pipe_class_dummy); 5720 %} 5721 5722 5723 instruct xchgI_reg_mem(memoryRSY mem, iRegI dst, iRegI tmp, flagsReg cr) %{ 5724 match(Set dst (GetAndSetI mem dst)); 5725 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule. 5726 format %{ "XCHGI $dst,[$mem]\t # EXCHANGE (int, atomic), temp $tmp" %} 5727 ins_encode(z_enc_SwapI(mem, dst, tmp)); 5728 ins_pipe(pipe_class_dummy); 5729 %} 5730 5731 instruct xchgL_reg_mem(memoryRSY mem, iRegL dst, iRegL tmp, flagsReg cr) %{ 5732 match(Set dst (GetAndSetL mem dst)); 5733 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule. 5734 format %{ "XCHGL $dst,[$mem]\t # EXCHANGE (long, atomic), temp $tmp" %} 5735 ins_encode(z_enc_SwapL(mem, dst, tmp)); 5736 ins_pipe(pipe_class_dummy); 5737 %} 5738 5739 instruct xchgN_reg_mem(memoryRSY mem, iRegN dst, iRegI tmp, flagsReg cr) %{ 5740 match(Set dst (GetAndSetN mem dst)); 5741 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule. 5742 format %{ "XCHGN $dst,[$mem]\t # EXCHANGE (coop, atomic), temp $tmp" %} 5743 ins_encode(z_enc_SwapI(mem, dst, tmp)); 5744 ins_pipe(pipe_class_dummy); 5745 %} 5746 5747 instruct xchgP_reg_mem(memoryRSY mem, iRegP dst, iRegL tmp, flagsReg cr) %{ 5748 match(Set dst (GetAndSetP mem dst)); 5749 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule. 5750 format %{ "XCHGP $dst,[$mem]\t # EXCHANGE (oop, atomic), temp $tmp" %} 5751 ins_encode(z_enc_SwapL(mem, dst, tmp)); 5752 ins_pipe(pipe_class_dummy); 5753 %} 5754 5755 5756 //----------Arithmetic Instructions-------------------------------------------- 5757 5758 // The rules are sorted by right operand type and operand length. Please keep 5759 // it that way. 5760 // Left operand type is always reg. Left operand len is I, L, P 5761 // Right operand type is reg, imm, mem. Right operand len is S, I, L, P 5762 // Special instruction formats, e.g. multi-operand, are inserted at the end. 5763 5764 // ADD 5765 5766 // REG = REG + REG 5767 5768 // Register Addition 5769 instruct addI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{ 5770 match(Set dst (AddI dst src)); 5771 effect(KILL cr); 5772 // TODO: s390 port size(FIXED_SIZE); 5773 format %{ "AR $dst,$src\t # int CISC ALU" %} 5774 opcode(AR_ZOPC); 5775 ins_encode(z_rrform(dst, src)); 5776 ins_pipe(pipe_class_dummy); 5777 %} 5778 5779 // Avoid use of LA(Y) for general ALU operation. 5780 instruct addI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 5781 match(Set dst (AddI src1 src2)); 5782 effect(KILL cr); 5783 predicate(VM_Version::has_DistinctOpnds()); 5784 ins_cost(DEFAULT_COST); 5785 size(4); 5786 format %{ "ARK $dst,$src1,$src2\t # int RISC ALU" %} 5787 opcode(ARK_ZOPC); 5788 ins_encode(z_rrfform(dst, src1, src2)); 5789 ins_pipe(pipe_class_dummy); 5790 %} 5791 5792 // REG = REG + IMM 5793 5794 // Avoid use of LA(Y) for general ALU operation. 5795 // Immediate Addition 5796 instruct addI_reg_imm16_CISC(iRegI dst, immI16 con, flagsReg cr) %{ 5797 match(Set dst (AddI dst con)); 5798 effect(KILL cr); 5799 ins_cost(DEFAULT_COST); 5800 // TODO: s390 port size(FIXED_SIZE); 5801 format %{ "AHI $dst,$con\t # int CISC ALU" %} 5802 opcode(AHI_ZOPC); 5803 ins_encode(z_riform_signed(dst, con)); 5804 ins_pipe(pipe_class_dummy); 5805 %} 5806 5807 // Avoid use of LA(Y) for general ALU operation. 5808 // Immediate Addition 5809 instruct addI_reg_imm16_RISC(iRegI dst, iRegI src, immI16 con, flagsReg cr) %{ 5810 match(Set dst (AddI src con)); 5811 effect(KILL cr); 5812 predicate( VM_Version::has_DistinctOpnds()); 5813 ins_cost(DEFAULT_COST); 5814 // TODO: s390 port size(FIXED_SIZE); 5815 format %{ "AHIK $dst,$src,$con\t # int RISC ALU" %} 5816 opcode(AHIK_ZOPC); 5817 ins_encode(z_rieform_d(dst, src, con)); 5818 ins_pipe(pipe_class_dummy); 5819 %} 5820 5821 // Immediate Addition 5822 instruct addI_reg_imm32(iRegI dst, immI src, flagsReg cr) %{ 5823 match(Set dst (AddI dst src)); 5824 effect(KILL cr); 5825 ins_cost(DEFAULT_COST_HIGH); 5826 size(6); 5827 format %{ "AFI $dst,$src" %} 5828 opcode(AFI_ZOPC); 5829 ins_encode(z_rilform_signed(dst, src)); 5830 ins_pipe(pipe_class_dummy); 5831 %} 5832 5833 // Immediate Addition 5834 instruct addI_reg_imm12(iRegI dst, iRegI src, uimmI12 con) %{ 5835 match(Set dst (AddI src con)); 5836 predicate(PreferLAoverADD); 5837 ins_cost(DEFAULT_COST_LOW); 5838 size(4); 5839 format %{ "LA $dst,$con(,$src)\t # int d12(,b)" %} 5840 opcode(LA_ZOPC); 5841 ins_encode(z_rxform_imm_reg(dst, con, src)); 5842 ins_pipe(pipe_class_dummy); 5843 %} 5844 5845 // Immediate Addition 5846 instruct addI_reg_imm20(iRegI dst, iRegI src, immI20 con) %{ 5847 match(Set dst (AddI src con)); 5848 predicate(PreferLAoverADD); 5849 ins_cost(DEFAULT_COST); 5850 size(6); 5851 format %{ "LAY $dst,$con(,$src)\t # int d20(,b)" %} 5852 opcode(LAY_ZOPC); 5853 ins_encode(z_rxyform_imm_reg(dst, con, src)); 5854 ins_pipe(pipe_class_dummy); 5855 %} 5856 5857 instruct addI_reg_reg_imm12(iRegI dst, iRegI src1, iRegI src2, uimmI12 con) %{ 5858 match(Set dst (AddI (AddI src1 src2) con)); 5859 predicate( PreferLAoverADD); 5860 ins_cost(DEFAULT_COST_LOW); 5861 size(4); 5862 format %{ "LA $dst,$con($src1,$src2)\t # int d12(x,b)" %} 5863 opcode(LA_ZOPC); 5864 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2)); 5865 ins_pipe(pipe_class_dummy); 5866 %} 5867 5868 instruct addI_reg_reg_imm20(iRegI dst, iRegI src1, iRegI src2, immI20 con) %{ 5869 match(Set dst (AddI (AddI src1 src2) con)); 5870 predicate(PreferLAoverADD); 5871 ins_cost(DEFAULT_COST); 5872 size(6); 5873 format %{ "LAY $dst,$con($src1,$src2)\t # int d20(x,b)" %} 5874 opcode(LAY_ZOPC); 5875 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2)); 5876 ins_pipe(pipe_class_dummy); 5877 %} 5878 5879 // REG = REG + MEM 5880 5881 instruct addI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{ 5882 match(Set dst (AddI dst (LoadI src))); 5883 effect(KILL cr); 5884 ins_cost(MEMORY_REF_COST); 5885 // TODO: s390 port size(VARIABLE_SIZE); 5886 format %{ "A(Y) $dst, $src\t # int" %} 5887 opcode(AY_ZOPC, A_ZOPC); 5888 ins_encode(z_form_rt_mem_opt(dst, src)); 5889 ins_pipe(pipe_class_dummy); 5890 %} 5891 5892 // MEM = MEM + IMM 5893 5894 // Add Immediate to 4-byte memory operand and result 5895 instruct addI_mem_imm(memoryRSY mem, immI8 src, flagsReg cr) %{ 5896 match(Set mem (StoreI mem (AddI (LoadI mem) src))); 5897 effect(KILL cr); 5898 predicate(VM_Version::has_MemWithImmALUOps()); 5899 ins_cost(MEMORY_REF_COST); 5900 size(6); 5901 format %{ "ASI $mem,$src\t # direct mem add 4" %} 5902 opcode(ASI_ZOPC); 5903 ins_encode(z_siyform(mem, src)); 5904 ins_pipe(pipe_class_dummy); 5905 %} 5906 5907 5908 // 5909 5910 // REG = REG + REG 5911 5912 instruct addL_reg_regI(iRegL dst, iRegI src, flagsReg cr) %{ 5913 match(Set dst (AddL dst (ConvI2L src))); 5914 effect(KILL cr); 5915 size(4); 5916 format %{ "AGFR $dst,$src\t # long<-int CISC ALU" %} 5917 opcode(AGFR_ZOPC); 5918 ins_encode(z_rreform(dst, src)); 5919 ins_pipe(pipe_class_dummy); 5920 %} 5921 5922 instruct addL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{ 5923 match(Set dst (AddL dst src)); 5924 effect(KILL cr); 5925 // TODO: s390 port size(FIXED_SIZE); 5926 format %{ "AGR $dst, $src\t # long CISC ALU" %} 5927 opcode(AGR_ZOPC); 5928 ins_encode(z_rreform(dst, src)); 5929 ins_pipe(pipe_class_dummy); 5930 %} 5931 5932 // Avoid use of LA(Y) for general ALU operation. 5933 instruct addL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ 5934 match(Set dst (AddL src1 src2)); 5935 effect(KILL cr); 5936 predicate(VM_Version::has_DistinctOpnds()); 5937 ins_cost(DEFAULT_COST); 5938 size(4); 5939 format %{ "AGRK $dst,$src1,$src2\t # long RISC ALU" %} 5940 opcode(AGRK_ZOPC); 5941 ins_encode(z_rrfform(dst, src1, src2)); 5942 ins_pipe(pipe_class_dummy); 5943 %} 5944 5945 // REG = REG + IMM 5946 5947 instruct addL_reg_imm12(iRegL dst, iRegL src, uimmL12 con) %{ 5948 match(Set dst (AddL src con)); 5949 predicate( PreferLAoverADD); 5950 ins_cost(DEFAULT_COST_LOW); 5951 size(4); 5952 format %{ "LA $dst,$con(,$src)\t # long d12(,b)" %} 5953 opcode(LA_ZOPC); 5954 ins_encode(z_rxform_imm_reg(dst, con, src)); 5955 ins_pipe(pipe_class_dummy); 5956 %} 5957 5958 instruct addL_reg_imm20(iRegL dst, iRegL src, immL20 con) %{ 5959 match(Set dst (AddL src con)); 5960 predicate(PreferLAoverADD); 5961 ins_cost(DEFAULT_COST); 5962 size(6); 5963 format %{ "LAY $dst,$con(,$src)\t # long d20(,b)" %} 5964 opcode(LAY_ZOPC); 5965 ins_encode(z_rxyform_imm_reg(dst, con, src)); 5966 ins_pipe(pipe_class_dummy); 5967 %} 5968 5969 instruct addL_reg_imm32(iRegL dst, immL32 con, flagsReg cr) %{ 5970 match(Set dst (AddL dst con)); 5971 effect(KILL cr); 5972 ins_cost(DEFAULT_COST_HIGH); 5973 size(6); 5974 format %{ "AGFI $dst,$con\t # long CISC ALU" %} 5975 opcode(AGFI_ZOPC); 5976 ins_encode(z_rilform_signed(dst, con)); 5977 ins_pipe(pipe_class_dummy); 5978 %} 5979 5980 // Avoid use of LA(Y) for general ALU operation. 5981 instruct addL_reg_imm16_CISC(iRegL dst, immL16 con, flagsReg cr) %{ 5982 match(Set dst (AddL dst con)); 5983 effect(KILL cr); 5984 ins_cost(DEFAULT_COST); 5985 // TODO: s390 port size(FIXED_SIZE); 5986 format %{ "AGHI $dst,$con\t # long CISC ALU" %} 5987 opcode(AGHI_ZOPC); 5988 ins_encode(z_riform_signed(dst, con)); 5989 ins_pipe(pipe_class_dummy); 5990 %} 5991 5992 // Avoid use of LA(Y) for general ALU operation. 5993 instruct addL_reg_imm16_RISC(iRegL dst, iRegL src, immL16 con, flagsReg cr) %{ 5994 match(Set dst (AddL src con)); 5995 effect(KILL cr); 5996 predicate( VM_Version::has_DistinctOpnds()); 5997 ins_cost(DEFAULT_COST); 5998 size(6); 5999 format %{ "AGHIK $dst,$src,$con\t # long RISC ALU" %} 6000 opcode(AGHIK_ZOPC); 6001 ins_encode(z_rieform_d(dst, src, con)); 6002 ins_pipe(pipe_class_dummy); 6003 %} 6004 6005 // REG = REG + MEM 6006 6007 instruct addL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{ 6008 match(Set dst (AddL dst (ConvI2L (LoadI src)))); 6009 effect(KILL cr); 6010 ins_cost(MEMORY_REF_COST); 6011 size(Z_DISP3_SIZE); 6012 format %{ "AGF $dst, $src\t # long/int" %} 6013 opcode(AGF_ZOPC, AGF_ZOPC); 6014 ins_encode(z_form_rt_mem_opt(dst, src)); 6015 ins_pipe(pipe_class_dummy); 6016 %} 6017 6018 instruct addL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{ 6019 match(Set dst (AddL dst (LoadL src))); 6020 effect(KILL cr); 6021 ins_cost(MEMORY_REF_COST); 6022 size(Z_DISP3_SIZE); 6023 format %{ "AG $dst, $src\t # long" %} 6024 opcode(AG_ZOPC, AG_ZOPC); 6025 ins_encode(z_form_rt_mem_opt(dst, src)); 6026 ins_pipe(pipe_class_dummy); 6027 %} 6028 6029 instruct addL_reg_reg_imm12(iRegL dst, iRegL src1, iRegL src2, uimmL12 con) %{ 6030 match(Set dst (AddL (AddL src1 src2) con)); 6031 predicate( PreferLAoverADD); 6032 ins_cost(DEFAULT_COST_LOW); 6033 size(4); 6034 format %{ "LA $dst,$con($src1,$src2)\t # long d12(x,b)" %} 6035 opcode(LA_ZOPC); 6036 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2)); 6037 ins_pipe(pipe_class_dummy); 6038 %} 6039 6040 instruct addL_reg_reg_imm20(iRegL dst, iRegL src1, iRegL src2, immL20 con) %{ 6041 match(Set dst (AddL (AddL src1 src2) con)); 6042 predicate(PreferLAoverADD); 6043 ins_cost(DEFAULT_COST); 6044 size(6); 6045 format %{ "LAY $dst,$con($src1,$src2)\t # long d20(x,b)" %} 6046 opcode(LAY_ZOPC); 6047 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2)); 6048 ins_pipe(pipe_class_dummy); 6049 %} 6050 6051 // MEM = MEM + IMM 6052 6053 // Add Immediate to 8-byte memory operand and result. 6054 instruct addL_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{ 6055 match(Set mem (StoreL mem (AddL (LoadL mem) src))); 6056 effect(KILL cr); 6057 predicate(VM_Version::has_MemWithImmALUOps()); 6058 ins_cost(MEMORY_REF_COST); 6059 size(6); 6060 format %{ "AGSI $mem,$src\t # direct mem add 8" %} 6061 opcode(AGSI_ZOPC); 6062 ins_encode(z_siyform(mem, src)); 6063 ins_pipe(pipe_class_dummy); 6064 %} 6065 6066 6067 // REG = REG + REG 6068 6069 // Ptr Addition 6070 instruct addP_reg_reg_LA(iRegP dst, iRegP_N2P src1, iRegL src2) %{ 6071 match(Set dst (AddP src1 src2)); 6072 predicate( PreferLAoverADD); 6073 ins_cost(DEFAULT_COST); 6074 size(4); 6075 format %{ "LA $dst,#0($src1,$src2)\t # ptr 0(x,b)" %} 6076 opcode(LA_ZOPC); 6077 ins_encode(z_rxform_imm_reg_reg(dst, 0x0, src1, src2)); 6078 ins_pipe(pipe_class_dummy); 6079 %} 6080 6081 // Ptr Addition 6082 // Avoid use of LA(Y) for general ALU operation. 6083 instruct addP_reg_reg_CISC(iRegP dst, iRegL src, flagsReg cr) %{ 6084 match(Set dst (AddP dst src)); 6085 effect(KILL cr); 6086 predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds()); 6087 ins_cost(DEFAULT_COST); 6088 // TODO: s390 port size(FIXED_SIZE); 6089 format %{ "ALGR $dst,$src\t # ptr CICS ALU" %} 6090 opcode(ALGR_ZOPC); 6091 ins_encode(z_rreform(dst, src)); 6092 ins_pipe(pipe_class_dummy); 6093 %} 6094 6095 // Ptr Addition 6096 // Avoid use of LA(Y) for general ALU operation. 6097 instruct addP_reg_reg_RISC(iRegP dst, iRegP_N2P src1, iRegL src2, flagsReg cr) %{ 6098 match(Set dst (AddP src1 src2)); 6099 effect(KILL cr); 6100 predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds()); 6101 ins_cost(DEFAULT_COST); 6102 // TODO: s390 port size(FIXED_SIZE); 6103 format %{ "ALGRK $dst,$src1,$src2\t # ptr RISC ALU" %} 6104 opcode(ALGRK_ZOPC); 6105 ins_encode(z_rrfform(dst, src1, src2)); 6106 ins_pipe(pipe_class_dummy); 6107 %} 6108 6109 // REG = REG + IMM 6110 6111 instruct addP_reg_imm12(iRegP dst, iRegP_N2P src, uimmL12 con) %{ 6112 match(Set dst (AddP src con)); 6113 predicate( PreferLAoverADD); 6114 ins_cost(DEFAULT_COST_LOW); 6115 size(4); 6116 format %{ "LA $dst,$con(,$src)\t # ptr d12(,b)" %} 6117 opcode(LA_ZOPC); 6118 ins_encode(z_rxform_imm_reg(dst, con, src)); 6119 ins_pipe(pipe_class_dummy); 6120 %} 6121 6122 // Avoid use of LA(Y) for general ALU operation. 6123 instruct addP_reg_imm16_CISC(iRegP dst, immL16 src, flagsReg cr) %{ 6124 match(Set dst (AddP dst src)); 6125 effect(KILL cr); 6126 predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds()); 6127 ins_cost(DEFAULT_COST); 6128 // TODO: s390 port size(FIXED_SIZE); 6129 format %{ "AGHI $dst,$src\t # ptr CISC ALU" %} 6130 opcode(AGHI_ZOPC); 6131 ins_encode(z_riform_signed(dst, src)); 6132 ins_pipe(pipe_class_dummy); 6133 %} 6134 6135 // Avoid use of LA(Y) for general ALU operation. 6136 instruct addP_reg_imm16_RISC(iRegP dst, iRegP_N2P src, immL16 con, flagsReg cr) %{ 6137 match(Set dst (AddP src con)); 6138 effect(KILL cr); 6139 predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds()); 6140 ins_cost(DEFAULT_COST); 6141 // TODO: s390 port size(FIXED_SIZE); 6142 format %{ "ALGHSIK $dst,$src,$con\t # ptr RISC ALU" %} 6143 opcode(ALGHSIK_ZOPC); 6144 ins_encode(z_rieform_d(dst, src, con)); 6145 ins_pipe(pipe_class_dummy); 6146 %} 6147 6148 instruct addP_reg_imm20(iRegP dst, memoryRegP src, immL20 con) %{ 6149 match(Set dst (AddP src con)); 6150 predicate(PreferLAoverADD); 6151 ins_cost(DEFAULT_COST); 6152 size(6); 6153 format %{ "LAY $dst,$con(,$src)\t # ptr d20(,b)" %} 6154 opcode(LAY_ZOPC); 6155 ins_encode(z_rxyform_imm_reg(dst, con, src)); 6156 ins_pipe(pipe_class_dummy); 6157 %} 6158 6159 // Pointer Immediate Addition 6160 instruct addP_reg_imm32(iRegP dst, immL32 src, flagsReg cr) %{ 6161 match(Set dst (AddP dst src)); 6162 effect(KILL cr); 6163 ins_cost(DEFAULT_COST_HIGH); 6164 // TODO: s390 port size(FIXED_SIZE); 6165 format %{ "AGFI $dst,$src\t # ptr" %} 6166 opcode(AGFI_ZOPC); 6167 ins_encode(z_rilform_signed(dst, src)); 6168 ins_pipe(pipe_class_dummy); 6169 %} 6170 6171 // REG = REG1 + REG2 + IMM 6172 6173 instruct addP_reg_reg_imm12(iRegP dst, memoryRegP src1, iRegL src2, uimmL12 con) %{ 6174 match(Set dst (AddP (AddP src1 src2) con)); 6175 predicate( PreferLAoverADD); 6176 ins_cost(DEFAULT_COST_LOW); 6177 size(4); 6178 format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %} 6179 opcode(LA_ZOPC); 6180 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2)); 6181 ins_pipe(pipe_class_dummy); 6182 %} 6183 6184 instruct addP_regN_reg_imm12(iRegP dst, iRegP_N2P src1, iRegL src2, uimmL12 con) %{ 6185 match(Set dst (AddP (AddP src1 src2) con)); 6186 predicate( PreferLAoverADD && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0); 6187 ins_cost(DEFAULT_COST_LOW); 6188 size(4); 6189 format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %} 6190 opcode(LA_ZOPC); 6191 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2)); 6192 ins_pipe(pipe_class_dummy); 6193 %} 6194 6195 instruct addP_reg_reg_imm20(iRegP dst, memoryRegP src1, iRegL src2, immL20 con) %{ 6196 match(Set dst (AddP (AddP src1 src2) con)); 6197 predicate(PreferLAoverADD); 6198 ins_cost(DEFAULT_COST); 6199 // TODO: s390 port size(FIXED_SIZE); 6200 format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %} 6201 opcode(LAY_ZOPC); 6202 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2)); 6203 ins_pipe(pipe_class_dummy); 6204 %} 6205 6206 instruct addP_regN_reg_imm20(iRegP dst, iRegP_N2P src1, iRegL src2, immL20 con) %{ 6207 match(Set dst (AddP (AddP src1 src2) con)); 6208 predicate( PreferLAoverADD && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0); 6209 ins_cost(DEFAULT_COST); 6210 // TODO: s390 port size(FIXED_SIZE); 6211 format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %} 6212 opcode(LAY_ZOPC); 6213 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2)); 6214 ins_pipe(pipe_class_dummy); 6215 %} 6216 6217 // MEM = MEM + IMM 6218 6219 // Add Immediate to 8-byte memory operand and result 6220 instruct addP_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{ 6221 match(Set mem (StoreP mem (AddP (LoadP mem) src))); 6222 effect(KILL cr); 6223 predicate(VM_Version::has_MemWithImmALUOps()); 6224 ins_cost(MEMORY_REF_COST); 6225 size(6); 6226 format %{ "AGSI $mem,$src\t # direct mem add 8 (ptr)" %} 6227 opcode(AGSI_ZOPC); 6228 ins_encode(z_siyform(mem, src)); 6229 ins_pipe(pipe_class_dummy); 6230 %} 6231 6232 // SUB 6233 6234 // Register Subtraction 6235 instruct subI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{ 6236 match(Set dst (SubI dst src)); 6237 effect(KILL cr); 6238 // TODO: s390 port size(FIXED_SIZE); 6239 format %{ "SR $dst,$src\t # int CISC ALU" %} 6240 opcode(SR_ZOPC); 6241 ins_encode(z_rrform(dst, src)); 6242 ins_pipe(pipe_class_dummy); 6243 %} 6244 6245 instruct subI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 6246 match(Set dst (SubI src1 src2)); 6247 effect(KILL cr); 6248 predicate(VM_Version::has_DistinctOpnds()); 6249 ins_cost(DEFAULT_COST); 6250 size(4); 6251 format %{ "SRK $dst,$src1,$src2\t # int RISC ALU" %} 6252 opcode(SRK_ZOPC); 6253 ins_encode(z_rrfform(dst, src1, src2)); 6254 ins_pipe(pipe_class_dummy); 6255 %} 6256 6257 instruct subI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{ 6258 match(Set dst (SubI dst (LoadI src))); 6259 effect(KILL cr); 6260 ins_cost(MEMORY_REF_COST); 6261 // TODO: s390 port size(VARIABLE_SIZE); 6262 format %{ "S(Y) $dst, $src\t # int" %} 6263 opcode(SY_ZOPC, S_ZOPC); 6264 ins_encode(z_form_rt_mem_opt(dst, src)); 6265 ins_pipe(pipe_class_dummy); 6266 %} 6267 6268 instruct subI_zero_reg(iRegI dst, immI_0 zero, iRegI src, flagsReg cr) %{ 6269 match(Set dst (SubI zero src)); 6270 effect(KILL cr); 6271 size(2); 6272 format %{ "NEG $dst, $src" %} 6273 ins_encode %{ __ z_lcr($dst$$Register, $src$$Register); %} 6274 ins_pipe(pipe_class_dummy); 6275 %} 6276 6277 // 6278 6279 // Long subtraction 6280 instruct subL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{ 6281 match(Set dst (SubL dst src)); 6282 effect(KILL cr); 6283 // TODO: s390 port size(FIXED_SIZE); 6284 format %{ "SGR $dst,$src\t # int CISC ALU" %} 6285 opcode(SGR_ZOPC); 6286 ins_encode(z_rreform(dst, src)); 6287 ins_pipe(pipe_class_dummy); 6288 %} 6289 6290 // Avoid use of LA(Y) for general ALU operation. 6291 instruct subL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ 6292 match(Set dst (SubL src1 src2)); 6293 effect(KILL cr); 6294 predicate(VM_Version::has_DistinctOpnds()); 6295 ins_cost(DEFAULT_COST); 6296 size(4); 6297 format %{ "SGRK $dst,$src1,$src2\t # int RISC ALU" %} 6298 opcode(SGRK_ZOPC); 6299 ins_encode(z_rrfform(dst, src1, src2)); 6300 ins_pipe(pipe_class_dummy); 6301 %} 6302 6303 instruct subL_reg_regI_CISC(iRegL dst, iRegI src, flagsReg cr) %{ 6304 match(Set dst (SubL dst (ConvI2L src))); 6305 effect(KILL cr); 6306 size(4); 6307 format %{ "SGFR $dst, $src\t # int CISC ALU" %} 6308 opcode(SGFR_ZOPC); 6309 ins_encode(z_rreform(dst, src)); 6310 ins_pipe(pipe_class_dummy); 6311 %} 6312 6313 instruct subL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{ 6314 match(Set dst (SubL dst (ConvI2L (LoadI src)))); 6315 effect(KILL cr); 6316 ins_cost(MEMORY_REF_COST); 6317 size(Z_DISP3_SIZE); 6318 format %{ "SGF $dst, $src\t # long/int" %} 6319 opcode(SGF_ZOPC, SGF_ZOPC); 6320 ins_encode(z_form_rt_mem_opt(dst, src)); 6321 ins_pipe(pipe_class_dummy); 6322 %} 6323 6324 instruct subL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{ 6325 match(Set dst (SubL dst (LoadL src))); 6326 effect(KILL cr); 6327 ins_cost(MEMORY_REF_COST); 6328 size(Z_DISP3_SIZE); 6329 format %{ "SG $dst, $src\t # long" %} 6330 opcode(SG_ZOPC, SG_ZOPC); 6331 ins_encode(z_form_rt_mem_opt(dst, src)); 6332 ins_pipe(pipe_class_dummy); 6333 %} 6334 6335 // Moved declaration of negL_reg_reg before encode nodes, where it is used. 6336 6337 // MUL 6338 6339 // Register Multiplication 6340 instruct mulI_reg_reg(iRegI dst, iRegI src) %{ 6341 match(Set dst (MulI dst src)); 6342 ins_cost(DEFAULT_COST); 6343 size(4); 6344 format %{ "MSR $dst, $src" %} 6345 opcode(MSR_ZOPC); 6346 ins_encode(z_rreform(dst, src)); 6347 ins_pipe(pipe_class_dummy); 6348 %} 6349 6350 // Immediate Multiplication 6351 instruct mulI_reg_imm16(iRegI dst, immI16 con) %{ 6352 match(Set dst (MulI dst con)); 6353 ins_cost(DEFAULT_COST); 6354 // TODO: s390 port size(FIXED_SIZE); 6355 format %{ "MHI $dst,$con" %} 6356 opcode(MHI_ZOPC); 6357 ins_encode(z_riform_signed(dst,con)); 6358 ins_pipe(pipe_class_dummy); 6359 %} 6360 6361 // Immediate (32bit) Multiplication 6362 instruct mulI_reg_imm32(iRegI dst, immI con) %{ 6363 match(Set dst (MulI dst con)); 6364 ins_cost(DEFAULT_COST); 6365 size(6); 6366 format %{ "MSFI $dst,$con" %} 6367 opcode(MSFI_ZOPC); 6368 ins_encode(z_rilform_signed(dst,con)); 6369 ins_pipe(pipe_class_dummy); 6370 %} 6371 6372 instruct mulI_Reg_mem(iRegI dst, memory src)%{ 6373 match(Set dst (MulI dst (LoadI src))); 6374 ins_cost(MEMORY_REF_COST); 6375 // TODO: s390 port size(VARIABLE_SIZE); 6376 format %{ "MS(Y) $dst, $src\t # int" %} 6377 opcode(MSY_ZOPC, MS_ZOPC); 6378 ins_encode(z_form_rt_mem_opt(dst, src)); 6379 ins_pipe(pipe_class_dummy); 6380 %} 6381 6382 // 6383 6384 instruct mulL_reg_regI(iRegL dst, iRegI src) %{ 6385 match(Set dst (MulL dst (ConvI2L src))); 6386 ins_cost(DEFAULT_COST); 6387 // TODO: s390 port size(FIXED_SIZE); 6388 format %{ "MSGFR $dst $src\t # long/int" %} 6389 opcode(MSGFR_ZOPC); 6390 ins_encode(z_rreform(dst, src)); 6391 ins_pipe(pipe_class_dummy); 6392 %} 6393 6394 instruct mulL_reg_reg(iRegL dst, iRegL src) %{ 6395 match(Set dst (MulL dst src)); 6396 ins_cost(DEFAULT_COST); 6397 size(4); 6398 format %{ "MSGR $dst $src\t # long" %} 6399 opcode(MSGR_ZOPC); 6400 ins_encode(z_rreform(dst, src)); 6401 ins_pipe(pipe_class_dummy); 6402 %} 6403 6404 // Immediate Multiplication 6405 instruct mulL_reg_imm16(iRegL dst, immL16 src) %{ 6406 match(Set dst (MulL dst src)); 6407 ins_cost(DEFAULT_COST); 6408 // TODO: s390 port size(FIXED_SIZE); 6409 format %{ "MGHI $dst,$src\t # long" %} 6410 opcode(MGHI_ZOPC); 6411 ins_encode(z_riform_signed(dst, src)); 6412 ins_pipe(pipe_class_dummy); 6413 %} 6414 6415 // Immediate (32bit) Multiplication 6416 instruct mulL_reg_imm32(iRegL dst, immL32 con) %{ 6417 match(Set dst (MulL dst con)); 6418 ins_cost(DEFAULT_COST); 6419 size(6); 6420 format %{ "MSGFI $dst,$con" %} 6421 opcode(MSGFI_ZOPC); 6422 ins_encode(z_rilform_signed(dst,con)); 6423 ins_pipe(pipe_class_dummy); 6424 %} 6425 6426 instruct mulL_Reg_memI(iRegL dst, memory src)%{ 6427 match(Set dst (MulL dst (ConvI2L (LoadI src)))); 6428 ins_cost(MEMORY_REF_COST); 6429 size(Z_DISP3_SIZE); 6430 format %{ "MSGF $dst, $src\t # long" %} 6431 opcode(MSGF_ZOPC, MSGF_ZOPC); 6432 ins_encode(z_form_rt_mem_opt(dst, src)); 6433 ins_pipe(pipe_class_dummy); 6434 %} 6435 6436 instruct mulL_Reg_mem(iRegL dst, memory src)%{ 6437 match(Set dst (MulL dst (LoadL src))); 6438 ins_cost(MEMORY_REF_COST); 6439 size(Z_DISP3_SIZE); 6440 format %{ "MSG $dst, $src\t # long" %} 6441 opcode(MSG_ZOPC, MSG_ZOPC); 6442 ins_encode(z_form_rt_mem_opt(dst, src)); 6443 ins_pipe(pipe_class_dummy); 6444 %} 6445 6446 instruct mulHiL_reg_reg(revenRegL Rdst, roddRegL Rsrc1, iRegL Rsrc2, iRegL Rtmp1, flagsReg cr)%{ 6447 match(Set Rdst (MulHiL Rsrc1 Rsrc2)); 6448 effect(TEMP_DEF Rdst, USE_KILL Rsrc1, TEMP Rtmp1, KILL cr); 6449 ins_cost(7*DEFAULT_COST); 6450 // TODO: s390 port size(VARIABLE_SIZE); 6451 format %{ "MulHiL $Rdst, $Rsrc1, $Rsrc2\t # Multiply High Long" %} 6452 ins_encode%{ 6453 Register dst = $Rdst$$Register; 6454 Register src1 = $Rsrc1$$Register; 6455 Register src2 = $Rsrc2$$Register; 6456 Register tmp1 = $Rtmp1$$Register; 6457 Register tmp2 = $Rdst$$Register; 6458 // z/Architecture has only unsigned multiply (64 * 64 -> 128). 6459 // implementing mulhs(a,b) = mulhu(a,b) – (a & (b>>63)) – (b & (a>>63)) 6460 __ z_srag(tmp2, src1, 63); // a>>63 6461 __ z_srag(tmp1, src2, 63); // b>>63 6462 __ z_ngr(tmp2, src2); // b & (a>>63) 6463 __ z_ngr(tmp1, src1); // a & (b>>63) 6464 __ z_agr(tmp1, tmp2); // ((a & (b>>63)) + (b & (a>>63))) 6465 __ z_mlgr(dst, src2); // tricky: 128-bit product is written to even/odd pair (dst,src1), 6466 // multiplicand is taken from oddReg (src1), multiplier in src2. 6467 __ z_sgr(dst, tmp1); 6468 %} 6469 ins_pipe(pipe_class_dummy); 6470 %} 6471 6472 // DIV 6473 6474 // Integer DIVMOD with Register, both quotient and mod results 6475 instruct divModI_reg_divmod(roddRegI dst1src1, revenRegI dst2, noOdd_iRegI src2, flagsReg cr) %{ 6476 match(DivModI dst1src1 src2); 6477 effect(KILL cr); 6478 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6479 size(VM_Version::has_CompareBranch() ? 24 : 26); 6480 format %{ "DIVMODI ($dst1src1, $dst2) $src2" %} 6481 ins_encode %{ 6482 Register d1s1 = $dst1src1$$Register; 6483 Register d2 = $dst2$$Register; 6484 Register s2 = $src2$$Register; 6485 6486 assert_different_registers(d1s1, s2); 6487 6488 Label do_div, done_div; 6489 if (VM_Version::has_CompareBranch()) { 6490 __ z_cij(s2, -1, Assembler::bcondNotEqual, do_div); 6491 } else { 6492 __ z_chi(s2, -1); 6493 __ z_brne(do_div); 6494 } 6495 __ z_lcr(d1s1, d1s1); 6496 __ clear_reg(d2, false, false); 6497 __ z_bru(done_div); 6498 __ bind(do_div); 6499 __ z_lgfr(d1s1, d1s1); 6500 __ z_dsgfr(d2, s2); 6501 __ bind(done_div); 6502 %} 6503 ins_pipe(pipe_class_dummy); 6504 %} 6505 6506 6507 // Register Division 6508 instruct divI_reg_reg(roddRegI dst, iRegI src1, noOdd_iRegI src2, revenRegI tmp, flagsReg cr) %{ 6509 match(Set dst (DivI src1 src2)); 6510 effect(KILL tmp, KILL cr); 6511 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6512 size(VM_Version::has_CompareBranch() ? 20 : 22); 6513 format %{ "DIV_checked $dst, $src1,$src2\t # treats special case 0x80../-1" %} 6514 ins_encode %{ 6515 Register a = $src1$$Register; 6516 Register b = $src2$$Register; 6517 Register t = $dst$$Register; 6518 6519 assert_different_registers(t, b); 6520 6521 Label do_div, done_div; 6522 if (VM_Version::has_CompareBranch()) { 6523 __ z_cij(b, -1, Assembler::bcondNotEqual, do_div); 6524 } else { 6525 __ z_chi(b, -1); 6526 __ z_brne(do_div); 6527 } 6528 __ z_lcr(t, a); 6529 __ z_bru(done_div); 6530 __ bind(do_div); 6531 __ z_lgfr(t, a); 6532 __ z_dsgfr(t->predecessor()/* t is odd part of a register pair. */, b); 6533 __ bind(done_div); 6534 %} 6535 ins_pipe(pipe_class_dummy); 6536 %} 6537 6538 // Immediate Division 6539 instruct divI_reg_imm16(roddRegI dst, iRegI src1, immI16 src2, revenRegI tmp, flagsReg cr) %{ 6540 match(Set dst (DivI src1 src2)); 6541 effect(KILL tmp, KILL cr); // R0 is killed, too. 6542 ins_cost(2 * DEFAULT_COST); 6543 // TODO: s390 port size(VARIABLE_SIZE); 6544 format %{ "DIV_const $dst,$src1,$src2" %} 6545 ins_encode %{ 6546 // No sign extension of Rdividend needed here. 6547 if ($src2$$constant != -1) { 6548 __ z_lghi(Z_R0_scratch, $src2$$constant); 6549 __ z_lgfr($dst$$Register, $src1$$Register); 6550 __ z_dsgfr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch); 6551 } else { 6552 __ z_lcr($dst$$Register, $src1$$Register); 6553 } 6554 %} 6555 ins_pipe(pipe_class_dummy); 6556 %} 6557 6558 // Long DIVMOD with Register, both quotient and mod results 6559 instruct divModL_reg_divmod(roddRegL dst1src1, revenRegL dst2, iRegL src2, flagsReg cr) %{ 6560 match(DivModL dst1src1 src2); 6561 effect(KILL cr); 6562 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6563 size(VM_Version::has_CompareBranch() ? 22 : 24); 6564 format %{ "DIVMODL ($dst1src1, $dst2) $src2" %} 6565 ins_encode %{ 6566 Register d1s1 = $dst1src1$$Register; 6567 Register d2 = $dst2$$Register; 6568 Register s2 = $src2$$Register; 6569 6570 Label do_div, done_div; 6571 if (VM_Version::has_CompareBranch()) { 6572 __ z_cgij(s2, -1, Assembler::bcondNotEqual, do_div); 6573 } else { 6574 __ z_cghi(s2, -1); 6575 __ z_brne(do_div); 6576 } 6577 __ z_lcgr(d1s1, d1s1); 6578 // indicate unused result 6579 (void) __ clear_reg(d2, true, false); 6580 __ z_bru(done_div); 6581 __ bind(do_div); 6582 __ z_dsgr(d2, s2); 6583 __ bind(done_div); 6584 %} 6585 ins_pipe(pipe_class_dummy); 6586 %} 6587 6588 // Register Long Division 6589 instruct divL_reg_reg(roddRegL dst, iRegL src, revenRegL tmp, flagsReg cr) %{ 6590 match(Set dst (DivL dst src)); 6591 effect(KILL tmp, KILL cr); 6592 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6593 size(VM_Version::has_CompareBranch() ? 18 : 20); 6594 format %{ "DIVG_checked $dst, $src\t # long, treats special case 0x80../-1" %} 6595 ins_encode %{ 6596 Register b = $src$$Register; 6597 Register t = $dst$$Register; 6598 6599 Label done_div; 6600 __ z_lcgr(t, t); // Does no harm. divisor is in other register. 6601 if (VM_Version::has_CompareBranch()) { 6602 __ z_cgij(b, -1, Assembler::bcondEqual, done_div); 6603 } else { 6604 __ z_cghi(b, -1); 6605 __ z_bre(done_div); 6606 } 6607 __ z_lcgr(t, t); // Restore sign. 6608 __ z_dsgr(t->predecessor()/* t is odd part of a register pair. */, b); 6609 __ bind(done_div); 6610 %} 6611 ins_pipe(pipe_class_dummy); 6612 %} 6613 6614 // Immediate Long Division 6615 instruct divL_reg_imm16(roddRegL dst, iRegL src1, immL16 src2, revenRegL tmp, flagsReg cr) %{ 6616 match(Set dst (DivL src1 src2)); 6617 effect(KILL tmp, KILL cr); // R0 is killed, too. 6618 ins_cost(2 * DEFAULT_COST); 6619 // TODO: s390 port size(VARIABLE_SIZE); 6620 format %{ "DIVG_const $dst,$src1,$src2\t # long" %} 6621 ins_encode %{ 6622 if ($src2$$constant != -1) { 6623 __ z_lghi(Z_R0_scratch, $src2$$constant); 6624 __ lgr_if_needed($dst$$Register, $src1$$Register); 6625 __ z_dsgr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch); 6626 } else { 6627 __ z_lcgr($dst$$Register, $src1$$Register); 6628 } 6629 %} 6630 ins_pipe(pipe_class_dummy); 6631 %} 6632 6633 // REM 6634 6635 // Integer Remainder 6636 // Register Remainder 6637 instruct modI_reg_reg(revenRegI dst, iRegI src1, noOdd_iRegI src2, roddRegI tmp, flagsReg cr) %{ 6638 match(Set dst (ModI src1 src2)); 6639 effect(KILL tmp, KILL cr); 6640 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6641 // TODO: s390 port size(VARIABLE_SIZE); 6642 format %{ "MOD_checked $dst,$src1,$src2" %} 6643 ins_encode %{ 6644 Register a = $src1$$Register; 6645 Register b = $src2$$Register; 6646 Register t = $dst$$Register; 6647 assert_different_registers(t->successor(), b); 6648 6649 Label do_div, done_div; 6650 6651 if ((t->encoding() != b->encoding()) && (t->encoding() != a->encoding())) { 6652 (void) __ clear_reg(t, true, false); // Does no harm. Operands are in other regs. 6653 if (VM_Version::has_CompareBranch()) { 6654 __ z_cij(b, -1, Assembler::bcondEqual, done_div); 6655 } else { 6656 __ z_chi(b, -1); 6657 __ z_bre(done_div); 6658 } 6659 __ z_lgfr(t->successor(), a); 6660 __ z_dsgfr(t/* t is even part of a register pair. */, b); 6661 } else { 6662 if (VM_Version::has_CompareBranch()) { 6663 __ z_cij(b, -1, Assembler::bcondNotEqual, do_div); 6664 } else { 6665 __ z_chi(b, -1); 6666 __ z_brne(do_div); 6667 } 6668 __ clear_reg(t, true, false); 6669 __ z_bru(done_div); 6670 __ bind(do_div); 6671 __ z_lgfr(t->successor(), a); 6672 __ z_dsgfr(t/* t is even part of a register pair. */, b); 6673 } 6674 __ bind(done_div); 6675 %} 6676 ins_pipe(pipe_class_dummy); 6677 %} 6678 6679 // Immediate Remainder 6680 instruct modI_reg_imm16(revenRegI dst, iRegI src1, immI16 src2, roddRegI tmp, flagsReg cr) %{ 6681 match(Set dst (ModI src1 src2)); 6682 effect(KILL tmp, KILL cr); // R0 is killed, too. 6683 ins_cost(3 * DEFAULT_COST); 6684 // TODO: s390 port size(VARIABLE_SIZE); 6685 format %{ "MOD_const $dst,src1,$src2" %} 6686 ins_encode %{ 6687 assert_different_registers($dst$$Register, $src1$$Register); 6688 assert_different_registers($dst$$Register->successor(), $src1$$Register); 6689 int divisor = $src2$$constant; 6690 6691 if (divisor != -1) { 6692 __ z_lghi(Z_R0_scratch, divisor); 6693 __ z_lgfr($dst$$Register->successor(), $src1$$Register); 6694 __ z_dsgfr($dst$$Register/* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp. 6695 } else { 6696 __ clear_reg($dst$$Register, true, false); 6697 } 6698 %} 6699 ins_pipe(pipe_class_dummy); 6700 %} 6701 6702 // Register Long Remainder 6703 instruct modL_reg_reg(revenRegL dst, roddRegL src1, iRegL src2, flagsReg cr) %{ 6704 match(Set dst (ModL src1 src2)); 6705 effect(KILL src1, KILL cr); // R0 is killed, too. 6706 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6707 // TODO: s390 port size(VARIABLE_SIZE); 6708 format %{ "MODG_checked $dst,$src1,$src2" %} 6709 ins_encode %{ 6710 Register a = $src1$$Register; 6711 Register b = $src2$$Register; 6712 Register t = $dst$$Register; 6713 assert(t->successor() == a, "(t,a) is an even-odd pair" ); 6714 6715 Label do_div, done_div; 6716 if (t->encoding() != b->encoding()) { 6717 (void) __ clear_reg(t, true, false); // Does no harm. Dividend is in successor. 6718 if (VM_Version::has_CompareBranch()) { 6719 __ z_cgij(b, -1, Assembler::bcondEqual, done_div); 6720 } else { 6721 __ z_cghi(b, -1); 6722 __ z_bre(done_div); 6723 } 6724 __ z_dsgr(t, b); 6725 } else { 6726 if (VM_Version::has_CompareBranch()) { 6727 __ z_cgij(b, -1, Assembler::bcondNotEqual, do_div); 6728 } else { 6729 __ z_cghi(b, -1); 6730 __ z_brne(do_div); 6731 } 6732 __ clear_reg(t, true, false); 6733 __ z_bru(done_div); 6734 __ bind(do_div); 6735 __ z_dsgr(t, b); 6736 } 6737 __ bind(done_div); 6738 %} 6739 ins_pipe(pipe_class_dummy); 6740 %} 6741 6742 // Register Long Remainder 6743 instruct modL_reg_imm16(revenRegL dst, iRegL src1, immL16 src2, roddRegL tmp, flagsReg cr) %{ 6744 match(Set dst (ModL src1 src2)); 6745 effect(KILL tmp, KILL cr); // R0 is killed, too. 6746 ins_cost(3 * DEFAULT_COST); 6747 // TODO: s390 port size(VARIABLE_SIZE); 6748 format %{ "MODG_const $dst,src1,$src2\t # long" %} 6749 ins_encode %{ 6750 int divisor = $src2$$constant; 6751 if (divisor != -1) { 6752 __ z_lghi(Z_R0_scratch, divisor); 6753 __ z_lgr($dst$$Register->successor(), $src1$$Register); 6754 __ z_dsgr($dst$$Register /* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp. 6755 } else { 6756 __ clear_reg($dst$$Register, true, false); 6757 } 6758 %} 6759 ins_pipe(pipe_class_dummy); 6760 %} 6761 6762 // SHIFT 6763 6764 // Shift left logical 6765 6766 // Register Shift Left variable 6767 instruct sllI_reg_reg(iRegI dst, iRegI src, iRegI nbits, flagsReg cr) %{ 6768 match(Set dst (LShiftI src nbits)); 6769 effect(KILL cr); // R1 is killed, too. 6770 ins_cost(3 * DEFAULT_COST); 6771 size(14); 6772 format %{ "SLL $dst,$src,[$nbits] & 31\t# use RISC-like SLLG also for int" %} 6773 ins_encode %{ 6774 __ z_lgr(Z_R1_scratch, $nbits$$Register); 6775 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1); 6776 __ z_sllg($dst$$Register, $src$$Register, 0, Z_R1_scratch); 6777 %} 6778 ins_pipe(pipe_class_dummy); 6779 %} 6780 6781 // Register Shift Left Immediate 6782 // Constant shift count is masked in ideal graph already. 6783 instruct sllI_reg_imm(iRegI dst, iRegI src, immI nbits) %{ 6784 match(Set dst (LShiftI src nbits)); 6785 size(6); 6786 format %{ "SLL $dst,$src,$nbits\t# use RISC-like SLLG also for int" %} 6787 ins_encode %{ 6788 int Nbit = $nbits$$constant; 6789 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph"); 6790 __ z_sllg($dst$$Register, $src$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0); 6791 %} 6792 ins_pipe(pipe_class_dummy); 6793 %} 6794 6795 // Register Shift Left Immediate by 1bit 6796 instruct sllI_reg_imm_1(iRegI dst, iRegI src, immI_1 nbits) %{ 6797 match(Set dst (LShiftI src nbits)); 6798 predicate(PreferLAoverADD); 6799 ins_cost(DEFAULT_COST_LOW); 6800 size(4); 6801 format %{ "LA $dst,#0($src,$src)\t # SLL by 1 (int)" %} 6802 ins_encode %{ __ z_la($dst$$Register, 0, $src$$Register, $src$$Register); %} 6803 ins_pipe(pipe_class_dummy); 6804 %} 6805 6806 // Register Shift Left Long 6807 instruct sllL_reg_reg(iRegL dst, iRegL src1, iRegI nbits) %{ 6808 match(Set dst (LShiftL src1 nbits)); 6809 size(6); 6810 format %{ "SLLG $dst,$src1,[$nbits]" %} 6811 opcode(SLLG_ZOPC); 6812 ins_encode(z_rsyform_reg_reg(dst, src1, nbits)); 6813 ins_pipe(pipe_class_dummy); 6814 %} 6815 6816 // Register Shift Left Long Immediate 6817 instruct sllL_reg_imm(iRegL dst, iRegL src1, immI nbits) %{ 6818 match(Set dst (LShiftL src1 nbits)); 6819 size(6); 6820 format %{ "SLLG $dst,$src1,$nbits" %} 6821 opcode(SLLG_ZOPC); 6822 ins_encode(z_rsyform_const(dst, src1, nbits)); 6823 ins_pipe(pipe_class_dummy); 6824 %} 6825 6826 // Register Shift Left Long Immediate by 1bit 6827 instruct sllL_reg_imm_1(iRegL dst, iRegL src1, immI_1 nbits) %{ 6828 match(Set dst (LShiftL src1 nbits)); 6829 predicate(PreferLAoverADD); 6830 ins_cost(DEFAULT_COST_LOW); 6831 size(4); 6832 format %{ "LA $dst,#0($src1,$src1)\t # SLLG by 1 (long)" %} 6833 ins_encode %{ __ z_la($dst$$Register, 0, $src1$$Register, $src1$$Register); %} 6834 ins_pipe(pipe_class_dummy); 6835 %} 6836 6837 // Shift right arithmetic 6838 6839 // Register Arithmetic Shift Right 6840 instruct sraI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 6841 match(Set dst (RShiftI dst src)); 6842 effect(KILL cr); // R1 is killed, too. 6843 ins_cost(3 * DEFAULT_COST); 6844 size(12); 6845 format %{ "SRA $dst,[$src] & 31" %} 6846 ins_encode %{ 6847 __ z_lgr(Z_R1_scratch, $src$$Register); 6848 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1); 6849 __ z_sra($dst$$Register, 0, Z_R1_scratch); 6850 %} 6851 ins_pipe(pipe_class_dummy); 6852 %} 6853 6854 // Register Arithmetic Shift Right Immediate 6855 // Constant shift count is masked in ideal graph already. 6856 instruct sraI_reg_imm(iRegI dst, immI src, flagsReg cr) %{ 6857 match(Set dst (RShiftI dst src)); 6858 effect(KILL cr); 6859 size(4); 6860 format %{ "SRA $dst,$src" %} 6861 ins_encode %{ 6862 int Nbit = $src$$constant; 6863 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph"); 6864 __ z_sra($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0); 6865 %} 6866 ins_pipe(pipe_class_dummy); 6867 %} 6868 6869 // Register Arithmetic Shift Right Long 6870 instruct sraL_reg_reg(iRegL dst, iRegL src1, iRegI src2, flagsReg cr) %{ 6871 match(Set dst (RShiftL src1 src2)); 6872 effect(KILL cr); 6873 size(6); 6874 format %{ "SRAG $dst,$src1,[$src2]" %} 6875 opcode(SRAG_ZOPC); 6876 ins_encode(z_rsyform_reg_reg(dst, src1, src2)); 6877 ins_pipe(pipe_class_dummy); 6878 %} 6879 6880 // Register Arithmetic Shift Right Long Immediate 6881 instruct sraL_reg_imm(iRegL dst, iRegL src1, immI src2, flagsReg cr) %{ 6882 match(Set dst (RShiftL src1 src2)); 6883 effect(KILL cr); 6884 size(6); 6885 format %{ "SRAG $dst,$src1,$src2" %} 6886 opcode(SRAG_ZOPC); 6887 ins_encode(z_rsyform_const(dst, src1, src2)); 6888 ins_pipe(pipe_class_dummy); 6889 %} 6890 6891 // Shift right logical 6892 6893 // Register Shift Right 6894 instruct srlI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 6895 match(Set dst (URShiftI dst src)); 6896 effect(KILL cr); // R1 is killed, too. 6897 ins_cost(3 * DEFAULT_COST); 6898 size(12); 6899 format %{ "SRL $dst,[$src] & 31" %} 6900 ins_encode %{ 6901 __ z_lgr(Z_R1_scratch, $src$$Register); 6902 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1); 6903 __ z_srl($dst$$Register, 0, Z_R1_scratch); 6904 %} 6905 ins_pipe(pipe_class_dummy); 6906 %} 6907 6908 // Register Shift Right Immediate 6909 // Constant shift count is masked in ideal graph already. 6910 instruct srlI_reg_imm(iRegI dst, immI src) %{ 6911 match(Set dst (URShiftI dst src)); 6912 size(4); 6913 format %{ "SRL $dst,$src" %} 6914 ins_encode %{ 6915 int Nbit = $src$$constant; 6916 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph"); 6917 __ z_srl($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0); 6918 %} 6919 ins_pipe(pipe_class_dummy); 6920 %} 6921 6922 // Register Shift Right Long 6923 instruct srlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 6924 match(Set dst (URShiftL src1 src2)); 6925 size(6); 6926 format %{ "SRLG $dst,$src1,[$src2]" %} 6927 opcode(SRLG_ZOPC); 6928 ins_encode(z_rsyform_reg_reg(dst, src1, src2)); 6929 ins_pipe(pipe_class_dummy); 6930 %} 6931 6932 // Register Shift Right Long Immediate 6933 instruct srlL_reg_imm(iRegL dst, iRegL src1, immI src2) %{ 6934 match(Set dst (URShiftL src1 src2)); 6935 size(6); 6936 format %{ "SRLG $dst,$src1,$src2" %} 6937 opcode(SRLG_ZOPC); 6938 ins_encode(z_rsyform_const(dst, src1, src2)); 6939 ins_pipe(pipe_class_dummy); 6940 %} 6941 6942 // Register Shift Right Immediate with a CastP2X 6943 instruct srlP_reg_imm(iRegL dst, iRegP_N2P src1, immI src2) %{ 6944 match(Set dst (URShiftL (CastP2X src1) src2)); 6945 size(6); 6946 format %{ "SRLG $dst,$src1,$src2\t # Cast ptr $src1 to long and shift" %} 6947 opcode(SRLG_ZOPC); 6948 ins_encode(z_rsyform_const(dst, src1, src2)); 6949 ins_pipe(pipe_class_dummy); 6950 %} 6951 6952 //----------Rotate Instructions------------------------------------------------ 6953 6954 // Rotate left 32bit. 6955 instruct rotlI_reg_immI8(iRegI dst, iRegI src, immI8 lshift, immI8 rshift) %{ 6956 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift))); 6957 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 6958 size(6); 6959 format %{ "RLL $dst,$src,$lshift\t # ROTL32" %} 6960 opcode(RLL_ZOPC); 6961 ins_encode(z_rsyform_const(dst, src, lshift)); 6962 ins_pipe(pipe_class_dummy); 6963 %} 6964 6965 // Rotate left 64bit. 6966 instruct rotlL_reg_immI8(iRegL dst, iRegL src, immI8 lshift, immI8 rshift) %{ 6967 match(Set dst (OrL (LShiftL src lshift) (URShiftL src rshift))); 6968 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); 6969 size(6); 6970 format %{ "RLLG $dst,$src,$lshift\t # ROTL64" %} 6971 opcode(RLLG_ZOPC); 6972 ins_encode(z_rsyform_const(dst, src, lshift)); 6973 ins_pipe(pipe_class_dummy); 6974 %} 6975 6976 // Rotate right 32bit. 6977 instruct rotrI_reg_immI8(iRegI dst, iRegI src, immI8 rshift, immI8 lshift) %{ 6978 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift))); 6979 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 6980 // TODO: s390 port size(FIXED_SIZE); 6981 format %{ "RLL $dst,$src,$rshift\t # ROTR32" %} 6982 opcode(RLL_ZOPC); 6983 ins_encode(z_rsyform_const(dst, src, rshift)); 6984 ins_pipe(pipe_class_dummy); 6985 %} 6986 6987 // Rotate right 64bit. 6988 instruct rotrL_reg_immI8(iRegL dst, iRegL src, immI8 rshift, immI8 lshift) %{ 6989 match(Set dst (OrL (URShiftL src rshift) (LShiftL src lshift))); 6990 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); 6991 // TODO: s390 port size(FIXED_SIZE); 6992 format %{ "RLLG $dst,$src,$rshift\t # ROTR64" %} 6993 opcode(RLLG_ZOPC); 6994 ins_encode(z_rsyform_const(dst, src, rshift)); 6995 ins_pipe(pipe_class_dummy); 6996 %} 6997 6998 6999 //----------Overflow Math Instructions----------------------------------------- 7000 7001 instruct overflowAddI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{ 7002 match(Set cr (OverflowAddI op1 op2)); 7003 effect(DEF cr, USE op1, USE op2); 7004 // TODO: s390 port size(FIXED_SIZE); 7005 format %{ "AR $op1,$op2\t # overflow check int" %} 7006 ins_encode %{ 7007 __ z_lr(Z_R0_scratch, $op1$$Register); 7008 __ z_ar(Z_R0_scratch, $op2$$Register); 7009 %} 7010 ins_pipe(pipe_class_dummy); 7011 %} 7012 7013 instruct overflowAddI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{ 7014 match(Set cr (OverflowAddI op1 op2)); 7015 effect(DEF cr, USE op1, USE op2); 7016 // TODO: s390 port size(VARIABLE_SIZE); 7017 format %{ "AR $op1,$op2\t # overflow check int" %} 7018 ins_encode %{ 7019 __ load_const_optimized(Z_R0_scratch, $op2$$constant); 7020 __ z_ar(Z_R0_scratch, $op1$$Register); 7021 %} 7022 ins_pipe(pipe_class_dummy); 7023 %} 7024 7025 instruct overflowAddL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{ 7026 match(Set cr (OverflowAddL op1 op2)); 7027 effect(DEF cr, USE op1, USE op2); 7028 // TODO: s390 port size(FIXED_SIZE); 7029 format %{ "AGR $op1,$op2\t # overflow check long" %} 7030 ins_encode %{ 7031 __ z_lgr(Z_R0_scratch, $op1$$Register); 7032 __ z_agr(Z_R0_scratch, $op2$$Register); 7033 %} 7034 ins_pipe(pipe_class_dummy); 7035 %} 7036 7037 instruct overflowAddL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{ 7038 match(Set cr (OverflowAddL op1 op2)); 7039 effect(DEF cr, USE op1, USE op2); 7040 // TODO: s390 port size(VARIABLE_SIZE); 7041 format %{ "AGR $op1,$op2\t # overflow check long" %} 7042 ins_encode %{ 7043 __ load_const_optimized(Z_R0_scratch, $op2$$constant); 7044 __ z_agr(Z_R0_scratch, $op1$$Register); 7045 %} 7046 ins_pipe(pipe_class_dummy); 7047 %} 7048 7049 instruct overflowSubI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{ 7050 match(Set cr (OverflowSubI op1 op2)); 7051 effect(DEF cr, USE op1, USE op2); 7052 // TODO: s390 port size(FIXED_SIZE); 7053 format %{ "SR $op1,$op2\t # overflow check int" %} 7054 ins_encode %{ 7055 __ z_lr(Z_R0_scratch, $op1$$Register); 7056 __ z_sr(Z_R0_scratch, $op2$$Register); 7057 %} 7058 ins_pipe(pipe_class_dummy); 7059 %} 7060 7061 instruct overflowSubI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{ 7062 match(Set cr (OverflowSubI op1 op2)); 7063 effect(DEF cr, USE op1, USE op2); 7064 // TODO: s390 port size(VARIABLE_SIZE); 7065 format %{ "SR $op1,$op2\t # overflow check int" %} 7066 ins_encode %{ 7067 __ load_const_optimized(Z_R1_scratch, $op2$$constant); 7068 __ z_lr(Z_R0_scratch, $op1$$Register); 7069 __ z_sr(Z_R0_scratch, Z_R1_scratch); 7070 %} 7071 ins_pipe(pipe_class_dummy); 7072 %} 7073 7074 instruct overflowSubL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{ 7075 match(Set cr (OverflowSubL op1 op2)); 7076 effect(DEF cr, USE op1, USE op2); 7077 // TODO: s390 port size(FIXED_SIZE); 7078 format %{ "SGR $op1,$op2\t # overflow check long" %} 7079 ins_encode %{ 7080 __ z_lgr(Z_R0_scratch, $op1$$Register); 7081 __ z_sgr(Z_R0_scratch, $op2$$Register); 7082 %} 7083 ins_pipe(pipe_class_dummy); 7084 %} 7085 7086 instruct overflowSubL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{ 7087 match(Set cr (OverflowSubL op1 op2)); 7088 effect(DEF cr, USE op1, USE op2); 7089 // TODO: s390 port size(VARIABLE_SIZE); 7090 format %{ "SGR $op1,$op2\t # overflow check long" %} 7091 ins_encode %{ 7092 __ load_const_optimized(Z_R1_scratch, $op2$$constant); 7093 __ z_lgr(Z_R0_scratch, $op1$$Register); 7094 __ z_sgr(Z_R0_scratch, Z_R1_scratch); 7095 %} 7096 ins_pipe(pipe_class_dummy); 7097 %} 7098 7099 instruct overflowNegI_rReg(flagsReg cr, immI_0 zero, iRegI op2) %{ 7100 match(Set cr (OverflowSubI zero op2)); 7101 effect(DEF cr, USE op2); 7102 format %{ "NEG $op2\t# overflow check int" %} 7103 ins_encode %{ 7104 __ clear_reg(Z_R0_scratch, false, false); 7105 __ z_sr(Z_R0_scratch, $op2$$Register); 7106 %} 7107 ins_pipe(pipe_class_dummy); 7108 %} 7109 7110 instruct overflowNegL_rReg(flagsReg cr, immL_0 zero, iRegL op2) %{ 7111 match(Set cr (OverflowSubL zero op2)); 7112 effect(DEF cr, USE op2); 7113 format %{ "NEGG $op2\t# overflow check long" %} 7114 ins_encode %{ 7115 __ clear_reg(Z_R0_scratch, true, false); 7116 __ z_sgr(Z_R0_scratch, $op2$$Register); 7117 %} 7118 ins_pipe(pipe_class_dummy); 7119 %} 7120 7121 // No intrinsics for multiplication, since there is no easy way 7122 // to check for overflow. 7123 7124 7125 //----------Floating Point Arithmetic Instructions----------------------------- 7126 7127 // ADD 7128 7129 // Add float single precision 7130 instruct addF_reg_reg(regF dst, regF src, flagsReg cr) %{ 7131 match(Set dst (AddF dst src)); 7132 effect(KILL cr); 7133 ins_cost(ALU_REG_COST); 7134 size(4); 7135 format %{ "AEBR $dst,$src" %} 7136 opcode(AEBR_ZOPC); 7137 ins_encode(z_rreform(dst, src)); 7138 ins_pipe(pipe_class_dummy); 7139 %} 7140 7141 instruct addF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{ 7142 match(Set dst (AddF dst (LoadF src))); 7143 effect(KILL cr); 7144 ins_cost(ALU_MEMORY_COST); 7145 size(6); 7146 format %{ "AEB $dst,$src\t # floatMemory" %} 7147 opcode(AEB_ZOPC); 7148 ins_encode(z_form_rt_memFP(dst, src)); 7149 ins_pipe(pipe_class_dummy); 7150 %} 7151 7152 // Add float double precision 7153 instruct addD_reg_reg(regD dst, regD src, flagsReg cr) %{ 7154 match(Set dst (AddD dst src)); 7155 effect(KILL cr); 7156 ins_cost(ALU_REG_COST); 7157 size(4); 7158 format %{ "ADBR $dst,$src" %} 7159 opcode(ADBR_ZOPC); 7160 ins_encode(z_rreform(dst, src)); 7161 ins_pipe(pipe_class_dummy); 7162 %} 7163 7164 instruct addD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{ 7165 match(Set dst (AddD dst (LoadD src))); 7166 effect(KILL cr); 7167 ins_cost(ALU_MEMORY_COST); 7168 size(6); 7169 format %{ "ADB $dst,$src\t # doubleMemory" %} 7170 opcode(ADB_ZOPC); 7171 ins_encode(z_form_rt_memFP(dst, src)); 7172 ins_pipe(pipe_class_dummy); 7173 %} 7174 7175 // SUB 7176 7177 // Sub float single precision 7178 instruct subF_reg_reg(regF dst, regF src, flagsReg cr) %{ 7179 match(Set dst (SubF dst src)); 7180 effect(KILL cr); 7181 ins_cost(ALU_REG_COST); 7182 size(4); 7183 format %{ "SEBR $dst,$src" %} 7184 opcode(SEBR_ZOPC); 7185 ins_encode(z_rreform(dst, src)); 7186 ins_pipe(pipe_class_dummy); 7187 %} 7188 7189 instruct subF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{ 7190 match(Set dst (SubF dst (LoadF src))); 7191 effect(KILL cr); 7192 ins_cost(ALU_MEMORY_COST); 7193 size(6); 7194 format %{ "SEB $dst,$src\t # floatMemory" %} 7195 opcode(SEB_ZOPC); 7196 ins_encode(z_form_rt_memFP(dst, src)); 7197 ins_pipe(pipe_class_dummy); 7198 %} 7199 7200 // Sub float double precision 7201 instruct subD_reg_reg(regD dst, regD src, flagsReg cr) %{ 7202 match(Set dst (SubD dst src)); 7203 effect(KILL cr); 7204 ins_cost(ALU_REG_COST); 7205 size(4); 7206 format %{ "SDBR $dst,$src" %} 7207 opcode(SDBR_ZOPC); 7208 ins_encode(z_rreform(dst, src)); 7209 ins_pipe(pipe_class_dummy); 7210 %} 7211 7212 instruct subD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{ 7213 match(Set dst (SubD dst (LoadD src))); 7214 effect(KILL cr); 7215 ins_cost(ALU_MEMORY_COST); 7216 size(6); 7217 format %{ "SDB $dst,$src\t # doubleMemory" %} 7218 opcode(SDB_ZOPC); 7219 ins_encode(z_form_rt_memFP(dst, src)); 7220 ins_pipe(pipe_class_dummy); 7221 %} 7222 7223 // MUL 7224 7225 // Mul float single precision 7226 instruct mulF_reg_reg(regF dst, regF src) %{ 7227 match(Set dst (MulF dst src)); 7228 // CC unchanged by MUL. 7229 ins_cost(ALU_REG_COST); 7230 size(4); 7231 format %{ "MEEBR $dst,$src" %} 7232 opcode(MEEBR_ZOPC); 7233 ins_encode(z_rreform(dst, src)); 7234 ins_pipe(pipe_class_dummy); 7235 %} 7236 7237 instruct mulF_reg_mem(regF dst, memoryRX src)%{ 7238 match(Set dst (MulF dst (LoadF src))); 7239 // CC unchanged by MUL. 7240 ins_cost(ALU_MEMORY_COST); 7241 size(6); 7242 format %{ "MEEB $dst,$src\t # floatMemory" %} 7243 opcode(MEEB_ZOPC); 7244 ins_encode(z_form_rt_memFP(dst, src)); 7245 ins_pipe(pipe_class_dummy); 7246 %} 7247 7248 // Mul float double precision 7249 instruct mulD_reg_reg(regD dst, regD src) %{ 7250 match(Set dst (MulD dst src)); 7251 // CC unchanged by MUL. 7252 ins_cost(ALU_REG_COST); 7253 size(4); 7254 format %{ "MDBR $dst,$src" %} 7255 opcode(MDBR_ZOPC); 7256 ins_encode(z_rreform(dst, src)); 7257 ins_pipe(pipe_class_dummy); 7258 %} 7259 7260 instruct mulD_reg_mem(regD dst, memoryRX src)%{ 7261 match(Set dst (MulD dst (LoadD src))); 7262 // CC unchanged by MUL. 7263 ins_cost(ALU_MEMORY_COST); 7264 size(6); 7265 format %{ "MDB $dst,$src\t # doubleMemory" %} 7266 opcode(MDB_ZOPC); 7267 ins_encode(z_form_rt_memFP(dst, src)); 7268 ins_pipe(pipe_class_dummy); 7269 %} 7270 7271 // Multiply-Accumulate 7272 // src1 * src2 + dst 7273 instruct maddF_reg_reg(regF dst, regF src1, regF src2) %{ 7274 match(Set dst (FmaF dst (Binary src1 src2))); 7275 // CC unchanged by MUL-ADD. 7276 ins_cost(ALU_REG_COST); 7277 size(4); 7278 format %{ "MAEBR $dst, $src1, $src2" %} 7279 ins_encode %{ 7280 __ z_maebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 7281 %} 7282 ins_pipe(pipe_class_dummy); 7283 %} 7284 7285 // src1 * src2 + dst 7286 instruct maddD_reg_reg(regD dst, regD src1, regD src2) %{ 7287 match(Set dst (FmaD dst (Binary src1 src2))); 7288 // CC unchanged by MUL-ADD. 7289 ins_cost(ALU_REG_COST); 7290 size(4); 7291 format %{ "MADBR $dst, $src1, $src2" %} 7292 ins_encode %{ 7293 __ z_madbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 7294 %} 7295 ins_pipe(pipe_class_dummy); 7296 %} 7297 7298 // src1 * src2 - dst 7299 instruct msubF_reg_reg(regF dst, regF src1, regF src2) %{ 7300 match(Set dst (FmaF (NegF dst) (Binary src1 src2))); 7301 // CC unchanged by MUL-SUB. 7302 ins_cost(ALU_REG_COST); 7303 size(4); 7304 format %{ "MSEBR $dst, $src1, $src2" %} 7305 ins_encode %{ 7306 __ z_msebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 7307 %} 7308 ins_pipe(pipe_class_dummy); 7309 %} 7310 7311 // src1 * src2 - dst 7312 instruct msubD_reg_reg(regD dst, regD src1, regD src2) %{ 7313 match(Set dst (FmaD (NegD dst) (Binary src1 src2))); 7314 // CC unchanged by MUL-SUB. 7315 ins_cost(ALU_REG_COST); 7316 size(4); 7317 format %{ "MSDBR $dst, $src1, $src2" %} 7318 ins_encode %{ 7319 __ z_msdbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 7320 %} 7321 ins_pipe(pipe_class_dummy); 7322 %} 7323 7324 // src1 * src2 + dst 7325 instruct maddF_reg_mem(regF dst, regF src1, memoryRX src2) %{ 7326 match(Set dst (FmaF dst (Binary src1 (LoadF src2)))); 7327 // CC unchanged by MUL-ADD. 7328 ins_cost(ALU_MEMORY_COST); 7329 size(6); 7330 format %{ "MAEB $dst, $src1, $src2" %} 7331 ins_encode %{ 7332 __ z_maeb($dst$$FloatRegister, $src1$$FloatRegister, 7333 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp)); 7334 %} 7335 ins_pipe(pipe_class_dummy); 7336 %} 7337 7338 // src1 * src2 + dst 7339 instruct maddD_reg_mem(regD dst, regD src1, memoryRX src2) %{ 7340 match(Set dst (FmaD dst (Binary src1 (LoadD src2)))); 7341 // CC unchanged by MUL-ADD. 7342 ins_cost(ALU_MEMORY_COST); 7343 size(6); 7344 format %{ "MADB $dst, $src1, $src2" %} 7345 ins_encode %{ 7346 __ z_madb($dst$$FloatRegister, $src1$$FloatRegister, 7347 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp)); 7348 %} 7349 ins_pipe(pipe_class_dummy); 7350 %} 7351 7352 // src1 * src2 - dst 7353 instruct msubF_reg_mem(regF dst, regF src1, memoryRX src2) %{ 7354 match(Set dst (FmaF (NegF dst) (Binary src1 (LoadF src2)))); 7355 // CC unchanged by MUL-SUB. 7356 ins_cost(ALU_MEMORY_COST); 7357 size(6); 7358 format %{ "MSEB $dst, $src1, $src2" %} 7359 ins_encode %{ 7360 __ z_mseb($dst$$FloatRegister, $src1$$FloatRegister, 7361 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp)); 7362 %} 7363 ins_pipe(pipe_class_dummy); 7364 %} 7365 7366 // src1 * src2 - dst 7367 instruct msubD_reg_mem(regD dst, regD src1, memoryRX src2) %{ 7368 match(Set dst (FmaD (NegD dst) (Binary src1 (LoadD src2)))); 7369 // CC unchanged by MUL-SUB. 7370 ins_cost(ALU_MEMORY_COST); 7371 size(6); 7372 format %{ "MSDB $dst, $src1, $src2" %} 7373 ins_encode %{ 7374 __ z_msdb($dst$$FloatRegister, $src1$$FloatRegister, 7375 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp)); 7376 %} 7377 ins_pipe(pipe_class_dummy); 7378 %} 7379 7380 // src1 * src2 + dst 7381 instruct maddF_mem_reg(regF dst, memoryRX src1, regF src2) %{ 7382 match(Set dst (FmaF dst (Binary (LoadF src1) src2))); 7383 // CC unchanged by MUL-ADD. 7384 ins_cost(ALU_MEMORY_COST); 7385 size(6); 7386 format %{ "MAEB $dst, $src1, $src2" %} 7387 ins_encode %{ 7388 __ z_maeb($dst$$FloatRegister, $src2$$FloatRegister, 7389 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp)); 7390 %} 7391 ins_pipe(pipe_class_dummy); 7392 %} 7393 7394 // src1 * src2 + dst 7395 instruct maddD_mem_reg(regD dst, memoryRX src1, regD src2) %{ 7396 match(Set dst (FmaD dst (Binary (LoadD src1) src2))); 7397 // CC unchanged by MUL-ADD. 7398 ins_cost(ALU_MEMORY_COST); 7399 size(6); 7400 format %{ "MADB $dst, $src1, $src2" %} 7401 ins_encode %{ 7402 __ z_madb($dst$$FloatRegister, $src2$$FloatRegister, 7403 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp)); 7404 %} 7405 ins_pipe(pipe_class_dummy); 7406 %} 7407 7408 // src1 * src2 - dst 7409 instruct msubF_mem_reg(regF dst, memoryRX src1, regF src2) %{ 7410 match(Set dst (FmaF (NegF dst) (Binary (LoadF src1) src2))); 7411 // CC unchanged by MUL-SUB. 7412 ins_cost(ALU_MEMORY_COST); 7413 size(6); 7414 format %{ "MSEB $dst, $src1, $src2" %} 7415 ins_encode %{ 7416 __ z_mseb($dst$$FloatRegister, $src2$$FloatRegister, 7417 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp)); 7418 %} 7419 ins_pipe(pipe_class_dummy); 7420 %} 7421 7422 // src1 * src2 - dst 7423 instruct msubD_mem_reg(regD dst, memoryRX src1, regD src2) %{ 7424 match(Set dst (FmaD (NegD dst) (Binary (LoadD src1) src2))); 7425 // CC unchanged by MUL-SUB. 7426 ins_cost(ALU_MEMORY_COST); 7427 size(6); 7428 format %{ "MSDB $dst, $src1, $src2" %} 7429 ins_encode %{ 7430 __ z_msdb($dst$$FloatRegister, $src2$$FloatRegister, 7431 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp)); 7432 %} 7433 ins_pipe(pipe_class_dummy); 7434 %} 7435 7436 // DIV 7437 7438 // Div float single precision 7439 instruct divF_reg_reg(regF dst, regF src) %{ 7440 match(Set dst (DivF dst src)); 7441 // CC unchanged by DIV. 7442 ins_cost(ALU_REG_COST); 7443 size(4); 7444 format %{ "DEBR $dst,$src" %} 7445 opcode(DEBR_ZOPC); 7446 ins_encode(z_rreform(dst, src)); 7447 ins_pipe(pipe_class_dummy); 7448 %} 7449 7450 instruct divF_reg_mem(regF dst, memoryRX src)%{ 7451 match(Set dst (DivF dst (LoadF src))); 7452 // CC unchanged by DIV. 7453 ins_cost(ALU_MEMORY_COST); 7454 size(6); 7455 format %{ "DEB $dst,$src\t # floatMemory" %} 7456 opcode(DEB_ZOPC); 7457 ins_encode(z_form_rt_memFP(dst, src)); 7458 ins_pipe(pipe_class_dummy); 7459 %} 7460 7461 // Div float double precision 7462 instruct divD_reg_reg(regD dst, regD src) %{ 7463 match(Set dst (DivD dst src)); 7464 // CC unchanged by DIV. 7465 ins_cost(ALU_REG_COST); 7466 size(4); 7467 format %{ "DDBR $dst,$src" %} 7468 opcode(DDBR_ZOPC); 7469 ins_encode(z_rreform(dst, src)); 7470 ins_pipe(pipe_class_dummy); 7471 %} 7472 7473 instruct divD_reg_mem(regD dst, memoryRX src)%{ 7474 match(Set dst (DivD dst (LoadD src))); 7475 // CC unchanged by DIV. 7476 ins_cost(ALU_MEMORY_COST); 7477 size(6); 7478 format %{ "DDB $dst,$src\t # doubleMemory" %} 7479 opcode(DDB_ZOPC); 7480 ins_encode(z_form_rt_memFP(dst, src)); 7481 ins_pipe(pipe_class_dummy); 7482 %} 7483 7484 // ABS 7485 7486 // Absolute float single precision 7487 instruct absF_reg(regF dst, regF src, flagsReg cr) %{ 7488 match(Set dst (AbsF src)); 7489 effect(KILL cr); 7490 size(4); 7491 format %{ "LPEBR $dst,$src\t float" %} 7492 opcode(LPEBR_ZOPC); 7493 ins_encode(z_rreform(dst, src)); 7494 ins_pipe(pipe_class_dummy); 7495 %} 7496 7497 // Absolute float double precision 7498 instruct absD_reg(regD dst, regD src, flagsReg cr) %{ 7499 match(Set dst (AbsD src)); 7500 effect(KILL cr); 7501 size(4); 7502 format %{ "LPDBR $dst,$src\t double" %} 7503 opcode(LPDBR_ZOPC); 7504 ins_encode(z_rreform(dst, src)); 7505 ins_pipe(pipe_class_dummy); 7506 %} 7507 7508 // NEG(ABS) 7509 7510 // Negative absolute float single precision 7511 instruct nabsF_reg(regF dst, regF src, flagsReg cr) %{ 7512 match(Set dst (NegF (AbsF src))); 7513 effect(KILL cr); 7514 size(4); 7515 format %{ "LNEBR $dst,$src\t float" %} 7516 opcode(LNEBR_ZOPC); 7517 ins_encode(z_rreform(dst, src)); 7518 ins_pipe(pipe_class_dummy); 7519 %} 7520 7521 // Negative absolute float double precision 7522 instruct nabsD_reg(regD dst, regD src, flagsReg cr) %{ 7523 match(Set dst (NegD (AbsD src))); 7524 effect(KILL cr); 7525 size(4); 7526 format %{ "LNDBR $dst,$src\t double" %} 7527 opcode(LNDBR_ZOPC); 7528 ins_encode(z_rreform(dst, src)); 7529 ins_pipe(pipe_class_dummy); 7530 %} 7531 7532 // NEG 7533 7534 instruct negF_reg(regF dst, regF src, flagsReg cr) %{ 7535 match(Set dst (NegF src)); 7536 effect(KILL cr); 7537 size(4); 7538 format %{ "NegF $dst,$src\t float" %} 7539 ins_encode %{ __ z_lcebr($dst$$FloatRegister, $src$$FloatRegister); %} 7540 ins_pipe(pipe_class_dummy); 7541 %} 7542 7543 instruct negD_reg(regD dst, regD src, flagsReg cr) %{ 7544 match(Set dst (NegD src)); 7545 effect(KILL cr); 7546 size(4); 7547 format %{ "NegD $dst,$src\t double" %} 7548 ins_encode %{ __ z_lcdbr($dst$$FloatRegister, $src$$FloatRegister); %} 7549 ins_pipe(pipe_class_dummy); 7550 %} 7551 7552 // SQRT 7553 7554 // Sqrt float precision 7555 instruct sqrtF_reg(regF dst, regF src) %{ 7556 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 7557 // CC remains unchanged. 7558 ins_cost(ALU_REG_COST); 7559 size(4); 7560 format %{ "SQEBR $dst,$src" %} 7561 opcode(SQEBR_ZOPC); 7562 ins_encode(z_rreform(dst, src)); 7563 ins_pipe(pipe_class_dummy); 7564 %} 7565 7566 // Sqrt double precision 7567 instruct sqrtD_reg(regD dst, regD src) %{ 7568 match(Set dst (SqrtD src)); 7569 // CC remains unchanged. 7570 ins_cost(ALU_REG_COST); 7571 size(4); 7572 format %{ "SQDBR $dst,$src" %} 7573 opcode(SQDBR_ZOPC); 7574 ins_encode(z_rreform(dst, src)); 7575 ins_pipe(pipe_class_dummy); 7576 %} 7577 7578 instruct sqrtF_mem(regF dst, memoryRX src) %{ 7579 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 7580 // CC remains unchanged. 7581 ins_cost(ALU_MEMORY_COST); 7582 size(6); 7583 format %{ "SQEB $dst,$src\t # floatMemory" %} 7584 opcode(SQEB_ZOPC); 7585 ins_encode(z_form_rt_memFP(dst, src)); 7586 ins_pipe(pipe_class_dummy); 7587 %} 7588 7589 instruct sqrtD_mem(regD dst, memoryRX src) %{ 7590 match(Set dst (SqrtD src)); 7591 // CC remains unchanged. 7592 ins_cost(ALU_MEMORY_COST); 7593 // TODO: s390 port size(FIXED_SIZE); 7594 format %{ "SQDB $dst,$src\t # doubleMemory" %} 7595 opcode(SQDB_ZOPC); 7596 ins_encode(z_form_rt_memFP(dst, src)); 7597 ins_pipe(pipe_class_dummy); 7598 %} 7599 7600 //----------Logical Instructions----------------------------------------------- 7601 7602 // Register And 7603 instruct andI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 7604 match(Set dst (AndI dst src)); 7605 effect(KILL cr); 7606 ins_cost(DEFAULT_COST_LOW); 7607 size(2); 7608 format %{ "NR $dst,$src\t # int" %} 7609 opcode(NR_ZOPC); 7610 ins_encode(z_rrform(dst, src)); 7611 ins_pipe(pipe_class_dummy); 7612 %} 7613 7614 instruct andI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{ 7615 match(Set dst (AndI dst (LoadI src))); 7616 effect(KILL cr); 7617 ins_cost(MEMORY_REF_COST); 7618 // TODO: s390 port size(VARIABLE_SIZE); 7619 format %{ "N(Y) $dst, $src\t # int" %} 7620 opcode(NY_ZOPC, N_ZOPC); 7621 ins_encode(z_form_rt_mem_opt(dst, src)); 7622 ins_pipe(pipe_class_dummy); 7623 %} 7624 7625 // Immediate And 7626 instruct andI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{ 7627 match(Set dst (AndI dst src)); 7628 effect(KILL cr); 7629 ins_cost(DEFAULT_COST_HIGH); 7630 size(6); 7631 format %{ "NILF $dst,$src" %} 7632 opcode(NILF_ZOPC); 7633 ins_encode(z_rilform_unsigned(dst, src)); 7634 ins_pipe(pipe_class_dummy); 7635 %} 7636 7637 instruct andI_reg_uimmI_LH1(iRegI dst, uimmI_LH1 src, flagsReg cr) %{ 7638 match(Set dst (AndI dst src)); 7639 effect(KILL cr); 7640 ins_cost(DEFAULT_COST); 7641 size(4); 7642 format %{ "NILH $dst,$src" %} 7643 ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %} 7644 ins_pipe(pipe_class_dummy); 7645 %} 7646 7647 instruct andI_reg_uimmI_LL1(iRegI dst, uimmI_LL1 src, flagsReg cr) %{ 7648 match(Set dst (AndI dst src)); 7649 effect(KILL cr); 7650 ins_cost(DEFAULT_COST); 7651 size(4); 7652 format %{ "NILL $dst,$src" %} 7653 ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %} 7654 ins_pipe(pipe_class_dummy); 7655 %} 7656 7657 // Register And Long 7658 instruct andL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{ 7659 match(Set dst (AndL dst src)); 7660 effect(KILL cr); 7661 ins_cost(DEFAULT_COST); 7662 size(4); 7663 format %{ "NGR $dst,$src\t # long" %} 7664 opcode(NGR_ZOPC); 7665 ins_encode(z_rreform(dst, src)); 7666 ins_pipe(pipe_class_dummy); 7667 %} 7668 7669 instruct andL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{ 7670 match(Set dst (AndL dst (LoadL src))); 7671 effect(KILL cr); 7672 ins_cost(MEMORY_REF_COST); 7673 size(Z_DISP3_SIZE); 7674 format %{ "NG $dst, $src\t # long" %} 7675 opcode(NG_ZOPC, NG_ZOPC); 7676 ins_encode(z_form_rt_mem_opt(dst, src)); 7677 ins_pipe(pipe_class_dummy); 7678 %} 7679 7680 instruct andL_reg_uimmL_LL1(iRegL dst, uimmL_LL1 src, flagsReg cr) %{ 7681 match(Set dst (AndL dst src)); 7682 effect(KILL cr); 7683 ins_cost(DEFAULT_COST); 7684 size(4); 7685 format %{ "NILL $dst,$src\t # long" %} 7686 ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %} 7687 ins_pipe(pipe_class_dummy); 7688 %} 7689 7690 instruct andL_reg_uimmL_LH1(iRegL dst, uimmL_LH1 src, flagsReg cr) %{ 7691 match(Set dst (AndL dst src)); 7692 effect(KILL cr); 7693 ins_cost(DEFAULT_COST); 7694 size(4); 7695 format %{ "NILH $dst,$src\t # long" %} 7696 ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %} 7697 ins_pipe(pipe_class_dummy); 7698 %} 7699 7700 instruct andL_reg_uimmL_HL1(iRegL dst, uimmL_HL1 src, flagsReg cr) %{ 7701 match(Set dst (AndL dst src)); 7702 effect(KILL cr); 7703 ins_cost(DEFAULT_COST); 7704 size(4); 7705 format %{ "NIHL $dst,$src\t # long" %} 7706 ins_encode %{ __ z_nihl($dst$$Register, ($src$$constant >> 32) & 0xFFFF); %} 7707 ins_pipe(pipe_class_dummy); 7708 %} 7709 7710 instruct andL_reg_uimmL_HH1(iRegL dst, uimmL_HH1 src, flagsReg cr) %{ 7711 match(Set dst (AndL dst src)); 7712 effect(KILL cr); 7713 ins_cost(DEFAULT_COST); 7714 size(4); 7715 format %{ "NIHH $dst,$src\t # long" %} 7716 ins_encode %{ __ z_nihh($dst$$Register, ($src$$constant >> 48) & 0xFFFF); %} 7717 ins_pipe(pipe_class_dummy); 7718 %} 7719 7720 // OR 7721 7722 // Or Instructions 7723 // Register Or 7724 instruct orI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 7725 match(Set dst (OrI dst src)); 7726 effect(KILL cr); 7727 size(2); 7728 format %{ "OR $dst,$src" %} 7729 opcode(OR_ZOPC); 7730 ins_encode(z_rrform(dst, src)); 7731 ins_pipe(pipe_class_dummy); 7732 %} 7733 7734 instruct orI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{ 7735 match(Set dst (OrI dst (LoadI src))); 7736 effect(KILL cr); 7737 ins_cost(MEMORY_REF_COST); 7738 // TODO: s390 port size(VARIABLE_SIZE); 7739 format %{ "O(Y) $dst, $src\t # int" %} 7740 opcode(OY_ZOPC, O_ZOPC); 7741 ins_encode(z_form_rt_mem_opt(dst, src)); 7742 ins_pipe(pipe_class_dummy); 7743 %} 7744 7745 // Immediate Or 7746 instruct orI_reg_uimm16(iRegI dst, uimmI16 con, flagsReg cr) %{ 7747 match(Set dst (OrI dst con)); 7748 effect(KILL cr); 7749 size(4); 7750 format %{ "OILL $dst,$con" %} 7751 opcode(OILL_ZOPC); 7752 ins_encode(z_riform_unsigned(dst,con)); 7753 ins_pipe(pipe_class_dummy); 7754 %} 7755 7756 instruct orI_reg_uimm32(iRegI dst, uimmI con, flagsReg cr) %{ 7757 match(Set dst (OrI dst con)); 7758 effect(KILL cr); 7759 ins_cost(DEFAULT_COST_HIGH); 7760 size(6); 7761 format %{ "OILF $dst,$con" %} 7762 opcode(OILF_ZOPC); 7763 ins_encode(z_rilform_unsigned(dst,con)); 7764 ins_pipe(pipe_class_dummy); 7765 %} 7766 7767 // Register Or Long 7768 instruct orL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{ 7769 match(Set dst (OrL dst src)); 7770 effect(KILL cr); 7771 ins_cost(DEFAULT_COST); 7772 size(4); 7773 format %{ "OGR $dst,$src\t # long" %} 7774 opcode(OGR_ZOPC); 7775 ins_encode(z_rreform(dst, src)); 7776 ins_pipe(pipe_class_dummy); 7777 %} 7778 7779 instruct orL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{ 7780 match(Set dst (OrL dst (LoadL src))); 7781 effect(KILL cr); 7782 ins_cost(MEMORY_REF_COST); 7783 size(Z_DISP3_SIZE); 7784 format %{ "OG $dst, $src\t # long" %} 7785 opcode(OG_ZOPC, OG_ZOPC); 7786 ins_encode(z_form_rt_mem_opt(dst, src)); 7787 ins_pipe(pipe_class_dummy); 7788 %} 7789 7790 // Immediate Or long 7791 instruct orL_reg_uimm16(iRegL dst, uimmL16 con, flagsReg cr) %{ 7792 match(Set dst (OrL dst con)); 7793 effect(KILL cr); 7794 ins_cost(DEFAULT_COST); 7795 size(4); 7796 format %{ "OILL $dst,$con\t # long" %} 7797 opcode(OILL_ZOPC); 7798 ins_encode(z_riform_unsigned(dst,con)); 7799 ins_pipe(pipe_class_dummy); 7800 %} 7801 7802 instruct orL_reg_uimm32(iRegI dst, uimmL32 con, flagsReg cr) %{ 7803 match(Set dst (OrI dst con)); 7804 effect(KILL cr); 7805 ins_cost(DEFAULT_COST_HIGH); 7806 // TODO: s390 port size(FIXED_SIZE); 7807 format %{ "OILF $dst,$con\t # long" %} 7808 opcode(OILF_ZOPC); 7809 ins_encode(z_rilform_unsigned(dst,con)); 7810 ins_pipe(pipe_class_dummy); 7811 %} 7812 7813 // XOR 7814 7815 // Register Xor 7816 instruct xorI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 7817 match(Set dst (XorI dst src)); 7818 effect(KILL cr); 7819 size(2); 7820 format %{ "XR $dst,$src" %} 7821 opcode(XR_ZOPC); 7822 ins_encode(z_rrform(dst, src)); 7823 ins_pipe(pipe_class_dummy); 7824 %} 7825 7826 instruct xorI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{ 7827 match(Set dst (XorI dst (LoadI src))); 7828 effect(KILL cr); 7829 ins_cost(MEMORY_REF_COST); 7830 // TODO: s390 port size(VARIABLE_SIZE); 7831 format %{ "X(Y) $dst, $src\t # int" %} 7832 opcode(XY_ZOPC, X_ZOPC); 7833 ins_encode(z_form_rt_mem_opt(dst, src)); 7834 ins_pipe(pipe_class_dummy); 7835 %} 7836 7837 // Immediate Xor 7838 instruct xorI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{ 7839 match(Set dst (XorI dst src)); 7840 effect(KILL cr); 7841 ins_cost(DEFAULT_COST_HIGH); 7842 size(6); 7843 format %{ "XILF $dst,$src" %} 7844 opcode(XILF_ZOPC); 7845 ins_encode(z_rilform_unsigned(dst, src)); 7846 ins_pipe(pipe_class_dummy); 7847 %} 7848 7849 // Register Xor Long 7850 instruct xorL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{ 7851 match(Set dst (XorL dst src)); 7852 effect(KILL cr); 7853 ins_cost(DEFAULT_COST); 7854 size(4); 7855 format %{ "XGR $dst,$src\t # long" %} 7856 opcode(XGR_ZOPC); 7857 ins_encode(z_rreform(dst, src)); 7858 ins_pipe(pipe_class_dummy); 7859 %} 7860 7861 instruct xorL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{ 7862 match(Set dst (XorL dst (LoadL src))); 7863 effect(KILL cr); 7864 ins_cost(MEMORY_REF_COST); 7865 size(Z_DISP3_SIZE); 7866 format %{ "XG $dst, $src\t # long" %} 7867 opcode(XG_ZOPC, XG_ZOPC); 7868 ins_encode(z_form_rt_mem_opt(dst, src)); 7869 ins_pipe(pipe_class_dummy); 7870 %} 7871 7872 // Immediate Xor Long 7873 instruct xorL_reg_uimm32(iRegL dst, uimmL32 con, flagsReg cr) %{ 7874 match(Set dst (XorL dst con)); 7875 effect(KILL cr); 7876 ins_cost(DEFAULT_COST_HIGH); 7877 size(6); 7878 format %{ "XILF $dst,$con\t # long" %} 7879 opcode(XILF_ZOPC); 7880 ins_encode(z_rilform_unsigned(dst,con)); 7881 ins_pipe(pipe_class_dummy); 7882 %} 7883 7884 //----------Convert to Boolean------------------------------------------------- 7885 7886 // Convert integer to boolean. 7887 instruct convI2B(iRegI dst, iRegI src, flagsReg cr) %{ 7888 match(Set dst (Conv2B src)); 7889 effect(KILL cr); 7890 ins_cost(3 * DEFAULT_COST); 7891 size(6); 7892 format %{ "convI2B $dst,$src" %} 7893 ins_encode %{ 7894 __ z_lnr($dst$$Register, $src$$Register); // Rdst := -|Rsrc|, i.e. Rdst == 0 <=> Rsrc == 0 7895 __ z_srl($dst$$Register, 31); // Rdst := sign(Rdest) 7896 %} 7897 ins_pipe(pipe_class_dummy); 7898 %} 7899 7900 instruct convP2B(iRegI dst, iRegP_N2P src, flagsReg cr) %{ 7901 match(Set dst (Conv2B src)); 7902 effect(KILL cr); 7903 ins_cost(3 * DEFAULT_COST); 7904 size(10); 7905 format %{ "convP2B $dst,$src" %} 7906 ins_encode %{ 7907 __ z_lngr($dst$$Register, $src$$Register); // Rdst := -|Rsrc| i.e. Rdst == 0 <=> Rsrc == 0 7908 __ z_srlg($dst$$Register, $dst$$Register, 63); // Rdst := sign(Rdest) 7909 %} 7910 ins_pipe(pipe_class_dummy); 7911 %} 7912 7913 instruct cmpLTMask_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 7914 match(Set dst (CmpLTMask dst src)); 7915 effect(KILL cr); 7916 ins_cost(2 * DEFAULT_COST); 7917 size(18); 7918 format %{ "Set $dst CmpLTMask $dst,$src" %} 7919 ins_encode %{ 7920 // Avoid signed 32 bit overflow: Do sign extend and sub 64 bit. 7921 __ z_lgfr(Z_R0_scratch, $src$$Register); 7922 __ z_lgfr($dst$$Register, $dst$$Register); 7923 __ z_sgr($dst$$Register, Z_R0_scratch); 7924 __ z_srag($dst$$Register, $dst$$Register, 63); 7925 %} 7926 ins_pipe(pipe_class_dummy); 7927 %} 7928 7929 instruct cmpLTMask_reg_zero(iRegI dst, immI_0 zero, flagsReg cr) %{ 7930 match(Set dst (CmpLTMask dst zero)); 7931 effect(KILL cr); 7932 ins_cost(DEFAULT_COST); 7933 size(4); 7934 format %{ "Set $dst CmpLTMask $dst,$zero" %} 7935 ins_encode %{ __ z_sra($dst$$Register, 31); %} 7936 ins_pipe(pipe_class_dummy); 7937 %} 7938 7939 7940 //----------Arithmetic Conversion Instructions--------------------------------- 7941 // The conversions operations are all Alpha sorted. Please keep it that way! 7942 7943 instruct convD2F_reg(regF dst, regD src) %{ 7944 match(Set dst (ConvD2F src)); 7945 // CC remains unchanged. 7946 size(4); 7947 format %{ "LEDBR $dst,$src" %} 7948 opcode(LEDBR_ZOPC); 7949 ins_encode(z_rreform(dst, src)); 7950 ins_pipe(pipe_class_dummy); 7951 %} 7952 7953 instruct convF2I_reg(iRegI dst, regF src, flagsReg cr) %{ 7954 match(Set dst (ConvF2I src)); 7955 effect(KILL cr); 7956 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 7957 size(16); 7958 format %{ "convF2I $dst,$src" %} 7959 ins_encode %{ 7960 Label done; 7961 __ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0. 7962 __ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round. 7963 __ z_brno(done); // Result is zero if unordered argument. 7964 __ z_cfebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero); 7965 __ bind(done); 7966 %} 7967 ins_pipe(pipe_class_dummy); 7968 %} 7969 7970 instruct convD2I_reg(iRegI dst, regD src, flagsReg cr) %{ 7971 match(Set dst (ConvD2I src)); 7972 effect(KILL cr); 7973 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 7974 size(16); 7975 format %{ "convD2I $dst,$src" %} 7976 ins_encode %{ 7977 Label done; 7978 __ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0. 7979 __ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round. 7980 __ z_brno(done); // Result is zero if unordered argument. 7981 __ z_cfdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero); 7982 __ bind(done); 7983 %} 7984 ins_pipe(pipe_class_dummy); 7985 %} 7986 7987 instruct convF2L_reg(iRegL dst, regF src, flagsReg cr) %{ 7988 match(Set dst (ConvF2L src)); 7989 effect(KILL cr); 7990 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 7991 size(16); 7992 format %{ "convF2L $dst,$src" %} 7993 ins_encode %{ 7994 Label done; 7995 __ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0. 7996 __ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round. 7997 __ z_brno(done); // Result is zero if unordered argument. 7998 __ z_cgebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero); 7999 __ bind(done); 8000 %} 8001 ins_pipe(pipe_class_dummy); 8002 %} 8003 8004 instruct convD2L_reg(iRegL dst, regD src, flagsReg cr) %{ 8005 match(Set dst (ConvD2L src)); 8006 effect(KILL cr); 8007 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8008 size(16); 8009 format %{ "convD2L $dst,$src" %} 8010 ins_encode %{ 8011 Label done; 8012 __ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0. 8013 __ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round. 8014 __ z_brno(done); // Result is zero if unordered argument. 8015 __ z_cgdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero); 8016 __ bind(done); 8017 %} 8018 ins_pipe(pipe_class_dummy); 8019 %} 8020 8021 instruct convF2D_reg(regD dst, regF src) %{ 8022 match(Set dst (ConvF2D src)); 8023 // CC remains unchanged. 8024 size(4); 8025 format %{ "LDEBR $dst,$src" %} 8026 opcode(LDEBR_ZOPC); 8027 ins_encode(z_rreform(dst, src)); 8028 ins_pipe(pipe_class_dummy); 8029 %} 8030 8031 instruct convF2D_mem(regD dst, memoryRX src) %{ 8032 match(Set dst (ConvF2D src)); 8033 // CC remains unchanged. 8034 size(6); 8035 format %{ "LDEB $dst,$src" %} 8036 opcode(LDEB_ZOPC); 8037 ins_encode(z_form_rt_memFP(dst, src)); 8038 ins_pipe(pipe_class_dummy); 8039 %} 8040 8041 instruct convI2D_reg(regD dst, iRegI src) %{ 8042 match(Set dst (ConvI2D src)); 8043 // CC remains unchanged. 8044 ins_cost(DEFAULT_COST); 8045 size(4); 8046 format %{ "CDFBR $dst,$src" %} 8047 opcode(CDFBR_ZOPC); 8048 ins_encode(z_rreform(dst, src)); 8049 ins_pipe(pipe_class_dummy); 8050 %} 8051 8052 // Optimization that saves up to two memory operations for each conversion. 8053 instruct convI2F_ireg(regF dst, iRegI src) %{ 8054 match(Set dst (ConvI2F src)); 8055 // CC remains unchanged. 8056 ins_cost(DEFAULT_COST); 8057 size(4); 8058 format %{ "CEFBR $dst,$src\t # convert int to float" %} 8059 opcode(CEFBR_ZOPC); 8060 ins_encode(z_rreform(dst, src)); 8061 ins_pipe(pipe_class_dummy); 8062 %} 8063 8064 instruct convI2L_reg(iRegL dst, iRegI src) %{ 8065 match(Set dst (ConvI2L src)); 8066 size(4); 8067 format %{ "LGFR $dst,$src\t # int->long" %} 8068 opcode(LGFR_ZOPC); 8069 ins_encode(z_rreform(dst, src)); 8070 ins_pipe(pipe_class_dummy); 8071 %} 8072 8073 // Zero-extend convert int to long. 8074 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask) %{ 8075 match(Set dst (AndL (ConvI2L src) mask)); 8076 size(4); 8077 format %{ "LLGFR $dst, $src \t # zero-extend int to long" %} 8078 ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %} 8079 ins_pipe(pipe_class_dummy); 8080 %} 8081 8082 // Zero-extend convert int to long. 8083 instruct convI2L_mem_zex(iRegL dst, memory src, immL_32bits mask) %{ 8084 match(Set dst (AndL (ConvI2L (LoadI src)) mask)); 8085 // Uses load_const_optmized, so size can vary. 8086 // TODO: s390 port size(VARIABLE_SIZE); 8087 format %{ "LLGF $dst, $src \t # zero-extend int to long" %} 8088 opcode(LLGF_ZOPC, LLGF_ZOPC); 8089 ins_encode(z_form_rt_mem_opt(dst, src)); 8090 ins_pipe(pipe_class_dummy); 8091 %} 8092 8093 // Zero-extend long 8094 instruct zeroExtend_long(iRegL dst, iRegL src, immL_32bits mask) %{ 8095 match(Set dst (AndL src mask)); 8096 size(4); 8097 format %{ "LLGFR $dst, $src \t # zero-extend long to long" %} 8098 ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %} 8099 ins_pipe(pipe_class_dummy); 8100 %} 8101 8102 instruct rShiftI16_lShiftI16_reg(iRegI dst, iRegI src, immI_16 amount) %{ 8103 match(Set dst (RShiftI (LShiftI src amount) amount)); 8104 size(4); 8105 format %{ "LHR $dst,$src\t short->int" %} 8106 opcode(LHR_ZOPC); 8107 ins_encode(z_rreform(dst, src)); 8108 ins_pipe(pipe_class_dummy); 8109 %} 8110 8111 instruct rShiftI24_lShiftI24_reg(iRegI dst, iRegI src, immI_24 amount) %{ 8112 match(Set dst (RShiftI (LShiftI src amount) amount)); 8113 size(4); 8114 format %{ "LBR $dst,$src\t byte->int" %} 8115 opcode(LBR_ZOPC); 8116 ins_encode(z_rreform(dst, src)); 8117 ins_pipe(pipe_class_dummy); 8118 %} 8119 8120 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ 8121 match(Set dst (MoveF2I src)); 8122 ins_cost(MEMORY_REF_COST); 8123 size(4); 8124 format %{ "L $dst,$src\t # MoveF2I" %} 8125 opcode(L_ZOPC); 8126 ins_encode(z_form_rt_mem(dst, src)); 8127 ins_pipe(pipe_class_dummy); 8128 %} 8129 8130 // javax.imageio.stream.ImageInputStreamImpl.toFloats([B[FII) 8131 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ 8132 match(Set dst (MoveI2F src)); 8133 ins_cost(MEMORY_REF_COST); 8134 // TODO: s390 port size(FIXED_SIZE); 8135 format %{ "LE $dst,$src\t # MoveI2F" %} 8136 opcode(LE_ZOPC); 8137 ins_encode(z_form_rt_mem(dst, src)); 8138 ins_pipe(pipe_class_dummy); 8139 %} 8140 8141 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ 8142 match(Set dst (MoveD2L src)); 8143 ins_cost(MEMORY_REF_COST); 8144 size(6); 8145 format %{ "LG $src,$dst\t # MoveD2L" %} 8146 opcode(LG_ZOPC); 8147 ins_encode(z_form_rt_mem(dst, src)); 8148 ins_pipe(pipe_class_dummy); 8149 %} 8150 8151 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ 8152 match(Set dst (MoveL2D src)); 8153 ins_cost(MEMORY_REF_COST); 8154 size(4); 8155 format %{ "LD $dst,$src\t # MoveL2D" %} 8156 opcode(LD_ZOPC); 8157 ins_encode(z_form_rt_mem(dst, src)); 8158 ins_pipe(pipe_class_dummy); 8159 %} 8160 8161 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ 8162 match(Set dst (MoveI2F src)); 8163 ins_cost(MEMORY_REF_COST); 8164 size(4); 8165 format %{ "ST $src,$dst\t # MoveI2F" %} 8166 opcode(ST_ZOPC); 8167 ins_encode(z_form_rt_mem(src, dst)); 8168 ins_pipe(pipe_class_dummy); 8169 %} 8170 8171 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ 8172 match(Set dst (MoveD2L src)); 8173 effect(DEF dst, USE src); 8174 ins_cost(MEMORY_REF_COST); 8175 size(4); 8176 format %{ "STD $src,$dst\t # MoveD2L" %} 8177 opcode(STD_ZOPC); 8178 ins_encode(z_form_rt_mem(src,dst)); 8179 ins_pipe(pipe_class_dummy); 8180 %} 8181 8182 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ 8183 match(Set dst (MoveL2D src)); 8184 ins_cost(MEMORY_REF_COST); 8185 size(6); 8186 format %{ "STG $src,$dst\t # MoveL2D" %} 8187 opcode(STG_ZOPC); 8188 ins_encode(z_form_rt_mem(src,dst)); 8189 ins_pipe(pipe_class_dummy); 8190 %} 8191 8192 instruct convL2F_reg(regF dst, iRegL src) %{ 8193 match(Set dst (ConvL2F src)); 8194 // CC remains unchanged. 8195 ins_cost(DEFAULT_COST); 8196 size(4); 8197 format %{ "CEGBR $dst,$src" %} 8198 opcode(CEGBR_ZOPC); 8199 ins_encode(z_rreform(dst, src)); 8200 ins_pipe(pipe_class_dummy); 8201 %} 8202 8203 instruct convL2D_reg(regD dst, iRegL src) %{ 8204 match(Set dst (ConvL2D src)); 8205 // CC remains unchanged. 8206 ins_cost(DEFAULT_COST); 8207 size(4); 8208 format %{ "CDGBR $dst,$src" %} 8209 opcode(CDGBR_ZOPC); 8210 ins_encode(z_rreform(dst, src)); 8211 ins_pipe(pipe_class_dummy); 8212 %} 8213 8214 instruct convL2I_reg(iRegI dst, iRegL src) %{ 8215 match(Set dst (ConvL2I src)); 8216 // TODO: s390 port size(VARIABLE_SIZE); 8217 format %{ "LR $dst,$src\t # long->int (if needed)" %} 8218 ins_encode %{ __ lr_if_needed($dst$$Register, $src$$Register); %} 8219 ins_pipe(pipe_class_dummy); 8220 %} 8221 8222 // Register Shift Right Immediate 8223 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt, flagsReg cr) %{ 8224 match(Set dst (ConvL2I (RShiftL src cnt))); 8225 effect(KILL cr); 8226 size(6); 8227 format %{ "SRAG $dst,$src,$cnt" %} 8228 opcode(SRAG_ZOPC); 8229 ins_encode(z_rsyform_const(dst, src, cnt)); 8230 ins_pipe(pipe_class_dummy); 8231 %} 8232 8233 //----------TRAP based zero checks and range checks---------------------------- 8234 8235 // SIGTRAP based implicit range checks in compiled code. 8236 // A range check in the ideal world has one of the following shapes: 8237 // - (If le (CmpU length index)), (IfTrue throw exception) 8238 // - (If lt (CmpU index length)), (IfFalse throw exception) 8239 // 8240 // Match range check 'If le (CmpU length index)' 8241 instruct rangeCheck_iReg_uimmI16(cmpOpT cmp, iRegI length, uimmI16 index, label labl) %{ 8242 match(If cmp (CmpU length index)); 8243 effect(USE labl); 8244 predicate(TrapBasedRangeChecks && 8245 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le && 8246 PROB_UNLIKELY(_leaf->as_If ()->_prob) >= PROB_ALWAYS && 8247 Matcher::branches_to_uncommon_trap(_leaf)); 8248 ins_cost(1); 8249 // TODO: s390 port size(FIXED_SIZE); 8250 8251 ins_is_TrapBasedCheckNode(true); 8252 8253 format %{ "RangeCheck len=$length cmp=$cmp idx=$index => trap $labl" %} 8254 ins_encode %{ __ z_clfit($length$$Register, $index$$constant, $cmp$$cmpcode); %} 8255 ins_pipe(pipe_class_trap); 8256 %} 8257 8258 // Match range check 'If lt (CmpU index length)' 8259 instruct rangeCheck_iReg_iReg(cmpOpT cmp, iRegI index, iRegI length, label labl, flagsReg cr) %{ 8260 match(If cmp (CmpU index length)); 8261 effect(USE labl, KILL cr); 8262 predicate(TrapBasedRangeChecks && 8263 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && 8264 _leaf->as_If ()->_prob >= PROB_ALWAYS && 8265 Matcher::branches_to_uncommon_trap(_leaf)); 8266 ins_cost(1); 8267 // TODO: s390 port size(FIXED_SIZE); 8268 8269 ins_is_TrapBasedCheckNode(true); 8270 8271 format %{ "RangeCheck idx=$index cmp=$cmp len=$length => trap $labl" %} 8272 ins_encode %{ __ z_clrt($index$$Register, $length$$Register, $cmp$$cmpcode); %} 8273 ins_pipe(pipe_class_trap); 8274 %} 8275 8276 // Match range check 'If lt (CmpU index length)' 8277 instruct rangeCheck_uimmI16_iReg(cmpOpT cmp, iRegI index, uimmI16 length, label labl) %{ 8278 match(If cmp (CmpU index length)); 8279 effect(USE labl); 8280 predicate(TrapBasedRangeChecks && 8281 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && 8282 _leaf->as_If ()->_prob >= PROB_ALWAYS && 8283 Matcher::branches_to_uncommon_trap(_leaf)); 8284 ins_cost(1); 8285 // TODO: s390 port size(FIXED_SIZE); 8286 8287 ins_is_TrapBasedCheckNode(true); 8288 8289 format %{ "RangeCheck idx=$index cmp=$cmp len= $length => trap $labl" %} 8290 ins_encode %{ __ z_clfit($index$$Register, $length$$constant, $cmp$$cmpcode); %} 8291 ins_pipe(pipe_class_trap); 8292 %} 8293 8294 // Implicit zero checks (more implicit null checks). 8295 instruct zeroCheckP_iReg_imm0(cmpOpT cmp, iRegP_N2P value, immP0 zero, label labl) %{ 8296 match(If cmp (CmpP value zero)); 8297 effect(USE labl); 8298 predicate(TrapBasedNullChecks && 8299 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && 8300 _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) && 8301 Matcher::branches_to_uncommon_trap(_leaf)); 8302 size(6); 8303 8304 ins_is_TrapBasedCheckNode(true); 8305 8306 format %{ "ZeroCheckP value=$value cmp=$cmp zero=$zero => trap $labl" %} 8307 ins_encode %{ __ z_cgit($value$$Register, 0, $cmp$$cmpcode); %} 8308 ins_pipe(pipe_class_trap); 8309 %} 8310 8311 // Implicit zero checks (more implicit null checks). 8312 instruct zeroCheckN_iReg_imm0(cmpOpT cmp, iRegN_P2N value, immN0 zero, label labl) %{ 8313 match(If cmp (CmpN value zero)); 8314 effect(USE labl); 8315 predicate(TrapBasedNullChecks && 8316 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && 8317 _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) && 8318 Matcher::branches_to_uncommon_trap(_leaf)); 8319 size(6); 8320 8321 ins_is_TrapBasedCheckNode(true); 8322 8323 format %{ "ZeroCheckN value=$value cmp=$cmp zero=$zero => trap $labl" %} 8324 ins_encode %{ __ z_cit($value$$Register, 0, $cmp$$cmpcode); %} 8325 ins_pipe(pipe_class_trap); 8326 %} 8327 8328 //----------Compare instructions----------------------------------------------- 8329 8330 // INT signed 8331 8332 // Compare Integers 8333 instruct compI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{ 8334 match(Set cr (CmpI op1 op2)); 8335 size(2); 8336 format %{ "CR $op1,$op2" %} 8337 opcode(CR_ZOPC); 8338 ins_encode(z_rrform(op1, op2)); 8339 ins_pipe(pipe_class_dummy); 8340 %} 8341 8342 instruct compI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{ 8343 match(Set cr (CmpI op1 op2)); 8344 size(6); 8345 format %{ "CFI $op1,$op2" %} 8346 opcode(CFI_ZOPC); 8347 ins_encode(z_rilform_signed(op1, op2)); 8348 ins_pipe(pipe_class_dummy); 8349 %} 8350 8351 instruct compI_reg_imm16(flagsReg cr, iRegI op1, immI16 op2) %{ 8352 match(Set cr (CmpI op1 op2)); 8353 size(4); 8354 format %{ "CHI $op1,$op2" %} 8355 opcode(CHI_ZOPC); 8356 ins_encode(z_riform_signed(op1, op2)); 8357 ins_pipe(pipe_class_dummy); 8358 %} 8359 8360 instruct compI_reg_imm0(flagsReg cr, iRegI op1, immI_0 zero) %{ 8361 match(Set cr (CmpI op1 zero)); 8362 ins_cost(DEFAULT_COST_LOW); 8363 size(2); 8364 format %{ "LTR $op1,$op1" %} 8365 opcode(LTR_ZOPC); 8366 ins_encode(z_rrform(op1, op1)); 8367 ins_pipe(pipe_class_dummy); 8368 %} 8369 8370 instruct compI_reg_mem(flagsReg cr, iRegI op1, memory op2)%{ 8371 match(Set cr (CmpI op1 (LoadI op2))); 8372 ins_cost(MEMORY_REF_COST); 8373 // TODO: s390 port size(VARIABLE_SIZE); 8374 format %{ "C(Y) $op1, $op2\t # int" %} 8375 opcode(CY_ZOPC, C_ZOPC); 8376 ins_encode(z_form_rt_mem_opt(op1, op2)); 8377 ins_pipe(pipe_class_dummy); 8378 %} 8379 8380 // INT unsigned 8381 8382 instruct compU_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{ 8383 match(Set cr (CmpU op1 op2)); 8384 size(2); 8385 format %{ "CLR $op1,$op2\t # unsigned" %} 8386 opcode(CLR_ZOPC); 8387 ins_encode(z_rrform(op1, op2)); 8388 ins_pipe(pipe_class_dummy); 8389 %} 8390 8391 instruct compU_reg_uimm(flagsReg cr, iRegI op1, uimmI op2) %{ 8392 match(Set cr (CmpU op1 op2)); 8393 size(6); 8394 format %{ "CLFI $op1,$op2\t # unsigned" %} 8395 opcode(CLFI_ZOPC); 8396 ins_encode(z_rilform_unsigned(op1, op2)); 8397 ins_pipe(pipe_class_dummy); 8398 %} 8399 8400 instruct compU_reg_imm0(flagsReg cr, iRegI op1, immI_0 zero) %{ 8401 match(Set cr (CmpU op1 zero)); 8402 ins_cost(DEFAULT_COST_LOW); 8403 size(2); 8404 format %{ "LTR $op1,$op1\t # unsigned" %} 8405 opcode(LTR_ZOPC); 8406 ins_encode(z_rrform(op1, op1)); 8407 ins_pipe(pipe_class_dummy); 8408 %} 8409 8410 instruct compU_reg_mem(flagsReg cr, iRegI op1, memory op2)%{ 8411 match(Set cr (CmpU op1 (LoadI op2))); 8412 ins_cost(MEMORY_REF_COST); 8413 // TODO: s390 port size(VARIABLE_SIZE); 8414 format %{ "CL(Y) $op1, $op2\t # unsigned" %} 8415 opcode(CLY_ZOPC, CL_ZOPC); 8416 ins_encode(z_form_rt_mem_opt(op1, op2)); 8417 ins_pipe(pipe_class_dummy); 8418 %} 8419 8420 // LONG signed 8421 8422 instruct compL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{ 8423 match(Set cr (CmpL op1 op2)); 8424 size(4); 8425 format %{ "CGR $op1,$op2\t # long" %} 8426 opcode(CGR_ZOPC); 8427 ins_encode(z_rreform(op1, op2)); 8428 ins_pipe(pipe_class_dummy); 8429 %} 8430 8431 instruct compL_reg_regI(flagsReg cr, iRegL op1, iRegI op2) %{ 8432 match(Set cr (CmpL op1 (ConvI2L op2))); 8433 size(4); 8434 format %{ "CGFR $op1,$op2\t # long/int" %} 8435 opcode(CGFR_ZOPC); 8436 ins_encode(z_rreform(op1, op2)); 8437 ins_pipe(pipe_class_dummy); 8438 %} 8439 8440 instruct compL_reg_imm32(flagsReg cr, iRegL op1, immL32 con) %{ 8441 match(Set cr (CmpL op1 con)); 8442 size(6); 8443 format %{ "CGFI $op1,$con" %} 8444 opcode(CGFI_ZOPC); 8445 ins_encode(z_rilform_signed(op1, con)); 8446 ins_pipe(pipe_class_dummy); 8447 %} 8448 8449 instruct compL_reg_imm16(flagsReg cr, iRegL op1, immL16 con) %{ 8450 match(Set cr (CmpL op1 con)); 8451 size(4); 8452 format %{ "CGHI $op1,$con" %} 8453 opcode(CGHI_ZOPC); 8454 ins_encode(z_riform_signed(op1, con)); 8455 ins_pipe(pipe_class_dummy); 8456 %} 8457 8458 instruct compL_reg_imm0(flagsReg cr, iRegL op1, immL_0 con) %{ 8459 match(Set cr (CmpL op1 con)); 8460 ins_cost(DEFAULT_COST_LOW); 8461 size(4); 8462 format %{ "LTGR $op1,$op1" %} 8463 opcode(LTGR_ZOPC); 8464 ins_encode(z_rreform(op1, op1)); 8465 ins_pipe(pipe_class_dummy); 8466 %} 8467 8468 instruct compL_conv_reg_imm0(flagsReg cr, iRegI op1, immL_0 con) %{ 8469 match(Set cr (CmpL (ConvI2L op1) con)); 8470 ins_cost(DEFAULT_COST_LOW); 8471 size(4); 8472 format %{ "LTGFR $op1,$op1" %} 8473 opcode(LTGFR_ZOPC); 8474 ins_encode(z_rreform(op1, op1)); 8475 ins_pipe(pipe_class_dummy); 8476 %} 8477 8478 instruct compL_reg_mem(iRegL dst, memory src, flagsReg cr)%{ 8479 match(Set cr (CmpL dst (LoadL src))); 8480 ins_cost(MEMORY_REF_COST); 8481 size(Z_DISP3_SIZE); 8482 format %{ "CG $dst, $src\t # long" %} 8483 opcode(CG_ZOPC, CG_ZOPC); 8484 ins_encode(z_form_rt_mem_opt(dst, src)); 8485 ins_pipe(pipe_class_dummy); 8486 %} 8487 8488 instruct compL_reg_memI(iRegL dst, memory src, flagsReg cr)%{ 8489 match(Set cr (CmpL dst (ConvI2L (LoadI src)))); 8490 ins_cost(MEMORY_REF_COST); 8491 size(Z_DISP3_SIZE); 8492 format %{ "CGF $dst, $src\t # long/int" %} 8493 opcode(CGF_ZOPC, CGF_ZOPC); 8494 ins_encode(z_form_rt_mem_opt(dst, src)); 8495 ins_pipe(pipe_class_dummy); 8496 %} 8497 8498 // LONG unsigned 8499 // Added CmpUL for LoopPredicate. 8500 instruct compUL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{ 8501 match(Set cr (CmpUL op1 op2)); 8502 size(4); 8503 format %{ "CLGR $op1,$op2\t # long" %} 8504 opcode(CLGR_ZOPC); 8505 ins_encode(z_rreform(op1, op2)); 8506 ins_pipe(pipe_class_dummy); 8507 %} 8508 8509 instruct compUL_reg_imm32(flagsReg cr, iRegL op1, uimmL32 con) %{ 8510 match(Set cr (CmpUL op1 con)); 8511 size(6); 8512 format %{ "CLGFI $op1,$con" %} 8513 opcode(CLGFI_ZOPC); 8514 ins_encode(z_rilform_unsigned(op1, con)); 8515 ins_pipe(pipe_class_dummy); 8516 %} 8517 8518 // PTR unsigned 8519 8520 instruct compP_reg_reg(flagsReg cr, iRegP_N2P op1, iRegP_N2P op2) %{ 8521 match(Set cr (CmpP op1 op2)); 8522 size(4); 8523 format %{ "CLGR $op1,$op2\t # ptr" %} 8524 opcode(CLGR_ZOPC); 8525 ins_encode(z_rreform(op1, op2)); 8526 ins_pipe(pipe_class_dummy); 8527 %} 8528 8529 instruct compP_reg_imm0(flagsReg cr, iRegP_N2P op1, immP0 op2) %{ 8530 match(Set cr (CmpP op1 op2)); 8531 ins_cost(DEFAULT_COST_LOW); 8532 size(4); 8533 format %{ "LTGR $op1, $op1\t # ptr" %} 8534 opcode(LTGR_ZOPC); 8535 ins_encode(z_rreform(op1, op1)); 8536 ins_pipe(pipe_class_dummy); 8537 %} 8538 8539 // Don't use LTGFR which performs sign extend. 8540 instruct compP_decode_reg_imm0(flagsReg cr, iRegN op1, immP0 op2) %{ 8541 match(Set cr (CmpP (DecodeN op1) op2)); 8542 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0); 8543 ins_cost(DEFAULT_COST_LOW); 8544 size(2); 8545 format %{ "LTR $op1, $op1\t # ptr" %} 8546 opcode(LTR_ZOPC); 8547 ins_encode(z_rrform(op1, op1)); 8548 ins_pipe(pipe_class_dummy); 8549 %} 8550 8551 instruct compP_reg_mem(iRegP dst, memory src, flagsReg cr)%{ 8552 match(Set cr (CmpP dst (LoadP src))); 8553 ins_cost(MEMORY_REF_COST); 8554 size(Z_DISP3_SIZE); 8555 format %{ "CLG $dst, $src\t # ptr" %} 8556 opcode(CLG_ZOPC, CLG_ZOPC); 8557 ins_encode(z_form_rt_mem_opt(dst, src)); 8558 ins_pipe(pipe_class_dummy); 8559 %} 8560 8561 //----------Max and Min-------------------------------------------------------- 8562 8563 // Max Register with Register 8564 instruct z196_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8565 match(Set dst (MinI src1 src2)); 8566 effect(KILL cr); 8567 predicate(VM_Version::has_LoadStoreConditional()); 8568 ins_cost(3 * DEFAULT_COST); 8569 // TODO: s390 port size(VARIABLE_SIZE); 8570 format %{ "MinI $dst $src1,$src2\t MinI (z196 only)" %} 8571 ins_encode %{ 8572 Register Rdst = $dst$$Register; 8573 Register Rsrc1 = $src1$$Register; 8574 Register Rsrc2 = $src2$$Register; 8575 8576 if (Rsrc1 == Rsrc2) { 8577 if (Rdst != Rsrc1) { 8578 __ z_lgfr(Rdst, Rsrc1); 8579 } 8580 } else if (Rdst == Rsrc1) { // Rdst preset with src1. 8581 __ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotLow. 8582 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow); 8583 } else if (Rdst == Rsrc2) { // Rdst preset with src2. 8584 __ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotLow. 8585 __ z_locr(Rdst, Rsrc1, Assembler::bcondNotLow); 8586 } else { 8587 // Rdst is disjoint from operands, move in either case. 8588 __ z_cr(Rsrc1, Rsrc2); 8589 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow); 8590 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow); 8591 } 8592 %} 8593 ins_pipe(pipe_class_dummy); 8594 %} 8595 8596 // Min Register with Register. 8597 instruct z10_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8598 match(Set dst (MinI src1 src2)); 8599 effect(KILL cr); 8600 predicate(VM_Version::has_CompareBranch()); 8601 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8602 // TODO: s390 port size(VARIABLE_SIZE); 8603 format %{ "MinI $dst $src1,$src2\t MinI (z10 only)" %} 8604 ins_encode %{ 8605 Register Rdst = $dst$$Register; 8606 Register Rsrc1 = $src1$$Register; 8607 Register Rsrc2 = $src2$$Register; 8608 Label done; 8609 8610 if (Rsrc1 == Rsrc2) { 8611 if (Rdst != Rsrc1) { 8612 __ z_lgfr(Rdst, Rsrc1); 8613 } 8614 } else if (Rdst == Rsrc1) { 8615 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done); 8616 __ z_lgfr(Rdst, Rsrc2); 8617 } else if (Rdst == Rsrc2) { 8618 __ z_crj(Rsrc2, Rsrc1, Assembler::bcondLow, done); 8619 __ z_lgfr(Rdst, Rsrc1); 8620 } else { 8621 __ z_lgfr(Rdst, Rsrc1); 8622 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done); 8623 __ z_lgfr(Rdst, Rsrc2); 8624 } 8625 __ bind(done); 8626 %} 8627 ins_pipe(pipe_class_dummy); 8628 %} 8629 8630 instruct minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8631 match(Set dst (MinI src1 src2)); 8632 effect(KILL cr); 8633 predicate(!VM_Version::has_CompareBranch()); 8634 ins_cost(3 * DEFAULT_COST + BRANCH_COST); 8635 // TODO: s390 port size(VARIABLE_SIZE); 8636 format %{ "MinI $dst $src1,$src2\t MinI" %} 8637 ins_encode %{ 8638 Register Rdst = $dst$$Register; 8639 Register Rsrc1 = $src1$$Register; 8640 Register Rsrc2 = $src2$$Register; 8641 Label done; 8642 8643 if (Rsrc1 == Rsrc2) { 8644 if (Rdst != Rsrc1) { 8645 __ z_lgfr(Rdst, Rsrc1); 8646 } 8647 } else if (Rdst == Rsrc1) { 8648 __ z_cr(Rsrc1, Rsrc2); 8649 __ z_brl(done); 8650 __ z_lgfr(Rdst, Rsrc2); 8651 } else if (Rdst == Rsrc2) { 8652 __ z_cr(Rsrc2, Rsrc1); 8653 __ z_brl(done); 8654 __ z_lgfr(Rdst, Rsrc1); 8655 } else { 8656 __ z_lgfr(Rdst, Rsrc1); 8657 __ z_cr(Rsrc1, Rsrc2); 8658 __ z_brl(done); 8659 __ z_lgfr(Rdst, Rsrc2); 8660 } 8661 __ bind(done); 8662 %} 8663 ins_pipe(pipe_class_dummy); 8664 %} 8665 8666 instruct z196_minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{ 8667 match(Set dst (MinI src1 src2)); 8668 effect(KILL cr); 8669 predicate(VM_Version::has_LoadStoreConditional()); 8670 ins_cost(3 * DEFAULT_COST); 8671 // TODO: s390 port size(VARIABLE_SIZE); 8672 format %{ "MinI $dst $src1,$src2\t MinI const32 (z196 only)" %} 8673 ins_encode %{ 8674 Register Rdst = $dst$$Register; 8675 Register Rsrc1 = $src1$$Register; 8676 int Isrc2 = $src2$$constant; 8677 8678 if (Rdst == Rsrc1) { 8679 __ load_const_optimized(Z_R0_scratch, Isrc2); 8680 __ z_cfi(Rsrc1, Isrc2); 8681 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow); 8682 } else { 8683 __ load_const_optimized(Rdst, Isrc2); 8684 __ z_cfi(Rsrc1, Isrc2); 8685 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow); 8686 } 8687 %} 8688 ins_pipe(pipe_class_dummy); 8689 %} 8690 8691 instruct minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{ 8692 match(Set dst (MinI src1 src2)); 8693 effect(KILL cr); 8694 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8695 // TODO: s390 port size(VARIABLE_SIZE); 8696 format %{ "MinI $dst $src1,$src2\t MinI const32" %} 8697 ins_encode %{ 8698 Label done; 8699 if ($dst$$Register != $src1$$Register) { 8700 __ z_lgfr($dst$$Register, $src1$$Register); 8701 } 8702 __ z_cfi($src1$$Register, $src2$$constant); 8703 __ z_brl(done); 8704 __ z_lgfi($dst$$Register, $src2$$constant); 8705 __ bind(done); 8706 %} 8707 ins_pipe(pipe_class_dummy); 8708 %} 8709 8710 instruct z196_minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{ 8711 match(Set dst (MinI src1 src2)); 8712 effect(KILL cr); 8713 predicate(VM_Version::has_LoadStoreConditional()); 8714 ins_cost(3 * DEFAULT_COST); 8715 // TODO: s390 port size(VARIABLE_SIZE); 8716 format %{ "MinI $dst $src1,$src2\t MinI const16 (z196 only)" %} 8717 ins_encode %{ 8718 Register Rdst = $dst$$Register; 8719 Register Rsrc1 = $src1$$Register; 8720 int Isrc2 = $src2$$constant; 8721 8722 if (Rdst == Rsrc1) { 8723 __ load_const_optimized(Z_R0_scratch, Isrc2); 8724 __ z_chi(Rsrc1, Isrc2); 8725 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow); 8726 } else { 8727 __ load_const_optimized(Rdst, Isrc2); 8728 __ z_chi(Rsrc1, Isrc2); 8729 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow); 8730 } 8731 %} 8732 ins_pipe(pipe_class_dummy); 8733 %} 8734 8735 instruct minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{ 8736 match(Set dst (MinI src1 src2)); 8737 effect(KILL cr); 8738 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8739 // TODO: s390 port size(VARIABLE_SIZE); 8740 format %{ "MinI $dst $src1,$src2\t MinI const16" %} 8741 ins_encode %{ 8742 Label done; 8743 if ($dst$$Register != $src1$$Register) { 8744 __ z_lgfr($dst$$Register, $src1$$Register); 8745 } 8746 __ z_chi($src1$$Register, $src2$$constant); 8747 __ z_brl(done); 8748 __ z_lghi($dst$$Register, $src2$$constant); 8749 __ bind(done); 8750 %} 8751 ins_pipe(pipe_class_dummy); 8752 %} 8753 8754 instruct z10_minI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{ 8755 match(Set dst (MinI src1 src2)); 8756 effect(KILL cr); 8757 predicate(VM_Version::has_CompareBranch()); 8758 ins_cost(DEFAULT_COST + BRANCH_COST); 8759 // TODO: s390 port size(VARIABLE_SIZE); 8760 format %{ "MinI $dst $src1,$src2\t MinI const8 (z10 only)" %} 8761 ins_encode %{ 8762 Label done; 8763 if ($dst$$Register != $src1$$Register) { 8764 __ z_lgfr($dst$$Register, $src1$$Register); 8765 } 8766 __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondLow, done); 8767 __ z_lghi($dst$$Register, $src2$$constant); 8768 __ bind(done); 8769 %} 8770 ins_pipe(pipe_class_dummy); 8771 %} 8772 8773 // Max Register with Register 8774 instruct z196_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8775 match(Set dst (MaxI src1 src2)); 8776 effect(KILL cr); 8777 predicate(VM_Version::has_LoadStoreConditional()); 8778 ins_cost(3 * DEFAULT_COST); 8779 // TODO: s390 port size(VARIABLE_SIZE); 8780 format %{ "MaxI $dst $src1,$src2\t MaxI (z196 only)" %} 8781 ins_encode %{ 8782 Register Rdst = $dst$$Register; 8783 Register Rsrc1 = $src1$$Register; 8784 Register Rsrc2 = $src2$$Register; 8785 8786 if (Rsrc1 == Rsrc2) { 8787 if (Rdst != Rsrc1) { 8788 __ z_lgfr(Rdst, Rsrc1); 8789 } 8790 } else if (Rdst == Rsrc1) { // Rdst preset with src1. 8791 __ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotHigh. 8792 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh); 8793 } else if (Rdst == Rsrc2) { // Rdst preset with src2. 8794 __ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotHigh. 8795 __ z_locr(Rdst, Rsrc1, Assembler::bcondNotHigh); 8796 } else { // Rdst is disjoint from operands, move in either case. 8797 __ z_cr(Rsrc1, Rsrc2); 8798 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh); 8799 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh); 8800 } 8801 %} 8802 ins_pipe(pipe_class_dummy); 8803 %} 8804 8805 // Max Register with Register 8806 instruct z10_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8807 match(Set dst (MaxI src1 src2)); 8808 effect(KILL cr); 8809 predicate(VM_Version::has_CompareBranch()); 8810 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8811 // TODO: s390 port size(VARIABLE_SIZE); 8812 format %{ "MaxI $dst $src1,$src2\t MaxI (z10 only)" %} 8813 ins_encode %{ 8814 Register Rdst = $dst$$Register; 8815 Register Rsrc1 = $src1$$Register; 8816 Register Rsrc2 = $src2$$Register; 8817 Label done; 8818 8819 if (Rsrc1 == Rsrc2) { 8820 if (Rdst != Rsrc1) { 8821 __ z_lgfr(Rdst, Rsrc1); 8822 } 8823 } else if (Rdst == Rsrc1) { 8824 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done); 8825 __ z_lgfr(Rdst, Rsrc2); 8826 } else if (Rdst == Rsrc2) { 8827 __ z_crj(Rsrc2, Rsrc1, Assembler::bcondHigh, done); 8828 __ z_lgfr(Rdst, Rsrc1); 8829 } else { 8830 __ z_lgfr(Rdst, Rsrc1); 8831 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done); 8832 __ z_lgfr(Rdst, Rsrc2); 8833 } 8834 __ bind(done); 8835 %} 8836 ins_pipe(pipe_class_dummy); 8837 %} 8838 8839 instruct maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8840 match(Set dst (MaxI src1 src2)); 8841 effect(KILL cr); 8842 predicate(!VM_Version::has_CompareBranch()); 8843 ins_cost(3 * DEFAULT_COST + BRANCH_COST); 8844 // TODO: s390 port size(VARIABLE_SIZE); 8845 format %{ "MaxI $dst $src1,$src2\t MaxI" %} 8846 ins_encode %{ 8847 Register Rdst = $dst$$Register; 8848 Register Rsrc1 = $src1$$Register; 8849 Register Rsrc2 = $src2$$Register; 8850 Label done; 8851 8852 if (Rsrc1 == Rsrc2) { 8853 if (Rdst != Rsrc1) { 8854 __ z_lgfr(Rdst, Rsrc1); 8855 } 8856 } else if (Rdst == Rsrc1) { 8857 __ z_cr(Rsrc1, Rsrc2); 8858 __ z_brh(done); 8859 __ z_lgfr(Rdst, Rsrc2); 8860 } else if (Rdst == Rsrc2) { 8861 __ z_cr(Rsrc2, Rsrc1); 8862 __ z_brh(done); 8863 __ z_lgfr(Rdst, Rsrc1); 8864 } else { 8865 __ z_lgfr(Rdst, Rsrc1); 8866 __ z_cr(Rsrc1, Rsrc2); 8867 __ z_brh(done); 8868 __ z_lgfr(Rdst, Rsrc2); 8869 } 8870 8871 __ bind(done); 8872 %} 8873 8874 ins_pipe(pipe_class_dummy); 8875 %} 8876 8877 instruct z196_maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{ 8878 match(Set dst (MaxI src1 src2)); 8879 effect(KILL cr); 8880 predicate(VM_Version::has_LoadStoreConditional()); 8881 ins_cost(3 * DEFAULT_COST); 8882 // TODO: s390 port size(VARIABLE_SIZE); 8883 format %{ "MaxI $dst $src1,$src2\t MaxI const32 (z196 only)" %} 8884 ins_encode %{ 8885 Register Rdst = $dst$$Register; 8886 Register Rsrc1 = $src1$$Register; 8887 int Isrc2 = $src2$$constant; 8888 8889 if (Rdst == Rsrc1) { 8890 __ load_const_optimized(Z_R0_scratch, Isrc2); 8891 __ z_cfi(Rsrc1, Isrc2); 8892 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh); 8893 } else { 8894 __ load_const_optimized(Rdst, Isrc2); 8895 __ z_cfi(Rsrc1, Isrc2); 8896 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh); 8897 } 8898 %} 8899 ins_pipe(pipe_class_dummy); 8900 %} 8901 8902 instruct maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{ 8903 match(Set dst (MaxI src1 src2)); 8904 effect(KILL cr); 8905 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8906 // TODO: s390 port size(VARIABLE_SIZE); 8907 format %{ "MaxI $dst $src1,$src2\t MaxI const32" %} 8908 ins_encode %{ 8909 Label done; 8910 if ($dst$$Register != $src1$$Register) { 8911 __ z_lgfr($dst$$Register, $src1$$Register); 8912 } 8913 __ z_cfi($src1$$Register, $src2$$constant); 8914 __ z_brh(done); 8915 __ z_lgfi($dst$$Register, $src2$$constant); 8916 __ bind(done); 8917 %} 8918 ins_pipe(pipe_class_dummy); 8919 %} 8920 8921 instruct z196_maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{ 8922 match(Set dst (MaxI src1 src2)); 8923 effect(KILL cr); 8924 predicate(VM_Version::has_LoadStoreConditional()); 8925 ins_cost(3 * DEFAULT_COST); 8926 // TODO: s390 port size(VARIABLE_SIZE); 8927 format %{ "MaxI $dst $src1,$src2\t MaxI const16 (z196 only)" %} 8928 ins_encode %{ 8929 Register Rdst = $dst$$Register; 8930 Register Rsrc1 = $src1$$Register; 8931 int Isrc2 = $src2$$constant; 8932 if (Rdst == Rsrc1) { 8933 __ load_const_optimized(Z_R0_scratch, Isrc2); 8934 __ z_chi(Rsrc1, Isrc2); 8935 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh); 8936 } else { 8937 __ load_const_optimized(Rdst, Isrc2); 8938 __ z_chi(Rsrc1, Isrc2); 8939 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh); 8940 } 8941 %} 8942 ins_pipe(pipe_class_dummy); 8943 %} 8944 8945 instruct maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{ 8946 match(Set dst (MaxI src1 src2)); 8947 effect(KILL cr); 8948 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8949 // TODO: s390 port size(VARIABLE_SIZE); 8950 format %{ "MaxI $dst $src1,$src2\t MaxI const16" %} 8951 ins_encode %{ 8952 Label done; 8953 if ($dst$$Register != $src1$$Register) { 8954 __ z_lgfr($dst$$Register, $src1$$Register); 8955 } 8956 __ z_chi($src1$$Register, $src2$$constant); 8957 __ z_brh(done); 8958 __ z_lghi($dst$$Register, $src2$$constant); 8959 __ bind(done); 8960 %} 8961 ins_pipe(pipe_class_dummy); 8962 %} 8963 8964 instruct z10_maxI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{ 8965 match(Set dst (MaxI src1 src2)); 8966 effect(KILL cr); 8967 predicate(VM_Version::has_CompareBranch()); 8968 ins_cost(DEFAULT_COST + BRANCH_COST); 8969 // TODO: s390 port size(VARIABLE_SIZE); 8970 format %{ "MaxI $dst $src1,$src2\t MaxI const8" %} 8971 ins_encode %{ 8972 Label done; 8973 if ($dst$$Register != $src1$$Register) { 8974 __ z_lgfr($dst$$Register, $src1$$Register); 8975 } 8976 __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondHigh, done); 8977 __ z_lghi($dst$$Register, $src2$$constant); 8978 __ bind(done); 8979 %} 8980 ins_pipe(pipe_class_dummy); 8981 %} 8982 8983 //----------Abs--------------------------------------------------------------- 8984 8985 instruct absI_reg(iRegI dst, iRegI src, flagsReg cr) %{ 8986 match(Set dst (AbsI src)); 8987 effect(KILL cr); 8988 ins_cost(DEFAULT_COST_LOW); 8989 // TODO: s390 port size(FIXED_SIZE); 8990 format %{ "LPR $dst, $src" %} 8991 opcode(LPR_ZOPC); 8992 ins_encode(z_rrform(dst, src)); 8993 ins_pipe(pipe_class_dummy); 8994 %} 8995 8996 instruct negabsI_reg(iRegI dst, iRegI src, immI_0 zero, flagsReg cr) %{ 8997 match(Set dst (SubI zero (AbsI src))); 8998 effect(KILL cr); 8999 ins_cost(DEFAULT_COST_LOW); 9000 // TODO: s390 port size(FIXED_SIZE); 9001 format %{ "LNR $dst, $src" %} 9002 opcode(LNR_ZOPC); 9003 ins_encode(z_rrform(dst, src)); 9004 ins_pipe(pipe_class_dummy); 9005 %} 9006 9007 //----------Float Compares---------------------------------------------------- 9008 9009 // Compare floating, generate condition code. 9010 instruct cmpF_cc(flagsReg cr, regF src1, regF src2) %{ 9011 match(Set cr (CmpF src1 src2)); 9012 ins_cost(ALU_REG_COST); 9013 size(4); 9014 format %{ "FCMPcc $src1,$src2\t # float" %} 9015 ins_encode %{ __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister); %} 9016 ins_pipe(pipe_class_dummy); 9017 %} 9018 9019 instruct cmpD_cc(flagsReg cr, regD src1, regD src2) %{ 9020 match(Set cr (CmpD src1 src2)); 9021 ins_cost(ALU_REG_COST); 9022 size(4); 9023 format %{ "FCMPcc $src1,$src2 \t # double" %} 9024 ins_encode %{ __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister); %} 9025 ins_pipe(pipe_class_dummy); 9026 %} 9027 9028 instruct cmpF_cc_mem(flagsReg cr, regF src1, memoryRX src2) %{ 9029 match(Set cr (CmpF src1 (LoadF src2))); 9030 ins_cost(ALU_MEMORY_COST); 9031 size(6); 9032 format %{ "FCMPcc_mem $src1,$src2\t # floatMemory" %} 9033 opcode(CEB_ZOPC); 9034 ins_encode(z_form_rt_memFP(src1, src2)); 9035 ins_pipe(pipe_class_dummy); 9036 %} 9037 9038 instruct cmpD_cc_mem(flagsReg cr, regD src1, memoryRX src2) %{ 9039 match(Set cr (CmpD src1 (LoadD src2))); 9040 ins_cost(ALU_MEMORY_COST); 9041 size(6); 9042 format %{ "DCMPcc_mem $src1,$src2\t # doubleMemory" %} 9043 opcode(CDB_ZOPC); 9044 ins_encode(z_form_rt_memFP(src1, src2)); 9045 ins_pipe(pipe_class_dummy); 9046 %} 9047 9048 // Compare floating, generate condition code 9049 instruct cmpF0_cc(flagsReg cr, regF src1, immFpm0 src2) %{ 9050 match(Set cr (CmpF src1 src2)); 9051 ins_cost(DEFAULT_COST); 9052 size(4); 9053 format %{ "LTEBR $src1,$src1\t # float" %} 9054 opcode(LTEBR_ZOPC); 9055 ins_encode(z_rreform(src1, src1)); 9056 ins_pipe(pipe_class_dummy); 9057 %} 9058 9059 instruct cmpD0_cc(flagsReg cr, regD src1, immDpm0 src2) %{ 9060 match(Set cr (CmpD src1 src2)); 9061 ins_cost(DEFAULT_COST); 9062 size(4); 9063 format %{ "LTDBR $src1,$src1 \t # double" %} 9064 opcode(LTDBR_ZOPC); 9065 ins_encode(z_rreform(src1, src1)); 9066 ins_pipe(pipe_class_dummy); 9067 %} 9068 9069 // Compare floating, generate -1,0,1 9070 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsReg cr) %{ 9071 match(Set dst (CmpF3 src1 src2)); 9072 effect(KILL cr); 9073 ins_cost(DEFAULT_COST * 5 + BRANCH_COST); 9074 size(24); 9075 format %{ "CmpF3 $dst,$src1,$src2" %} 9076 ins_encode %{ 9077 // compare registers 9078 __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister); 9079 // Convert condition code into -1,0,1, where 9080 // -1 means unordered or less 9081 // 0 means equal 9082 // 1 means greater. 9083 if (VM_Version::has_LoadStoreConditional()) { 9084 Register one = Z_R0_scratch; 9085 Register minus_one = Z_R1_scratch; 9086 __ z_lghi(minus_one, -1); 9087 __ z_lghi(one, 1); 9088 __ z_lghi( $dst$$Register, 0); 9089 __ z_locgr($dst$$Register, one, Assembler::bcondHigh); 9090 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered); 9091 } else { 9092 Label done; 9093 __ clear_reg($dst$$Register, true, false); 9094 __ z_bre(done); 9095 __ z_lhi($dst$$Register, 1); 9096 __ z_brh(done); 9097 __ z_lhi($dst$$Register, -1); 9098 __ bind(done); 9099 } 9100 %} 9101 ins_pipe(pipe_class_dummy); 9102 %} 9103 9104 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsReg cr) %{ 9105 match(Set dst (CmpD3 src1 src2)); 9106 effect(KILL cr); 9107 ins_cost(DEFAULT_COST * 5 + BRANCH_COST); 9108 size(24); 9109 format %{ "CmpD3 $dst,$src1,$src2" %} 9110 ins_encode %{ 9111 // compare registers 9112 __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister); 9113 // Convert condition code into -1,0,1, where 9114 // -1 means unordered or less 9115 // 0 means equal 9116 // 1 means greater. 9117 if (VM_Version::has_LoadStoreConditional()) { 9118 Register one = Z_R0_scratch; 9119 Register minus_one = Z_R1_scratch; 9120 __ z_lghi(minus_one, -1); 9121 __ z_lghi(one, 1); 9122 __ z_lghi( $dst$$Register, 0); 9123 __ z_locgr($dst$$Register, one, Assembler::bcondHigh); 9124 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered); 9125 } else { 9126 Label done; 9127 // indicate unused result 9128 (void) __ clear_reg($dst$$Register, true, false); 9129 __ z_bre(done); 9130 __ z_lhi($dst$$Register, 1); 9131 __ z_brh(done); 9132 __ z_lhi($dst$$Register, -1); 9133 __ bind(done); 9134 } 9135 %} 9136 ins_pipe(pipe_class_dummy); 9137 %} 9138 9139 //----------Branches--------------------------------------------------------- 9140 // Jump 9141 9142 // Direct Branch. 9143 instruct branch(label labl) %{ 9144 match(Goto); 9145 effect(USE labl); 9146 ins_cost(BRANCH_COST); 9147 size(4); 9148 format %{ "BRU $labl" %} 9149 ins_encode(z_enc_bru(labl)); 9150 ins_pipe(pipe_class_dummy); 9151 // If set to 1 this indicates that the current instruction is a 9152 // short variant of a long branch. This avoids using this 9153 // instruction in first-pass matching. It will then only be used in 9154 // the `Shorten_branches' pass. 9155 ins_short_branch(1); 9156 %} 9157 9158 // Direct Branch. 9159 instruct branchFar(label labl) %{ 9160 match(Goto); 9161 effect(USE labl); 9162 ins_cost(BRANCH_COST); 9163 size(6); 9164 format %{ "BRUL $labl" %} 9165 ins_encode(z_enc_brul(labl)); 9166 ins_pipe(pipe_class_dummy); 9167 // This is not a short variant of a branch, but the long variant. 9168 ins_short_branch(0); 9169 %} 9170 9171 // Conditional Near Branch 9172 instruct branchCon(cmpOp cmp, flagsReg cr, label lbl) %{ 9173 // Same match rule as `branchConFar'. 9174 match(If cmp cr); 9175 effect(USE lbl); 9176 ins_cost(BRANCH_COST); 9177 size(4); 9178 format %{ "branch_con_short,$cmp $cr, $lbl" %} 9179 ins_encode(z_enc_branch_con_short(cmp, lbl)); 9180 ins_pipe(pipe_class_dummy); 9181 // If set to 1 this indicates that the current instruction is a 9182 // short variant of a long branch. This avoids using this 9183 // instruction in first-pass matching. It will then only be used in 9184 // the `Shorten_branches' pass. 9185 ins_short_branch(1); 9186 %} 9187 9188 // This is for cases when the z/Architecture conditional branch instruction 9189 // does not reach far enough. So we emit a far branch here, which is 9190 // more expensive. 9191 // 9192 // Conditional Far Branch 9193 instruct branchConFar(cmpOp cmp, flagsReg cr, label lbl) %{ 9194 // Same match rule as `branchCon'. 9195 match(If cmp cr); 9196 effect(USE cr, USE lbl); 9197 // Make more expensive to prefer compare_and_branch over separate instructions. 9198 ins_cost(2 * BRANCH_COST); 9199 size(6); 9200 format %{ "branch_con_far,$cmp $cr, $lbl" %} 9201 ins_encode(z_enc_branch_con_far(cmp, lbl)); 9202 ins_pipe(pipe_class_dummy); 9203 // This is not a short variant of a branch, but the long variant.. 9204 ins_short_branch(0); 9205 %} 9206 9207 instruct branchLoopEnd(cmpOp cmp, flagsReg cr, label labl) %{ 9208 match(CountedLoopEnd cmp cr); 9209 effect(USE labl); 9210 ins_cost(BRANCH_COST); 9211 size(4); 9212 format %{ "branch_con_short,$cmp $labl\t # counted loop end" %} 9213 ins_encode(z_enc_branch_con_short(cmp, labl)); 9214 ins_pipe(pipe_class_dummy); 9215 // If set to 1 this indicates that the current instruction is a 9216 // short variant of a long branch. This avoids using this 9217 // instruction in first-pass matching. It will then only be used in 9218 // the `Shorten_branches' pass. 9219 ins_short_branch(1); 9220 %} 9221 9222 instruct branchLoopEndFar(cmpOp cmp, flagsReg cr, label labl) %{ 9223 match(CountedLoopEnd cmp cr); 9224 effect(USE labl); 9225 ins_cost(BRANCH_COST); 9226 size(6); 9227 format %{ "branch_con_far,$cmp $labl\t # counted loop end" %} 9228 ins_encode(z_enc_branch_con_far(cmp, labl)); 9229 ins_pipe(pipe_class_dummy); 9230 // This is not a short variant of a branch, but the long variant. 9231 ins_short_branch(0); 9232 %} 9233 9234 //----------Compare and Branch (short distance)------------------------------ 9235 9236 // INT REG operands for loop counter processing. 9237 instruct testAndBranchLoopEnd_Reg(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9238 match(CountedLoopEnd boolnode (CmpI src1 src2)); 9239 effect(USE labl, KILL cr); 9240 predicate(VM_Version::has_CompareBranch()); 9241 ins_cost(BRANCH_COST); 9242 // TODO: s390 port size(FIXED_SIZE); 9243 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %} 9244 opcode(CRJ_ZOPC); 9245 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9246 ins_pipe(pipe_class_dummy); 9247 ins_short_branch(1); 9248 %} 9249 9250 // INT REG operands. 9251 instruct cmpb_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9252 match(If boolnode (CmpI src1 src2)); 9253 effect(USE labl, KILL cr); 9254 predicate(VM_Version::has_CompareBranch()); 9255 ins_cost(BRANCH_COST); 9256 // TODO: s390 port size(FIXED_SIZE); 9257 format %{ "CRJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9258 opcode(CRJ_ZOPC); 9259 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9260 ins_pipe(pipe_class_dummy); 9261 ins_short_branch(1); 9262 %} 9263 9264 // Unsigned INT REG operands 9265 instruct cmpbU_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9266 match(If boolnode (CmpU src1 src2)); 9267 effect(USE labl, KILL cr); 9268 predicate(VM_Version::has_CompareBranch()); 9269 ins_cost(BRANCH_COST); 9270 // TODO: s390 port size(FIXED_SIZE); 9271 format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9272 opcode(CLRJ_ZOPC); 9273 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9274 ins_pipe(pipe_class_dummy); 9275 ins_short_branch(1); 9276 %} 9277 9278 // LONG REG operands 9279 instruct cmpb_RegL(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{ 9280 match(If boolnode (CmpL src1 src2)); 9281 effect(USE labl, KILL cr); 9282 predicate(VM_Version::has_CompareBranch()); 9283 ins_cost(BRANCH_COST); 9284 // TODO: s390 port size(FIXED_SIZE); 9285 format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9286 opcode(CGRJ_ZOPC); 9287 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9288 ins_pipe(pipe_class_dummy); 9289 ins_short_branch(1); 9290 %} 9291 9292 // PTR REG operands 9293 9294 // Separate rules for regular and narrow oops. ADLC can't recognize 9295 // rules with polymorphic operands to be sisters -> shorten_branches 9296 // will not shorten. 9297 9298 instruct cmpb_RegPP(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{ 9299 match(If boolnode (CmpP src1 src2)); 9300 effect(USE labl, KILL cr); 9301 predicate(VM_Version::has_CompareBranch()); 9302 ins_cost(BRANCH_COST); 9303 // TODO: s390 port size(FIXED_SIZE); 9304 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9305 opcode(CLGRJ_ZOPC); 9306 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9307 ins_pipe(pipe_class_dummy); 9308 ins_short_branch(1); 9309 %} 9310 9311 instruct cmpb_RegNN(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{ 9312 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2))); 9313 effect(USE labl, KILL cr); 9314 predicate(VM_Version::has_CompareBranch()); 9315 ins_cost(BRANCH_COST); 9316 // TODO: s390 port size(FIXED_SIZE); 9317 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9318 opcode(CLGRJ_ZOPC); 9319 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9320 ins_pipe(pipe_class_dummy); 9321 ins_short_branch(1); 9322 %} 9323 9324 // INT REG/IMM operands for loop counter processing 9325 instruct testAndBranchLoopEnd_Imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{ 9326 match(CountedLoopEnd boolnode (CmpI src1 src2)); 9327 effect(USE labl, KILL cr); 9328 predicate(VM_Version::has_CompareBranch()); 9329 ins_cost(BRANCH_COST); 9330 // TODO: s390 port size(FIXED_SIZE); 9331 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %} 9332 opcode(CIJ_ZOPC); 9333 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9334 ins_pipe(pipe_class_dummy); 9335 ins_short_branch(1); 9336 %} 9337 9338 // INT REG/IMM operands 9339 instruct cmpb_RegI_imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{ 9340 match(If boolnode (CmpI src1 src2)); 9341 effect(USE labl, KILL cr); 9342 predicate(VM_Version::has_CompareBranch()); 9343 ins_cost(BRANCH_COST); 9344 // TODO: s390 port size(FIXED_SIZE); 9345 format %{ "CIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9346 opcode(CIJ_ZOPC); 9347 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9348 ins_pipe(pipe_class_dummy); 9349 ins_short_branch(1); 9350 %} 9351 9352 // INT REG/IMM operands 9353 instruct cmpbU_RegI_imm(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{ 9354 match(If boolnode (CmpU src1 src2)); 9355 effect(USE labl, KILL cr); 9356 predicate(VM_Version::has_CompareBranch()); 9357 ins_cost(BRANCH_COST); 9358 // TODO: s390 port size(FIXED_SIZE); 9359 format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9360 opcode(CLIJ_ZOPC); 9361 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9362 ins_pipe(pipe_class_dummy); 9363 ins_short_branch(1); 9364 %} 9365 9366 // LONG REG/IMM operands 9367 instruct cmpb_RegL_imm(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{ 9368 match(If boolnode (CmpL src1 src2)); 9369 effect(USE labl, KILL cr); 9370 predicate(VM_Version::has_CompareBranch()); 9371 ins_cost(BRANCH_COST); 9372 // TODO: s390 port size(FIXED_SIZE); 9373 format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9374 opcode(CGIJ_ZOPC); 9375 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9376 ins_pipe(pipe_class_dummy); 9377 ins_short_branch(1); 9378 %} 9379 9380 // PTR REG-imm operands 9381 9382 // Separate rules for regular and narrow oops. ADLC can't recognize 9383 // rules with polymorphic operands to be sisters -> shorten_branches 9384 // will not shorten. 9385 9386 instruct cmpb_RegP_immP(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{ 9387 match(If boolnode (CmpP src1 src2)); 9388 effect(USE labl, KILL cr); 9389 predicate(VM_Version::has_CompareBranch()); 9390 ins_cost(BRANCH_COST); 9391 // TODO: s390 port size(FIXED_SIZE); 9392 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9393 opcode(CLGIJ_ZOPC); 9394 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9395 ins_pipe(pipe_class_dummy); 9396 ins_short_branch(1); 9397 %} 9398 9399 // Compare against zero only, do not mix N and P oops (encode/decode required). 9400 instruct cmpb_RegN_immP0(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{ 9401 match(If boolnode (CmpP (DecodeN src1) src2)); 9402 effect(USE labl, KILL cr); 9403 predicate(VM_Version::has_CompareBranch()); 9404 ins_cost(BRANCH_COST); 9405 // TODO: s390 port size(FIXED_SIZE); 9406 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9407 opcode(CLGIJ_ZOPC); 9408 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9409 ins_pipe(pipe_class_dummy); 9410 ins_short_branch(1); 9411 %} 9412 9413 instruct cmpb_RegN_imm(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{ 9414 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2))); 9415 effect(USE labl, KILL cr); 9416 predicate(VM_Version::has_CompareBranch()); 9417 ins_cost(BRANCH_COST); 9418 // TODO: s390 port size(FIXED_SIZE); 9419 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9420 opcode(CLGIJ_ZOPC); 9421 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9422 ins_pipe(pipe_class_dummy); 9423 ins_short_branch(1); 9424 %} 9425 9426 9427 //----------Compare and Branch (far distance)------------------------------ 9428 9429 // INT REG operands for loop counter processing 9430 instruct testAndBranchLoopEnd_RegFar(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9431 match(CountedLoopEnd boolnode (CmpI src1 src2)); 9432 effect(USE labl, KILL cr); 9433 predicate(VM_Version::has_CompareBranch()); 9434 ins_cost(BRANCH_COST+DEFAULT_COST); 9435 // TODO: s390 port size(FIXED_SIZE); 9436 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %} 9437 opcode(CR_ZOPC, BRCL_ZOPC); 9438 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9439 ins_pipe(pipe_class_dummy); 9440 ins_short_branch(0); 9441 %} 9442 9443 // INT REG operands 9444 instruct cmpb_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9445 match(If boolnode (CmpI src1 src2)); 9446 effect(USE labl, KILL cr); 9447 predicate(VM_Version::has_CompareBranch()); 9448 ins_cost(BRANCH_COST+DEFAULT_COST); 9449 // TODO: s390 port size(FIXED_SIZE); 9450 format %{ "CRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9451 opcode(CR_ZOPC, BRCL_ZOPC); 9452 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9453 ins_pipe(pipe_class_dummy); 9454 ins_short_branch(0); 9455 %} 9456 9457 // INT REG operands 9458 instruct cmpbU_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9459 match(If boolnode (CmpU src1 src2)); 9460 effect(USE labl, KILL cr); 9461 predicate(VM_Version::has_CompareBranch()); 9462 ins_cost(BRANCH_COST+DEFAULT_COST); 9463 // TODO: s390 port size(FIXED_SIZE); 9464 format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9465 opcode(CLR_ZOPC, BRCL_ZOPC); 9466 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9467 ins_pipe(pipe_class_dummy); 9468 ins_short_branch(0); 9469 %} 9470 9471 // LONG REG operands 9472 instruct cmpb_RegL_Far(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{ 9473 match(If boolnode (CmpL src1 src2)); 9474 effect(USE labl, KILL cr); 9475 predicate(VM_Version::has_CompareBranch()); 9476 ins_cost(BRANCH_COST+DEFAULT_COST); 9477 // TODO: s390 port size(FIXED_SIZE); 9478 format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9479 opcode(CGR_ZOPC, BRCL_ZOPC); 9480 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9481 ins_pipe(pipe_class_dummy); 9482 ins_short_branch(0); 9483 %} 9484 9485 // PTR REG operands 9486 9487 // Separate rules for regular and narrow oops. ADLC can't recognize 9488 // rules with polymorphic operands to be sisters -> shorten_branches 9489 // will not shorten. 9490 9491 instruct cmpb_RegPP_Far(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{ 9492 match(If boolnode (CmpP src1 src2)); 9493 effect(USE labl, KILL cr); 9494 predicate(VM_Version::has_CompareBranch()); 9495 ins_cost(BRANCH_COST+DEFAULT_COST); 9496 // TODO: s390 port size(FIXED_SIZE); 9497 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9498 opcode(CLGR_ZOPC, BRCL_ZOPC); 9499 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9500 ins_pipe(pipe_class_dummy); 9501 ins_short_branch(0); 9502 %} 9503 9504 instruct cmpb_RegNN_Far(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{ 9505 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2))); 9506 effect(USE labl, KILL cr); 9507 predicate(VM_Version::has_CompareBranch()); 9508 ins_cost(BRANCH_COST+DEFAULT_COST); 9509 // TODO: s390 port size(FIXED_SIZE); 9510 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9511 opcode(CLGR_ZOPC, BRCL_ZOPC); 9512 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9513 ins_pipe(pipe_class_dummy); 9514 ins_short_branch(0); 9515 %} 9516 9517 // INT REG/IMM operands for loop counter processing 9518 instruct testAndBranchLoopEnd_ImmFar(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{ 9519 match(CountedLoopEnd boolnode (CmpI src1 src2)); 9520 effect(USE labl, KILL cr); 9521 predicate(VM_Version::has_CompareBranch()); 9522 ins_cost(BRANCH_COST+DEFAULT_COST); 9523 // TODO: s390 port size(FIXED_SIZE); 9524 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %} 9525 opcode(CHI_ZOPC, BRCL_ZOPC); 9526 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9527 ins_pipe(pipe_class_dummy); 9528 ins_short_branch(0); 9529 %} 9530 9531 // INT REG/IMM operands 9532 instruct cmpb_RegI_imm_Far(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{ 9533 match(If boolnode (CmpI src1 src2)); 9534 effect(USE labl, KILL cr); 9535 predicate(VM_Version::has_CompareBranch()); 9536 ins_cost(BRANCH_COST+DEFAULT_COST); 9537 // TODO: s390 port size(FIXED_SIZE); 9538 format %{ "CIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9539 opcode(CHI_ZOPC, BRCL_ZOPC); 9540 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9541 ins_pipe(pipe_class_dummy); 9542 ins_short_branch(0); 9543 %} 9544 9545 // INT REG/IMM operands 9546 instruct cmpbU_RegI_imm_Far(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{ 9547 match(If boolnode (CmpU src1 src2)); 9548 effect(USE labl, KILL cr); 9549 predicate(VM_Version::has_CompareBranch()); 9550 ins_cost(BRANCH_COST+DEFAULT_COST); 9551 // TODO: s390 port size(FIXED_SIZE); 9552 format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9553 opcode(CLFI_ZOPC, BRCL_ZOPC); 9554 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9555 ins_pipe(pipe_class_dummy); 9556 ins_short_branch(0); 9557 %} 9558 9559 // LONG REG/IMM operands 9560 instruct cmpb_RegL_imm_Far(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{ 9561 match(If boolnode (CmpL src1 src2)); 9562 effect(USE labl, KILL cr); 9563 predicate(VM_Version::has_CompareBranch()); 9564 ins_cost(BRANCH_COST+DEFAULT_COST); 9565 // TODO: s390 port size(FIXED_SIZE); 9566 format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9567 opcode(CGHI_ZOPC, BRCL_ZOPC); 9568 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9569 ins_pipe(pipe_class_dummy); 9570 ins_short_branch(0); 9571 %} 9572 9573 // PTR REG-imm operands 9574 9575 // Separate rules for regular and narrow oops. ADLC can't recognize 9576 // rules with polymorphic operands to be sisters -> shorten_branches 9577 // will not shorten. 9578 9579 instruct cmpb_RegP_immP_Far(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{ 9580 match(If boolnode (CmpP src1 src2)); 9581 effect(USE labl, KILL cr); 9582 predicate(VM_Version::has_CompareBranch()); 9583 ins_cost(BRANCH_COST+DEFAULT_COST); 9584 // TODO: s390 port size(FIXED_SIZE); 9585 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9586 opcode(CLGFI_ZOPC, BRCL_ZOPC); 9587 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9588 ins_pipe(pipe_class_dummy); 9589 ins_short_branch(0); 9590 %} 9591 9592 // Compare against zero only, do not mix N and P oops (encode/decode required). 9593 instruct cmpb_RegN_immP0_Far(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{ 9594 match(If boolnode (CmpP (DecodeN src1) src2)); 9595 effect(USE labl, KILL cr); 9596 predicate(VM_Version::has_CompareBranch()); 9597 ins_cost(BRANCH_COST+DEFAULT_COST); 9598 // TODO: s390 port size(FIXED_SIZE); 9599 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9600 opcode(CLGFI_ZOPC, BRCL_ZOPC); 9601 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9602 ins_pipe(pipe_class_dummy); 9603 ins_short_branch(0); 9604 %} 9605 9606 instruct cmpb_RegN_immN_Far(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{ 9607 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2))); 9608 effect(USE labl, KILL cr); 9609 predicate(VM_Version::has_CompareBranch()); 9610 ins_cost(BRANCH_COST+DEFAULT_COST); 9611 // TODO: s390 port size(FIXED_SIZE); 9612 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9613 opcode(CLGFI_ZOPC, BRCL_ZOPC); 9614 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9615 ins_pipe(pipe_class_dummy); 9616 ins_short_branch(0); 9617 %} 9618 9619 // ============================================================================ 9620 // Long Compare 9621 9622 // Due to a shortcoming in the ADLC, it mixes up expressions like: 9623 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 9624 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections 9625 // are collapsed internally in the ADLC's dfa-gen code. The match for 9626 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 9627 // foo match ends up with the wrong leaf. One fix is to not match both 9628 // reg-reg and reg-zero forms of long-compare. This is unfortunate because 9629 // both forms beat the trinary form of long-compare and both are very useful 9630 // on platforms which have few registers. 9631 9632 // Manifest a CmpL3 result in an integer register. Very painful. 9633 // This is the test to avoid. 9634 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr) %{ 9635 match(Set dst (CmpL3 src1 src2)); 9636 effect(KILL cr); 9637 ins_cost(DEFAULT_COST * 5 + BRANCH_COST); 9638 size(24); 9639 format %{ "CmpL3 $dst,$src1,$src2" %} 9640 ins_encode %{ 9641 Label done; 9642 // compare registers 9643 __ z_cgr($src1$$Register, $src2$$Register); 9644 // Convert condition code into -1,0,1, where 9645 // -1 means less 9646 // 0 means equal 9647 // 1 means greater. 9648 if (VM_Version::has_LoadStoreConditional()) { 9649 Register one = Z_R0_scratch; 9650 Register minus_one = Z_R1_scratch; 9651 __ z_lghi(minus_one, -1); 9652 __ z_lghi(one, 1); 9653 __ z_lghi( $dst$$Register, 0); 9654 __ z_locgr($dst$$Register, one, Assembler::bcondHigh); 9655 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLow); 9656 } else { 9657 __ clear_reg($dst$$Register, true, false); 9658 __ z_bre(done); 9659 __ z_lhi($dst$$Register, 1); 9660 __ z_brh(done); 9661 __ z_lhi($dst$$Register, -1); 9662 } 9663 __ bind(done); 9664 %} 9665 ins_pipe(pipe_class_dummy); 9666 %} 9667 9668 // ============================================================================ 9669 // Safepoint Instruction 9670 9671 instruct safePoint() %{ 9672 match(SafePoint); 9673 predicate(false); 9674 // TODO: s390 port size(FIXED_SIZE); 9675 format %{ "UNIMPLEMENTED Safepoint_ " %} 9676 ins_encode(enc_unimplemented()); 9677 ins_pipe(pipe_class_dummy); 9678 %} 9679 9680 instruct safePoint_poll(iRegP poll, flagsReg cr) %{ 9681 match(SafePoint poll); 9682 effect(USE poll, KILL cr); // R0 is killed, too. 9683 // TODO: s390 port size(FIXED_SIZE); 9684 format %{ "TM #0[,$poll],#111\t # Safepoint: poll for GC" %} 9685 ins_encode %{ 9686 // Mark the code position where the load from the safepoint 9687 // polling page was emitted as relocInfo::poll_type. 9688 __ relocate(relocInfo::poll_type); 9689 __ load_from_polling_page($poll$$Register); 9690 %} 9691 ins_pipe(pipe_class_dummy); 9692 %} 9693 9694 // ============================================================================ 9695 9696 // Call Instructions 9697 9698 // Call Java Static Instruction 9699 instruct CallStaticJavaDirect_dynTOC(method meth) %{ 9700 match(CallStaticJava); 9701 effect(USE meth); 9702 ins_cost(CALL_COST); 9703 // TODO: s390 port size(VARIABLE_SIZE); 9704 format %{ "CALL,static dynTOC $meth; ==> " %} 9705 ins_encode( z_enc_java_static_call(meth) ); 9706 ins_pipe(pipe_class_dummy); 9707 ins_alignment(2); 9708 %} 9709 9710 // Call Java Dynamic Instruction 9711 instruct CallDynamicJavaDirect_dynTOC(method meth) %{ 9712 match(CallDynamicJava); 9713 effect(USE meth); 9714 ins_cost(CALL_COST); 9715 // TODO: s390 port size(VARIABLE_SIZE); 9716 format %{ "CALL,dynamic dynTOC $meth; ==> " %} 9717 ins_encode(z_enc_java_dynamic_call(meth)); 9718 ins_pipe(pipe_class_dummy); 9719 ins_alignment(2); 9720 %} 9721 9722 // Call Runtime Instruction 9723 instruct CallRuntimeDirect(method meth) %{ 9724 match(CallRuntime); 9725 effect(USE meth); 9726 ins_cost(CALL_COST); 9727 // TODO: s390 port size(VARIABLE_SIZE); 9728 ins_num_consts(1); 9729 ins_alignment(2); 9730 format %{ "CALL,runtime" %} 9731 ins_encode( z_enc_java_to_runtime_call(meth) ); 9732 ins_pipe(pipe_class_dummy); 9733 %} 9734 9735 // Call runtime without safepoint - same as CallRuntime 9736 instruct CallLeafDirect(method meth) %{ 9737 match(CallLeaf); 9738 effect(USE meth); 9739 ins_cost(CALL_COST); 9740 // TODO: s390 port size(VARIABLE_SIZE); 9741 ins_num_consts(1); 9742 ins_alignment(2); 9743 format %{ "CALL,runtime leaf $meth" %} 9744 ins_encode( z_enc_java_to_runtime_call(meth) ); 9745 ins_pipe(pipe_class_dummy); 9746 %} 9747 9748 // Call runtime without safepoint - same as CallLeaf 9749 instruct CallLeafNoFPDirect(method meth) %{ 9750 match(CallLeafNoFP); 9751 effect(USE meth); 9752 ins_cost(CALL_COST); 9753 // TODO: s390 port size(VARIABLE_SIZE); 9754 ins_num_consts(1); 9755 format %{ "CALL,runtime leaf nofp $meth" %} 9756 ins_encode( z_enc_java_to_runtime_call(meth) ); 9757 ins_pipe(pipe_class_dummy); 9758 ins_alignment(2); 9759 %} 9760 9761 // Tail Call; Jump from runtime stub to Java code. 9762 // Also known as an 'interprocedural jump'. 9763 // Target of jump will eventually return to caller. 9764 // TailJump below removes the return address. 9765 instruct TailCalljmpInd(iRegP jump_target, inline_cache_regP method_oop) %{ 9766 match(TailCall jump_target method_oop); 9767 ins_cost(CALL_COST); 9768 size(2); 9769 format %{ "Jmp $jump_target\t# $method_oop holds method oop" %} 9770 ins_encode %{ __ z_br($jump_target$$Register); %} 9771 ins_pipe(pipe_class_dummy); 9772 %} 9773 9774 // Return Instruction 9775 instruct Ret() %{ 9776 match(Return); 9777 size(2); 9778 format %{ "BR(Z_R14) // branch to link register" %} 9779 ins_encode %{ __ z_br(Z_R14); %} 9780 ins_pipe(pipe_class_dummy); 9781 %} 9782 9783 // Tail Jump; remove the return address; jump to target. 9784 // TailCall above leaves the return address around. 9785 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 9786 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 9787 // "restore" before this instruction (in Epilogue), we need to materialize it 9788 // in %i0. 9789 instruct tailjmpInd(iRegP jump_target, rarg1RegP ex_oop) %{ 9790 match(TailJump jump_target ex_oop); 9791 ins_cost(CALL_COST); 9792 size(8); 9793 format %{ "TailJump $jump_target" %} 9794 ins_encode %{ 9795 __ z_lg(Z_ARG2/* issuing pc */, _z_abi(return_pc), Z_SP); 9796 __ z_br($jump_target$$Register); 9797 %} 9798 ins_pipe(pipe_class_dummy); 9799 %} 9800 9801 // Create exception oop: created by stack-crawling runtime code. 9802 // Created exception is now available to this handler, and is setup 9803 // just prior to jumping to this handler. No code emitted. 9804 instruct CreateException(rarg1RegP ex_oop) %{ 9805 match(Set ex_oop (CreateEx)); 9806 ins_cost(0); 9807 size(0); 9808 format %{ "# exception oop; no code emitted" %} 9809 ins_encode(/*empty*/); 9810 ins_pipe(pipe_class_dummy); 9811 %} 9812 9813 // Rethrow exception: The exception oop will come in the first 9814 // argument position. Then JUMP (not call) to the rethrow stub code. 9815 instruct RethrowException() %{ 9816 match(Rethrow); 9817 ins_cost(CALL_COST); 9818 // TODO: s390 port size(VARIABLE_SIZE); 9819 format %{ "Jmp rethrow_stub" %} 9820 ins_encode %{ 9821 cbuf.set_insts_mark(); 9822 __ load_const_optimized(Z_R1_scratch, (address)OptoRuntime::rethrow_stub()); 9823 __ z_br(Z_R1_scratch); 9824 %} 9825 ins_pipe(pipe_class_dummy); 9826 %} 9827 9828 // Die now. 9829 instruct ShouldNotReachHere() %{ 9830 match(Halt); 9831 ins_cost(CALL_COST); 9832 size(2); 9833 format %{ "ILLTRAP; ShouldNotReachHere" %} 9834 ins_encode %{ __ z_illtrap(); %} 9835 ins_pipe(pipe_class_dummy); 9836 %} 9837 9838 // ============================================================================ 9839 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 9840 // array for an instance of the superklass. Set a hidden internal cache on a 9841 // hit (cache is checked with exposed code in gen_subtype_check()). Return 9842 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. 9843 instruct partialSubtypeCheck(rarg1RegP index, rarg2RegP sub, rarg3RegP super, flagsReg pcc, 9844 rarg4RegP scratch1, rarg5RegP scratch2) %{ 9845 match(Set index (PartialSubtypeCheck sub super)); 9846 effect(KILL pcc, KILL scratch1, KILL scratch2); 9847 ins_cost(10 * DEFAULT_COST); 9848 size(12); 9849 format %{ " CALL PartialSubtypeCheck\n" %} 9850 ins_encode %{ 9851 AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check()); 9852 __ load_const_optimized(Z_ARG4, stub_address); 9853 __ z_basr(Z_R14, Z_ARG4); 9854 %} 9855 ins_pipe(pipe_class_dummy); 9856 %} 9857 9858 instruct partialSubtypeCheck_vs_zero(flagsReg pcc, rarg2RegP sub, rarg3RegP super, immP0 zero, 9859 rarg1RegP index, rarg4RegP scratch1, rarg5RegP scratch2) %{ 9860 match(Set pcc (CmpI (PartialSubtypeCheck sub super) zero)); 9861 effect(KILL scratch1, KILL scratch2, KILL index); 9862 ins_cost(10 * DEFAULT_COST); 9863 // TODO: s390 port size(FIXED_SIZE); 9864 format %{ "CALL PartialSubtypeCheck_vs_zero\n" %} 9865 ins_encode %{ 9866 AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check()); 9867 __ load_const_optimized(Z_ARG4, stub_address); 9868 __ z_basr(Z_R14, Z_ARG4); 9869 %} 9870 ins_pipe(pipe_class_dummy); 9871 %} 9872 9873 // ============================================================================ 9874 // inlined locking and unlocking 9875 9876 instruct cmpFastLock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{ 9877 match(Set pcc (FastLock oop box)); 9878 effect(TEMP tmp1, TEMP tmp2); 9879 ins_cost(100); 9880 // TODO: s390 port size(VARIABLE_SIZE); // Uses load_const_optimized. 9881 format %{ "FASTLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %} 9882 ins_encode %{ __ compiler_fast_lock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register, 9883 UseBiasedLocking && !UseOptoBiasInlining); %} 9884 ins_pipe(pipe_class_dummy); 9885 %} 9886 9887 instruct cmpFastUnlock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{ 9888 match(Set pcc (FastUnlock oop box)); 9889 effect(TEMP tmp1, TEMP tmp2); 9890 ins_cost(100); 9891 // TODO: s390 port size(FIXED_SIZE); // emitted code depends on UseBiasedLocking being on/off. 9892 format %{ "FASTUNLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %} 9893 ins_encode %{ __ compiler_fast_unlock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register, 9894 UseBiasedLocking && !UseOptoBiasInlining); %} 9895 ins_pipe(pipe_class_dummy); 9896 %} 9897 9898 instruct inlineCallClearArrayConst(SSlenDW cnt, iRegP_N2P base, Universe dummy, flagsReg cr) %{ 9899 match(Set dummy (ClearArray cnt base)); 9900 effect(KILL cr); 9901 ins_cost(100); 9902 // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to varying #instructions. 9903 format %{ "ClearArrayConst $cnt,$base" %} 9904 ins_encode %{ __ Clear_Array_Const($cnt$$constant, $base$$Register); %} 9905 ins_pipe(pipe_class_dummy); 9906 %} 9907 9908 instruct inlineCallClearArrayConstBig(immL cnt, iRegP_N2P base, Universe dummy, revenRegL srcA, roddRegL srcL, flagsReg cr) %{ 9909 match(Set dummy (ClearArray cnt base)); 9910 effect(TEMP srcA, TEMP srcL, KILL cr); // R0, R1 are killed, too. 9911 ins_cost(200); 9912 // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to optimized constant loader. 9913 format %{ "ClearArrayConstBig $cnt,$base" %} 9914 ins_encode %{ __ Clear_Array_Const_Big($cnt$$constant, $base$$Register, $srcA$$Register, $srcL$$Register); %} 9915 ins_pipe(pipe_class_dummy); 9916 %} 9917 9918 instruct inlineCallClearArray(iRegL cnt, iRegP_N2P base, Universe dummy, revenRegL srcA, roddRegL srcL, flagsReg cr) %{ 9919 match(Set dummy (ClearArray cnt base)); 9920 effect(TEMP srcA, TEMP srcL, KILL cr); // R0, R1 are killed, too. 9921 ins_cost(300); 9922 // TODO: s390 port size(FIXED_SIZE); // z/Architecture: emitted code depends on PreferLAoverADD being on/off. 9923 format %{ "ClearArrayVar $cnt,$base" %} 9924 ins_encode %{ __ Clear_Array($cnt$$Register, $base$$Register, $srcA$$Register, $srcL$$Register); %} 9925 ins_pipe(pipe_class_dummy); 9926 %} 9927 9928 // ============================================================================ 9929 // CompactStrings 9930 9931 // String equals 9932 instruct string_equalsL(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 9933 match(Set result (StrEquals (Binary str1 str2) cnt)); 9934 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 9935 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL); 9936 ins_cost(300); 9937 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %} 9938 ins_encode %{ 9939 __ array_equals(false, $str1$$Register, $str2$$Register, 9940 $cnt$$Register, $oddReg$$Register, $evenReg$$Register, 9941 $result$$Register, true /* byte */); 9942 %} 9943 ins_pipe(pipe_class_dummy); 9944 %} 9945 9946 instruct string_equalsU(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 9947 match(Set result (StrEquals (Binary str1 str2) cnt)); 9948 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 9949 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none); 9950 ins_cost(300); 9951 format %{ "String Equals char[] $str1,$str2,$cnt -> $result" %} 9952 ins_encode %{ 9953 __ array_equals(false, $str1$$Register, $str2$$Register, 9954 $cnt$$Register, $oddReg$$Register, $evenReg$$Register, 9955 $result$$Register, false /* byte */); 9956 %} 9957 ins_pipe(pipe_class_dummy); 9958 %} 9959 9960 instruct string_equals_imm(iRegP str1, iRegP str2, uimmI8 cnt, iRegI result, flagsReg cr) %{ 9961 match(Set result (StrEquals (Binary str1 str2) cnt)); 9962 effect(KILL cr); // R0 is killed, too. 9963 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU); 9964 ins_cost(100); 9965 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %} 9966 ins_encode %{ 9967 const int cnt_imm = $cnt$$constant; 9968 if (cnt_imm) { __ z_clc(0, cnt_imm - 1, $str1$$Register, 0, $str2$$Register); } 9969 __ z_lhi($result$$Register, 1); 9970 if (cnt_imm) { 9971 if (VM_Version::has_LoadStoreConditional()) { 9972 __ z_lhi(Z_R0_scratch, 0); 9973 __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual); 9974 } else { 9975 Label Lskip; 9976 __ z_bre(Lskip); 9977 __ clear_reg($result$$Register); 9978 __ bind(Lskip); 9979 } 9980 } 9981 %} 9982 ins_pipe(pipe_class_dummy); 9983 %} 9984 9985 instruct string_equalsC_imm(iRegP str1, iRegP str2, immI8 cnt, iRegI result, flagsReg cr) %{ 9986 match(Set result (StrEquals (Binary str1 str2) cnt)); 9987 effect(KILL cr); // R0 is killed, too. 9988 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none); 9989 ins_cost(100); 9990 format %{ "String Equals $str1,$str2,$cnt -> $result" %} 9991 ins_encode %{ 9992 const int cnt_imm = $cnt$$constant; // positive immI8 (7 bits used) 9993 if (cnt_imm) { __ z_clc(0, (cnt_imm << 1) - 1, $str1$$Register, 0, $str2$$Register); } 9994 __ z_lhi($result$$Register, 1); 9995 if (cnt_imm) { 9996 if (VM_Version::has_LoadStoreConditional()) { 9997 __ z_lhi(Z_R0_scratch, 0); 9998 __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual); 9999 } else { 10000 Label Lskip; 10001 __ z_bre(Lskip); 10002 __ clear_reg($result$$Register); 10003 __ bind(Lskip); 10004 } 10005 } 10006 %} 10007 ins_pipe(pipe_class_dummy); 10008 %} 10009 10010 // Array equals 10011 instruct array_equalsB(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10012 match(Set result (AryEq ary1 ary2)); 10013 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10014 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL); 10015 ins_cost(300); 10016 format %{ "Array Equals $ary1,$ary2 -> $result" %} 10017 ins_encode %{ 10018 __ array_equals(true, $ary1$$Register, $ary2$$Register, 10019 noreg, $oddReg$$Register, $evenReg$$Register, 10020 $result$$Register, true /* byte */); 10021 %} 10022 ins_pipe(pipe_class_dummy); 10023 %} 10024 10025 instruct array_equalsC(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10026 match(Set result (AryEq ary1 ary2)); 10027 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10028 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU); 10029 ins_cost(300); 10030 format %{ "Array Equals $ary1,$ary2 -> $result" %} 10031 ins_encode %{ 10032 __ array_equals(true, $ary1$$Register, $ary2$$Register, 10033 noreg, $oddReg$$Register, $evenReg$$Register, 10034 $result$$Register, false /* byte */); 10035 %} 10036 ins_pipe(pipe_class_dummy); 10037 %} 10038 10039 // String CompareTo 10040 instruct string_compareL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10041 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10042 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10043 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL); 10044 ins_cost(300); 10045 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %} 10046 ins_encode %{ 10047 __ string_compare($str1$$Register, $str2$$Register, 10048 $cnt1$$Register, $cnt2$$Register, 10049 $oddReg$$Register, $evenReg$$Register, 10050 $result$$Register, StrIntrinsicNode::LL); 10051 %} 10052 ins_pipe(pipe_class_dummy); 10053 %} 10054 10055 instruct string_compareU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10056 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10057 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10058 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrCompNode*)n)->encoding() == StrIntrinsicNode::none); 10059 ins_cost(300); 10060 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result" %} 10061 ins_encode %{ 10062 __ string_compare($str1$$Register, $str2$$Register, 10063 $cnt1$$Register, $cnt2$$Register, 10064 $oddReg$$Register, $evenReg$$Register, 10065 $result$$Register, StrIntrinsicNode::UU); 10066 %} 10067 ins_pipe(pipe_class_dummy); 10068 %} 10069 10070 instruct string_compareLU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10071 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10072 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10073 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU); 10074 ins_cost(300); 10075 format %{ "String Compare byte[],char[] $str1,$cnt1,$str2,$cnt2 -> $result" %} 10076 ins_encode %{ 10077 __ string_compare($str1$$Register, $str2$$Register, 10078 $cnt1$$Register, $cnt2$$Register, 10079 $oddReg$$Register, $evenReg$$Register, 10080 $result$$Register, StrIntrinsicNode::LU); 10081 %} 10082 ins_pipe(pipe_class_dummy); 10083 %} 10084 10085 instruct string_compareUL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10086 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10087 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10088 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL); 10089 ins_cost(300); 10090 format %{ "String Compare char[],byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %} 10091 ins_encode %{ 10092 __ string_compare($str2$$Register, $str1$$Register, 10093 $cnt2$$Register, $cnt1$$Register, 10094 $oddReg$$Register, $evenReg$$Register, 10095 $result$$Register, StrIntrinsicNode::UL); 10096 %} 10097 ins_pipe(pipe_class_dummy); 10098 %} 10099 10100 // String IndexOfChar 10101 instruct indexOfChar_U(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10102 match(Set result (StrIndexOfChar (Binary haystack haycnt) ch)); 10103 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too. 10104 ins_cost(200); 10105 format %{ "String IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %} 10106 ins_encode %{ 10107 __ string_indexof_char($result$$Register, 10108 $haystack$$Register, $haycnt$$Register, 10109 $ch$$Register, 0 /* unused, ch is in register */, 10110 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/); 10111 %} 10112 ins_pipe(pipe_class_dummy); 10113 %} 10114 10115 instruct indexOf_imm1_U(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10116 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10117 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too. 10118 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none); 10119 ins_cost(200); 10120 format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %} 10121 ins_encode %{ 10122 immPOper *needleOper = (immPOper *)$needle; 10123 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); 10124 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * 10125 jchar chr; 10126 #ifdef VM_LITTLE_ENDIAN 10127 Unimplemented(); 10128 #else 10129 chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) | 10130 ((jchar)(unsigned char)needle_values->element_value(1).as_byte()); 10131 #endif 10132 __ string_indexof_char($result$$Register, 10133 $haystack$$Register, $haycnt$$Register, 10134 noreg, chr, 10135 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/); 10136 %} 10137 ins_pipe(pipe_class_dummy); 10138 %} 10139 10140 instruct indexOf_imm1_L(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10141 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10142 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too. 10143 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL); 10144 ins_cost(200); 10145 format %{ "String IndexOf L [0..$haycnt]($haystack), [0]($needle) -> $result" %} 10146 ins_encode %{ 10147 immPOper *needleOper = (immPOper *)$needle; 10148 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); 10149 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * 10150 jchar chr = (jchar)needle_values->element_value(0).as_byte(); 10151 __ string_indexof_char($result$$Register, 10152 $haystack$$Register, $haycnt$$Register, 10153 noreg, chr, 10154 $oddReg$$Register, $evenReg$$Register, true /*is_byte*/); 10155 %} 10156 ins_pipe(pipe_class_dummy); 10157 %} 10158 10159 instruct indexOf_imm1_UL(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10160 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10161 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too. 10162 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL); 10163 ins_cost(200); 10164 format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %} 10165 ins_encode %{ 10166 immPOper *needleOper = (immPOper *)$needle; 10167 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); 10168 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * 10169 jchar chr = (jchar)needle_values->element_value(0).as_byte(); 10170 __ string_indexof_char($result$$Register, 10171 $haystack$$Register, $haycnt$$Register, 10172 noreg, chr, 10173 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/); 10174 %} 10175 ins_pipe(pipe_class_dummy); 10176 %} 10177 10178 // String IndexOf 10179 instruct indexOf_imm_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10180 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 10181 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10182 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none); 10183 ins_cost(250); 10184 format %{ "String IndexOf U [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10185 ins_encode %{ 10186 __ string_indexof($result$$Register, 10187 $haystack$$Register, $haycnt$$Register, 10188 $needle$$Register, noreg, $needlecntImm$$constant, 10189 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU); 10190 %} 10191 ins_pipe(pipe_class_dummy); 10192 %} 10193 10194 instruct indexOf_imm_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10195 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 10196 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10197 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL); 10198 ins_cost(250); 10199 format %{ "String IndexOf L [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10200 ins_encode %{ 10201 __ string_indexof($result$$Register, 10202 $haystack$$Register, $haycnt$$Register, 10203 $needle$$Register, noreg, $needlecntImm$$constant, 10204 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL); 10205 %} 10206 ins_pipe(pipe_class_dummy); 10207 %} 10208 10209 instruct indexOf_imm_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10210 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 10211 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10212 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL); 10213 ins_cost(250); 10214 format %{ "String IndexOf UL [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10215 ins_encode %{ 10216 __ string_indexof($result$$Register, 10217 $haystack$$Register, $haycnt$$Register, 10218 $needle$$Register, noreg, $needlecntImm$$constant, 10219 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL); 10220 %} 10221 ins_pipe(pipe_class_dummy); 10222 %} 10223 10224 instruct indexOf_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10225 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10226 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10227 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none); 10228 ins_cost(300); 10229 format %{ "String IndexOf U [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10230 ins_encode %{ 10231 __ string_indexof($result$$Register, 10232 $haystack$$Register, $haycnt$$Register, 10233 $needle$$Register, $needlecnt$$Register, 0, 10234 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU); 10235 %} 10236 ins_pipe(pipe_class_dummy); 10237 %} 10238 10239 instruct indexOf_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10240 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10241 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10242 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL); 10243 ins_cost(300); 10244 format %{ "String IndexOf L [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10245 ins_encode %{ 10246 __ string_indexof($result$$Register, 10247 $haystack$$Register, $haycnt$$Register, 10248 $needle$$Register, $needlecnt$$Register, 0, 10249 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL); 10250 %} 10251 ins_pipe(pipe_class_dummy); 10252 %} 10253 10254 instruct indexOf_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10255 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10256 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10257 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL); 10258 ins_cost(300); 10259 format %{ "String IndexOf UL [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10260 ins_encode %{ 10261 __ string_indexof($result$$Register, 10262 $haystack$$Register, $haycnt$$Register, 10263 $needle$$Register, $needlecnt$$Register, 0, 10264 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL); 10265 %} 10266 ins_pipe(pipe_class_dummy); 10267 %} 10268 10269 // char[] to byte[] compression 10270 instruct string_compress(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, flagsReg cr) %{ 10271 match(Set result (StrCompressedCopy src (Binary dst len))); 10272 effect(TEMP_DEF result, TEMP tmp, KILL cr); // R0, R1 are killed, too. 10273 ins_cost(300); 10274 format %{ "String Compress $src->$dst($len) -> $result" %} 10275 ins_encode %{ 10276 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register, 10277 $tmp$$Register, false); 10278 %} 10279 ins_pipe(pipe_class_dummy); 10280 %} 10281 10282 // byte[] to char[] inflation. trot implementation is shorter, but slower than the unrolled icm(h) loop. 10283 //instruct string_inflate_trot(Universe dummy, iRegP src, revenRegP dst, roddRegI len, iRegI tmp, flagsReg cr) %{ 10284 // match(Set dummy (StrInflatedCopy src (Binary dst len))); 10285 // effect(USE_KILL dst, USE_KILL len, TEMP tmp, KILL cr); // R0, R1 are killed, too. 10286 // predicate(VM_Version::has_ETF2Enhancements()); 10287 // ins_cost(300); 10288 // format %{ "String Inflate (trot) $dst,$src($len)" %} 10289 // ins_encode %{ 10290 // __ string_inflate_trot($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register); 10291 // %} 10292 // ins_pipe(pipe_class_dummy); 10293 //%} 10294 10295 // byte[] to char[] inflation 10296 instruct string_inflate(Universe dummy, iRegP src, iRegP dst, iRegI len, iRegI tmp, flagsReg cr) %{ 10297 match(Set dummy (StrInflatedCopy src (Binary dst len))); 10298 effect(TEMP tmp, KILL cr); // R0, R1 are killed, too. 10299 ins_cost(300); 10300 format %{ "String Inflate $src->$dst($len)" %} 10301 ins_encode %{ 10302 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register); 10303 %} 10304 ins_pipe(pipe_class_dummy); 10305 %} 10306 10307 // byte[] to char[] inflation 10308 instruct string_inflate_const(Universe dummy, iRegP src, iRegP dst, iRegI tmp, immI len, flagsReg cr) %{ 10309 match(Set dummy (StrInflatedCopy src (Binary dst len))); 10310 effect(TEMP tmp, KILL cr); // R0, R1 are killed, too. 10311 ins_cost(300); 10312 format %{ "String Inflate (constLen) $src->$dst($len)" %} 10313 ins_encode %{ 10314 __ string_inflate_const($src$$Register, $dst$$Register, $tmp$$Register, $len$$constant); 10315 %} 10316 ins_pipe(pipe_class_dummy); 10317 %} 10318 10319 // StringCoding.java intrinsics 10320 instruct has_negatives(rarg5RegP ary1, iRegI len, iRegI result, roddRegI oddReg, revenRegI evenReg, iRegI tmp, flagsReg cr) %{ 10321 match(Set result (HasNegatives ary1 len)); 10322 effect(TEMP_DEF result, USE_KILL ary1, TEMP oddReg, TEMP evenReg, TEMP tmp, KILL cr); // R0, R1 are killed, too. 10323 ins_cost(300); 10324 format %{ "has negatives byte[] $ary1($len) -> $result" %} 10325 ins_encode %{ 10326 __ has_negatives($result$$Register, $ary1$$Register, $len$$Register, 10327 $oddReg$$Register, $evenReg$$Register, $tmp$$Register); 10328 %} 10329 ins_pipe(pipe_class_dummy); 10330 %} 10331 10332 // encode char[] to byte[] in ISO_8859_1 10333 instruct encode_iso_array(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, flagsReg cr) %{ 10334 match(Set result (EncodeISOArray src (Binary dst len))); 10335 effect(TEMP_DEF result, TEMP tmp, KILL cr); // R0, R1 are killed, too. 10336 ins_cost(300); 10337 format %{ "Encode array $src->$dst($len) -> $result" %} 10338 ins_encode %{ 10339 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register, 10340 $tmp$$Register, true); 10341 %} 10342 ins_pipe(pipe_class_dummy); 10343 %} 10344 10345 10346 //----------PEEPHOLE RULES----------------------------------------------------- 10347 // These must follow all instruction definitions as they use the names 10348 // defined in the instructions definitions. 10349 // 10350 // peepmatch (root_instr_name [preceeding_instruction]*); 10351 // 10352 // peepconstraint %{ 10353 // (instruction_number.operand_name relational_op instruction_number.operand_name 10354 // [, ...]); 10355 // // instruction numbers are zero-based using left to right order in peepmatch 10356 // 10357 // peepreplace (instr_name([instruction_number.operand_name]*)); 10358 // // provide an instruction_number.operand_name for each operand that appears 10359 // // in the replacement instruction's match rule 10360 // 10361 // ---------VM FLAGS--------------------------------------------------------- 10362 // 10363 // All peephole optimizations can be turned off using -XX:-OptoPeephole 10364 // 10365 // Each peephole rule is given an identifying number starting with zero and 10366 // increasing by one in the order seen by the parser. An individual peephole 10367 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 10368 // on the command-line. 10369 // 10370 // ---------CURRENT LIMITATIONS---------------------------------------------- 10371 // 10372 // Only match adjacent instructions in same basic block 10373 // Only equality constraints 10374 // Only constraints between operands, not (0.dest_reg == EAX_enc) 10375 // Only one replacement instruction 10376 // 10377 // ---------EXAMPLE---------------------------------------------------------- 10378 // 10379 // // pertinent parts of existing instructions in architecture description 10380 // instruct movI(eRegI dst, eRegI src) %{ 10381 // match(Set dst (CopyI src)); 10382 // %} 10383 // 10384 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 10385 // match(Set dst (AddI dst src)); 10386 // effect(KILL cr); 10387 // %} 10388 // 10389 // // Change (inc mov) to lea 10390 // peephole %{ 10391 // // increment preceeded by register-register move 10392 // peepmatch (incI_eReg movI); 10393 // // require that the destination register of the increment 10394 // // match the destination register of the move 10395 // peepconstraint (0.dst == 1.dst); 10396 // // construct a replacement instruction that sets 10397 // // the destination to (move's source register + one) 10398 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src)); 10399 // %} 10400 // 10401 // Implementation no longer uses movX instructions since 10402 // machine-independent system no longer uses CopyX nodes. 10403 // 10404 // peephole %{ 10405 // peepmatch (incI_eReg movI); 10406 // peepconstraint (0.dst == 1.dst); 10407 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src)); 10408 // %} 10409 // 10410 // peephole %{ 10411 // peepmatch (decI_eReg movI); 10412 // peepconstraint (0.dst == 1.dst); 10413 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src)); 10414 // %} 10415 // 10416 // peephole %{ 10417 // peepmatch (addI_eReg_imm movI); 10418 // peepconstraint (0.dst == 1.dst); 10419 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src)); 10420 // %} 10421 // 10422 // peephole %{ 10423 // peepmatch (addP_eReg_imm movP); 10424 // peepconstraint (0.dst == 1.dst); 10425 // peepreplace (leaP_eReg_immI(0.dst 1.src 0.src)); 10426 // %} 10427 10428 10429 // This peephole rule does not work, probably because ADLC can't handle two effects: 10430 // Effect 1 is defining 0.op1 and effect 2 is setting CC 10431 // condense a load from memory and subsequent test for zero 10432 // into a single, more efficient ICM instruction. 10433 // peephole %{ 10434 // peepmatch (compI_iReg_imm0 loadI); 10435 // peepconstraint (1.dst == 0.op1); 10436 // peepreplace (loadtest15_iReg_mem(0.op1 0.op1 1.mem)); 10437 // %} 10438 10439 // // Change load of spilled value to only a spill 10440 // instruct storeI(memory mem, eRegI src) %{ 10441 // match(Set mem (StoreI mem src)); 10442 // %} 10443 // 10444 // instruct loadI(eRegI dst, memory mem) %{ 10445 // match(Set dst (LoadI mem)); 10446 // %} 10447 // 10448 peephole %{ 10449 peepmatch (loadI storeI); 10450 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); 10451 peepreplace (storeI(1.mem 1.mem 1.src)); 10452 %} 10453 10454 peephole %{ 10455 peepmatch (loadL storeL); 10456 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); 10457 peepreplace (storeL(1.mem 1.mem 1.src)); 10458 %} 10459 10460 peephole %{ 10461 peepmatch (loadP storeP); 10462 peepconstraint (1.src == 0.dst, 1.dst == 0.mem); 10463 peepreplace (storeP(1.dst 1.dst 1.src)); 10464 %} 10465 10466 //----------SUPERWORD RULES--------------------------------------------------- 10467 10468 // Expand rules for special cases 10469 10470 instruct expand_storeF(stackSlotF mem, regF src) %{ 10471 // No match rule, false predicate, for expand only. 10472 effect(DEF mem, USE src); 10473 predicate(false); 10474 ins_cost(MEMORY_REF_COST); 10475 // TODO: s390 port size(FIXED_SIZE); 10476 format %{ "STE $src,$mem\t # replicate(float2stack)" %} 10477 opcode(STE_ZOPC, STE_ZOPC); 10478 ins_encode(z_form_rt_mem(src, mem)); 10479 ins_pipe(pipe_class_dummy); 10480 %} 10481 10482 instruct expand_LoadLogical_I2L(iRegL dst, stackSlotF mem) %{ 10483 // No match rule, false predicate, for expand only. 10484 effect(DEF dst, USE mem); 10485 predicate(false); 10486 ins_cost(MEMORY_REF_COST); 10487 // TODO: s390 port size(FIXED_SIZE); 10488 format %{ "LLGF $dst,$mem\t # replicate(stack2reg(unsigned))" %} 10489 opcode(LLGF_ZOPC, LLGF_ZOPC); 10490 ins_encode(z_form_rt_mem(dst, mem)); 10491 ins_pipe(pipe_class_dummy); 10492 %} 10493 10494 // Replicate scalar int to packed int values (8 Bytes) 10495 instruct expand_Repl2I_reg(iRegL dst, iRegL src) %{ 10496 // Dummy match rule, false predicate, for expand only. 10497 match(Set dst (ConvI2L src)); 10498 predicate(false); 10499 ins_cost(DEFAULT_COST); 10500 // TODO: s390 port size(FIXED_SIZE); 10501 format %{ "REPLIC2F $dst,$src\t # replicate(pack2F)" %} 10502 ins_encode %{ 10503 if ($dst$$Register == $src$$Register) { 10504 __ z_sllg(Z_R0_scratch, $src$$Register, 64-32); 10505 __ z_ogr($dst$$Register, Z_R0_scratch); 10506 } else { 10507 __ z_sllg($dst$$Register, $src$$Register, 64-32); 10508 __ z_ogr( $dst$$Register, $src$$Register); 10509 } 10510 %} 10511 ins_pipe(pipe_class_dummy); 10512 %} 10513 10514 // Replication 10515 10516 // Exploit rotate_then_insert, if available 10517 // Replicate scalar byte to packed byte values (8 Bytes). 10518 instruct Repl8B_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{ 10519 match(Set dst (ReplicateB src)); 10520 effect(KILL cr); 10521 predicate((n->as_Vector()->length() == 8)); 10522 format %{ "REPLIC8B $dst,$src\t # pack8B" %} 10523 ins_encode %{ 10524 if ($dst$$Register != $src$$Register) { 10525 __ z_lgr($dst$$Register, $src$$Register); 10526 } 10527 __ rotate_then_insert($dst$$Register, $dst$$Register, 48, 55, 8, false); 10528 __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false); 10529 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false); 10530 %} 10531 ins_pipe(pipe_class_dummy); 10532 %} 10533 10534 // Replicate scalar byte to packed byte values (8 Bytes). 10535 instruct Repl8B_imm(iRegL dst, immB_n0m1 src) %{ 10536 match(Set dst (ReplicateB src)); 10537 predicate(n->as_Vector()->length() == 8); 10538 ins_should_rematerialize(true); 10539 format %{ "REPLIC8B $dst,$src\t # pack8B imm" %} 10540 ins_encode %{ 10541 int64_t Isrc8 = $src$$constant & 0x000000ff; 10542 int64_t Isrc16 = Isrc8 << 8 | Isrc8; 10543 int64_t Isrc32 = Isrc16 << 16 | Isrc16; 10544 assert(Isrc8 != 0x000000ff && Isrc8 != 0, "should be handled by other match rules."); 10545 10546 __ z_llilf($dst$$Register, Isrc32); 10547 __ z_iihf($dst$$Register, Isrc32); 10548 %} 10549 ins_pipe(pipe_class_dummy); 10550 %} 10551 10552 // Replicate scalar byte to packed byte values (8 Bytes). 10553 instruct Repl8B_imm0(iRegL dst, immI_0 src) %{ 10554 match(Set dst (ReplicateB src)); 10555 predicate(n->as_Vector()->length() == 8); 10556 ins_should_rematerialize(true); 10557 format %{ "REPLIC8B $dst,$src\t # pack8B imm0" %} 10558 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %} 10559 ins_pipe(pipe_class_dummy); 10560 %} 10561 10562 // Replicate scalar byte to packed byte values (8 Bytes). 10563 instruct Repl8B_immm1(iRegL dst, immB_minus1 src) %{ 10564 match(Set dst (ReplicateB src)); 10565 predicate(n->as_Vector()->length() == 8); 10566 ins_should_rematerialize(true); 10567 format %{ "REPLIC8B $dst,$src\t # pack8B immm1" %} 10568 ins_encode %{ __ z_lghi($dst$$Register, -1); %} 10569 ins_pipe(pipe_class_dummy); 10570 %} 10571 10572 // Exploit rotate_then_insert, if available 10573 // Replicate scalar short to packed short values (8 Bytes). 10574 instruct Repl4S_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{ 10575 match(Set dst (ReplicateS src)); 10576 effect(KILL cr); 10577 predicate((n->as_Vector()->length() == 4)); 10578 format %{ "REPLIC4S $dst,$src\t # pack4S" %} 10579 ins_encode %{ 10580 if ($dst$$Register != $src$$Register) { 10581 __ z_lgr($dst$$Register, $src$$Register); 10582 } 10583 __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false); 10584 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false); 10585 %} 10586 ins_pipe(pipe_class_dummy); 10587 %} 10588 10589 // Replicate scalar short to packed short values (8 Bytes). 10590 instruct Repl4S_imm(iRegL dst, immS_n0m1 src) %{ 10591 match(Set dst (ReplicateS src)); 10592 predicate(n->as_Vector()->length() == 4); 10593 ins_should_rematerialize(true); 10594 format %{ "REPLIC4S $dst,$src\t # pack4S imm" %} 10595 ins_encode %{ 10596 int64_t Isrc16 = $src$$constant & 0x0000ffff; 10597 int64_t Isrc32 = Isrc16 << 16 | Isrc16; 10598 assert(Isrc16 != 0x0000ffff && Isrc16 != 0, "Repl4S_imm: (src == " INT64_FORMAT 10599 ") should be handled by other match rules.", $src$$constant); 10600 10601 __ z_llilf($dst$$Register, Isrc32); 10602 __ z_iihf($dst$$Register, Isrc32); 10603 %} 10604 ins_pipe(pipe_class_dummy); 10605 %} 10606 10607 // Replicate scalar short to packed short values (8 Bytes). 10608 instruct Repl4S_imm0(iRegL dst, immI_0 src) %{ 10609 match(Set dst (ReplicateS src)); 10610 predicate(n->as_Vector()->length() == 4); 10611 ins_should_rematerialize(true); 10612 format %{ "REPLIC4S $dst,$src\t # pack4S imm0" %} 10613 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %} 10614 ins_pipe(pipe_class_dummy); 10615 %} 10616 10617 // Replicate scalar short to packed short values (8 Bytes). 10618 instruct Repl4S_immm1(iRegL dst, immS_minus1 src) %{ 10619 match(Set dst (ReplicateS src)); 10620 predicate(n->as_Vector()->length() == 4); 10621 ins_should_rematerialize(true); 10622 format %{ "REPLIC4S $dst,$src\t # pack4S immm1" %} 10623 ins_encode %{ __ z_lghi($dst$$Register, -1); %} 10624 ins_pipe(pipe_class_dummy); 10625 %} 10626 10627 // Exploit rotate_then_insert, if available. 10628 // Replicate scalar int to packed int values (8 Bytes). 10629 instruct Repl2I_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{ 10630 match(Set dst (ReplicateI src)); 10631 effect(KILL cr); 10632 predicate((n->as_Vector()->length() == 2)); 10633 format %{ "REPLIC2I $dst,$src\t # pack2I" %} 10634 ins_encode %{ 10635 if ($dst$$Register != $src$$Register) { 10636 __ z_lgr($dst$$Register, $src$$Register); 10637 } 10638 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false); 10639 %} 10640 ins_pipe(pipe_class_dummy); 10641 %} 10642 10643 // Replicate scalar int to packed int values (8 Bytes). 10644 instruct Repl2I_imm(iRegL dst, immI_n0m1 src) %{ 10645 match(Set dst (ReplicateI src)); 10646 predicate(n->as_Vector()->length() == 2); 10647 ins_should_rematerialize(true); 10648 format %{ "REPLIC2I $dst,$src\t # pack2I imm" %} 10649 ins_encode %{ 10650 int64_t Isrc32 = $src$$constant; 10651 assert(Isrc32 != -1 && Isrc32 != 0, "should be handled by other match rules."); 10652 10653 __ z_llilf($dst$$Register, Isrc32); 10654 __ z_iihf($dst$$Register, Isrc32); 10655 %} 10656 ins_pipe(pipe_class_dummy); 10657 %} 10658 10659 // Replicate scalar int to packed int values (8 Bytes). 10660 instruct Repl2I_imm0(iRegL dst, immI_0 src) %{ 10661 match(Set dst (ReplicateI src)); 10662 predicate(n->as_Vector()->length() == 2); 10663 ins_should_rematerialize(true); 10664 format %{ "REPLIC2I $dst,$src\t # pack2I imm0" %} 10665 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %} 10666 ins_pipe(pipe_class_dummy); 10667 %} 10668 10669 // Replicate scalar int to packed int values (8 Bytes). 10670 instruct Repl2I_immm1(iRegL dst, immI_minus1 src) %{ 10671 match(Set dst (ReplicateI src)); 10672 predicate(n->as_Vector()->length() == 2); 10673 ins_should_rematerialize(true); 10674 format %{ "REPLIC2I $dst,$src\t # pack2I immm1" %} 10675 ins_encode %{ __ z_lghi($dst$$Register, -1); %} 10676 ins_pipe(pipe_class_dummy); 10677 %} 10678 10679 // 10680 10681 instruct Repl2F_reg_indirect(iRegL dst, regF src, flagsReg cr) %{ 10682 match(Set dst (ReplicateF src)); 10683 effect(KILL cr); 10684 predicate(!VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2); 10685 format %{ "REPLIC2F $dst,$src\t # pack2F indirect" %} 10686 expand %{ 10687 stackSlotF tmp; 10688 iRegL tmp2; 10689 expand_storeF(tmp, src); 10690 expand_LoadLogical_I2L(tmp2, tmp); 10691 expand_Repl2I_reg(dst, tmp2); 10692 %} 10693 %} 10694 10695 // Replicate scalar float to packed float values in GREG (8 Bytes). 10696 instruct Repl2F_reg_direct(iRegL dst, regF src, flagsReg cr) %{ 10697 match(Set dst (ReplicateF src)); 10698 effect(KILL cr); 10699 predicate(VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2); 10700 format %{ "REPLIC2F $dst,$src\t # pack2F direct" %} 10701 ins_encode %{ 10702 assert(VM_Version::has_FPSupportEnhancements(), "encoder should never be called on old H/W"); 10703 __ z_lgdr($dst$$Register, $src$$FloatRegister); 10704 10705 __ z_srlg(Z_R0_scratch, $dst$$Register, 32); // Floats are left-justified in 64bit reg. 10706 __ z_iilf($dst$$Register, 0); // Save a "result not ready" stall. 10707 __ z_ogr($dst$$Register, Z_R0_scratch); 10708 %} 10709 ins_pipe(pipe_class_dummy); 10710 %} 10711 10712 // Replicate scalar float immediate to packed float values in GREG (8 Bytes). 10713 instruct Repl2F_imm(iRegL dst, immF src) %{ 10714 match(Set dst (ReplicateF src)); 10715 predicate(n->as_Vector()->length() == 2); 10716 ins_should_rematerialize(true); 10717 format %{ "REPLIC2F $dst,$src\t # pack2F imm" %} 10718 ins_encode %{ 10719 union { 10720 int Isrc32; 10721 float Fsrc32; 10722 }; 10723 Fsrc32 = $src$$constant; 10724 __ z_llilf($dst$$Register, Isrc32); 10725 __ z_iihf($dst$$Register, Isrc32); 10726 %} 10727 ins_pipe(pipe_class_dummy); 10728 %} 10729 10730 // Replicate scalar float immediate zeroes to packed float values in GREG (8 Bytes). 10731 // Do this only for 'real' zeroes, especially don't loose sign of negative zeroes. 10732 instruct Repl2F_imm0(iRegL dst, immFp0 src) %{ 10733 match(Set dst (ReplicateF src)); 10734 predicate(n->as_Vector()->length() == 2); 10735 ins_should_rematerialize(true); 10736 format %{ "REPLIC2F $dst,$src\t # pack2F imm0" %} 10737 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %} 10738 ins_pipe(pipe_class_dummy); 10739 %} 10740 10741 // Store 10742 10743 // Store Aligned Packed Byte register to memory (8 Bytes). 10744 instruct storeA8B(memory mem, iRegL src) %{ 10745 match(Set mem (StoreVector mem src)); 10746 predicate(n->as_StoreVector()->memory_size() == 8); 10747 ins_cost(MEMORY_REF_COST); 10748 // TODO: s390 port size(VARIABLE_SIZE); 10749 format %{ "STG $src,$mem\t # ST(packed8B)" %} 10750 opcode(STG_ZOPC, STG_ZOPC); 10751 ins_encode(z_form_rt_mem_opt(src, mem)); 10752 ins_pipe(pipe_class_dummy); 10753 %} 10754 10755 // Load 10756 10757 instruct loadV8(iRegL dst, memory mem) %{ 10758 match(Set dst (LoadVector mem)); 10759 predicate(n->as_LoadVector()->memory_size() == 8); 10760 ins_cost(MEMORY_REF_COST); 10761 // TODO: s390 port size(VARIABLE_SIZE); 10762 format %{ "LG $dst,$mem\t # L(packed8B)" %} 10763 opcode(LG_ZOPC, LG_ZOPC); 10764 ins_encode(z_form_rt_mem_opt(dst, mem)); 10765 ins_pipe(pipe_class_dummy); 10766 %} 10767 10768 //----------POPULATION COUNT RULES-------------------------------------------- 10769 10770 // Byte reverse 10771 10772 instruct bytes_reverse_int(iRegI dst, iRegI src) %{ 10773 match(Set dst (ReverseBytesI src)); 10774 predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported 10775 ins_cost(DEFAULT_COST); 10776 size(4); 10777 format %{ "LRVR $dst,$src\t# byte reverse int" %} 10778 opcode(LRVR_ZOPC); 10779 ins_encode(z_rreform(dst, src)); 10780 ins_pipe(pipe_class_dummy); 10781 %} 10782 10783 instruct bytes_reverse_long(iRegL dst, iRegL src) %{ 10784 match(Set dst (ReverseBytesL src)); 10785 predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported 10786 ins_cost(DEFAULT_COST); 10787 // TODO: s390 port size(FIXED_SIZE); 10788 format %{ "LRVGR $dst,$src\t# byte reverse long" %} 10789 opcode(LRVGR_ZOPC); 10790 ins_encode(z_rreform(dst, src)); 10791 ins_pipe(pipe_class_dummy); 10792 %} 10793 10794 // Leading zeroes 10795 10796 // The instruction FLOGR (Find Leftmost One in Grande (64bit) Register) 10797 // returns the bit position of the leftmost 1 in the 64bit source register. 10798 // As the bits are numbered from left to right (0..63), the returned 10799 // position index is equivalent to the number of leading zeroes. 10800 // If no 1-bit is found (i.e. the regsiter contains zero), the instruction 10801 // returns position 64. That's exactly what we need. 10802 10803 instruct countLeadingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{ 10804 match(Set dst (CountLeadingZerosI src)); 10805 effect(KILL tmp, KILL cr); 10806 ins_cost(3 * DEFAULT_COST); 10807 size(14); 10808 format %{ "SLLG $dst,$src,32\t# no need to always count 32 zeroes first\n\t" 10809 "IILH $dst,0x8000 \t# insert \"stop bit\" to force result 32 for zero src.\n\t" 10810 "FLOGR $dst,$dst" 10811 %} 10812 ins_encode %{ 10813 // Performance experiments indicate that "FLOGR" is using some kind of 10814 // iteration to find the leftmost "1" bit. 10815 // 10816 // The prior implementation zero-extended the 32-bit argument to 64 bit, 10817 // thus forcing "FLOGR" to count 32 bits of which we know they are zero. 10818 // We could gain measurable speedup in micro benchmark: 10819 // 10820 // leading trailing 10821 // z10: int 2.04 1.68 10822 // long 1.00 1.02 10823 // z196: int 0.99 1.23 10824 // long 1.00 1.11 10825 // 10826 // By shifting the argument into the high-word instead of zero-extending it. 10827 // The add'l branch on condition (taken for a zero argument, very infrequent, 10828 // good prediction) is well compensated for by the savings. 10829 // 10830 // We leave the previous implementation in for some time in the future when 10831 // the "FLOGR" instruction may become less iterative. 10832 10833 // Version 2: shows 62%(z9), 204%(z10), -1%(z196) improvement over original 10834 __ z_sllg($dst$$Register, $src$$Register, 32); // No need to always count 32 zeroes first. 10835 __ z_iilh($dst$$Register, 0x8000); // Insert "stop bit" to force result 32 for zero src. 10836 __ z_flogr($dst$$Register, $dst$$Register); 10837 %} 10838 ins_pipe(pipe_class_dummy); 10839 %} 10840 10841 instruct countLeadingZerosL(revenRegI dst, iRegL src, roddRegI tmp, flagsReg cr) %{ 10842 match(Set dst (CountLeadingZerosL src)); 10843 effect(KILL tmp, KILL cr); 10844 ins_cost(DEFAULT_COST); 10845 size(4); 10846 format %{ "FLOGR $dst,$src \t# count leading zeros (long)\n\t" %} 10847 ins_encode %{ __ z_flogr($dst$$Register, $src$$Register); %} 10848 ins_pipe(pipe_class_dummy); 10849 %} 10850 10851 // trailing zeroes 10852 10853 // We transform the trailing zeroes problem to a leading zeroes problem 10854 // such that can use the FLOGR instruction to our advantage. 10855 10856 // With 10857 // tmp1 = src - 1 10858 // we flip all trailing zeroes to ones and the rightmost one to zero. 10859 // All other bits remain unchanged. 10860 // With the complement 10861 // tmp2 = ~src 10862 // we get all ones in the trailing zeroes positions. Thus, 10863 // tmp3 = tmp1 & tmp2 10864 // yields ones in the trailing zeroes positions and zeroes elsewhere. 10865 // Now we can apply FLOGR and get 64-(trailing zeroes). 10866 instruct countTrailingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{ 10867 match(Set dst (CountTrailingZerosI src)); 10868 effect(TEMP_DEF dst, TEMP tmp, KILL cr); 10869 ins_cost(8 * DEFAULT_COST); 10870 // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off. 10871 format %{ "LLGFR $dst,$src \t# clear upper 32 bits (we are dealing with int)\n\t" 10872 "LCGFR $tmp,$src \t# load 2's complement (32->64 bit)\n\t" 10873 "AGHI $dst,-1 \t# tmp1 = src-1\n\t" 10874 "AGHI $tmp,-1 \t# tmp2 = -src-1 = ~src\n\t" 10875 "NGR $dst,$tmp \t# tmp3 = tmp1&tmp2\n\t" 10876 "FLOGR $dst,$dst \t# count trailing zeros (int)\n\t" 10877 "AHI $dst,-64 \t# tmp4 = 64-(trailing zeroes)-64\n\t" 10878 "LCR $dst,$dst \t# res = -tmp4" 10879 %} 10880 ins_encode %{ 10881 Register Rdst = $dst$$Register; 10882 Register Rsrc = $src$$Register; 10883 // Rtmp only needed for for zero-argument shortcut. With kill effect in 10884 // match rule Rsrc = roddReg would be possible, saving one register. 10885 Register Rtmp = $tmp$$Register; 10886 10887 assert_different_registers(Rdst, Rsrc, Rtmp); 10888 10889 // Algorithm: 10890 // - Isolate the least significant (rightmost) set bit using (src & (-src)). 10891 // All other bits in the result are zero. 10892 // - Find the "leftmost one" bit position in the single-bit result from previous step. 10893 // - 63-("leftmost one" bit position) gives the # of trailing zeros. 10894 10895 // Version 2: shows 79%(z9), 68%(z10), 23%(z196) improvement over original. 10896 Label done; 10897 __ load_const_optimized(Rdst, 32); // Prepare for shortcut (zero argument), result will be 32. 10898 __ z_lcgfr(Rtmp, Rsrc); 10899 __ z_bre(done); // Taken very infrequently, good prediction, no BHT entry. 10900 10901 __ z_nr(Rtmp, Rsrc); // (src) & (-src) leaves nothing but least significant bit. 10902 __ z_ahi(Rtmp, -1); // Subtract one to fill all trailing zero positions with ones. 10903 // Use 32bit op to prevent borrow propagation (case Rdst = 0x80000000) 10904 // into upper half of reg. Not relevant with sllg below. 10905 __ z_sllg(Rdst, Rtmp, 32); // Shift interesting contents to upper half of register. 10906 __ z_bre(done); // Shortcut for argument = 1, result will be 0. 10907 // Depends on CC set by ahi above. 10908 // Taken very infrequently, good prediction, no BHT entry. 10909 // Branch delayed to have Rdst set correctly (Rtmp == 0(32bit) 10910 // after SLLG Rdst == 0(64bit)). 10911 __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst. 10912 __ add2reg(Rdst, -32); // 32-pos(leftmost1) is #trailing zeros 10913 __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost. 10914 __ bind(done); 10915 %} 10916 ins_pipe(pipe_class_dummy); 10917 %} 10918 10919 instruct countTrailingZerosL(revenRegI dst, iRegL src, roddRegL tmp, flagsReg cr) %{ 10920 match(Set dst (CountTrailingZerosL src)); 10921 effect(TEMP_DEF dst, KILL tmp, KILL cr); 10922 ins_cost(8 * DEFAULT_COST); 10923 // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off. 10924 format %{ "LCGR $dst,$src \t# preserve src\n\t" 10925 "NGR $dst,$src \t#" 10926 "AGHI $dst,-1 \t# tmp1 = src-1\n\t" 10927 "FLOGR $dst,$dst \t# count trailing zeros (long), kill $tmp\n\t" 10928 "AHI $dst,-64 \t# tmp4 = 64-(trailing zeroes)-64\n\t" 10929 "LCR $dst,$dst \t#" 10930 %} 10931 ins_encode %{ 10932 Register Rdst = $dst$$Register; 10933 Register Rsrc = $src$$Register; 10934 assert_different_registers(Rdst, Rsrc); // Rtmp == Rsrc allowed. 10935 10936 // New version: shows 5%(z9), 2%(z10), 11%(z196) improvement over original. 10937 __ z_lcgr(Rdst, Rsrc); 10938 __ z_ngr(Rdst, Rsrc); 10939 __ add2reg(Rdst, -1); 10940 __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst. 10941 __ add2reg(Rdst, -64); 10942 __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost. 10943 %} 10944 ins_pipe(pipe_class_dummy); 10945 %} 10946 10947 10948 // bit count 10949 10950 instruct popCountI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ 10951 match(Set dst (PopCountI src)); 10952 effect(TEMP_DEF dst, TEMP tmp, KILL cr); 10953 predicate(UsePopCountInstruction && VM_Version::has_PopCount()); 10954 ins_cost(DEFAULT_COST); 10955 size(24); 10956 format %{ "POPCNT $dst,$src\t# pop count int" %} 10957 ins_encode %{ 10958 Register Rdst = $dst$$Register; 10959 Register Rsrc = $src$$Register; 10960 Register Rtmp = $tmp$$Register; 10961 10962 // Prefer compile-time assertion over run-time SIGILL. 10963 assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI"); 10964 assert_different_registers(Rdst, Rtmp); 10965 10966 // Version 2: shows 10%(z196) improvement over original. 10967 __ z_popcnt(Rdst, Rsrc); 10968 __ z_srlg(Rtmp, Rdst, 16); // calc byte4+byte6 and byte5+byte7 10969 __ z_alr(Rdst, Rtmp); // into byte6 and byte7 10970 __ z_srlg(Rtmp, Rdst, 8); // calc (byte4+byte6) + (byte5+byte7) 10971 __ z_alr(Rdst, Rtmp); // into byte7 10972 __ z_llgcr(Rdst, Rdst); // zero-extend sum 10973 %} 10974 ins_pipe(pipe_class_dummy); 10975 %} 10976 10977 instruct popCountL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{ 10978 match(Set dst (PopCountL src)); 10979 effect(TEMP_DEF dst, TEMP tmp, KILL cr); 10980 predicate(UsePopCountInstruction && VM_Version::has_PopCount()); 10981 ins_cost(DEFAULT_COST); 10982 // TODO: s390 port size(FIXED_SIZE); 10983 format %{ "POPCNT $dst,$src\t# pop count long" %} 10984 ins_encode %{ 10985 Register Rdst = $dst$$Register; 10986 Register Rsrc = $src$$Register; 10987 Register Rtmp = $tmp$$Register; 10988 10989 // Prefer compile-time assertion over run-time SIGILL. 10990 assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI"); 10991 assert_different_registers(Rdst, Rtmp); 10992 10993 // Original version. Using LA instead of algr seems to be a really bad idea (-35%). 10994 __ z_popcnt(Rdst, Rsrc); 10995 __ z_ahhlr(Rdst, Rdst, Rdst); 10996 __ z_sllg(Rtmp, Rdst, 16); 10997 __ z_algr(Rdst, Rtmp); 10998 __ z_sllg(Rtmp, Rdst, 8); 10999 __ z_algr(Rdst, Rtmp); 11000 __ z_srlg(Rdst, Rdst, 56); 11001 %} 11002 ins_pipe(pipe_class_dummy); 11003 %} 11004 11005 //----------SMARTSPILL RULES--------------------------------------------------- 11006 // These must follow all instruction definitions as they use the names 11007 // defined in the instructions definitions. 11008 11009 // ============================================================================ 11010 // TYPE PROFILING RULES 11011