448 return;
449 }
450
451 assert(r != tmp, " need a different temporary register !");
452 load_const_optimized(tmp, mask);
453 z_ngr(r, tmp);
454 }
455
456 // Calculate the 1's complement.
457 // Note: The condition code is neither preserved nor correctly set by this code!!!
458 // Note: (wide == false) does not protect the high order half of the target register
459 // from alteration. It only serves as optimization hint for 32-bit results.
460 void MacroAssembler::not_(Register r1, Register r2, bool wide) {
461
462 if ((r2 == noreg) || (r2 == r1)) { // Calc 1's complement in place.
463 z_xilf(r1, -1);
464 if (wide) {
465 z_xihf(r1, -1);
466 }
467 } else { // Distinct src and dst registers.
468 if (VM_Version::has_DistinctOpnds()) {
469 load_const_optimized(r1, -1);
470 z_xgrk(r1, r2, r1);
471 } else {
472 if (wide) {
473 z_lgr(r1, r2);
474 z_xilf(r1, -1);
475 z_xihf(r1, -1);
476 } else {
477 z_lr(r1, r2);
478 z_xilf(r1, -1);
479 }
480 }
481 }
482 }
483
484 unsigned long MacroAssembler::create_mask(int lBitPos, int rBitPos) {
485 assert(lBitPos >= 0, "zero is leftmost bit position");
486 assert(rBitPos <= 63, "63 is rightmost bit position");
487 assert(lBitPos <= rBitPos, "inverted selection interval");
488 return (lBitPos == 0 ? (unsigned long)(-1L) : ((1UL<<(63-lBitPos+1))-1)) & (~((1UL<<(63-rBitPos))-1));
489 }
490
491 // Helper function for the "Rotate_then_<logicalOP>" emitters.
492 // Rotate src, then mask register contents such that only bits in range survive.
493 // For oneBits == false, all bits not in range are set to 0. Useful for deleting all bits outside range.
494 // For oneBits == true, all bits not in range are set to 1. Useful for preserving all bits outside range.
495 // The caller must ensure that the selected range only contains bits with defined value.
496 void MacroAssembler::rotate_then_mask(Register dst, Register src, int lBitPos, int rBitPos,
497 int nRotate, bool src32bit, bool dst32bit, bool oneBits) {
498 assert(!(dst32bit && lBitPos < 32), "selection interval out of range for int destination");
499 bool sll4rll = (nRotate >= 0) && (nRotate <= (63-rBitPos)); // Substitute SLL(G) for RLL(G).
500 bool srl4rll = (nRotate < 0) && (-nRotate <= lBitPos); // Substitute SRL(G) for RLL(G).
1141 assert(addr != NULL, "should not happen");
1142 BLOCK_COMMENT("load_absolute_address:");
1143 if (addr == NULL) {
1144 z_larl(d, pc()); // Dummy emit for size calc.
1145 return;
1146 }
1147
1148 if (RelAddr::is_in_range_of_RelAddr32(addr, pc())) {
1149 z_larl(d, addr);
1150 return;
1151 }
1152
1153 load_const_optimized(d, (long)addr);
1154 }
1155
1156 // Load a 64bit constant.
1157 // Patchable code sequence, but not atomically patchable.
1158 // Make sure to keep code size constant -> no value-dependent optimizations.
1159 // Do not kill condition code.
1160 void MacroAssembler::load_const(Register t, long x) {
1161 Assembler::z_iihf(t, (int)(x >> 32));
1162 Assembler::z_iilf(t, (int)(x & 0xffffffff));
1163 }
1164
1165 // Load a 32bit constant into a 64bit register, sign-extend or zero-extend.
1166 // Patchable code sequence, but not atomically patchable.
1167 // Make sure to keep code size constant -> no value-dependent optimizations.
1168 // Do not kill condition code.
1169 void MacroAssembler::load_const_32to64(Register t, int64_t x, bool sign_extend) {
1170 if (sign_extend) { Assembler::z_lgfi(t, x); }
1171 else { Assembler::z_llilf(t, x); }
1172 }
1173
1174 // Load narrow oop constant, no decompression.
1175 void MacroAssembler::load_narrow_oop(Register t, narrowOop a) {
1176 assert(UseCompressedOops, "must be on to call this method");
1177 load_const_32to64(t, a, false /*sign_extend*/);
1178 }
1179
1180 // Load narrow klass constant, compression required.
1181 void MacroAssembler::load_narrow_klass(Register t, Klass* k) {
1182 assert(UseCompressedClassPointers, "must be on to call this method");
1239
1240 // Detection of compare_immediate_narrow sequence.
1241 // The detection is valid only for code sequences generated by compare_immediate_narrow_oop.
1242 bool MacroAssembler::is_compare_immediate_narrow_oop(address pos) {
1243 return is_compare_immediate32(pos);
1244 }
1245
1246 // Detection of compare_immediate_narrow sequence.
1247 // The detection is valid only for code sequences generated by compare_immediate_narrow_klass.
1248 bool MacroAssembler::is_compare_immediate_narrow_klass(address pos) {
1249 return is_compare_immediate32(pos);
1250 }
1251
1252 //-----------------------------------
1253 // patch the load_constant
1254 //-----------------------------------
1255
1256 // CPU-version dependend patching of load_const.
1257 void MacroAssembler::patch_const(address a, long x) {
1258 assert(is_load_const(a), "not a load of a constant");
1259 set_imm32((address)a, (int) ((x >> 32) & 0xffffffff));
1260 set_imm32((address)(a + 6), (int)(x & 0xffffffff));
1261 }
1262
1263 // Patching the value of CPU version dependent load_const_32to64 sequence.
1264 // The passed ptr MUST be in compressed format!
1265 int MacroAssembler::patch_load_const_32to64(address pos, int64_t np) {
1266 assert(is_load_const_32to64(pos), "not a load of a narrow ptr (oop or klass)");
1267
1268 set_imm32(pos, np);
1269 return 6;
1270 }
1271
1272 // Patching the value of CPU version dependent compare_immediate_narrow sequence.
1273 // The passed ptr MUST be in compressed format!
1274 int MacroAssembler::patch_compare_immediate_32(address pos, int64_t np) {
1275 assert(is_compare_immediate32(pos), "not a compressed ptr compare");
1276
1277 set_imm32(pos, np);
1278 return 6;
1279 }
1280
1444 // Load constant x into register t with a fast instrcution sequence
1445 // depending on the bits in x. Preserves CC under all circumstances.
1446 int MacroAssembler::load_const_optimized_rtn_len(Register t, long x, bool emit) {
1447 if (x == 0) {
1448 int len;
1449 if (emit) {
1450 len = clear_reg(t, true, false);
1451 } else {
1452 len = 4;
1453 }
1454 return len;
1455 }
1456
1457 if (Immediate::is_simm16(x)) {
1458 if (emit) { z_lghi(t, x); }
1459 return 4;
1460 }
1461
1462 // 64 bit value: | part1 | part2 | part3 | part4 |
1463 // At least one part is not zero!
1464 int part1 = ((x >> 32) & 0xffff0000) >> 16;
1465 int part2 = (x >> 32) & 0x0000ffff;
1466 int part3 = (x & 0xffff0000) >> 16;
1467 int part4 = (x & 0x0000ffff);
1468
1469 // Lower word only (unsigned).
1470 if ((part1 == 0) && (part2 == 0)) {
1471 if (part3 == 0) {
1472 if (emit) z_llill(t, part4);
1473 return 4;
1474 }
1475 if (part4 == 0) {
1476 if (emit) z_llilh(t, part3);
1477 return 4;
1478 }
1479 if (emit) z_llilf(t, (int)(x & 0xffffffff));
1480 return 6;
1481 }
1482
1483 // Upper word only.
1484 if ((part3 == 0) && (part4 == 0)) {
1485 if (part1 == 0) {
1486 if (emit) z_llihl(t, part2);
1487 return 4;
1488 }
1489 if (part2 == 0) {
1490 if (emit) z_llihh(t, part1);
1491 return 4;
1492 }
1493 if (emit) z_llihf(t, (int)(x >> 32));
1494 return 6;
1495 }
1496
1497 // Lower word only (signed).
1498 if ((part1 == 0x0000ffff) && (part2 == 0x0000ffff) && ((part3 & 0x00008000) != 0)) {
1499 if (emit) z_lgfi(t, (int)(x & 0xffffffff));
1500 return 6;
1501 }
1502
1503 int len = 0;
1504
1505 if ((part1 == 0) || (part2 == 0)) {
1506 if (part1 == 0) {
1507 if (emit) z_llihl(t, part2);
1508 len += 4;
1509 } else {
1510 if (emit) z_llihh(t, part1);
1511 len += 4;
1512 }
1513 } else {
1514 if (emit) z_llihf(t, (int)(x >> 32));
1515 len += 6;
1516 }
1517
1518 if ((part3 == 0) || (part4 == 0)) {
1519 if (part3 == 0) {
1520 if (emit) z_iill(t, part4);
1521 len += 4;
1522 } else {
1523 if (emit) z_iilh(t, part3);
1524 len += 4;
1525 }
1526 } else {
1527 if (emit) z_iilf(t, (int)(x & 0xffffffff));
1528 len += 6;
1529 }
1530 return len;
1531 }
1532
1533 //=====================================================================
1534 //=== H I G H E R L E V E L B R A N C H E M I T T E R S ===
1535 //=====================================================================
1536
1537 // Note: In the worst case, one of the scratch registers is destroyed!!!
1538 void MacroAssembler::compare32_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& lbl) {
1539 // Right operand is constant.
1540 if (x2.is_constant()) {
1541 jlong value = x2.as_constant();
1542 compare_and_branch_optimized(r1, value, cond, lbl, /*len64=*/false, /*has_sign=*/true);
1543 return;
1544 }
1545
1546 // Right operand is in register.
1547 compare_and_branch_optimized(r1, x2.as_register(), cond, lbl, /*len64=*/false, /*has_sign=*/true);
|
448 return;
449 }
450
451 assert(r != tmp, " need a different temporary register !");
452 load_const_optimized(tmp, mask);
453 z_ngr(r, tmp);
454 }
455
456 // Calculate the 1's complement.
457 // Note: The condition code is neither preserved nor correctly set by this code!!!
458 // Note: (wide == false) does not protect the high order half of the target register
459 // from alteration. It only serves as optimization hint for 32-bit results.
460 void MacroAssembler::not_(Register r1, Register r2, bool wide) {
461
462 if ((r2 == noreg) || (r2 == r1)) { // Calc 1's complement in place.
463 z_xilf(r1, -1);
464 if (wide) {
465 z_xihf(r1, -1);
466 }
467 } else { // Distinct src and dst registers.
468 load_const_optimized(r1, -1);
469 z_xgr(r1, r2);
470 }
471 }
472
473 unsigned long MacroAssembler::create_mask(int lBitPos, int rBitPos) {
474 assert(lBitPos >= 0, "zero is leftmost bit position");
475 assert(rBitPos <= 63, "63 is rightmost bit position");
476 assert(lBitPos <= rBitPos, "inverted selection interval");
477 return (lBitPos == 0 ? (unsigned long)(-1L) : ((1UL<<(63-lBitPos+1))-1)) & (~((1UL<<(63-rBitPos))-1));
478 }
479
480 // Helper function for the "Rotate_then_<logicalOP>" emitters.
481 // Rotate src, then mask register contents such that only bits in range survive.
482 // For oneBits == false, all bits not in range are set to 0. Useful for deleting all bits outside range.
483 // For oneBits == true, all bits not in range are set to 1. Useful for preserving all bits outside range.
484 // The caller must ensure that the selected range only contains bits with defined value.
485 void MacroAssembler::rotate_then_mask(Register dst, Register src, int lBitPos, int rBitPos,
486 int nRotate, bool src32bit, bool dst32bit, bool oneBits) {
487 assert(!(dst32bit && lBitPos < 32), "selection interval out of range for int destination");
488 bool sll4rll = (nRotate >= 0) && (nRotate <= (63-rBitPos)); // Substitute SLL(G) for RLL(G).
489 bool srl4rll = (nRotate < 0) && (-nRotate <= lBitPos); // Substitute SRL(G) for RLL(G).
1130 assert(addr != NULL, "should not happen");
1131 BLOCK_COMMENT("load_absolute_address:");
1132 if (addr == NULL) {
1133 z_larl(d, pc()); // Dummy emit for size calc.
1134 return;
1135 }
1136
1137 if (RelAddr::is_in_range_of_RelAddr32(addr, pc())) {
1138 z_larl(d, addr);
1139 return;
1140 }
1141
1142 load_const_optimized(d, (long)addr);
1143 }
1144
1145 // Load a 64bit constant.
1146 // Patchable code sequence, but not atomically patchable.
1147 // Make sure to keep code size constant -> no value-dependent optimizations.
1148 // Do not kill condition code.
1149 void MacroAssembler::load_const(Register t, long x) {
1150 // Note: Right shift is only cleanly defined for unsigned types
1151 // or for signed types with nonnegative values.
1152 Assembler::z_iihf(t, (long)((unsigned long)x >> 32));
1153 Assembler::z_iilf(t, (long)((unsigned long)x & 0xffffffffUL));
1154 }
1155
1156 // Load a 32bit constant into a 64bit register, sign-extend or zero-extend.
1157 // Patchable code sequence, but not atomically patchable.
1158 // Make sure to keep code size constant -> no value-dependent optimizations.
1159 // Do not kill condition code.
1160 void MacroAssembler::load_const_32to64(Register t, int64_t x, bool sign_extend) {
1161 if (sign_extend) { Assembler::z_lgfi(t, x); }
1162 else { Assembler::z_llilf(t, x); }
1163 }
1164
1165 // Load narrow oop constant, no decompression.
1166 void MacroAssembler::load_narrow_oop(Register t, narrowOop a) {
1167 assert(UseCompressedOops, "must be on to call this method");
1168 load_const_32to64(t, a, false /*sign_extend*/);
1169 }
1170
1171 // Load narrow klass constant, compression required.
1172 void MacroAssembler::load_narrow_klass(Register t, Klass* k) {
1173 assert(UseCompressedClassPointers, "must be on to call this method");
1230
1231 // Detection of compare_immediate_narrow sequence.
1232 // The detection is valid only for code sequences generated by compare_immediate_narrow_oop.
1233 bool MacroAssembler::is_compare_immediate_narrow_oop(address pos) {
1234 return is_compare_immediate32(pos);
1235 }
1236
1237 // Detection of compare_immediate_narrow sequence.
1238 // The detection is valid only for code sequences generated by compare_immediate_narrow_klass.
1239 bool MacroAssembler::is_compare_immediate_narrow_klass(address pos) {
1240 return is_compare_immediate32(pos);
1241 }
1242
1243 //-----------------------------------
1244 // patch the load_constant
1245 //-----------------------------------
1246
1247 // CPU-version dependend patching of load_const.
1248 void MacroAssembler::patch_const(address a, long x) {
1249 assert(is_load_const(a), "not a load of a constant");
1250 // Note: Right shift is only cleanly defined for unsigned types
1251 // or for signed types with nonnegative values.
1252 set_imm32((address)a, (long)((unsigned long)x >> 32));
1253 set_imm32((address)(a + 6), (long)((unsigned long)x & 0xffffffffUL));
1254 }
1255
1256 // Patching the value of CPU version dependent load_const_32to64 sequence.
1257 // The passed ptr MUST be in compressed format!
1258 int MacroAssembler::patch_load_const_32to64(address pos, int64_t np) {
1259 assert(is_load_const_32to64(pos), "not a load of a narrow ptr (oop or klass)");
1260
1261 set_imm32(pos, np);
1262 return 6;
1263 }
1264
1265 // Patching the value of CPU version dependent compare_immediate_narrow sequence.
1266 // The passed ptr MUST be in compressed format!
1267 int MacroAssembler::patch_compare_immediate_32(address pos, int64_t np) {
1268 assert(is_compare_immediate32(pos), "not a compressed ptr compare");
1269
1270 set_imm32(pos, np);
1271 return 6;
1272 }
1273
1437 // Load constant x into register t with a fast instrcution sequence
1438 // depending on the bits in x. Preserves CC under all circumstances.
1439 int MacroAssembler::load_const_optimized_rtn_len(Register t, long x, bool emit) {
1440 if (x == 0) {
1441 int len;
1442 if (emit) {
1443 len = clear_reg(t, true, false);
1444 } else {
1445 len = 4;
1446 }
1447 return len;
1448 }
1449
1450 if (Immediate::is_simm16(x)) {
1451 if (emit) { z_lghi(t, x); }
1452 return 4;
1453 }
1454
1455 // 64 bit value: | part1 | part2 | part3 | part4 |
1456 // At least one part is not zero!
1457 // Note: Right shift is only cleanly defined for unsigned types
1458 // or for signed types with nonnegative values.
1459 int part1 = (int)((unsigned long)x >> 48) & 0x0000ffff;
1460 int part2 = (int)((unsigned long)x >> 32) & 0x0000ffff;
1461 int part3 = (int)((unsigned long)x >> 16) & 0x0000ffff;
1462 int part4 = (int)x & 0x0000ffff;
1463 int part12 = (int)((unsigned long)x >> 32);
1464 int part34 = (int)x;
1465
1466 // Lower word only (unsigned).
1467 if (part12 == 0) {
1468 if (part3 == 0) {
1469 if (emit) z_llill(t, part4);
1470 return 4;
1471 }
1472 if (part4 == 0) {
1473 if (emit) z_llilh(t, part3);
1474 return 4;
1475 }
1476 if (emit) z_llilf(t, part34);
1477 return 6;
1478 }
1479
1480 // Upper word only.
1481 if (part34 == 0) {
1482 if (part1 == 0) {
1483 if (emit) z_llihl(t, part2);
1484 return 4;
1485 }
1486 if (part2 == 0) {
1487 if (emit) z_llihh(t, part1);
1488 return 4;
1489 }
1490 if (emit) z_llihf(t, part12);
1491 return 6;
1492 }
1493
1494 // Lower word only (signed).
1495 if ((part1 == 0x0000ffff) && (part2 == 0x0000ffff) && ((part3 & 0x00008000) != 0)) {
1496 if (emit) z_lgfi(t, part34);
1497 return 6;
1498 }
1499
1500 int len = 0;
1501
1502 if ((part1 == 0) || (part2 == 0)) {
1503 if (part1 == 0) {
1504 if (emit) z_llihl(t, part2);
1505 len += 4;
1506 } else {
1507 if (emit) z_llihh(t, part1);
1508 len += 4;
1509 }
1510 } else {
1511 if (emit) z_llihf(t, part12);
1512 len += 6;
1513 }
1514
1515 if ((part3 == 0) || (part4 == 0)) {
1516 if (part3 == 0) {
1517 if (emit) z_iill(t, part4);
1518 len += 4;
1519 } else {
1520 if (emit) z_iilh(t, part3);
1521 len += 4;
1522 }
1523 } else {
1524 if (emit) z_iilf(t, part34);
1525 len += 6;
1526 }
1527 return len;
1528 }
1529
1530 //=====================================================================
1531 //=== H I G H E R L E V E L B R A N C H E M I T T E R S ===
1532 //=====================================================================
1533
1534 // Note: In the worst case, one of the scratch registers is destroyed!!!
1535 void MacroAssembler::compare32_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& lbl) {
1536 // Right operand is constant.
1537 if (x2.is_constant()) {
1538 jlong value = x2.as_constant();
1539 compare_and_branch_optimized(r1, value, cond, lbl, /*len64=*/false, /*has_sign=*/true);
1540 return;
1541 }
1542
1543 // Right operand is in register.
1544 compare_and_branch_optimized(r1, x2.as_register(), cond, lbl, /*len64=*/false, /*has_sign=*/true);
|