src/hotspot/share/opto/block.cpp

rev 54542 : 8213084: Rework and enhance Print[Opto]Assembly output
Reviewed-by:

*** 1,7 ****
  /*
!  * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.
--- 1,7 ----
  /*
!  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.
*** 265,275 ****
    return false;
  }
  
  #ifndef PRODUCT
  void Block::dump_bidx(const Block* orig, outputStream* st) const {
!   if (_pre_order) st->print("B%d",_pre_order);
    else st->print("N%d", head()->_idx);
  
    if (Verbose && orig != this) {
      // Dump the original block's idx
      st->print(" (");
--- 265,275 ----
    return false;
  }
  
  #ifndef PRODUCT
  void Block::dump_bidx(const Block* orig, outputStream* st) const {
!   if (_pre_order) st->print("B%d", _pre_order);
    else st->print("N%d", head()->_idx);
  
    if (Verbose && orig != this) {
      // Dump the original block's idx
      st->print(" (");
*** 289,320 ****
      st->print(" ");
    }
  }
  
  void Block::dump_head(const PhaseCFG* cfg, outputStream* st) const {
!   // Print the basic block
    dump_bidx(this, st);
!   st->print(": #\t");
  
!   // Print the incoming CFG edges and the outgoing CFG edges
    for( uint i=0; i<_num_succs; i++ ) {
      non_connector_successor(i)->dump_bidx(_succs[i], st);
      st->print(" ");
    }
!   st->print("<- ");
    if( head()->is_block_start() ) {
      for (uint i=1; i<num_preds(); i++) {
        Node *s = pred(i);
        if (cfg != NULL) {
          Block *p = cfg->get_block_for_node(s);
          p->dump_pred(cfg, p, st);
        } else {
!         while (!s->is_block_start())
            s = s->in(0);
          st->print("N%d ", s->_idx );
        }
      }
    } else {
      st->print("BLOCK HEAD IS JUNK  ");
    }
  
    // Print loop, if any
--- 289,326 ----
      st->print(" ");
    }
  }
  
  void Block::dump_head(const PhaseCFG* cfg, outputStream* st) const {
!   // Print the basic block.
    dump_bidx(this, st);
!   st->print(": ");
  
!   // Print the outgoing CFG edges.
!   st->print("#\tout( ");
    for( uint i=0; i<_num_succs; i++ ) {
      non_connector_successor(i)->dump_bidx(_succs[i], st);
      st->print(" ");
    }
! 
!   // Print the incoming CFG edges.
!   st->print(") <- ");
    if( head()->is_block_start() ) {
+     st->print("in( ");
      for (uint i=1; i<num_preds(); i++) {
        Node *s = pred(i);
        if (cfg != NULL) {
          Block *p = cfg->get_block_for_node(s);
          p->dump_pred(cfg, p, st);
        } else {
!         while (!s->is_block_start()) {
            s = s->in(0);
+         }
          st->print("N%d ", s->_idx );
        }
      }
+     st->print(") ");
    } else {
      st->print("BLOCK HEAD IS JUNK ");
    }
  
    // Print loop, if any
*** 325,340 ****
      LoopNode *loop = bh->as_Loop();
      const Block *bx = cfg->get_block_for_node(loop->in(LoopNode::LoopBackControl));
      while (bx->is_connector()) {
        bx = cfg->get_block_for_node(bx->pred(1));
      }
!     st->print("\tLoop: B%d-B%d ", bhead->_pre_order, bx->_pre_order);
      // Dump any loop-specific bits, especially for CountedLoops.
      loop->dump_spec(st);
    } else if (has_loop_alignment()) {
!     st->print(" top-of-loop");
    }
    st->print(" Freq: %g",_freq);
    if( Verbose || WizardMode ) {
      st->print(" IDom: %d/#%d", _idom ? _idom->_pre_order : 0, _dom_depth);
      st->print(" RegPressure: %d",_reg_pressure);
      st->print(" IHRP Index: %d",_ihrp_index);
--- 331,349 ----
      LoopNode *loop = bh->as_Loop();
      const Block *bx = cfg->get_block_for_node(loop->in(LoopNode::LoopBackControl));
      while (bx->is_connector()) {
        bx = cfg->get_block_for_node(bx->pred(1));
      }
!     st->print("Loop( B%d-B%d ", bhead->_pre_order, bx->_pre_order);
      // Dump any loop-specific bits, especially for CountedLoops.
      loop->dump_spec(st);
+     st->print(")");
    } else if (has_loop_alignment()) {
!     st->print("top-of-loop");
    }
+ 
+   // Print frequency and other optimization-relevant information
    st->print(" Freq: %g",_freq);
    if( Verbose || WizardMode ) {
      st->print(" IDom: %d/#%d", _idom ? _idom->_pre_order : 0, _dom_depth);
      st->print(" RegPressure: %d",_reg_pressure);
      st->print(" IHRP Index: %d",_ihrp_index);