rev 56859 : 8233787: Break cycle in vm_version* includes
Reviewed-by:

   1 /*
   2  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2019, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_VM_VERSION_AARCH64_HPP
  27 #define CPU_AARCH64_VM_VERSION_AARCH64_HPP
  28 
  29 #include "runtime/globals_extension.hpp"

  30 #include "utilities/sizes.hpp"
  31 
  32 class VM_Version : public Abstract_VM_Version {
  33   friend class JVMCIVMStructs;
  34 
  35 protected:
  36   static int _cpu;
  37   static int _model;
  38   static int _model2;
  39   static int _variant;
  40   static int _revision;
  41   static int _stepping;
  42   static bool _dcpop;
  43   struct PsrInfo {
  44     uint32_t dczid_el0;
  45     uint32_t ctr_el0;
  46   };
  47   static PsrInfo _psr_info;
  48   static void get_processor_features();
  49 
  50 public:
  51   // Initialization
  52   static void initialize();
  53 
  54   // Asserts
  55   static void assert_is_initialized() {
  56   }
  57 
  58   static bool expensive_load(int ld_size, int scale) {
  59     if (cpu_family() == CPU_ARM) {
  60       // Half-word load with index shift by 1 (aka scale is 2) has
  61       // extra cycle latency, e.g. ldrsh w0, [x1,w2,sxtw #1].
  62       if (ld_size == 2 && scale == 2) {
  63         return true;
  64       }
  65     }
  66     return false;
  67   }
  68 
  69   // The CPU implementer codes can be found in
  70   // ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile
  71   // https://developer.arm.com/docs/ddi0487/latest
  72   enum Family {
  73     CPU_AMPERE    = 0xC0,
  74     CPU_ARM       = 'A',
  75     CPU_BROADCOM  = 'B',
  76     CPU_CAVIUM    = 'C',
  77     CPU_DEC       = 'D',
  78     CPU_HISILICON = 'H',
  79     CPU_INFINEON  = 'I',
  80     CPU_MOTOROLA  = 'M',
  81     CPU_NVIDIA    = 'N',
  82     CPU_AMCC      = 'P',
  83     CPU_QUALCOM   = 'Q',
  84     CPU_MARVELL   = 'V',
  85     CPU_INTEL     = 'i',
  86   };
  87 
  88   enum Feature_Flag {
  89     CPU_FP           = (1<<0),
  90     CPU_ASIMD        = (1<<1),
  91     CPU_EVTSTRM      = (1<<2),
  92     CPU_AES          = (1<<3),
  93     CPU_PMULL        = (1<<4),
  94     CPU_SHA1         = (1<<5),
  95     CPU_SHA2         = (1<<6),
  96     CPU_CRC32        = (1<<7),
  97     CPU_LSE          = (1<<8),
  98     CPU_STXR_PREFETCH= (1 << 29),
  99     CPU_A53MAC       = (1 << 30),
 100     CPU_DMB_ATOMICS  = (1 << 31),
 101   };
 102 
 103   static int cpu_family()                     { return _cpu; }
 104   static int cpu_model()                      { return _model; }
 105   static int cpu_model2()                     { return _model2; }
 106   static int cpu_variant()                    { return _variant; }
 107   static int cpu_revision()                   { return _revision; }
 108   static bool supports_dcpop()                { return _dcpop; }
 109   static ByteSize dczid_el0_offset() { return byte_offset_of(PsrInfo, dczid_el0); }
 110   static ByteSize ctr_el0_offset()   { return byte_offset_of(PsrInfo, ctr_el0); }
 111   static bool is_zva_enabled() {
 112     // Check the DZP bit (bit 4) of dczid_el0 is zero
 113     // and block size (bit 0~3) is not zero.
 114     return ((_psr_info.dczid_el0 & 0x10) == 0 &&
 115             (_psr_info.dczid_el0 & 0xf) != 0);
 116   }
 117   static int zva_length() {
 118     assert(is_zva_enabled(), "ZVA not available");
 119     return 4 << (_psr_info.dczid_el0 & 0xf);
 120   }
 121   static int icache_line_size() {
 122     return (1 << (_psr_info.ctr_el0 & 0x0f)) * 4;
 123   }
 124   static int dcache_line_size() {
 125     return (1 << ((_psr_info.ctr_el0 >> 16) & 0x0f)) * 4;
 126   }
 127   static bool supports_fast_class_init_checks() { return true; }
 128 };
 129 
 130 #endif // CPU_AARCH64_VM_VERSION_AARCH64_HPP
--- EOF ---