1 /*
2 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_SPARC_VM_VERSION_SPARC_HPP
26 #define CPU_SPARC_VM_VERSION_SPARC_HPP
27
28 #include "runtime/globals_extension.hpp"
29
30 class VM_Version: public Abstract_VM_Version {
31 friend class VMStructs;
32 friend class JVMCIVMStructs;
33
34 protected:
35 enum {
36 ISA_V9,
37 ISA_POPC,
38 ISA_VIS1,
39 ISA_VIS2,
40 ISA_BLK_INIT,
41 ISA_FMAF,
42 ISA_VIS3,
43 ISA_HPC,
44 ISA_IMA,
45 ISA_AES,
46 ISA_DES,
47 ISA_KASUMI,
48 ISA_CAMELLIA,
49 ISA_MD5,
50 ISA_SHA1,
51 ISA_SHA256,
52 ISA_SHA512,
53 ISA_MPMUL,
54 ISA_MONT,
55 ISA_PAUSE,
56 ISA_CBCOND,
57 ISA_CRC32C,
58
59 ISA_FJATHPLUS,
60 ISA_VIS3B,
61 ISA_ADI,
62 ISA_SPARC5,
63 ISA_MWAIT,
64 ISA_XMPMUL,
65 ISA_XMONT,
66 ISA_PAUSE_NSEC,
67 ISA_VAMASK,
68
69 ISA_SPARC6,
70 ISA_DICTUNP,
71 ISA_FPCMPSHL,
72 ISA_RLE,
73 ISA_SHA3,
74 ISA_FJATHPLUS2,
75 ISA_VIS3C,
76 ISA_SPARC5B,
77 ISA_MME,
78
79 // Synthesised properties:
80
81 CPU_FAST_IDIV,
82 CPU_FAST_RDPC,
83 CPU_FAST_BIS,
84 CPU_FAST_LD,
85 CPU_FAST_CMOVE,
86 CPU_FAST_IND_BR,
87 CPU_BLK_ZEROING
88 };
89
90 private:
91 enum { ISA_last_feature = ISA_MME,
92 CPU_last_feature = CPU_BLK_ZEROING };
93
94 enum {
95 ISA_unknown_msk = 0,
96
97 ISA_v9_msk = UINT64_C(1) << ISA_V9,
98
99 ISA_popc_msk = UINT64_C(1) << ISA_POPC,
100 ISA_vis1_msk = UINT64_C(1) << ISA_VIS1,
101 ISA_vis2_msk = UINT64_C(1) << ISA_VIS2,
102 ISA_blk_init_msk = UINT64_C(1) << ISA_BLK_INIT,
103 ISA_fmaf_msk = UINT64_C(1) << ISA_FMAF,
104 ISA_vis3_msk = UINT64_C(1) << ISA_VIS3,
105 ISA_hpc_msk = UINT64_C(1) << ISA_HPC,
106 ISA_ima_msk = UINT64_C(1) << ISA_IMA,
107 ISA_aes_msk = UINT64_C(1) << ISA_AES,
108 ISA_des_msk = UINT64_C(1) << ISA_DES,
109 ISA_kasumi_msk = UINT64_C(1) << ISA_KASUMI,
110 ISA_camellia_msk = UINT64_C(1) << ISA_CAMELLIA,
111 ISA_md5_msk = UINT64_C(1) << ISA_MD5,
112 ISA_sha1_msk = UINT64_C(1) << ISA_SHA1,
113 ISA_sha256_msk = UINT64_C(1) << ISA_SHA256,
114 ISA_sha512_msk = UINT64_C(1) << ISA_SHA512,
115 ISA_mpmul_msk = UINT64_C(1) << ISA_MPMUL,
116 ISA_mont_msk = UINT64_C(1) << ISA_MONT,
117 ISA_pause_msk = UINT64_C(1) << ISA_PAUSE,
118 ISA_cbcond_msk = UINT64_C(1) << ISA_CBCOND,
119 ISA_crc32c_msk = UINT64_C(1) << ISA_CRC32C,
120
121 ISA_fjathplus_msk = UINT64_C(1) << ISA_FJATHPLUS,
122 ISA_vis3b_msk = UINT64_C(1) << ISA_VIS3B,
123 ISA_adi_msk = UINT64_C(1) << ISA_ADI,
124 ISA_sparc5_msk = UINT64_C(1) << ISA_SPARC5,
125 ISA_mwait_msk = UINT64_C(1) << ISA_MWAIT,
126 ISA_xmpmul_msk = UINT64_C(1) << ISA_XMPMUL,
127 ISA_xmont_msk = UINT64_C(1) << ISA_XMONT,
128 ISA_pause_nsec_msk = UINT64_C(1) << ISA_PAUSE_NSEC,
129 ISA_vamask_msk = UINT64_C(1) << ISA_VAMASK,
130
131 ISA_sparc6_msk = UINT64_C(1) << ISA_SPARC6,
132 ISA_dictunp_msk = UINT64_C(1) << ISA_DICTUNP,
133 ISA_fpcmpshl_msk = UINT64_C(1) << ISA_FPCMPSHL,
134 ISA_rle_msk = UINT64_C(1) << ISA_RLE,
135 ISA_sha3_msk = UINT64_C(1) << ISA_SHA3,
136 ISA_fjathplus2_msk = UINT64_C(1) << ISA_FJATHPLUS2,
137 ISA_vis3c_msk = UINT64_C(1) << ISA_VIS3C,
138 ISA_sparc5b_msk = UINT64_C(1) << ISA_SPARC5B,
139 ISA_mme_msk = UINT64_C(1) << ISA_MME,
140
141 CPU_fast_idiv_msk = UINT64_C(1) << CPU_FAST_IDIV,
142 CPU_fast_rdpc_msk = UINT64_C(1) << CPU_FAST_RDPC,
143 CPU_fast_bis_msk = UINT64_C(1) << CPU_FAST_BIS,
144 CPU_fast_ld_msk = UINT64_C(1) << CPU_FAST_LD,
145 CPU_fast_cmove_msk = UINT64_C(1) << CPU_FAST_CMOVE,
146 CPU_fast_ind_br_msk = UINT64_C(1) << CPU_FAST_IND_BR,
147 CPU_blk_zeroing_msk = UINT64_C(1) << CPU_BLK_ZEROING,
148
149 last_feature_msk = CPU_blk_zeroing_msk,
150 full_feature_msk = (last_feature_msk << 1) - 1
151 };
152
153 /* The following, previously supported, SPARC implementations are no longer
154 * supported.
155 *
156 * UltraSPARC I/II:
157 * SPARC-V9, VIS
158 * UltraSPARC III/+: (Cheetah/+)
159 * SPARC-V9, VIS
160 * UltraSPARC IV: (Jaguar)
161 * SPARC-V9, VIS
162 * UltraSPARC IV+: (Panther)
163 * SPARC-V9, VIS, POPC
164 *
165 * The currently supported SPARC implementations are listed below (including
166 * generic V9 support).
167 *
168 * UltraSPARC T1: (Niagara)
169 * SPARC-V9, VIS, ASI_BIS (Crypto/hash in SPU)
170 * UltraSPARC T2: (Niagara-2)
171 * SPARC-V9, VIS, ASI_BIS, POPC (Crypto/hash in SPU)
172 * UltraSPARC T2+: (Victoria Falls, etc.)
173 * SPARC-V9, VIS, VIS2, ASI_BIS, POPC (Crypto/hash in SPU)
174 *
175 * UltraSPARC T3: (Rainbow Falls/C2)
176 * SPARC-V9, VIS, VIS2, ASI_BIS, POPC (Crypto/hash in SPU)
177 *
178 * Oracle SPARC T4/T5/M5: (Core C3)
179 * SPARC-V9, VIS, VIS2, VIS3, ASI_BIS, HPC, POPC, FMAF, IMA, PAUSE, CBCOND,
180 * AES, DES, Kasumi, Camellia, MD5, SHA1, SHA256, SHA512, CRC32C, MONT, MPMUL
181 *
182 * Oracle SPARC M7: (Core C4)
183 * SPARC-V9, VIS, VIS2, VIS3, ASI_BIS, HPC, POPC, FMAF, IMA, PAUSE, CBCOND,
184 * AES, DES, Camellia, MD5, SHA1, SHA256, SHA512, CRC32C, MONT, MPMUL, VIS3b,
185 * ADI, SPARC5, MWAIT, XMPMUL, XMONT, PAUSE_NSEC, VAMASK
186 *
187 * Oracle SPARC M8: (Core C5)
188 * SPARC-V9, VIS, VIS2, VIS3, ASI_BIS, HPC, POPC, FMAF, IMA, PAUSE, CBCOND,
189 * AES, DES, Camellia, MD5, SHA1, SHA256, SHA512, CRC32C, MONT, MPMUL, VIS3b,
190 * ADI, SPARC5, MWAIT, XMPMUL, XMONT, PAUSE_NSEC, VAMASK, SPARC6, FPCMPSHL,
191 * DICTUNP, RLE, SHA3, MME
192 *
193 * NOTE: Oracle Number support ignored.
194 */
195 enum {
196 niagara1_msk = ISA_v9_msk | ISA_vis1_msk | ISA_blk_init_msk,
197 niagara2_msk = niagara1_msk | ISA_popc_msk,
198
199 core_C2_msk = niagara2_msk | ISA_vis2_msk,
200
201 core_C3_msk = core_C2_msk | ISA_fmaf_msk | ISA_vis3_msk | ISA_hpc_msk |
202 ISA_ima_msk | ISA_aes_msk | ISA_des_msk | ISA_kasumi_msk |
203 ISA_camellia_msk | ISA_md5_msk | ISA_sha1_msk | ISA_sha256_msk |
204 ISA_sha512_msk | ISA_mpmul_msk | ISA_mont_msk | ISA_pause_msk |
205 ISA_cbcond_msk | ISA_crc32c_msk,
206
207 core_C4_msk = core_C3_msk - ISA_kasumi_msk |
208 ISA_vis3b_msk | ISA_adi_msk | ISA_sparc5_msk | ISA_mwait_msk |
209 ISA_xmpmul_msk | ISA_xmont_msk | ISA_pause_nsec_msk | ISA_vamask_msk,
210
211 core_C5_msk = core_C4_msk | ISA_sparc6_msk | ISA_dictunp_msk |
212 ISA_fpcmpshl_msk | ISA_rle_msk | ISA_sha3_msk | ISA_mme_msk,
213
214 ultra_sparc_t1_msk = niagara1_msk,
215 ultra_sparc_t2_msk = niagara2_msk,
216 ultra_sparc_t3_msk = core_C2_msk,
217 ultra_sparc_m5_msk = core_C3_msk, // NOTE: First out-of-order pipeline.
218 ultra_sparc_m7_msk = core_C4_msk,
219 ultra_sparc_m8_msk = core_C5_msk
220 };
221
222 static uint _L2_data_cache_line_size;
223 static uint L2_data_cache_line_size() { return _L2_data_cache_line_size; }
224
225 static void determine_features();
226 static void platform_features();
227 static void print_features();
228
229 public:
230 enum {
231 // Adopt a conservative behaviour (modelling single-insn-fetch-n-issue) for
232 // Niagara (and SPARC64). While there are at least two entries/slots in the
233 // instruction fetch buffer on any Niagara core (and as many as eight on a
234 // SPARC64), the performance improvement from keeping hot branch targets on
235 // optimally aligned addresses is such a small one (if any) that we choose
236 // not to use the extra code space required.
237
238 insn_fetch_alignment = 4 // Byte alignment in L1 insn. cache.
239 };
240
241 static void initialize();
242
243 static void init_before_ergo() { determine_features(); }
244
245 // Instruction feature support:
246
247 static bool has_v9() { return (_features & ISA_v9_msk) != 0; }
248 static bool has_popc() { return (_features & ISA_popc_msk) != 0; }
249 static bool has_vis1() { return (_features & ISA_vis1_msk) != 0; }
250 static bool has_vis2() { return (_features & ISA_vis2_msk) != 0; }
251 static bool has_blk_init() { return (_features & ISA_blk_init_msk) != 0; }
252 static bool has_fmaf() { return (_features & ISA_fmaf_msk) != 0; }
253 static bool has_vis3() { return (_features & ISA_vis3_msk) != 0; }
254 static bool has_hpc() { return (_features & ISA_hpc_msk) != 0; }
255 static bool has_ima() { return (_features & ISA_ima_msk) != 0; }
256 static bool has_aes() { return (_features & ISA_aes_msk) != 0; }
257 static bool has_des() { return (_features & ISA_des_msk) != 0; }
258 static bool has_kasumi() { return (_features & ISA_kasumi_msk) != 0; }
259 static bool has_camellia() { return (_features & ISA_camellia_msk) != 0; }
260 static bool has_md5() { return (_features & ISA_md5_msk) != 0; }
261 static bool has_sha1() { return (_features & ISA_sha1_msk) != 0; }
262 static bool has_sha256() { return (_features & ISA_sha256_msk) != 0; }
263 static bool has_sha512() { return (_features & ISA_sha512_msk) != 0; }
264 static bool has_mpmul() { return (_features & ISA_mpmul_msk) != 0; }
265 static bool has_mont() { return (_features & ISA_mont_msk) != 0; }
266 static bool has_pause() { return (_features & ISA_pause_msk) != 0; }
267 static bool has_cbcond() { return (_features & ISA_cbcond_msk) != 0; }
268 static bool has_crc32c() { return (_features & ISA_crc32c_msk) != 0; }
269
270 static bool has_athena_plus() { return (_features & ISA_fjathplus_msk) != 0; }
271 static bool has_vis3b() { return (_features & ISA_vis3b_msk) != 0; }
272 static bool has_adi() { return (_features & ISA_adi_msk) != 0; }
273 static bool has_sparc5() { return (_features & ISA_sparc5_msk) != 0; }
274 static bool has_mwait() { return (_features & ISA_mwait_msk) != 0; }
275 static bool has_xmpmul() { return (_features & ISA_xmpmul_msk) != 0; }
276 static bool has_xmont() { return (_features & ISA_xmont_msk) != 0; }
277 static bool has_pause_nsec() { return (_features & ISA_pause_nsec_msk) != 0; }
278 static bool has_vamask() { return (_features & ISA_vamask_msk) != 0; }
279
280 static bool has_sparc6() { return (_features & ISA_sparc6_msk) != 0; }
281 static bool has_dictunp() { return (_features & ISA_dictunp_msk) != 0; }
282 static bool has_fpcmpshl() { return (_features & ISA_fpcmpshl_msk) != 0; }
283 static bool has_rle() { return (_features & ISA_rle_msk) != 0; }
284 static bool has_sha3() { return (_features & ISA_sha3_msk) != 0; }
285 static bool has_athena_plus2() { return (_features & ISA_fjathplus2_msk) != 0; }
286 static bool has_vis3c() { return (_features & ISA_vis3c_msk) != 0; }
287 static bool has_sparc5b() { return (_features & ISA_sparc5b_msk) != 0; }
288 static bool has_mme() { return (_features & ISA_mme_msk) != 0; }
289
290 static bool has_fast_idiv() { return (_features & CPU_fast_idiv_msk) != 0; }
291 static bool has_fast_rdpc() { return (_features & CPU_fast_rdpc_msk) != 0; }
292 static bool has_fast_bis() { return (_features & CPU_fast_bis_msk) != 0; }
293 static bool has_fast_ld() { return (_features & CPU_fast_ld_msk) != 0; }
294 static bool has_fast_cmove() { return (_features & CPU_fast_cmove_msk) != 0; }
295
296 // If indirect and direct branching is equally fast.
297 static bool has_fast_ind_br() { return (_features & CPU_fast_ind_br_msk) != 0; }
298 // If SPARC BIS to the beginning of cache line always zeros it.
299 static bool has_blk_zeroing() { return (_features & CPU_blk_zeroing_msk) != 0; }
300
301 static bool supports_compare_and_exchange() { return true; }
302
303 // FIXME: To be removed.
304 static bool is_post_niagara() {
305 return (_features & niagara2_msk) == niagara2_msk;
306 }
307
308 // Default prefetch block size on SPARC.
309 static uint prefetch_data_size() { return L2_data_cache_line_size(); }
310
311 private:
312 // Prefetch policy and characteristics:
313 //
314 // These support routines are used in order to isolate any CPU/core specific
315 // logic from the actual flag/option processing. They should reflect the HW
316 // characteristics for the associated options on the current platform.
317 //
318 // The three Prefetch* options below (assigned -1 in the configuration) are
319 // treated according to (given the accepted range [-1..<maxint>]):
320 // -1: Determine a proper HW-specific value for the current HW.
321 // 0: Off
322 // >0: Command-line supplied value to use.
323 //
324 // FIXME: The documentation string in the configuration is wrong, saying that
325 // -1 is also interpreted as off.
326 //
327 static intx prefetch_copy_interval_in_bytes() {
328 intx bytes = PrefetchCopyIntervalInBytes;
329 return bytes < 0 ? 512 : bytes;
330 }
331 static intx prefetch_scan_interval_in_bytes() {
332 intx bytes = PrefetchScanIntervalInBytes;
333 return bytes < 0 ? 512 : bytes;
334 }
335 static intx prefetch_fields_ahead() {
336 intx count = PrefetchFieldsAhead;
337 return count < 0 ? 0 : count;
338 }
339
340 // AllocatePrefetchDistance is treated under the same interpretation as the
341 // Prefetch* options above (i.e., -1, 0, >0).
342 static intx allocate_prefetch_distance() {
343 intx count = AllocatePrefetchDistance;
344 return count < 0 ? 512 : count;
345 }
346
347 // AllocatePrefetchStyle is guaranteed to be in range [0..3] defined by the
348 // configuration.
349 static intx allocate_prefetch_style() {
350 intx distance = allocate_prefetch_distance();
351 // Return 0 (off/none) if AllocatePrefetchDistance was not defined.
352 return distance > 0 ? AllocatePrefetchStyle : 0;
353 }
354
355 public:
356 // Assembler testing
357 static void allow_all();
358 static void revert();
359
360 // Override the Abstract_VM_Version implementation.
361 //
362 // FIXME: Removed broken test on sun4v (always false when invoked prior to the
363 // proper capability setup), thus always returning 2. Still need to fix
364 // this properly in order to enable complete page size support.
365 static uint page_size_count() { return 2; }
366
367 // Override default denominator for ParallelGCThreads.
368 //
369 // FIXME: Simply checking the processor family is insufficient.
370 static uint parallel_worker_threads_denominator() {
371 return is_post_niagara() ? 16 : 8;
372 }
373 };
374
375 #endif // CPU_SPARC_VM_VERSION_SPARC_HPP