1 /*
2 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_VERSION_X86_HPP
26 #define CPU_X86_VM_VERSION_X86_HPP
27
28 #include "memory/universe.hpp"
29 #include "runtime/globals_extension.hpp"
30
31 class VM_Version : public Abstract_VM_Version {
32 friend class VMStructs;
33 friend class JVMCIVMStructs;
34
35 public:
36 // cpuid result register layouts. These are all unions of a uint32_t
37 // (in case anyone wants access to the register as a whole) and a bitfield.
38
39 union StdCpuid1Eax {
40 uint32_t value;
41 struct {
42 uint32_t stepping : 4,
43 model : 4,
44 family : 4,
45 proc_type : 2,
46 : 2,
47 ext_model : 4,
48 ext_family : 8,
49 : 4;
50 } bits;
51 };
52
53 union StdCpuid1Ebx { // example, unused
54 uint32_t value;
55 struct {
56 uint32_t brand_id : 8,
57 clflush_size : 8,
58 threads_per_cpu : 8,
59 apic_id : 8;
60 } bits;
61 };
62
63 union StdCpuid1Ecx {
64 uint32_t value;
65 struct {
66 uint32_t sse3 : 1,
67 clmul : 1,
68 : 1,
69 monitor : 1,
70 : 1,
71 vmx : 1,
72 : 1,
73 est : 1,
74 : 1,
75 ssse3 : 1,
76 cid : 1,
77 : 1,
78 fma : 1,
79 cmpxchg16: 1,
80 : 4,
81 dca : 1,
82 sse4_1 : 1,
83 sse4_2 : 1,
84 : 2,
85 popcnt : 1,
86 : 1,
87 aes : 1,
88 : 1,
89 osxsave : 1,
90 avx : 1,
91 : 3;
92 } bits;
93 };
94
95 union StdCpuid1Edx {
96 uint32_t value;
97 struct {
98 uint32_t : 4,
99 tsc : 1,
100 : 3,
101 cmpxchg8 : 1,
102 : 6,
103 cmov : 1,
104 : 3,
105 clflush : 1,
106 : 3,
107 mmx : 1,
108 fxsr : 1,
109 sse : 1,
110 sse2 : 1,
111 : 1,
112 ht : 1,
113 : 3;
114 } bits;
115 };
116
117 union DcpCpuid4Eax {
118 uint32_t value;
119 struct {
120 uint32_t cache_type : 5,
121 : 21,
122 cores_per_cpu : 6;
123 } bits;
124 };
125
126 union DcpCpuid4Ebx {
127 uint32_t value;
128 struct {
129 uint32_t L1_line_size : 12,
130 partitions : 10,
131 associativity : 10;
132 } bits;
133 };
134
135 union TplCpuidBEbx {
136 uint32_t value;
137 struct {
138 uint32_t logical_cpus : 16,
139 : 16;
140 } bits;
141 };
142
143 union ExtCpuid1Ecx {
144 uint32_t value;
145 struct {
146 uint32_t LahfSahf : 1,
147 CmpLegacy : 1,
148 : 3,
149 lzcnt_intel : 1,
150 lzcnt : 1,
151 sse4a : 1,
152 misalignsse : 1,
153 prefetchw : 1,
154 : 22;
155 } bits;
156 };
157
158 union ExtCpuid1Edx {
159 uint32_t value;
160 struct {
161 uint32_t : 22,
162 mmx_amd : 1,
163 mmx : 1,
164 fxsr : 1,
165 : 4,
166 long_mode : 1,
167 tdnow2 : 1,
168 tdnow : 1;
169 } bits;
170 };
171
172 union ExtCpuid5Ex {
173 uint32_t value;
174 struct {
175 uint32_t L1_line_size : 8,
176 L1_tag_lines : 8,
177 L1_assoc : 8,
178 L1_size : 8;
179 } bits;
180 };
181
182 union ExtCpuid7Edx {
183 uint32_t value;
184 struct {
185 uint32_t : 8,
186 tsc_invariance : 1,
187 : 23;
188 } bits;
189 };
190
191 union ExtCpuid8Ecx {
192 uint32_t value;
193 struct {
194 uint32_t cores_per_cpu : 8,
195 : 24;
196 } bits;
197 };
198
199 union SefCpuid7Eax {
200 uint32_t value;
201 };
202
203 union SefCpuid7Ebx {
204 uint32_t value;
205 struct {
206 uint32_t fsgsbase : 1,
207 : 2,
208 bmi1 : 1,
209 : 1,
210 avx2 : 1,
211 : 2,
212 bmi2 : 1,
213 erms : 1,
214 : 1,
215 rtm : 1,
216 : 4,
217 avx512f : 1,
218 avx512dq : 1,
219 : 1,
220 adx : 1,
221 : 3,
222 clflushopt : 1,
223 clwb : 1,
224 : 1,
225 avx512pf : 1,
226 avx512er : 1,
227 avx512cd : 1,
228 sha : 1,
229 avx512bw : 1,
230 avx512vl : 1;
231 } bits;
232 };
233
234 union SefCpuid7Ecx {
235 uint32_t value;
236 struct {
237 uint32_t prefetchwt1 : 1,
238 avx512_vbmi : 1,
239 umip : 1,
240 pku : 1,
241 ospke : 1,
242 : 1,
243 avx512_vbmi2 : 1,
244 : 1,
245 gfni : 1,
246 vaes : 1,
247 vpclmulqdq : 1,
248 avx512_vnni : 1,
249 avx512_bitalg : 1,
250 : 1,
251 avx512_vpopcntdq : 1,
252 : 17;
253 } bits;
254 };
255
256 union SefCpuid7Edx {
257 uint32_t value;
258 struct {
259 uint32_t : 2,
260 avx512_4vnniw : 1,
261 avx512_4fmaps : 1,
262 : 28;
263 } bits;
264 };
265
266 union ExtCpuid1EEbx {
267 uint32_t value;
268 struct {
269 uint32_t : 8,
270 threads_per_core : 8,
271 : 16;
272 } bits;
273 };
274
275 union XemXcr0Eax {
276 uint32_t value;
277 struct {
278 uint32_t x87 : 1,
279 sse : 1,
280 ymm : 1,
281 bndregs : 1,
282 bndcsr : 1,
283 opmask : 1,
284 zmm512 : 1,
285 zmm32 : 1,
286 : 24;
287 } bits;
288 };
289
290 protected:
291 static int _cpu;
292 static int _model;
293 static int _stepping;
294
295 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV
296 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
297
298 enum Feature_Flag {
299 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX)
300 CPU_CMOV = (1 << 1),
301 CPU_FXSR = (1 << 2),
302 CPU_HT = (1 << 3),
303 CPU_MMX = (1 << 4),
304 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions
305 // may not necessarily support other 3dnow instructions
306 CPU_SSE = (1 << 6),
307 CPU_SSE2 = (1 << 7),
308 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX)
309 CPU_SSSE3 = (1 << 9),
310 CPU_SSE4A = (1 << 10),
311 CPU_SSE4_1 = (1 << 11),
312 CPU_SSE4_2 = (1 << 12),
313 CPU_POPCNT = (1 << 13),
314 CPU_LZCNT = (1 << 14),
315 CPU_TSC = (1 << 15),
316 CPU_TSCINV = (1 << 16),
317 CPU_AVX = (1 << 17),
318 CPU_AVX2 = (1 << 18),
319 CPU_AES = (1 << 19),
320 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions
321 CPU_CLMUL = (1 << 21), // carryless multiply for CRC
322 CPU_BMI1 = (1 << 22),
323 CPU_BMI2 = (1 << 23),
324 CPU_RTM = (1 << 24), // Restricted Transactional Memory instructions
325 CPU_ADX = (1 << 25),
326 CPU_AVX512F = (1 << 26), // AVX 512bit foundation instructions
327 CPU_AVX512DQ = (1 << 27),
328 CPU_AVX512PF = (1 << 28),
329 CPU_AVX512ER = (1 << 29),
330 CPU_AVX512CD = (1 << 30)
331 // Keeping sign bit 31 unassigned.
332 };
333
334 #define CPU_AVX512BW ((uint64_t)UCONST64(0x100000000)) // enums are limited to 31 bit
335 #define CPU_AVX512VL ((uint64_t)UCONST64(0x200000000)) // EVEX instructions with smaller vector length
336 #define CPU_SHA ((uint64_t)UCONST64(0x400000000)) // SHA instructions
337 #define CPU_FMA ((uint64_t)UCONST64(0x800000000)) // FMA instructions
338 #define CPU_VZEROUPPER ((uint64_t)UCONST64(0x1000000000)) // Vzeroupper instruction
339 #define CPU_AVX512_VPOPCNTDQ ((uint64_t)UCONST64(0x2000000000)) // Vector popcount
340 #define CPU_VPCLMULQDQ ((uint64_t)UCONST64(0x4000000000)) //Vector carryless multiplication
341 #define CPU_VAES ((uint64_t)UCONST64(0x8000000000)) // Vector AES instructions
342 #define CPU_VNNI ((uint64_t)UCONST64(0x10000000000)) // Vector Neural Network Instructions
343
344 #define CPU_FLUSH ((uint64_t)UCONST64(0x20000000000)) // flush instruction
345 #define CPU_FLUSHOPT ((uint64_t)UCONST64(0x40000000000)) // flushopt instruction
346 #define CPU_CLWB ((uint64_t)UCONST64(0x80000000000)) // clwb instruction
347
348 enum Extended_Family {
349 // AMD
350 CPU_FAMILY_AMD_11H = 0x11,
351 // ZX
352 CPU_FAMILY_ZX_CORE_F6 = 6,
353 CPU_FAMILY_ZX_CORE_F7 = 7,
354 // Intel
355 CPU_FAMILY_INTEL_CORE = 6,
356 CPU_MODEL_NEHALEM = 0x1e,
357 CPU_MODEL_NEHALEM_EP = 0x1a,
358 CPU_MODEL_NEHALEM_EX = 0x2e,
359 CPU_MODEL_WESTMERE = 0x25,
360 CPU_MODEL_WESTMERE_EP = 0x2c,
361 CPU_MODEL_WESTMERE_EX = 0x2f,
362 CPU_MODEL_SANDYBRIDGE = 0x2a,
363 CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
364 CPU_MODEL_IVYBRIDGE_EP = 0x3a,
365 CPU_MODEL_HASWELL_E3 = 0x3c,
366 CPU_MODEL_HASWELL_E7 = 0x3f,
367 CPU_MODEL_BROADWELL = 0x3d,
368 CPU_MODEL_SKYLAKE = 0x55
369 };
370
371 // cpuid information block. All info derived from executing cpuid with
372 // various function numbers is stored here. Intel and AMD info is
373 // merged in this block: accessor methods disentangle it.
374 //
375 // The info block is laid out in subblocks of 4 dwords corresponding to
376 // eax, ebx, ecx and edx, whether or not they contain anything useful.
377 struct CpuidInfo {
378 // cpuid function 0
379 uint32_t std_max_function;
380 uint32_t std_vendor_name_0;
381 uint32_t std_vendor_name_1;
382 uint32_t std_vendor_name_2;
383
384 // cpuid function 1
385 StdCpuid1Eax std_cpuid1_eax;
386 StdCpuid1Ebx std_cpuid1_ebx;
387 StdCpuid1Ecx std_cpuid1_ecx;
388 StdCpuid1Edx std_cpuid1_edx;
389
390 // cpuid function 4 (deterministic cache parameters)
391 DcpCpuid4Eax dcp_cpuid4_eax;
392 DcpCpuid4Ebx dcp_cpuid4_ebx;
393 uint32_t dcp_cpuid4_ecx; // unused currently
394 uint32_t dcp_cpuid4_edx; // unused currently
395
396 // cpuid function 7 (structured extended features)
397 SefCpuid7Eax sef_cpuid7_eax;
398 SefCpuid7Ebx sef_cpuid7_ebx;
399 SefCpuid7Ecx sef_cpuid7_ecx;
400 SefCpuid7Edx sef_cpuid7_edx;
401
402 // cpuid function 0xB (processor topology)
403 // ecx = 0
404 uint32_t tpl_cpuidB0_eax;
405 TplCpuidBEbx tpl_cpuidB0_ebx;
406 uint32_t tpl_cpuidB0_ecx; // unused currently
407 uint32_t tpl_cpuidB0_edx; // unused currently
408
409 // ecx = 1
410 uint32_t tpl_cpuidB1_eax;
411 TplCpuidBEbx tpl_cpuidB1_ebx;
412 uint32_t tpl_cpuidB1_ecx; // unused currently
413 uint32_t tpl_cpuidB1_edx; // unused currently
414
415 // ecx = 2
416 uint32_t tpl_cpuidB2_eax;
417 TplCpuidBEbx tpl_cpuidB2_ebx;
418 uint32_t tpl_cpuidB2_ecx; // unused currently
419 uint32_t tpl_cpuidB2_edx; // unused currently
420
421 // cpuid function 0x80000000 // example, unused
422 uint32_t ext_max_function;
423 uint32_t ext_vendor_name_0;
424 uint32_t ext_vendor_name_1;
425 uint32_t ext_vendor_name_2;
426
427 // cpuid function 0x80000001
428 uint32_t ext_cpuid1_eax; // reserved
429 uint32_t ext_cpuid1_ebx; // reserved
430 ExtCpuid1Ecx ext_cpuid1_ecx;
431 ExtCpuid1Edx ext_cpuid1_edx;
432
433 // cpuid functions 0x80000002 thru 0x80000004: example, unused
434 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
435 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
436 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
437
438 // cpuid function 0x80000005 // AMD L1, Intel reserved
439 uint32_t ext_cpuid5_eax; // unused currently
440 uint32_t ext_cpuid5_ebx; // reserved
441 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD)
442 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD)
443
444 // cpuid function 0x80000007
445 uint32_t ext_cpuid7_eax; // reserved
446 uint32_t ext_cpuid7_ebx; // reserved
447 uint32_t ext_cpuid7_ecx; // reserved
448 ExtCpuid7Edx ext_cpuid7_edx; // tscinv
449
450 // cpuid function 0x80000008
451 uint32_t ext_cpuid8_eax; // unused currently
452 uint32_t ext_cpuid8_ebx; // reserved
453 ExtCpuid8Ecx ext_cpuid8_ecx;
454 uint32_t ext_cpuid8_edx; // reserved
455
456 // cpuid function 0x8000001E // AMD 17h
457 uint32_t ext_cpuid1E_eax;
458 ExtCpuid1EEbx ext_cpuid1E_ebx; // threads per core (AMD17h)
459 uint32_t ext_cpuid1E_ecx;
460 uint32_t ext_cpuid1E_edx; // unused currently
461
462 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register)
463 XemXcr0Eax xem_xcr0_eax;
464 uint32_t xem_xcr0_edx; // reserved
465
466 // Space to save ymm registers after signal handle
467 int ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15
468
469 // Space to save zmm registers after signal handle
470 int zmm_save[16*4]; // Save zmm0, zmm7, zmm8, zmm31
471 };
472
473 // The actual cpuid info block
474 static CpuidInfo _cpuid_info;
475
476 // Extractors and predicates
477 static uint32_t extended_cpu_family() {
478 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family;
479 result += _cpuid_info.std_cpuid1_eax.bits.ext_family;
480 return result;
481 }
482
483 static uint32_t extended_cpu_model() {
484 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model;
485 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;
486 return result;
487 }
488
489 static uint32_t cpu_stepping() {
490 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;
491 return result;
492 }
493
494 static uint logical_processor_count() {
495 uint result = threads_per_core();
496 return result;
497 }
498
499 static uint64_t feature_flags() {
500 uint64_t result = 0;
501 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
502 result |= CPU_CX8;
503 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
504 result |= CPU_CMOV;
505 if (_cpuid_info.std_cpuid1_edx.bits.clflush != 0)
506 result |= CPU_FLUSH;
507 #ifdef _LP64
508 // clflush should always be available on x86_64
509 // if not we are in real trouble because we rely on it
510 // to flush the code cache.
511 assert ((result & CPU_FLUSH) != 0, "clflush should be available");
512 #endif
513 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd_family() &&
514 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
515 result |= CPU_FXSR;
516 // HT flag is set for multi-core processors also.
517 if (threads_per_core() > 1)
518 result |= CPU_HT;
519 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd_family() &&
520 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
521 result |= CPU_MMX;
522 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
523 result |= CPU_SSE;
524 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
525 result |= CPU_SSE2;
526 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
527 result |= CPU_SSE3;
528 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
529 result |= CPU_SSSE3;
530 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
531 result |= CPU_SSE4_1;
532 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
533 result |= CPU_SSE4_2;
534 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
535 result |= CPU_POPCNT;
536 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 &&
537 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 &&
538 _cpuid_info.xem_xcr0_eax.bits.sse != 0 &&
539 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) {
540 result |= CPU_AVX;
541 result |= CPU_VZEROUPPER;
542 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0)
543 result |= CPU_AVX2;
544 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512f != 0 &&
545 _cpuid_info.xem_xcr0_eax.bits.opmask != 0 &&
546 _cpuid_info.xem_xcr0_eax.bits.zmm512 != 0 &&
547 _cpuid_info.xem_xcr0_eax.bits.zmm32 != 0) {
548 result |= CPU_AVX512F;
549 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512cd != 0)
550 result |= CPU_AVX512CD;
551 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512dq != 0)
552 result |= CPU_AVX512DQ;
553 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512pf != 0)
554 result |= CPU_AVX512PF;
555 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512er != 0)
556 result |= CPU_AVX512ER;
557 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512bw != 0)
558 result |= CPU_AVX512BW;
559 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512vl != 0)
560 result |= CPU_AVX512VL;
561 if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vpopcntdq != 0)
562 result |= CPU_AVX512_VPOPCNTDQ;
563 if (_cpuid_info.sef_cpuid7_ecx.bits.vpclmulqdq != 0)
564 result |= CPU_VPCLMULQDQ;
565 if (_cpuid_info.sef_cpuid7_ecx.bits.vaes != 0)
566 result |= CPU_VAES;
567 if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vnni != 0)
568 result |= CPU_VNNI;
569 }
570 }
571 if (_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
572 result |= CPU_BMI1;
573 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
574 result |= CPU_TSC;
575 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
576 result |= CPU_TSCINV;
577 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
578 result |= CPU_AES;
579 if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
580 result |= CPU_ERMS;
581 if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
582 result |= CPU_CLMUL;
583 if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
584 result |= CPU_RTM;
585 if (_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
586 result |= CPU_ADX;
587 if (_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
588 result |= CPU_BMI2;
589 if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0)
590 result |= CPU_SHA;
591 if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0)
592 result |= CPU_FMA;
593 if (_cpuid_info.sef_cpuid7_ebx.bits.clflushopt != 0)
594 result |= CPU_FLUSHOPT;
595
596 // AMD|Hygon features.
597 if (is_amd_family()) {
598 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
599 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
600 result |= CPU_3DNOW_PREFETCH;
601 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
602 result |= CPU_LZCNT;
603 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
604 result |= CPU_SSE4A;
605 }
606 // Intel features.
607 if (is_intel()) {
608 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
609 result |= CPU_LZCNT;
610 // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
611 if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
612 result |= CPU_3DNOW_PREFETCH;
613 }
614 if (_cpuid_info.sef_cpuid7_ebx.bits.clwb != 0) {
615 result |= CPU_CLWB;
616 }
617 }
618
619 // ZX features.
620 if (is_zx()) {
621 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
622 result |= CPU_LZCNT;
623 // for ZX, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
624 if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
625 result |= CPU_3DNOW_PREFETCH;
626 }
627 }
628
629 return result;
630 }
631
632 static bool os_supports_avx_vectors() {
633 bool retVal = false;
634 int nreg = 2 LP64_ONLY(+2);
635 if (supports_evex()) {
636 // Verify that OS save/restore all bits of EVEX registers
637 // during signal processing.
638 retVal = true;
639 for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register
640 if (_cpuid_info.zmm_save[i] != ymm_test_value()) {
641 retVal = false;
642 break;
643 }
644 }
645 } else if (supports_avx()) {
646 // Verify that OS save/restore all bits of AVX registers
647 // during signal processing.
648 retVal = true;
649 for (int i = 0; i < 8 * nreg; i++) { // 32 bytes per ymm register
650 if (_cpuid_info.ymm_save[i] != ymm_test_value()) {
651 retVal = false;
652 break;
653 }
654 }
655 // zmm_save will be set on a EVEX enabled machine even if we choose AVX code gen
656 if (retVal == false) {
657 // Verify that OS save/restore all bits of EVEX registers
658 // during signal processing.
659 retVal = true;
660 for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register
661 if (_cpuid_info.zmm_save[i] != ymm_test_value()) {
662 retVal = false;
663 break;
664 }
665 }
666 }
667 }
668 return retVal;
669 }
670
671 static void get_processor_features();
672
673 public:
674 // Offsets for cpuid asm stub
675 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
676 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
677 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
678 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); }
679 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
680 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
681 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); }
682 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
683 static ByteSize ext_cpuid1E_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1E_eax); }
684 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
685 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
686 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
687 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); }
688 static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); }
689 static ByteSize zmm_save_offset() { return byte_offset_of(CpuidInfo, zmm_save); }
690
691 // The value used to check ymm register after signal handle
692 static int ymm_test_value() { return 0xCAFEBABE; }
693
694 static void get_cpu_info_wrapper();
695 static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; }
696 static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; }
697 static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; }
698 static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; }
699
700 static void clean_cpuFeatures() { _features = 0; }
701 static void set_avx_cpuFeatures() { _features = (CPU_SSE | CPU_SSE2 | CPU_AVX | CPU_VZEROUPPER ); }
702 static void set_evex_cpuFeatures() { _features = (CPU_AVX512F | CPU_SSE | CPU_SSE2 | CPU_VZEROUPPER ); }
703
704
705 // Initialization
706 static void initialize();
707
708 // Override Abstract_VM_Version implementation
709 static void print_platform_virtualization_info(outputStream*);
710
711 // Override Abstract_VM_Version implementation
712 static bool use_biased_locking();
713
714 // Asserts
715 static void assert_is_initialized() {
716 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
717 }
718
719 //
720 // Processor family:
721 // 3 - 386
722 // 4 - 486
723 // 5 - Pentium
724 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
725 // Pentium M, Core Solo, Core Duo, Core2 Duo
726 // family 6 model: 9, 13, 14, 15
727 // 0x0f - Pentium 4, Opteron
728 //
729 // Note: The cpu family should be used to select between
730 // instruction sequences which are valid on all Intel
731 // processors. Use the feature test functions below to
732 // determine whether a particular instruction is supported.
733 //
734 static int cpu_family() { return _cpu;}
735 static bool is_P6() { return cpu_family() >= 6; }
736 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
737 static bool is_hygon() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x6F677948; } // 'ogyH'
738 static bool is_amd_family() { return is_amd() || is_hygon(); }
739 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
740 static bool is_zx() { assert_is_initialized(); return (_cpuid_info.std_vendor_name_0 == 0x746e6543) || (_cpuid_info.std_vendor_name_0 == 0x68532020); } // 'tneC'||'hS '
741 static bool is_atom_family() { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x36) || (extended_cpu_model() == 0x37) || (extended_cpu_model() == 0x4D))); } //Silvermont and Centerton
742 static bool is_knights_family() { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x57) || (extended_cpu_model() == 0x85))); } // Xeon Phi 3200/5200/7200 and Future Xeon Phi
743
744 static bool supports_processor_topology() {
745 return (_cpuid_info.std_max_function >= 0xB) &&
746 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
747 // Some cpus have max cpuid >= 0xB but do not support processor topology.
748 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
749 }
750
751 static uint cores_per_cpu() {
752 uint result = 1;
753 if (is_intel()) {
754 bool supports_topology = supports_processor_topology();
755 if (supports_topology) {
756 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
757 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
758 }
759 if (!supports_topology || result == 0) {
760 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
761 }
762 } else if (is_amd_family()) {
763 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
764 } else if (is_zx()) {
765 bool supports_topology = supports_processor_topology();
766 if (supports_topology) {
767 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
768 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
769 }
770 if (!supports_topology || result == 0) {
771 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
772 }
773 }
774 return result;
775 }
776
777 static uint threads_per_core() {
778 uint result = 1;
779 if (is_intel() && supports_processor_topology()) {
780 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
781 } else if (is_zx() && supports_processor_topology()) {
782 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
783 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
784 if (cpu_family() >= 0x17) {
785 result = _cpuid_info.ext_cpuid1E_ebx.bits.threads_per_core + 1;
786 } else {
787 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
788 cores_per_cpu();
789 }
790 }
791 return (result == 0 ? 1 : result);
792 }
793
794 static intx L1_line_size() {
795 intx result = 0;
796 if (is_intel()) {
797 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
798 } else if (is_amd_family()) {
799 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
800 } else if (is_zx()) {
801 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
802 }
803 if (result < 32) // not defined ?
804 result = 32; // 32 bytes by default on x86 and other x64
805 return result;
806 }
807
808 static intx prefetch_data_size() {
809 return L1_line_size();
810 }
811
812 //
813 // Feature identification
814 //
815 static bool supports_cpuid() { return _features != 0; }
816 static bool supports_cmpxchg8() { return (_features & CPU_CX8) != 0; }
817 static bool supports_cmov() { return (_features & CPU_CMOV) != 0; }
818 static bool supports_fxsr() { return (_features & CPU_FXSR) != 0; }
819 static bool supports_ht() { return (_features & CPU_HT) != 0; }
820 static bool supports_mmx() { return (_features & CPU_MMX) != 0; }
821 static bool supports_sse() { return (_features & CPU_SSE) != 0; }
822 static bool supports_sse2() { return (_features & CPU_SSE2) != 0; }
823 static bool supports_sse3() { return (_features & CPU_SSE3) != 0; }
824 static bool supports_ssse3() { return (_features & CPU_SSSE3)!= 0; }
825 static bool supports_sse4_1() { return (_features & CPU_SSE4_1) != 0; }
826 static bool supports_sse4_2() { return (_features & CPU_SSE4_2) != 0; }
827 static bool supports_popcnt() { return (_features & CPU_POPCNT) != 0; }
828 static bool supports_avx() { return (_features & CPU_AVX) != 0; }
829 static bool supports_avx2() { return (_features & CPU_AVX2) != 0; }
830 static bool supports_tsc() { return (_features & CPU_TSC) != 0; }
831 static bool supports_aes() { return (_features & CPU_AES) != 0; }
832 static bool supports_erms() { return (_features & CPU_ERMS) != 0; }
833 static bool supports_clmul() { return (_features & CPU_CLMUL) != 0; }
834 static bool supports_rtm() { return (_features & CPU_RTM) != 0; }
835 static bool supports_bmi1() { return (_features & CPU_BMI1) != 0; }
836 static bool supports_bmi2() { return (_features & CPU_BMI2) != 0; }
837 static bool supports_adx() { return (_features & CPU_ADX) != 0; }
838 static bool supports_evex() { return (_features & CPU_AVX512F) != 0; }
839 static bool supports_avx512dq() { return (_features & CPU_AVX512DQ) != 0; }
840 static bool supports_avx512pf() { return (_features & CPU_AVX512PF) != 0; }
841 static bool supports_avx512er() { return (_features & CPU_AVX512ER) != 0; }
842 static bool supports_avx512cd() { return (_features & CPU_AVX512CD) != 0; }
843 static bool supports_avx512bw() { return (_features & CPU_AVX512BW) != 0; }
844 static bool supports_avx512vl() { return (_features & CPU_AVX512VL) != 0; }
845 static bool supports_avx512vlbw() { return (supports_evex() && supports_avx512bw() && supports_avx512vl()); }
846 static bool supports_avx512vldq() { return (supports_evex() && supports_avx512dq() && supports_avx512vl()); }
847 static bool supports_avx512vlbwdq() { return (supports_evex() && supports_avx512vl() &&
848 supports_avx512bw() && supports_avx512dq()); }
849 static bool supports_avx512novl() { return (supports_evex() && !supports_avx512vl()); }
850 static bool supports_avx512nobw() { return (supports_evex() && !supports_avx512bw()); }
851 static bool supports_avx256only() { return (supports_avx2() && !supports_evex()); }
852 static bool supports_avxonly() { return ((supports_avx2() || supports_avx()) && !supports_evex()); }
853 static bool supports_sha() { return (_features & CPU_SHA) != 0; }
854 static bool supports_fma() { return (_features & CPU_FMA) != 0 && supports_avx(); }
855 static bool supports_vzeroupper() { return (_features & CPU_VZEROUPPER) != 0; }
856 static bool supports_vpopcntdq() { return (_features & CPU_AVX512_VPOPCNTDQ) != 0; }
857 static bool supports_vpclmulqdq() { return (_features & CPU_VPCLMULQDQ) != 0; }
858 static bool supports_vaes() { return (_features & CPU_VAES) != 0; }
859 static bool supports_vnni() { return (_features & CPU_VNNI) != 0; }
860
861 // Intel features
862 static bool is_intel_family_core() { return is_intel() &&
863 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
864
865 static bool is_intel_tsc_synched_at_init() {
866 if (is_intel_family_core()) {
867 uint32_t ext_model = extended_cpu_model();
868 if (ext_model == CPU_MODEL_NEHALEM_EP ||
869 ext_model == CPU_MODEL_WESTMERE_EP ||
870 ext_model == CPU_MODEL_SANDYBRIDGE_EP ||
871 ext_model == CPU_MODEL_IVYBRIDGE_EP) {
872 // <= 2-socket invariant tsc support. EX versions are usually used
873 // in > 2-socket systems and likely don't synchronize tscs at
874 // initialization.
875 // Code that uses tsc values must be prepared for them to arbitrarily
876 // jump forward or backward.
877 return true;
878 }
879 }
880 return false;
881 }
882
883 // AMD features
884 static bool supports_3dnow_prefetch() { return (_features & CPU_3DNOW_PREFETCH) != 0; }
885 static bool supports_mmx_ext() { return is_amd_family() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
886 static bool supports_lzcnt() { return (_features & CPU_LZCNT) != 0; }
887 static bool supports_sse4a() { return (_features & CPU_SSE4A) != 0; }
888
889 static bool is_amd_Barcelona() { return is_amd() &&
890 extended_cpu_family() == CPU_FAMILY_AMD_11H; }
891
892 // Intel and AMD newer cores support fast timestamps well
893 static bool supports_tscinv_bit() {
894 return (_features & CPU_TSCINV) != 0;
895 }
896 static bool supports_tscinv() {
897 return supports_tscinv_bit() &&
898 ((is_amd_family() && !is_amd_Barcelona()) ||
899 is_intel_tsc_synched_at_init());
900 }
901
902 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
903 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 &&
904 supports_sse3() && _model != 0x1C; }
905
906 static bool supports_compare_and_exchange() { return true; }
907
908 static intx allocate_prefetch_distance(bool use_watermark_prefetch) {
909 // Hardware prefetching (distance/size in bytes):
910 // Pentium 3 - 64 / 32
911 // Pentium 4 - 256 / 128
912 // Athlon - 64 / 32 ????
913 // Opteron - 128 / 64 only when 2 sequential cache lines accessed
914 // Core - 128 / 64
915 //
916 // Software prefetching (distance in bytes / instruction with best score):
917 // Pentium 3 - 128 / prefetchnta
918 // Pentium 4 - 512 / prefetchnta
919 // Athlon - 128 / prefetchnta
920 // Opteron - 256 / prefetchnta
921 // Core - 256 / prefetchnta
922 // It will be used only when AllocatePrefetchStyle > 0
923
924 if (is_amd_family()) { // AMD | Hygon
925 if (supports_sse2()) {
926 return 256; // Opteron
927 } else {
928 return 128; // Athlon
929 }
930 } else { // Intel
931 if (supports_sse3() && cpu_family() == 6) {
932 if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus
933 return 192;
934 } else if (use_watermark_prefetch) { // watermark prefetching on Core
935 #ifdef _LP64
936 return 384;
937 #else
938 return 320;
939 #endif
940 }
941 }
942 if (supports_sse2()) {
943 if (cpu_family() == 6) {
944 return 256; // Pentium M, Core, Core2
945 } else {
946 return 512; // Pentium 4
947 }
948 } else {
949 return 128; // Pentium 3 (and all other old CPUs)
950 }
951 }
952 }
953
954 // SSE2 and later processors implement a 'pause' instruction
955 // that can be used for efficient implementation of
956 // the intrinsic for java.lang.Thread.onSpinWait()
957 static bool supports_on_spin_wait() { return supports_sse2(); }
958
959 // x86_64 supports fast class initialization checks for static methods.
960 static bool supports_fast_class_init_checks() {
961 return LP64_ONLY(true) NOT_LP64(false); // not implemented on x86_32
962 }
963
964 // there are several insns to force cache line sync to memory which
965 // we can use to ensure mapped non-volatile memory is up to date with
966 // pending in-cache changes.
967 //
968 // 64 bit cpus always support clflush which writes back and evicts
969 // on 32 bit cpus support is recorded via a feature flag
970 //
971 // clflushopt is optional and acts like clflush except it does
972 // not synchronize with other memory ops. it needs a preceding
973 // and trailing StoreStore fence
974 //
975 // clwb is an optional, intel-specific instruction optional which
976 // writes back without evicting the line. it also does not
977 // synchronize with other memory ops. so, it also needs a preceding
978 // and trailing StoreStore fence.
979
980 #ifdef _LP64
981 static bool supports_clflush() {
982 // clflush should always be available on x86_64
983 // if not we are in real trouble because we rely on it
984 // to flush the code cache.
985 // Unfortunately, Assembler::clflush is currently called as part
986 // of generation of the code cache flush routine. This happens
987 // under Universe::init before the processor features are set
988 // up. Assembler::flush calls this routine to check that clflush
989 // is allowed. So, we give the caller a free pass if Universe init
990 // is still in progress.
991 assert ((!Universe::is_fully_initialized() || (_features & CPU_FLUSH) != 0), "clflush should be available");
992 return true;
993 }
994 static bool supports_clflushopt() { return ((_features & CPU_FLUSHOPT) != 0); }
995 static bool supports_clwb() { return ((_features & CPU_CLWB) != 0); }
996 #else
997 static bool supports_clflush() { return ((_features & CPU_FLUSH) != 0); }
998 static bool supports_clflushopt() { return false; }
999 static bool supports_clwb() { return false; }
1000 #endif // _LP64
1001
1002 // support functions for virtualization detection
1003 private:
1004 static void check_virt_cpuid(uint32_t idx, uint32_t *regs);
1005 static void check_virtualizations();
1006 };
1007
1008 #endif // CPU_X86_VM_VERSION_X86_HPP