1 /*
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   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
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   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
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  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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  24 
  25 #ifndef OS_CPU_LINUX_ARM_ORDERACCESS_LINUX_ARM_HPP
  26 #define OS_CPU_LINUX_ARM_ORDERACCESS_LINUX_ARM_HPP
  27 
  28 // Included in orderAccess.hpp header file.
  29 
  30 #include "runtime/os.hpp"
  31 #include "runtime/vm_version.hpp"
  32 
  33 // Implementation of class OrderAccess.
  34 // - we define the high level barriers below and use the general
  35 //   implementation in orderAccess.hpp.
  36 
  37 // Memory Ordering on ARM is weak.
  38 //
  39 // Implement all 4 memory ordering barriers by DMB, since it is a
  40 // lighter version of DSB.
  41 // dmb_sy implies full system shareability domain. RD/WR access type.
  42 // dmb_st implies full system shareability domain. WR only access type.
  43 //
  44 // NOP on < ARMv6 (MP not supported)
  45 //
  46 // Non mcr instructions can be used if we build for armv7 or higher arch
  47 //    __asm__ __volatile__ ("dmb" : : : "memory");
  48 //    __asm__ __volatile__ ("dsb" : : : "memory");
  49 //
  50 // inline void _OrderAccess_dsb() {
  51 //    volatile intptr_t dummy = 0;
  52 //    __asm__ volatile (
  53 //      "mcr p15, 0, %0, c7, c10, 4"
  54 //      : : "r" (dummy) : "memory");
  55 // }
  56 
  57 inline static void dmb_sy() {
  58    if (VM_Version::arm_arch() >= 7) {
  59 #ifdef __thumb__
  60      __asm__ volatile (
  61      "dmb sy": : : "memory");
  62 #else
  63      __asm__ volatile (
  64      ".word 0xF57FF050 | 0xf" : : : "memory");
  65 #endif
  66    } else if (VM_Version::arm_arch() == 6) {
  67      intptr_t zero = 0;
  68      __asm__ volatile (
  69        "mcr p15, 0, %0, c7, c10, 5"
  70        : : "r" (zero) : "memory");
  71    }
  72 }
  73 
  74 inline static void dmb_st() {
  75    if (VM_Version::arm_arch() >= 7) {
  76 #ifdef __thumb__
  77      __asm__ volatile (
  78      "dmb st": : : "memory");
  79 #else
  80      __asm__ volatile (
  81      ".word 0xF57FF050 | 0xe" : : : "memory");
  82 #endif
  83    } else if (VM_Version::arm_arch() == 6) {
  84      intptr_t zero = 0;
  85      __asm__ volatile (
  86        "mcr p15, 0, %0, c7, c10, 5"
  87        : : "r" (zero) : "memory");
  88    }
  89 }
  90 
  91 // Load-Load/Store barrier
  92 inline static void dmb_ld() {
  93    dmb_sy();
  94 }
  95 
  96 
  97 inline void OrderAccess::loadload()   { dmb_ld(); }
  98 inline void OrderAccess::loadstore()  { dmb_ld(); }
  99 inline void OrderAccess::acquire()    { dmb_ld(); }
 100 inline void OrderAccess::storestore() { dmb_st(); }
 101 inline void OrderAccess::storeload()  { dmb_sy(); }
 102 inline void OrderAccess::release()    { dmb_sy(); }
 103 inline void OrderAccess::fence()      { dmb_sy(); }
 104 inline void OrderAccess::cross_modify_fence()   { }
 105 
 106 #endif // OS_CPU_LINUX_ARM_ORDERACCESS_LINUX_ARM_HPP