1 /* 2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "jvm.h" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "logging/log.hpp" 29 #include "logging/logStream.hpp" 30 #include "memory/resourceArea.hpp" 31 #include "oops/compressedOops.hpp" 32 #include "runtime/java.hpp" 33 #include "runtime/os.hpp" 34 #include "runtime/stubCodeGenerator.hpp" 35 #include "vm_version_sparc.hpp" 36 37 #include <sys/mman.h> 38 39 uint VM_Version::_L2_data_cache_line_size = 0; 40 41 void VM_Version::initialize() { 42 assert(_features != 0, "System pre-initialization is not complete."); 43 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported"); 44 45 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); 46 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); 47 PrefetchFieldsAhead = prefetch_fields_ahead(); 48 49 // Allocation prefetch settings 50 51 AllocatePrefetchDistance = allocate_prefetch_distance(); 52 AllocatePrefetchStyle = allocate_prefetch_style(); 53 54 intx cache_line_size = prefetch_data_size(); 55 56 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize)) { 57 AllocatePrefetchStepSize = MAX2(AllocatePrefetchStepSize, cache_line_size); 58 } 59 60 if (AllocatePrefetchInstr == 1) { 61 if (!has_blk_init()) { 62 warning("BIS instructions required for AllocatePrefetchInstr 1 unavailable"); 63 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0); 64 } 65 if (cache_line_size <= 0) { 66 warning("Cache-line size must be known for AllocatePrefetchInstr 1 to work"); 67 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0); 68 } 69 } 70 71 UseSSE = false; // Only used on x86 and x64. 72 73 _supports_cx8 = true; // All SPARC V9 implementations. 74 _supports_atomic_getset4 = true; // Using the 'swap' instruction. 75 76 if (has_fast_ind_br() && FLAG_IS_DEFAULT(UseInlineCaches)) { 77 // Indirect and direct branches are cost equivalent. 78 FLAG_SET_DEFAULT(UseInlineCaches, false); 79 } 80 // Align loops on the proper instruction boundary to fill the instruction 81 // fetch buffer. 82 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { 83 FLAG_SET_DEFAULT(OptoLoopAlignment, VM_Version::insn_fetch_alignment); 84 } 85 86 // 32-bit oops don't make sense for the 64-bit VM on SPARC since the 32-bit 87 // VM has the same registers and smaller objects. 88 CompressedOops::set_shift(LogMinObjAlignmentInBytes); 89 CompressedKlassPointers::set_shift(LogKlassAlignmentInBytes); 90 91 #ifdef COMPILER2 92 if (has_fast_ind_br() && FLAG_IS_DEFAULT(UseJumpTables)) { 93 // Indirect and direct branches are cost equivalent. 94 FLAG_SET_DEFAULT(UseJumpTables, true); 95 } 96 // Entry and loop tops are aligned to fill the instruction fetch buffer. 97 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { 98 FLAG_SET_DEFAULT(InteriorEntryAlignment, VM_Version::insn_fetch_alignment); 99 } 100 if (UseTLAB && cache_line_size > 0 && 101 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { 102 if (has_fast_bis()) { 103 // Use BIS instruction for TLAB allocation prefetch. 104 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1); 105 } 106 else if (has_sparc5()) { 107 // Use prefetch instruction to avoid partial RAW issue on Core C4 processors, 108 // also use prefetch style 3. 109 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0); 110 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { 111 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3); 112 } 113 } 114 } 115 if (AllocatePrefetchInstr == 1) { 116 // Use allocation prefetch style 3 because BIS instructions require 117 // aligned memory addresses. 118 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3); 119 } 120 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { 121 if (AllocatePrefetchInstr == 0) { 122 // Use different prefetch distance without BIS 123 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); 124 } else { 125 // Use smaller prefetch distance with BIS 126 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64); 127 } 128 } 129 130 // We increase the number of prefetched cache lines, to use just a bit more 131 // aggressive approach, when the L2-cache line size is small (32 bytes), or 132 // when running on newer processor implementations, such as the Core C4. 133 bool inc_prefetch = cache_line_size > 0 && (cache_line_size < 64 || has_sparc5()); 134 135 if (inc_prefetch) { 136 // We use a factor two for small cache line sizes (as before) but a slightly 137 // more conservative increase when running on more recent hardware that will 138 // benefit from just a bit more aggressive prefetching. 139 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) { 140 const int ap_lns = AllocatePrefetchLines; 141 const int ap_inc = cache_line_size < 64 ? ap_lns : (ap_lns + 1) / 2; 142 FLAG_SET_ERGO(AllocatePrefetchLines, ap_lns + ap_inc); 143 } 144 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) { 145 const int ip_lns = AllocateInstancePrefetchLines; 146 const int ip_inc = cache_line_size < 64 ? ip_lns : (ip_lns + 1) / 2; 147 FLAG_SET_ERGO(AllocateInstancePrefetchLines, ip_lns + ip_inc); 148 } 149 } 150 #endif /* COMPILER2 */ 151 152 // Use hardware population count instruction if available. 153 if (has_popc()) { 154 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { 155 FLAG_SET_DEFAULT(UsePopCountInstruction, true); 156 } 157 } else if (UsePopCountInstruction) { 158 warning("POPC instruction is not available on this CPU"); 159 FLAG_SET_DEFAULT(UsePopCountInstruction, false); 160 } 161 162 // Use compare and branch instructions if available. 163 if (has_cbcond()) { 164 if (FLAG_IS_DEFAULT(UseCBCond)) { 165 FLAG_SET_DEFAULT(UseCBCond, true); 166 } 167 } else if (UseCBCond) { 168 warning("CBCOND instruction is not available on this CPU"); 169 FLAG_SET_DEFAULT(UseCBCond, false); 170 } 171 172 // Use 'mpmul' instruction if available. 173 if (has_mpmul()) { 174 if (FLAG_IS_DEFAULT(UseMPMUL)) { 175 FLAG_SET_DEFAULT(UseMPMUL, true); 176 } 177 } else if (UseMPMUL) { 178 warning("MPMUL instruction is not available on this CPU"); 179 FLAG_SET_DEFAULT(UseMPMUL, false); 180 } 181 182 assert(BlockZeroingLowLimit > 0, "invalid value"); 183 184 if (has_blk_zeroing() && cache_line_size > 0) { 185 if (FLAG_IS_DEFAULT(UseBlockZeroing)) { 186 FLAG_SET_DEFAULT(UseBlockZeroing, true); 187 } 188 } else if (UseBlockZeroing) { 189 warning("BIS zeroing instructions are not available on this CPU"); 190 FLAG_SET_DEFAULT(UseBlockZeroing, false); 191 } 192 193 assert(BlockCopyLowLimit > 0, "invalid value"); 194 195 if (has_blk_zeroing() && cache_line_size > 0) { 196 if (FLAG_IS_DEFAULT(UseBlockCopy)) { 197 FLAG_SET_DEFAULT(UseBlockCopy, true); 198 } 199 } else if (UseBlockCopy) { 200 warning("BIS instructions are not available or expensive on this CPU"); 201 FLAG_SET_DEFAULT(UseBlockCopy, false); 202 } 203 204 #ifdef COMPILER2 205 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) { 206 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true); 207 } 208 209 // Currently not supported anywhere. 210 FLAG_SET_DEFAULT(UseFPUForSpilling, false); 211 212 MaxVectorSize = 8; 213 214 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); 215 #endif 216 217 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); 218 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); 219 220 char buf[512]; 221 jio_snprintf(buf, sizeof(buf), 222 "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s" 223 "%s%s%s%s%s%s%s%s%s" "%s%s%s%s%s%s%s%s%s" 224 "%s%s%s%s%s%s%s", 225 (has_v9() ? "v9" : ""), 226 (has_popc() ? ", popc" : ""), 227 (has_vis1() ? ", vis1" : ""), 228 (has_vis2() ? ", vis2" : ""), 229 (has_blk_init() ? ", blk_init" : ""), 230 (has_fmaf() ? ", fmaf" : ""), 231 (has_hpc() ? ", hpc" : ""), 232 (has_ima() ? ", ima" : ""), 233 (has_aes() ? ", aes" : ""), 234 (has_des() ? ", des" : ""), 235 (has_kasumi() ? ", kas" : ""), 236 (has_camellia() ? ", cam" : ""), 237 (has_md5() ? ", md5" : ""), 238 (has_sha1() ? ", sha1" : ""), 239 (has_sha256() ? ", sha256" : ""), 240 (has_sha512() ? ", sha512" : ""), 241 (has_mpmul() ? ", mpmul" : ""), 242 (has_mont() ? ", mont" : ""), 243 (has_pause() ? ", pause" : ""), 244 (has_cbcond() ? ", cbcond" : ""), 245 (has_crc32c() ? ", crc32c" : ""), 246 247 (has_athena_plus() ? ", athena_plus" : ""), 248 (has_vis3b() ? ", vis3b" : ""), 249 (has_adi() ? ", adi" : ""), 250 (has_sparc5() ? ", sparc5" : ""), 251 (has_mwait() ? ", mwait" : ""), 252 (has_xmpmul() ? ", xmpmul" : ""), 253 (has_xmont() ? ", xmont" : ""), 254 (has_pause_nsec() ? ", pause_nsec" : ""), 255 (has_vamask() ? ", vamask" : ""), 256 257 (has_sparc6() ? ", sparc6" : ""), 258 (has_dictunp() ? ", dictunp" : ""), 259 (has_fpcmpshl() ? ", fpcmpshl" : ""), 260 (has_rle() ? ", rle" : ""), 261 (has_sha3() ? ", sha3" : ""), 262 (has_athena_plus2()? ", athena_plus2" : ""), 263 (has_vis3c() ? ", vis3c" : ""), 264 (has_sparc5b() ? ", sparc5b" : ""), 265 (has_mme() ? ", mme" : ""), 266 267 (has_fast_idiv() ? ", *idiv" : ""), 268 (has_fast_rdpc() ? ", *rdpc" : ""), 269 (has_fast_bis() ? ", *bis" : ""), 270 (has_fast_ld() ? ", *ld" : ""), 271 (has_fast_cmove() ? ", *cmove" : ""), 272 (has_fast_ind_br() ? ", *ind_br" : ""), 273 (has_blk_zeroing() ? ", *blk_zeroing" : "")); 274 275 assert(strlen(buf) >= 2, "must be"); 276 277 _features_string = os::strdup(buf); 278 279 log_info(os, cpu)("SPARC features detected: %s", _features_string); 280 281 // UseVIS is set to the smallest of what hardware supports and what the command 282 // line requires, i.e. you cannot set UseVIS to 3 on older UltraSparc which do 283 // not support it. 284 285 if (UseVIS > 3) UseVIS = 3; 286 if (UseVIS < 0) UseVIS = 0; 287 if (!has_vis3()) // Drop to 2 if no VIS3 support 288 UseVIS = MIN2((intx)2, UseVIS); 289 if (!has_vis2()) // Drop to 1 if no VIS2 support 290 UseVIS = MIN2((intx)1, UseVIS); 291 if (!has_vis1()) // Drop to 0 if no VIS1 support 292 UseVIS = 0; 293 294 if (has_aes()) { 295 if (FLAG_IS_DEFAULT(UseAES)) { 296 FLAG_SET_DEFAULT(UseAES, true); 297 } 298 if (!UseAES) { 299 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { 300 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled."); 301 } 302 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 303 } else { 304 // The AES intrinsic stubs require AES instruction support (of course) 305 // but also require VIS3 mode or higher for instructions it use. 306 if (UseVIS > 2) { 307 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { 308 FLAG_SET_DEFAULT(UseAESIntrinsics, true); 309 } 310 } else { 311 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { 312 warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled."); 313 } 314 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 315 } 316 } 317 } else if (UseAES || UseAESIntrinsics) { 318 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) { 319 warning("AES instructions are not available on this CPU"); 320 FLAG_SET_DEFAULT(UseAES, false); 321 } 322 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { 323 warning("AES intrinsics are not available on this CPU"); 324 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 325 } 326 } 327 328 if (UseAESCTRIntrinsics) { 329 warning("AES/CTR intrinsics are not available on this CPU"); 330 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); 331 } 332 333 // GHASH/GCM intrinsics 334 if (has_vis3() && (UseVIS > 2)) { 335 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) { 336 UseGHASHIntrinsics = true; 337 } 338 } else if (UseGHASHIntrinsics) { 339 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics)) 340 warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled"); 341 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false); 342 } 343 344 if (has_fmaf()) { 345 if (FLAG_IS_DEFAULT(UseFMA)) { 346 UseFMA = true; 347 } 348 } else if (UseFMA) { 349 warning("FMA instructions are not available on this CPU"); 350 FLAG_SET_DEFAULT(UseFMA, false); 351 } 352 353 // SHA1, SHA256, and SHA512 instructions were added to SPARC at different times 354 if (has_sha1() || has_sha256() || has_sha512()) { 355 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions 356 if (FLAG_IS_DEFAULT(UseSHA)) { 357 FLAG_SET_DEFAULT(UseSHA, true); 358 } 359 } else { 360 if (UseSHA) { 361 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled."); 362 FLAG_SET_DEFAULT(UseSHA, false); 363 } 364 } 365 } else if (UseSHA) { 366 warning("SHA instructions are not available on this CPU"); 367 FLAG_SET_DEFAULT(UseSHA, false); 368 } 369 370 if (UseSHA && has_sha1()) { 371 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) { 372 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true); 373 } 374 } else if (UseSHA1Intrinsics) { 375 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU."); 376 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); 377 } 378 379 if (UseSHA && has_sha256()) { 380 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) { 381 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true); 382 } 383 } else if (UseSHA256Intrinsics) { 384 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU."); 385 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); 386 } 387 388 if (UseSHA && has_sha512()) { 389 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) { 390 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true); 391 } 392 } else if (UseSHA512Intrinsics) { 393 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU."); 394 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 395 } 396 397 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) { 398 FLAG_SET_DEFAULT(UseSHA, false); 399 } 400 401 if (has_crc32c()) { 402 if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions 403 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) { 404 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true); 405 } 406 } else { 407 if (UseCRC32CIntrinsics) { 408 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled."); 409 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); 410 } 411 } 412 } else if (UseCRC32CIntrinsics) { 413 warning("CRC32C instruction is not available on this CPU"); 414 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); 415 } 416 417 if (UseVIS > 2) { 418 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) { 419 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true); 420 } 421 } else if (UseAdler32Intrinsics) { 422 warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled."); 423 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false); 424 } 425 426 if (UseVIS > 2) { 427 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { 428 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true); 429 } 430 } else if (UseCRC32Intrinsics) { 431 warning("SPARC CRC32 intrinsics require VIS3 instructions support. Intrinsics will be disabled"); 432 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false); 433 } 434 435 if (UseVIS > 2) { 436 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { 437 FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, true); 438 } 439 } else if (UseMultiplyToLenIntrinsic) { 440 warning("SPARC multiplyToLen intrinsics require VIS3 instructions support. Intrinsics will be disabled"); 441 FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false); 442 } 443 444 if (UseVectorizedMismatchIntrinsic) { 445 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU."); 446 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false); 447 } 448 449 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && 450 (cache_line_size > ContendedPaddingWidth)) 451 ContendedPaddingWidth = cache_line_size; 452 453 // This machine does not allow unaligned memory accesses 454 if (UseUnalignedAccesses) { 455 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses)) 456 warning("Unaligned memory access is not available on this CPU"); 457 FLAG_SET_DEFAULT(UseUnalignedAccesses, false); 458 } 459 460 if (log_is_enabled(Info, os, cpu)) { 461 ResourceMark rm; 462 LogStream ls(Log(os, cpu)::info()); 463 outputStream* log = &ls; 464 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size()); 465 log->print_cr("L2 data cache line size: %u", L2_data_cache_line_size()); 466 log->print("Allocation"); 467 if (AllocatePrefetchStyle <= 0) { 468 log->print(": no prefetching"); 469 } else { 470 log->print(" prefetching: "); 471 if (AllocatePrefetchInstr == 0) { 472 log->print("PREFETCH"); 473 } else if (AllocatePrefetchInstr == 1) { 474 log->print("BIS"); 475 } 476 if (AllocatePrefetchLines > 1) { 477 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize); 478 } else { 479 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize); 480 } 481 } 482 if (PrefetchCopyIntervalInBytes > 0) { 483 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes); 484 } 485 if (PrefetchScanIntervalInBytes > 0) { 486 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes); 487 } 488 if (PrefetchFieldsAhead > 0) { 489 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead); 490 } 491 if (ContendedPaddingWidth > 0) { 492 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth); 493 } 494 } 495 } 496 497 void VM_Version::print_features() { 498 tty->print("ISA features [0x%0" PRIx64 "]:", _features); 499 if (_features_string != NULL) { 500 tty->print(" %s", _features_string); 501 } 502 tty->cr(); 503 } 504 505 void VM_Version::determine_features() { 506 platform_features(); // platform_features() is os_arch specific. 507 508 assert(has_v9(), "must be"); 509 510 if (UseNiagaraInstrs) { // Limit code generation to Niagara. 511 _features &= niagara1_msk; 512 } 513 } 514 515 static uint64_t saved_features = 0; 516 517 void VM_Version::allow_all() { 518 saved_features = _features; 519 _features = full_feature_msk; 520 } 521 522 void VM_Version::revert() { 523 _features = saved_features; 524 }