1 /* 2 * Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2016, 2017 SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 1327 #define ECAG_ZOPC (unsigned long)(0xebL <<40 | 0x4cL) // z10 1328 1329 // Execution Prediction 1330 #define PFD_ZOPC (unsigned long)(0xe3L <<40 | 0x36L) // z10 1331 #define PFDRL_ZOPC (unsigned long)(0xc6L <<40 | 0x02L << 32) // z10 1332 #define BPP_ZOPC (unsigned long)(0xc7L <<40) // branch prediction preload -- EC12 1333 #define BPRP_ZOPC (unsigned long)(0xc5L <<40) // branch prediction preload -- EC12 1334 1335 // Transaction Control 1336 #define TBEGIN_ZOPC (unsigned long)(0xe560L << 32) // tx begin -- EC12 1337 #define TBEGINC_ZOPC (unsigned long)(0xe561L << 32) // tx begin (constrained) -- EC12 1338 #define TEND_ZOPC (unsigned int)(0xb2f8 << 16) // tx end -- EC12 1339 #define TABORT_ZOPC (unsigned int)(0xb2fc << 16) // tx abort -- EC12 1340 #define ETND_ZOPC (unsigned int)(0xb2ec << 16) // tx nesting depth -- EC12 1341 #define PPA_ZOPC (unsigned int)(0xb2e8 << 16) // tx processor assist -- EC12 1342 1343 // Crypto and Checksum 1344 #define CKSM_ZOPC (unsigned int)(0xb2 << 24 | 0x41 << 16) // checksum. This is NOT CRC32 1345 #define KM_ZOPC (unsigned int)(0xb9 << 24 | 0x2e << 16) // cipher 1346 #define KMC_ZOPC (unsigned int)(0xb9 << 24 | 0x2f << 16) // cipher 1347 #define KIMD_ZOPC (unsigned int)(0xb9 << 24 | 0x3e << 16) // SHA (msg digest) 1348 #define KLMD_ZOPC (unsigned int)(0xb9 << 24 | 0x3f << 16) // SHA (msg digest) 1349 #define KMAC_ZOPC (unsigned int)(0xb9 << 24 | 0x1e << 16) // Message Authentication Code 1350 1351 // Various 1352 #define TCEB_ZOPC (unsigned long)(237L << 40 | 16) 1353 #define TCDB_ZOPC (unsigned long)(237L << 40 | 17) 1354 #define TAM_ZOPC (unsigned long)(267) 1355 1356 #define FLOGR_ZOPC (unsigned int)(0xb9 << 24 | 0x83 << 16) 1357 #define POPCNT_ZOPC (unsigned int)(0xb9e1 << 16) 1358 #define AHHHR_ZOPC (unsigned int)(0xb9c8 << 16) 1359 #define AHHLR_ZOPC (unsigned int)(0xb9d8 << 16) 1360 1361 1362 // OpCode field masks 1363 1364 #define RI_MASK (unsigned int)(0xff << 24 | 0x0f << 16) 1365 #define RRE_MASK (unsigned int)(0xff << 24 | 0xff << 16) 1366 #define RSI_MASK (unsigned int)(0xff << 24) 2372 inline void z_tabort(int64_t d2, Register b2); // abort transaction -- EC12 2373 inline void z_etnd(Register r1); // extract tx nesting depth -- EC12 2374 inline void z_ppa(Register r1, Register r2, int64_t m3); // perform processor assist -- EC12 2375 2376 //--------------------------------- 2377 // Conditional Execution 2378 //--------------------------------- 2379 inline void z_locr( Register r1, Register r2, branch_condition cc); // if (cc) load r1 = r2 ; int32 -- z196 2380 inline void z_locgr(Register r1, Register r2, branch_condition cc); // if (cc) load r1 = r2 ; int64 -- z196 2381 inline void z_loc( Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) load r1 = *(d2_simm20+b2) ; int32 -- z196 2382 inline void z_locg( Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) load r1 = *(d2_simm20+b2) ; int64 -- z196 2383 inline void z_loc( Register r1, const Address& a, branch_condition cc); // if (cc) load r1 = *(a) ; int32 -- z196 2384 inline void z_locg( Register r1, const Address& a, branch_condition cc); // if (cc) load r1 = *(a) ; int64 -- z196 2385 inline void z_stoc( Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) store *(d2_simm20+b2) = r1 ; int32 -- z196 2386 inline void z_stocg(Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) store *(d2_simm20+b2) = r1 ; int64 -- z196 2387 2388 2389 // Complex CISC instructions 2390 // ========================== 2391 2392 inline void z_cksm(Register r1, Register r2); // checksum. This is NOT CRC32 2393 inline void z_km( Register r1, Register r2); // cipher message 2394 inline void z_kmc( Register r1, Register r2); // cipher message with chaining 2395 inline void z_kimd(Register r1, Register r2); // msg digest (SHA) 2396 inline void z_klmd(Register r1, Register r2); // msg digest (SHA) 2397 inline void z_kmac(Register r1, Register r2); // msg authentication code 2398 2399 inline void z_ex(Register r1, int64_t d2, Register x2, Register b2);// execute 2400 inline void z_exrl(Register r1, int64_t i2); // execute relative long -- z10 2401 inline void z_exrl(Register r1, address a2); // execute relative long -- z10 2402 2403 inline void z_ectg(int64_t d1, Register b1, int64_t d2, Register b2, Register r3); // extract cpu time 2404 inline void z_ecag(Register r1, Register r3, int64_t d2, Register b2); // extract CPU attribute 2405 2406 inline void z_srst(Register r1, Register r2); // search string 2407 inline void z_srstu(Register r1, Register r2); // search string unicode 2408 2409 inline void z_mvc(const Address& d, const Address& s, int64_t l); // move l bytes 2410 inline void z_mvc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2); // move l+1 bytes 2411 inline void z_mvcle(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // move region of memory 2412 2413 inline void z_stfle(int64_t d2, Register b2); // store facility list extended 2414 2415 inline void z_nc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);// and *(d1+b1) = *(d1+l+b1) & *(d2+b2) ; d1, d2: uimm12, ands l+1 bytes 2416 inline void z_oc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);// or *(d1+b1) = *(d1+l+b1) | *(d2+b2) ; d1, d2: uimm12, ors l+1 bytes 2417 inline void z_xc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);// xor *(d1+b1) = *(d1+l+b1) ^ *(d2+b2) ; d1, d2: uimm12, xors l+1 bytes 3013 inline void z_brul(Label& L); 3014 inline void z_brul(address a); 3015 inline void z_brh( Label& L); 3016 inline void z_brl( Label& L); 3017 inline void z_bre( Label& L); 3018 inline void z_brnh(Label& L); 3019 inline void z_brnl(Label& L); 3020 inline void z_brne(Label& L); 3021 inline void z_brz( Label& L); 3022 inline void z_brnz(Label& L); 3023 inline void z_brnaz(Label& L); 3024 inline void z_braz(Label& L); 3025 inline void z_brnp(Label& L); 3026 3027 inline void z_btrue( Label& L); 3028 inline void z_bfalse(Label& L); 3029 3030 inline void z_bvat(Label& L); // all true 3031 inline void z_bvnt(Label& L); // not all true (mixed or all false) 3032 inline void z_bvmix(Label& L); // mixed true and false 3033 inline void z_bvaf(Label& L); // not all false (mixed or all true) 3034 inline void z_bvnf(Label& L); // all false 3035 3036 inline void z_brno( Label& L); 3037 3038 3039 inline void z_basr(Register r1, Register r2); 3040 inline void z_brasl(Register r1, address a); 3041 inline void z_brct(Register r1, address a); 3042 inline void z_brct(Register r1, Label& L); 3043 3044 inline void z_brxh(Register r1, Register r3, address a); 3045 inline void z_brxh(Register r1, Register r3, Label& L); 3046 3047 inline void z_brxle(Register r1, Register r3, address a); 3048 inline void z_brxle(Register r1, Register r3, Label& L); 3049 3050 inline void z_brxhg(Register r1, Register r3, address a); 3051 inline void z_brxhg(Register r1, Register r3, Label& L); 3052 3053 inline void z_brxlg(Register r1, Register r3, address a); 3054 inline void z_brxlg(Register r1, Register r3, Label& L); | 1 /* 2 * Copyright (c) 2016, 2021, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2016, 2021 SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 1327 #define ECAG_ZOPC (unsigned long)(0xebL <<40 | 0x4cL) // z10 1328 1329 // Execution Prediction 1330 #define PFD_ZOPC (unsigned long)(0xe3L <<40 | 0x36L) // z10 1331 #define PFDRL_ZOPC (unsigned long)(0xc6L <<40 | 0x02L << 32) // z10 1332 #define BPP_ZOPC (unsigned long)(0xc7L <<40) // branch prediction preload -- EC12 1333 #define BPRP_ZOPC (unsigned long)(0xc5L <<40) // branch prediction preload -- EC12 1334 1335 // Transaction Control 1336 #define TBEGIN_ZOPC (unsigned long)(0xe560L << 32) // tx begin -- EC12 1337 #define TBEGINC_ZOPC (unsigned long)(0xe561L << 32) // tx begin (constrained) -- EC12 1338 #define TEND_ZOPC (unsigned int)(0xb2f8 << 16) // tx end -- EC12 1339 #define TABORT_ZOPC (unsigned int)(0xb2fc << 16) // tx abort -- EC12 1340 #define ETND_ZOPC (unsigned int)(0xb2ec << 16) // tx nesting depth -- EC12 1341 #define PPA_ZOPC (unsigned int)(0xb2e8 << 16) // tx processor assist -- EC12 1342 1343 // Crypto and Checksum 1344 #define CKSM_ZOPC (unsigned int)(0xb2 << 24 | 0x41 << 16) // checksum. This is NOT CRC32 1345 #define KM_ZOPC (unsigned int)(0xb9 << 24 | 0x2e << 16) // cipher 1346 #define KMC_ZOPC (unsigned int)(0xb9 << 24 | 0x2f << 16) // cipher 1347 #define KMA_ZOPC (unsigned int)(0xb9 << 24 | 0x29 << 16) // cipher 1348 #define KMF_ZOPC (unsigned int)(0xb9 << 24 | 0x2a << 16) // cipher 1349 #define KMCTR_ZOPC (unsigned int)(0xb9 << 24 | 0x2d << 16) // cipher 1350 #define KMO_ZOPC (unsigned int)(0xb9 << 24 | 0x2b << 16) // cipher 1351 #define KIMD_ZOPC (unsigned int)(0xb9 << 24 | 0x3e << 16) // SHA (msg digest) 1352 #define KLMD_ZOPC (unsigned int)(0xb9 << 24 | 0x3f << 16) // SHA (msg digest) 1353 #define KMAC_ZOPC (unsigned int)(0xb9 << 24 | 0x1e << 16) // Message Authentication Code 1354 1355 // Various 1356 #define TCEB_ZOPC (unsigned long)(237L << 40 | 16) 1357 #define TCDB_ZOPC (unsigned long)(237L << 40 | 17) 1358 #define TAM_ZOPC (unsigned long)(267) 1359 1360 #define FLOGR_ZOPC (unsigned int)(0xb9 << 24 | 0x83 << 16) 1361 #define POPCNT_ZOPC (unsigned int)(0xb9e1 << 16) 1362 #define AHHHR_ZOPC (unsigned int)(0xb9c8 << 16) 1363 #define AHHLR_ZOPC (unsigned int)(0xb9d8 << 16) 1364 1365 1366 // OpCode field masks 1367 1368 #define RI_MASK (unsigned int)(0xff << 24 | 0x0f << 16) 1369 #define RRE_MASK (unsigned int)(0xff << 24 | 0xff << 16) 1370 #define RSI_MASK (unsigned int)(0xff << 24) 2376 inline void z_tabort(int64_t d2, Register b2); // abort transaction -- EC12 2377 inline void z_etnd(Register r1); // extract tx nesting depth -- EC12 2378 inline void z_ppa(Register r1, Register r2, int64_t m3); // perform processor assist -- EC12 2379 2380 //--------------------------------- 2381 // Conditional Execution 2382 //--------------------------------- 2383 inline void z_locr( Register r1, Register r2, branch_condition cc); // if (cc) load r1 = r2 ; int32 -- z196 2384 inline void z_locgr(Register r1, Register r2, branch_condition cc); // if (cc) load r1 = r2 ; int64 -- z196 2385 inline void z_loc( Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) load r1 = *(d2_simm20+b2) ; int32 -- z196 2386 inline void z_locg( Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) load r1 = *(d2_simm20+b2) ; int64 -- z196 2387 inline void z_loc( Register r1, const Address& a, branch_condition cc); // if (cc) load r1 = *(a) ; int32 -- z196 2388 inline void z_locg( Register r1, const Address& a, branch_condition cc); // if (cc) load r1 = *(a) ; int64 -- z196 2389 inline void z_stoc( Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) store *(d2_simm20+b2) = r1 ; int32 -- z196 2390 inline void z_stocg(Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) store *(d2_simm20+b2) = r1 ; int64 -- z196 2391 2392 2393 // Complex CISC instructions 2394 // ========================== 2395 2396 inline void z_cksm( Register r1, Register r2); // checksum. This is NOT CRC32 2397 inline void z_km( Register r1, Register r2); // cipher message 2398 inline void z_kmc( Register r1, Register r2); // cipher message with chaining 2399 inline void z_kma( Register r1, Register r3, Register r2); // cipher message with authentication 2400 inline void z_kmf( Register r1, Register r2); // cipher message with cipher feedback 2401 inline void z_kmctr(Register r1, Register r3, Register r2); // cipher message with counter 2402 inline void z_kmo( Register r1, Register r2); // cipher message with output feedback 2403 inline void z_kimd( Register r1, Register r2); // msg digest (SHA) 2404 inline void z_klmd( Register r1, Register r2); // msg digest (SHA) 2405 inline void z_kmac( Register r1, Register r2); // msg authentication code 2406 2407 inline void z_ex(Register r1, int64_t d2, Register x2, Register b2);// execute 2408 inline void z_exrl(Register r1, int64_t i2); // execute relative long -- z10 2409 inline void z_exrl(Register r1, address a2); // execute relative long -- z10 2410 2411 inline void z_ectg(int64_t d1, Register b1, int64_t d2, Register b2, Register r3); // extract cpu time 2412 inline void z_ecag(Register r1, Register r3, int64_t d2, Register b2); // extract CPU attribute 2413 2414 inline void z_srst(Register r1, Register r2); // search string 2415 inline void z_srstu(Register r1, Register r2); // search string unicode 2416 2417 inline void z_mvc(const Address& d, const Address& s, int64_t l); // move l bytes 2418 inline void z_mvc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2); // move l+1 bytes 2419 inline void z_mvcle(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // move region of memory 2420 2421 inline void z_stfle(int64_t d2, Register b2); // store facility list extended 2422 2423 inline void z_nc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);// and *(d1+b1) = *(d1+l+b1) & *(d2+b2) ; d1, d2: uimm12, ands l+1 bytes 2424 inline void z_oc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);// or *(d1+b1) = *(d1+l+b1) | *(d2+b2) ; d1, d2: uimm12, ors l+1 bytes 2425 inline void z_xc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);// xor *(d1+b1) = *(d1+l+b1) ^ *(d2+b2) ; d1, d2: uimm12, xors l+1 bytes 3021 inline void z_brul(Label& L); 3022 inline void z_brul(address a); 3023 inline void z_brh( Label& L); 3024 inline void z_brl( Label& L); 3025 inline void z_bre( Label& L); 3026 inline void z_brnh(Label& L); 3027 inline void z_brnl(Label& L); 3028 inline void z_brne(Label& L); 3029 inline void z_brz( Label& L); 3030 inline void z_brnz(Label& L); 3031 inline void z_brnaz(Label& L); 3032 inline void z_braz(Label& L); 3033 inline void z_brnp(Label& L); 3034 3035 inline void z_btrue( Label& L); 3036 inline void z_bfalse(Label& L); 3037 3038 inline void z_bvat(Label& L); // all true 3039 inline void z_bvnt(Label& L); // not all true (mixed or all false) 3040 inline void z_bvmix(Label& L); // mixed true and false 3041 inline void z_bvnf(Label& L); // not all false (mixed or all true) 3042 inline void z_bvaf(Label& L); // all false 3043 3044 inline void z_brno( Label& L); 3045 3046 3047 inline void z_basr(Register r1, Register r2); 3048 inline void z_brasl(Register r1, address a); 3049 inline void z_brct(Register r1, address a); 3050 inline void z_brct(Register r1, Label& L); 3051 3052 inline void z_brxh(Register r1, Register r3, address a); 3053 inline void z_brxh(Register r1, Register r3, Label& L); 3054 3055 inline void z_brxle(Register r1, Register r3, address a); 3056 inline void z_brxle(Register r1, Register r3, Label& L); 3057 3058 inline void z_brxhg(Register r1, Register r3, address a); 3059 inline void z_brxhg(Register r1, Register r3, Label& L); 3060 3061 inline void z_brxlg(Register r1, Register r3, address a); 3062 inline void z_brxlg(Register r1, Register r3, Label& L); |