1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc_interface/collectedHeap.inline.hpp"
29 #include "interpreter/interpreter.hpp"
30 #include "memory/cardTableModRefBS.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
42 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc_implementation/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
59 // -----------------Table 4.5 -------------------- //
60 16, 32, 64, // EVEX_FV(0)
61 4, 4, 4, // EVEX_FV(1) - with Evex.b
62 16, 32, 64, // EVEX_FV(2) - with Evex.w
63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
64 8, 16, 32, // EVEX_HV(0)
65 4, 4, 4, // EVEX_HV(1) - with Evex.b
66 // -----------------Table 4.6 -------------------- //
67 16, 32, 64, // EVEX_FVM(0)
68 1, 1, 1, // EVEX_T1S(0)
69 2, 2, 2, // EVEX_T1S(1)
70 4, 4, 4, // EVEX_T1S(2)
71 8, 8, 8, // EVEX_T1S(3)
72 4, 4, 4, // EVEX_T1F(0)
73 8, 8, 8, // EVEX_T1F(1)
74 8, 8, 8, // EVEX_T2(0)
75 0, 16, 16, // EVEX_T2(1)
76 0, 16, 16, // EVEX_T4(0)
77 0, 0, 32, // EVEX_T4(1)
78 0, 0, 32, // EVEX_T8(0)
79 8, 16, 32, // EVEX_HVM(0)
80 4, 8, 16, // EVEX_QVM(0)
81 2, 4, 8, // EVEX_OVM(0)
82 16, 16, 16, // EVEX_M128(0)
83 8, 32, 64, // EVEX_DUP(0)
84 0, 0, 0 // EVEX_NTUP
85 };
86
87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
88 _is_lval = false;
89 _target = target;
90 switch (rtype) {
91 case relocInfo::oop_type:
92 case relocInfo::metadata_type:
93 // Oops are a special case. Normally they would be their own section
94 // but in cases like icBuffer they are literals in the code stream that
95 // we don't have a section for. We use none so that we get a literal address
96 // which is always patchable.
97 break;
98 case relocInfo::external_word_type:
99 _rspec = external_word_Relocation::spec(target);
100 break;
101 case relocInfo::internal_word_type:
102 _rspec = internal_word_Relocation::spec(target);
103 break;
104 case relocInfo::opt_virtual_call_type:
105 _rspec = opt_virtual_call_Relocation::spec();
106 break;
107 case relocInfo::static_call_type:
108 _rspec = static_call_Relocation::spec();
109 break;
110 case relocInfo::runtime_call_type:
111 _rspec = runtime_call_Relocation::spec();
112 break;
113 case relocInfo::poll_type:
114 case relocInfo::poll_return_type:
115 _rspec = Relocation::spec_simple(rtype);
116 break;
117 case relocInfo::none:
118 break;
119 default:
120 ShouldNotReachHere();
121 break;
122 }
123 }
124
125 // Implementation of Address
126
127 #ifdef _LP64
128
129 Address Address::make_array(ArrayAddress adr) {
130 // Not implementable on 64bit machines
131 // Should have been handled higher up the call chain.
132 ShouldNotReachHere();
133 return Address();
134 }
135
136 // exceedingly dangerous constructor
137 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
138 _base = noreg;
139 _index = noreg;
140 _scale = no_scale;
141 _disp = disp;
142 switch (rtype) {
143 case relocInfo::external_word_type:
144 _rspec = external_word_Relocation::spec(loc);
145 break;
146 case relocInfo::internal_word_type:
147 _rspec = internal_word_Relocation::spec(loc);
148 break;
149 case relocInfo::runtime_call_type:
150 // HMM
151 _rspec = runtime_call_Relocation::spec();
152 break;
153 case relocInfo::poll_type:
154 case relocInfo::poll_return_type:
155 _rspec = Relocation::spec_simple(rtype);
156 break;
157 case relocInfo::none:
158 break;
159 default:
160 ShouldNotReachHere();
161 }
162 }
163 #else // LP64
164
165 Address Address::make_array(ArrayAddress adr) {
166 AddressLiteral base = adr.base();
167 Address index = adr.index();
168 assert(index._disp == 0, "must not have disp"); // maybe it can?
169 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
170 array._rspec = base._rspec;
171 return array;
172 }
173
174 // exceedingly dangerous constructor
175 Address::Address(address loc, RelocationHolder spec) {
176 _base = noreg;
177 _index = noreg;
178 _scale = no_scale;
179 _disp = (intptr_t) loc;
180 _rspec = spec;
181 }
182
183 #endif // _LP64
184
185
186
187 // Convert the raw encoding form into the form expected by the constructor for
188 // Address. An index of 4 (rsp) corresponds to having no index, so convert
189 // that to noreg for the Address constructor.
190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
191 RelocationHolder rspec;
192 if (disp_reloc != relocInfo::none) {
193 rspec = Relocation::spec_simple(disp_reloc);
194 }
195 bool valid_index = index != rsp->encoding();
196 if (valid_index) {
197 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
198 madr._rspec = rspec;
199 return madr;
200 } else {
201 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
202 madr._rspec = rspec;
203 return madr;
204 }
205 }
206
207 // Implementation of Assembler
208
209 int AbstractAssembler::code_fill_byte() {
210 return (u_char)'\xF4'; // hlt
211 }
212
213 // make this go away someday
214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
215 if (rtype == relocInfo::none)
216 emit_int32(data);
217 else
218 emit_data(data, Relocation::spec_simple(rtype), format);
219 }
220
221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
222 assert(imm_operand == 0, "default format must be immediate in this file");
223 assert(inst_mark() != NULL, "must be inside InstructionMark");
224 if (rspec.type() != relocInfo::none) {
225 #ifdef ASSERT
226 check_relocation(rspec, format);
227 #endif
228 // Do not use AbstractAssembler::relocate, which is not intended for
229 // embedded words. Instead, relocate to the enclosing instruction.
230
231 // hack. call32 is too wide for mask so use disp32
232 if (format == call32_operand)
233 code_section()->relocate(inst_mark(), rspec, disp32_operand);
234 else
235 code_section()->relocate(inst_mark(), rspec, format);
236 }
237 emit_int32(data);
238 }
239
240 static int encode(Register r) {
241 int enc = r->encoding();
242 if (enc >= 8) {
243 enc -= 8;
244 }
245 return enc;
246 }
247
248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
249 assert(dst->has_byte_register(), "must have byte register");
250 assert(isByte(op1) && isByte(op2), "wrong opcode");
251 assert(isByte(imm8), "not a byte");
252 assert((op1 & 0x01) == 0, "should be 8bit operation");
253 emit_int8(op1);
254 emit_int8(op2 | encode(dst));
255 emit_int8(imm8);
256 }
257
258
259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
260 assert(isByte(op1) && isByte(op2), "wrong opcode");
261 assert((op1 & 0x01) == 1, "should be 32bit operation");
262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
263 if (is8bit(imm32)) {
264 emit_int8(op1 | 0x02); // set sign bit
265 emit_int8(op2 | encode(dst));
266 emit_int8(imm32 & 0xFF);
267 } else {
268 emit_int8(op1);
269 emit_int8(op2 | encode(dst));
270 emit_int32(imm32);
271 }
272 }
273
274 // Force generation of a 4 byte immediate value even if it fits into 8bit
275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
276 assert(isByte(op1) && isByte(op2), "wrong opcode");
277 assert((op1 & 0x01) == 1, "should be 32bit operation");
278 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
279 emit_int8(op1);
280 emit_int8(op2 | encode(dst));
281 emit_int32(imm32);
282 }
283
284 // immediate-to-memory forms
285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
286 assert((op1 & 0x01) == 1, "should be 32bit operation");
287 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
288 if (is8bit(imm32)) {
289 emit_int8(op1 | 0x02); // set sign bit
290 emit_operand(rm, adr, 1);
291 emit_int8(imm32 & 0xFF);
292 } else {
293 emit_int8(op1);
294 emit_operand(rm, adr, 4);
295 emit_int32(imm32);
296 }
297 }
298
299
300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
301 assert(isByte(op1) && isByte(op2), "wrong opcode");
302 emit_int8(op1);
303 emit_int8(op2 | encode(dst) << 3 | encode(src));
304 }
305
306
307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
309 int mod_idx = 0;
310 // We will test if the displacement fits the compressed format and if so
311 // apply the compression to the displacment iff the result is8bit.
312 if (VM_Version::supports_evex() && is_evex_inst) {
313 switch (cur_tuple_type) {
314 case EVEX_FV:
315 if ((cur_encoding & VEX_W) == VEX_W) {
316 mod_idx += 2 + ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
317 } else {
318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
319 }
320 break;
321
322 case EVEX_HV:
323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
324 break;
325
326 case EVEX_FVM:
327 break;
328
329 case EVEX_T1S:
330 switch (in_size_in_bits) {
331 case EVEX_8bit:
332 break;
333
334 case EVEX_16bit:
335 mod_idx = 1;
336 break;
337
338 case EVEX_32bit:
339 mod_idx = 2;
340 break;
341
342 case EVEX_64bit:
343 mod_idx = 3;
344 break;
345 }
346 break;
347
348 case EVEX_T1F:
349 case EVEX_T2:
350 case EVEX_T4:
351 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
352 break;
353
354 case EVEX_T8:
355 break;
356
357 case EVEX_HVM:
358 break;
359
360 case EVEX_QVM:
361 break;
362
363 case EVEX_OVM:
364 break;
365
366 case EVEX_M128:
367 break;
368
369 case EVEX_DUP:
370 break;
371
372 default:
373 assert(0, "no valid evex tuple_table entry");
374 break;
375 }
376
377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
379 if ((disp % disp_factor) == 0) {
380 int new_disp = disp / disp_factor;
381 if ((-0x80 <= new_disp && new_disp < 0x80)) {
382 disp = new_disp;
383 }
384 } else {
385 return false;
386 }
387 }
388 }
389 return (-0x80 <= disp && disp < 0x80);
390 }
391
392
393 bool Assembler::emit_compressed_disp_byte(int &disp) {
394 int mod_idx = 0;
395 // We will test if the displacement fits the compressed format and if so
396 // apply the compression to the displacment iff the result is8bit.
397 if (VM_Version::supports_evex() && is_evex_instruction) {
398 switch (tuple_type) {
399 case EVEX_FV:
400 if ((evex_encoding & VEX_W) == VEX_W) {
401 mod_idx += 2 + ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
402 } else {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
404 }
405 break;
406
407 case EVEX_HV:
408 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
409 break;
410
411 case EVEX_FVM:
412 break;
413
414 case EVEX_T1S:
415 switch (input_size_in_bits) {
416 case EVEX_8bit:
417 break;
418
419 case EVEX_16bit:
420 mod_idx = 1;
421 break;
422
423 case EVEX_32bit:
424 mod_idx = 2;
425 break;
426
427 case EVEX_64bit:
428 mod_idx = 3;
429 break;
430 }
431 break;
432
433 case EVEX_T1F:
434 case EVEX_T2:
435 case EVEX_T4:
436 mod_idx = (input_size_in_bits == EVEX_64bit) ? 1 : 0;
437 break;
438
439 case EVEX_T8:
440 break;
441
442 case EVEX_HVM:
443 break;
444
445 case EVEX_QVM:
446 break;
447
448 case EVEX_OVM:
449 break;
450
451 case EVEX_M128:
452 break;
453
454 case EVEX_DUP:
455 break;
456
457 default:
458 assert(0, "no valid evex tuple_table entry");
459 break;
460 }
461
462 if (avx_vector_len >= AVX_128bit && avx_vector_len <= AVX_512bit) {
463 int disp_factor = tuple_table[tuple_type + mod_idx][avx_vector_len];
464 if ((disp % disp_factor) == 0) {
465 int new_disp = disp / disp_factor;
466 if (is8bit(new_disp)) {
467 disp = new_disp;
468 }
469 } else {
470 return false;
471 }
472 }
473 }
474 return is8bit(disp);
475 }
476
477
478 void Assembler::emit_operand(Register reg, Register base, Register index,
479 Address::ScaleFactor scale, int disp,
480 RelocationHolder const& rspec,
481 int rip_relative_correction) {
482 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
483
484 // Encode the registers as needed in the fields they are used in
485
486 int regenc = encode(reg) << 3;
487 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
488 int baseenc = base->is_valid() ? encode(base) : 0;
489
490 if (base->is_valid()) {
491 if (index->is_valid()) {
492 assert(scale != Address::no_scale, "inconsistent address");
493 // [base + index*scale + disp]
494 if (disp == 0 && rtype == relocInfo::none &&
495 base != rbp LP64_ONLY(&& base != r13)) {
496 // [base + index*scale]
497 // [00 reg 100][ss index base]
498 assert(index != rsp, "illegal addressing mode");
499 emit_int8(0x04 | regenc);
500 emit_int8(scale << 6 | indexenc | baseenc);
501 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
502 // [base + index*scale + imm8]
503 // [01 reg 100][ss index base] imm8
504 assert(index != rsp, "illegal addressing mode");
505 emit_int8(0x44 | regenc);
506 emit_int8(scale << 6 | indexenc | baseenc);
507 emit_int8(disp & 0xFF);
508 } else {
509 // [base + index*scale + disp32]
510 // [10 reg 100][ss index base] disp32
511 assert(index != rsp, "illegal addressing mode");
512 emit_int8(0x84 | regenc);
513 emit_int8(scale << 6 | indexenc | baseenc);
514 emit_data(disp, rspec, disp32_operand);
515 }
516 } else if (base == rsp LP64_ONLY(|| base == r12)) {
517 // [rsp + disp]
518 if (disp == 0 && rtype == relocInfo::none) {
519 // [rsp]
520 // [00 reg 100][00 100 100]
521 emit_int8(0x04 | regenc);
522 emit_int8(0x24);
523 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
524 // [rsp + imm8]
525 // [01 reg 100][00 100 100] disp8
526 emit_int8(0x44 | regenc);
527 emit_int8(0x24);
528 emit_int8(disp & 0xFF);
529 } else {
530 // [rsp + imm32]
531 // [10 reg 100][00 100 100] disp32
532 emit_int8(0x84 | regenc);
533 emit_int8(0x24);
534 emit_data(disp, rspec, disp32_operand);
535 }
536 } else {
537 // [base + disp]
538 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
539 if (disp == 0 && rtype == relocInfo::none &&
540 base != rbp LP64_ONLY(&& base != r13)) {
541 // [base]
542 // [00 reg base]
543 emit_int8(0x00 | regenc | baseenc);
544 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
545 // [base + disp8]
546 // [01 reg base] disp8
547 emit_int8(0x40 | regenc | baseenc);
548 emit_int8(disp & 0xFF);
549 } else {
550 // [base + disp32]
551 // [10 reg base] disp32
552 emit_int8(0x80 | regenc | baseenc);
553 emit_data(disp, rspec, disp32_operand);
554 }
555 }
556 } else {
557 if (index->is_valid()) {
558 assert(scale != Address::no_scale, "inconsistent address");
559 // [index*scale + disp]
560 // [00 reg 100][ss index 101] disp32
561 assert(index != rsp, "illegal addressing mode");
562 emit_int8(0x04 | regenc);
563 emit_int8(scale << 6 | indexenc | 0x05);
564 emit_data(disp, rspec, disp32_operand);
565 } else if (rtype != relocInfo::none ) {
566 // [disp] (64bit) RIP-RELATIVE (32bit) abs
567 // [00 000 101] disp32
568
569 emit_int8(0x05 | regenc);
570 // Note that the RIP-rel. correction applies to the generated
571 // disp field, but _not_ to the target address in the rspec.
572
573 // disp was created by converting the target address minus the pc
574 // at the start of the instruction. That needs more correction here.
575 // intptr_t disp = target - next_ip;
576 assert(inst_mark() != NULL, "must be inside InstructionMark");
577 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
578 int64_t adjusted = disp;
579 // Do rip-rel adjustment for 64bit
580 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
581 assert(is_simm32(adjusted),
582 "must be 32bit offset (RIP relative address)");
583 emit_data((int32_t) adjusted, rspec, disp32_operand);
584
585 } else {
586 // 32bit never did this, did everything as the rip-rel/disp code above
587 // [disp] ABSOLUTE
588 // [00 reg 100][00 100 101] disp32
589 emit_int8(0x04 | regenc);
590 emit_int8(0x25);
591 emit_data(disp, rspec, disp32_operand);
592 }
593 }
594 is_evex_instruction = false;
595 }
596
597 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
598 Address::ScaleFactor scale, int disp,
599 RelocationHolder const& rspec) {
600 if (UseAVX > 2) {
601 int xreg_enc = reg->encoding();
602 if (xreg_enc > 15) {
603 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
604 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
605 return;
606 }
607 }
608 emit_operand((Register)reg, base, index, scale, disp, rspec);
609 }
610
611 // Secret local extension to Assembler::WhichOperand:
612 #define end_pc_operand (_WhichOperand_limit)
613
614 address Assembler::locate_operand(address inst, WhichOperand which) {
615 // Decode the given instruction, and return the address of
616 // an embedded 32-bit operand word.
617
618 // If "which" is disp32_operand, selects the displacement portion
619 // of an effective address specifier.
620 // If "which" is imm64_operand, selects the trailing immediate constant.
621 // If "which" is call32_operand, selects the displacement of a call or jump.
622 // Caller is responsible for ensuring that there is such an operand,
623 // and that it is 32/64 bits wide.
624
625 // If "which" is end_pc_operand, find the end of the instruction.
626
627 address ip = inst;
628 bool is_64bit = false;
629
630 debug_only(bool has_disp32 = false);
631 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
632
633 again_after_prefix:
634 switch (0xFF & *ip++) {
635
636 // These convenience macros generate groups of "case" labels for the switch.
637 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
638 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
639 case (x)+4: case (x)+5: case (x)+6: case (x)+7
640 #define REP16(x) REP8((x)+0): \
641 case REP8((x)+8)
642
643 case CS_segment:
644 case SS_segment:
645 case DS_segment:
646 case ES_segment:
647 case FS_segment:
648 case GS_segment:
649 // Seems dubious
650 LP64_ONLY(assert(false, "shouldn't have that prefix"));
651 assert(ip == inst+1, "only one prefix allowed");
652 goto again_after_prefix;
653
654 case 0x67:
655 case REX:
656 case REX_B:
657 case REX_X:
658 case REX_XB:
659 case REX_R:
660 case REX_RB:
661 case REX_RX:
662 case REX_RXB:
663 NOT_LP64(assert(false, "64bit prefixes"));
664 goto again_after_prefix;
665
666 case REX_W:
667 case REX_WB:
668 case REX_WX:
669 case REX_WXB:
670 case REX_WR:
671 case REX_WRB:
672 case REX_WRX:
673 case REX_WRXB:
674 NOT_LP64(assert(false, "64bit prefixes"));
675 is_64bit = true;
676 goto again_after_prefix;
677
678 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
679 case 0x88: // movb a, r
680 case 0x89: // movl a, r
681 case 0x8A: // movb r, a
682 case 0x8B: // movl r, a
683 case 0x8F: // popl a
684 debug_only(has_disp32 = true);
685 break;
686
687 case 0x68: // pushq #32
688 if (which == end_pc_operand) {
689 return ip + 4;
690 }
691 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
692 return ip; // not produced by emit_operand
693
694 case 0x66: // movw ... (size prefix)
695 again_after_size_prefix2:
696 switch (0xFF & *ip++) {
697 case REX:
698 case REX_B:
699 case REX_X:
700 case REX_XB:
701 case REX_R:
702 case REX_RB:
703 case REX_RX:
704 case REX_RXB:
705 case REX_W:
706 case REX_WB:
707 case REX_WX:
708 case REX_WXB:
709 case REX_WR:
710 case REX_WRB:
711 case REX_WRX:
712 case REX_WRXB:
713 NOT_LP64(assert(false, "64bit prefix found"));
714 goto again_after_size_prefix2;
715 case 0x8B: // movw r, a
716 case 0x89: // movw a, r
717 debug_only(has_disp32 = true);
718 break;
719 case 0xC7: // movw a, #16
720 debug_only(has_disp32 = true);
721 tail_size = 2; // the imm16
722 break;
723 case 0x0F: // several SSE/SSE2 variants
724 ip--; // reparse the 0x0F
725 goto again_after_prefix;
726 default:
727 ShouldNotReachHere();
728 }
729 break;
730
731 case REP8(0xB8): // movl/q r, #32/#64(oop?)
732 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
733 // these asserts are somewhat nonsensical
734 #ifndef _LP64
735 assert(which == imm_operand || which == disp32_operand,
736 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)));
737 #else
738 assert((which == call32_operand || which == imm_operand) && is_64bit ||
739 which == narrow_oop_operand && !is_64bit,
740 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)));
741 #endif // _LP64
742 return ip;
743
744 case 0x69: // imul r, a, #32
745 case 0xC7: // movl a, #32(oop?)
746 tail_size = 4;
747 debug_only(has_disp32 = true); // has both kinds of operands!
748 break;
749
750 case 0x0F: // movx..., etc.
751 switch (0xFF & *ip++) {
752 case 0x3A: // pcmpestri
753 tail_size = 1;
754 case 0x38: // ptest, pmovzxbw
755 ip++; // skip opcode
756 debug_only(has_disp32 = true); // has both kinds of operands!
757 break;
758
759 case 0x70: // pshufd r, r/a, #8
760 debug_only(has_disp32 = true); // has both kinds of operands!
761 case 0x73: // psrldq r, #8
762 tail_size = 1;
763 break;
764
765 case 0x12: // movlps
766 case 0x28: // movaps
767 case 0x2E: // ucomiss
768 case 0x2F: // comiss
769 case 0x54: // andps
770 case 0x55: // andnps
771 case 0x56: // orps
772 case 0x57: // xorps
773 case 0x6E: // movd
774 case 0x7E: // movd
775 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
776 debug_only(has_disp32 = true);
777 break;
778
779 case 0xAD: // shrd r, a, %cl
780 case 0xAF: // imul r, a
781 case 0xBE: // movsbl r, a (movsxb)
782 case 0xBF: // movswl r, a (movsxw)
783 case 0xB6: // movzbl r, a (movzxb)
784 case 0xB7: // movzwl r, a (movzxw)
785 case REP16(0x40): // cmovl cc, r, a
786 case 0xB0: // cmpxchgb
787 case 0xB1: // cmpxchg
788 case 0xC1: // xaddl
789 case 0xC7: // cmpxchg8
790 case REP16(0x90): // setcc a
791 debug_only(has_disp32 = true);
792 // fall out of the switch to decode the address
793 break;
794
795 case 0xC4: // pinsrw r, a, #8
796 debug_only(has_disp32 = true);
797 case 0xC5: // pextrw r, r, #8
798 tail_size = 1; // the imm8
799 break;
800
801 case 0xAC: // shrd r, a, #8
802 debug_only(has_disp32 = true);
803 tail_size = 1; // the imm8
804 break;
805
806 case REP16(0x80): // jcc rdisp32
807 if (which == end_pc_operand) return ip + 4;
808 assert(which == call32_operand, "jcc has no disp32 or imm");
809 return ip;
810 default:
811 ShouldNotReachHere();
812 }
813 break;
814
815 case 0x81: // addl a, #32; addl r, #32
816 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
817 // on 32bit in the case of cmpl, the imm might be an oop
818 tail_size = 4;
819 debug_only(has_disp32 = true); // has both kinds of operands!
820 break;
821
822 case 0x83: // addl a, #8; addl r, #8
823 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
824 debug_only(has_disp32 = true); // has both kinds of operands!
825 tail_size = 1;
826 break;
827
828 case 0x9B:
829 switch (0xFF & *ip++) {
830 case 0xD9: // fnstcw a
831 debug_only(has_disp32 = true);
832 break;
833 default:
834 ShouldNotReachHere();
835 }
836 break;
837
838 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
839 case REP4(0x10): // adc...
840 case REP4(0x20): // and...
841 case REP4(0x30): // xor...
842 case REP4(0x08): // or...
843 case REP4(0x18): // sbb...
844 case REP4(0x28): // sub...
845 case 0xF7: // mull a
846 case 0x8D: // lea r, a
847 case 0x87: // xchg r, a
848 case REP4(0x38): // cmp...
849 case 0x85: // test r, a
850 debug_only(has_disp32 = true); // has both kinds of operands!
851 break;
852
853 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
854 case 0xC6: // movb a, #8
855 case 0x80: // cmpb a, #8
856 case 0x6B: // imul r, a, #8
857 debug_only(has_disp32 = true); // has both kinds of operands!
858 tail_size = 1; // the imm8
859 break;
860
861 case 0xC4: // VEX_3bytes
862 case 0xC5: // VEX_2bytes
863 assert((UseAVX > 0), "shouldn't have VEX prefix");
864 assert(ip == inst+1, "no prefixes allowed");
865 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
866 // but they have prefix 0x0F and processed when 0x0F processed above.
867 //
868 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
869 // instructions (these instructions are not supported in 64-bit mode).
870 // To distinguish them bits [7:6] are set in the VEX second byte since
871 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
872 // those VEX bits REX and vvvv bits are inverted.
873 //
874 // Fortunately C2 doesn't generate these instructions so we don't need
875 // to check for them in product version.
876
877 // Check second byte
878 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
879
880 // First byte
881 if ((0xFF & *inst) == VEX_3bytes) {
882 ip++; // third byte
883 is_64bit = ((VEX_W & *ip) == VEX_W);
884 }
885 ip++; // opcode
886 // To find the end of instruction (which == end_pc_operand).
887 switch (0xFF & *ip) {
888 case 0x61: // pcmpestri r, r/a, #8
889 case 0x70: // pshufd r, r/a, #8
890 case 0x73: // psrldq r, #8
891 tail_size = 1; // the imm8
892 break;
893 default:
894 break;
895 }
896 ip++; // skip opcode
897 debug_only(has_disp32 = true); // has both kinds of operands!
898 break;
899
900 case 0x62: // EVEX_4bytes
901 assert((UseAVX > 0), "shouldn't have EVEX prefix");
902 assert(ip == inst+1, "no prefixes allowed");
903 // no EVEX collisions, all instructions that have 0x62 opcodes
904 // have EVEX versions and are subopcodes of 0x66
905 ip++; // skip P0 and exmaine W in P1
906 is_64bit = ((VEX_W & *ip) == VEX_W);
907 ip++; // move to P2
908 ip++; // skip P2, move to opcode
909 // To find the end of instruction (which == end_pc_operand).
910 switch (0xFF & *ip) {
911 case 0x61: // pcmpestri r, r/a, #8
912 case 0x70: // pshufd r, r/a, #8
913 case 0x73: // psrldq r, #8
914 tail_size = 1; // the imm8
915 break;
916 default:
917 break;
918 }
919 ip++; // skip opcode
920 debug_only(has_disp32 = true); // has both kinds of operands!
921 break;
922
923 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
924 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
925 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
926 case 0xDD: // fld_d a; fst_d a; fstp_d a
927 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
928 case 0xDF: // fild_d a; fistp_d a
929 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
930 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
931 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
932 debug_only(has_disp32 = true);
933 break;
934
935 case 0xE8: // call rdisp32
936 case 0xE9: // jmp rdisp32
937 if (which == end_pc_operand) return ip + 4;
938 assert(which == call32_operand, "call has no disp32 or imm");
939 return ip;
940
941 case 0xF0: // Lock
942 assert(os::is_MP(), "only on MP");
943 goto again_after_prefix;
944
945 case 0xF3: // For SSE
946 case 0xF2: // For SSE2
947 switch (0xFF & *ip++) {
948 case REX:
949 case REX_B:
950 case REX_X:
951 case REX_XB:
952 case REX_R:
953 case REX_RB:
954 case REX_RX:
955 case REX_RXB:
956 case REX_W:
957 case REX_WB:
958 case REX_WX:
959 case REX_WXB:
960 case REX_WR:
961 case REX_WRB:
962 case REX_WRX:
963 case REX_WRXB:
964 NOT_LP64(assert(false, "found 64bit prefix"));
965 ip++;
966 default:
967 ip++;
968 }
969 debug_only(has_disp32 = true); // has both kinds of operands!
970 break;
971
972 default:
973 ShouldNotReachHere();
974
975 #undef REP8
976 #undef REP16
977 }
978
979 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
980 #ifdef _LP64
981 assert(which != imm_operand, "instruction is not a movq reg, imm64");
982 #else
983 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
984 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
985 #endif // LP64
986 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
987
988 // parse the output of emit_operand
989 int op2 = 0xFF & *ip++;
990 int base = op2 & 0x07;
991 int op3 = -1;
992 const int b100 = 4;
993 const int b101 = 5;
994 if (base == b100 && (op2 >> 6) != 3) {
995 op3 = 0xFF & *ip++;
996 base = op3 & 0x07; // refetch the base
997 }
998 // now ip points at the disp (if any)
999
1000 switch (op2 >> 6) {
1001 case 0:
1002 // [00 reg 100][ss index base]
1003 // [00 reg 100][00 100 esp]
1004 // [00 reg base]
1005 // [00 reg 100][ss index 101][disp32]
1006 // [00 reg 101] [disp32]
1007
1008 if (base == b101) {
1009 if (which == disp32_operand)
1010 return ip; // caller wants the disp32
1011 ip += 4; // skip the disp32
1012 }
1013 break;
1014
1015 case 1:
1016 // [01 reg 100][ss index base][disp8]
1017 // [01 reg 100][00 100 esp][disp8]
1018 // [01 reg base] [disp8]
1019 ip += 1; // skip the disp8
1020 break;
1021
1022 case 2:
1023 // [10 reg 100][ss index base][disp32]
1024 // [10 reg 100][00 100 esp][disp32]
1025 // [10 reg base] [disp32]
1026 if (which == disp32_operand)
1027 return ip; // caller wants the disp32
1028 ip += 4; // skip the disp32
1029 break;
1030
1031 case 3:
1032 // [11 reg base] (not a memory addressing mode)
1033 break;
1034 }
1035
1036 if (which == end_pc_operand) {
1037 return ip + tail_size;
1038 }
1039
1040 #ifdef _LP64
1041 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1042 #else
1043 assert(which == imm_operand, "instruction has only an imm field");
1044 #endif // LP64
1045 return ip;
1046 }
1047
1048 address Assembler::locate_next_instruction(address inst) {
1049 // Secretly share code with locate_operand:
1050 return locate_operand(inst, end_pc_operand);
1051 }
1052
1053
1054 #ifdef ASSERT
1055 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1056 address inst = inst_mark();
1057 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1058 address opnd;
1059
1060 Relocation* r = rspec.reloc();
1061 if (r->type() == relocInfo::none) {
1062 return;
1063 } else if (r->is_call() || format == call32_operand) {
1064 // assert(format == imm32_operand, "cannot specify a nonzero format");
1065 opnd = locate_operand(inst, call32_operand);
1066 } else if (r->is_data()) {
1067 assert(format == imm_operand || format == disp32_operand
1068 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1069 opnd = locate_operand(inst, (WhichOperand)format);
1070 } else {
1071 assert(format == imm_operand, "cannot specify a format");
1072 return;
1073 }
1074 assert(opnd == pc(), "must put operand where relocs can find it");
1075 }
1076 #endif // ASSERT
1077
1078 void Assembler::emit_operand32(Register reg, Address adr) {
1079 assert(reg->encoding() < 8, "no extended registers");
1080 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1081 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1082 adr._rspec);
1083 }
1084
1085 void Assembler::emit_operand(Register reg, Address adr,
1086 int rip_relative_correction) {
1087 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1088 adr._rspec,
1089 rip_relative_correction);
1090 }
1091
1092 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1093 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1094 adr._rspec);
1095 }
1096
1097 // MMX operations
1098 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1099 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1100 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1101 }
1102
1103 // work around gcc (3.2.1-7a) bug
1104 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1105 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1106 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1107 }
1108
1109
1110 void Assembler::emit_farith(int b1, int b2, int i) {
1111 assert(isByte(b1) && isByte(b2), "wrong opcode");
1112 assert(0 <= i && i < 8, "illegal stack offset");
1113 emit_int8(b1);
1114 emit_int8(b2 + i);
1115 }
1116
1117
1118 // Now the Assembler instructions (identical for 32/64 bits)
1119
1120 void Assembler::adcl(Address dst, int32_t imm32) {
1121 InstructionMark im(this);
1122 prefix(dst);
1123 emit_arith_operand(0x81, rdx, dst, imm32);
1124 }
1125
1126 void Assembler::adcl(Address dst, Register src) {
1127 InstructionMark im(this);
1128 prefix(dst, src);
1129 emit_int8(0x11);
1130 emit_operand(src, dst);
1131 }
1132
1133 void Assembler::adcl(Register dst, int32_t imm32) {
1134 prefix(dst);
1135 emit_arith(0x81, 0xD0, dst, imm32);
1136 }
1137
1138 void Assembler::adcl(Register dst, Address src) {
1139 InstructionMark im(this);
1140 prefix(src, dst);
1141 emit_int8(0x13);
1142 emit_operand(dst, src);
1143 }
1144
1145 void Assembler::adcl(Register dst, Register src) {
1146 (void) prefix_and_encode(dst->encoding(), src->encoding());
1147 emit_arith(0x13, 0xC0, dst, src);
1148 }
1149
1150 void Assembler::addl(Address dst, int32_t imm32) {
1151 InstructionMark im(this);
1152 prefix(dst);
1153 emit_arith_operand(0x81, rax, dst, imm32);
1154 }
1155
1156 void Assembler::addl(Address dst, Register src) {
1157 InstructionMark im(this);
1158 prefix(dst, src);
1159 emit_int8(0x01);
1160 emit_operand(src, dst);
1161 }
1162
1163 void Assembler::addl(Register dst, int32_t imm32) {
1164 prefix(dst);
1165 emit_arith(0x81, 0xC0, dst, imm32);
1166 }
1167
1168 void Assembler::addl(Register dst, Address src) {
1169 InstructionMark im(this);
1170 prefix(src, dst);
1171 emit_int8(0x03);
1172 emit_operand(dst, src);
1173 }
1174
1175 void Assembler::addl(Register dst, Register src) {
1176 (void) prefix_and_encode(dst->encoding(), src->encoding());
1177 emit_arith(0x03, 0xC0, dst, src);
1178 }
1179
1180 void Assembler::addr_nop_4() {
1181 assert(UseAddressNop, "no CPU support");
1182 // 4 bytes: NOP DWORD PTR [EAX+0]
1183 emit_int8(0x0F);
1184 emit_int8(0x1F);
1185 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1186 emit_int8(0); // 8-bits offset (1 byte)
1187 }
1188
1189 void Assembler::addr_nop_5() {
1190 assert(UseAddressNop, "no CPU support");
1191 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1192 emit_int8(0x0F);
1193 emit_int8(0x1F);
1194 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1195 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1196 emit_int8(0); // 8-bits offset (1 byte)
1197 }
1198
1199 void Assembler::addr_nop_7() {
1200 assert(UseAddressNop, "no CPU support");
1201 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1202 emit_int8(0x0F);
1203 emit_int8(0x1F);
1204 emit_int8((unsigned char)0x80);
1205 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1206 emit_int32(0); // 32-bits offset (4 bytes)
1207 }
1208
1209 void Assembler::addr_nop_8() {
1210 assert(UseAddressNop, "no CPU support");
1211 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1212 emit_int8(0x0F);
1213 emit_int8(0x1F);
1214 emit_int8((unsigned char)0x84);
1215 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1216 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1217 emit_int32(0); // 32-bits offset (4 bytes)
1218 }
1219
1220 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1221 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1222 if (VM_Version::supports_evex()) {
1223 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_F2);
1224 } else {
1225 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
1226 }
1227 }
1228
1229 void Assembler::addsd(XMMRegister dst, Address src) {
1230 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1231 if (VM_Version::supports_evex()) {
1232 tuple_type = EVEX_T1S;
1233 input_size_in_bits = EVEX_64bit;
1234 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_F2);
1235 } else {
1236 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
1237 }
1238 }
1239
1240 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1241 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1242 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1243 }
1244
1245 void Assembler::addss(XMMRegister dst, Address src) {
1246 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1247 if (VM_Version::supports_evex()) {
1248 tuple_type = EVEX_T1S;
1249 input_size_in_bits = EVEX_32bit;
1250 }
1251 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1252 }
1253
1254 void Assembler::aesdec(XMMRegister dst, Address src) {
1255 assert(VM_Version::supports_aes(), "");
1256 InstructionMark im(this);
1257 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1258 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1259 emit_int8((unsigned char)0xDE);
1260 emit_operand(dst, src);
1261 }
1262
1263 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1264 assert(VM_Version::supports_aes(), "");
1265 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1266 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1267 emit_int8((unsigned char)0xDE);
1268 emit_int8(0xC0 | encode);
1269 }
1270
1271 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1272 assert(VM_Version::supports_aes(), "");
1273 InstructionMark im(this);
1274 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1275 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1276 emit_int8((unsigned char)0xDF);
1277 emit_operand(dst, src);
1278 }
1279
1280 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1281 assert(VM_Version::supports_aes(), "");
1282 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1283 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1284 emit_int8((unsigned char)0xDF);
1285 emit_int8((unsigned char)(0xC0 | encode));
1286 }
1287
1288 void Assembler::aesenc(XMMRegister dst, Address src) {
1289 assert(VM_Version::supports_aes(), "");
1290 InstructionMark im(this);
1291 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1292 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1293 emit_int8((unsigned char)0xDC);
1294 emit_operand(dst, src);
1295 }
1296
1297 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1298 assert(VM_Version::supports_aes(), "");
1299 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1300 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1301 emit_int8((unsigned char)0xDC);
1302 emit_int8(0xC0 | encode);
1303 }
1304
1305 void Assembler::aesenclast(XMMRegister dst, Address src) {
1306 assert(VM_Version::supports_aes(), "");
1307 InstructionMark im(this);
1308 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1309 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1310 emit_int8((unsigned char)0xDD);
1311 emit_operand(dst, src);
1312 }
1313
1314 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1315 assert(VM_Version::supports_aes(), "");
1316 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1317 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1318 emit_int8((unsigned char)0xDD);
1319 emit_int8((unsigned char)(0xC0 | encode));
1320 }
1321
1322
1323 void Assembler::andl(Address dst, int32_t imm32) {
1324 InstructionMark im(this);
1325 prefix(dst);
1326 emit_int8((unsigned char)0x81);
1327 emit_operand(rsp, dst, 4);
1328 emit_int32(imm32);
1329 }
1330
1331 void Assembler::andl(Register dst, int32_t imm32) {
1332 prefix(dst);
1333 emit_arith(0x81, 0xE0, dst, imm32);
1334 }
1335
1336 void Assembler::andl(Register dst, Address src) {
1337 InstructionMark im(this);
1338 prefix(src, dst);
1339 emit_int8(0x23);
1340 emit_operand(dst, src);
1341 }
1342
1343 void Assembler::andl(Register dst, Register src) {
1344 (void) prefix_and_encode(dst->encoding(), src->encoding());
1345 emit_arith(0x23, 0xC0, dst, src);
1346 }
1347
1348 void Assembler::andnl(Register dst, Register src1, Register src2) {
1349 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1350 int encode = vex_prefix_0F38_and_encode(dst, src1, src2, false);
1351 emit_int8((unsigned char)0xF2);
1352 emit_int8((unsigned char)(0xC0 | encode));
1353 }
1354
1355 void Assembler::andnl(Register dst, Register src1, Address src2) {
1356 InstructionMark im(this);
1357 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1358 vex_prefix_0F38(dst, src1, src2, false);
1359 emit_int8((unsigned char)0xF2);
1360 emit_operand(dst, src2);
1361 }
1362
1363 void Assembler::bsfl(Register dst, Register src) {
1364 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1365 emit_int8(0x0F);
1366 emit_int8((unsigned char)0xBC);
1367 emit_int8((unsigned char)(0xC0 | encode));
1368 }
1369
1370 void Assembler::bsrl(Register dst, Register src) {
1371 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1372 emit_int8(0x0F);
1373 emit_int8((unsigned char)0xBD);
1374 emit_int8((unsigned char)(0xC0 | encode));
1375 }
1376
1377 void Assembler::bswapl(Register reg) { // bswap
1378 int encode = prefix_and_encode(reg->encoding());
1379 emit_int8(0x0F);
1380 emit_int8((unsigned char)(0xC8 | encode));
1381 }
1382
1383 void Assembler::blsil(Register dst, Register src) {
1384 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1385 int encode = vex_prefix_0F38_and_encode(rbx, dst, src, false);
1386 emit_int8((unsigned char)0xF3);
1387 emit_int8((unsigned char)(0xC0 | encode));
1388 }
1389
1390 void Assembler::blsil(Register dst, Address src) {
1391 InstructionMark im(this);
1392 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1393 vex_prefix_0F38(rbx, dst, src, false);
1394 emit_int8((unsigned char)0xF3);
1395 emit_operand(rbx, src);
1396 }
1397
1398 void Assembler::blsmskl(Register dst, Register src) {
1399 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1400 int encode = vex_prefix_0F38_and_encode(rdx, dst, src, false);
1401 emit_int8((unsigned char)0xF3);
1402 emit_int8((unsigned char)(0xC0 | encode));
1403 }
1404
1405 void Assembler::blsmskl(Register dst, Address src) {
1406 InstructionMark im(this);
1407 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1408 vex_prefix_0F38(rdx, dst, src, false);
1409 emit_int8((unsigned char)0xF3);
1410 emit_operand(rdx, src);
1411 }
1412
1413 void Assembler::blsrl(Register dst, Register src) {
1414 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1415 int encode = vex_prefix_0F38_and_encode(rcx, dst, src, false);
1416 emit_int8((unsigned char)0xF3);
1417 emit_int8((unsigned char)(0xC0 | encode));
1418 }
1419
1420 void Assembler::blsrl(Register dst, Address src) {
1421 InstructionMark im(this);
1422 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1423 vex_prefix_0F38(rcx, dst, src, false);
1424 emit_int8((unsigned char)0xF3);
1425 emit_operand(rcx, src);
1426 }
1427
1428 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1429 // suspect disp32 is always good
1430 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1431
1432 if (L.is_bound()) {
1433 const int long_size = 5;
1434 int offs = (int)( target(L) - pc() );
1435 assert(offs <= 0, "assembler error");
1436 InstructionMark im(this);
1437 // 1110 1000 #32-bit disp
1438 emit_int8((unsigned char)0xE8);
1439 emit_data(offs - long_size, rtype, operand);
1440 } else {
1441 InstructionMark im(this);
1442 // 1110 1000 #32-bit disp
1443 L.add_patch_at(code(), locator());
1444
1445 emit_int8((unsigned char)0xE8);
1446 emit_data(int(0), rtype, operand);
1447 }
1448 }
1449
1450 void Assembler::call(Register dst) {
1451 int encode = prefix_and_encode(dst->encoding());
1452 emit_int8((unsigned char)0xFF);
1453 emit_int8((unsigned char)(0xD0 | encode));
1454 }
1455
1456
1457 void Assembler::call(Address adr) {
1458 InstructionMark im(this);
1459 prefix(adr);
1460 emit_int8((unsigned char)0xFF);
1461 emit_operand(rdx, adr);
1462 }
1463
1464 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1465 assert(entry != NULL, "call most probably wrong");
1466 InstructionMark im(this);
1467 emit_int8((unsigned char)0xE8);
1468 intptr_t disp = entry - (pc() + sizeof(int32_t));
1469 assert(is_simm32(disp), "must be 32bit offset (call2)");
1470 // Technically, should use call32_operand, but this format is
1471 // implied by the fact that we're emitting a call instruction.
1472
1473 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1474 emit_data((int) disp, rspec, operand);
1475 }
1476
1477 void Assembler::cdql() {
1478 emit_int8((unsigned char)0x99);
1479 }
1480
1481 void Assembler::cld() {
1482 emit_int8((unsigned char)0xFC);
1483 }
1484
1485 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1486 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1487 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1488 emit_int8(0x0F);
1489 emit_int8(0x40 | cc);
1490 emit_int8((unsigned char)(0xC0 | encode));
1491 }
1492
1493
1494 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1495 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1496 prefix(src, dst);
1497 emit_int8(0x0F);
1498 emit_int8(0x40 | cc);
1499 emit_operand(dst, src);
1500 }
1501
1502 void Assembler::cmpb(Address dst, int imm8) {
1503 InstructionMark im(this);
1504 prefix(dst);
1505 emit_int8((unsigned char)0x80);
1506 emit_operand(rdi, dst, 1);
1507 emit_int8(imm8);
1508 }
1509
1510 void Assembler::cmpl(Address dst, int32_t imm32) {
1511 InstructionMark im(this);
1512 prefix(dst);
1513 emit_int8((unsigned char)0x81);
1514 emit_operand(rdi, dst, 4);
1515 emit_int32(imm32);
1516 }
1517
1518 void Assembler::cmpl(Register dst, int32_t imm32) {
1519 prefix(dst);
1520 emit_arith(0x81, 0xF8, dst, imm32);
1521 }
1522
1523 void Assembler::cmpl(Register dst, Register src) {
1524 (void) prefix_and_encode(dst->encoding(), src->encoding());
1525 emit_arith(0x3B, 0xC0, dst, src);
1526 }
1527
1528
1529 void Assembler::cmpl(Register dst, Address src) {
1530 InstructionMark im(this);
1531 prefix(src, dst);
1532 emit_int8((unsigned char)0x3B);
1533 emit_operand(dst, src);
1534 }
1535
1536 void Assembler::cmpw(Address dst, int imm16) {
1537 InstructionMark im(this);
1538 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1539 emit_int8(0x66);
1540 emit_int8((unsigned char)0x81);
1541 emit_operand(rdi, dst, 2);
1542 emit_int16(imm16);
1543 }
1544
1545 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1546 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1547 // The ZF is set if the compared values were equal, and cleared otherwise.
1548 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1549 InstructionMark im(this);
1550 prefix(adr, reg);
1551 emit_int8(0x0F);
1552 emit_int8((unsigned char)0xB1);
1553 emit_operand(reg, adr);
1554 }
1555
1556 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1557 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1558 // The ZF is set if the compared values were equal, and cleared otherwise.
1559 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1560 InstructionMark im(this);
1561 prefix(adr, reg, true);
1562 emit_int8(0x0F);
1563 emit_int8((unsigned char)0xB0);
1564 emit_operand(reg, adr);
1565 }
1566
1567 void Assembler::comisd(XMMRegister dst, Address src) {
1568 // NOTE: dbx seems to decode this as comiss even though the
1569 // 0x66 is there. Strangly ucomisd comes out correct
1570 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1571 if (VM_Version::supports_evex()) {
1572 tuple_type = EVEX_T1S;
1573 input_size_in_bits = EVEX_64bit;
1574 emit_simd_arith_nonds_q(0x2F, dst, src, VEX_SIMD_66, true);
1575 } else {
1576 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1577 }
1578 }
1579
1580 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1581 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1582 if (VM_Version::supports_evex()) {
1583 emit_simd_arith_nonds_q(0x2F, dst, src, VEX_SIMD_66, true);
1584 } else {
1585 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1586 }
1587 }
1588
1589 void Assembler::comiss(XMMRegister dst, Address src) {
1590 if (VM_Version::supports_evex()) {
1591 tuple_type = EVEX_T1S;
1592 input_size_in_bits = EVEX_32bit;
1593 }
1594 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1595 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE, true);
1596 }
1597
1598 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1599 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1600 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE, true);
1601 }
1602
1603 void Assembler::cpuid() {
1604 emit_int8(0x0F);
1605 emit_int8((unsigned char)0xA2);
1606 }
1607
1608 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1609 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1610 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3);
1611 }
1612
1613 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1614 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1615 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE);
1616 }
1617
1618 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1619 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1620 if (VM_Version::supports_evex()) {
1621 emit_simd_arith_q(0x5A, dst, src, VEX_SIMD_F2);
1622 } else {
1623 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1624 }
1625 }
1626
1627 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1628 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1629 if (VM_Version::supports_evex()) {
1630 tuple_type = EVEX_T1F;
1631 input_size_in_bits = EVEX_64bit;
1632 emit_simd_arith_q(0x5A, dst, src, VEX_SIMD_F2);
1633 } else {
1634 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1635 }
1636 }
1637
1638 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1639 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1640 int encode = 0;
1641 if (VM_Version::supports_evex()) {
1642 encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2, true);
1643 } else {
1644 encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, false);
1645 }
1646 emit_int8(0x2A);
1647 emit_int8((unsigned char)(0xC0 | encode));
1648 }
1649
1650 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1651 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1652 if (VM_Version::supports_evex()) {
1653 tuple_type = EVEX_T1S;
1654 input_size_in_bits = EVEX_32bit;
1655 emit_simd_arith_q(0x2A, dst, src, VEX_SIMD_F2, true);
1656 } else {
1657 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2);
1658 }
1659 }
1660
1661 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1662 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1663 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, true);
1664 emit_int8(0x2A);
1665 emit_int8((unsigned char)(0xC0 | encode));
1666 }
1667
1668 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1669 if (VM_Version::supports_evex()) {
1670 tuple_type = EVEX_T1S;
1671 input_size_in_bits = EVEX_32bit;
1672 }
1673 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1674 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3, true);
1675 }
1676
1677 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1678 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1679 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1680 }
1681
1682 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1683 if (VM_Version::supports_evex()) {
1684 tuple_type = EVEX_T1S;
1685 input_size_in_bits = EVEX_32bit;
1686 }
1687 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1688 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1689 }
1690
1691
1692 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1693 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1694 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, true);
1695 emit_int8(0x2C);
1696 emit_int8((unsigned char)(0xC0 | encode));
1697 }
1698
1699 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1700 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1701 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, true);
1702 emit_int8(0x2C);
1703 emit_int8((unsigned char)(0xC0 | encode));
1704 }
1705
1706 void Assembler::decl(Address dst) {
1707 // Don't use it directly. Use MacroAssembler::decrement() instead.
1708 InstructionMark im(this);
1709 prefix(dst);
1710 emit_int8((unsigned char)0xFF);
1711 emit_operand(rcx, dst);
1712 }
1713
1714 void Assembler::divsd(XMMRegister dst, Address src) {
1715 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1716 if (VM_Version::supports_evex()) {
1717 tuple_type = EVEX_T1S;
1718 input_size_in_bits = EVEX_64bit;
1719 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_F2);
1720 } else {
1721 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1722 }
1723 }
1724
1725 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1726 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1727 if (VM_Version::supports_evex()) {
1728 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_F2);
1729 } else {
1730 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1731 }
1732 }
1733
1734 void Assembler::divss(XMMRegister dst, Address src) {
1735 if (VM_Version::supports_evex()) {
1736 tuple_type = EVEX_T1S;
1737 input_size_in_bits = EVEX_32bit;
1738 }
1739 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1740 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1741 }
1742
1743 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1744 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1745 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1746 }
1747
1748 void Assembler::emms() {
1749 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1750 emit_int8(0x0F);
1751 emit_int8(0x77);
1752 }
1753
1754 void Assembler::hlt() {
1755 emit_int8((unsigned char)0xF4);
1756 }
1757
1758 void Assembler::idivl(Register src) {
1759 int encode = prefix_and_encode(src->encoding());
1760 emit_int8((unsigned char)0xF7);
1761 emit_int8((unsigned char)(0xF8 | encode));
1762 }
1763
1764 void Assembler::divl(Register src) { // Unsigned
1765 int encode = prefix_and_encode(src->encoding());
1766 emit_int8((unsigned char)0xF7);
1767 emit_int8((unsigned char)(0xF0 | encode));
1768 }
1769
1770 void Assembler::imull(Register dst, Register src) {
1771 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1772 emit_int8(0x0F);
1773 emit_int8((unsigned char)0xAF);
1774 emit_int8((unsigned char)(0xC0 | encode));
1775 }
1776
1777
1778 void Assembler::imull(Register dst, Register src, int value) {
1779 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1780 if (is8bit(value)) {
1781 emit_int8(0x6B);
1782 emit_int8((unsigned char)(0xC0 | encode));
1783 emit_int8(value & 0xFF);
1784 } else {
1785 emit_int8(0x69);
1786 emit_int8((unsigned char)(0xC0 | encode));
1787 emit_int32(value);
1788 }
1789 }
1790
1791 void Assembler::imull(Register dst, Address src) {
1792 InstructionMark im(this);
1793 prefix(src, dst);
1794 emit_int8(0x0F);
1795 emit_int8((unsigned char) 0xAF);
1796 emit_operand(dst, src);
1797 }
1798
1799
1800 void Assembler::incl(Address dst) {
1801 // Don't use it directly. Use MacroAssembler::increment() instead.
1802 InstructionMark im(this);
1803 prefix(dst);
1804 emit_int8((unsigned char)0xFF);
1805 emit_operand(rax, dst);
1806 }
1807
1808 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1809 InstructionMark im(this);
1810 assert((0 <= cc) && (cc < 16), "illegal cc");
1811 if (L.is_bound()) {
1812 address dst = target(L);
1813 assert(dst != NULL, "jcc most probably wrong");
1814
1815 const int short_size = 2;
1816 const int long_size = 6;
1817 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1818 if (maybe_short && is8bit(offs - short_size)) {
1819 // 0111 tttn #8-bit disp
1820 emit_int8(0x70 | cc);
1821 emit_int8((offs - short_size) & 0xFF);
1822 } else {
1823 // 0000 1111 1000 tttn #32-bit disp
1824 assert(is_simm32(offs - long_size),
1825 "must be 32bit offset (call4)");
1826 emit_int8(0x0F);
1827 emit_int8((unsigned char)(0x80 | cc));
1828 emit_int32(offs - long_size);
1829 }
1830 } else {
1831 // Note: could eliminate cond. jumps to this jump if condition
1832 // is the same however, seems to be rather unlikely case.
1833 // Note: use jccb() if label to be bound is very close to get
1834 // an 8-bit displacement
1835 L.add_patch_at(code(), locator());
1836 emit_int8(0x0F);
1837 emit_int8((unsigned char)(0x80 | cc));
1838 emit_int32(0);
1839 }
1840 }
1841
1842 void Assembler::jccb(Condition cc, Label& L) {
1843 if (L.is_bound()) {
1844 const int short_size = 2;
1845 address entry = target(L);
1846 #ifdef ASSERT
1847 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1848 intptr_t delta = short_branch_delta();
1849 if (delta != 0) {
1850 dist += (dist < 0 ? (-delta) :delta);
1851 }
1852 assert(is8bit(dist), "Dispacement too large for a short jmp");
1853 #endif
1854 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1855 // 0111 tttn #8-bit disp
1856 emit_int8(0x70 | cc);
1857 emit_int8((offs - short_size) & 0xFF);
1858 } else {
1859 InstructionMark im(this);
1860 L.add_patch_at(code(), locator());
1861 emit_int8(0x70 | cc);
1862 emit_int8(0);
1863 }
1864 }
1865
1866 void Assembler::jmp(Address adr) {
1867 InstructionMark im(this);
1868 prefix(adr);
1869 emit_int8((unsigned char)0xFF);
1870 emit_operand(rsp, adr);
1871 }
1872
1873 void Assembler::jmp(Label& L, bool maybe_short) {
1874 if (L.is_bound()) {
1875 address entry = target(L);
1876 assert(entry != NULL, "jmp most probably wrong");
1877 InstructionMark im(this);
1878 const int short_size = 2;
1879 const int long_size = 5;
1880 intptr_t offs = entry - pc();
1881 if (maybe_short && is8bit(offs - short_size)) {
1882 emit_int8((unsigned char)0xEB);
1883 emit_int8((offs - short_size) & 0xFF);
1884 } else {
1885 emit_int8((unsigned char)0xE9);
1886 emit_int32(offs - long_size);
1887 }
1888 } else {
1889 // By default, forward jumps are always 32-bit displacements, since
1890 // we can't yet know where the label will be bound. If you're sure that
1891 // the forward jump will not run beyond 256 bytes, use jmpb to
1892 // force an 8-bit displacement.
1893 InstructionMark im(this);
1894 L.add_patch_at(code(), locator());
1895 emit_int8((unsigned char)0xE9);
1896 emit_int32(0);
1897 }
1898 }
1899
1900 void Assembler::jmp(Register entry) {
1901 int encode = prefix_and_encode(entry->encoding());
1902 emit_int8((unsigned char)0xFF);
1903 emit_int8((unsigned char)(0xE0 | encode));
1904 }
1905
1906 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1907 InstructionMark im(this);
1908 emit_int8((unsigned char)0xE9);
1909 assert(dest != NULL, "must have a target");
1910 intptr_t disp = dest - (pc() + sizeof(int32_t));
1911 assert(is_simm32(disp), "must be 32bit offset (jmp)");
1912 emit_data(disp, rspec.reloc(), call32_operand);
1913 }
1914
1915 void Assembler::jmpb(Label& L) {
1916 if (L.is_bound()) {
1917 const int short_size = 2;
1918 address entry = target(L);
1919 assert(entry != NULL, "jmp most probably wrong");
1920 #ifdef ASSERT
1921 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1922 intptr_t delta = short_branch_delta();
1923 if (delta != 0) {
1924 dist += (dist < 0 ? (-delta) :delta);
1925 }
1926 assert(is8bit(dist), "Dispacement too large for a short jmp");
1927 #endif
1928 intptr_t offs = entry - pc();
1929 emit_int8((unsigned char)0xEB);
1930 emit_int8((offs - short_size) & 0xFF);
1931 } else {
1932 InstructionMark im(this);
1933 L.add_patch_at(code(), locator());
1934 emit_int8((unsigned char)0xEB);
1935 emit_int8(0);
1936 }
1937 }
1938
1939 void Assembler::ldmxcsr( Address src) {
1940 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1941 InstructionMark im(this);
1942 prefix(src);
1943 emit_int8(0x0F);
1944 emit_int8((unsigned char)0xAE);
1945 emit_operand(as_Register(2), src);
1946 }
1947
1948 void Assembler::leal(Register dst, Address src) {
1949 InstructionMark im(this);
1950 #ifdef _LP64
1951 emit_int8(0x67); // addr32
1952 prefix(src, dst);
1953 #endif // LP64
1954 emit_int8((unsigned char)0x8D);
1955 emit_operand(dst, src);
1956 }
1957
1958 void Assembler::lfence() {
1959 emit_int8(0x0F);
1960 emit_int8((unsigned char)0xAE);
1961 emit_int8((unsigned char)0xE8);
1962 }
1963
1964 void Assembler::lock() {
1965 emit_int8((unsigned char)0xF0);
1966 }
1967
1968 void Assembler::lzcntl(Register dst, Register src) {
1969 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1970 emit_int8((unsigned char)0xF3);
1971 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1972 emit_int8(0x0F);
1973 emit_int8((unsigned char)0xBD);
1974 emit_int8((unsigned char)(0xC0 | encode));
1975 }
1976
1977 // Emit mfence instruction
1978 void Assembler::mfence() {
1979 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1980 emit_int8(0x0F);
1981 emit_int8((unsigned char)0xAE);
1982 emit_int8((unsigned char)0xF0);
1983 }
1984
1985 void Assembler::mov(Register dst, Register src) {
1986 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1987 }
1988
1989 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1990 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1991 if (VM_Version::supports_evex()) {
1992 emit_simd_arith_nonds_q(0x28, dst, src, VEX_SIMD_66, true);
1993 } else {
1994 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66);
1995 }
1996 }
1997
1998 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1999 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2000 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE);
2001 }
2002
2003 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2004 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2005 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, true, VEX_OPCODE_0F,
2006 false, AVX_128bit);
2007 emit_int8(0x16);
2008 emit_int8((unsigned char)(0xC0 | encode));
2009 }
2010
2011 void Assembler::movb(Register dst, Address src) {
2012 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2013 InstructionMark im(this);
2014 prefix(src, dst, true);
2015 emit_int8((unsigned char)0x8A);
2016 emit_operand(dst, src);
2017 }
2018
2019 void Assembler::kmovq(KRegister dst, KRegister src) {
2020 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2021 int encode = kreg_prefix_and_encode(dst, knoreg, src, VEX_SIMD_NONE,
2022 true, VEX_OPCODE_0F, true);
2023 emit_int8((unsigned char)0x90);
2024 emit_int8((unsigned char)(0xC0 | encode));
2025 }
2026
2027 void Assembler::kmovq(KRegister dst, Address src) {
2028 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2029 int dst_enc = dst->encoding();
2030 int nds_enc = 0;
2031 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_NONE,
2032 VEX_OPCODE_0F, true, AVX_128bit, true, true);
2033 emit_int8((unsigned char)0x90);
2034 emit_operand((Register)dst, src);
2035 }
2036
2037 void Assembler::kmovq(Address dst, KRegister src) {
2038 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2039 int src_enc = src->encoding();
2040 int nds_enc = 0;
2041 vex_prefix(dst, nds_enc, src_enc, VEX_SIMD_NONE,
2042 VEX_OPCODE_0F, true, AVX_128bit, true, true);
2043 emit_int8((unsigned char)0x90);
2044 emit_operand((Register)src, dst);
2045 }
2046
2047 void Assembler::kmovql(KRegister dst, Register src) {
2048 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2049 bool supports_bw = VM_Version::supports_avx512bw();
2050 VexSimdPrefix pre = supports_bw ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2051 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, true,
2052 VEX_OPCODE_0F, supports_bw);
2053 emit_int8((unsigned char)0x92);
2054 emit_int8((unsigned char)(0xC0 | encode));
2055 }
2056
2057 void Assembler::kmovdl(KRegister dst, Register src) {
2058 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2059 VexSimdPrefix pre = VM_Version::supports_avx512bw() ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2060 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, true, VEX_OPCODE_0F, false);
2061 emit_int8((unsigned char)0x92);
2062 emit_int8((unsigned char)(0xC0 | encode));
2063 }
2064
2065 void Assembler::movb(Address dst, int imm8) {
2066 InstructionMark im(this);
2067 prefix(dst);
2068 emit_int8((unsigned char)0xC6);
2069 emit_operand(rax, dst, 1);
2070 emit_int8(imm8);
2071 }
2072
2073
2074 void Assembler::movb(Address dst, Register src) {
2075 assert(src->has_byte_register(), "must have byte register");
2076 InstructionMark im(this);
2077 prefix(dst, src, true);
2078 emit_int8((unsigned char)0x88);
2079 emit_operand(src, dst);
2080 }
2081
2082 void Assembler::movdl(XMMRegister dst, Register src) {
2083 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2084 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, true);
2085 emit_int8(0x6E);
2086 emit_int8((unsigned char)(0xC0 | encode));
2087 }
2088
2089 void Assembler::movdl(Register dst, XMMRegister src) {
2090 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2091 // swap src/dst to get correct prefix
2092 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66, true);
2093 emit_int8(0x7E);
2094 emit_int8((unsigned char)(0xC0 | encode));
2095 }
2096
2097 void Assembler::movdl(XMMRegister dst, Address src) {
2098 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2099 if (VM_Version::supports_evex()) {
2100 tuple_type = EVEX_T1S;
2101 input_size_in_bits = EVEX_32bit;
2102 }
2103 InstructionMark im(this);
2104 simd_prefix(dst, src, VEX_SIMD_66, true, VEX_OPCODE_0F);
2105 emit_int8(0x6E);
2106 emit_operand(dst, src);
2107 }
2108
2109 void Assembler::movdl(Address dst, XMMRegister src) {
2110 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2111 if (VM_Version::supports_evex()) {
2112 tuple_type = EVEX_T1S;
2113 input_size_in_bits = EVEX_32bit;
2114 }
2115 InstructionMark im(this);
2116 simd_prefix(dst, src, VEX_SIMD_66, true);
2117 emit_int8(0x7E);
2118 emit_operand(src, dst);
2119 }
2120
2121 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2122 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2123 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
2124 }
2125
2126 void Assembler::movdqa(XMMRegister dst, Address src) {
2127 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2128 if (VM_Version::supports_evex()) {
2129 tuple_type = EVEX_FVM;
2130 }
2131 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
2132 }
2133
2134 void Assembler::movdqu(XMMRegister dst, Address src) {
2135 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2136 if (VM_Version::supports_evex()) {
2137 tuple_type = EVEX_FVM;
2138 }
2139 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
2140 }
2141
2142 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2143 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2144 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
2145 }
2146
2147 void Assembler::movdqu(Address dst, XMMRegister src) {
2148 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2149 if (VM_Version::supports_evex()) {
2150 tuple_type = EVEX_FVM;
2151 }
2152 InstructionMark im(this);
2153 simd_prefix(dst, src, VEX_SIMD_F3, false);
2154 emit_int8(0x7F);
2155 emit_operand(src, dst);
2156 }
2157
2158 // Move Unaligned 256bit Vector
2159 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2160 assert(UseAVX > 0, "");
2161 if (VM_Version::supports_evex()) {
2162 tuple_type = EVEX_FVM;
2163 }
2164 int vector_len = AVX_256bit;
2165 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector_len);
2166 emit_int8(0x6F);
2167 emit_int8((unsigned char)(0xC0 | encode));
2168 }
2169
2170 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2171 assert(UseAVX > 0, "");
2172 if (VM_Version::supports_evex()) {
2173 tuple_type = EVEX_FVM;
2174 }
2175 InstructionMark im(this);
2176 int vector_len = AVX_256bit;
2177 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector_len, false);
2178 emit_int8(0x6F);
2179 emit_operand(dst, src);
2180 }
2181
2182 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2183 assert(UseAVX > 0, "");
2184 if (VM_Version::supports_evex()) {
2185 tuple_type = EVEX_FVM;
2186 }
2187 InstructionMark im(this);
2188 int vector_len = AVX_256bit;
2189 // swap src<->dst for encoding
2190 assert(src != xnoreg, "sanity");
2191 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector_len, false);
2192 emit_int8(0x7F);
2193 emit_operand(src, dst);
2194 }
2195
2196 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2197 void Assembler::evmovdqu(XMMRegister dst, XMMRegister src, int vector_len) {
2198 assert(UseAVX > 0, "");
2199 int src_enc = src->encoding();
2200 int dst_enc = dst->encoding();
2201 int encode = vex_prefix_and_encode(dst_enc, 0, src_enc, VEX_SIMD_F3, VEX_OPCODE_0F,
2202 true, vector_len, false, false);
2203 emit_int8(0x6F);
2204 emit_int8((unsigned char)(0xC0 | encode));
2205 }
2206
2207 void Assembler::evmovdqu(XMMRegister dst, Address src, int vector_len) {
2208 assert(UseAVX > 0, "");
2209 InstructionMark im(this);
2210 if (VM_Version::supports_evex()) {
2211 tuple_type = EVEX_FVM;
2212 vex_prefix_q(dst, xnoreg, src, VEX_SIMD_F3, vector_len, false);
2213 } else {
2214 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector_len, false);
2215 }
2216 emit_int8(0x6F);
2217 emit_operand(dst, src);
2218 }
2219
2220 void Assembler::evmovdqu(Address dst, XMMRegister src, int vector_len) {
2221 assert(UseAVX > 0, "");
2222 InstructionMark im(this);
2223 assert(src != xnoreg, "sanity");
2224 if (VM_Version::supports_evex()) {
2225 tuple_type = EVEX_FVM;
2226 // swap src<->dst for encoding
2227 vex_prefix_q(src, xnoreg, dst, VEX_SIMD_F3, vector_len, false);
2228 } else {
2229 // swap src<->dst for encoding
2230 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector_len, false);
2231 }
2232 emit_int8(0x7F);
2233 emit_operand(src, dst);
2234 }
2235
2236 // Uses zero extension on 64bit
2237
2238 void Assembler::movl(Register dst, int32_t imm32) {
2239 int encode = prefix_and_encode(dst->encoding());
2240 emit_int8((unsigned char)(0xB8 | encode));
2241 emit_int32(imm32);
2242 }
2243
2244 void Assembler::movl(Register dst, Register src) {
2245 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2246 emit_int8((unsigned char)0x8B);
2247 emit_int8((unsigned char)(0xC0 | encode));
2248 }
2249
2250 void Assembler::movl(Register dst, Address src) {
2251 InstructionMark im(this);
2252 prefix(src, dst);
2253 emit_int8((unsigned char)0x8B);
2254 emit_operand(dst, src);
2255 }
2256
2257 void Assembler::movl(Address dst, int32_t imm32) {
2258 InstructionMark im(this);
2259 prefix(dst);
2260 emit_int8((unsigned char)0xC7);
2261 emit_operand(rax, dst, 4);
2262 emit_int32(imm32);
2263 }
2264
2265 void Assembler::movl(Address dst, Register src) {
2266 InstructionMark im(this);
2267 prefix(dst, src);
2268 emit_int8((unsigned char)0x89);
2269 emit_operand(src, dst);
2270 }
2271
2272 // New cpus require to use movsd and movss to avoid partial register stall
2273 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2274 // The selection is done in MacroAssembler::movdbl() and movflt().
2275 void Assembler::movlpd(XMMRegister dst, Address src) {
2276 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2277 if (VM_Version::supports_evex()) {
2278 tuple_type = EVEX_T1S;
2279 input_size_in_bits = EVEX_32bit;
2280 }
2281 emit_simd_arith(0x12, dst, src, VEX_SIMD_66, true);
2282 }
2283
2284 void Assembler::movq( MMXRegister dst, Address src ) {
2285 assert( VM_Version::supports_mmx(), "" );
2286 emit_int8(0x0F);
2287 emit_int8(0x6F);
2288 emit_operand(dst, src);
2289 }
2290
2291 void Assembler::movq( Address dst, MMXRegister src ) {
2292 assert( VM_Version::supports_mmx(), "" );
2293 emit_int8(0x0F);
2294 emit_int8(0x7F);
2295 // workaround gcc (3.2.1-7a) bug
2296 // In that version of gcc with only an emit_operand(MMX, Address)
2297 // gcc will tail jump and try and reverse the parameters completely
2298 // obliterating dst in the process. By having a version available
2299 // that doesn't need to swap the args at the tail jump the bug is
2300 // avoided.
2301 emit_operand(dst, src);
2302 }
2303
2304 void Assembler::movq(XMMRegister dst, Address src) {
2305 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2306 InstructionMark im(this);
2307 if (VM_Version::supports_evex()) {
2308 tuple_type = EVEX_T1S;
2309 input_size_in_bits = EVEX_64bit;
2310 simd_prefix_q(dst, xnoreg, src, VEX_SIMD_F3, true);
2311 } else {
2312 simd_prefix(dst, src, VEX_SIMD_F3, true, VEX_OPCODE_0F);
2313 }
2314 emit_int8(0x7E);
2315 emit_operand(dst, src);
2316 }
2317
2318 void Assembler::movq(Address dst, XMMRegister src) {
2319 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2320 InstructionMark im(this);
2321 if (VM_Version::supports_evex()) {
2322 tuple_type = EVEX_T1S;
2323 input_size_in_bits = EVEX_64bit;
2324 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, true,
2325 VEX_OPCODE_0F, true, AVX_128bit);
2326 } else {
2327 simd_prefix(dst, src, VEX_SIMD_66, true);
2328 }
2329 emit_int8((unsigned char)0xD6);
2330 emit_operand(src, dst);
2331 }
2332
2333 void Assembler::movsbl(Register dst, Address src) { // movsxb
2334 InstructionMark im(this);
2335 prefix(src, dst);
2336 emit_int8(0x0F);
2337 emit_int8((unsigned char)0xBE);
2338 emit_operand(dst, src);
2339 }
2340
2341 void Assembler::movsbl(Register dst, Register src) { // movsxb
2342 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2343 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
2344 emit_int8(0x0F);
2345 emit_int8((unsigned char)0xBE);
2346 emit_int8((unsigned char)(0xC0 | encode));
2347 }
2348
2349 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2350 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2351 if (VM_Version::supports_evex()) {
2352 emit_simd_arith_q(0x10, dst, src, VEX_SIMD_F2, true);
2353 } else {
2354 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2);
2355 }
2356 }
2357
2358 void Assembler::movsd(XMMRegister dst, Address src) {
2359 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2360 if (VM_Version::supports_evex()) {
2361 tuple_type = EVEX_T1S;
2362 input_size_in_bits = EVEX_64bit;
2363 emit_simd_arith_nonds_q(0x10, dst, src, VEX_SIMD_F2, true);
2364 } else {
2365 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2);
2366 }
2367 }
2368
2369 void Assembler::movsd(Address dst, XMMRegister src) {
2370 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2371 InstructionMark im(this);
2372 if (VM_Version::supports_evex()) {
2373 tuple_type = EVEX_T1S;
2374 input_size_in_bits = EVEX_64bit;
2375 simd_prefix_q(src, xnoreg, dst, VEX_SIMD_F2);
2376 } else {
2377 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, false);
2378 }
2379 emit_int8(0x11);
2380 emit_operand(src, dst);
2381 }
2382
2383 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2384 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2385 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3, true);
2386 }
2387
2388 void Assembler::movss(XMMRegister dst, Address src) {
2389 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2390 if (VM_Version::supports_evex()) {
2391 tuple_type = EVEX_T1S;
2392 input_size_in_bits = EVEX_32bit;
2393 }
2394 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3, true);
2395 }
2396
2397 void Assembler::movss(Address dst, XMMRegister src) {
2398 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2399 if (VM_Version::supports_evex()) {
2400 tuple_type = EVEX_T1S;
2401 input_size_in_bits = EVEX_32bit;
2402 }
2403 InstructionMark im(this);
2404 simd_prefix(dst, src, VEX_SIMD_F3, false);
2405 emit_int8(0x11);
2406 emit_operand(src, dst);
2407 }
2408
2409 void Assembler::movswl(Register dst, Address src) { // movsxw
2410 InstructionMark im(this);
2411 prefix(src, dst);
2412 emit_int8(0x0F);
2413 emit_int8((unsigned char)0xBF);
2414 emit_operand(dst, src);
2415 }
2416
2417 void Assembler::movswl(Register dst, Register src) { // movsxw
2418 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2419 emit_int8(0x0F);
2420 emit_int8((unsigned char)0xBF);
2421 emit_int8((unsigned char)(0xC0 | encode));
2422 }
2423
2424 void Assembler::movw(Address dst, int imm16) {
2425 InstructionMark im(this);
2426
2427 emit_int8(0x66); // switch to 16-bit mode
2428 prefix(dst);
2429 emit_int8((unsigned char)0xC7);
2430 emit_operand(rax, dst, 2);
2431 emit_int16(imm16);
2432 }
2433
2434 void Assembler::movw(Register dst, Address src) {
2435 InstructionMark im(this);
2436 emit_int8(0x66);
2437 prefix(src, dst);
2438 emit_int8((unsigned char)0x8B);
2439 emit_operand(dst, src);
2440 }
2441
2442 void Assembler::movw(Address dst, Register src) {
2443 InstructionMark im(this);
2444 emit_int8(0x66);
2445 prefix(dst, src);
2446 emit_int8((unsigned char)0x89);
2447 emit_operand(src, dst);
2448 }
2449
2450 void Assembler::movzbl(Register dst, Address src) { // movzxb
2451 InstructionMark im(this);
2452 prefix(src, dst);
2453 emit_int8(0x0F);
2454 emit_int8((unsigned char)0xB6);
2455 emit_operand(dst, src);
2456 }
2457
2458 void Assembler::movzbl(Register dst, Register src) { // movzxb
2459 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2460 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
2461 emit_int8(0x0F);
2462 emit_int8((unsigned char)0xB6);
2463 emit_int8(0xC0 | encode);
2464 }
2465
2466 void Assembler::movzwl(Register dst, Address src) { // movzxw
2467 InstructionMark im(this);
2468 prefix(src, dst);
2469 emit_int8(0x0F);
2470 emit_int8((unsigned char)0xB7);
2471 emit_operand(dst, src);
2472 }
2473
2474 void Assembler::movzwl(Register dst, Register src) { // movzxw
2475 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2476 emit_int8(0x0F);
2477 emit_int8((unsigned char)0xB7);
2478 emit_int8(0xC0 | encode);
2479 }
2480
2481 void Assembler::mull(Address src) {
2482 InstructionMark im(this);
2483 prefix(src);
2484 emit_int8((unsigned char)0xF7);
2485 emit_operand(rsp, src);
2486 }
2487
2488 void Assembler::mull(Register src) {
2489 int encode = prefix_and_encode(src->encoding());
2490 emit_int8((unsigned char)0xF7);
2491 emit_int8((unsigned char)(0xE0 | encode));
2492 }
2493
2494 void Assembler::mulsd(XMMRegister dst, Address src) {
2495 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2496 if (VM_Version::supports_evex()) {
2497 tuple_type = EVEX_T1S;
2498 input_size_in_bits = EVEX_64bit;
2499 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_F2);
2500 } else {
2501 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2502 }
2503 }
2504
2505 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2506 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2507 if (VM_Version::supports_evex()) {
2508 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_F2);
2509 } else {
2510 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2511 }
2512 }
2513
2514 void Assembler::mulss(XMMRegister dst, Address src) {
2515 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2516 if (VM_Version::supports_evex()) {
2517 tuple_type = EVEX_T1S;
2518 input_size_in_bits = EVEX_32bit;
2519 }
2520 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2521 }
2522
2523 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2524 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2525 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2526 }
2527
2528 void Assembler::negl(Register dst) {
2529 int encode = prefix_and_encode(dst->encoding());
2530 emit_int8((unsigned char)0xF7);
2531 emit_int8((unsigned char)(0xD8 | encode));
2532 }
2533
2534 void Assembler::nop(int i) {
2535 #ifdef ASSERT
2536 assert(i > 0, " ");
2537 // The fancy nops aren't currently recognized by debuggers making it a
2538 // pain to disassemble code while debugging. If asserts are on clearly
2539 // speed is not an issue so simply use the single byte traditional nop
2540 // to do alignment.
2541
2542 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2543 return;
2544
2545 #endif // ASSERT
2546
2547 if (UseAddressNop && VM_Version::is_intel()) {
2548 //
2549 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2550 // 1: 0x90
2551 // 2: 0x66 0x90
2552 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2553 // 4: 0x0F 0x1F 0x40 0x00
2554 // 5: 0x0F 0x1F 0x44 0x00 0x00
2555 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2556 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2557 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2558 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2559 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2560 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2561
2562 // The rest coding is Intel specific - don't use consecutive address nops
2563
2564 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2565 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2566 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2567 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2568
2569 while(i >= 15) {
2570 // For Intel don't generate consecutive addess nops (mix with regular nops)
2571 i -= 15;
2572 emit_int8(0x66); // size prefix
2573 emit_int8(0x66); // size prefix
2574 emit_int8(0x66); // size prefix
2575 addr_nop_8();
2576 emit_int8(0x66); // size prefix
2577 emit_int8(0x66); // size prefix
2578 emit_int8(0x66); // size prefix
2579 emit_int8((unsigned char)0x90);
2580 // nop
2581 }
2582 switch (i) {
2583 case 14:
2584 emit_int8(0x66); // size prefix
2585 case 13:
2586 emit_int8(0x66); // size prefix
2587 case 12:
2588 addr_nop_8();
2589 emit_int8(0x66); // size prefix
2590 emit_int8(0x66); // size prefix
2591 emit_int8(0x66); // size prefix
2592 emit_int8((unsigned char)0x90);
2593 // nop
2594 break;
2595 case 11:
2596 emit_int8(0x66); // size prefix
2597 case 10:
2598 emit_int8(0x66); // size prefix
2599 case 9:
2600 emit_int8(0x66); // size prefix
2601 case 8:
2602 addr_nop_8();
2603 break;
2604 case 7:
2605 addr_nop_7();
2606 break;
2607 case 6:
2608 emit_int8(0x66); // size prefix
2609 case 5:
2610 addr_nop_5();
2611 break;
2612 case 4:
2613 addr_nop_4();
2614 break;
2615 case 3:
2616 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2617 emit_int8(0x66); // size prefix
2618 case 2:
2619 emit_int8(0x66); // size prefix
2620 case 1:
2621 emit_int8((unsigned char)0x90);
2622 // nop
2623 break;
2624 default:
2625 assert(i == 0, " ");
2626 }
2627 return;
2628 }
2629 if (UseAddressNop && VM_Version::is_amd()) {
2630 //
2631 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2632 // 1: 0x90
2633 // 2: 0x66 0x90
2634 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2635 // 4: 0x0F 0x1F 0x40 0x00
2636 // 5: 0x0F 0x1F 0x44 0x00 0x00
2637 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2638 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2639 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2640 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2641 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2642 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2643
2644 // The rest coding is AMD specific - use consecutive address nops
2645
2646 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2647 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2648 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2649 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2650 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2651 // Size prefixes (0x66) are added for larger sizes
2652
2653 while(i >= 22) {
2654 i -= 11;
2655 emit_int8(0x66); // size prefix
2656 emit_int8(0x66); // size prefix
2657 emit_int8(0x66); // size prefix
2658 addr_nop_8();
2659 }
2660 // Generate first nop for size between 21-12
2661 switch (i) {
2662 case 21:
2663 i -= 1;
2664 emit_int8(0x66); // size prefix
2665 case 20:
2666 case 19:
2667 i -= 1;
2668 emit_int8(0x66); // size prefix
2669 case 18:
2670 case 17:
2671 i -= 1;
2672 emit_int8(0x66); // size prefix
2673 case 16:
2674 case 15:
2675 i -= 8;
2676 addr_nop_8();
2677 break;
2678 case 14:
2679 case 13:
2680 i -= 7;
2681 addr_nop_7();
2682 break;
2683 case 12:
2684 i -= 6;
2685 emit_int8(0x66); // size prefix
2686 addr_nop_5();
2687 break;
2688 default:
2689 assert(i < 12, " ");
2690 }
2691
2692 // Generate second nop for size between 11-1
2693 switch (i) {
2694 case 11:
2695 emit_int8(0x66); // size prefix
2696 case 10:
2697 emit_int8(0x66); // size prefix
2698 case 9:
2699 emit_int8(0x66); // size prefix
2700 case 8:
2701 addr_nop_8();
2702 break;
2703 case 7:
2704 addr_nop_7();
2705 break;
2706 case 6:
2707 emit_int8(0x66); // size prefix
2708 case 5:
2709 addr_nop_5();
2710 break;
2711 case 4:
2712 addr_nop_4();
2713 break;
2714 case 3:
2715 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2716 emit_int8(0x66); // size prefix
2717 case 2:
2718 emit_int8(0x66); // size prefix
2719 case 1:
2720 emit_int8((unsigned char)0x90);
2721 // nop
2722 break;
2723 default:
2724 assert(i == 0, " ");
2725 }
2726 return;
2727 }
2728
2729 // Using nops with size prefixes "0x66 0x90".
2730 // From AMD Optimization Guide:
2731 // 1: 0x90
2732 // 2: 0x66 0x90
2733 // 3: 0x66 0x66 0x90
2734 // 4: 0x66 0x66 0x66 0x90
2735 // 5: 0x66 0x66 0x90 0x66 0x90
2736 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2737 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2738 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2739 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2740 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2741 //
2742 while(i > 12) {
2743 i -= 4;
2744 emit_int8(0x66); // size prefix
2745 emit_int8(0x66);
2746 emit_int8(0x66);
2747 emit_int8((unsigned char)0x90);
2748 // nop
2749 }
2750 // 1 - 12 nops
2751 if(i > 8) {
2752 if(i > 9) {
2753 i -= 1;
2754 emit_int8(0x66);
2755 }
2756 i -= 3;
2757 emit_int8(0x66);
2758 emit_int8(0x66);
2759 emit_int8((unsigned char)0x90);
2760 }
2761 // 1 - 8 nops
2762 if(i > 4) {
2763 if(i > 6) {
2764 i -= 1;
2765 emit_int8(0x66);
2766 }
2767 i -= 3;
2768 emit_int8(0x66);
2769 emit_int8(0x66);
2770 emit_int8((unsigned char)0x90);
2771 }
2772 switch (i) {
2773 case 4:
2774 emit_int8(0x66);
2775 case 3:
2776 emit_int8(0x66);
2777 case 2:
2778 emit_int8(0x66);
2779 case 1:
2780 emit_int8((unsigned char)0x90);
2781 break;
2782 default:
2783 assert(i == 0, " ");
2784 }
2785 }
2786
2787 void Assembler::notl(Register dst) {
2788 int encode = prefix_and_encode(dst->encoding());
2789 emit_int8((unsigned char)0xF7);
2790 emit_int8((unsigned char)(0xD0 | encode));
2791 }
2792
2793 void Assembler::orl(Address dst, int32_t imm32) {
2794 InstructionMark im(this);
2795 prefix(dst);
2796 emit_arith_operand(0x81, rcx, dst, imm32);
2797 }
2798
2799 void Assembler::orl(Register dst, int32_t imm32) {
2800 prefix(dst);
2801 emit_arith(0x81, 0xC8, dst, imm32);
2802 }
2803
2804 void Assembler::orl(Register dst, Address src) {
2805 InstructionMark im(this);
2806 prefix(src, dst);
2807 emit_int8(0x0B);
2808 emit_operand(dst, src);
2809 }
2810
2811 void Assembler::orl(Register dst, Register src) {
2812 (void) prefix_and_encode(dst->encoding(), src->encoding());
2813 emit_arith(0x0B, 0xC0, dst, src);
2814 }
2815
2816 void Assembler::packuswb(XMMRegister dst, Address src) {
2817 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2818 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2819 if (VM_Version::supports_evex()) {
2820 tuple_type = EVEX_FV;
2821 input_size_in_bits = EVEX_32bit;
2822 }
2823 emit_simd_arith(0x67, dst, src, VEX_SIMD_66,
2824 false, (VM_Version::supports_avx512dq() == false));
2825 }
2826
2827 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2828 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2829 emit_simd_arith(0x67, dst, src, VEX_SIMD_66,
2830 false, (VM_Version::supports_avx512dq() == false));
2831 }
2832
2833 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2834 assert(UseAVX > 0, "some form of AVX must be enabled");
2835 emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector_len,
2836 false, (VM_Version::supports_avx512dq() == false));
2837 }
2838
2839 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
2840 assert(VM_Version::supports_avx2(), "");
2841 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false,
2842 VEX_OPCODE_0F_3A, true, vector_len);
2843 emit_int8(0x00);
2844 emit_int8(0xC0 | encode);
2845 emit_int8(imm8);
2846 }
2847
2848 void Assembler::pause() {
2849 emit_int8((unsigned char)0xF3);
2850 emit_int8((unsigned char)0x90);
2851 }
2852
2853 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2854 assert(VM_Version::supports_sse4_2(), "");
2855 InstructionMark im(this);
2856 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, false, VEX_OPCODE_0F_3A,
2857 false, AVX_128bit, true);
2858 emit_int8(0x61);
2859 emit_operand(dst, src);
2860 emit_int8(imm8);
2861 }
2862
2863 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2864 assert(VM_Version::supports_sse4_2(), "");
2865 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false,
2866 VEX_OPCODE_0F_3A, false, AVX_128bit, true);
2867 emit_int8(0x61);
2868 emit_int8((unsigned char)(0xC0 | encode));
2869 emit_int8(imm8);
2870 }
2871
2872 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
2873 assert(VM_Version::supports_sse4_1(), "");
2874 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2875 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2876 emit_int8(0x16);
2877 emit_int8((unsigned char)(0xC0 | encode));
2878 emit_int8(imm8);
2879 }
2880
2881 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
2882 assert(VM_Version::supports_sse4_1(), "");
2883 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2884 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2885 emit_int8(0x16);
2886 emit_int8((unsigned char)(0xC0 | encode));
2887 emit_int8(imm8);
2888 }
2889
2890 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
2891 assert(VM_Version::supports_sse4_1(), "");
2892 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2893 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2894 emit_int8(0x22);
2895 emit_int8((unsigned char)(0xC0 | encode));
2896 emit_int8(imm8);
2897 }
2898
2899 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
2900 assert(VM_Version::supports_sse4_1(), "");
2901 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2902 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2903 emit_int8(0x22);
2904 emit_int8((unsigned char)(0xC0 | encode));
2905 emit_int8(imm8);
2906 }
2907
2908 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
2909 assert(VM_Version::supports_sse4_1(), "");
2910 if (VM_Version::supports_evex()) {
2911 tuple_type = EVEX_HVM;
2912 }
2913 InstructionMark im(this);
2914 simd_prefix(dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38);
2915 emit_int8(0x30);
2916 emit_operand(dst, src);
2917 }
2918
2919 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2920 assert(VM_Version::supports_sse4_1(), "");
2921 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38);
2922 emit_int8(0x30);
2923 emit_int8((unsigned char)(0xC0 | encode));
2924 }
2925
2926 // generic
2927 void Assembler::pop(Register dst) {
2928 int encode = prefix_and_encode(dst->encoding());
2929 emit_int8(0x58 | encode);
2930 }
2931
2932 void Assembler::popcntl(Register dst, Address src) {
2933 assert(VM_Version::supports_popcnt(), "must support");
2934 InstructionMark im(this);
2935 emit_int8((unsigned char)0xF3);
2936 prefix(src, dst);
2937 emit_int8(0x0F);
2938 emit_int8((unsigned char)0xB8);
2939 emit_operand(dst, src);
2940 }
2941
2942 void Assembler::popcntl(Register dst, Register src) {
2943 assert(VM_Version::supports_popcnt(), "must support");
2944 emit_int8((unsigned char)0xF3);
2945 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2946 emit_int8(0x0F);
2947 emit_int8((unsigned char)0xB8);
2948 emit_int8((unsigned char)(0xC0 | encode));
2949 }
2950
2951 void Assembler::popf() {
2952 emit_int8((unsigned char)0x9D);
2953 }
2954
2955 #ifndef _LP64 // no 32bit push/pop on amd64
2956 void Assembler::popl(Address dst) {
2957 // NOTE: this will adjust stack by 8byte on 64bits
2958 InstructionMark im(this);
2959 prefix(dst);
2960 emit_int8((unsigned char)0x8F);
2961 emit_operand(rax, dst);
2962 }
2963 #endif
2964
2965 void Assembler::prefetch_prefix(Address src) {
2966 prefix(src);
2967 emit_int8(0x0F);
2968 }
2969
2970 void Assembler::prefetchnta(Address src) {
2971 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2972 InstructionMark im(this);
2973 prefetch_prefix(src);
2974 emit_int8(0x18);
2975 emit_operand(rax, src); // 0, src
2976 }
2977
2978 void Assembler::prefetchr(Address src) {
2979 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2980 InstructionMark im(this);
2981 prefetch_prefix(src);
2982 emit_int8(0x0D);
2983 emit_operand(rax, src); // 0, src
2984 }
2985
2986 void Assembler::prefetcht0(Address src) {
2987 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2988 InstructionMark im(this);
2989 prefetch_prefix(src);
2990 emit_int8(0x18);
2991 emit_operand(rcx, src); // 1, src
2992 }
2993
2994 void Assembler::prefetcht1(Address src) {
2995 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2996 InstructionMark im(this);
2997 prefetch_prefix(src);
2998 emit_int8(0x18);
2999 emit_operand(rdx, src); // 2, src
3000 }
3001
3002 void Assembler::prefetcht2(Address src) {
3003 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3004 InstructionMark im(this);
3005 prefetch_prefix(src);
3006 emit_int8(0x18);
3007 emit_operand(rbx, src); // 3, src
3008 }
3009
3010 void Assembler::prefetchw(Address src) {
3011 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3012 InstructionMark im(this);
3013 prefetch_prefix(src);
3014 emit_int8(0x0D);
3015 emit_operand(rcx, src); // 1, src
3016 }
3017
3018 void Assembler::prefix(Prefix p) {
3019 emit_int8(p);
3020 }
3021
3022 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3023 assert(VM_Version::supports_ssse3(), "");
3024 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38,
3025 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3026 emit_int8(0x00);
3027 emit_int8((unsigned char)(0xC0 | encode));
3028 }
3029
3030 void Assembler::pshufb(XMMRegister dst, Address src) {
3031 assert(VM_Version::supports_ssse3(), "");
3032 if (VM_Version::supports_evex()) {
3033 tuple_type = EVEX_FVM;
3034 }
3035 InstructionMark im(this);
3036 simd_prefix(dst, dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38,
3037 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3038 emit_int8(0x00);
3039 emit_operand(dst, src);
3040 }
3041
3042 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
3043 assert(isByte(mode), "invalid value");
3044 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3045 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
3046 emit_int8(mode & 0xFF);
3047
3048 }
3049
3050 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
3051 assert(isByte(mode), "invalid value");
3052 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3053 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3054 if (VM_Version::supports_evex()) {
3055 tuple_type = EVEX_FV;
3056 input_size_in_bits = EVEX_32bit;
3057 }
3058 InstructionMark im(this);
3059 simd_prefix(dst, src, VEX_SIMD_66, false);
3060 emit_int8(0x70);
3061 emit_operand(dst, src);
3062 emit_int8(mode & 0xFF);
3063 }
3064
3065 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3066 assert(isByte(mode), "invalid value");
3067 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3068 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2, false,
3069 (VM_Version::supports_avx512bw() == false));
3070 emit_int8(mode & 0xFF);
3071 }
3072
3073 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3074 assert(isByte(mode), "invalid value");
3075 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3076 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3077 if (VM_Version::supports_evex()) {
3078 tuple_type = EVEX_FVM;
3079 }
3080 InstructionMark im(this);
3081 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, false, VEX_OPCODE_0F,
3082 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3083 emit_int8(0x70);
3084 emit_operand(dst, src);
3085 emit_int8(mode & 0xFF);
3086 }
3087
3088 void Assembler::psrldq(XMMRegister dst, int shift) {
3089 // Shift 128 bit value in xmm register by number of bytes.
3090 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3091 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, true, VEX_OPCODE_0F,
3092 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3093 emit_int8(0x73);
3094 emit_int8((unsigned char)(0xC0 | encode));
3095 emit_int8(shift);
3096 }
3097
3098 void Assembler::ptest(XMMRegister dst, Address src) {
3099 assert(VM_Version::supports_sse4_1(), "");
3100 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3101 InstructionMark im(this);
3102 simd_prefix(dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38);
3103 emit_int8(0x17);
3104 emit_operand(dst, src);
3105 }
3106
3107 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3108 assert(VM_Version::supports_sse4_1(), "");
3109 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
3110 false, VEX_OPCODE_0F_38);
3111 emit_int8(0x17);
3112 emit_int8((unsigned char)(0xC0 | encode));
3113 }
3114
3115 void Assembler::vptest(XMMRegister dst, Address src) {
3116 assert(VM_Version::supports_avx(), "");
3117 InstructionMark im(this);
3118 int vector_len = AVX_256bit;
3119 assert(dst != xnoreg, "sanity");
3120 int dst_enc = dst->encoding();
3121 // swap src<->dst for encoding
3122 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector_len);
3123 emit_int8(0x17);
3124 emit_operand(dst, src);
3125 }
3126
3127 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
3128 assert(VM_Version::supports_avx(), "");
3129 int vector_len = AVX_256bit;
3130 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
3131 vector_len, VEX_OPCODE_0F_38);
3132 emit_int8(0x17);
3133 emit_int8((unsigned char)(0xC0 | encode));
3134 }
3135
3136 void Assembler::punpcklbw(XMMRegister dst, Address src) {
3137 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3138 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3139 if (VM_Version::supports_evex()) {
3140 tuple_type = EVEX_FVM;
3141 }
3142 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
3143 }
3144
3145 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3146 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3147 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
3148 }
3149
3150 void Assembler::punpckldq(XMMRegister dst, Address src) {
3151 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3152 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3153 if (VM_Version::supports_evex()) {
3154 tuple_type = EVEX_FV;
3155 input_size_in_bits = EVEX_32bit;
3156 }
3157 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
3158 }
3159
3160 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
3161 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3162 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
3163 }
3164
3165 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
3166 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3167 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66);
3168 }
3169
3170 void Assembler::push(int32_t imm32) {
3171 // in 64bits we push 64bits onto the stack but only
3172 // take a 32bit immediate
3173 emit_int8(0x68);
3174 emit_int32(imm32);
3175 }
3176
3177 void Assembler::push(Register src) {
3178 int encode = prefix_and_encode(src->encoding());
3179
3180 emit_int8(0x50 | encode);
3181 }
3182
3183 void Assembler::pushf() {
3184 emit_int8((unsigned char)0x9C);
3185 }
3186
3187 #ifndef _LP64 // no 32bit push/pop on amd64
3188 void Assembler::pushl(Address src) {
3189 // Note this will push 64bit on 64bit
3190 InstructionMark im(this);
3191 prefix(src);
3192 emit_int8((unsigned char)0xFF);
3193 emit_operand(rsi, src);
3194 }
3195 #endif
3196
3197 void Assembler::rcll(Register dst, int imm8) {
3198 assert(isShiftCount(imm8), "illegal shift count");
3199 int encode = prefix_and_encode(dst->encoding());
3200 if (imm8 == 1) {
3201 emit_int8((unsigned char)0xD1);
3202 emit_int8((unsigned char)(0xD0 | encode));
3203 } else {
3204 emit_int8((unsigned char)0xC1);
3205 emit_int8((unsigned char)0xD0 | encode);
3206 emit_int8(imm8);
3207 }
3208 }
3209
3210 void Assembler::rdtsc() {
3211 emit_int8((unsigned char)0x0F);
3212 emit_int8((unsigned char)0x31);
3213 }
3214
3215 // copies data from [esi] to [edi] using rcx pointer sized words
3216 // generic
3217 void Assembler::rep_mov() {
3218 emit_int8((unsigned char)0xF3);
3219 // MOVSQ
3220 LP64_ONLY(prefix(REX_W));
3221 emit_int8((unsigned char)0xA5);
3222 }
3223
3224 // sets rcx bytes with rax, value at [edi]
3225 void Assembler::rep_stosb() {
3226 emit_int8((unsigned char)0xF3); // REP
3227 LP64_ONLY(prefix(REX_W));
3228 emit_int8((unsigned char)0xAA); // STOSB
3229 }
3230
3231 // sets rcx pointer sized words with rax, value at [edi]
3232 // generic
3233 void Assembler::rep_stos() {
3234 emit_int8((unsigned char)0xF3); // REP
3235 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
3236 emit_int8((unsigned char)0xAB);
3237 }
3238
3239 // scans rcx pointer sized words at [edi] for occurance of rax,
3240 // generic
3241 void Assembler::repne_scan() { // repne_scan
3242 emit_int8((unsigned char)0xF2);
3243 // SCASQ
3244 LP64_ONLY(prefix(REX_W));
3245 emit_int8((unsigned char)0xAF);
3246 }
3247
3248 #ifdef _LP64
3249 // scans rcx 4 byte words at [edi] for occurance of rax,
3250 // generic
3251 void Assembler::repne_scanl() { // repne_scan
3252 emit_int8((unsigned char)0xF2);
3253 // SCASL
3254 emit_int8((unsigned char)0xAF);
3255 }
3256 #endif
3257
3258 void Assembler::ret(int imm16) {
3259 if (imm16 == 0) {
3260 emit_int8((unsigned char)0xC3);
3261 } else {
3262 emit_int8((unsigned char)0xC2);
3263 emit_int16(imm16);
3264 }
3265 }
3266
3267 void Assembler::sahf() {
3268 #ifdef _LP64
3269 // Not supported in 64bit mode
3270 ShouldNotReachHere();
3271 #endif
3272 emit_int8((unsigned char)0x9E);
3273 }
3274
3275 void Assembler::sarl(Register dst, int imm8) {
3276 int encode = prefix_and_encode(dst->encoding());
3277 assert(isShiftCount(imm8), "illegal shift count");
3278 if (imm8 == 1) {
3279 emit_int8((unsigned char)0xD1);
3280 emit_int8((unsigned char)(0xF8 | encode));
3281 } else {
3282 emit_int8((unsigned char)0xC1);
3283 emit_int8((unsigned char)(0xF8 | encode));
3284 emit_int8(imm8);
3285 }
3286 }
3287
3288 void Assembler::sarl(Register dst) {
3289 int encode = prefix_and_encode(dst->encoding());
3290 emit_int8((unsigned char)0xD3);
3291 emit_int8((unsigned char)(0xF8 | encode));
3292 }
3293
3294 void Assembler::sbbl(Address dst, int32_t imm32) {
3295 InstructionMark im(this);
3296 prefix(dst);
3297 emit_arith_operand(0x81, rbx, dst, imm32);
3298 }
3299
3300 void Assembler::sbbl(Register dst, int32_t imm32) {
3301 prefix(dst);
3302 emit_arith(0x81, 0xD8, dst, imm32);
3303 }
3304
3305
3306 void Assembler::sbbl(Register dst, Address src) {
3307 InstructionMark im(this);
3308 prefix(src, dst);
3309 emit_int8(0x1B);
3310 emit_operand(dst, src);
3311 }
3312
3313 void Assembler::sbbl(Register dst, Register src) {
3314 (void) prefix_and_encode(dst->encoding(), src->encoding());
3315 emit_arith(0x1B, 0xC0, dst, src);
3316 }
3317
3318 void Assembler::setb(Condition cc, Register dst) {
3319 assert(0 <= cc && cc < 16, "illegal cc");
3320 int encode = prefix_and_encode(dst->encoding(), true);
3321 emit_int8(0x0F);
3322 emit_int8((unsigned char)0x90 | cc);
3323 emit_int8((unsigned char)(0xC0 | encode));
3324 }
3325
3326 void Assembler::shll(Register dst, int imm8) {
3327 assert(isShiftCount(imm8), "illegal shift count");
3328 int encode = prefix_and_encode(dst->encoding());
3329 if (imm8 == 1 ) {
3330 emit_int8((unsigned char)0xD1);
3331 emit_int8((unsigned char)(0xE0 | encode));
3332 } else {
3333 emit_int8((unsigned char)0xC1);
3334 emit_int8((unsigned char)(0xE0 | encode));
3335 emit_int8(imm8);
3336 }
3337 }
3338
3339 void Assembler::shll(Register dst) {
3340 int encode = prefix_and_encode(dst->encoding());
3341 emit_int8((unsigned char)0xD3);
3342 emit_int8((unsigned char)(0xE0 | encode));
3343 }
3344
3345 void Assembler::shrl(Register dst, int imm8) {
3346 assert(isShiftCount(imm8), "illegal shift count");
3347 int encode = prefix_and_encode(dst->encoding());
3348 emit_int8((unsigned char)0xC1);
3349 emit_int8((unsigned char)(0xE8 | encode));
3350 emit_int8(imm8);
3351 }
3352
3353 void Assembler::shrl(Register dst) {
3354 int encode = prefix_and_encode(dst->encoding());
3355 emit_int8((unsigned char)0xD3);
3356 emit_int8((unsigned char)(0xE8 | encode));
3357 }
3358
3359 // copies a single word from [esi] to [edi]
3360 void Assembler::smovl() {
3361 emit_int8((unsigned char)0xA5);
3362 }
3363
3364 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
3365 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3366 if (VM_Version::supports_evex()) {
3367 emit_simd_arith_q(0x51, dst, src, VEX_SIMD_F2);
3368 } else {
3369 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
3370 }
3371 }
3372
3373 void Assembler::sqrtsd(XMMRegister dst, Address src) {
3374 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3375 if (VM_Version::supports_evex()) {
3376 tuple_type = EVEX_T1S;
3377 input_size_in_bits = EVEX_64bit;
3378 emit_simd_arith_q(0x51, dst, src, VEX_SIMD_F2);
3379 } else {
3380 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
3381 }
3382 }
3383
3384 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
3385 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3386 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
3387 }
3388
3389 void Assembler::std() {
3390 emit_int8((unsigned char)0xFD);
3391 }
3392
3393 void Assembler::sqrtss(XMMRegister dst, Address src) {
3394 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3395 if (VM_Version::supports_evex()) {
3396 tuple_type = EVEX_T1S;
3397 input_size_in_bits = EVEX_32bit;
3398 }
3399 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
3400 }
3401
3402 void Assembler::stmxcsr( Address dst) {
3403 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3404 InstructionMark im(this);
3405 prefix(dst);
3406 emit_int8(0x0F);
3407 emit_int8((unsigned char)0xAE);
3408 emit_operand(as_Register(3), dst);
3409 }
3410
3411 void Assembler::subl(Address dst, int32_t imm32) {
3412 InstructionMark im(this);
3413 prefix(dst);
3414 emit_arith_operand(0x81, rbp, dst, imm32);
3415 }
3416
3417 void Assembler::subl(Address dst, Register src) {
3418 InstructionMark im(this);
3419 prefix(dst, src);
3420 emit_int8(0x29);
3421 emit_operand(src, dst);
3422 }
3423
3424 void Assembler::subl(Register dst, int32_t imm32) {
3425 prefix(dst);
3426 emit_arith(0x81, 0xE8, dst, imm32);
3427 }
3428
3429 // Force generation of a 4 byte immediate value even if it fits into 8bit
3430 void Assembler::subl_imm32(Register dst, int32_t imm32) {
3431 prefix(dst);
3432 emit_arith_imm32(0x81, 0xE8, dst, imm32);
3433 }
3434
3435 void Assembler::subl(Register dst, Address src) {
3436 InstructionMark im(this);
3437 prefix(src, dst);
3438 emit_int8(0x2B);
3439 emit_operand(dst, src);
3440 }
3441
3442 void Assembler::subl(Register dst, Register src) {
3443 (void) prefix_and_encode(dst->encoding(), src->encoding());
3444 emit_arith(0x2B, 0xC0, dst, src);
3445 }
3446
3447 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
3448 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3449 if (VM_Version::supports_evex()) {
3450 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_F2);
3451 } else {
3452 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
3453 }
3454 }
3455
3456 void Assembler::subsd(XMMRegister dst, Address src) {
3457 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3458 if (VM_Version::supports_evex()) {
3459 tuple_type = EVEX_T1S;
3460 input_size_in_bits = EVEX_64bit;
3461 }
3462 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_F2);
3463 }
3464
3465 void Assembler::subss(XMMRegister dst, XMMRegister src) {
3466 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3467 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
3468 }
3469
3470 void Assembler::subss(XMMRegister dst, Address src) {
3471 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3472 if (VM_Version::supports_evex()) {
3473 tuple_type = EVEX_T1S;
3474 input_size_in_bits = EVEX_32bit;
3475 }
3476 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
3477 }
3478
3479 void Assembler::testb(Register dst, int imm8) {
3480 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
3481 (void) prefix_and_encode(dst->encoding(), true);
3482 emit_arith_b(0xF6, 0xC0, dst, imm8);
3483 }
3484
3485 void Assembler::testl(Register dst, int32_t imm32) {
3486 // not using emit_arith because test
3487 // doesn't support sign-extension of
3488 // 8bit operands
3489 int encode = dst->encoding();
3490 if (encode == 0) {
3491 emit_int8((unsigned char)0xA9);
3492 } else {
3493 encode = prefix_and_encode(encode);
3494 emit_int8((unsigned char)0xF7);
3495 emit_int8((unsigned char)(0xC0 | encode));
3496 }
3497 emit_int32(imm32);
3498 }
3499
3500 void Assembler::testl(Register dst, Register src) {
3501 (void) prefix_and_encode(dst->encoding(), src->encoding());
3502 emit_arith(0x85, 0xC0, dst, src);
3503 }
3504
3505 void Assembler::testl(Register dst, Address src) {
3506 InstructionMark im(this);
3507 prefix(src, dst);
3508 emit_int8((unsigned char)0x85);
3509 emit_operand(dst, src);
3510 }
3511
3512 void Assembler::tzcntl(Register dst, Register src) {
3513 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
3514 emit_int8((unsigned char)0xF3);
3515 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3516 emit_int8(0x0F);
3517 emit_int8((unsigned char)0xBC);
3518 emit_int8((unsigned char)0xC0 | encode);
3519 }
3520
3521 void Assembler::tzcntq(Register dst, Register src) {
3522 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
3523 emit_int8((unsigned char)0xF3);
3524 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3525 emit_int8(0x0F);
3526 emit_int8((unsigned char)0xBC);
3527 emit_int8((unsigned char)(0xC0 | encode));
3528 }
3529
3530 void Assembler::ucomisd(XMMRegister dst, Address src) {
3531 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3532 if (VM_Version::supports_evex()) {
3533 tuple_type = EVEX_T1S;
3534 input_size_in_bits = EVEX_64bit;
3535 emit_simd_arith_nonds_q(0x2E, dst, src, VEX_SIMD_66, true);
3536 } else {
3537 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
3538 }
3539 }
3540
3541 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
3542 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3543 if (VM_Version::supports_evex()) {
3544 emit_simd_arith_nonds_q(0x2E, dst, src, VEX_SIMD_66, true);
3545 } else {
3546 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
3547 }
3548 }
3549
3550 void Assembler::ucomiss(XMMRegister dst, Address src) {
3551 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3552 if (VM_Version::supports_evex()) {
3553 tuple_type = EVEX_T1S;
3554 input_size_in_bits = EVEX_32bit;
3555 }
3556 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE, true);
3557 }
3558
3559 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
3560 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3561 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE, true);
3562 }
3563
3564 void Assembler::xabort(int8_t imm8) {
3565 emit_int8((unsigned char)0xC6);
3566 emit_int8((unsigned char)0xF8);
3567 emit_int8((unsigned char)(imm8 & 0xFF));
3568 }
3569
3570 void Assembler::xaddl(Address dst, Register src) {
3571 InstructionMark im(this);
3572 prefix(dst, src);
3573 emit_int8(0x0F);
3574 emit_int8((unsigned char)0xC1);
3575 emit_operand(src, dst);
3576 }
3577
3578 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
3579 InstructionMark im(this);
3580 relocate(rtype);
3581 if (abort.is_bound()) {
3582 address entry = target(abort);
3583 assert(entry != NULL, "abort entry NULL");
3584 intptr_t offset = entry - pc();
3585 emit_int8((unsigned char)0xC7);
3586 emit_int8((unsigned char)0xF8);
3587 emit_int32(offset - 6); // 2 opcode + 4 address
3588 } else {
3589 abort.add_patch_at(code(), locator());
3590 emit_int8((unsigned char)0xC7);
3591 emit_int8((unsigned char)0xF8);
3592 emit_int32(0);
3593 }
3594 }
3595
3596 void Assembler::xchgl(Register dst, Address src) { // xchg
3597 InstructionMark im(this);
3598 prefix(src, dst);
3599 emit_int8((unsigned char)0x87);
3600 emit_operand(dst, src);
3601 }
3602
3603 void Assembler::xchgl(Register dst, Register src) {
3604 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3605 emit_int8((unsigned char)0x87);
3606 emit_int8((unsigned char)(0xC0 | encode));
3607 }
3608
3609 void Assembler::xend() {
3610 emit_int8((unsigned char)0x0F);
3611 emit_int8((unsigned char)0x01);
3612 emit_int8((unsigned char)0xD5);
3613 }
3614
3615 void Assembler::xgetbv() {
3616 emit_int8(0x0F);
3617 emit_int8(0x01);
3618 emit_int8((unsigned char)0xD0);
3619 }
3620
3621 void Assembler::xorl(Register dst, int32_t imm32) {
3622 prefix(dst);
3623 emit_arith(0x81, 0xF0, dst, imm32);
3624 }
3625
3626 void Assembler::xorl(Register dst, Address src) {
3627 InstructionMark im(this);
3628 prefix(src, dst);
3629 emit_int8(0x33);
3630 emit_operand(dst, src);
3631 }
3632
3633 void Assembler::xorl(Register dst, Register src) {
3634 (void) prefix_and_encode(dst->encoding(), src->encoding());
3635 emit_arith(0x33, 0xC0, dst, src);
3636 }
3637
3638
3639 // AVX 3-operands scalar float-point arithmetic instructions
3640
3641 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
3642 assert(VM_Version::supports_avx(), "");
3643 if (VM_Version::supports_evex()) {
3644 tuple_type = EVEX_T1S;
3645 input_size_in_bits = EVEX_64bit;
3646 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3647 } else {
3648 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3649 }
3650 }
3651
3652 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3653 assert(VM_Version::supports_avx(), "");
3654 if (VM_Version::supports_evex()) {
3655 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3656 } else {
3657 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3658 }
3659 }
3660
3661 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
3662 assert(VM_Version::supports_avx(), "");
3663 if (VM_Version::supports_evex()) {
3664 tuple_type = EVEX_T1S;
3665 input_size_in_bits = EVEX_32bit;
3666 }
3667 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3668 }
3669
3670 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3671 assert(VM_Version::supports_avx(), "");
3672 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3673 }
3674
3675 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
3676 assert(VM_Version::supports_avx(), "");
3677 if (VM_Version::supports_evex()) {
3678 tuple_type = EVEX_T1S;
3679 input_size_in_bits = EVEX_64bit;
3680 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3681 } else {
3682 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3683 }
3684 }
3685
3686 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3687 assert(VM_Version::supports_avx(), "");
3688 if (VM_Version::supports_evex()) {
3689 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3690 } else {
3691 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3692 }
3693 }
3694
3695 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
3696 assert(VM_Version::supports_avx(), "");
3697 if (VM_Version::supports_evex()) {
3698 tuple_type = EVEX_T1S;
3699 input_size_in_bits = EVEX_32bit;
3700 }
3701 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3702 }
3703
3704 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3705 assert(VM_Version::supports_avx(), "");
3706 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3707 }
3708
3709 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
3710 assert(VM_Version::supports_avx(), "");
3711 if (VM_Version::supports_evex()) {
3712 tuple_type = EVEX_T1S;
3713 input_size_in_bits = EVEX_64bit;
3714 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3715 } else {
3716 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3717 }
3718 }
3719
3720 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3721 assert(VM_Version::supports_avx(), "");
3722 if (VM_Version::supports_evex()) {
3723 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3724 } else {
3725 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3726 }
3727 }
3728
3729 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
3730 assert(VM_Version::supports_avx(), "");
3731 if (VM_Version::supports_evex()) {
3732 tuple_type = EVEX_T1S;
3733 input_size_in_bits = EVEX_32bit;
3734 }
3735 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3736 }
3737
3738 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3739 assert(VM_Version::supports_avx(), "");
3740 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3741 }
3742
3743 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
3744 assert(VM_Version::supports_avx(), "");
3745 if (VM_Version::supports_evex()) {
3746 tuple_type = EVEX_T1S;
3747 input_size_in_bits = EVEX_64bit;
3748 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3749 } else {
3750 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3751 }
3752 }
3753
3754 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3755 assert(VM_Version::supports_avx(), "");
3756 if (VM_Version::supports_evex()) {
3757 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3758 } else {
3759 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3760 }
3761 }
3762
3763 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
3764 assert(VM_Version::supports_avx(), "");
3765 if (VM_Version::supports_evex()) {
3766 tuple_type = EVEX_T1S;
3767 input_size_in_bits = EVEX_32bit;
3768 }
3769 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3770 }
3771
3772 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3773 assert(VM_Version::supports_avx(), "");
3774 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3775 }
3776
3777 //====================VECTOR ARITHMETIC=====================================
3778
3779 // Float-point vector arithmetic
3780
3781 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
3782 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3783 if (VM_Version::supports_evex()) {
3784 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_66);
3785 } else {
3786 emit_simd_arith(0x58, dst, src, VEX_SIMD_66);
3787 }
3788 }
3789
3790 void Assembler::addps(XMMRegister dst, XMMRegister src) {
3791 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3792 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE);
3793 }
3794
3795 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3796 assert(VM_Version::supports_avx(), "");
3797 if (VM_Version::supports_evex()) {
3798 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3799 } else {
3800 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3801 }
3802 }
3803
3804 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3805 assert(VM_Version::supports_avx(), "");
3806 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector_len);
3807 }
3808
3809 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3810 assert(VM_Version::supports_avx(), "");
3811 if (VM_Version::supports_evex()) {
3812 tuple_type = EVEX_FV;
3813 input_size_in_bits = EVEX_64bit;
3814 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3815 } else {
3816 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3817 }
3818 }
3819
3820 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3821 assert(VM_Version::supports_avx(), "");
3822 if (VM_Version::supports_evex()) {
3823 tuple_type = EVEX_FV;
3824 input_size_in_bits = EVEX_32bit;
3825 }
3826 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector_len);
3827 }
3828
3829 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
3830 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3831 if (VM_Version::supports_evex()) {
3832 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_66);
3833 } else {
3834 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66);
3835 }
3836 }
3837
3838 void Assembler::subps(XMMRegister dst, XMMRegister src) {
3839 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3840 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE);
3841 }
3842
3843 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3844 assert(VM_Version::supports_avx(), "");
3845 if (VM_Version::supports_evex()) {
3846 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3847 } else {
3848 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3849 }
3850 }
3851
3852 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3853 assert(VM_Version::supports_avx(), "");
3854 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector_len);
3855 }
3856
3857 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3858 assert(VM_Version::supports_avx(), "");
3859 if (VM_Version::supports_evex()) {
3860 tuple_type = EVEX_FV;
3861 input_size_in_bits = EVEX_64bit;
3862 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3863 } else {
3864 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3865 }
3866 }
3867
3868 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3869 assert(VM_Version::supports_avx(), "");
3870 if (VM_Version::supports_evex()) {
3871 tuple_type = EVEX_FV;
3872 input_size_in_bits = EVEX_32bit;
3873 }
3874 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector_len);
3875 }
3876
3877 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
3878 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3879 if (VM_Version::supports_evex()) {
3880 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_66);
3881 } else {
3882 emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
3883 }
3884 }
3885
3886 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
3887 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3888 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE);
3889 }
3890
3891 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3892 assert(VM_Version::supports_avx(), "");
3893 if (VM_Version::supports_evex()) {
3894 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
3895 } else {
3896 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
3897 }
3898 }
3899
3900 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3901 assert(VM_Version::supports_avx(), "");
3902 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector_len);
3903 }
3904
3905 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3906 assert(VM_Version::supports_avx(), "");
3907 if (VM_Version::supports_evex()) {
3908 tuple_type = EVEX_FV;
3909 input_size_in_bits = EVEX_64bit;
3910 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
3911 } else {
3912 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
3913 }
3914 }
3915
3916 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3917 assert(VM_Version::supports_avx(), "");
3918 if (VM_Version::supports_evex()) {
3919 tuple_type = EVEX_FV;
3920 input_size_in_bits = EVEX_32bit;
3921 }
3922 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector_len);
3923 }
3924
3925 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
3926 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3927 if (VM_Version::supports_evex()) {
3928 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_66);
3929 } else {
3930 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66);
3931 }
3932 }
3933
3934 void Assembler::divps(XMMRegister dst, XMMRegister src) {
3935 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3936 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE);
3937 }
3938
3939 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3940 assert(VM_Version::supports_avx(), "");
3941 if (VM_Version::supports_evex()) {
3942 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
3943 } else {
3944 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
3945 }
3946 }
3947
3948 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3949 assert(VM_Version::supports_avx(), "");
3950 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector_len);
3951 }
3952
3953 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3954 assert(VM_Version::supports_avx(), "");
3955 if (VM_Version::supports_evex()) {
3956 tuple_type = EVEX_FV;
3957 input_size_in_bits = EVEX_64bit;
3958 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
3959 } else {
3960 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
3961 }
3962 }
3963
3964 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3965 assert(VM_Version::supports_avx(), "");
3966 if (VM_Version::supports_evex()) {
3967 tuple_type = EVEX_FV;
3968 input_size_in_bits = EVEX_32bit;
3969 }
3970 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector_len);
3971 }
3972
3973 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
3974 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3975 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
3976 emit_simd_arith_q(0x54, dst, src, VEX_SIMD_66);
3977 } else {
3978 emit_simd_arith(0x54, dst, src, VEX_SIMD_66, false, true);
3979 }
3980 }
3981
3982 void Assembler::andps(XMMRegister dst, XMMRegister src) {
3983 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3984 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE, false,
3985 (VM_Version::supports_avx512dq() == false));
3986 }
3987
3988 void Assembler::andps(XMMRegister dst, Address src) {
3989 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3990 if (VM_Version::supports_evex()) {
3991 tuple_type = EVEX_FV;
3992 input_size_in_bits = EVEX_32bit;
3993 }
3994 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE,
3995 false, (VM_Version::supports_avx512dq() == false));
3996 }
3997
3998 void Assembler::andpd(XMMRegister dst, Address src) {
3999 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4000 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4001 tuple_type = EVEX_FV;
4002 input_size_in_bits = EVEX_64bit;
4003 emit_simd_arith_q(0x54, dst, src, VEX_SIMD_66);
4004 } else {
4005 emit_simd_arith(0x54, dst, src, VEX_SIMD_66, false, true);
4006 }
4007 }
4008
4009 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4010 assert(VM_Version::supports_avx(), "");
4011 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4012 emit_vex_arith_q(0x54, dst, nds, src, VEX_SIMD_66, vector_len);
4013 } else {
4014 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector_len, true);
4015 }
4016 }
4017
4018 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4019 assert(VM_Version::supports_avx(), "");
4020 bool legacy_mode = (VM_Version::supports_avx512dq() == false);
4021 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector_len, legacy_mode);
4022 }
4023
4024 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4025 assert(VM_Version::supports_avx(), "");
4026 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4027 tuple_type = EVEX_FV;
4028 input_size_in_bits = EVEX_64bit;
4029 emit_vex_arith_q(0x54, dst, nds, src, VEX_SIMD_66, vector_len);
4030 } else {
4031 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector_len, true);
4032 }
4033 }
4034
4035 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4036 assert(VM_Version::supports_avx(), "");
4037 if (VM_Version::supports_evex()) {
4038 tuple_type = EVEX_FV;
4039 input_size_in_bits = EVEX_32bit;
4040 }
4041 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector_len,
4042 (VM_Version::supports_avx512dq() == false));
4043 }
4044
4045 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
4046 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4047 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4048 emit_simd_arith_q(0x57, dst, src, VEX_SIMD_66);
4049 } else {
4050 emit_simd_arith(0x57, dst, src, VEX_SIMD_66, false, true);
4051 }
4052 }
4053
4054 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
4055 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4056 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE,
4057 false, (VM_Version::supports_avx512dq() == false));
4058 }
4059
4060 void Assembler::xorpd(XMMRegister dst, Address src) {
4061 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4062 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4063 tuple_type = EVEX_FV;
4064 input_size_in_bits = EVEX_64bit;
4065 emit_simd_arith_q(0x57, dst, src, VEX_SIMD_66);
4066 } else {
4067 emit_simd_arith(0x57, dst, src, VEX_SIMD_66, false, true);
4068 }
4069 }
4070
4071 void Assembler::xorps(XMMRegister dst, Address src) {
4072 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4073 if (VM_Version::supports_evex()) {
4074 tuple_type = EVEX_FV;
4075 input_size_in_bits = EVEX_32bit;
4076 }
4077 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE, false,
4078 (VM_Version::supports_avx512dq() == false));
4079 }
4080
4081 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4082 assert(VM_Version::supports_avx(), "");
4083 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4084 emit_vex_arith_q(0x57, dst, nds, src, VEX_SIMD_66, vector_len);
4085 } else {
4086 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector_len, true);
4087 }
4088 }
4089
4090 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4091 assert(VM_Version::supports_avx(), "");
4092 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector_len,
4093 (VM_Version::supports_avx512dq() == false));
4094 }
4095
4096 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4097 assert(VM_Version::supports_avx(), "");
4098 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4099 tuple_type = EVEX_FV;
4100 input_size_in_bits = EVEX_64bit;
4101 emit_vex_arith_q(0x57, dst, nds, src, VEX_SIMD_66, vector_len);
4102 } else {
4103 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector_len, true);
4104 }
4105 }
4106
4107 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4108 assert(VM_Version::supports_avx(), "");
4109 if (VM_Version::supports_evex()) {
4110 tuple_type = EVEX_FV;
4111 input_size_in_bits = EVEX_32bit;
4112 }
4113 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector_len,
4114 (VM_Version::supports_avx512dq() == false));
4115 }
4116
4117 // Integer vector arithmetic
4118 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4119 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4120 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4121 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len,
4122 VEX_OPCODE_0F_38, true, false);
4123 emit_int8(0x01);
4124 emit_int8((unsigned char)(0xC0 | encode));
4125 }
4126
4127 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4128 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4129 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4130 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len,
4131 VEX_OPCODE_0F_38, true, false);
4132 emit_int8(0x02);
4133 emit_int8((unsigned char)(0xC0 | encode));
4134 }
4135
4136 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
4137 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4138 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66);
4139 }
4140
4141 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
4142 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4143 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66);
4144 }
4145
4146 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
4147 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4148 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66);
4149 }
4150
4151 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
4152 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4153 if (VM_Version::supports_evex()) {
4154 emit_simd_arith_q(0xD4, dst, src, VEX_SIMD_66);
4155 } else {
4156 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66);
4157 }
4158 }
4159
4160 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
4161 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4162 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
4163 VEX_OPCODE_0F_38, false, AVX_128bit, true);
4164 emit_int8(0x01);
4165 emit_int8((unsigned char)(0xC0 | encode));
4166 }
4167
4168 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
4169 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4170 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
4171 VEX_OPCODE_0F_38, false, AVX_128bit, true);
4172 emit_int8(0x02);
4173 emit_int8((unsigned char)(0xC0 | encode));
4174 }
4175
4176 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4177 assert(UseAVX > 0, "requires some form of AVX");
4178 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector_len,
4179 (VM_Version::supports_avx512bw() == false));
4180 }
4181
4182 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4183 assert(UseAVX > 0, "requires some form of AVX");
4184 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector_len,
4185 (VM_Version::supports_avx512bw() == false));
4186 }
4187
4188 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4189 assert(UseAVX > 0, "requires some form of AVX");
4190 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector_len);
4191 }
4192
4193 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4194 assert(UseAVX > 0, "requires some form of AVX");
4195 if (VM_Version::supports_evex()) {
4196 emit_vex_arith_q(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4197 } else {
4198 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4199 }
4200 }
4201
4202 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4203 assert(UseAVX > 0, "requires some form of AVX");
4204 if (VM_Version::supports_evex()) {
4205 tuple_type = EVEX_FVM;
4206 }
4207 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector_len);
4208 }
4209
4210 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4211 assert(UseAVX > 0, "requires some form of AVX");
4212 if (VM_Version::supports_evex()) {
4213 tuple_type = EVEX_FVM;
4214 }
4215 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector_len);
4216 }
4217
4218 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4219 assert(UseAVX > 0, "requires some form of AVX");
4220 if (VM_Version::supports_evex()) {
4221 tuple_type = EVEX_FV;
4222 input_size_in_bits = EVEX_32bit;
4223 }
4224 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector_len);
4225 }
4226
4227 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4228 assert(UseAVX > 0, "requires some form of AVX");
4229 if (VM_Version::supports_evex()) {
4230 tuple_type = EVEX_FV;
4231 input_size_in_bits = EVEX_64bit;
4232 emit_vex_arith_q(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4233 } else {
4234 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4235 }
4236 }
4237
4238 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
4239 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4240 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66);
4241 }
4242
4243 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
4244 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4245 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66);
4246 }
4247
4248 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
4249 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4250 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66);
4251 }
4252
4253 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
4254 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4255 if (VM_Version::supports_evex()) {
4256 emit_simd_arith_q(0xFB, dst, src, VEX_SIMD_66);
4257 } else {
4258 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66);
4259 }
4260 }
4261
4262 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4263 assert(UseAVX > 0, "requires some form of AVX");
4264 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector_len,
4265 (VM_Version::supports_avx512bw() == false));
4266 }
4267
4268 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4269 assert(UseAVX > 0, "requires some form of AVX");
4270 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector_len,
4271 (VM_Version::supports_avx512bw() == false));
4272 }
4273
4274 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4275 assert(UseAVX > 0, "requires some form of AVX");
4276 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector_len);
4277 }
4278
4279 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4280 assert(UseAVX > 0, "requires some form of AVX");
4281 if (VM_Version::supports_evex()) {
4282 emit_vex_arith_q(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4283 } else {
4284 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4285 }
4286 }
4287
4288 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4289 assert(UseAVX > 0, "requires some form of AVX");
4290 if (VM_Version::supports_evex()) {
4291 tuple_type = EVEX_FVM;
4292 }
4293 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector_len,
4294 (VM_Version::supports_avx512bw() == false));
4295 }
4296
4297 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4298 assert(UseAVX > 0, "requires some form of AVX");
4299 if (VM_Version::supports_evex()) {
4300 tuple_type = EVEX_FVM;
4301 }
4302 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector_len,
4303 (VM_Version::supports_avx512bw() == false));
4304 }
4305
4306 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4307 assert(UseAVX > 0, "requires some form of AVX");
4308 if (VM_Version::supports_evex()) {
4309 tuple_type = EVEX_FV;
4310 input_size_in_bits = EVEX_32bit;
4311 }
4312 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector_len);
4313 }
4314
4315 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4316 assert(UseAVX > 0, "requires some form of AVX");
4317 if (VM_Version::supports_evex()) {
4318 tuple_type = EVEX_FV;
4319 input_size_in_bits = EVEX_64bit;
4320 emit_vex_arith_q(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4321 } else {
4322 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4323 }
4324 }
4325
4326 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
4327 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4328 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66,
4329 (VM_Version::supports_avx512bw() == false));
4330 }
4331
4332 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
4333 assert(VM_Version::supports_sse4_1(), "");
4334 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66,
4335 false, VEX_OPCODE_0F_38);
4336 emit_int8(0x40);
4337 emit_int8((unsigned char)(0xC0 | encode));
4338 }
4339
4340 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4341 assert(UseAVX > 0, "requires some form of AVX");
4342 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector_len,
4343 (VM_Version::supports_avx512bw() == false));
4344 }
4345
4346 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4347 assert(UseAVX > 0, "requires some form of AVX");
4348 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66,
4349 vector_len, VEX_OPCODE_0F_38);
4350 emit_int8(0x40);
4351 emit_int8((unsigned char)(0xC0 | encode));
4352 }
4353
4354 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4355 assert(UseAVX > 2, "requires some form of AVX");
4356 int src_enc = src->encoding();
4357 int dst_enc = dst->encoding();
4358 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4359 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66,
4360 VEX_OPCODE_0F_38, true, vector_len, false, false);
4361 emit_int8(0x40);
4362 emit_int8((unsigned char)(0xC0 | encode));
4363 }
4364
4365 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4366 assert(UseAVX > 0, "requires some form of AVX");
4367 if (VM_Version::supports_evex()) {
4368 tuple_type = EVEX_FVM;
4369 }
4370 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector_len);
4371 }
4372
4373 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4374 assert(UseAVX > 0, "requires some form of AVX");
4375 if (VM_Version::supports_evex()) {
4376 tuple_type = EVEX_FV;
4377 input_size_in_bits = EVEX_32bit;
4378 }
4379 InstructionMark im(this);
4380 int dst_enc = dst->encoding();
4381 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4382 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66,
4383 VEX_OPCODE_0F_38, false, vector_len);
4384 emit_int8(0x40);
4385 emit_operand(dst, src);
4386 }
4387
4388 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4389 assert(UseAVX > 0, "requires some form of AVX");
4390 if (VM_Version::supports_evex()) {
4391 tuple_type = EVEX_FV;
4392 input_size_in_bits = EVEX_64bit;
4393 }
4394 InstructionMark im(this);
4395 int dst_enc = dst->encoding();
4396 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4397 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, true, vector_len);
4398 emit_int8(0x40);
4399 emit_operand(dst, src);
4400 }
4401
4402 // Shift packed integers left by specified number of bits.
4403 void Assembler::psllw(XMMRegister dst, int shift) {
4404 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4405 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
4406 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F,
4407 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
4408 emit_int8(0x71);
4409 emit_int8((unsigned char)(0xC0 | encode));
4410 emit_int8(shift & 0xFF);
4411 }
4412
4413 void Assembler::pslld(XMMRegister dst, int shift) {
4414 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4415 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
4416 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, false);
4417 emit_int8(0x72);
4418 emit_int8((unsigned char)(0xC0 | encode));
4419 emit_int8(shift & 0xFF);
4420 }
4421
4422 void Assembler::psllq(XMMRegister dst, int shift) {
4423 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4424 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
4425 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F, true);
4426 emit_int8(0x73);
4427 emit_int8((unsigned char)(0xC0 | encode));
4428 emit_int8(shift & 0xFF);
4429 }
4430
4431 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
4432 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4433 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66, false,
4434 (VM_Version::supports_avx512bw() == false));
4435 }
4436
4437 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
4438 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4439 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66);
4440 }
4441
4442 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
4443 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4444 if (VM_Version::supports_evex()) {
4445 emit_simd_arith_q(0xF3, dst, shift, VEX_SIMD_66);
4446 } else {
4447 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66);
4448 }
4449 }
4450
4451 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4452 assert(UseAVX > 0, "requires some form of AVX");
4453 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
4454 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector_len,
4455 (VM_Version::supports_avx512bw() == false));
4456 emit_int8(shift & 0xFF);
4457 }
4458
4459 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4460 assert(UseAVX > 0, "requires some form of AVX");
4461 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
4462 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector_len);
4463 emit_int8(shift & 0xFF);
4464 }
4465
4466 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4467 assert(UseAVX > 0, "requires some form of AVX");
4468 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
4469 if (VM_Version::supports_evex()) {
4470 emit_vex_arith_q(0x73, xmm6, dst, src, VEX_SIMD_66, vector_len);
4471 } else {
4472 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector_len);
4473 }
4474 emit_int8(shift & 0xFF);
4475 }
4476
4477 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4478 assert(UseAVX > 0, "requires some form of AVX");
4479 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector_len,
4480 (VM_Version::supports_avx512bw() == false));
4481 }
4482
4483 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4484 assert(UseAVX > 0, "requires some form of AVX");
4485 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector_len);
4486 }
4487
4488 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4489 assert(UseAVX > 0, "requires some form of AVX");
4490 if (VM_Version::supports_evex()) {
4491 emit_vex_arith_q(0xF3, dst, src, shift, VEX_SIMD_66, vector_len);
4492 } else {
4493 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector_len);
4494 }
4495 }
4496
4497 // Shift packed integers logically right by specified number of bits.
4498 void Assembler::psrlw(XMMRegister dst, int shift) {
4499 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4500 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
4501 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F,
4502 (VM_Version::supports_avx512bw() == false));
4503 emit_int8(0x71);
4504 emit_int8((unsigned char)(0xC0 | encode));
4505 emit_int8(shift & 0xFF);
4506 }
4507
4508 void Assembler::psrld(XMMRegister dst, int shift) {
4509 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4510 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
4511 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, false);
4512 emit_int8(0x72);
4513 emit_int8((unsigned char)(0xC0 | encode));
4514 emit_int8(shift & 0xFF);
4515 }
4516
4517 void Assembler::psrlq(XMMRegister dst, int shift) {
4518 // Do not confuse it with psrldq SSE2 instruction which
4519 // shifts 128 bit value in xmm register by number of bytes.
4520 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4521 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4522 int encode = 0;
4523 if (VM_Version::supports_evex() && VM_Version::supports_avx512bw()) {
4524 encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, true, VEX_OPCODE_0F, false);
4525 } else {
4526 encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F, true);
4527 }
4528 emit_int8(0x73);
4529 emit_int8((unsigned char)(0xC0 | encode));
4530 emit_int8(shift & 0xFF);
4531 }
4532
4533 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
4534 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4535 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66, false,
4536 (VM_Version::supports_avx512bw() == false));
4537 }
4538
4539 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
4540 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4541 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66);
4542 }
4543
4544 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
4545 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4546 if (VM_Version::supports_evex()) {
4547 emit_simd_arith_q(0xD3, dst, shift, VEX_SIMD_66);
4548 } else {
4549 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66);
4550 }
4551 }
4552
4553 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4554 assert(UseAVX > 0, "requires some form of AVX");
4555 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4556 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector_len,
4557 (VM_Version::supports_avx512bw() == false));
4558 emit_int8(shift & 0xFF);
4559 }
4560
4561 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4562 assert(UseAVX > 0, "requires some form of AVX");
4563 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4564 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector_len);
4565 emit_int8(shift & 0xFF);
4566 }
4567
4568 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4569 assert(UseAVX > 0, "requires some form of AVX");
4570 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4571 if (VM_Version::supports_evex()) {
4572 emit_vex_arith_q(0x73, xmm2, dst, src, VEX_SIMD_66, vector_len);
4573 } else {
4574 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector_len);
4575 }
4576 emit_int8(shift & 0xFF);
4577 }
4578
4579 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4580 assert(UseAVX > 0, "requires some form of AVX");
4581 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector_len,
4582 (VM_Version::supports_avx512bw() == false));
4583 }
4584
4585 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4586 assert(UseAVX > 0, "requires some form of AVX");
4587 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector_len);
4588 }
4589
4590 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4591 assert(UseAVX > 0, "requires some form of AVX");
4592 if (VM_Version::supports_evex()) {
4593 emit_vex_arith_q(0xD3, dst, src, shift, VEX_SIMD_66, vector_len);
4594 } else {
4595 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector_len);
4596 }
4597 }
4598
4599 // Shift packed integers arithmetically right by specified number of bits.
4600 void Assembler::psraw(XMMRegister dst, int shift) {
4601 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4602 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4603 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F,
4604 (VM_Version::supports_avx512bw() == false));
4605 emit_int8(0x71);
4606 emit_int8((unsigned char)(0xC0 | encode));
4607 emit_int8(shift & 0xFF);
4608 }
4609
4610 void Assembler::psrad(XMMRegister dst, int shift) {
4611 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4612 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
4613 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, false);
4614 emit_int8(0x72);
4615 emit_int8((unsigned char)(0xC0 | encode));
4616 emit_int8(shift & 0xFF);
4617 }
4618
4619 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
4620 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4621 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66,
4622 (VM_Version::supports_avx512bw() == false));
4623 }
4624
4625 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
4626 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4627 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66);
4628 }
4629
4630 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4631 assert(UseAVX > 0, "requires some form of AVX");
4632 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4633 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector_len,
4634 (VM_Version::supports_avx512bw() == false));
4635 emit_int8(shift & 0xFF);
4636 }
4637
4638 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4639 assert(UseAVX > 0, "requires some form of AVX");
4640 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4641 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector_len);
4642 emit_int8(shift & 0xFF);
4643 }
4644
4645 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4646 assert(UseAVX > 0, "requires some form of AVX");
4647 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector_len,
4648 (VM_Version::supports_avx512bw() == false));
4649 }
4650
4651 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4652 assert(UseAVX > 0, "requires some form of AVX");
4653 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector_len);
4654 }
4655
4656
4657 // AND packed integers
4658 void Assembler::pand(XMMRegister dst, XMMRegister src) {
4659 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4660 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66);
4661 }
4662
4663 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4664 assert(UseAVX > 0, "requires some form of AVX");
4665 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector_len);
4666 }
4667
4668 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4669 assert(UseAVX > 0, "requires some form of AVX");
4670 if (VM_Version::supports_evex()) {
4671 tuple_type = EVEX_FV;
4672 input_size_in_bits = EVEX_32bit;
4673 }
4674 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector_len);
4675 }
4676
4677 void Assembler::por(XMMRegister dst, XMMRegister src) {
4678 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4679 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66);
4680 }
4681
4682 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4683 assert(UseAVX > 0, "requires some form of AVX");
4684 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector_len);
4685 }
4686
4687 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4688 assert(UseAVX > 0, "requires some form of AVX");
4689 if (VM_Version::supports_evex()) {
4690 tuple_type = EVEX_FV;
4691 input_size_in_bits = EVEX_32bit;
4692 }
4693 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector_len);
4694 }
4695
4696 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
4697 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4698 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66);
4699 }
4700
4701 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4702 assert(UseAVX > 0, "requires some form of AVX");
4703 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector_len);
4704 }
4705
4706 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4707 assert(UseAVX > 0, "requires some form of AVX");
4708 if (VM_Version::supports_evex()) {
4709 tuple_type = EVEX_FV;
4710 input_size_in_bits = EVEX_32bit;
4711 }
4712 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector_len);
4713 }
4714
4715
4716 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4717 assert(VM_Version::supports_avx(), "");
4718 int vector_len = AVX_256bit;
4719 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4720 emit_int8(0x18);
4721 emit_int8((unsigned char)(0xC0 | encode));
4722 // 0x00 - insert into lower 128 bits
4723 // 0x01 - insert into upper 128 bits
4724 emit_int8(0x01);
4725 }
4726
4727 void Assembler::vinsertf64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4728 assert(VM_Version::supports_evex(), "");
4729 int vector_len = AVX_512bit;
4730 int src_enc = src->encoding();
4731 int dst_enc = dst->encoding();
4732 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4733 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66,
4734 VEX_OPCODE_0F_3A, true, vector_len, false, false);
4735 emit_int8(0x1A);
4736 emit_int8((unsigned char)(0xC0 | encode));
4737 // 0x00 - insert into lower 256 bits
4738 // 0x01 - insert into upper 256 bits
4739 emit_int8(0x01);
4740 }
4741
4742 void Assembler::vinsertf64x4h(XMMRegister dst, Address src) {
4743 assert(VM_Version::supports_avx(), "");
4744 if (VM_Version::supports_evex()) {
4745 tuple_type = EVEX_T4;
4746 input_size_in_bits = EVEX_64bit;
4747 }
4748 InstructionMark im(this);
4749 int vector_len = AVX_512bit;
4750 assert(dst != xnoreg, "sanity");
4751 int dst_enc = dst->encoding();
4752 // swap src<->dst for encoding
4753 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, true, vector_len);
4754 emit_int8(0x1A);
4755 emit_operand(dst, src);
4756 // 0x01 - insert into upper 128 bits
4757 emit_int8(0x01);
4758 }
4759
4760 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
4761 assert(VM_Version::supports_avx(), "");
4762 if (VM_Version::supports_evex()) {
4763 tuple_type = EVEX_T4;
4764 input_size_in_bits = EVEX_32bit;
4765 }
4766 InstructionMark im(this);
4767 int vector_len = AVX_256bit;
4768 assert(dst != xnoreg, "sanity");
4769 int dst_enc = dst->encoding();
4770 // swap src<->dst for encoding
4771 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4772 emit_int8(0x18);
4773 emit_operand(dst, src);
4774 // 0x01 - insert into upper 128 bits
4775 emit_int8(0x01);
4776 }
4777
4778 void Assembler::vextractf128h(XMMRegister dst, XMMRegister src) {
4779 assert(VM_Version::supports_avx(), "");
4780 int vector_len = AVX_256bit;
4781 int encode = vex_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4782 emit_int8(0x19);
4783 emit_int8((unsigned char)(0xC0 | encode));
4784 // 0x00 - insert into lower 128 bits
4785 // 0x01 - insert into upper 128 bits
4786 emit_int8(0x01);
4787 }
4788
4789 void Assembler::vextractf128h(Address dst, XMMRegister src) {
4790 assert(VM_Version::supports_avx(), "");
4791 if (VM_Version::supports_evex()) {
4792 tuple_type = EVEX_T4;
4793 input_size_in_bits = EVEX_32bit;
4794 }
4795 InstructionMark im(this);
4796 int vector_len = AVX_256bit;
4797 assert(src != xnoreg, "sanity");
4798 int src_enc = src->encoding();
4799 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4800 emit_int8(0x19);
4801 emit_operand(src, dst);
4802 // 0x01 - extract from upper 128 bits
4803 emit_int8(0x01);
4804 }
4805
4806 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4807 assert(VM_Version::supports_avx2(), "");
4808 int vector_len = AVX_256bit;
4809 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4810 emit_int8(0x38);
4811 emit_int8((unsigned char)(0xC0 | encode));
4812 // 0x00 - insert into lower 128 bits
4813 // 0x01 - insert into upper 128 bits
4814 emit_int8(0x01);
4815 }
4816
4817 void Assembler::vinserti64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4818 assert(VM_Version::supports_evex(), "");
4819 int vector_len = AVX_512bit;
4820 int src_enc = src->encoding();
4821 int dst_enc = dst->encoding();
4822 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4823 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4824 VM_Version::supports_avx512dq(), vector_len, false, false);
4825 emit_int8(0x38);
4826 emit_int8((unsigned char)(0xC0 | encode));
4827 // 0x00 - insert into lower 256 bits
4828 // 0x01 - insert into upper 256 bits
4829 emit_int8(0x01);
4830 }
4831
4832 void Assembler::vinserti128h(XMMRegister dst, Address src) {
4833 assert(VM_Version::supports_avx2(), "");
4834 if (VM_Version::supports_evex()) {
4835 tuple_type = EVEX_T4;
4836 input_size_in_bits = EVEX_32bit;
4837 }
4838 InstructionMark im(this);
4839 int vector_len = AVX_256bit;
4840 assert(dst != xnoreg, "sanity");
4841 int dst_enc = dst->encoding();
4842 // swap src<->dst for encoding
4843 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4844 emit_int8(0x38);
4845 emit_operand(dst, src);
4846 // 0x01 - insert into upper 128 bits
4847 emit_int8(0x01);
4848 }
4849
4850 void Assembler::vextracti128h(XMMRegister dst, XMMRegister src) {
4851 assert(VM_Version::supports_avx(), "");
4852 int vector_len = AVX_256bit;
4853 int encode = vex_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4854 emit_int8(0x39);
4855 emit_int8((unsigned char)(0xC0 | encode));
4856 // 0x00 - insert into lower 128 bits
4857 // 0x01 - insert into upper 128 bits
4858 emit_int8(0x01);
4859 }
4860
4861 void Assembler::vextracti128h(Address dst, XMMRegister src) {
4862 assert(VM_Version::supports_avx2(), "");
4863 if (VM_Version::supports_evex()) {
4864 tuple_type = EVEX_T4;
4865 input_size_in_bits = EVEX_32bit;
4866 }
4867 InstructionMark im(this);
4868 int vector_len = AVX_256bit;
4869 assert(src != xnoreg, "sanity");
4870 int src_enc = src->encoding();
4871 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4872 emit_int8(0x39);
4873 emit_operand(src, dst);
4874 // 0x01 - extract from upper 128 bits
4875 emit_int8(0x01);
4876 }
4877
4878 void Assembler::vextracti64x4h(XMMRegister dst, XMMRegister src) {
4879 assert(VM_Version::supports_evex(), "");
4880 int vector_len = AVX_512bit;
4881 int src_enc = src->encoding();
4882 int dst_enc = dst->encoding();
4883 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4884 true, vector_len, false, false);
4885 emit_int8(0x3B);
4886 emit_int8((unsigned char)(0xC0 | encode));
4887 // 0x01 - extract from upper 256 bits
4888 emit_int8(0x01);
4889 }
4890
4891 void Assembler::vextracti64x2h(XMMRegister dst, XMMRegister src, int value) {
4892 assert(VM_Version::supports_evex(), "");
4893 int vector_len = AVX_512bit;
4894 int src_enc = src->encoding();
4895 int dst_enc = dst->encoding();
4896 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4897 VM_Version::supports_avx512dq(), vector_len, false, false);
4898 emit_int8(0x39);
4899 emit_int8((unsigned char)(0xC0 | encode));
4900 // 0x01 - extract from bits 255:128
4901 // 0x02 - extract from bits 383:256
4902 // 0x03 - extract from bits 511:384
4903 emit_int8(value & 0x3);
4904 }
4905
4906 void Assembler::vextractf64x4h(XMMRegister dst, XMMRegister src) {
4907 assert(VM_Version::supports_evex(), "");
4908 int vector_len = AVX_512bit;
4909 int src_enc = src->encoding();
4910 int dst_enc = dst->encoding();
4911 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4912 VM_Version::supports_avx512dq(), vector_len, false, false);
4913 emit_int8(0x1B);
4914 emit_int8((unsigned char)(0xC0 | encode));
4915 // 0x01 - extract from upper 256 bits
4916 emit_int8(0x01);
4917 }
4918
4919 void Assembler::vextractf64x4h(Address dst, XMMRegister src) {
4920 assert(VM_Version::supports_avx2(), "");
4921 tuple_type = EVEX_T4;
4922 input_size_in_bits = EVEX_64bit;
4923 InstructionMark im(this);
4924 int vector_len = AVX_512bit;
4925 assert(src != xnoreg, "sanity");
4926 int src_enc = src->encoding();
4927 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4928 VM_Version::supports_avx512dq(), vector_len);
4929 emit_int8(0x1B);
4930 emit_operand(src, dst);
4931 // 0x01 - extract from upper 128 bits
4932 emit_int8(0x01);
4933 }
4934
4935 void Assembler::vextractf32x4h(XMMRegister dst, XMMRegister src, int value) {
4936 assert(VM_Version::supports_evex(), "");
4937 int vector_len = AVX_512bit;
4938 int src_enc = src->encoding();
4939 int dst_enc = dst->encoding();
4940 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66,
4941 VEX_OPCODE_0F_3A, false, vector_len, false, false);
4942 emit_int8(0x19);
4943 emit_int8((unsigned char)(0xC0 | encode));
4944 // 0x01 - extract from bits 255:128
4945 // 0x02 - extract from bits 383:256
4946 // 0x03 - extract from bits 511:384
4947 emit_int8(value & 0x3);
4948 }
4949
4950 void Assembler::vextractf64x2h(XMMRegister dst, XMMRegister src, int value) {
4951 assert(VM_Version::supports_evex(), "");
4952 int vector_len = AVX_512bit;
4953 int src_enc = src->encoding();
4954 int dst_enc = dst->encoding();
4955 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4956 VM_Version::supports_avx512dq(), vector_len, false, false);
4957 emit_int8(0x19);
4958 emit_int8((unsigned char)(0xC0 | encode));
4959 // 0x01 - extract from bits 255:128
4960 // 0x02 - extract from bits 383:256
4961 // 0x03 - extract from bits 511:384
4962 emit_int8(value & 0x3);
4963 }
4964
4965 // duplicate 4-bytes integer data from src into 8 locations in dest
4966 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
4967 assert(VM_Version::supports_avx2(), "");
4968 int vector_len = AVX_256bit;
4969 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
4970 vector_len, VEX_OPCODE_0F_38, false);
4971 emit_int8(0x58);
4972 emit_int8((unsigned char)(0xC0 | encode));
4973 }
4974
4975 // duplicate 4-bytes integer data from src into 8 locations in dest
4976 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
4977 assert(VM_Version::supports_evex(), "");
4978 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
4979 vector_len, VEX_OPCODE_0F_38, false);
4980 emit_int8(0x58);
4981 emit_int8((unsigned char)(0xC0 | encode));
4982 }
4983
4984 // Carry-Less Multiplication Quadword
4985 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
4986 assert(VM_Version::supports_clmul(), "");
4987 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
4988 VEX_OPCODE_0F_3A, false, AVX_128bit, true);
4989 emit_int8(0x44);
4990 emit_int8((unsigned char)(0xC0 | encode));
4991 emit_int8((unsigned char)mask);
4992 }
4993
4994 // Carry-Less Multiplication Quadword
4995 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
4996 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
4997 int vector_len = AVX_128bit;
4998 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66,
4999 vector_len, VEX_OPCODE_0F_3A, true);
5000 emit_int8(0x44);
5001 emit_int8((unsigned char)(0xC0 | encode));
5002 emit_int8((unsigned char)mask);
5003 }
5004
5005 void Assembler::vzeroupper() {
5006 assert(VM_Version::supports_avx(), "");
5007 if (UseAVX < 3)
5008 {
5009 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
5010 emit_int8(0x77);
5011 }
5012 }
5013
5014
5015 #ifndef _LP64
5016 // 32bit only pieces of the assembler
5017
5018 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
5019 // NO PREFIX AS NEVER 64BIT
5020 InstructionMark im(this);
5021 emit_int8((unsigned char)0x81);
5022 emit_int8((unsigned char)(0xF8 | src1->encoding()));
5023 emit_data(imm32, rspec, 0);
5024 }
5025
5026 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
5027 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
5028 InstructionMark im(this);
5029 emit_int8((unsigned char)0x81);
5030 emit_operand(rdi, src1);
5031 emit_data(imm32, rspec, 0);
5032 }
5033
5034 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
5035 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
5036 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
5037 void Assembler::cmpxchg8(Address adr) {
5038 InstructionMark im(this);
5039 emit_int8(0x0F);
5040 emit_int8((unsigned char)0xC7);
5041 emit_operand(rcx, adr);
5042 }
5043
5044 void Assembler::decl(Register dst) {
5045 // Don't use it directly. Use MacroAssembler::decrementl() instead.
5046 emit_int8(0x48 | dst->encoding());
5047 }
5048
5049 #endif // _LP64
5050
5051 // 64bit typically doesn't use the x87 but needs to for the trig funcs
5052
5053 void Assembler::fabs() {
5054 emit_int8((unsigned char)0xD9);
5055 emit_int8((unsigned char)0xE1);
5056 }
5057
5058 void Assembler::fadd(int i) {
5059 emit_farith(0xD8, 0xC0, i);
5060 }
5061
5062 void Assembler::fadd_d(Address src) {
5063 InstructionMark im(this);
5064 emit_int8((unsigned char)0xDC);
5065 emit_operand32(rax, src);
5066 }
5067
5068 void Assembler::fadd_s(Address src) {
5069 InstructionMark im(this);
5070 emit_int8((unsigned char)0xD8);
5071 emit_operand32(rax, src);
5072 }
5073
5074 void Assembler::fadda(int i) {
5075 emit_farith(0xDC, 0xC0, i);
5076 }
5077
5078 void Assembler::faddp(int i) {
5079 emit_farith(0xDE, 0xC0, i);
5080 }
5081
5082 void Assembler::fchs() {
5083 emit_int8((unsigned char)0xD9);
5084 emit_int8((unsigned char)0xE0);
5085 }
5086
5087 void Assembler::fcom(int i) {
5088 emit_farith(0xD8, 0xD0, i);
5089 }
5090
5091 void Assembler::fcomp(int i) {
5092 emit_farith(0xD8, 0xD8, i);
5093 }
5094
5095 void Assembler::fcomp_d(Address src) {
5096 InstructionMark im(this);
5097 emit_int8((unsigned char)0xDC);
5098 emit_operand32(rbx, src);
5099 }
5100
5101 void Assembler::fcomp_s(Address src) {
5102 InstructionMark im(this);
5103 emit_int8((unsigned char)0xD8);
5104 emit_operand32(rbx, src);
5105 }
5106
5107 void Assembler::fcompp() {
5108 emit_int8((unsigned char)0xDE);
5109 emit_int8((unsigned char)0xD9);
5110 }
5111
5112 void Assembler::fcos() {
5113 emit_int8((unsigned char)0xD9);
5114 emit_int8((unsigned char)0xFF);
5115 }
5116
5117 void Assembler::fdecstp() {
5118 emit_int8((unsigned char)0xD9);
5119 emit_int8((unsigned char)0xF6);
5120 }
5121
5122 void Assembler::fdiv(int i) {
5123 emit_farith(0xD8, 0xF0, i);
5124 }
5125
5126 void Assembler::fdiv_d(Address src) {
5127 InstructionMark im(this);
5128 emit_int8((unsigned char)0xDC);
5129 emit_operand32(rsi, src);
5130 }
5131
5132 void Assembler::fdiv_s(Address src) {
5133 InstructionMark im(this);
5134 emit_int8((unsigned char)0xD8);
5135 emit_operand32(rsi, src);
5136 }
5137
5138 void Assembler::fdiva(int i) {
5139 emit_farith(0xDC, 0xF8, i);
5140 }
5141
5142 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
5143 // is erroneous for some of the floating-point instructions below.
5144
5145 void Assembler::fdivp(int i) {
5146 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
5147 }
5148
5149 void Assembler::fdivr(int i) {
5150 emit_farith(0xD8, 0xF8, i);
5151 }
5152
5153 void Assembler::fdivr_d(Address src) {
5154 InstructionMark im(this);
5155 emit_int8((unsigned char)0xDC);
5156 emit_operand32(rdi, src);
5157 }
5158
5159 void Assembler::fdivr_s(Address src) {
5160 InstructionMark im(this);
5161 emit_int8((unsigned char)0xD8);
5162 emit_operand32(rdi, src);
5163 }
5164
5165 void Assembler::fdivra(int i) {
5166 emit_farith(0xDC, 0xF0, i);
5167 }
5168
5169 void Assembler::fdivrp(int i) {
5170 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
5171 }
5172
5173 void Assembler::ffree(int i) {
5174 emit_farith(0xDD, 0xC0, i);
5175 }
5176
5177 void Assembler::fild_d(Address adr) {
5178 InstructionMark im(this);
5179 emit_int8((unsigned char)0xDF);
5180 emit_operand32(rbp, adr);
5181 }
5182
5183 void Assembler::fild_s(Address adr) {
5184 InstructionMark im(this);
5185 emit_int8((unsigned char)0xDB);
5186 emit_operand32(rax, adr);
5187 }
5188
5189 void Assembler::fincstp() {
5190 emit_int8((unsigned char)0xD9);
5191 emit_int8((unsigned char)0xF7);
5192 }
5193
5194 void Assembler::finit() {
5195 emit_int8((unsigned char)0x9B);
5196 emit_int8((unsigned char)0xDB);
5197 emit_int8((unsigned char)0xE3);
5198 }
5199
5200 void Assembler::fist_s(Address adr) {
5201 InstructionMark im(this);
5202 emit_int8((unsigned char)0xDB);
5203 emit_operand32(rdx, adr);
5204 }
5205
5206 void Assembler::fistp_d(Address adr) {
5207 InstructionMark im(this);
5208 emit_int8((unsigned char)0xDF);
5209 emit_operand32(rdi, adr);
5210 }
5211
5212 void Assembler::fistp_s(Address adr) {
5213 InstructionMark im(this);
5214 emit_int8((unsigned char)0xDB);
5215 emit_operand32(rbx, adr);
5216 }
5217
5218 void Assembler::fld1() {
5219 emit_int8((unsigned char)0xD9);
5220 emit_int8((unsigned char)0xE8);
5221 }
5222
5223 void Assembler::fld_d(Address adr) {
5224 InstructionMark im(this);
5225 emit_int8((unsigned char)0xDD);
5226 emit_operand32(rax, adr);
5227 }
5228
5229 void Assembler::fld_s(Address adr) {
5230 InstructionMark im(this);
5231 emit_int8((unsigned char)0xD9);
5232 emit_operand32(rax, adr);
5233 }
5234
5235
5236 void Assembler::fld_s(int index) {
5237 emit_farith(0xD9, 0xC0, index);
5238 }
5239
5240 void Assembler::fld_x(Address adr) {
5241 InstructionMark im(this);
5242 emit_int8((unsigned char)0xDB);
5243 emit_operand32(rbp, adr);
5244 }
5245
5246 void Assembler::fldcw(Address src) {
5247 InstructionMark im(this);
5248 emit_int8((unsigned char)0xD9);
5249 emit_operand32(rbp, src);
5250 }
5251
5252 void Assembler::fldenv(Address src) {
5253 InstructionMark im(this);
5254 emit_int8((unsigned char)0xD9);
5255 emit_operand32(rsp, src);
5256 }
5257
5258 void Assembler::fldlg2() {
5259 emit_int8((unsigned char)0xD9);
5260 emit_int8((unsigned char)0xEC);
5261 }
5262
5263 void Assembler::fldln2() {
5264 emit_int8((unsigned char)0xD9);
5265 emit_int8((unsigned char)0xED);
5266 }
5267
5268 void Assembler::fldz() {
5269 emit_int8((unsigned char)0xD9);
5270 emit_int8((unsigned char)0xEE);
5271 }
5272
5273 void Assembler::flog() {
5274 fldln2();
5275 fxch();
5276 fyl2x();
5277 }
5278
5279 void Assembler::flog10() {
5280 fldlg2();
5281 fxch();
5282 fyl2x();
5283 }
5284
5285 void Assembler::fmul(int i) {
5286 emit_farith(0xD8, 0xC8, i);
5287 }
5288
5289 void Assembler::fmul_d(Address src) {
5290 InstructionMark im(this);
5291 emit_int8((unsigned char)0xDC);
5292 emit_operand32(rcx, src);
5293 }
5294
5295 void Assembler::fmul_s(Address src) {
5296 InstructionMark im(this);
5297 emit_int8((unsigned char)0xD8);
5298 emit_operand32(rcx, src);
5299 }
5300
5301 void Assembler::fmula(int i) {
5302 emit_farith(0xDC, 0xC8, i);
5303 }
5304
5305 void Assembler::fmulp(int i) {
5306 emit_farith(0xDE, 0xC8, i);
5307 }
5308
5309 void Assembler::fnsave(Address dst) {
5310 InstructionMark im(this);
5311 emit_int8((unsigned char)0xDD);
5312 emit_operand32(rsi, dst);
5313 }
5314
5315 void Assembler::fnstcw(Address src) {
5316 InstructionMark im(this);
5317 emit_int8((unsigned char)0x9B);
5318 emit_int8((unsigned char)0xD9);
5319 emit_operand32(rdi, src);
5320 }
5321
5322 void Assembler::fnstsw_ax() {
5323 emit_int8((unsigned char)0xDF);
5324 emit_int8((unsigned char)0xE0);
5325 }
5326
5327 void Assembler::fprem() {
5328 emit_int8((unsigned char)0xD9);
5329 emit_int8((unsigned char)0xF8);
5330 }
5331
5332 void Assembler::fprem1() {
5333 emit_int8((unsigned char)0xD9);
5334 emit_int8((unsigned char)0xF5);
5335 }
5336
5337 void Assembler::frstor(Address src) {
5338 InstructionMark im(this);
5339 emit_int8((unsigned char)0xDD);
5340 emit_operand32(rsp, src);
5341 }
5342
5343 void Assembler::fsin() {
5344 emit_int8((unsigned char)0xD9);
5345 emit_int8((unsigned char)0xFE);
5346 }
5347
5348 void Assembler::fsqrt() {
5349 emit_int8((unsigned char)0xD9);
5350 emit_int8((unsigned char)0xFA);
5351 }
5352
5353 void Assembler::fst_d(Address adr) {
5354 InstructionMark im(this);
5355 emit_int8((unsigned char)0xDD);
5356 emit_operand32(rdx, adr);
5357 }
5358
5359 void Assembler::fst_s(Address adr) {
5360 InstructionMark im(this);
5361 emit_int8((unsigned char)0xD9);
5362 emit_operand32(rdx, adr);
5363 }
5364
5365 void Assembler::fstp_d(Address adr) {
5366 InstructionMark im(this);
5367 emit_int8((unsigned char)0xDD);
5368 emit_operand32(rbx, adr);
5369 }
5370
5371 void Assembler::fstp_d(int index) {
5372 emit_farith(0xDD, 0xD8, index);
5373 }
5374
5375 void Assembler::fstp_s(Address adr) {
5376 InstructionMark im(this);
5377 emit_int8((unsigned char)0xD9);
5378 emit_operand32(rbx, adr);
5379 }
5380
5381 void Assembler::fstp_x(Address adr) {
5382 InstructionMark im(this);
5383 emit_int8((unsigned char)0xDB);
5384 emit_operand32(rdi, adr);
5385 }
5386
5387 void Assembler::fsub(int i) {
5388 emit_farith(0xD8, 0xE0, i);
5389 }
5390
5391 void Assembler::fsub_d(Address src) {
5392 InstructionMark im(this);
5393 emit_int8((unsigned char)0xDC);
5394 emit_operand32(rsp, src);
5395 }
5396
5397 void Assembler::fsub_s(Address src) {
5398 InstructionMark im(this);
5399 emit_int8((unsigned char)0xD8);
5400 emit_operand32(rsp, src);
5401 }
5402
5403 void Assembler::fsuba(int i) {
5404 emit_farith(0xDC, 0xE8, i);
5405 }
5406
5407 void Assembler::fsubp(int i) {
5408 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
5409 }
5410
5411 void Assembler::fsubr(int i) {
5412 emit_farith(0xD8, 0xE8, i);
5413 }
5414
5415 void Assembler::fsubr_d(Address src) {
5416 InstructionMark im(this);
5417 emit_int8((unsigned char)0xDC);
5418 emit_operand32(rbp, src);
5419 }
5420
5421 void Assembler::fsubr_s(Address src) {
5422 InstructionMark im(this);
5423 emit_int8((unsigned char)0xD8);
5424 emit_operand32(rbp, src);
5425 }
5426
5427 void Assembler::fsubra(int i) {
5428 emit_farith(0xDC, 0xE0, i);
5429 }
5430
5431 void Assembler::fsubrp(int i) {
5432 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
5433 }
5434
5435 void Assembler::ftan() {
5436 emit_int8((unsigned char)0xD9);
5437 emit_int8((unsigned char)0xF2);
5438 emit_int8((unsigned char)0xDD);
5439 emit_int8((unsigned char)0xD8);
5440 }
5441
5442 void Assembler::ftst() {
5443 emit_int8((unsigned char)0xD9);
5444 emit_int8((unsigned char)0xE4);
5445 }
5446
5447 void Assembler::fucomi(int i) {
5448 // make sure the instruction is supported (introduced for P6, together with cmov)
5449 guarantee(VM_Version::supports_cmov(), "illegal instruction");
5450 emit_farith(0xDB, 0xE8, i);
5451 }
5452
5453 void Assembler::fucomip(int i) {
5454 // make sure the instruction is supported (introduced for P6, together with cmov)
5455 guarantee(VM_Version::supports_cmov(), "illegal instruction");
5456 emit_farith(0xDF, 0xE8, i);
5457 }
5458
5459 void Assembler::fwait() {
5460 emit_int8((unsigned char)0x9B);
5461 }
5462
5463 void Assembler::fxch(int i) {
5464 emit_farith(0xD9, 0xC8, i);
5465 }
5466
5467 void Assembler::fyl2x() {
5468 emit_int8((unsigned char)0xD9);
5469 emit_int8((unsigned char)0xF1);
5470 }
5471
5472 void Assembler::frndint() {
5473 emit_int8((unsigned char)0xD9);
5474 emit_int8((unsigned char)0xFC);
5475 }
5476
5477 void Assembler::f2xm1() {
5478 emit_int8((unsigned char)0xD9);
5479 emit_int8((unsigned char)0xF0);
5480 }
5481
5482 void Assembler::fldl2e() {
5483 emit_int8((unsigned char)0xD9);
5484 emit_int8((unsigned char)0xEA);
5485 }
5486
5487 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
5488 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
5489 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
5490 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
5491
5492 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
5493 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
5494 if (pre > 0) {
5495 emit_int8(simd_pre[pre]);
5496 }
5497 if (rex_w) {
5498 prefixq(adr, xreg);
5499 } else {
5500 prefix(adr, xreg);
5501 }
5502 if (opc > 0) {
5503 emit_int8(0x0F);
5504 int opc2 = simd_opc[opc];
5505 if (opc2 > 0) {
5506 emit_int8(opc2);
5507 }
5508 }
5509 }
5510
5511 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
5512 if (pre > 0) {
5513 emit_int8(simd_pre[pre]);
5514 }
5515 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) :
5516 prefix_and_encode(dst_enc, src_enc);
5517 if (opc > 0) {
5518 emit_int8(0x0F);
5519 int opc2 = simd_opc[opc];
5520 if (opc2 > 0) {
5521 emit_int8(opc2);
5522 }
5523 }
5524 return encode;
5525 }
5526
5527
5528 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, int vector_len) {
5529 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
5530 prefix(VEX_3bytes);
5531
5532 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
5533 byte1 = (~byte1) & 0xE0;
5534 byte1 |= opc;
5535 emit_int8(byte1);
5536
5537 int byte2 = ((~nds_enc) & 0xf) << 3;
5538 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
5539 emit_int8(byte2);
5540 } else {
5541 prefix(VEX_2bytes);
5542
5543 int byte1 = vex_r ? VEX_R : 0;
5544 byte1 = (~byte1) & 0x80;
5545 byte1 |= ((~nds_enc) & 0xf) << 3;
5546 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
5547 emit_int8(byte1);
5548 }
5549 }
5550
5551 // This is a 4 byte encoding
5552 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, bool evex_r, bool evex_v,
5553 int nds_enc, VexSimdPrefix pre, VexOpcode opc,
5554 bool is_extended_context, bool is_merge_context,
5555 int vector_len, bool no_mask_reg ){
5556 // EVEX 0x62 prefix
5557 prefix(EVEX_4bytes);
5558 evex_encoding = (vex_w ? VEX_W : 0) | (evex_r ? EVEX_Rb : 0);
5559
5560 // P0: byte 2, initialized to RXBR`00mm
5561 // instead of not'd
5562 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
5563 byte2 = (~byte2) & 0xF0;
5564 // confine opc opcode extensions in mm bits to lower two bits
5565 // of form {0F, 0F_38, 0F_3A}
5566 byte2 |= opc;
5567 emit_int8(byte2);
5568
5569 // P1: byte 3 as Wvvvv1pp
5570 int byte3 = ((~nds_enc) & 0xf) << 3;
5571 // p[10] is always 1
5572 byte3 |= EVEX_F;
5573 byte3 |= (vex_w & 1) << 7;
5574 // confine pre opcode extensions in pp bits to lower two bits
5575 // of form {66, F3, F2}
5576 byte3 |= pre;
5577 emit_int8(byte3);
5578
5579 // P2: byte 4 as zL'Lbv'aaa
5580 int byte4 = (no_mask_reg) ? 0 : 1; // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
5581 // EVEX.v` for extending EVEX.vvvv or VIDX
5582 byte4 |= (evex_v ? 0: EVEX_V);
5583 // third EXEC.b for broadcast actions
5584 byte4 |= (is_extended_context ? EVEX_Rb : 0);
5585 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
5586 byte4 |= ((vector_len) & 0x3) << 5;
5587 // last is EVEX.z for zero/merge actions
5588 byte4 |= (is_merge_context ? EVEX_Z : 0);
5589 emit_int8(byte4);
5590 }
5591
5592 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre,
5593 VexOpcode opc, bool vex_w, int vector_len, bool legacy_mode, bool no_mask_reg) {
5594 bool vex_r = (xreg_enc >= 8);
5595 bool vex_b = adr.base_needs_rex();
5596 bool vex_x = adr.index_needs_rex();
5597 avx_vector_len = vector_len;
5598
5599 // if vector length is turned off, revert to AVX for vectors smaller than AVX_512bit
5600 if (VM_Version::supports_avx512vl() == false) {
5601 switch (vector_len) {
5602 case AVX_128bit:
5603 case AVX_256bit:
5604 legacy_mode = true;
5605 break;
5606 }
5607 }
5608
5609 if ((UseAVX > 2) && (legacy_mode == false))
5610 {
5611 bool evex_r = (xreg_enc >= 16);
5612 bool evex_v = (nds_enc >= 16);
5613 is_evex_instruction = true;
5614 evex_prefix(vex_r, vex_b, vex_x, vex_w, evex_r, evex_v, nds_enc, pre, opc, false, false, vector_len, no_mask_reg);
5615 } else {
5616 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector_len);
5617 }
5618 }
5619
5620 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,
5621 bool vex_w, int vector_len, bool legacy_mode, bool no_mask_reg ) {
5622 bool vex_r = (dst_enc >= 8);
5623 bool vex_b = (src_enc >= 8);
5624 bool vex_x = false;
5625 avx_vector_len = vector_len;
5626
5627 // if vector length is turned off, revert to AVX for vectors smaller than AVX_512bit
5628 if (VM_Version::supports_avx512vl() == false) {
5629 switch (vector_len) {
5630 case AVX_128bit:
5631 case AVX_256bit:
5632 legacy_mode = true;
5633 break;
5634 }
5635 }
5636
5637 if ((UseAVX > 2) && (legacy_mode == false))
5638 {
5639 bool evex_r = (dst_enc >= 16);
5640 bool evex_v = (nds_enc >= 16);
5641 // can use vex_x as bank extender on rm encoding
5642 vex_x = (src_enc >= 16);
5643 evex_prefix(vex_r, vex_b, vex_x, vex_w, evex_r, evex_v, nds_enc, pre, opc, false, false, vector_len, no_mask_reg);
5644 } else {
5645 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector_len);
5646 }
5647
5648 // return modrm byte components for operands
5649 return (((dst_enc & 7) << 3) | (src_enc & 7));
5650 }
5651
5652
5653 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
5654 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len, bool legacy_mode) {
5655 if (UseAVX > 0) {
5656 int xreg_enc = xreg->encoding();
5657 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5658 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector_len, legacy_mode, no_mask_reg);
5659 } else {
5660 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
5661 rex_prefix(adr, xreg, pre, opc, rex_w);
5662 }
5663 }
5664
5665 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
5666 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len, bool legacy_mode) {
5667 int dst_enc = dst->encoding();
5668 int src_enc = src->encoding();
5669 if (UseAVX > 0) {
5670 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5671 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, legacy_mode, no_mask_reg);
5672 } else {
5673 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
5674 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w);
5675 }
5676 }
5677
5678 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, KRegister src, VexSimdPrefix pre,
5679 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len) {
5680 int dst_enc = dst->encoding();
5681 int src_enc = src->encoding();
5682 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5683 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, true, no_mask_reg);
5684 }
5685
5686 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, Register src, VexSimdPrefix pre,
5687 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len) {
5688 int dst_enc = dst->encoding();
5689 int src_enc = src->encoding();
5690 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5691 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, true, no_mask_reg);
5692 }
5693
5694 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
5695 InstructionMark im(this);
5696 simd_prefix(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, false, AVX_128bit, legacy_mode);
5697 emit_int8(opcode);
5698 emit_operand(dst, src);
5699 }
5700
5701 void Assembler::emit_simd_arith_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg) {
5702 InstructionMark im(this);
5703 simd_prefix_q(dst, dst, src, pre, no_mask_reg);
5704 emit_int8(opcode);
5705 emit_operand(dst, src);
5706 }
5707
5708 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
5709 int encode = simd_prefix_and_encode(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, false, AVX_128bit, legacy_mode);
5710 emit_int8(opcode);
5711 emit_int8((unsigned char)(0xC0 | encode));
5712 }
5713
5714 void Assembler::emit_simd_arith_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg) {
5715 int encode = simd_prefix_and_encode(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, true, AVX_128bit);
5716 emit_int8(opcode);
5717 emit_int8((unsigned char)(0xC0 | encode));
5718 }
5719
5720 // Versions with no second source register (non-destructive source).
5721 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool opNoRegMask) {
5722 InstructionMark im(this);
5723 simd_prefix(dst, xnoreg, src, pre, opNoRegMask);
5724 emit_int8(opcode);
5725 emit_operand(dst, src);
5726 }
5727
5728 void Assembler::emit_simd_arith_nonds_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool opNoRegMask) {
5729 InstructionMark im(this);
5730 simd_prefix_q(dst, xnoreg, src, pre, opNoRegMask);
5731 emit_int8(opcode);
5732 emit_operand(dst, src);
5733 }
5734
5735 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
5736 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre, no_mask_reg, VEX_OPCODE_0F, legacy_mode, AVX_128bit);
5737 emit_int8(opcode);
5738 emit_int8((unsigned char)(0xC0 | encode));
5739 }
5740
5741 void Assembler::emit_simd_arith_nonds_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg) {
5742 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre, no_mask_reg, VEX_OPCODE_0F, true, AVX_128bit);
5743 emit_int8(opcode);
5744 emit_int8((unsigned char)(0xC0 | encode));
5745 }
5746
5747 // 3-operands AVX instructions
5748 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, Address src,
5749 VexSimdPrefix pre, int vector_len, bool no_mask_reg, bool legacy_mode) {
5750 InstructionMark im(this);
5751 vex_prefix(dst, nds, src, pre, vector_len, no_mask_reg, legacy_mode);
5752 emit_int8(opcode);
5753 emit_operand(dst, src);
5754 }
5755
5756 void Assembler::emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds,
5757 Address src, VexSimdPrefix pre, int vector_len, bool no_mask_reg) {
5758 InstructionMark im(this);
5759 vex_prefix_q(dst, nds, src, pre, vector_len, no_mask_reg);
5760 emit_int8(opcode);
5761 emit_operand(dst, src);
5762 }
5763
5764 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
5765 VexSimdPrefix pre, int vector_len, bool no_mask_reg, bool legacy_mode) {
5766 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector_len, VEX_OPCODE_0F, false, no_mask_reg);
5767 emit_int8(opcode);
5768 emit_int8((unsigned char)(0xC0 | encode));
5769 }
5770
5771 void Assembler::emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
5772 VexSimdPrefix pre, int vector_len, bool no_mask_reg) {
5773 int src_enc = src->encoding();
5774 int dst_enc = dst->encoding();
5775 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5776 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, VEX_OPCODE_0F, true, vector_len, false, no_mask_reg);
5777 emit_int8(opcode);
5778 emit_int8((unsigned char)(0xC0 | encode));
5779 }
5780
5781 #ifndef _LP64
5782
5783 void Assembler::incl(Register dst) {
5784 // Don't use it directly. Use MacroAssembler::incrementl() instead.
5785 emit_int8(0x40 | dst->encoding());
5786 }
5787
5788 void Assembler::lea(Register dst, Address src) {
5789 leal(dst, src);
5790 }
5791
5792 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
5793 InstructionMark im(this);
5794 emit_int8((unsigned char)0xC7);
5795 emit_operand(rax, dst);
5796 emit_data((int)imm32, rspec, 0);
5797 }
5798
5799 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
5800 InstructionMark im(this);
5801 int encode = prefix_and_encode(dst->encoding());
5802 emit_int8((unsigned char)(0xB8 | encode));
5803 emit_data((int)imm32, rspec, 0);
5804 }
5805
5806 void Assembler::popa() { // 32bit
5807 emit_int8(0x61);
5808 }
5809
5810 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
5811 InstructionMark im(this);
5812 emit_int8(0x68);
5813 emit_data(imm32, rspec, 0);
5814 }
5815
5816 void Assembler::pusha() { // 32bit
5817 emit_int8(0x60);
5818 }
5819
5820 void Assembler::set_byte_if_not_zero(Register dst) {
5821 emit_int8(0x0F);
5822 emit_int8((unsigned char)0x95);
5823 emit_int8((unsigned char)(0xE0 | dst->encoding()));
5824 }
5825
5826 void Assembler::shldl(Register dst, Register src) {
5827 emit_int8(0x0F);
5828 emit_int8((unsigned char)0xA5);
5829 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
5830 }
5831
5832 void Assembler::shrdl(Register dst, Register src) {
5833 emit_int8(0x0F);
5834 emit_int8((unsigned char)0xAD);
5835 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
5836 }
5837
5838 #else // LP64
5839
5840 void Assembler::set_byte_if_not_zero(Register dst) {
5841 int enc = prefix_and_encode(dst->encoding(), true);
5842 emit_int8(0x0F);
5843 emit_int8((unsigned char)0x95);
5844 emit_int8((unsigned char)(0xE0 | enc));
5845 }
5846
5847 // 64bit only pieces of the assembler
5848 // This should only be used by 64bit instructions that can use rip-relative
5849 // it cannot be used by instructions that want an immediate value.
5850
5851 bool Assembler::reachable(AddressLiteral adr) {
5852 int64_t disp;
5853 // None will force a 64bit literal to the code stream. Likely a placeholder
5854 // for something that will be patched later and we need to certain it will
5855 // always be reachable.
5856 if (adr.reloc() == relocInfo::none) {
5857 return false;
5858 }
5859 if (adr.reloc() == relocInfo::internal_word_type) {
5860 // This should be rip relative and easily reachable.
5861 return true;
5862 }
5863 if (adr.reloc() == relocInfo::virtual_call_type ||
5864 adr.reloc() == relocInfo::opt_virtual_call_type ||
5865 adr.reloc() == relocInfo::static_call_type ||
5866 adr.reloc() == relocInfo::static_stub_type ) {
5867 // This should be rip relative within the code cache and easily
5868 // reachable until we get huge code caches. (At which point
5869 // ic code is going to have issues).
5870 return true;
5871 }
5872 if (adr.reloc() != relocInfo::external_word_type &&
5873 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
5874 adr.reloc() != relocInfo::poll_type && // relocs to identify them
5875 adr.reloc() != relocInfo::runtime_call_type ) {
5876 return false;
5877 }
5878
5879 // Stress the correction code
5880 if (ForceUnreachable) {
5881 // Must be runtimecall reloc, see if it is in the codecache
5882 // Flipping stuff in the codecache to be unreachable causes issues
5883 // with things like inline caches where the additional instructions
5884 // are not handled.
5885 if (CodeCache::find_blob(adr._target) == NULL) {
5886 return false;
5887 }
5888 }
5889 // For external_word_type/runtime_call_type if it is reachable from where we
5890 // are now (possibly a temp buffer) and where we might end up
5891 // anywhere in the codeCache then we are always reachable.
5892 // This would have to change if we ever save/restore shared code
5893 // to be more pessimistic.
5894 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
5895 if (!is_simm32(disp)) return false;
5896 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
5897 if (!is_simm32(disp)) return false;
5898
5899 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
5900
5901 // Because rip relative is a disp + address_of_next_instruction and we
5902 // don't know the value of address_of_next_instruction we apply a fudge factor
5903 // to make sure we will be ok no matter the size of the instruction we get placed into.
5904 // We don't have to fudge the checks above here because they are already worst case.
5905
5906 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
5907 // + 4 because better safe than sorry.
5908 const int fudge = 12 + 4;
5909 if (disp < 0) {
5910 disp -= fudge;
5911 } else {
5912 disp += fudge;
5913 }
5914 return is_simm32(disp);
5915 }
5916
5917 // Check if the polling page is not reachable from the code cache using rip-relative
5918 // addressing.
5919 bool Assembler::is_polling_page_far() {
5920 intptr_t addr = (intptr_t)os::get_polling_page();
5921 return ForceUnreachable ||
5922 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
5923 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
5924 }
5925
5926 void Assembler::emit_data64(jlong data,
5927 relocInfo::relocType rtype,
5928 int format) {
5929 if (rtype == relocInfo::none) {
5930 emit_int64(data);
5931 } else {
5932 emit_data64(data, Relocation::spec_simple(rtype), format);
5933 }
5934 }
5935
5936 void Assembler::emit_data64(jlong data,
5937 RelocationHolder const& rspec,
5938 int format) {
5939 assert(imm_operand == 0, "default format must be immediate in this file");
5940 assert(imm_operand == format, "must be immediate");
5941 assert(inst_mark() != NULL, "must be inside InstructionMark");
5942 // Do not use AbstractAssembler::relocate, which is not intended for
5943 // embedded words. Instead, relocate to the enclosing instruction.
5944 code_section()->relocate(inst_mark(), rspec, format);
5945 #ifdef ASSERT
5946 check_relocation(rspec, format);
5947 #endif
5948 emit_int64(data);
5949 }
5950
5951 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
5952 if (reg_enc >= 8) {
5953 prefix(REX_B);
5954 reg_enc -= 8;
5955 } else if (byteinst && reg_enc >= 4) {
5956 prefix(REX);
5957 }
5958 return reg_enc;
5959 }
5960
5961 int Assembler::prefixq_and_encode(int reg_enc) {
5962 if (reg_enc < 8) {
5963 prefix(REX_W);
5964 } else {
5965 prefix(REX_WB);
5966 reg_enc -= 8;
5967 }
5968 return reg_enc;
5969 }
5970
5971 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
5972 if (dst_enc < 8) {
5973 if (src_enc >= 8) {
5974 prefix(REX_B);
5975 src_enc -= 8;
5976 } else if (byteinst && src_enc >= 4) {
5977 prefix(REX);
5978 }
5979 } else {
5980 if (src_enc < 8) {
5981 prefix(REX_R);
5982 } else {
5983 prefix(REX_RB);
5984 src_enc -= 8;
5985 }
5986 dst_enc -= 8;
5987 }
5988 return dst_enc << 3 | src_enc;
5989 }
5990
5991 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
5992 if (dst_enc < 8) {
5993 if (src_enc < 8) {
5994 prefix(REX_W);
5995 } else {
5996 prefix(REX_WB);
5997 src_enc -= 8;
5998 }
5999 } else {
6000 if (src_enc < 8) {
6001 prefix(REX_WR);
6002 } else {
6003 prefix(REX_WRB);
6004 src_enc -= 8;
6005 }
6006 dst_enc -= 8;
6007 }
6008 return dst_enc << 3 | src_enc;
6009 }
6010
6011 void Assembler::prefix(Register reg) {
6012 if (reg->encoding() >= 8) {
6013 prefix(REX_B);
6014 }
6015 }
6016
6017 void Assembler::prefix(Address adr) {
6018 if (adr.base_needs_rex()) {
6019 if (adr.index_needs_rex()) {
6020 prefix(REX_XB);
6021 } else {
6022 prefix(REX_B);
6023 }
6024 } else {
6025 if (adr.index_needs_rex()) {
6026 prefix(REX_X);
6027 }
6028 }
6029 }
6030
6031 void Assembler::prefixq(Address adr) {
6032 if (adr.base_needs_rex()) {
6033 if (adr.index_needs_rex()) {
6034 prefix(REX_WXB);
6035 } else {
6036 prefix(REX_WB);
6037 }
6038 } else {
6039 if (adr.index_needs_rex()) {
6040 prefix(REX_WX);
6041 } else {
6042 prefix(REX_W);
6043 }
6044 }
6045 }
6046
6047
6048 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
6049 if (reg->encoding() < 8) {
6050 if (adr.base_needs_rex()) {
6051 if (adr.index_needs_rex()) {
6052 prefix(REX_XB);
6053 } else {
6054 prefix(REX_B);
6055 }
6056 } else {
6057 if (adr.index_needs_rex()) {
6058 prefix(REX_X);
6059 } else if (byteinst && reg->encoding() >= 4 ) {
6060 prefix(REX);
6061 }
6062 }
6063 } else {
6064 if (adr.base_needs_rex()) {
6065 if (adr.index_needs_rex()) {
6066 prefix(REX_RXB);
6067 } else {
6068 prefix(REX_RB);
6069 }
6070 } else {
6071 if (adr.index_needs_rex()) {
6072 prefix(REX_RX);
6073 } else {
6074 prefix(REX_R);
6075 }
6076 }
6077 }
6078 }
6079
6080 void Assembler::prefixq(Address adr, Register src) {
6081 if (src->encoding() < 8) {
6082 if (adr.base_needs_rex()) {
6083 if (adr.index_needs_rex()) {
6084 prefix(REX_WXB);
6085 } else {
6086 prefix(REX_WB);
6087 }
6088 } else {
6089 if (adr.index_needs_rex()) {
6090 prefix(REX_WX);
6091 } else {
6092 prefix(REX_W);
6093 }
6094 }
6095 } else {
6096 if (adr.base_needs_rex()) {
6097 if (adr.index_needs_rex()) {
6098 prefix(REX_WRXB);
6099 } else {
6100 prefix(REX_WRB);
6101 }
6102 } else {
6103 if (adr.index_needs_rex()) {
6104 prefix(REX_WRX);
6105 } else {
6106 prefix(REX_WR);
6107 }
6108 }
6109 }
6110 }
6111
6112 void Assembler::prefix(Address adr, XMMRegister reg) {
6113 if (reg->encoding() < 8) {
6114 if (adr.base_needs_rex()) {
6115 if (adr.index_needs_rex()) {
6116 prefix(REX_XB);
6117 } else {
6118 prefix(REX_B);
6119 }
6120 } else {
6121 if (adr.index_needs_rex()) {
6122 prefix(REX_X);
6123 }
6124 }
6125 } else {
6126 if (adr.base_needs_rex()) {
6127 if (adr.index_needs_rex()) {
6128 prefix(REX_RXB);
6129 } else {
6130 prefix(REX_RB);
6131 }
6132 } else {
6133 if (adr.index_needs_rex()) {
6134 prefix(REX_RX);
6135 } else {
6136 prefix(REX_R);
6137 }
6138 }
6139 }
6140 }
6141
6142 void Assembler::prefixq(Address adr, XMMRegister src) {
6143 if (src->encoding() < 8) {
6144 if (adr.base_needs_rex()) {
6145 if (adr.index_needs_rex()) {
6146 prefix(REX_WXB);
6147 } else {
6148 prefix(REX_WB);
6149 }
6150 } else {
6151 if (adr.index_needs_rex()) {
6152 prefix(REX_WX);
6153 } else {
6154 prefix(REX_W);
6155 }
6156 }
6157 } else {
6158 if (adr.base_needs_rex()) {
6159 if (adr.index_needs_rex()) {
6160 prefix(REX_WRXB);
6161 } else {
6162 prefix(REX_WRB);
6163 }
6164 } else {
6165 if (adr.index_needs_rex()) {
6166 prefix(REX_WRX);
6167 } else {
6168 prefix(REX_WR);
6169 }
6170 }
6171 }
6172 }
6173
6174 void Assembler::adcq(Register dst, int32_t imm32) {
6175 (void) prefixq_and_encode(dst->encoding());
6176 emit_arith(0x81, 0xD0, dst, imm32);
6177 }
6178
6179 void Assembler::adcq(Register dst, Address src) {
6180 InstructionMark im(this);
6181 prefixq(src, dst);
6182 emit_int8(0x13);
6183 emit_operand(dst, src);
6184 }
6185
6186 void Assembler::adcq(Register dst, Register src) {
6187 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6188 emit_arith(0x13, 0xC0, dst, src);
6189 }
6190
6191 void Assembler::addq(Address dst, int32_t imm32) {
6192 InstructionMark im(this);
6193 prefixq(dst);
6194 emit_arith_operand(0x81, rax, dst,imm32);
6195 }
6196
6197 void Assembler::addq(Address dst, Register src) {
6198 InstructionMark im(this);
6199 prefixq(dst, src);
6200 emit_int8(0x01);
6201 emit_operand(src, dst);
6202 }
6203
6204 void Assembler::addq(Register dst, int32_t imm32) {
6205 (void) prefixq_and_encode(dst->encoding());
6206 emit_arith(0x81, 0xC0, dst, imm32);
6207 }
6208
6209 void Assembler::addq(Register dst, Address src) {
6210 InstructionMark im(this);
6211 prefixq(src, dst);
6212 emit_int8(0x03);
6213 emit_operand(dst, src);
6214 }
6215
6216 void Assembler::addq(Register dst, Register src) {
6217 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6218 emit_arith(0x03, 0xC0, dst, src);
6219 }
6220
6221 void Assembler::adcxq(Register dst, Register src) {
6222 //assert(VM_Version::supports_adx(), "adx instructions not supported");
6223 emit_int8((unsigned char)0x66);
6224 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6225 emit_int8(0x0F);
6226 emit_int8(0x38);
6227 emit_int8((unsigned char)0xF6);
6228 emit_int8((unsigned char)(0xC0 | encode));
6229 }
6230
6231 void Assembler::adoxq(Register dst, Register src) {
6232 //assert(VM_Version::supports_adx(), "adx instructions not supported");
6233 emit_int8((unsigned char)0xF3);
6234 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6235 emit_int8(0x0F);
6236 emit_int8(0x38);
6237 emit_int8((unsigned char)0xF6);
6238 emit_int8((unsigned char)(0xC0 | encode));
6239 }
6240
6241 void Assembler::andq(Address dst, int32_t imm32) {
6242 InstructionMark im(this);
6243 prefixq(dst);
6244 emit_int8((unsigned char)0x81);
6245 emit_operand(rsp, dst, 4);
6246 emit_int32(imm32);
6247 }
6248
6249 void Assembler::andq(Register dst, int32_t imm32) {
6250 (void) prefixq_and_encode(dst->encoding());
6251 emit_arith(0x81, 0xE0, dst, imm32);
6252 }
6253
6254 void Assembler::andq(Register dst, Address src) {
6255 InstructionMark im(this);
6256 prefixq(src, dst);
6257 emit_int8(0x23);
6258 emit_operand(dst, src);
6259 }
6260
6261 void Assembler::andq(Register dst, Register src) {
6262 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6263 emit_arith(0x23, 0xC0, dst, src);
6264 }
6265
6266 void Assembler::andnq(Register dst, Register src1, Register src2) {
6267 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6268 int encode = vex_prefix_0F38_and_encode_q(dst, src1, src2);
6269 emit_int8((unsigned char)0xF2);
6270 emit_int8((unsigned char)(0xC0 | encode));
6271 }
6272
6273 void Assembler::andnq(Register dst, Register src1, Address src2) {
6274 if (VM_Version::supports_evex()) {
6275 tuple_type = EVEX_T1S;
6276 input_size_in_bits = EVEX_64bit;
6277 }
6278 InstructionMark im(this);
6279 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6280 vex_prefix_0F38_q(dst, src1, src2);
6281 emit_int8((unsigned char)0xF2);
6282 emit_operand(dst, src2);
6283 }
6284
6285 void Assembler::bsfq(Register dst, Register src) {
6286 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6287 emit_int8(0x0F);
6288 emit_int8((unsigned char)0xBC);
6289 emit_int8((unsigned char)(0xC0 | encode));
6290 }
6291
6292 void Assembler::bsrq(Register dst, Register src) {
6293 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6294 emit_int8(0x0F);
6295 emit_int8((unsigned char)0xBD);
6296 emit_int8((unsigned char)(0xC0 | encode));
6297 }
6298
6299 void Assembler::bswapq(Register reg) {
6300 int encode = prefixq_and_encode(reg->encoding());
6301 emit_int8(0x0F);
6302 emit_int8((unsigned char)(0xC8 | encode));
6303 }
6304
6305 void Assembler::blsiq(Register dst, Register src) {
6306 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6307 int encode = vex_prefix_0F38_and_encode_q(rbx, dst, src);
6308 emit_int8((unsigned char)0xF3);
6309 emit_int8((unsigned char)(0xC0 | encode));
6310 }
6311
6312 void Assembler::blsiq(Register dst, Address src) {
6313 InstructionMark im(this);
6314 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6315 vex_prefix_0F38_q(rbx, dst, src);
6316 emit_int8((unsigned char)0xF3);
6317 emit_operand(rbx, src);
6318 }
6319
6320 void Assembler::blsmskq(Register dst, Register src) {
6321 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6322 int encode = vex_prefix_0F38_and_encode_q(rdx, dst, src);
6323 emit_int8((unsigned char)0xF3);
6324 emit_int8((unsigned char)(0xC0 | encode));
6325 }
6326
6327 void Assembler::blsmskq(Register dst, Address src) {
6328 InstructionMark im(this);
6329 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6330 vex_prefix_0F38_q(rdx, dst, src);
6331 emit_int8((unsigned char)0xF3);
6332 emit_operand(rdx, src);
6333 }
6334
6335 void Assembler::blsrq(Register dst, Register src) {
6336 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6337 int encode = vex_prefix_0F38_and_encode_q(rcx, dst, src);
6338 emit_int8((unsigned char)0xF3);
6339 emit_int8((unsigned char)(0xC0 | encode));
6340 }
6341
6342 void Assembler::blsrq(Register dst, Address src) {
6343 InstructionMark im(this);
6344 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6345 vex_prefix_0F38_q(rcx, dst, src);
6346 emit_int8((unsigned char)0xF3);
6347 emit_operand(rcx, src);
6348 }
6349
6350 void Assembler::cdqq() {
6351 prefix(REX_W);
6352 emit_int8((unsigned char)0x99);
6353 }
6354
6355 void Assembler::clflush(Address adr) {
6356 prefix(adr);
6357 emit_int8(0x0F);
6358 emit_int8((unsigned char)0xAE);
6359 emit_operand(rdi, adr);
6360 }
6361
6362 void Assembler::cmovq(Condition cc, Register dst, Register src) {
6363 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6364 emit_int8(0x0F);
6365 emit_int8(0x40 | cc);
6366 emit_int8((unsigned char)(0xC0 | encode));
6367 }
6368
6369 void Assembler::cmovq(Condition cc, Register dst, Address src) {
6370 InstructionMark im(this);
6371 prefixq(src, dst);
6372 emit_int8(0x0F);
6373 emit_int8(0x40 | cc);
6374 emit_operand(dst, src);
6375 }
6376
6377 void Assembler::cmpq(Address dst, int32_t imm32) {
6378 InstructionMark im(this);
6379 prefixq(dst);
6380 emit_int8((unsigned char)0x81);
6381 emit_operand(rdi, dst, 4);
6382 emit_int32(imm32);
6383 }
6384
6385 void Assembler::cmpq(Register dst, int32_t imm32) {
6386 (void) prefixq_and_encode(dst->encoding());
6387 emit_arith(0x81, 0xF8, dst, imm32);
6388 }
6389
6390 void Assembler::cmpq(Address dst, Register src) {
6391 InstructionMark im(this);
6392 prefixq(dst, src);
6393 emit_int8(0x3B);
6394 emit_operand(src, dst);
6395 }
6396
6397 void Assembler::cmpq(Register dst, Register src) {
6398 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6399 emit_arith(0x3B, 0xC0, dst, src);
6400 }
6401
6402 void Assembler::cmpq(Register dst, Address src) {
6403 InstructionMark im(this);
6404 prefixq(src, dst);
6405 emit_int8(0x3B);
6406 emit_operand(dst, src);
6407 }
6408
6409 void Assembler::cmpxchgq(Register reg, Address adr) {
6410 InstructionMark im(this);
6411 prefixq(adr, reg);
6412 emit_int8(0x0F);
6413 emit_int8((unsigned char)0xB1);
6414 emit_operand(reg, adr);
6415 }
6416
6417 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
6418 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6419 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2, true);
6420 emit_int8(0x2A);
6421 emit_int8((unsigned char)(0xC0 | encode));
6422 }
6423
6424 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
6425 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6426 if (VM_Version::supports_evex()) {
6427 tuple_type = EVEX_T1S;
6428 input_size_in_bits = EVEX_32bit;
6429 }
6430 InstructionMark im(this);
6431 simd_prefix_q(dst, dst, src, VEX_SIMD_F2, true);
6432 emit_int8(0x2A);
6433 emit_operand(dst, src);
6434 }
6435
6436 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
6437 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6438 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3, true);
6439 emit_int8(0x2A);
6440 emit_int8((unsigned char)(0xC0 | encode));
6441 }
6442
6443 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
6444 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6445 if (VM_Version::supports_evex()) {
6446 tuple_type = EVEX_T1S;
6447 input_size_in_bits = EVEX_32bit;
6448 }
6449 InstructionMark im(this);
6450 simd_prefix_q(dst, dst, src, VEX_SIMD_F3, true);
6451 emit_int8(0x2A);
6452 emit_operand(dst, src);
6453 }
6454
6455 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
6456 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6457 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, true);
6458 emit_int8(0x2C);
6459 emit_int8((unsigned char)(0xC0 | encode));
6460 }
6461
6462 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
6463 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6464 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, true);
6465 emit_int8(0x2C);
6466 emit_int8((unsigned char)(0xC0 | encode));
6467 }
6468
6469 void Assembler::decl(Register dst) {
6470 // Don't use it directly. Use MacroAssembler::decrementl() instead.
6471 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
6472 int encode = prefix_and_encode(dst->encoding());
6473 emit_int8((unsigned char)0xFF);
6474 emit_int8((unsigned char)(0xC8 | encode));
6475 }
6476
6477 void Assembler::decq(Register dst) {
6478 // Don't use it directly. Use MacroAssembler::decrementq() instead.
6479 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
6480 int encode = prefixq_and_encode(dst->encoding());
6481 emit_int8((unsigned char)0xFF);
6482 emit_int8(0xC8 | encode);
6483 }
6484
6485 void Assembler::decq(Address dst) {
6486 // Don't use it directly. Use MacroAssembler::decrementq() instead.
6487 InstructionMark im(this);
6488 prefixq(dst);
6489 emit_int8((unsigned char)0xFF);
6490 emit_operand(rcx, dst);
6491 }
6492
6493 void Assembler::fxrstor(Address src) {
6494 prefixq(src);
6495 emit_int8(0x0F);
6496 emit_int8((unsigned char)0xAE);
6497 emit_operand(as_Register(1), src);
6498 }
6499
6500 void Assembler::fxsave(Address dst) {
6501 prefixq(dst);
6502 emit_int8(0x0F);
6503 emit_int8((unsigned char)0xAE);
6504 emit_operand(as_Register(0), dst);
6505 }
6506
6507 void Assembler::idivq(Register src) {
6508 int encode = prefixq_and_encode(src->encoding());
6509 emit_int8((unsigned char)0xF7);
6510 emit_int8((unsigned char)(0xF8 | encode));
6511 }
6512
6513 void Assembler::imulq(Register dst, Register src) {
6514 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6515 emit_int8(0x0F);
6516 emit_int8((unsigned char)0xAF);
6517 emit_int8((unsigned char)(0xC0 | encode));
6518 }
6519
6520 void Assembler::imulq(Register dst, Register src, int value) {
6521 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6522 if (is8bit(value)) {
6523 emit_int8(0x6B);
6524 emit_int8((unsigned char)(0xC0 | encode));
6525 emit_int8(value & 0xFF);
6526 } else {
6527 emit_int8(0x69);
6528 emit_int8((unsigned char)(0xC0 | encode));
6529 emit_int32(value);
6530 }
6531 }
6532
6533 void Assembler::imulq(Register dst, Address src) {
6534 InstructionMark im(this);
6535 prefixq(src, dst);
6536 emit_int8(0x0F);
6537 emit_int8((unsigned char) 0xAF);
6538 emit_operand(dst, src);
6539 }
6540
6541 void Assembler::incl(Register dst) {
6542 // Don't use it directly. Use MacroAssembler::incrementl() instead.
6543 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
6544 int encode = prefix_and_encode(dst->encoding());
6545 emit_int8((unsigned char)0xFF);
6546 emit_int8((unsigned char)(0xC0 | encode));
6547 }
6548
6549 void Assembler::incq(Register dst) {
6550 // Don't use it directly. Use MacroAssembler::incrementq() instead.
6551 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
6552 int encode = prefixq_and_encode(dst->encoding());
6553 emit_int8((unsigned char)0xFF);
6554 emit_int8((unsigned char)(0xC0 | encode));
6555 }
6556
6557 void Assembler::incq(Address dst) {
6558 // Don't use it directly. Use MacroAssembler::incrementq() instead.
6559 InstructionMark im(this);
6560 prefixq(dst);
6561 emit_int8((unsigned char)0xFF);
6562 emit_operand(rax, dst);
6563 }
6564
6565 void Assembler::lea(Register dst, Address src) {
6566 leaq(dst, src);
6567 }
6568
6569 void Assembler::leaq(Register dst, Address src) {
6570 InstructionMark im(this);
6571 prefixq(src, dst);
6572 emit_int8((unsigned char)0x8D);
6573 emit_operand(dst, src);
6574 }
6575
6576 void Assembler::mov64(Register dst, int64_t imm64) {
6577 InstructionMark im(this);
6578 int encode = prefixq_and_encode(dst->encoding());
6579 emit_int8((unsigned char)(0xB8 | encode));
6580 emit_int64(imm64);
6581 }
6582
6583 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
6584 InstructionMark im(this);
6585 int encode = prefixq_and_encode(dst->encoding());
6586 emit_int8(0xB8 | encode);
6587 emit_data64(imm64, rspec);
6588 }
6589
6590 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
6591 InstructionMark im(this);
6592 int encode = prefix_and_encode(dst->encoding());
6593 emit_int8((unsigned char)(0xB8 | encode));
6594 emit_data((int)imm32, rspec, narrow_oop_operand);
6595 }
6596
6597 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
6598 InstructionMark im(this);
6599 prefix(dst);
6600 emit_int8((unsigned char)0xC7);
6601 emit_operand(rax, dst, 4);
6602 emit_data((int)imm32, rspec, narrow_oop_operand);
6603 }
6604
6605 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
6606 InstructionMark im(this);
6607 int encode = prefix_and_encode(src1->encoding());
6608 emit_int8((unsigned char)0x81);
6609 emit_int8((unsigned char)(0xF8 | encode));
6610 emit_data((int)imm32, rspec, narrow_oop_operand);
6611 }
6612
6613 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
6614 InstructionMark im(this);
6615 prefix(src1);
6616 emit_int8((unsigned char)0x81);
6617 emit_operand(rax, src1, 4);
6618 emit_data((int)imm32, rspec, narrow_oop_operand);
6619 }
6620
6621 void Assembler::lzcntq(Register dst, Register src) {
6622 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
6623 emit_int8((unsigned char)0xF3);
6624 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6625 emit_int8(0x0F);
6626 emit_int8((unsigned char)0xBD);
6627 emit_int8((unsigned char)(0xC0 | encode));
6628 }
6629
6630 void Assembler::movdq(XMMRegister dst, Register src) {
6631 // table D-1 says MMX/SSE2
6632 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6633 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66, true);
6634 emit_int8(0x6E);
6635 emit_int8((unsigned char)(0xC0 | encode));
6636 }
6637
6638 void Assembler::movdq(Register dst, XMMRegister src) {
6639 // table D-1 says MMX/SSE2
6640 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6641 // swap src/dst to get correct prefix
6642 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66, true);
6643 emit_int8(0x7E);
6644 emit_int8((unsigned char)(0xC0 | encode));
6645 }
6646
6647 void Assembler::movq(Register dst, Register src) {
6648 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6649 emit_int8((unsigned char)0x8B);
6650 emit_int8((unsigned char)(0xC0 | encode));
6651 }
6652
6653 void Assembler::movq(Register dst, Address src) {
6654 InstructionMark im(this);
6655 prefixq(src, dst);
6656 emit_int8((unsigned char)0x8B);
6657 emit_operand(dst, src);
6658 }
6659
6660 void Assembler::movq(Address dst, Register src) {
6661 InstructionMark im(this);
6662 prefixq(dst, src);
6663 emit_int8((unsigned char)0x89);
6664 emit_operand(src, dst);
6665 }
6666
6667 void Assembler::movsbq(Register dst, Address src) {
6668 InstructionMark im(this);
6669 prefixq(src, dst);
6670 emit_int8(0x0F);
6671 emit_int8((unsigned char)0xBE);
6672 emit_operand(dst, src);
6673 }
6674
6675 void Assembler::movsbq(Register dst, Register src) {
6676 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6677 emit_int8(0x0F);
6678 emit_int8((unsigned char)0xBE);
6679 emit_int8((unsigned char)(0xC0 | encode));
6680 }
6681
6682 void Assembler::movslq(Register dst, int32_t imm32) {
6683 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
6684 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
6685 // as a result we shouldn't use until tested at runtime...
6686 ShouldNotReachHere();
6687 InstructionMark im(this);
6688 int encode = prefixq_and_encode(dst->encoding());
6689 emit_int8((unsigned char)(0xC7 | encode));
6690 emit_int32(imm32);
6691 }
6692
6693 void Assembler::movslq(Address dst, int32_t imm32) {
6694 assert(is_simm32(imm32), "lost bits");
6695 InstructionMark im(this);
6696 prefixq(dst);
6697 emit_int8((unsigned char)0xC7);
6698 emit_operand(rax, dst, 4);
6699 emit_int32(imm32);
6700 }
6701
6702 void Assembler::movslq(Register dst, Address src) {
6703 InstructionMark im(this);
6704 prefixq(src, dst);
6705 emit_int8(0x63);
6706 emit_operand(dst, src);
6707 }
6708
6709 void Assembler::movslq(Register dst, Register src) {
6710 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6711 emit_int8(0x63);
6712 emit_int8((unsigned char)(0xC0 | encode));
6713 }
6714
6715 void Assembler::movswq(Register dst, Address src) {
6716 InstructionMark im(this);
6717 prefixq(src, dst);
6718 emit_int8(0x0F);
6719 emit_int8((unsigned char)0xBF);
6720 emit_operand(dst, src);
6721 }
6722
6723 void Assembler::movswq(Register dst, Register src) {
6724 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6725 emit_int8((unsigned char)0x0F);
6726 emit_int8((unsigned char)0xBF);
6727 emit_int8((unsigned char)(0xC0 | encode));
6728 }
6729
6730 void Assembler::movzbq(Register dst, Address src) {
6731 InstructionMark im(this);
6732 prefixq(src, dst);
6733 emit_int8((unsigned char)0x0F);
6734 emit_int8((unsigned char)0xB6);
6735 emit_operand(dst, src);
6736 }
6737
6738 void Assembler::movzbq(Register dst, Register src) {
6739 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6740 emit_int8(0x0F);
6741 emit_int8((unsigned char)0xB6);
6742 emit_int8(0xC0 | encode);
6743 }
6744
6745 void Assembler::movzwq(Register dst, Address src) {
6746 InstructionMark im(this);
6747 prefixq(src, dst);
6748 emit_int8((unsigned char)0x0F);
6749 emit_int8((unsigned char)0xB7);
6750 emit_operand(dst, src);
6751 }
6752
6753 void Assembler::movzwq(Register dst, Register src) {
6754 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6755 emit_int8((unsigned char)0x0F);
6756 emit_int8((unsigned char)0xB7);
6757 emit_int8((unsigned char)(0xC0 | encode));
6758 }
6759
6760 void Assembler::mulq(Address src) {
6761 InstructionMark im(this);
6762 prefixq(src);
6763 emit_int8((unsigned char)0xF7);
6764 emit_operand(rsp, src);
6765 }
6766
6767 void Assembler::mulq(Register src) {
6768 int encode = prefixq_and_encode(src->encoding());
6769 emit_int8((unsigned char)0xF7);
6770 emit_int8((unsigned char)(0xE0 | encode));
6771 }
6772
6773 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
6774 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
6775 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(),
6776 VEX_SIMD_F2, VEX_OPCODE_0F_38, true, AVX_128bit, true, false);
6777 emit_int8((unsigned char)0xF6);
6778 emit_int8((unsigned char)(0xC0 | encode));
6779 }
6780
6781 void Assembler::negq(Register dst) {
6782 int encode = prefixq_and_encode(dst->encoding());
6783 emit_int8((unsigned char)0xF7);
6784 emit_int8((unsigned char)(0xD8 | encode));
6785 }
6786
6787 void Assembler::notq(Register dst) {
6788 int encode = prefixq_and_encode(dst->encoding());
6789 emit_int8((unsigned char)0xF7);
6790 emit_int8((unsigned char)(0xD0 | encode));
6791 }
6792
6793 void Assembler::orq(Address dst, int32_t imm32) {
6794 InstructionMark im(this);
6795 prefixq(dst);
6796 emit_int8((unsigned char)0x81);
6797 emit_operand(rcx, dst, 4);
6798 emit_int32(imm32);
6799 }
6800
6801 void Assembler::orq(Register dst, int32_t imm32) {
6802 (void) prefixq_and_encode(dst->encoding());
6803 emit_arith(0x81, 0xC8, dst, imm32);
6804 }
6805
6806 void Assembler::orq(Register dst, Address src) {
6807 InstructionMark im(this);
6808 prefixq(src, dst);
6809 emit_int8(0x0B);
6810 emit_operand(dst, src);
6811 }
6812
6813 void Assembler::orq(Register dst, Register src) {
6814 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6815 emit_arith(0x0B, 0xC0, dst, src);
6816 }
6817
6818 void Assembler::popa() { // 64bit
6819 movq(r15, Address(rsp, 0));
6820 movq(r14, Address(rsp, wordSize));
6821 movq(r13, Address(rsp, 2 * wordSize));
6822 movq(r12, Address(rsp, 3 * wordSize));
6823 movq(r11, Address(rsp, 4 * wordSize));
6824 movq(r10, Address(rsp, 5 * wordSize));
6825 movq(r9, Address(rsp, 6 * wordSize));
6826 movq(r8, Address(rsp, 7 * wordSize));
6827 movq(rdi, Address(rsp, 8 * wordSize));
6828 movq(rsi, Address(rsp, 9 * wordSize));
6829 movq(rbp, Address(rsp, 10 * wordSize));
6830 // skip rsp
6831 movq(rbx, Address(rsp, 12 * wordSize));
6832 movq(rdx, Address(rsp, 13 * wordSize));
6833 movq(rcx, Address(rsp, 14 * wordSize));
6834 movq(rax, Address(rsp, 15 * wordSize));
6835
6836 addq(rsp, 16 * wordSize);
6837 }
6838
6839 void Assembler::popcntq(Register dst, Address src) {
6840 assert(VM_Version::supports_popcnt(), "must support");
6841 InstructionMark im(this);
6842 emit_int8((unsigned char)0xF3);
6843 prefixq(src, dst);
6844 emit_int8((unsigned char)0x0F);
6845 emit_int8((unsigned char)0xB8);
6846 emit_operand(dst, src);
6847 }
6848
6849 void Assembler::popcntq(Register dst, Register src) {
6850 assert(VM_Version::supports_popcnt(), "must support");
6851 emit_int8((unsigned char)0xF3);
6852 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6853 emit_int8((unsigned char)0x0F);
6854 emit_int8((unsigned char)0xB8);
6855 emit_int8((unsigned char)(0xC0 | encode));
6856 }
6857
6858 void Assembler::popq(Address dst) {
6859 InstructionMark im(this);
6860 prefixq(dst);
6861 emit_int8((unsigned char)0x8F);
6862 emit_operand(rax, dst);
6863 }
6864
6865 void Assembler::pusha() { // 64bit
6866 // we have to store original rsp. ABI says that 128 bytes
6867 // below rsp are local scratch.
6868 movq(Address(rsp, -5 * wordSize), rsp);
6869
6870 subq(rsp, 16 * wordSize);
6871
6872 movq(Address(rsp, 15 * wordSize), rax);
6873 movq(Address(rsp, 14 * wordSize), rcx);
6874 movq(Address(rsp, 13 * wordSize), rdx);
6875 movq(Address(rsp, 12 * wordSize), rbx);
6876 // skip rsp
6877 movq(Address(rsp, 10 * wordSize), rbp);
6878 movq(Address(rsp, 9 * wordSize), rsi);
6879 movq(Address(rsp, 8 * wordSize), rdi);
6880 movq(Address(rsp, 7 * wordSize), r8);
6881 movq(Address(rsp, 6 * wordSize), r9);
6882 movq(Address(rsp, 5 * wordSize), r10);
6883 movq(Address(rsp, 4 * wordSize), r11);
6884 movq(Address(rsp, 3 * wordSize), r12);
6885 movq(Address(rsp, 2 * wordSize), r13);
6886 movq(Address(rsp, wordSize), r14);
6887 movq(Address(rsp, 0), r15);
6888 }
6889
6890 void Assembler::pushq(Address src) {
6891 InstructionMark im(this);
6892 prefixq(src);
6893 emit_int8((unsigned char)0xFF);
6894 emit_operand(rsi, src);
6895 }
6896
6897 void Assembler::rclq(Register dst, int imm8) {
6898 assert(isShiftCount(imm8 >> 1), "illegal shift count");
6899 int encode = prefixq_and_encode(dst->encoding());
6900 if (imm8 == 1) {
6901 emit_int8((unsigned char)0xD1);
6902 emit_int8((unsigned char)(0xD0 | encode));
6903 } else {
6904 emit_int8((unsigned char)0xC1);
6905 emit_int8((unsigned char)(0xD0 | encode));
6906 emit_int8(imm8);
6907 }
6908 }
6909
6910 void Assembler::rorq(Register dst, int imm8) {
6911 assert(isShiftCount(imm8 >> 1), "illegal shift count");
6912 int encode = prefixq_and_encode(dst->encoding());
6913 if (imm8 == 1) {
6914 emit_int8((unsigned char)0xD1);
6915 emit_int8((unsigned char)(0xC8 | encode));
6916 } else {
6917 emit_int8((unsigned char)0xC1);
6918 emit_int8((unsigned char)(0xc8 | encode));
6919 emit_int8(imm8);
6920 }
6921 }
6922
6923 void Assembler::rorxq(Register dst, Register src, int imm8) {
6924 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
6925 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2,
6926 VEX_OPCODE_0F_3A, true, AVX_128bit, true, false);
6927 emit_int8((unsigned char)0xF0);
6928 emit_int8((unsigned char)(0xC0 | encode));
6929 emit_int8(imm8);
6930 }
6931
6932 void Assembler::sarq(Register dst, int imm8) {
6933 assert(isShiftCount(imm8 >> 1), "illegal shift count");
6934 int encode = prefixq_and_encode(dst->encoding());
6935 if (imm8 == 1) {
6936 emit_int8((unsigned char)0xD1);
6937 emit_int8((unsigned char)(0xF8 | encode));
6938 } else {
6939 emit_int8((unsigned char)0xC1);
6940 emit_int8((unsigned char)(0xF8 | encode));
6941 emit_int8(imm8);
6942 }
6943 }
6944
6945 void Assembler::sarq(Register dst) {
6946 int encode = prefixq_and_encode(dst->encoding());
6947 emit_int8((unsigned char)0xD3);
6948 emit_int8((unsigned char)(0xF8 | encode));
6949 }
6950
6951 void Assembler::sbbq(Address dst, int32_t imm32) {
6952 InstructionMark im(this);
6953 prefixq(dst);
6954 emit_arith_operand(0x81, rbx, dst, imm32);
6955 }
6956
6957 void Assembler::sbbq(Register dst, int32_t imm32) {
6958 (void) prefixq_and_encode(dst->encoding());
6959 emit_arith(0x81, 0xD8, dst, imm32);
6960 }
6961
6962 void Assembler::sbbq(Register dst, Address src) {
6963 InstructionMark im(this);
6964 prefixq(src, dst);
6965 emit_int8(0x1B);
6966 emit_operand(dst, src);
6967 }
6968
6969 void Assembler::sbbq(Register dst, Register src) {
6970 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6971 emit_arith(0x1B, 0xC0, dst, src);
6972 }
6973
6974 void Assembler::shlq(Register dst, int imm8) {
6975 assert(isShiftCount(imm8 >> 1), "illegal shift count");
6976 int encode = prefixq_and_encode(dst->encoding());
6977 if (imm8 == 1) {
6978 emit_int8((unsigned char)0xD1);
6979 emit_int8((unsigned char)(0xE0 | encode));
6980 } else {
6981 emit_int8((unsigned char)0xC1);
6982 emit_int8((unsigned char)(0xE0 | encode));
6983 emit_int8(imm8);
6984 }
6985 }
6986
6987 void Assembler::shlq(Register dst) {
6988 int encode = prefixq_and_encode(dst->encoding());
6989 emit_int8((unsigned char)0xD3);
6990 emit_int8((unsigned char)(0xE0 | encode));
6991 }
6992
6993 void Assembler::shrq(Register dst, int imm8) {
6994 assert(isShiftCount(imm8 >> 1), "illegal shift count");
6995 int encode = prefixq_and_encode(dst->encoding());
6996 emit_int8((unsigned char)0xC1);
6997 emit_int8((unsigned char)(0xE8 | encode));
6998 emit_int8(imm8);
6999 }
7000
7001 void Assembler::shrq(Register dst) {
7002 int encode = prefixq_and_encode(dst->encoding());
7003 emit_int8((unsigned char)0xD3);
7004 emit_int8(0xE8 | encode);
7005 }
7006
7007 void Assembler::subq(Address dst, int32_t imm32) {
7008 InstructionMark im(this);
7009 prefixq(dst);
7010 emit_arith_operand(0x81, rbp, dst, imm32);
7011 }
7012
7013 void Assembler::subq(Address dst, Register src) {
7014 InstructionMark im(this);
7015 prefixq(dst, src);
7016 emit_int8(0x29);
7017 emit_operand(src, dst);
7018 }
7019
7020 void Assembler::subq(Register dst, int32_t imm32) {
7021 (void) prefixq_and_encode(dst->encoding());
7022 emit_arith(0x81, 0xE8, dst, imm32);
7023 }
7024
7025 // Force generation of a 4 byte immediate value even if it fits into 8bit
7026 void Assembler::subq_imm32(Register dst, int32_t imm32) {
7027 (void) prefixq_and_encode(dst->encoding());
7028 emit_arith_imm32(0x81, 0xE8, dst, imm32);
7029 }
7030
7031 void Assembler::subq(Register dst, Address src) {
7032 InstructionMark im(this);
7033 prefixq(src, dst);
7034 emit_int8(0x2B);
7035 emit_operand(dst, src);
7036 }
7037
7038 void Assembler::subq(Register dst, Register src) {
7039 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7040 emit_arith(0x2B, 0xC0, dst, src);
7041 }
7042
7043 void Assembler::testq(Register dst, int32_t imm32) {
7044 // not using emit_arith because test
7045 // doesn't support sign-extension of
7046 // 8bit operands
7047 int encode = dst->encoding();
7048 if (encode == 0) {
7049 prefix(REX_W);
7050 emit_int8((unsigned char)0xA9);
7051 } else {
7052 encode = prefixq_and_encode(encode);
7053 emit_int8((unsigned char)0xF7);
7054 emit_int8((unsigned char)(0xC0 | encode));
7055 }
7056 emit_int32(imm32);
7057 }
7058
7059 void Assembler::testq(Register dst, Register src) {
7060 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7061 emit_arith(0x85, 0xC0, dst, src);
7062 }
7063
7064 void Assembler::xaddq(Address dst, Register src) {
7065 InstructionMark im(this);
7066 prefixq(dst, src);
7067 emit_int8(0x0F);
7068 emit_int8((unsigned char)0xC1);
7069 emit_operand(src, dst);
7070 }
7071
7072 void Assembler::xchgq(Register dst, Address src) {
7073 InstructionMark im(this);
7074 prefixq(src, dst);
7075 emit_int8((unsigned char)0x87);
7076 emit_operand(dst, src);
7077 }
7078
7079 void Assembler::xchgq(Register dst, Register src) {
7080 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7081 emit_int8((unsigned char)0x87);
7082 emit_int8((unsigned char)(0xc0 | encode));
7083 }
7084
7085 void Assembler::xorq(Register dst, Register src) {
7086 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7087 emit_arith(0x33, 0xC0, dst, src);
7088 }
7089
7090 void Assembler::xorq(Register dst, Address src) {
7091 InstructionMark im(this);
7092 prefixq(src, dst);
7093 emit_int8(0x33);
7094 emit_operand(dst, src);
7095 }
7096
7097 #endif // !LP64