1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc_interface/collectedHeap.inline.hpp"
29 #include "interpreter/interpreter.hpp"
30 #include "memory/cardTableModRefBS.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
42 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc_implementation/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
59 // -----------------Table 4.5 -------------------- //
60 16, 32, 64, // EVEX_FV(0)
61 4, 4, 4, // EVEX_FV(1) - with Evex.b
62 16, 32, 64, // EVEX_FV(2) - with Evex.w
63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
64 8, 16, 32, // EVEX_HV(0)
65 4, 4, 4, // EVEX_HV(1) - with Evex.b
66 // -----------------Table 4.6 -------------------- //
67 16, 32, 64, // EVEX_FVM(0)
68 1, 1, 1, // EVEX_T1S(0)
69 2, 2, 2, // EVEX_T1S(1)
70 4, 4, 4, // EVEX_T1S(2)
71 8, 8, 8, // EVEX_T1S(3)
72 4, 4, 4, // EVEX_T1F(0)
73 8, 8, 8, // EVEX_T1F(1)
74 8, 8, 8, // EVEX_T2(0)
75 0, 16, 16, // EVEX_T2(1)
76 0, 16, 16, // EVEX_T4(0)
77 0, 0, 32, // EVEX_T4(1)
78 0, 0, 32, // EVEX_T8(0)
79 8, 16, 32, // EVEX_HVM(0)
80 4, 8, 16, // EVEX_QVM(0)
81 2, 4, 8, // EVEX_OVM(0)
82 16, 16, 16, // EVEX_M128(0)
83 8, 32, 64, // EVEX_DUP(0)
84 0, 0, 0 // EVEX_NTUP
85 };
86
87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
88 _is_lval = false;
89 _target = target;
90 switch (rtype) {
91 case relocInfo::oop_type:
92 case relocInfo::metadata_type:
93 // Oops are a special case. Normally they would be their own section
94 // but in cases like icBuffer they are literals in the code stream that
95 // we don't have a section for. We use none so that we get a literal address
96 // which is always patchable.
97 break;
98 case relocInfo::external_word_type:
99 _rspec = external_word_Relocation::spec(target);
100 break;
101 case relocInfo::internal_word_type:
102 _rspec = internal_word_Relocation::spec(target);
103 break;
104 case relocInfo::opt_virtual_call_type:
105 _rspec = opt_virtual_call_Relocation::spec();
106 break;
107 case relocInfo::static_call_type:
108 _rspec = static_call_Relocation::spec();
109 break;
110 case relocInfo::runtime_call_type:
111 _rspec = runtime_call_Relocation::spec();
112 break;
113 case relocInfo::poll_type:
114 case relocInfo::poll_return_type:
115 _rspec = Relocation::spec_simple(rtype);
116 break;
117 case relocInfo::none:
118 break;
119 default:
120 ShouldNotReachHere();
121 break;
122 }
123 }
124
125 // Implementation of Address
126
127 #ifdef _LP64
128
129 Address Address::make_array(ArrayAddress adr) {
130 // Not implementable on 64bit machines
131 // Should have been handled higher up the call chain.
132 ShouldNotReachHere();
133 return Address();
134 }
135
136 // exceedingly dangerous constructor
137 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
138 _base = noreg;
139 _index = noreg;
140 _scale = no_scale;
141 _disp = disp;
142 switch (rtype) {
143 case relocInfo::external_word_type:
144 _rspec = external_word_Relocation::spec(loc);
145 break;
146 case relocInfo::internal_word_type:
147 _rspec = internal_word_Relocation::spec(loc);
148 break;
149 case relocInfo::runtime_call_type:
150 // HMM
151 _rspec = runtime_call_Relocation::spec();
152 break;
153 case relocInfo::poll_type:
154 case relocInfo::poll_return_type:
155 _rspec = Relocation::spec_simple(rtype);
156 break;
157 case relocInfo::none:
158 break;
159 default:
160 ShouldNotReachHere();
161 }
162 }
163 #else // LP64
164
165 Address Address::make_array(ArrayAddress adr) {
166 AddressLiteral base = adr.base();
167 Address index = adr.index();
168 assert(index._disp == 0, "must not have disp"); // maybe it can?
169 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
170 array._rspec = base._rspec;
171 return array;
172 }
173
174 // exceedingly dangerous constructor
175 Address::Address(address loc, RelocationHolder spec) {
176 _base = noreg;
177 _index = noreg;
178 _scale = no_scale;
179 _disp = (intptr_t) loc;
180 _rspec = spec;
181 }
182
183 #endif // _LP64
184
185
186
187 // Convert the raw encoding form into the form expected by the constructor for
188 // Address. An index of 4 (rsp) corresponds to having no index, so convert
189 // that to noreg for the Address constructor.
190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
191 RelocationHolder rspec;
192 if (disp_reloc != relocInfo::none) {
193 rspec = Relocation::spec_simple(disp_reloc);
194 }
195 bool valid_index = index != rsp->encoding();
196 if (valid_index) {
197 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
198 madr._rspec = rspec;
199 return madr;
200 } else {
201 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
202 madr._rspec = rspec;
203 return madr;
204 }
205 }
206
207 // Implementation of Assembler
208
209 int AbstractAssembler::code_fill_byte() {
210 return (u_char)'\xF4'; // hlt
211 }
212
213 // make this go away someday
214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
215 if (rtype == relocInfo::none)
216 emit_int32(data);
217 else
218 emit_data(data, Relocation::spec_simple(rtype), format);
219 }
220
221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
222 assert(imm_operand == 0, "default format must be immediate in this file");
223 assert(inst_mark() != NULL, "must be inside InstructionMark");
224 if (rspec.type() != relocInfo::none) {
225 #ifdef ASSERT
226 check_relocation(rspec, format);
227 #endif
228 // Do not use AbstractAssembler::relocate, which is not intended for
229 // embedded words. Instead, relocate to the enclosing instruction.
230
231 // hack. call32 is too wide for mask so use disp32
232 if (format == call32_operand)
233 code_section()->relocate(inst_mark(), rspec, disp32_operand);
234 else
235 code_section()->relocate(inst_mark(), rspec, format);
236 }
237 emit_int32(data);
238 }
239
240 static int encode(Register r) {
241 int enc = r->encoding();
242 if (enc >= 8) {
243 enc -= 8;
244 }
245 return enc;
246 }
247
248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
249 assert(dst->has_byte_register(), "must have byte register");
250 assert(isByte(op1) && isByte(op2), "wrong opcode");
251 assert(isByte(imm8), "not a byte");
252 assert((op1 & 0x01) == 0, "should be 8bit operation");
253 emit_int8(op1);
254 emit_int8(op2 | encode(dst));
255 emit_int8(imm8);
256 }
257
258
259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
260 assert(isByte(op1) && isByte(op2), "wrong opcode");
261 assert((op1 & 0x01) == 1, "should be 32bit operation");
262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
263 if (is8bit(imm32)) {
264 emit_int8(op1 | 0x02); // set sign bit
265 emit_int8(op2 | encode(dst));
266 emit_int8(imm32 & 0xFF);
267 } else {
268 emit_int8(op1);
269 emit_int8(op2 | encode(dst));
270 emit_int32(imm32);
271 }
272 }
273
274 // Force generation of a 4 byte immediate value even if it fits into 8bit
275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
276 assert(isByte(op1) && isByte(op2), "wrong opcode");
277 assert((op1 & 0x01) == 1, "should be 32bit operation");
278 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
279 emit_int8(op1);
280 emit_int8(op2 | encode(dst));
281 emit_int32(imm32);
282 }
283
284 // immediate-to-memory forms
285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
286 assert((op1 & 0x01) == 1, "should be 32bit operation");
287 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
288 if (is8bit(imm32)) {
289 emit_int8(op1 | 0x02); // set sign bit
290 emit_operand(rm, adr, 1);
291 emit_int8(imm32 & 0xFF);
292 } else {
293 emit_int8(op1);
294 emit_operand(rm, adr, 4);
295 emit_int32(imm32);
296 }
297 }
298
299
300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
301 assert(isByte(op1) && isByte(op2), "wrong opcode");
302 emit_int8(op1);
303 emit_int8(op2 | encode(dst) << 3 | encode(src));
304 }
305
306
307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
309 int mod_idx = 0;
310 // We will test if the displacement fits the compressed format and if so
311 // apply the compression to the displacment iff the result is8bit.
312 if (VM_Version::supports_evex() && is_evex_inst) {
313 switch (cur_tuple_type) {
314 case EVEX_FV:
315 if ((cur_encoding & VEX_W) == VEX_W) {
316 mod_idx += 2 + ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
317 } else {
318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
319 }
320 break;
321
322 case EVEX_HV:
323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
324 break;
325
326 case EVEX_FVM:
327 break;
328
329 case EVEX_T1S:
330 switch (in_size_in_bits) {
331 case EVEX_8bit:
332 break;
333
334 case EVEX_16bit:
335 mod_idx = 1;
336 break;
337
338 case EVEX_32bit:
339 mod_idx = 2;
340 break;
341
342 case EVEX_64bit:
343 mod_idx = 3;
344 break;
345 }
346 break;
347
348 case EVEX_T1F:
349 case EVEX_T2:
350 case EVEX_T4:
351 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
352 break;
353
354 case EVEX_T8:
355 break;
356
357 case EVEX_HVM:
358 break;
359
360 case EVEX_QVM:
361 break;
362
363 case EVEX_OVM:
364 break;
365
366 case EVEX_M128:
367 break;
368
369 case EVEX_DUP:
370 break;
371
372 default:
373 assert(0, "no valid evex tuple_table entry");
374 break;
375 }
376
377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
379 if ((disp % disp_factor) == 0) {
380 int new_disp = disp / disp_factor;
381 if ((-0x80 <= new_disp && new_disp < 0x80)) {
382 disp = new_disp;
383 }
384 } else {
385 return false;
386 }
387 }
388 }
389 return (-0x80 <= disp && disp < 0x80);
390 }
391
392
393 bool Assembler::emit_compressed_disp_byte(int &disp) {
394 int mod_idx = 0;
395 // We will test if the displacement fits the compressed format and if so
396 // apply the compression to the displacment iff the result is8bit.
397 if (VM_Version::supports_evex() && is_evex_instruction) {
398 switch (tuple_type) {
399 case EVEX_FV:
400 if ((evex_encoding & VEX_W) == VEX_W) {
401 mod_idx += 2 + ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
402 } else {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
404 }
405 break;
406
407 case EVEX_HV:
408 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
409 break;
410
411 case EVEX_FVM:
412 break;
413
414 case EVEX_T1S:
415 switch (input_size_in_bits) {
416 case EVEX_8bit:
417 break;
418
419 case EVEX_16bit:
420 mod_idx = 1;
421 break;
422
423 case EVEX_32bit:
424 mod_idx = 2;
425 break;
426
427 case EVEX_64bit:
428 mod_idx = 3;
429 break;
430 }
431 break;
432
433 case EVEX_T1F:
434 case EVEX_T2:
435 case EVEX_T4:
436 mod_idx = (input_size_in_bits == EVEX_64bit) ? 1 : 0;
437 break;
438
439 case EVEX_T8:
440 break;
441
442 case EVEX_HVM:
443 break;
444
445 case EVEX_QVM:
446 break;
447
448 case EVEX_OVM:
449 break;
450
451 case EVEX_M128:
452 break;
453
454 case EVEX_DUP:
455 break;
456
457 default:
458 assert(0, "no valid evex tuple_table entry");
459 break;
460 }
461
462 if (avx_vector_len >= AVX_128bit && avx_vector_len <= AVX_512bit) {
463 int disp_factor = tuple_table[tuple_type + mod_idx][avx_vector_len];
464 if ((disp % disp_factor) == 0) {
465 int new_disp = disp / disp_factor;
466 if (is8bit(new_disp)) {
467 disp = new_disp;
468 }
469 } else {
470 return false;
471 }
472 }
473 }
474 return is8bit(disp);
475 }
476
477
478 void Assembler::emit_operand(Register reg, Register base, Register index,
479 Address::ScaleFactor scale, int disp,
480 RelocationHolder const& rspec,
481 int rip_relative_correction) {
482 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
483
484 // Encode the registers as needed in the fields they are used in
485
486 int regenc = encode(reg) << 3;
487 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
488 int baseenc = base->is_valid() ? encode(base) : 0;
489
490 if (base->is_valid()) {
491 if (index->is_valid()) {
492 assert(scale != Address::no_scale, "inconsistent address");
493 // [base + index*scale + disp]
494 if (disp == 0 && rtype == relocInfo::none &&
495 base != rbp LP64_ONLY(&& base != r13)) {
496 // [base + index*scale]
497 // [00 reg 100][ss index base]
498 assert(index != rsp, "illegal addressing mode");
499 emit_int8(0x04 | regenc);
500 emit_int8(scale << 6 | indexenc | baseenc);
501 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
502 // [base + index*scale + imm8]
503 // [01 reg 100][ss index base] imm8
504 assert(index != rsp, "illegal addressing mode");
505 emit_int8(0x44 | regenc);
506 emit_int8(scale << 6 | indexenc | baseenc);
507 emit_int8(disp & 0xFF);
508 } else {
509 // [base + index*scale + disp32]
510 // [10 reg 100][ss index base] disp32
511 assert(index != rsp, "illegal addressing mode");
512 emit_int8(0x84 | regenc);
513 emit_int8(scale << 6 | indexenc | baseenc);
514 emit_data(disp, rspec, disp32_operand);
515 }
516 } else if (base == rsp LP64_ONLY(|| base == r12)) {
517 // [rsp + disp]
518 if (disp == 0 && rtype == relocInfo::none) {
519 // [rsp]
520 // [00 reg 100][00 100 100]
521 emit_int8(0x04 | regenc);
522 emit_int8(0x24);
523 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
524 // [rsp + imm8]
525 // [01 reg 100][00 100 100] disp8
526 emit_int8(0x44 | regenc);
527 emit_int8(0x24);
528 emit_int8(disp & 0xFF);
529 } else {
530 // [rsp + imm32]
531 // [10 reg 100][00 100 100] disp32
532 emit_int8(0x84 | regenc);
533 emit_int8(0x24);
534 emit_data(disp, rspec, disp32_operand);
535 }
536 } else {
537 // [base + disp]
538 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
539 if (disp == 0 && rtype == relocInfo::none &&
540 base != rbp LP64_ONLY(&& base != r13)) {
541 // [base]
542 // [00 reg base]
543 emit_int8(0x00 | regenc | baseenc);
544 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
545 // [base + disp8]
546 // [01 reg base] disp8
547 emit_int8(0x40 | regenc | baseenc);
548 emit_int8(disp & 0xFF);
549 } else {
550 // [base + disp32]
551 // [10 reg base] disp32
552 emit_int8(0x80 | regenc | baseenc);
553 emit_data(disp, rspec, disp32_operand);
554 }
555 }
556 } else {
557 if (index->is_valid()) {
558 assert(scale != Address::no_scale, "inconsistent address");
559 // [index*scale + disp]
560 // [00 reg 100][ss index 101] disp32
561 assert(index != rsp, "illegal addressing mode");
562 emit_int8(0x04 | regenc);
563 emit_int8(scale << 6 | indexenc | 0x05);
564 emit_data(disp, rspec, disp32_operand);
565 } else if (rtype != relocInfo::none ) {
566 // [disp] (64bit) RIP-RELATIVE (32bit) abs
567 // [00 000 101] disp32
568
569 emit_int8(0x05 | regenc);
570 // Note that the RIP-rel. correction applies to the generated
571 // disp field, but _not_ to the target address in the rspec.
572
573 // disp was created by converting the target address minus the pc
574 // at the start of the instruction. That needs more correction here.
575 // intptr_t disp = target - next_ip;
576 assert(inst_mark() != NULL, "must be inside InstructionMark");
577 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
578 int64_t adjusted = disp;
579 // Do rip-rel adjustment for 64bit
580 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
581 assert(is_simm32(adjusted),
582 "must be 32bit offset (RIP relative address)");
583 emit_data((int32_t) adjusted, rspec, disp32_operand);
584
585 } else {
586 // 32bit never did this, did everything as the rip-rel/disp code above
587 // [disp] ABSOLUTE
588 // [00 reg 100][00 100 101] disp32
589 emit_int8(0x04 | regenc);
590 emit_int8(0x25);
591 emit_data(disp, rspec, disp32_operand);
592 }
593 }
594 is_evex_instruction = false;
595 }
596
597 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
598 Address::ScaleFactor scale, int disp,
599 RelocationHolder const& rspec) {
600 if (UseAVX > 2) {
601 int xreg_enc = reg->encoding();
602 if (xreg_enc > 15) {
603 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
604 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
605 return;
606 }
607 }
608 emit_operand((Register)reg, base, index, scale, disp, rspec);
609 }
610
611 // Secret local extension to Assembler::WhichOperand:
612 #define end_pc_operand (_WhichOperand_limit)
613
614 address Assembler::locate_operand(address inst, WhichOperand which) {
615 // Decode the given instruction, and return the address of
616 // an embedded 32-bit operand word.
617
618 // If "which" is disp32_operand, selects the displacement portion
619 // of an effective address specifier.
620 // If "which" is imm64_operand, selects the trailing immediate constant.
621 // If "which" is call32_operand, selects the displacement of a call or jump.
622 // Caller is responsible for ensuring that there is such an operand,
623 // and that it is 32/64 bits wide.
624
625 // If "which" is end_pc_operand, find the end of the instruction.
626
627 address ip = inst;
628 bool is_64bit = false;
629
630 debug_only(bool has_disp32 = false);
631 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
632
633 again_after_prefix:
634 switch (0xFF & *ip++) {
635
636 // These convenience macros generate groups of "case" labels for the switch.
637 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
638 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
639 case (x)+4: case (x)+5: case (x)+6: case (x)+7
640 #define REP16(x) REP8((x)+0): \
641 case REP8((x)+8)
642
643 case CS_segment:
644 case SS_segment:
645 case DS_segment:
646 case ES_segment:
647 case FS_segment:
648 case GS_segment:
649 // Seems dubious
650 LP64_ONLY(assert(false, "shouldn't have that prefix"));
651 assert(ip == inst+1, "only one prefix allowed");
652 goto again_after_prefix;
653
654 case 0x67:
655 case REX:
656 case REX_B:
657 case REX_X:
658 case REX_XB:
659 case REX_R:
660 case REX_RB:
661 case REX_RX:
662 case REX_RXB:
663 NOT_LP64(assert(false, "64bit prefixes"));
664 goto again_after_prefix;
665
666 case REX_W:
667 case REX_WB:
668 case REX_WX:
669 case REX_WXB:
670 case REX_WR:
671 case REX_WRB:
672 case REX_WRX:
673 case REX_WRXB:
674 NOT_LP64(assert(false, "64bit prefixes"));
675 is_64bit = true;
676 goto again_after_prefix;
677
678 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
679 case 0x88: // movb a, r
680 case 0x89: // movl a, r
681 case 0x8A: // movb r, a
682 case 0x8B: // movl r, a
683 case 0x8F: // popl a
684 debug_only(has_disp32 = true);
685 break;
686
687 case 0x68: // pushq #32
688 if (which == end_pc_operand) {
689 return ip + 4;
690 }
691 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
692 return ip; // not produced by emit_operand
693
694 case 0x66: // movw ... (size prefix)
695 again_after_size_prefix2:
696 switch (0xFF & *ip++) {
697 case REX:
698 case REX_B:
699 case REX_X:
700 case REX_XB:
701 case REX_R:
702 case REX_RB:
703 case REX_RX:
704 case REX_RXB:
705 case REX_W:
706 case REX_WB:
707 case REX_WX:
708 case REX_WXB:
709 case REX_WR:
710 case REX_WRB:
711 case REX_WRX:
712 case REX_WRXB:
713 NOT_LP64(assert(false, "64bit prefix found"));
714 goto again_after_size_prefix2;
715 case 0x8B: // movw r, a
716 case 0x89: // movw a, r
717 debug_only(has_disp32 = true);
718 break;
719 case 0xC7: // movw a, #16
720 debug_only(has_disp32 = true);
721 tail_size = 2; // the imm16
722 break;
723 case 0x0F: // several SSE/SSE2 variants
724 ip--; // reparse the 0x0F
725 goto again_after_prefix;
726 default:
727 ShouldNotReachHere();
728 }
729 break;
730
731 case REP8(0xB8): // movl/q r, #32/#64(oop?)
732 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
733 // these asserts are somewhat nonsensical
734 #ifndef _LP64
735 assert(which == imm_operand || which == disp32_operand,
736 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)));
737 #else
738 assert((which == call32_operand || which == imm_operand) && is_64bit ||
739 which == narrow_oop_operand && !is_64bit,
740 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)));
741 #endif // _LP64
742 return ip;
743
744 case 0x69: // imul r, a, #32
745 case 0xC7: // movl a, #32(oop?)
746 tail_size = 4;
747 debug_only(has_disp32 = true); // has both kinds of operands!
748 break;
749
750 case 0x0F: // movx..., etc.
751 switch (0xFF & *ip++) {
752 case 0x3A: // pcmpestri
753 tail_size = 1;
754 case 0x38: // ptest, pmovzxbw
755 ip++; // skip opcode
756 debug_only(has_disp32 = true); // has both kinds of operands!
757 break;
758
759 case 0x70: // pshufd r, r/a, #8
760 debug_only(has_disp32 = true); // has both kinds of operands!
761 case 0x73: // psrldq r, #8
762 tail_size = 1;
763 break;
764
765 case 0x12: // movlps
766 case 0x28: // movaps
767 case 0x2E: // ucomiss
768 case 0x2F: // comiss
769 case 0x54: // andps
770 case 0x55: // andnps
771 case 0x56: // orps
772 case 0x57: // xorps
773 case 0x6E: // movd
774 case 0x7E: // movd
775 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
776 debug_only(has_disp32 = true);
777 break;
778
779 case 0xAD: // shrd r, a, %cl
780 case 0xAF: // imul r, a
781 case 0xBE: // movsbl r, a (movsxb)
782 case 0xBF: // movswl r, a (movsxw)
783 case 0xB6: // movzbl r, a (movzxb)
784 case 0xB7: // movzwl r, a (movzxw)
785 case REP16(0x40): // cmovl cc, r, a
786 case 0xB0: // cmpxchgb
787 case 0xB1: // cmpxchg
788 case 0xC1: // xaddl
789 case 0xC7: // cmpxchg8
790 case REP16(0x90): // setcc a
791 debug_only(has_disp32 = true);
792 // fall out of the switch to decode the address
793 break;
794
795 case 0xC4: // pinsrw r, a, #8
796 debug_only(has_disp32 = true);
797 case 0xC5: // pextrw r, r, #8
798 tail_size = 1; // the imm8
799 break;
800
801 case 0xAC: // shrd r, a, #8
802 debug_only(has_disp32 = true);
803 tail_size = 1; // the imm8
804 break;
805
806 case REP16(0x80): // jcc rdisp32
807 if (which == end_pc_operand) return ip + 4;
808 assert(which == call32_operand, "jcc has no disp32 or imm");
809 return ip;
810 default:
811 ShouldNotReachHere();
812 }
813 break;
814
815 case 0x81: // addl a, #32; addl r, #32
816 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
817 // on 32bit in the case of cmpl, the imm might be an oop
818 tail_size = 4;
819 debug_only(has_disp32 = true); // has both kinds of operands!
820 break;
821
822 case 0x83: // addl a, #8; addl r, #8
823 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
824 debug_only(has_disp32 = true); // has both kinds of operands!
825 tail_size = 1;
826 break;
827
828 case 0x9B:
829 switch (0xFF & *ip++) {
830 case 0xD9: // fnstcw a
831 debug_only(has_disp32 = true);
832 break;
833 default:
834 ShouldNotReachHere();
835 }
836 break;
837
838 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
839 case REP4(0x10): // adc...
840 case REP4(0x20): // and...
841 case REP4(0x30): // xor...
842 case REP4(0x08): // or...
843 case REP4(0x18): // sbb...
844 case REP4(0x28): // sub...
845 case 0xF7: // mull a
846 case 0x8D: // lea r, a
847 case 0x87: // xchg r, a
848 case REP4(0x38): // cmp...
849 case 0x85: // test r, a
850 debug_only(has_disp32 = true); // has both kinds of operands!
851 break;
852
853 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
854 case 0xC6: // movb a, #8
855 case 0x80: // cmpb a, #8
856 case 0x6B: // imul r, a, #8
857 debug_only(has_disp32 = true); // has both kinds of operands!
858 tail_size = 1; // the imm8
859 break;
860
861 case 0xC4: // VEX_3bytes
862 case 0xC5: // VEX_2bytes
863 assert((UseAVX > 0), "shouldn't have VEX prefix");
864 assert(ip == inst+1, "no prefixes allowed");
865 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
866 // but they have prefix 0x0F and processed when 0x0F processed above.
867 //
868 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
869 // instructions (these instructions are not supported in 64-bit mode).
870 // To distinguish them bits [7:6] are set in the VEX second byte since
871 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
872 // those VEX bits REX and vvvv bits are inverted.
873 //
874 // Fortunately C2 doesn't generate these instructions so we don't need
875 // to check for them in product version.
876
877 // Check second byte
878 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
879
880 // First byte
881 if ((0xFF & *inst) == VEX_3bytes) {
882 ip++; // third byte
883 is_64bit = ((VEX_W & *ip) == VEX_W);
884 }
885 ip++; // opcode
886 // To find the end of instruction (which == end_pc_operand).
887 switch (0xFF & *ip) {
888 case 0x61: // pcmpestri r, r/a, #8
889 case 0x70: // pshufd r, r/a, #8
890 case 0x73: // psrldq r, #8
891 tail_size = 1; // the imm8
892 break;
893 default:
894 break;
895 }
896 ip++; // skip opcode
897 debug_only(has_disp32 = true); // has both kinds of operands!
898 break;
899
900 case 0x62: // EVEX_4bytes
901 assert((UseAVX > 0), "shouldn't have EVEX prefix");
902 assert(ip == inst+1, "no prefixes allowed");
903 // no EVEX collisions, all instructions that have 0x62 opcodes
904 // have EVEX versions and are subopcodes of 0x66
905 ip++; // skip P0 and exmaine W in P1
906 is_64bit = ((VEX_W & *ip) == VEX_W);
907 ip++; // move to P2
908 ip++; // skip P2, move to opcode
909 // To find the end of instruction (which == end_pc_operand).
910 switch (0xFF & *ip) {
911 case 0x61: // pcmpestri r, r/a, #8
912 case 0x70: // pshufd r, r/a, #8
913 case 0x73: // psrldq r, #8
914 tail_size = 1; // the imm8
915 break;
916 default:
917 break;
918 }
919 ip++; // skip opcode
920 debug_only(has_disp32 = true); // has both kinds of operands!
921 break;
922
923 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
924 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
925 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
926 case 0xDD: // fld_d a; fst_d a; fstp_d a
927 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
928 case 0xDF: // fild_d a; fistp_d a
929 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
930 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
931 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
932 debug_only(has_disp32 = true);
933 break;
934
935 case 0xE8: // call rdisp32
936 case 0xE9: // jmp rdisp32
937 if (which == end_pc_operand) return ip + 4;
938 assert(which == call32_operand, "call has no disp32 or imm");
939 return ip;
940
941 case 0xF0: // Lock
942 assert(os::is_MP(), "only on MP");
943 goto again_after_prefix;
944
945 case 0xF3: // For SSE
946 case 0xF2: // For SSE2
947 switch (0xFF & *ip++) {
948 case REX:
949 case REX_B:
950 case REX_X:
951 case REX_XB:
952 case REX_R:
953 case REX_RB:
954 case REX_RX:
955 case REX_RXB:
956 case REX_W:
957 case REX_WB:
958 case REX_WX:
959 case REX_WXB:
960 case REX_WR:
961 case REX_WRB:
962 case REX_WRX:
963 case REX_WRXB:
964 NOT_LP64(assert(false, "found 64bit prefix"));
965 ip++;
966 default:
967 ip++;
968 }
969 debug_only(has_disp32 = true); // has both kinds of operands!
970 break;
971
972 default:
973 ShouldNotReachHere();
974
975 #undef REP8
976 #undef REP16
977 }
978
979 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
980 #ifdef _LP64
981 assert(which != imm_operand, "instruction is not a movq reg, imm64");
982 #else
983 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
984 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
985 #endif // LP64
986 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
987
988 // parse the output of emit_operand
989 int op2 = 0xFF & *ip++;
990 int base = op2 & 0x07;
991 int op3 = -1;
992 const int b100 = 4;
993 const int b101 = 5;
994 if (base == b100 && (op2 >> 6) != 3) {
995 op3 = 0xFF & *ip++;
996 base = op3 & 0x07; // refetch the base
997 }
998 // now ip points at the disp (if any)
999
1000 switch (op2 >> 6) {
1001 case 0:
1002 // [00 reg 100][ss index base]
1003 // [00 reg 100][00 100 esp]
1004 // [00 reg base]
1005 // [00 reg 100][ss index 101][disp32]
1006 // [00 reg 101] [disp32]
1007
1008 if (base == b101) {
1009 if (which == disp32_operand)
1010 return ip; // caller wants the disp32
1011 ip += 4; // skip the disp32
1012 }
1013 break;
1014
1015 case 1:
1016 // [01 reg 100][ss index base][disp8]
1017 // [01 reg 100][00 100 esp][disp8]
1018 // [01 reg base] [disp8]
1019 ip += 1; // skip the disp8
1020 break;
1021
1022 case 2:
1023 // [10 reg 100][ss index base][disp32]
1024 // [10 reg 100][00 100 esp][disp32]
1025 // [10 reg base] [disp32]
1026 if (which == disp32_operand)
1027 return ip; // caller wants the disp32
1028 ip += 4; // skip the disp32
1029 break;
1030
1031 case 3:
1032 // [11 reg base] (not a memory addressing mode)
1033 break;
1034 }
1035
1036 if (which == end_pc_operand) {
1037 return ip + tail_size;
1038 }
1039
1040 #ifdef _LP64
1041 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1042 #else
1043 assert(which == imm_operand, "instruction has only an imm field");
1044 #endif // LP64
1045 return ip;
1046 }
1047
1048 address Assembler::locate_next_instruction(address inst) {
1049 // Secretly share code with locate_operand:
1050 return locate_operand(inst, end_pc_operand);
1051 }
1052
1053
1054 #ifdef ASSERT
1055 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1056 address inst = inst_mark();
1057 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1058 address opnd;
1059
1060 Relocation* r = rspec.reloc();
1061 if (r->type() == relocInfo::none) {
1062 return;
1063 } else if (r->is_call() || format == call32_operand) {
1064 // assert(format == imm32_operand, "cannot specify a nonzero format");
1065 opnd = locate_operand(inst, call32_operand);
1066 } else if (r->is_data()) {
1067 assert(format == imm_operand || format == disp32_operand
1068 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1069 opnd = locate_operand(inst, (WhichOperand)format);
1070 } else {
1071 assert(format == imm_operand, "cannot specify a format");
1072 return;
1073 }
1074 assert(opnd == pc(), "must put operand where relocs can find it");
1075 }
1076 #endif // ASSERT
1077
1078 void Assembler::emit_operand32(Register reg, Address adr) {
1079 assert(reg->encoding() < 8, "no extended registers");
1080 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1081 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1082 adr._rspec);
1083 }
1084
1085 void Assembler::emit_operand(Register reg, Address adr,
1086 int rip_relative_correction) {
1087 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1088 adr._rspec,
1089 rip_relative_correction);
1090 }
1091
1092 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1093 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1094 adr._rspec);
1095 }
1096
1097 // MMX operations
1098 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1099 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1100 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1101 }
1102
1103 // work around gcc (3.2.1-7a) bug
1104 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1105 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1106 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1107 }
1108
1109
1110 void Assembler::emit_farith(int b1, int b2, int i) {
1111 assert(isByte(b1) && isByte(b2), "wrong opcode");
1112 assert(0 <= i && i < 8, "illegal stack offset");
1113 emit_int8(b1);
1114 emit_int8(b2 + i);
1115 }
1116
1117
1118 // Now the Assembler instructions (identical for 32/64 bits)
1119
1120 void Assembler::adcl(Address dst, int32_t imm32) {
1121 InstructionMark im(this);
1122 prefix(dst);
1123 emit_arith_operand(0x81, rdx, dst, imm32);
1124 }
1125
1126 void Assembler::adcl(Address dst, Register src) {
1127 InstructionMark im(this);
1128 prefix(dst, src);
1129 emit_int8(0x11);
1130 emit_operand(src, dst);
1131 }
1132
1133 void Assembler::adcl(Register dst, int32_t imm32) {
1134 prefix(dst);
1135 emit_arith(0x81, 0xD0, dst, imm32);
1136 }
1137
1138 void Assembler::adcl(Register dst, Address src) {
1139 InstructionMark im(this);
1140 prefix(src, dst);
1141 emit_int8(0x13);
1142 emit_operand(dst, src);
1143 }
1144
1145 void Assembler::adcl(Register dst, Register src) {
1146 (void) prefix_and_encode(dst->encoding(), src->encoding());
1147 emit_arith(0x13, 0xC0, dst, src);
1148 }
1149
1150 void Assembler::addl(Address dst, int32_t imm32) {
1151 InstructionMark im(this);
1152 prefix(dst);
1153 emit_arith_operand(0x81, rax, dst, imm32);
1154 }
1155
1156 void Assembler::addl(Address dst, Register src) {
1157 InstructionMark im(this);
1158 prefix(dst, src);
1159 emit_int8(0x01);
1160 emit_operand(src, dst);
1161 }
1162
1163 void Assembler::addl(Register dst, int32_t imm32) {
1164 prefix(dst);
1165 emit_arith(0x81, 0xC0, dst, imm32);
1166 }
1167
1168 void Assembler::addl(Register dst, Address src) {
1169 InstructionMark im(this);
1170 prefix(src, dst);
1171 emit_int8(0x03);
1172 emit_operand(dst, src);
1173 }
1174
1175 void Assembler::addl(Register dst, Register src) {
1176 (void) prefix_and_encode(dst->encoding(), src->encoding());
1177 emit_arith(0x03, 0xC0, dst, src);
1178 }
1179
1180 void Assembler::addr_nop_4() {
1181 assert(UseAddressNop, "no CPU support");
1182 // 4 bytes: NOP DWORD PTR [EAX+0]
1183 emit_int8(0x0F);
1184 emit_int8(0x1F);
1185 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1186 emit_int8(0); // 8-bits offset (1 byte)
1187 }
1188
1189 void Assembler::addr_nop_5() {
1190 assert(UseAddressNop, "no CPU support");
1191 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1192 emit_int8(0x0F);
1193 emit_int8(0x1F);
1194 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1195 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1196 emit_int8(0); // 8-bits offset (1 byte)
1197 }
1198
1199 void Assembler::addr_nop_7() {
1200 assert(UseAddressNop, "no CPU support");
1201 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1202 emit_int8(0x0F);
1203 emit_int8(0x1F);
1204 emit_int8((unsigned char)0x80);
1205 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1206 emit_int32(0); // 32-bits offset (4 bytes)
1207 }
1208
1209 void Assembler::addr_nop_8() {
1210 assert(UseAddressNop, "no CPU support");
1211 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1212 emit_int8(0x0F);
1213 emit_int8(0x1F);
1214 emit_int8((unsigned char)0x84);
1215 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1216 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1217 emit_int32(0); // 32-bits offset (4 bytes)
1218 }
1219
1220 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1221 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1222 if (VM_Version::supports_evex()) {
1223 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_F2);
1224 } else {
1225 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
1226 }
1227 }
1228
1229 void Assembler::addsd(XMMRegister dst, Address src) {
1230 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1231 if (VM_Version::supports_evex()) {
1232 tuple_type = EVEX_T1S;
1233 input_size_in_bits = EVEX_64bit;
1234 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_F2);
1235 } else {
1236 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
1237 }
1238 }
1239
1240 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1241 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1242 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1243 }
1244
1245 void Assembler::addss(XMMRegister dst, Address src) {
1246 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1247 if (VM_Version::supports_evex()) {
1248 tuple_type = EVEX_T1S;
1249 input_size_in_bits = EVEX_32bit;
1250 }
1251 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1252 }
1253
1254 void Assembler::aesdec(XMMRegister dst, Address src) {
1255 assert(VM_Version::supports_aes(), "");
1256 InstructionMark im(this);
1257 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1258 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1259 emit_int8((unsigned char)0xDE);
1260 emit_operand(dst, src);
1261 }
1262
1263 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1264 assert(VM_Version::supports_aes(), "");
1265 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1266 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1267 emit_int8((unsigned char)0xDE);
1268 emit_int8(0xC0 | encode);
1269 }
1270
1271 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1272 assert(VM_Version::supports_aes(), "");
1273 InstructionMark im(this);
1274 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1275 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1276 emit_int8((unsigned char)0xDF);
1277 emit_operand(dst, src);
1278 }
1279
1280 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1281 assert(VM_Version::supports_aes(), "");
1282 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1283 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1284 emit_int8((unsigned char)0xDF);
1285 emit_int8((unsigned char)(0xC0 | encode));
1286 }
1287
1288 void Assembler::aesenc(XMMRegister dst, Address src) {
1289 assert(VM_Version::supports_aes(), "");
1290 InstructionMark im(this);
1291 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1292 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1293 emit_int8((unsigned char)0xDC);
1294 emit_operand(dst, src);
1295 }
1296
1297 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1298 assert(VM_Version::supports_aes(), "");
1299 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1300 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1301 emit_int8((unsigned char)0xDC);
1302 emit_int8(0xC0 | encode);
1303 }
1304
1305 void Assembler::aesenclast(XMMRegister dst, Address src) {
1306 assert(VM_Version::supports_aes(), "");
1307 InstructionMark im(this);
1308 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1309 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1310 emit_int8((unsigned char)0xDD);
1311 emit_operand(dst, src);
1312 }
1313
1314 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1315 assert(VM_Version::supports_aes(), "");
1316 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1317 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1318 emit_int8((unsigned char)0xDD);
1319 emit_int8((unsigned char)(0xC0 | encode));
1320 }
1321
1322
1323 void Assembler::andl(Address dst, int32_t imm32) {
1324 InstructionMark im(this);
1325 prefix(dst);
1326 emit_int8((unsigned char)0x81);
1327 emit_operand(rsp, dst, 4);
1328 emit_int32(imm32);
1329 }
1330
1331 void Assembler::andl(Register dst, int32_t imm32) {
1332 prefix(dst);
1333 emit_arith(0x81, 0xE0, dst, imm32);
1334 }
1335
1336 void Assembler::andl(Register dst, Address src) {
1337 InstructionMark im(this);
1338 prefix(src, dst);
1339 emit_int8(0x23);
1340 emit_operand(dst, src);
1341 }
1342
1343 void Assembler::andl(Register dst, Register src) {
1344 (void) prefix_and_encode(dst->encoding(), src->encoding());
1345 emit_arith(0x23, 0xC0, dst, src);
1346 }
1347
1348 void Assembler::andnl(Register dst, Register src1, Register src2) {
1349 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1350 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(),
1351 VEX_SIMD_NONE, VEX_OPCODE_0F_38, false, AVX_128bit,
1352 true, false);
1353 emit_int8((unsigned char)0xF2);
1354 emit_int8((unsigned char)(0xC0 | encode));
1355 }
1356
1357 void Assembler::andnl(Register dst, Register src1, Address src2) {
1358 InstructionMark im(this);
1359 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1360 vex_prefix(src2, src1->encoding(), dst->encoding(),
1361 VEX_SIMD_NONE, VEX_OPCODE_0F_38, false,
1362 AVX_128bit, true, false);
1363 emit_int8((unsigned char)0xF2);
1364 emit_operand(dst, src2);
1365 }
1366
1367 void Assembler::bsfl(Register dst, Register src) {
1368 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1369 emit_int8(0x0F);
1370 emit_int8((unsigned char)0xBC);
1371 emit_int8((unsigned char)(0xC0 | encode));
1372 }
1373
1374 void Assembler::bsrl(Register dst, Register src) {
1375 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1376 emit_int8(0x0F);
1377 emit_int8((unsigned char)0xBD);
1378 emit_int8((unsigned char)(0xC0 | encode));
1379 }
1380
1381 void Assembler::bswapl(Register reg) { // bswap
1382 int encode = prefix_and_encode(reg->encoding());
1383 emit_int8(0x0F);
1384 emit_int8((unsigned char)(0xC8 | encode));
1385 }
1386
1387 void Assembler::blsil(Register dst, Register src) {
1388 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1389 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(),
1390 VEX_SIMD_NONE, VEX_OPCODE_0F_38, false, AVX_128bit,
1391 true, false);
1392 emit_int8((unsigned char)0xF3);
1393 emit_int8((unsigned char)(0xC0 | encode));
1394 }
1395
1396 void Assembler::blsil(Register dst, Address src) {
1397 InstructionMark im(this);
1398 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1399 vex_prefix(src, dst->encoding(), rbx->encoding(),
1400 VEX_SIMD_NONE, VEX_OPCODE_0F_38, false,
1401 AVX_128bit, true, false);
1402 emit_int8((unsigned char)0xF3);
1403 emit_operand(rbx, src);
1404 }
1405
1406 void Assembler::blsmskl(Register dst, Register src) {
1407 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1408 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(),
1409 VEX_SIMD_NONE, VEX_OPCODE_0F_38, false, AVX_128bit,
1410 true, false);
1411 emit_int8((unsigned char)0xF3);
1412 emit_int8((unsigned char)(0xC0 | encode));
1413 }
1414
1415 void Assembler::blsmskl(Register dst, Address src) {
1416 InstructionMark im(this);
1417 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1418 vex_prefix_0F38(rdx, dst, src, false);
1419 emit_int8((unsigned char)0xF3);
1420 emit_operand(rdx, src);
1421 }
1422
1423 void Assembler::blsrl(Register dst, Register src) {
1424 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1425 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(),
1426 VEX_SIMD_NONE, VEX_OPCODE_0F_38, false, AVX_128bit,
1427 true, false);
1428 emit_int8((unsigned char)0xF3);
1429 emit_int8((unsigned char)(0xC0 | encode));
1430 }
1431
1432 void Assembler::blsrl(Register dst, Address src) {
1433 InstructionMark im(this);
1434 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1435 vex_prefix(src, dst->encoding(), rcx->encoding(),
1436 VEX_SIMD_NONE, VEX_OPCODE_0F_38, false,
1437 AVX_128bit, true, false);
1438 emit_int8((unsigned char)0xF3);
1439 emit_operand(rcx, src);
1440 }
1441
1442 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1443 // suspect disp32 is always good
1444 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1445
1446 if (L.is_bound()) {
1447 const int long_size = 5;
1448 int offs = (int)( target(L) - pc() );
1449 assert(offs <= 0, "assembler error");
1450 InstructionMark im(this);
1451 // 1110 1000 #32-bit disp
1452 emit_int8((unsigned char)0xE8);
1453 emit_data(offs - long_size, rtype, operand);
1454 } else {
1455 InstructionMark im(this);
1456 // 1110 1000 #32-bit disp
1457 L.add_patch_at(code(), locator());
1458
1459 emit_int8((unsigned char)0xE8);
1460 emit_data(int(0), rtype, operand);
1461 }
1462 }
1463
1464 void Assembler::call(Register dst) {
1465 int encode = prefix_and_encode(dst->encoding());
1466 emit_int8((unsigned char)0xFF);
1467 emit_int8((unsigned char)(0xD0 | encode));
1468 }
1469
1470
1471 void Assembler::call(Address adr) {
1472 InstructionMark im(this);
1473 prefix(adr);
1474 emit_int8((unsigned char)0xFF);
1475 emit_operand(rdx, adr);
1476 }
1477
1478 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1479 assert(entry != NULL, "call most probably wrong");
1480 InstructionMark im(this);
1481 emit_int8((unsigned char)0xE8);
1482 intptr_t disp = entry - (pc() + sizeof(int32_t));
1483 assert(is_simm32(disp), "must be 32bit offset (call2)");
1484 // Technically, should use call32_operand, but this format is
1485 // implied by the fact that we're emitting a call instruction.
1486
1487 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1488 emit_data((int) disp, rspec, operand);
1489 }
1490
1491 void Assembler::cdql() {
1492 emit_int8((unsigned char)0x99);
1493 }
1494
1495 void Assembler::cld() {
1496 emit_int8((unsigned char)0xFC);
1497 }
1498
1499 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1500 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1501 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1502 emit_int8(0x0F);
1503 emit_int8(0x40 | cc);
1504 emit_int8((unsigned char)(0xC0 | encode));
1505 }
1506
1507
1508 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1509 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1510 prefix(src, dst);
1511 emit_int8(0x0F);
1512 emit_int8(0x40 | cc);
1513 emit_operand(dst, src);
1514 }
1515
1516 void Assembler::cmpb(Address dst, int imm8) {
1517 InstructionMark im(this);
1518 prefix(dst);
1519 emit_int8((unsigned char)0x80);
1520 emit_operand(rdi, dst, 1);
1521 emit_int8(imm8);
1522 }
1523
1524 void Assembler::cmpl(Address dst, int32_t imm32) {
1525 InstructionMark im(this);
1526 prefix(dst);
1527 emit_int8((unsigned char)0x81);
1528 emit_operand(rdi, dst, 4);
1529 emit_int32(imm32);
1530 }
1531
1532 void Assembler::cmpl(Register dst, int32_t imm32) {
1533 prefix(dst);
1534 emit_arith(0x81, 0xF8, dst, imm32);
1535 }
1536
1537 void Assembler::cmpl(Register dst, Register src) {
1538 (void) prefix_and_encode(dst->encoding(), src->encoding());
1539 emit_arith(0x3B, 0xC0, dst, src);
1540 }
1541
1542
1543 void Assembler::cmpl(Register dst, Address src) {
1544 InstructionMark im(this);
1545 prefix(src, dst);
1546 emit_int8((unsigned char)0x3B);
1547 emit_operand(dst, src);
1548 }
1549
1550 void Assembler::cmpw(Address dst, int imm16) {
1551 InstructionMark im(this);
1552 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1553 emit_int8(0x66);
1554 emit_int8((unsigned char)0x81);
1555 emit_operand(rdi, dst, 2);
1556 emit_int16(imm16);
1557 }
1558
1559 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1560 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1561 // The ZF is set if the compared values were equal, and cleared otherwise.
1562 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1563 InstructionMark im(this);
1564 prefix(adr, reg);
1565 emit_int8(0x0F);
1566 emit_int8((unsigned char)0xB1);
1567 emit_operand(reg, adr);
1568 }
1569
1570 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1571 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1572 // The ZF is set if the compared values were equal, and cleared otherwise.
1573 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1574 InstructionMark im(this);
1575 prefix(adr, reg, true);
1576 emit_int8(0x0F);
1577 emit_int8((unsigned char)0xB0);
1578 emit_operand(reg, adr);
1579 }
1580
1581 void Assembler::comisd(XMMRegister dst, Address src) {
1582 // NOTE: dbx seems to decode this as comiss even though the
1583 // 0x66 is there. Strangly ucomisd comes out correct
1584 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1585 if (VM_Version::supports_evex()) {
1586 tuple_type = EVEX_T1S;
1587 input_size_in_bits = EVEX_64bit;
1588 emit_simd_arith_nonds_q(0x2F, dst, src, VEX_SIMD_66, true);
1589 } else {
1590 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1591 }
1592 }
1593
1594 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1595 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1596 if (VM_Version::supports_evex()) {
1597 emit_simd_arith_nonds_q(0x2F, dst, src, VEX_SIMD_66, true);
1598 } else {
1599 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1600 }
1601 }
1602
1603 void Assembler::comiss(XMMRegister dst, Address src) {
1604 if (VM_Version::supports_evex()) {
1605 tuple_type = EVEX_T1S;
1606 input_size_in_bits = EVEX_32bit;
1607 }
1608 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1609 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE, true);
1610 }
1611
1612 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1613 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1614 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE, true);
1615 }
1616
1617 void Assembler::cpuid() {
1618 emit_int8(0x0F);
1619 emit_int8((unsigned char)0xA2);
1620 }
1621
1622 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1623 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1624 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3);
1625 }
1626
1627 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1628 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1629 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE);
1630 }
1631
1632 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1633 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1634 if (VM_Version::supports_evex()) {
1635 emit_simd_arith_q(0x5A, dst, src, VEX_SIMD_F2);
1636 } else {
1637 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1638 }
1639 }
1640
1641 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1642 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1643 if (VM_Version::supports_evex()) {
1644 tuple_type = EVEX_T1F;
1645 input_size_in_bits = EVEX_64bit;
1646 emit_simd_arith_q(0x5A, dst, src, VEX_SIMD_F2);
1647 } else {
1648 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1649 }
1650 }
1651
1652 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1653 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1654 int encode = 0;
1655 if (VM_Version::supports_evex()) {
1656 encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2, true);
1657 } else {
1658 encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, false);
1659 }
1660 emit_int8(0x2A);
1661 emit_int8((unsigned char)(0xC0 | encode));
1662 }
1663
1664 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1665 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1666 if (VM_Version::supports_evex()) {
1667 tuple_type = EVEX_T1S;
1668 input_size_in_bits = EVEX_32bit;
1669 emit_simd_arith_q(0x2A, dst, src, VEX_SIMD_F2, true);
1670 } else {
1671 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2);
1672 }
1673 }
1674
1675 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1676 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1677 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, true);
1678 emit_int8(0x2A);
1679 emit_int8((unsigned char)(0xC0 | encode));
1680 }
1681
1682 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1683 if (VM_Version::supports_evex()) {
1684 tuple_type = EVEX_T1S;
1685 input_size_in_bits = EVEX_32bit;
1686 }
1687 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1688 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3, true);
1689 }
1690
1691 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1692 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1693 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1694 }
1695
1696 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1697 if (VM_Version::supports_evex()) {
1698 tuple_type = EVEX_T1S;
1699 input_size_in_bits = EVEX_32bit;
1700 }
1701 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1702 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1703 }
1704
1705
1706 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1707 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1708 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, true);
1709 emit_int8(0x2C);
1710 emit_int8((unsigned char)(0xC0 | encode));
1711 }
1712
1713 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1714 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1715 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, true);
1716 emit_int8(0x2C);
1717 emit_int8((unsigned char)(0xC0 | encode));
1718 }
1719
1720 void Assembler::decl(Address dst) {
1721 // Don't use it directly. Use MacroAssembler::decrement() instead.
1722 InstructionMark im(this);
1723 prefix(dst);
1724 emit_int8((unsigned char)0xFF);
1725 emit_operand(rcx, dst);
1726 }
1727
1728 void Assembler::divsd(XMMRegister dst, Address src) {
1729 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1730 if (VM_Version::supports_evex()) {
1731 tuple_type = EVEX_T1S;
1732 input_size_in_bits = EVEX_64bit;
1733 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_F2);
1734 } else {
1735 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1736 }
1737 }
1738
1739 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1740 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1741 if (VM_Version::supports_evex()) {
1742 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_F2);
1743 } else {
1744 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1745 }
1746 }
1747
1748 void Assembler::divss(XMMRegister dst, Address src) {
1749 if (VM_Version::supports_evex()) {
1750 tuple_type = EVEX_T1S;
1751 input_size_in_bits = EVEX_32bit;
1752 }
1753 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1754 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1755 }
1756
1757 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1758 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1759 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1760 }
1761
1762 void Assembler::emms() {
1763 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1764 emit_int8(0x0F);
1765 emit_int8(0x77);
1766 }
1767
1768 void Assembler::hlt() {
1769 emit_int8((unsigned char)0xF4);
1770 }
1771
1772 void Assembler::idivl(Register src) {
1773 int encode = prefix_and_encode(src->encoding());
1774 emit_int8((unsigned char)0xF7);
1775 emit_int8((unsigned char)(0xF8 | encode));
1776 }
1777
1778 void Assembler::divl(Register src) { // Unsigned
1779 int encode = prefix_and_encode(src->encoding());
1780 emit_int8((unsigned char)0xF7);
1781 emit_int8((unsigned char)(0xF0 | encode));
1782 }
1783
1784 void Assembler::imull(Register dst, Register src) {
1785 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1786 emit_int8(0x0F);
1787 emit_int8((unsigned char)0xAF);
1788 emit_int8((unsigned char)(0xC0 | encode));
1789 }
1790
1791
1792 void Assembler::imull(Register dst, Register src, int value) {
1793 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1794 if (is8bit(value)) {
1795 emit_int8(0x6B);
1796 emit_int8((unsigned char)(0xC0 | encode));
1797 emit_int8(value & 0xFF);
1798 } else {
1799 emit_int8(0x69);
1800 emit_int8((unsigned char)(0xC0 | encode));
1801 emit_int32(value);
1802 }
1803 }
1804
1805 void Assembler::imull(Register dst, Address src) {
1806 InstructionMark im(this);
1807 prefix(src, dst);
1808 emit_int8(0x0F);
1809 emit_int8((unsigned char) 0xAF);
1810 emit_operand(dst, src);
1811 }
1812
1813
1814 void Assembler::incl(Address dst) {
1815 // Don't use it directly. Use MacroAssembler::increment() instead.
1816 InstructionMark im(this);
1817 prefix(dst);
1818 emit_int8((unsigned char)0xFF);
1819 emit_operand(rax, dst);
1820 }
1821
1822 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1823 InstructionMark im(this);
1824 assert((0 <= cc) && (cc < 16), "illegal cc");
1825 if (L.is_bound()) {
1826 address dst = target(L);
1827 assert(dst != NULL, "jcc most probably wrong");
1828
1829 const int short_size = 2;
1830 const int long_size = 6;
1831 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1832 if (maybe_short && is8bit(offs - short_size)) {
1833 // 0111 tttn #8-bit disp
1834 emit_int8(0x70 | cc);
1835 emit_int8((offs - short_size) & 0xFF);
1836 } else {
1837 // 0000 1111 1000 tttn #32-bit disp
1838 assert(is_simm32(offs - long_size),
1839 "must be 32bit offset (call4)");
1840 emit_int8(0x0F);
1841 emit_int8((unsigned char)(0x80 | cc));
1842 emit_int32(offs - long_size);
1843 }
1844 } else {
1845 // Note: could eliminate cond. jumps to this jump if condition
1846 // is the same however, seems to be rather unlikely case.
1847 // Note: use jccb() if label to be bound is very close to get
1848 // an 8-bit displacement
1849 L.add_patch_at(code(), locator());
1850 emit_int8(0x0F);
1851 emit_int8((unsigned char)(0x80 | cc));
1852 emit_int32(0);
1853 }
1854 }
1855
1856 void Assembler::jccb(Condition cc, Label& L) {
1857 if (L.is_bound()) {
1858 const int short_size = 2;
1859 address entry = target(L);
1860 #ifdef ASSERT
1861 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1862 intptr_t delta = short_branch_delta();
1863 if (delta != 0) {
1864 dist += (dist < 0 ? (-delta) :delta);
1865 }
1866 assert(is8bit(dist), "Dispacement too large for a short jmp");
1867 #endif
1868 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1869 // 0111 tttn #8-bit disp
1870 emit_int8(0x70 | cc);
1871 emit_int8((offs - short_size) & 0xFF);
1872 } else {
1873 InstructionMark im(this);
1874 L.add_patch_at(code(), locator());
1875 emit_int8(0x70 | cc);
1876 emit_int8(0);
1877 }
1878 }
1879
1880 void Assembler::jmp(Address adr) {
1881 InstructionMark im(this);
1882 prefix(adr);
1883 emit_int8((unsigned char)0xFF);
1884 emit_operand(rsp, adr);
1885 }
1886
1887 void Assembler::jmp(Label& L, bool maybe_short) {
1888 if (L.is_bound()) {
1889 address entry = target(L);
1890 assert(entry != NULL, "jmp most probably wrong");
1891 InstructionMark im(this);
1892 const int short_size = 2;
1893 const int long_size = 5;
1894 intptr_t offs = entry - pc();
1895 if (maybe_short && is8bit(offs - short_size)) {
1896 emit_int8((unsigned char)0xEB);
1897 emit_int8((offs - short_size) & 0xFF);
1898 } else {
1899 emit_int8((unsigned char)0xE9);
1900 emit_int32(offs - long_size);
1901 }
1902 } else {
1903 // By default, forward jumps are always 32-bit displacements, since
1904 // we can't yet know where the label will be bound. If you're sure that
1905 // the forward jump will not run beyond 256 bytes, use jmpb to
1906 // force an 8-bit displacement.
1907 InstructionMark im(this);
1908 L.add_patch_at(code(), locator());
1909 emit_int8((unsigned char)0xE9);
1910 emit_int32(0);
1911 }
1912 }
1913
1914 void Assembler::jmp(Register entry) {
1915 int encode = prefix_and_encode(entry->encoding());
1916 emit_int8((unsigned char)0xFF);
1917 emit_int8((unsigned char)(0xE0 | encode));
1918 }
1919
1920 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1921 InstructionMark im(this);
1922 emit_int8((unsigned char)0xE9);
1923 assert(dest != NULL, "must have a target");
1924 intptr_t disp = dest - (pc() + sizeof(int32_t));
1925 assert(is_simm32(disp), "must be 32bit offset (jmp)");
1926 emit_data(disp, rspec.reloc(), call32_operand);
1927 }
1928
1929 void Assembler::jmpb(Label& L) {
1930 if (L.is_bound()) {
1931 const int short_size = 2;
1932 address entry = target(L);
1933 assert(entry != NULL, "jmp most probably wrong");
1934 #ifdef ASSERT
1935 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1936 intptr_t delta = short_branch_delta();
1937 if (delta != 0) {
1938 dist += (dist < 0 ? (-delta) :delta);
1939 }
1940 assert(is8bit(dist), "Dispacement too large for a short jmp");
1941 #endif
1942 intptr_t offs = entry - pc();
1943 emit_int8((unsigned char)0xEB);
1944 emit_int8((offs - short_size) & 0xFF);
1945 } else {
1946 InstructionMark im(this);
1947 L.add_patch_at(code(), locator());
1948 emit_int8((unsigned char)0xEB);
1949 emit_int8(0);
1950 }
1951 }
1952
1953 void Assembler::ldmxcsr( Address src) {
1954 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1955 InstructionMark im(this);
1956 prefix(src);
1957 emit_int8(0x0F);
1958 emit_int8((unsigned char)0xAE);
1959 emit_operand(as_Register(2), src);
1960 }
1961
1962 void Assembler::leal(Register dst, Address src) {
1963 InstructionMark im(this);
1964 #ifdef _LP64
1965 emit_int8(0x67); // addr32
1966 prefix(src, dst);
1967 #endif // LP64
1968 emit_int8((unsigned char)0x8D);
1969 emit_operand(dst, src);
1970 }
1971
1972 void Assembler::lfence() {
1973 emit_int8(0x0F);
1974 emit_int8((unsigned char)0xAE);
1975 emit_int8((unsigned char)0xE8);
1976 }
1977
1978 void Assembler::lock() {
1979 emit_int8((unsigned char)0xF0);
1980 }
1981
1982 void Assembler::lzcntl(Register dst, Register src) {
1983 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1984 emit_int8((unsigned char)0xF3);
1985 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1986 emit_int8(0x0F);
1987 emit_int8((unsigned char)0xBD);
1988 emit_int8((unsigned char)(0xC0 | encode));
1989 }
1990
1991 // Emit mfence instruction
1992 void Assembler::mfence() {
1993 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1994 emit_int8(0x0F);
1995 emit_int8((unsigned char)0xAE);
1996 emit_int8((unsigned char)0xF0);
1997 }
1998
1999 void Assembler::mov(Register dst, Register src) {
2000 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2001 }
2002
2003 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2004 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2005 if (VM_Version::supports_evex()) {
2006 emit_simd_arith_nonds_q(0x28, dst, src, VEX_SIMD_66, true);
2007 } else {
2008 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66);
2009 }
2010 }
2011
2012 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2013 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2014 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE);
2015 }
2016
2017 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2018 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2019 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, true, VEX_OPCODE_0F,
2020 false, AVX_128bit);
2021 emit_int8(0x16);
2022 emit_int8((unsigned char)(0xC0 | encode));
2023 }
2024
2025 void Assembler::movb(Register dst, Address src) {
2026 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2027 InstructionMark im(this);
2028 prefix(src, dst, true);
2029 emit_int8((unsigned char)0x8A);
2030 emit_operand(dst, src);
2031 }
2032
2033 void Assembler::kmovq(KRegister dst, KRegister src) {
2034 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2035 int encode = kreg_prefix_and_encode(dst, knoreg, src, VEX_SIMD_NONE,
2036 true, VEX_OPCODE_0F, true);
2037 emit_int8((unsigned char)0x90);
2038 emit_int8((unsigned char)(0xC0 | encode));
2039 }
2040
2041 void Assembler::kmovq(KRegister dst, Address src) {
2042 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2043 int dst_enc = dst->encoding();
2044 int nds_enc = 0;
2045 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_NONE,
2046 VEX_OPCODE_0F, true, AVX_128bit, true, true);
2047 emit_int8((unsigned char)0x90);
2048 emit_operand((Register)dst, src);
2049 }
2050
2051 void Assembler::kmovq(Address dst, KRegister src) {
2052 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2053 int src_enc = src->encoding();
2054 int nds_enc = 0;
2055 vex_prefix(dst, nds_enc, src_enc, VEX_SIMD_NONE,
2056 VEX_OPCODE_0F, true, AVX_128bit, true, true);
2057 emit_int8((unsigned char)0x90);
2058 emit_operand((Register)src, dst);
2059 }
2060
2061 void Assembler::kmovql(KRegister dst, Register src) {
2062 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2063 bool supports_bw = VM_Version::supports_avx512bw();
2064 VexSimdPrefix pre = supports_bw ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2065 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, true,
2066 VEX_OPCODE_0F, supports_bw);
2067 emit_int8((unsigned char)0x92);
2068 emit_int8((unsigned char)(0xC0 | encode));
2069 }
2070
2071 void Assembler::kmovdl(KRegister dst, Register src) {
2072 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2073 VexSimdPrefix pre = VM_Version::supports_avx512bw() ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2074 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, true, VEX_OPCODE_0F, false);
2075 emit_int8((unsigned char)0x92);
2076 emit_int8((unsigned char)(0xC0 | encode));
2077 }
2078
2079 void Assembler::movb(Address dst, int imm8) {
2080 InstructionMark im(this);
2081 prefix(dst);
2082 emit_int8((unsigned char)0xC6);
2083 emit_operand(rax, dst, 1);
2084 emit_int8(imm8);
2085 }
2086
2087
2088 void Assembler::movb(Address dst, Register src) {
2089 assert(src->has_byte_register(), "must have byte register");
2090 InstructionMark im(this);
2091 prefix(dst, src, true);
2092 emit_int8((unsigned char)0x88);
2093 emit_operand(src, dst);
2094 }
2095
2096 void Assembler::movdl(XMMRegister dst, Register src) {
2097 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2098 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, true);
2099 emit_int8(0x6E);
2100 emit_int8((unsigned char)(0xC0 | encode));
2101 }
2102
2103 void Assembler::movdl(Register dst, XMMRegister src) {
2104 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2105 // swap src/dst to get correct prefix
2106 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66, true);
2107 emit_int8(0x7E);
2108 emit_int8((unsigned char)(0xC0 | encode));
2109 }
2110
2111 void Assembler::movdl(XMMRegister dst, Address src) {
2112 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2113 if (VM_Version::supports_evex()) {
2114 tuple_type = EVEX_T1S;
2115 input_size_in_bits = EVEX_32bit;
2116 }
2117 InstructionMark im(this);
2118 simd_prefix(dst, src, VEX_SIMD_66, true, VEX_OPCODE_0F);
2119 emit_int8(0x6E);
2120 emit_operand(dst, src);
2121 }
2122
2123 void Assembler::movdl(Address dst, XMMRegister src) {
2124 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2125 if (VM_Version::supports_evex()) {
2126 tuple_type = EVEX_T1S;
2127 input_size_in_bits = EVEX_32bit;
2128 }
2129 InstructionMark im(this);
2130 simd_prefix(dst, src, VEX_SIMD_66, true);
2131 emit_int8(0x7E);
2132 emit_operand(src, dst);
2133 }
2134
2135 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2136 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2137 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
2138 }
2139
2140 void Assembler::movdqa(XMMRegister dst, Address src) {
2141 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2142 if (VM_Version::supports_evex()) {
2143 tuple_type = EVEX_FVM;
2144 }
2145 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
2146 }
2147
2148 void Assembler::movdqu(XMMRegister dst, Address src) {
2149 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2150 if (VM_Version::supports_evex()) {
2151 tuple_type = EVEX_FVM;
2152 }
2153 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
2154 }
2155
2156 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2157 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2158 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
2159 }
2160
2161 void Assembler::movdqu(Address dst, XMMRegister src) {
2162 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2163 if (VM_Version::supports_evex()) {
2164 tuple_type = EVEX_FVM;
2165 }
2166 InstructionMark im(this);
2167 simd_prefix(dst, src, VEX_SIMD_F3, false);
2168 emit_int8(0x7F);
2169 emit_operand(src, dst);
2170 }
2171
2172 // Move Unaligned 256bit Vector
2173 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2174 assert(UseAVX > 0, "");
2175 if (VM_Version::supports_evex()) {
2176 tuple_type = EVEX_FVM;
2177 }
2178 int vector_len = AVX_256bit;
2179 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector_len);
2180 emit_int8(0x6F);
2181 emit_int8((unsigned char)(0xC0 | encode));
2182 }
2183
2184 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2185 assert(UseAVX > 0, "");
2186 if (VM_Version::supports_evex()) {
2187 tuple_type = EVEX_FVM;
2188 }
2189 InstructionMark im(this);
2190 int vector_len = AVX_256bit;
2191 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector_len, false);
2192 emit_int8(0x6F);
2193 emit_operand(dst, src);
2194 }
2195
2196 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2197 assert(UseAVX > 0, "");
2198 if (VM_Version::supports_evex()) {
2199 tuple_type = EVEX_FVM;
2200 }
2201 InstructionMark im(this);
2202 int vector_len = AVX_256bit;
2203 // swap src<->dst for encoding
2204 assert(src != xnoreg, "sanity");
2205 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector_len, false);
2206 emit_int8(0x7F);
2207 emit_operand(src, dst);
2208 }
2209
2210 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2211 void Assembler::evmovdqu(XMMRegister dst, XMMRegister src, int vector_len) {
2212 assert(UseAVX > 0, "");
2213 int src_enc = src->encoding();
2214 int dst_enc = dst->encoding();
2215 int encode = vex_prefix_and_encode(dst_enc, 0, src_enc, VEX_SIMD_F3, VEX_OPCODE_0F,
2216 true, vector_len, false, false);
2217 emit_int8(0x6F);
2218 emit_int8((unsigned char)(0xC0 | encode));
2219 }
2220
2221 void Assembler::evmovdqu(XMMRegister dst, Address src, int vector_len) {
2222 assert(UseAVX > 0, "");
2223 InstructionMark im(this);
2224 if (VM_Version::supports_evex()) {
2225 tuple_type = EVEX_FVM;
2226 vex_prefix_q(dst, xnoreg, src, VEX_SIMD_F3, vector_len, false);
2227 } else {
2228 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector_len, false);
2229 }
2230 emit_int8(0x6F);
2231 emit_operand(dst, src);
2232 }
2233
2234 void Assembler::evmovdqu(Address dst, XMMRegister src, int vector_len) {
2235 assert(UseAVX > 0, "");
2236 InstructionMark im(this);
2237 assert(src != xnoreg, "sanity");
2238 if (VM_Version::supports_evex()) {
2239 tuple_type = EVEX_FVM;
2240 // swap src<->dst for encoding
2241 vex_prefix_q(src, xnoreg, dst, VEX_SIMD_F3, vector_len, false);
2242 } else {
2243 // swap src<->dst for encoding
2244 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector_len, false);
2245 }
2246 emit_int8(0x7F);
2247 emit_operand(src, dst);
2248 }
2249
2250 // Uses zero extension on 64bit
2251
2252 void Assembler::movl(Register dst, int32_t imm32) {
2253 int encode = prefix_and_encode(dst->encoding());
2254 emit_int8((unsigned char)(0xB8 | encode));
2255 emit_int32(imm32);
2256 }
2257
2258 void Assembler::movl(Register dst, Register src) {
2259 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2260 emit_int8((unsigned char)0x8B);
2261 emit_int8((unsigned char)(0xC0 | encode));
2262 }
2263
2264 void Assembler::movl(Register dst, Address src) {
2265 InstructionMark im(this);
2266 prefix(src, dst);
2267 emit_int8((unsigned char)0x8B);
2268 emit_operand(dst, src);
2269 }
2270
2271 void Assembler::movl(Address dst, int32_t imm32) {
2272 InstructionMark im(this);
2273 prefix(dst);
2274 emit_int8((unsigned char)0xC7);
2275 emit_operand(rax, dst, 4);
2276 emit_int32(imm32);
2277 }
2278
2279 void Assembler::movl(Address dst, Register src) {
2280 InstructionMark im(this);
2281 prefix(dst, src);
2282 emit_int8((unsigned char)0x89);
2283 emit_operand(src, dst);
2284 }
2285
2286 // New cpus require to use movsd and movss to avoid partial register stall
2287 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2288 // The selection is done in MacroAssembler::movdbl() and movflt().
2289 void Assembler::movlpd(XMMRegister dst, Address src) {
2290 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2291 if (VM_Version::supports_evex()) {
2292 tuple_type = EVEX_T1S;
2293 input_size_in_bits = EVEX_32bit;
2294 }
2295 emit_simd_arith(0x12, dst, src, VEX_SIMD_66, true);
2296 }
2297
2298 void Assembler::movq( MMXRegister dst, Address src ) {
2299 assert( VM_Version::supports_mmx(), "" );
2300 emit_int8(0x0F);
2301 emit_int8(0x6F);
2302 emit_operand(dst, src);
2303 }
2304
2305 void Assembler::movq( Address dst, MMXRegister src ) {
2306 assert( VM_Version::supports_mmx(), "" );
2307 emit_int8(0x0F);
2308 emit_int8(0x7F);
2309 // workaround gcc (3.2.1-7a) bug
2310 // In that version of gcc with only an emit_operand(MMX, Address)
2311 // gcc will tail jump and try and reverse the parameters completely
2312 // obliterating dst in the process. By having a version available
2313 // that doesn't need to swap the args at the tail jump the bug is
2314 // avoided.
2315 emit_operand(dst, src);
2316 }
2317
2318 void Assembler::movq(XMMRegister dst, Address src) {
2319 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2320 InstructionMark im(this);
2321 if (VM_Version::supports_evex()) {
2322 tuple_type = EVEX_T1S;
2323 input_size_in_bits = EVEX_64bit;
2324 simd_prefix_q(dst, xnoreg, src, VEX_SIMD_F3, true);
2325 } else {
2326 simd_prefix(dst, src, VEX_SIMD_F3, true, VEX_OPCODE_0F);
2327 }
2328 emit_int8(0x7E);
2329 emit_operand(dst, src);
2330 }
2331
2332 void Assembler::movq(Address dst, XMMRegister src) {
2333 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2334 InstructionMark im(this);
2335 if (VM_Version::supports_evex()) {
2336 tuple_type = EVEX_T1S;
2337 input_size_in_bits = EVEX_64bit;
2338 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, true,
2339 VEX_OPCODE_0F, true, AVX_128bit);
2340 } else {
2341 simd_prefix(dst, src, VEX_SIMD_66, true);
2342 }
2343 emit_int8((unsigned char)0xD6);
2344 emit_operand(src, dst);
2345 }
2346
2347 void Assembler::movsbl(Register dst, Address src) { // movsxb
2348 InstructionMark im(this);
2349 prefix(src, dst);
2350 emit_int8(0x0F);
2351 emit_int8((unsigned char)0xBE);
2352 emit_operand(dst, src);
2353 }
2354
2355 void Assembler::movsbl(Register dst, Register src) { // movsxb
2356 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2357 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
2358 emit_int8(0x0F);
2359 emit_int8((unsigned char)0xBE);
2360 emit_int8((unsigned char)(0xC0 | encode));
2361 }
2362
2363 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2364 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2365 if (VM_Version::supports_evex()) {
2366 emit_simd_arith_q(0x10, dst, src, VEX_SIMD_F2, true);
2367 } else {
2368 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2);
2369 }
2370 }
2371
2372 void Assembler::movsd(XMMRegister dst, Address src) {
2373 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2374 if (VM_Version::supports_evex()) {
2375 tuple_type = EVEX_T1S;
2376 input_size_in_bits = EVEX_64bit;
2377 emit_simd_arith_nonds_q(0x10, dst, src, VEX_SIMD_F2, true);
2378 } else {
2379 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2);
2380 }
2381 }
2382
2383 void Assembler::movsd(Address dst, XMMRegister src) {
2384 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2385 InstructionMark im(this);
2386 if (VM_Version::supports_evex()) {
2387 tuple_type = EVEX_T1S;
2388 input_size_in_bits = EVEX_64bit;
2389 simd_prefix_q(src, xnoreg, dst, VEX_SIMD_F2);
2390 } else {
2391 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, false);
2392 }
2393 emit_int8(0x11);
2394 emit_operand(src, dst);
2395 }
2396
2397 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2398 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2399 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3, true);
2400 }
2401
2402 void Assembler::movss(XMMRegister dst, Address src) {
2403 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2404 if (VM_Version::supports_evex()) {
2405 tuple_type = EVEX_T1S;
2406 input_size_in_bits = EVEX_32bit;
2407 }
2408 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3, true);
2409 }
2410
2411 void Assembler::movss(Address dst, XMMRegister src) {
2412 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2413 if (VM_Version::supports_evex()) {
2414 tuple_type = EVEX_T1S;
2415 input_size_in_bits = EVEX_32bit;
2416 }
2417 InstructionMark im(this);
2418 simd_prefix(dst, src, VEX_SIMD_F3, false);
2419 emit_int8(0x11);
2420 emit_operand(src, dst);
2421 }
2422
2423 void Assembler::movswl(Register dst, Address src) { // movsxw
2424 InstructionMark im(this);
2425 prefix(src, dst);
2426 emit_int8(0x0F);
2427 emit_int8((unsigned char)0xBF);
2428 emit_operand(dst, src);
2429 }
2430
2431 void Assembler::movswl(Register dst, Register src) { // movsxw
2432 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2433 emit_int8(0x0F);
2434 emit_int8((unsigned char)0xBF);
2435 emit_int8((unsigned char)(0xC0 | encode));
2436 }
2437
2438 void Assembler::movw(Address dst, int imm16) {
2439 InstructionMark im(this);
2440
2441 emit_int8(0x66); // switch to 16-bit mode
2442 prefix(dst);
2443 emit_int8((unsigned char)0xC7);
2444 emit_operand(rax, dst, 2);
2445 emit_int16(imm16);
2446 }
2447
2448 void Assembler::movw(Register dst, Address src) {
2449 InstructionMark im(this);
2450 emit_int8(0x66);
2451 prefix(src, dst);
2452 emit_int8((unsigned char)0x8B);
2453 emit_operand(dst, src);
2454 }
2455
2456 void Assembler::movw(Address dst, Register src) {
2457 InstructionMark im(this);
2458 emit_int8(0x66);
2459 prefix(dst, src);
2460 emit_int8((unsigned char)0x89);
2461 emit_operand(src, dst);
2462 }
2463
2464 void Assembler::movzbl(Register dst, Address src) { // movzxb
2465 InstructionMark im(this);
2466 prefix(src, dst);
2467 emit_int8(0x0F);
2468 emit_int8((unsigned char)0xB6);
2469 emit_operand(dst, src);
2470 }
2471
2472 void Assembler::movzbl(Register dst, Register src) { // movzxb
2473 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2474 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
2475 emit_int8(0x0F);
2476 emit_int8((unsigned char)0xB6);
2477 emit_int8(0xC0 | encode);
2478 }
2479
2480 void Assembler::movzwl(Register dst, Address src) { // movzxw
2481 InstructionMark im(this);
2482 prefix(src, dst);
2483 emit_int8(0x0F);
2484 emit_int8((unsigned char)0xB7);
2485 emit_operand(dst, src);
2486 }
2487
2488 void Assembler::movzwl(Register dst, Register src) { // movzxw
2489 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2490 emit_int8(0x0F);
2491 emit_int8((unsigned char)0xB7);
2492 emit_int8(0xC0 | encode);
2493 }
2494
2495 void Assembler::mull(Address src) {
2496 InstructionMark im(this);
2497 prefix(src);
2498 emit_int8((unsigned char)0xF7);
2499 emit_operand(rsp, src);
2500 }
2501
2502 void Assembler::mull(Register src) {
2503 int encode = prefix_and_encode(src->encoding());
2504 emit_int8((unsigned char)0xF7);
2505 emit_int8((unsigned char)(0xE0 | encode));
2506 }
2507
2508 void Assembler::mulsd(XMMRegister dst, Address src) {
2509 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2510 if (VM_Version::supports_evex()) {
2511 tuple_type = EVEX_T1S;
2512 input_size_in_bits = EVEX_64bit;
2513 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_F2);
2514 } else {
2515 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2516 }
2517 }
2518
2519 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2520 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2521 if (VM_Version::supports_evex()) {
2522 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_F2);
2523 } else {
2524 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2525 }
2526 }
2527
2528 void Assembler::mulss(XMMRegister dst, Address src) {
2529 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2530 if (VM_Version::supports_evex()) {
2531 tuple_type = EVEX_T1S;
2532 input_size_in_bits = EVEX_32bit;
2533 }
2534 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2535 }
2536
2537 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2538 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2539 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2540 }
2541
2542 void Assembler::negl(Register dst) {
2543 int encode = prefix_and_encode(dst->encoding());
2544 emit_int8((unsigned char)0xF7);
2545 emit_int8((unsigned char)(0xD8 | encode));
2546 }
2547
2548 void Assembler::nop(int i) {
2549 #ifdef ASSERT
2550 assert(i > 0, " ");
2551 // The fancy nops aren't currently recognized by debuggers making it a
2552 // pain to disassemble code while debugging. If asserts are on clearly
2553 // speed is not an issue so simply use the single byte traditional nop
2554 // to do alignment.
2555
2556 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2557 return;
2558
2559 #endif // ASSERT
2560
2561 if (UseAddressNop && VM_Version::is_intel()) {
2562 //
2563 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2564 // 1: 0x90
2565 // 2: 0x66 0x90
2566 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2567 // 4: 0x0F 0x1F 0x40 0x00
2568 // 5: 0x0F 0x1F 0x44 0x00 0x00
2569 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2570 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2571 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2572 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2573 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2574 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2575
2576 // The rest coding is Intel specific - don't use consecutive address nops
2577
2578 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2579 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2580 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2581 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2582
2583 while(i >= 15) {
2584 // For Intel don't generate consecutive addess nops (mix with regular nops)
2585 i -= 15;
2586 emit_int8(0x66); // size prefix
2587 emit_int8(0x66); // size prefix
2588 emit_int8(0x66); // size prefix
2589 addr_nop_8();
2590 emit_int8(0x66); // size prefix
2591 emit_int8(0x66); // size prefix
2592 emit_int8(0x66); // size prefix
2593 emit_int8((unsigned char)0x90);
2594 // nop
2595 }
2596 switch (i) {
2597 case 14:
2598 emit_int8(0x66); // size prefix
2599 case 13:
2600 emit_int8(0x66); // size prefix
2601 case 12:
2602 addr_nop_8();
2603 emit_int8(0x66); // size prefix
2604 emit_int8(0x66); // size prefix
2605 emit_int8(0x66); // size prefix
2606 emit_int8((unsigned char)0x90);
2607 // nop
2608 break;
2609 case 11:
2610 emit_int8(0x66); // size prefix
2611 case 10:
2612 emit_int8(0x66); // size prefix
2613 case 9:
2614 emit_int8(0x66); // size prefix
2615 case 8:
2616 addr_nop_8();
2617 break;
2618 case 7:
2619 addr_nop_7();
2620 break;
2621 case 6:
2622 emit_int8(0x66); // size prefix
2623 case 5:
2624 addr_nop_5();
2625 break;
2626 case 4:
2627 addr_nop_4();
2628 break;
2629 case 3:
2630 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2631 emit_int8(0x66); // size prefix
2632 case 2:
2633 emit_int8(0x66); // size prefix
2634 case 1:
2635 emit_int8((unsigned char)0x90);
2636 // nop
2637 break;
2638 default:
2639 assert(i == 0, " ");
2640 }
2641 return;
2642 }
2643 if (UseAddressNop && VM_Version::is_amd()) {
2644 //
2645 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2646 // 1: 0x90
2647 // 2: 0x66 0x90
2648 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2649 // 4: 0x0F 0x1F 0x40 0x00
2650 // 5: 0x0F 0x1F 0x44 0x00 0x00
2651 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2652 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2653 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2654 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2655 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2656 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2657
2658 // The rest coding is AMD specific - use consecutive address nops
2659
2660 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2661 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2662 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2663 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2664 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2665 // Size prefixes (0x66) are added for larger sizes
2666
2667 while(i >= 22) {
2668 i -= 11;
2669 emit_int8(0x66); // size prefix
2670 emit_int8(0x66); // size prefix
2671 emit_int8(0x66); // size prefix
2672 addr_nop_8();
2673 }
2674 // Generate first nop for size between 21-12
2675 switch (i) {
2676 case 21:
2677 i -= 1;
2678 emit_int8(0x66); // size prefix
2679 case 20:
2680 case 19:
2681 i -= 1;
2682 emit_int8(0x66); // size prefix
2683 case 18:
2684 case 17:
2685 i -= 1;
2686 emit_int8(0x66); // size prefix
2687 case 16:
2688 case 15:
2689 i -= 8;
2690 addr_nop_8();
2691 break;
2692 case 14:
2693 case 13:
2694 i -= 7;
2695 addr_nop_7();
2696 break;
2697 case 12:
2698 i -= 6;
2699 emit_int8(0x66); // size prefix
2700 addr_nop_5();
2701 break;
2702 default:
2703 assert(i < 12, " ");
2704 }
2705
2706 // Generate second nop for size between 11-1
2707 switch (i) {
2708 case 11:
2709 emit_int8(0x66); // size prefix
2710 case 10:
2711 emit_int8(0x66); // size prefix
2712 case 9:
2713 emit_int8(0x66); // size prefix
2714 case 8:
2715 addr_nop_8();
2716 break;
2717 case 7:
2718 addr_nop_7();
2719 break;
2720 case 6:
2721 emit_int8(0x66); // size prefix
2722 case 5:
2723 addr_nop_5();
2724 break;
2725 case 4:
2726 addr_nop_4();
2727 break;
2728 case 3:
2729 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2730 emit_int8(0x66); // size prefix
2731 case 2:
2732 emit_int8(0x66); // size prefix
2733 case 1:
2734 emit_int8((unsigned char)0x90);
2735 // nop
2736 break;
2737 default:
2738 assert(i == 0, " ");
2739 }
2740 return;
2741 }
2742
2743 // Using nops with size prefixes "0x66 0x90".
2744 // From AMD Optimization Guide:
2745 // 1: 0x90
2746 // 2: 0x66 0x90
2747 // 3: 0x66 0x66 0x90
2748 // 4: 0x66 0x66 0x66 0x90
2749 // 5: 0x66 0x66 0x90 0x66 0x90
2750 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2751 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2752 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2753 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2754 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2755 //
2756 while(i > 12) {
2757 i -= 4;
2758 emit_int8(0x66); // size prefix
2759 emit_int8(0x66);
2760 emit_int8(0x66);
2761 emit_int8((unsigned char)0x90);
2762 // nop
2763 }
2764 // 1 - 12 nops
2765 if(i > 8) {
2766 if(i > 9) {
2767 i -= 1;
2768 emit_int8(0x66);
2769 }
2770 i -= 3;
2771 emit_int8(0x66);
2772 emit_int8(0x66);
2773 emit_int8((unsigned char)0x90);
2774 }
2775 // 1 - 8 nops
2776 if(i > 4) {
2777 if(i > 6) {
2778 i -= 1;
2779 emit_int8(0x66);
2780 }
2781 i -= 3;
2782 emit_int8(0x66);
2783 emit_int8(0x66);
2784 emit_int8((unsigned char)0x90);
2785 }
2786 switch (i) {
2787 case 4:
2788 emit_int8(0x66);
2789 case 3:
2790 emit_int8(0x66);
2791 case 2:
2792 emit_int8(0x66);
2793 case 1:
2794 emit_int8((unsigned char)0x90);
2795 break;
2796 default:
2797 assert(i == 0, " ");
2798 }
2799 }
2800
2801 void Assembler::notl(Register dst) {
2802 int encode = prefix_and_encode(dst->encoding());
2803 emit_int8((unsigned char)0xF7);
2804 emit_int8((unsigned char)(0xD0 | encode));
2805 }
2806
2807 void Assembler::orl(Address dst, int32_t imm32) {
2808 InstructionMark im(this);
2809 prefix(dst);
2810 emit_arith_operand(0x81, rcx, dst, imm32);
2811 }
2812
2813 void Assembler::orl(Register dst, int32_t imm32) {
2814 prefix(dst);
2815 emit_arith(0x81, 0xC8, dst, imm32);
2816 }
2817
2818 void Assembler::orl(Register dst, Address src) {
2819 InstructionMark im(this);
2820 prefix(src, dst);
2821 emit_int8(0x0B);
2822 emit_operand(dst, src);
2823 }
2824
2825 void Assembler::orl(Register dst, Register src) {
2826 (void) prefix_and_encode(dst->encoding(), src->encoding());
2827 emit_arith(0x0B, 0xC0, dst, src);
2828 }
2829
2830 void Assembler::packuswb(XMMRegister dst, Address src) {
2831 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2832 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2833 if (VM_Version::supports_evex()) {
2834 tuple_type = EVEX_FV;
2835 input_size_in_bits = EVEX_32bit;
2836 }
2837 emit_simd_arith(0x67, dst, src, VEX_SIMD_66,
2838 false, (VM_Version::supports_avx512dq() == false));
2839 }
2840
2841 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2842 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2843 emit_simd_arith(0x67, dst, src, VEX_SIMD_66,
2844 false, (VM_Version::supports_avx512dq() == false));
2845 }
2846
2847 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2848 assert(UseAVX > 0, "some form of AVX must be enabled");
2849 emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector_len,
2850 false, (VM_Version::supports_avx512dq() == false));
2851 }
2852
2853 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
2854 assert(VM_Version::supports_avx2(), "");
2855 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false,
2856 VEX_OPCODE_0F_3A, true, vector_len);
2857 emit_int8(0x00);
2858 emit_int8(0xC0 | encode);
2859 emit_int8(imm8);
2860 }
2861
2862 void Assembler::pause() {
2863 emit_int8((unsigned char)0xF3);
2864 emit_int8((unsigned char)0x90);
2865 }
2866
2867 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2868 assert(VM_Version::supports_sse4_2(), "");
2869 InstructionMark im(this);
2870 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, false, VEX_OPCODE_0F_3A,
2871 false, AVX_128bit, true);
2872 emit_int8(0x61);
2873 emit_operand(dst, src);
2874 emit_int8(imm8);
2875 }
2876
2877 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2878 assert(VM_Version::supports_sse4_2(), "");
2879 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false,
2880 VEX_OPCODE_0F_3A, false, AVX_128bit, true);
2881 emit_int8(0x61);
2882 emit_int8((unsigned char)(0xC0 | encode));
2883 emit_int8(imm8);
2884 }
2885
2886 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
2887 assert(VM_Version::supports_sse4_1(), "");
2888 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2889 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2890 emit_int8(0x16);
2891 emit_int8((unsigned char)(0xC0 | encode));
2892 emit_int8(imm8);
2893 }
2894
2895 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
2896 assert(VM_Version::supports_sse4_1(), "");
2897 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2898 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2899 emit_int8(0x16);
2900 emit_int8((unsigned char)(0xC0 | encode));
2901 emit_int8(imm8);
2902 }
2903
2904 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
2905 assert(VM_Version::supports_sse4_1(), "");
2906 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2907 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2908 emit_int8(0x22);
2909 emit_int8((unsigned char)(0xC0 | encode));
2910 emit_int8(imm8);
2911 }
2912
2913 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
2914 assert(VM_Version::supports_sse4_1(), "");
2915 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2916 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2917 emit_int8(0x22);
2918 emit_int8((unsigned char)(0xC0 | encode));
2919 emit_int8(imm8);
2920 }
2921
2922 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
2923 assert(VM_Version::supports_sse4_1(), "");
2924 if (VM_Version::supports_evex()) {
2925 tuple_type = EVEX_HVM;
2926 }
2927 InstructionMark im(this);
2928 simd_prefix(dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38);
2929 emit_int8(0x30);
2930 emit_operand(dst, src);
2931 }
2932
2933 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2934 assert(VM_Version::supports_sse4_1(), "");
2935 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38);
2936 emit_int8(0x30);
2937 emit_int8((unsigned char)(0xC0 | encode));
2938 }
2939
2940 // generic
2941 void Assembler::pop(Register dst) {
2942 int encode = prefix_and_encode(dst->encoding());
2943 emit_int8(0x58 | encode);
2944 }
2945
2946 void Assembler::popcntl(Register dst, Address src) {
2947 assert(VM_Version::supports_popcnt(), "must support");
2948 InstructionMark im(this);
2949 emit_int8((unsigned char)0xF3);
2950 prefix(src, dst);
2951 emit_int8(0x0F);
2952 emit_int8((unsigned char)0xB8);
2953 emit_operand(dst, src);
2954 }
2955
2956 void Assembler::popcntl(Register dst, Register src) {
2957 assert(VM_Version::supports_popcnt(), "must support");
2958 emit_int8((unsigned char)0xF3);
2959 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2960 emit_int8(0x0F);
2961 emit_int8((unsigned char)0xB8);
2962 emit_int8((unsigned char)(0xC0 | encode));
2963 }
2964
2965 void Assembler::popf() {
2966 emit_int8((unsigned char)0x9D);
2967 }
2968
2969 #ifndef _LP64 // no 32bit push/pop on amd64
2970 void Assembler::popl(Address dst) {
2971 // NOTE: this will adjust stack by 8byte on 64bits
2972 InstructionMark im(this);
2973 prefix(dst);
2974 emit_int8((unsigned char)0x8F);
2975 emit_operand(rax, dst);
2976 }
2977 #endif
2978
2979 void Assembler::prefetch_prefix(Address src) {
2980 prefix(src);
2981 emit_int8(0x0F);
2982 }
2983
2984 void Assembler::prefetchnta(Address src) {
2985 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2986 InstructionMark im(this);
2987 prefetch_prefix(src);
2988 emit_int8(0x18);
2989 emit_operand(rax, src); // 0, src
2990 }
2991
2992 void Assembler::prefetchr(Address src) {
2993 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2994 InstructionMark im(this);
2995 prefetch_prefix(src);
2996 emit_int8(0x0D);
2997 emit_operand(rax, src); // 0, src
2998 }
2999
3000 void Assembler::prefetcht0(Address src) {
3001 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3002 InstructionMark im(this);
3003 prefetch_prefix(src);
3004 emit_int8(0x18);
3005 emit_operand(rcx, src); // 1, src
3006 }
3007
3008 void Assembler::prefetcht1(Address src) {
3009 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3010 InstructionMark im(this);
3011 prefetch_prefix(src);
3012 emit_int8(0x18);
3013 emit_operand(rdx, src); // 2, src
3014 }
3015
3016 void Assembler::prefetcht2(Address src) {
3017 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3018 InstructionMark im(this);
3019 prefetch_prefix(src);
3020 emit_int8(0x18);
3021 emit_operand(rbx, src); // 3, src
3022 }
3023
3024 void Assembler::prefetchw(Address src) {
3025 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3026 InstructionMark im(this);
3027 prefetch_prefix(src);
3028 emit_int8(0x0D);
3029 emit_operand(rcx, src); // 1, src
3030 }
3031
3032 void Assembler::prefix(Prefix p) {
3033 emit_int8(p);
3034 }
3035
3036 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3037 assert(VM_Version::supports_ssse3(), "");
3038 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38,
3039 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3040 emit_int8(0x00);
3041 emit_int8((unsigned char)(0xC0 | encode));
3042 }
3043
3044 void Assembler::pshufb(XMMRegister dst, Address src) {
3045 assert(VM_Version::supports_ssse3(), "");
3046 if (VM_Version::supports_evex()) {
3047 tuple_type = EVEX_FVM;
3048 }
3049 InstructionMark im(this);
3050 simd_prefix(dst, dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38,
3051 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3052 emit_int8(0x00);
3053 emit_operand(dst, src);
3054 }
3055
3056 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
3057 assert(isByte(mode), "invalid value");
3058 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3059 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
3060 emit_int8(mode & 0xFF);
3061
3062 }
3063
3064 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
3065 assert(isByte(mode), "invalid value");
3066 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3067 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3068 if (VM_Version::supports_evex()) {
3069 tuple_type = EVEX_FV;
3070 input_size_in_bits = EVEX_32bit;
3071 }
3072 InstructionMark im(this);
3073 simd_prefix(dst, src, VEX_SIMD_66, false);
3074 emit_int8(0x70);
3075 emit_operand(dst, src);
3076 emit_int8(mode & 0xFF);
3077 }
3078
3079 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3080 assert(isByte(mode), "invalid value");
3081 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3082 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2, false,
3083 (VM_Version::supports_avx512bw() == false));
3084 emit_int8(mode & 0xFF);
3085 }
3086
3087 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3088 assert(isByte(mode), "invalid value");
3089 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3090 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3091 if (VM_Version::supports_evex()) {
3092 tuple_type = EVEX_FVM;
3093 }
3094 InstructionMark im(this);
3095 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, false, VEX_OPCODE_0F,
3096 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3097 emit_int8(0x70);
3098 emit_operand(dst, src);
3099 emit_int8(mode & 0xFF);
3100 }
3101
3102 void Assembler::psrldq(XMMRegister dst, int shift) {
3103 // Shift 128 bit value in xmm register by number of bytes.
3104 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3105 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, true, VEX_OPCODE_0F,
3106 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3107 emit_int8(0x73);
3108 emit_int8((unsigned char)(0xC0 | encode));
3109 emit_int8(shift);
3110 }
3111
3112 void Assembler::ptest(XMMRegister dst, Address src) {
3113 assert(VM_Version::supports_sse4_1(), "");
3114 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3115 InstructionMark im(this);
3116 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, false,
3117 VEX_OPCODE_0F_38, false, AVX_128bit, true);
3118 emit_int8(0x17);
3119 emit_operand(dst, src);
3120 }
3121
3122 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3123 assert(VM_Version::supports_sse4_1(), "");
3124 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false,
3125 VEX_OPCODE_0F_38, false, AVX_128bit, true);
3126 emit_int8(0x17);
3127 emit_int8((unsigned char)(0xC0 | encode));
3128 }
3129
3130 void Assembler::vptest(XMMRegister dst, Address src) {
3131 assert(VM_Version::supports_avx(), "");
3132 InstructionMark im(this);
3133 int vector_len = AVX_256bit;
3134 assert(dst != xnoreg, "sanity");
3135 int dst_enc = dst->encoding();
3136 // swap src<->dst for encoding
3137 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector_len, true, false);
3138 emit_int8(0x17);
3139 emit_operand(dst, src);
3140 }
3141
3142 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
3143 assert(VM_Version::supports_avx(), "");
3144 int vector_len = AVX_256bit;
3145 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
3146 vector_len, VEX_OPCODE_0F_38, true, false);
3147 emit_int8(0x17);
3148 emit_int8((unsigned char)(0xC0 | encode));
3149 }
3150
3151 void Assembler::punpcklbw(XMMRegister dst, Address src) {
3152 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3153 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3154 if (VM_Version::supports_evex()) {
3155 tuple_type = EVEX_FVM;
3156 }
3157 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
3158 }
3159
3160 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3161 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3162 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
3163 }
3164
3165 void Assembler::punpckldq(XMMRegister dst, Address src) {
3166 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3167 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3168 if (VM_Version::supports_evex()) {
3169 tuple_type = EVEX_FV;
3170 input_size_in_bits = EVEX_32bit;
3171 }
3172 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
3173 }
3174
3175 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
3176 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3177 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
3178 }
3179
3180 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
3181 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3182 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66);
3183 }
3184
3185 void Assembler::push(int32_t imm32) {
3186 // in 64bits we push 64bits onto the stack but only
3187 // take a 32bit immediate
3188 emit_int8(0x68);
3189 emit_int32(imm32);
3190 }
3191
3192 void Assembler::push(Register src) {
3193 int encode = prefix_and_encode(src->encoding());
3194
3195 emit_int8(0x50 | encode);
3196 }
3197
3198 void Assembler::pushf() {
3199 emit_int8((unsigned char)0x9C);
3200 }
3201
3202 #ifndef _LP64 // no 32bit push/pop on amd64
3203 void Assembler::pushl(Address src) {
3204 // Note this will push 64bit on 64bit
3205 InstructionMark im(this);
3206 prefix(src);
3207 emit_int8((unsigned char)0xFF);
3208 emit_operand(rsi, src);
3209 }
3210 #endif
3211
3212 void Assembler::rcll(Register dst, int imm8) {
3213 assert(isShiftCount(imm8), "illegal shift count");
3214 int encode = prefix_and_encode(dst->encoding());
3215 if (imm8 == 1) {
3216 emit_int8((unsigned char)0xD1);
3217 emit_int8((unsigned char)(0xD0 | encode));
3218 } else {
3219 emit_int8((unsigned char)0xC1);
3220 emit_int8((unsigned char)0xD0 | encode);
3221 emit_int8(imm8);
3222 }
3223 }
3224
3225 void Assembler::rdtsc() {
3226 emit_int8((unsigned char)0x0F);
3227 emit_int8((unsigned char)0x31);
3228 }
3229
3230 // copies data from [esi] to [edi] using rcx pointer sized words
3231 // generic
3232 void Assembler::rep_mov() {
3233 emit_int8((unsigned char)0xF3);
3234 // MOVSQ
3235 LP64_ONLY(prefix(REX_W));
3236 emit_int8((unsigned char)0xA5);
3237 }
3238
3239 // sets rcx bytes with rax, value at [edi]
3240 void Assembler::rep_stosb() {
3241 emit_int8((unsigned char)0xF3); // REP
3242 LP64_ONLY(prefix(REX_W));
3243 emit_int8((unsigned char)0xAA); // STOSB
3244 }
3245
3246 // sets rcx pointer sized words with rax, value at [edi]
3247 // generic
3248 void Assembler::rep_stos() {
3249 emit_int8((unsigned char)0xF3); // REP
3250 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
3251 emit_int8((unsigned char)0xAB);
3252 }
3253
3254 // scans rcx pointer sized words at [edi] for occurance of rax,
3255 // generic
3256 void Assembler::repne_scan() { // repne_scan
3257 emit_int8((unsigned char)0xF2);
3258 // SCASQ
3259 LP64_ONLY(prefix(REX_W));
3260 emit_int8((unsigned char)0xAF);
3261 }
3262
3263 #ifdef _LP64
3264 // scans rcx 4 byte words at [edi] for occurance of rax,
3265 // generic
3266 void Assembler::repne_scanl() { // repne_scan
3267 emit_int8((unsigned char)0xF2);
3268 // SCASL
3269 emit_int8((unsigned char)0xAF);
3270 }
3271 #endif
3272
3273 void Assembler::ret(int imm16) {
3274 if (imm16 == 0) {
3275 emit_int8((unsigned char)0xC3);
3276 } else {
3277 emit_int8((unsigned char)0xC2);
3278 emit_int16(imm16);
3279 }
3280 }
3281
3282 void Assembler::sahf() {
3283 #ifdef _LP64
3284 // Not supported in 64bit mode
3285 ShouldNotReachHere();
3286 #endif
3287 emit_int8((unsigned char)0x9E);
3288 }
3289
3290 void Assembler::sarl(Register dst, int imm8) {
3291 int encode = prefix_and_encode(dst->encoding());
3292 assert(isShiftCount(imm8), "illegal shift count");
3293 if (imm8 == 1) {
3294 emit_int8((unsigned char)0xD1);
3295 emit_int8((unsigned char)(0xF8 | encode));
3296 } else {
3297 emit_int8((unsigned char)0xC1);
3298 emit_int8((unsigned char)(0xF8 | encode));
3299 emit_int8(imm8);
3300 }
3301 }
3302
3303 void Assembler::sarl(Register dst) {
3304 int encode = prefix_and_encode(dst->encoding());
3305 emit_int8((unsigned char)0xD3);
3306 emit_int8((unsigned char)(0xF8 | encode));
3307 }
3308
3309 void Assembler::sbbl(Address dst, int32_t imm32) {
3310 InstructionMark im(this);
3311 prefix(dst);
3312 emit_arith_operand(0x81, rbx, dst, imm32);
3313 }
3314
3315 void Assembler::sbbl(Register dst, int32_t imm32) {
3316 prefix(dst);
3317 emit_arith(0x81, 0xD8, dst, imm32);
3318 }
3319
3320
3321 void Assembler::sbbl(Register dst, Address src) {
3322 InstructionMark im(this);
3323 prefix(src, dst);
3324 emit_int8(0x1B);
3325 emit_operand(dst, src);
3326 }
3327
3328 void Assembler::sbbl(Register dst, Register src) {
3329 (void) prefix_and_encode(dst->encoding(), src->encoding());
3330 emit_arith(0x1B, 0xC0, dst, src);
3331 }
3332
3333 void Assembler::setb(Condition cc, Register dst) {
3334 assert(0 <= cc && cc < 16, "illegal cc");
3335 int encode = prefix_and_encode(dst->encoding(), true);
3336 emit_int8(0x0F);
3337 emit_int8((unsigned char)0x90 | cc);
3338 emit_int8((unsigned char)(0xC0 | encode));
3339 }
3340
3341 void Assembler::shll(Register dst, int imm8) {
3342 assert(isShiftCount(imm8), "illegal shift count");
3343 int encode = prefix_and_encode(dst->encoding());
3344 if (imm8 == 1 ) {
3345 emit_int8((unsigned char)0xD1);
3346 emit_int8((unsigned char)(0xE0 | encode));
3347 } else {
3348 emit_int8((unsigned char)0xC1);
3349 emit_int8((unsigned char)(0xE0 | encode));
3350 emit_int8(imm8);
3351 }
3352 }
3353
3354 void Assembler::shll(Register dst) {
3355 int encode = prefix_and_encode(dst->encoding());
3356 emit_int8((unsigned char)0xD3);
3357 emit_int8((unsigned char)(0xE0 | encode));
3358 }
3359
3360 void Assembler::shrl(Register dst, int imm8) {
3361 assert(isShiftCount(imm8), "illegal shift count");
3362 int encode = prefix_and_encode(dst->encoding());
3363 emit_int8((unsigned char)0xC1);
3364 emit_int8((unsigned char)(0xE8 | encode));
3365 emit_int8(imm8);
3366 }
3367
3368 void Assembler::shrl(Register dst) {
3369 int encode = prefix_and_encode(dst->encoding());
3370 emit_int8((unsigned char)0xD3);
3371 emit_int8((unsigned char)(0xE8 | encode));
3372 }
3373
3374 // copies a single word from [esi] to [edi]
3375 void Assembler::smovl() {
3376 emit_int8((unsigned char)0xA5);
3377 }
3378
3379 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
3380 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3381 if (VM_Version::supports_evex()) {
3382 emit_simd_arith_q(0x51, dst, src, VEX_SIMD_F2);
3383 } else {
3384 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
3385 }
3386 }
3387
3388 void Assembler::sqrtsd(XMMRegister dst, Address src) {
3389 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3390 if (VM_Version::supports_evex()) {
3391 tuple_type = EVEX_T1S;
3392 input_size_in_bits = EVEX_64bit;
3393 emit_simd_arith_q(0x51, dst, src, VEX_SIMD_F2);
3394 } else {
3395 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
3396 }
3397 }
3398
3399 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
3400 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3401 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
3402 }
3403
3404 void Assembler::std() {
3405 emit_int8((unsigned char)0xFD);
3406 }
3407
3408 void Assembler::sqrtss(XMMRegister dst, Address src) {
3409 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3410 if (VM_Version::supports_evex()) {
3411 tuple_type = EVEX_T1S;
3412 input_size_in_bits = EVEX_32bit;
3413 }
3414 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
3415 }
3416
3417 void Assembler::stmxcsr( Address dst) {
3418 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3419 InstructionMark im(this);
3420 prefix(dst);
3421 emit_int8(0x0F);
3422 emit_int8((unsigned char)0xAE);
3423 emit_operand(as_Register(3), dst);
3424 }
3425
3426 void Assembler::subl(Address dst, int32_t imm32) {
3427 InstructionMark im(this);
3428 prefix(dst);
3429 emit_arith_operand(0x81, rbp, dst, imm32);
3430 }
3431
3432 void Assembler::subl(Address dst, Register src) {
3433 InstructionMark im(this);
3434 prefix(dst, src);
3435 emit_int8(0x29);
3436 emit_operand(src, dst);
3437 }
3438
3439 void Assembler::subl(Register dst, int32_t imm32) {
3440 prefix(dst);
3441 emit_arith(0x81, 0xE8, dst, imm32);
3442 }
3443
3444 // Force generation of a 4 byte immediate value even if it fits into 8bit
3445 void Assembler::subl_imm32(Register dst, int32_t imm32) {
3446 prefix(dst);
3447 emit_arith_imm32(0x81, 0xE8, dst, imm32);
3448 }
3449
3450 void Assembler::subl(Register dst, Address src) {
3451 InstructionMark im(this);
3452 prefix(src, dst);
3453 emit_int8(0x2B);
3454 emit_operand(dst, src);
3455 }
3456
3457 void Assembler::subl(Register dst, Register src) {
3458 (void) prefix_and_encode(dst->encoding(), src->encoding());
3459 emit_arith(0x2B, 0xC0, dst, src);
3460 }
3461
3462 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
3463 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3464 if (VM_Version::supports_evex()) {
3465 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_F2);
3466 } else {
3467 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
3468 }
3469 }
3470
3471 void Assembler::subsd(XMMRegister dst, Address src) {
3472 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3473 if (VM_Version::supports_evex()) {
3474 tuple_type = EVEX_T1S;
3475 input_size_in_bits = EVEX_64bit;
3476 }
3477 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_F2);
3478 }
3479
3480 void Assembler::subss(XMMRegister dst, XMMRegister src) {
3481 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3482 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
3483 }
3484
3485 void Assembler::subss(XMMRegister dst, Address src) {
3486 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3487 if (VM_Version::supports_evex()) {
3488 tuple_type = EVEX_T1S;
3489 input_size_in_bits = EVEX_32bit;
3490 }
3491 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
3492 }
3493
3494 void Assembler::testb(Register dst, int imm8) {
3495 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
3496 (void) prefix_and_encode(dst->encoding(), true);
3497 emit_arith_b(0xF6, 0xC0, dst, imm8);
3498 }
3499
3500 void Assembler::testl(Register dst, int32_t imm32) {
3501 // not using emit_arith because test
3502 // doesn't support sign-extension of
3503 // 8bit operands
3504 int encode = dst->encoding();
3505 if (encode == 0) {
3506 emit_int8((unsigned char)0xA9);
3507 } else {
3508 encode = prefix_and_encode(encode);
3509 emit_int8((unsigned char)0xF7);
3510 emit_int8((unsigned char)(0xC0 | encode));
3511 }
3512 emit_int32(imm32);
3513 }
3514
3515 void Assembler::testl(Register dst, Register src) {
3516 (void) prefix_and_encode(dst->encoding(), src->encoding());
3517 emit_arith(0x85, 0xC0, dst, src);
3518 }
3519
3520 void Assembler::testl(Register dst, Address src) {
3521 InstructionMark im(this);
3522 prefix(src, dst);
3523 emit_int8((unsigned char)0x85);
3524 emit_operand(dst, src);
3525 }
3526
3527 void Assembler::tzcntl(Register dst, Register src) {
3528 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
3529 emit_int8((unsigned char)0xF3);
3530 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3531 emit_int8(0x0F);
3532 emit_int8((unsigned char)0xBC);
3533 emit_int8((unsigned char)0xC0 | encode);
3534 }
3535
3536 void Assembler::tzcntq(Register dst, Register src) {
3537 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
3538 emit_int8((unsigned char)0xF3);
3539 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3540 emit_int8(0x0F);
3541 emit_int8((unsigned char)0xBC);
3542 emit_int8((unsigned char)(0xC0 | encode));
3543 }
3544
3545 void Assembler::ucomisd(XMMRegister dst, Address src) {
3546 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3547 if (VM_Version::supports_evex()) {
3548 tuple_type = EVEX_T1S;
3549 input_size_in_bits = EVEX_64bit;
3550 emit_simd_arith_nonds_q(0x2E, dst, src, VEX_SIMD_66, true);
3551 } else {
3552 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
3553 }
3554 }
3555
3556 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
3557 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3558 if (VM_Version::supports_evex()) {
3559 emit_simd_arith_nonds_q(0x2E, dst, src, VEX_SIMD_66, true);
3560 } else {
3561 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
3562 }
3563 }
3564
3565 void Assembler::ucomiss(XMMRegister dst, Address src) {
3566 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3567 if (VM_Version::supports_evex()) {
3568 tuple_type = EVEX_T1S;
3569 input_size_in_bits = EVEX_32bit;
3570 }
3571 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE, true);
3572 }
3573
3574 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
3575 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3576 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE, true);
3577 }
3578
3579 void Assembler::xabort(int8_t imm8) {
3580 emit_int8((unsigned char)0xC6);
3581 emit_int8((unsigned char)0xF8);
3582 emit_int8((unsigned char)(imm8 & 0xFF));
3583 }
3584
3585 void Assembler::xaddl(Address dst, Register src) {
3586 InstructionMark im(this);
3587 prefix(dst, src);
3588 emit_int8(0x0F);
3589 emit_int8((unsigned char)0xC1);
3590 emit_operand(src, dst);
3591 }
3592
3593 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
3594 InstructionMark im(this);
3595 relocate(rtype);
3596 if (abort.is_bound()) {
3597 address entry = target(abort);
3598 assert(entry != NULL, "abort entry NULL");
3599 intptr_t offset = entry - pc();
3600 emit_int8((unsigned char)0xC7);
3601 emit_int8((unsigned char)0xF8);
3602 emit_int32(offset - 6); // 2 opcode + 4 address
3603 } else {
3604 abort.add_patch_at(code(), locator());
3605 emit_int8((unsigned char)0xC7);
3606 emit_int8((unsigned char)0xF8);
3607 emit_int32(0);
3608 }
3609 }
3610
3611 void Assembler::xchgl(Register dst, Address src) { // xchg
3612 InstructionMark im(this);
3613 prefix(src, dst);
3614 emit_int8((unsigned char)0x87);
3615 emit_operand(dst, src);
3616 }
3617
3618 void Assembler::xchgl(Register dst, Register src) {
3619 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3620 emit_int8((unsigned char)0x87);
3621 emit_int8((unsigned char)(0xC0 | encode));
3622 }
3623
3624 void Assembler::xend() {
3625 emit_int8((unsigned char)0x0F);
3626 emit_int8((unsigned char)0x01);
3627 emit_int8((unsigned char)0xD5);
3628 }
3629
3630 void Assembler::xgetbv() {
3631 emit_int8(0x0F);
3632 emit_int8(0x01);
3633 emit_int8((unsigned char)0xD0);
3634 }
3635
3636 void Assembler::xorl(Register dst, int32_t imm32) {
3637 prefix(dst);
3638 emit_arith(0x81, 0xF0, dst, imm32);
3639 }
3640
3641 void Assembler::xorl(Register dst, Address src) {
3642 InstructionMark im(this);
3643 prefix(src, dst);
3644 emit_int8(0x33);
3645 emit_operand(dst, src);
3646 }
3647
3648 void Assembler::xorl(Register dst, Register src) {
3649 (void) prefix_and_encode(dst->encoding(), src->encoding());
3650 emit_arith(0x33, 0xC0, dst, src);
3651 }
3652
3653
3654 // AVX 3-operands scalar float-point arithmetic instructions
3655
3656 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
3657 assert(VM_Version::supports_avx(), "");
3658 if (VM_Version::supports_evex()) {
3659 tuple_type = EVEX_T1S;
3660 input_size_in_bits = EVEX_64bit;
3661 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3662 } else {
3663 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3664 }
3665 }
3666
3667 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3668 assert(VM_Version::supports_avx(), "");
3669 if (VM_Version::supports_evex()) {
3670 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3671 } else {
3672 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3673 }
3674 }
3675
3676 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
3677 assert(VM_Version::supports_avx(), "");
3678 if (VM_Version::supports_evex()) {
3679 tuple_type = EVEX_T1S;
3680 input_size_in_bits = EVEX_32bit;
3681 }
3682 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3683 }
3684
3685 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3686 assert(VM_Version::supports_avx(), "");
3687 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3688 }
3689
3690 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
3691 assert(VM_Version::supports_avx(), "");
3692 if (VM_Version::supports_evex()) {
3693 tuple_type = EVEX_T1S;
3694 input_size_in_bits = EVEX_64bit;
3695 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3696 } else {
3697 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3698 }
3699 }
3700
3701 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3702 assert(VM_Version::supports_avx(), "");
3703 if (VM_Version::supports_evex()) {
3704 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3705 } else {
3706 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3707 }
3708 }
3709
3710 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
3711 assert(VM_Version::supports_avx(), "");
3712 if (VM_Version::supports_evex()) {
3713 tuple_type = EVEX_T1S;
3714 input_size_in_bits = EVEX_32bit;
3715 }
3716 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3717 }
3718
3719 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3720 assert(VM_Version::supports_avx(), "");
3721 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3722 }
3723
3724 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
3725 assert(VM_Version::supports_avx(), "");
3726 if (VM_Version::supports_evex()) {
3727 tuple_type = EVEX_T1S;
3728 input_size_in_bits = EVEX_64bit;
3729 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3730 } else {
3731 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3732 }
3733 }
3734
3735 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3736 assert(VM_Version::supports_avx(), "");
3737 if (VM_Version::supports_evex()) {
3738 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3739 } else {
3740 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3741 }
3742 }
3743
3744 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
3745 assert(VM_Version::supports_avx(), "");
3746 if (VM_Version::supports_evex()) {
3747 tuple_type = EVEX_T1S;
3748 input_size_in_bits = EVEX_32bit;
3749 }
3750 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3751 }
3752
3753 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3754 assert(VM_Version::supports_avx(), "");
3755 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3756 }
3757
3758 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
3759 assert(VM_Version::supports_avx(), "");
3760 if (VM_Version::supports_evex()) {
3761 tuple_type = EVEX_T1S;
3762 input_size_in_bits = EVEX_64bit;
3763 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3764 } else {
3765 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3766 }
3767 }
3768
3769 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3770 assert(VM_Version::supports_avx(), "");
3771 if (VM_Version::supports_evex()) {
3772 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3773 } else {
3774 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3775 }
3776 }
3777
3778 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
3779 assert(VM_Version::supports_avx(), "");
3780 if (VM_Version::supports_evex()) {
3781 tuple_type = EVEX_T1S;
3782 input_size_in_bits = EVEX_32bit;
3783 }
3784 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3785 }
3786
3787 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3788 assert(VM_Version::supports_avx(), "");
3789 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3790 }
3791
3792 //====================VECTOR ARITHMETIC=====================================
3793
3794 // Float-point vector arithmetic
3795
3796 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
3797 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3798 if (VM_Version::supports_evex()) {
3799 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_66);
3800 } else {
3801 emit_simd_arith(0x58, dst, src, VEX_SIMD_66);
3802 }
3803 }
3804
3805 void Assembler::addps(XMMRegister dst, XMMRegister src) {
3806 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3807 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE);
3808 }
3809
3810 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3811 assert(VM_Version::supports_avx(), "");
3812 if (VM_Version::supports_evex()) {
3813 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3814 } else {
3815 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3816 }
3817 }
3818
3819 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3820 assert(VM_Version::supports_avx(), "");
3821 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector_len);
3822 }
3823
3824 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3825 assert(VM_Version::supports_avx(), "");
3826 if (VM_Version::supports_evex()) {
3827 tuple_type = EVEX_FV;
3828 input_size_in_bits = EVEX_64bit;
3829 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3830 } else {
3831 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3832 }
3833 }
3834
3835 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3836 assert(VM_Version::supports_avx(), "");
3837 if (VM_Version::supports_evex()) {
3838 tuple_type = EVEX_FV;
3839 input_size_in_bits = EVEX_32bit;
3840 }
3841 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector_len);
3842 }
3843
3844 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
3845 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3846 if (VM_Version::supports_evex()) {
3847 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_66);
3848 } else {
3849 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66);
3850 }
3851 }
3852
3853 void Assembler::subps(XMMRegister dst, XMMRegister src) {
3854 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3855 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE);
3856 }
3857
3858 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3859 assert(VM_Version::supports_avx(), "");
3860 if (VM_Version::supports_evex()) {
3861 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3862 } else {
3863 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3864 }
3865 }
3866
3867 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3868 assert(VM_Version::supports_avx(), "");
3869 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector_len);
3870 }
3871
3872 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3873 assert(VM_Version::supports_avx(), "");
3874 if (VM_Version::supports_evex()) {
3875 tuple_type = EVEX_FV;
3876 input_size_in_bits = EVEX_64bit;
3877 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3878 } else {
3879 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3880 }
3881 }
3882
3883 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3884 assert(VM_Version::supports_avx(), "");
3885 if (VM_Version::supports_evex()) {
3886 tuple_type = EVEX_FV;
3887 input_size_in_bits = EVEX_32bit;
3888 }
3889 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector_len);
3890 }
3891
3892 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
3893 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3894 if (VM_Version::supports_evex()) {
3895 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_66);
3896 } else {
3897 emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
3898 }
3899 }
3900
3901 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
3902 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3903 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE);
3904 }
3905
3906 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3907 assert(VM_Version::supports_avx(), "");
3908 if (VM_Version::supports_evex()) {
3909 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
3910 } else {
3911 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
3912 }
3913 }
3914
3915 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3916 assert(VM_Version::supports_avx(), "");
3917 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector_len);
3918 }
3919
3920 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3921 assert(VM_Version::supports_avx(), "");
3922 if (VM_Version::supports_evex()) {
3923 tuple_type = EVEX_FV;
3924 input_size_in_bits = EVEX_64bit;
3925 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
3926 } else {
3927 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
3928 }
3929 }
3930
3931 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3932 assert(VM_Version::supports_avx(), "");
3933 if (VM_Version::supports_evex()) {
3934 tuple_type = EVEX_FV;
3935 input_size_in_bits = EVEX_32bit;
3936 }
3937 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector_len);
3938 }
3939
3940 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
3941 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3942 if (VM_Version::supports_evex()) {
3943 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_66);
3944 } else {
3945 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66);
3946 }
3947 }
3948
3949 void Assembler::divps(XMMRegister dst, XMMRegister src) {
3950 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3951 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE);
3952 }
3953
3954 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3955 assert(VM_Version::supports_avx(), "");
3956 if (VM_Version::supports_evex()) {
3957 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
3958 } else {
3959 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
3960 }
3961 }
3962
3963 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3964 assert(VM_Version::supports_avx(), "");
3965 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector_len);
3966 }
3967
3968 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3969 assert(VM_Version::supports_avx(), "");
3970 if (VM_Version::supports_evex()) {
3971 tuple_type = EVEX_FV;
3972 input_size_in_bits = EVEX_64bit;
3973 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
3974 } else {
3975 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
3976 }
3977 }
3978
3979 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3980 assert(VM_Version::supports_avx(), "");
3981 if (VM_Version::supports_evex()) {
3982 tuple_type = EVEX_FV;
3983 input_size_in_bits = EVEX_32bit;
3984 }
3985 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector_len);
3986 }
3987
3988 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
3989 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3990 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
3991 emit_simd_arith_q(0x54, dst, src, VEX_SIMD_66);
3992 } else {
3993 emit_simd_arith(0x54, dst, src, VEX_SIMD_66, false, true);
3994 }
3995 }
3996
3997 void Assembler::andps(XMMRegister dst, XMMRegister src) {
3998 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3999 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE, false,
4000 (VM_Version::supports_avx512dq() == false));
4001 }
4002
4003 void Assembler::andps(XMMRegister dst, Address src) {
4004 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4005 if (VM_Version::supports_evex()) {
4006 tuple_type = EVEX_FV;
4007 input_size_in_bits = EVEX_32bit;
4008 }
4009 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE,
4010 false, (VM_Version::supports_avx512dq() == false));
4011 }
4012
4013 void Assembler::andpd(XMMRegister dst, Address src) {
4014 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4015 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4016 tuple_type = EVEX_FV;
4017 input_size_in_bits = EVEX_64bit;
4018 emit_simd_arith_q(0x54, dst, src, VEX_SIMD_66);
4019 } else {
4020 emit_simd_arith(0x54, dst, src, VEX_SIMD_66, false, true);
4021 }
4022 }
4023
4024 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4025 assert(VM_Version::supports_avx(), "");
4026 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4027 emit_vex_arith_q(0x54, dst, nds, src, VEX_SIMD_66, vector_len);
4028 } else {
4029 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector_len, true);
4030 }
4031 }
4032
4033 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4034 assert(VM_Version::supports_avx(), "");
4035 bool legacy_mode = (VM_Version::supports_avx512dq() == false);
4036 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector_len, legacy_mode);
4037 }
4038
4039 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4040 assert(VM_Version::supports_avx(), "");
4041 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4042 tuple_type = EVEX_FV;
4043 input_size_in_bits = EVEX_64bit;
4044 emit_vex_arith_q(0x54, dst, nds, src, VEX_SIMD_66, vector_len);
4045 } else {
4046 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector_len, true);
4047 }
4048 }
4049
4050 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4051 assert(VM_Version::supports_avx(), "");
4052 if (VM_Version::supports_evex()) {
4053 tuple_type = EVEX_FV;
4054 input_size_in_bits = EVEX_32bit;
4055 }
4056 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector_len,
4057 (VM_Version::supports_avx512dq() == false));
4058 }
4059
4060 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
4061 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4062 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4063 emit_simd_arith_q(0x57, dst, src, VEX_SIMD_66);
4064 } else {
4065 emit_simd_arith(0x57, dst, src, VEX_SIMD_66, false, true);
4066 }
4067 }
4068
4069 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
4070 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4071 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE,
4072 false, (VM_Version::supports_avx512dq() == false));
4073 }
4074
4075 void Assembler::xorpd(XMMRegister dst, Address src) {
4076 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4077 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4078 tuple_type = EVEX_FV;
4079 input_size_in_bits = EVEX_64bit;
4080 emit_simd_arith_q(0x57, dst, src, VEX_SIMD_66);
4081 } else {
4082 emit_simd_arith(0x57, dst, src, VEX_SIMD_66, false, true);
4083 }
4084 }
4085
4086 void Assembler::xorps(XMMRegister dst, Address src) {
4087 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4088 if (VM_Version::supports_evex()) {
4089 tuple_type = EVEX_FV;
4090 input_size_in_bits = EVEX_32bit;
4091 }
4092 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE, false,
4093 (VM_Version::supports_avx512dq() == false));
4094 }
4095
4096 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4097 assert(VM_Version::supports_avx(), "");
4098 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4099 emit_vex_arith_q(0x57, dst, nds, src, VEX_SIMD_66, vector_len);
4100 } else {
4101 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector_len, true);
4102 }
4103 }
4104
4105 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4106 assert(VM_Version::supports_avx(), "");
4107 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector_len,
4108 (VM_Version::supports_avx512dq() == false));
4109 }
4110
4111 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4112 assert(VM_Version::supports_avx(), "");
4113 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4114 tuple_type = EVEX_FV;
4115 input_size_in_bits = EVEX_64bit;
4116 emit_vex_arith_q(0x57, dst, nds, src, VEX_SIMD_66, vector_len);
4117 } else {
4118 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector_len, true);
4119 }
4120 }
4121
4122 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4123 assert(VM_Version::supports_avx(), "");
4124 if (VM_Version::supports_evex()) {
4125 tuple_type = EVEX_FV;
4126 input_size_in_bits = EVEX_32bit;
4127 }
4128 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector_len,
4129 (VM_Version::supports_avx512dq() == false));
4130 }
4131
4132 // Integer vector arithmetic
4133 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4134 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4135 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4136 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len,
4137 VEX_OPCODE_0F_38, true, false);
4138 emit_int8(0x01);
4139 emit_int8((unsigned char)(0xC0 | encode));
4140 }
4141
4142 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4143 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4144 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4145 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len,
4146 VEX_OPCODE_0F_38, true, false);
4147 emit_int8(0x02);
4148 emit_int8((unsigned char)(0xC0 | encode));
4149 }
4150
4151 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
4152 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4153 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66);
4154 }
4155
4156 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
4157 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4158 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66);
4159 }
4160
4161 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
4162 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4163 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66);
4164 }
4165
4166 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
4167 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4168 if (VM_Version::supports_evex()) {
4169 emit_simd_arith_q(0xD4, dst, src, VEX_SIMD_66);
4170 } else {
4171 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66);
4172 }
4173 }
4174
4175 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
4176 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4177 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
4178 VEX_OPCODE_0F_38, false, AVX_128bit, true);
4179 emit_int8(0x01);
4180 emit_int8((unsigned char)(0xC0 | encode));
4181 }
4182
4183 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
4184 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4185 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
4186 VEX_OPCODE_0F_38, false, AVX_128bit, true);
4187 emit_int8(0x02);
4188 emit_int8((unsigned char)(0xC0 | encode));
4189 }
4190
4191 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4192 assert(UseAVX > 0, "requires some form of AVX");
4193 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector_len,
4194 (VM_Version::supports_avx512bw() == false));
4195 }
4196
4197 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4198 assert(UseAVX > 0, "requires some form of AVX");
4199 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector_len,
4200 (VM_Version::supports_avx512bw() == false));
4201 }
4202
4203 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4204 assert(UseAVX > 0, "requires some form of AVX");
4205 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector_len);
4206 }
4207
4208 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4209 assert(UseAVX > 0, "requires some form of AVX");
4210 if (VM_Version::supports_evex()) {
4211 emit_vex_arith_q(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4212 } else {
4213 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4214 }
4215 }
4216
4217 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4218 assert(UseAVX > 0, "requires some form of AVX");
4219 if (VM_Version::supports_evex()) {
4220 tuple_type = EVEX_FVM;
4221 }
4222 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector_len);
4223 }
4224
4225 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4226 assert(UseAVX > 0, "requires some form of AVX");
4227 if (VM_Version::supports_evex()) {
4228 tuple_type = EVEX_FVM;
4229 }
4230 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector_len);
4231 }
4232
4233 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4234 assert(UseAVX > 0, "requires some form of AVX");
4235 if (VM_Version::supports_evex()) {
4236 tuple_type = EVEX_FV;
4237 input_size_in_bits = EVEX_32bit;
4238 }
4239 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector_len);
4240 }
4241
4242 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4243 assert(UseAVX > 0, "requires some form of AVX");
4244 if (VM_Version::supports_evex()) {
4245 tuple_type = EVEX_FV;
4246 input_size_in_bits = EVEX_64bit;
4247 emit_vex_arith_q(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4248 } else {
4249 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4250 }
4251 }
4252
4253 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
4254 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4255 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66);
4256 }
4257
4258 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
4259 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4260 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66);
4261 }
4262
4263 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
4264 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4265 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66);
4266 }
4267
4268 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
4269 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4270 if (VM_Version::supports_evex()) {
4271 emit_simd_arith_q(0xFB, dst, src, VEX_SIMD_66);
4272 } else {
4273 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66);
4274 }
4275 }
4276
4277 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4278 assert(UseAVX > 0, "requires some form of AVX");
4279 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector_len,
4280 (VM_Version::supports_avx512bw() == false));
4281 }
4282
4283 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4284 assert(UseAVX > 0, "requires some form of AVX");
4285 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector_len,
4286 (VM_Version::supports_avx512bw() == false));
4287 }
4288
4289 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4290 assert(UseAVX > 0, "requires some form of AVX");
4291 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector_len);
4292 }
4293
4294 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4295 assert(UseAVX > 0, "requires some form of AVX");
4296 if (VM_Version::supports_evex()) {
4297 emit_vex_arith_q(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4298 } else {
4299 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4300 }
4301 }
4302
4303 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4304 assert(UseAVX > 0, "requires some form of AVX");
4305 if (VM_Version::supports_evex()) {
4306 tuple_type = EVEX_FVM;
4307 }
4308 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector_len,
4309 (VM_Version::supports_avx512bw() == false));
4310 }
4311
4312 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4313 assert(UseAVX > 0, "requires some form of AVX");
4314 if (VM_Version::supports_evex()) {
4315 tuple_type = EVEX_FVM;
4316 }
4317 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector_len,
4318 (VM_Version::supports_avx512bw() == false));
4319 }
4320
4321 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4322 assert(UseAVX > 0, "requires some form of AVX");
4323 if (VM_Version::supports_evex()) {
4324 tuple_type = EVEX_FV;
4325 input_size_in_bits = EVEX_32bit;
4326 }
4327 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector_len);
4328 }
4329
4330 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4331 assert(UseAVX > 0, "requires some form of AVX");
4332 if (VM_Version::supports_evex()) {
4333 tuple_type = EVEX_FV;
4334 input_size_in_bits = EVEX_64bit;
4335 emit_vex_arith_q(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4336 } else {
4337 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4338 }
4339 }
4340
4341 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
4342 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4343 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66,
4344 (VM_Version::supports_avx512bw() == false));
4345 }
4346
4347 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
4348 assert(VM_Version::supports_sse4_1(), "");
4349 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66,
4350 false, VEX_OPCODE_0F_38);
4351 emit_int8(0x40);
4352 emit_int8((unsigned char)(0xC0 | encode));
4353 }
4354
4355 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4356 assert(UseAVX > 0, "requires some form of AVX");
4357 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector_len,
4358 (VM_Version::supports_avx512bw() == false));
4359 }
4360
4361 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4362 assert(UseAVX > 0, "requires some form of AVX");
4363 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66,
4364 vector_len, VEX_OPCODE_0F_38);
4365 emit_int8(0x40);
4366 emit_int8((unsigned char)(0xC0 | encode));
4367 }
4368
4369 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4370 assert(UseAVX > 2, "requires some form of AVX");
4371 int src_enc = src->encoding();
4372 int dst_enc = dst->encoding();
4373 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4374 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66,
4375 VEX_OPCODE_0F_38, true, vector_len, false, false);
4376 emit_int8(0x40);
4377 emit_int8((unsigned char)(0xC0 | encode));
4378 }
4379
4380 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4381 assert(UseAVX > 0, "requires some form of AVX");
4382 if (VM_Version::supports_evex()) {
4383 tuple_type = EVEX_FVM;
4384 }
4385 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector_len);
4386 }
4387
4388 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4389 assert(UseAVX > 0, "requires some form of AVX");
4390 if (VM_Version::supports_evex()) {
4391 tuple_type = EVEX_FV;
4392 input_size_in_bits = EVEX_32bit;
4393 }
4394 InstructionMark im(this);
4395 int dst_enc = dst->encoding();
4396 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4397 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66,
4398 VEX_OPCODE_0F_38, false, vector_len);
4399 emit_int8(0x40);
4400 emit_operand(dst, src);
4401 }
4402
4403 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4404 assert(UseAVX > 0, "requires some form of AVX");
4405 if (VM_Version::supports_evex()) {
4406 tuple_type = EVEX_FV;
4407 input_size_in_bits = EVEX_64bit;
4408 }
4409 InstructionMark im(this);
4410 int dst_enc = dst->encoding();
4411 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4412 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, true, vector_len);
4413 emit_int8(0x40);
4414 emit_operand(dst, src);
4415 }
4416
4417 // Shift packed integers left by specified number of bits.
4418 void Assembler::psllw(XMMRegister dst, int shift) {
4419 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4420 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
4421 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F,
4422 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
4423 emit_int8(0x71);
4424 emit_int8((unsigned char)(0xC0 | encode));
4425 emit_int8(shift & 0xFF);
4426 }
4427
4428 void Assembler::pslld(XMMRegister dst, int shift) {
4429 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4430 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
4431 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, false);
4432 emit_int8(0x72);
4433 emit_int8((unsigned char)(0xC0 | encode));
4434 emit_int8(shift & 0xFF);
4435 }
4436
4437 void Assembler::psllq(XMMRegister dst, int shift) {
4438 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4439 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
4440 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F, true);
4441 emit_int8(0x73);
4442 emit_int8((unsigned char)(0xC0 | encode));
4443 emit_int8(shift & 0xFF);
4444 }
4445
4446 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
4447 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4448 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66, false,
4449 (VM_Version::supports_avx512bw() == false));
4450 }
4451
4452 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
4453 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4454 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66);
4455 }
4456
4457 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
4458 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4459 if (VM_Version::supports_evex()) {
4460 emit_simd_arith_q(0xF3, dst, shift, VEX_SIMD_66);
4461 } else {
4462 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66);
4463 }
4464 }
4465
4466 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4467 assert(UseAVX > 0, "requires some form of AVX");
4468 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
4469 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector_len,
4470 (VM_Version::supports_avx512bw() == false));
4471 emit_int8(shift & 0xFF);
4472 }
4473
4474 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4475 assert(UseAVX > 0, "requires some form of AVX");
4476 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
4477 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector_len);
4478 emit_int8(shift & 0xFF);
4479 }
4480
4481 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4482 assert(UseAVX > 0, "requires some form of AVX");
4483 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
4484 if (VM_Version::supports_evex()) {
4485 emit_vex_arith_q(0x73, xmm6, dst, src, VEX_SIMD_66, vector_len);
4486 } else {
4487 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector_len);
4488 }
4489 emit_int8(shift & 0xFF);
4490 }
4491
4492 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4493 assert(UseAVX > 0, "requires some form of AVX");
4494 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector_len,
4495 (VM_Version::supports_avx512bw() == false));
4496 }
4497
4498 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4499 assert(UseAVX > 0, "requires some form of AVX");
4500 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector_len);
4501 }
4502
4503 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4504 assert(UseAVX > 0, "requires some form of AVX");
4505 if (VM_Version::supports_evex()) {
4506 emit_vex_arith_q(0xF3, dst, src, shift, VEX_SIMD_66, vector_len);
4507 } else {
4508 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector_len);
4509 }
4510 }
4511
4512 // Shift packed integers logically right by specified number of bits.
4513 void Assembler::psrlw(XMMRegister dst, int shift) {
4514 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4515 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
4516 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F,
4517 (VM_Version::supports_avx512bw() == false));
4518 emit_int8(0x71);
4519 emit_int8((unsigned char)(0xC0 | encode));
4520 emit_int8(shift & 0xFF);
4521 }
4522
4523 void Assembler::psrld(XMMRegister dst, int shift) {
4524 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4525 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
4526 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, false);
4527 emit_int8(0x72);
4528 emit_int8((unsigned char)(0xC0 | encode));
4529 emit_int8(shift & 0xFF);
4530 }
4531
4532 void Assembler::psrlq(XMMRegister dst, int shift) {
4533 // Do not confuse it with psrldq SSE2 instruction which
4534 // shifts 128 bit value in xmm register by number of bytes.
4535 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4536 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4537 int encode = 0;
4538 if (VM_Version::supports_evex() && VM_Version::supports_avx512bw()) {
4539 encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, true, VEX_OPCODE_0F, false);
4540 } else {
4541 encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F, true);
4542 }
4543 emit_int8(0x73);
4544 emit_int8((unsigned char)(0xC0 | encode));
4545 emit_int8(shift & 0xFF);
4546 }
4547
4548 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
4549 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4550 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66, false,
4551 (VM_Version::supports_avx512bw() == false));
4552 }
4553
4554 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
4555 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4556 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66);
4557 }
4558
4559 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
4560 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4561 if (VM_Version::supports_evex()) {
4562 emit_simd_arith_q(0xD3, dst, shift, VEX_SIMD_66);
4563 } else {
4564 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66);
4565 }
4566 }
4567
4568 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4569 assert(UseAVX > 0, "requires some form of AVX");
4570 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4571 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector_len,
4572 (VM_Version::supports_avx512bw() == false));
4573 emit_int8(shift & 0xFF);
4574 }
4575
4576 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4577 assert(UseAVX > 0, "requires some form of AVX");
4578 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4579 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector_len);
4580 emit_int8(shift & 0xFF);
4581 }
4582
4583 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4584 assert(UseAVX > 0, "requires some form of AVX");
4585 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4586 if (VM_Version::supports_evex()) {
4587 emit_vex_arith_q(0x73, xmm2, dst, src, VEX_SIMD_66, vector_len);
4588 } else {
4589 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector_len);
4590 }
4591 emit_int8(shift & 0xFF);
4592 }
4593
4594 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4595 assert(UseAVX > 0, "requires some form of AVX");
4596 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector_len,
4597 (VM_Version::supports_avx512bw() == false));
4598 }
4599
4600 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4601 assert(UseAVX > 0, "requires some form of AVX");
4602 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector_len);
4603 }
4604
4605 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4606 assert(UseAVX > 0, "requires some form of AVX");
4607 if (VM_Version::supports_evex()) {
4608 emit_vex_arith_q(0xD3, dst, src, shift, VEX_SIMD_66, vector_len);
4609 } else {
4610 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector_len);
4611 }
4612 }
4613
4614 // Shift packed integers arithmetically right by specified number of bits.
4615 void Assembler::psraw(XMMRegister dst, int shift) {
4616 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4617 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4618 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F,
4619 (VM_Version::supports_avx512bw() == false));
4620 emit_int8(0x71);
4621 emit_int8((unsigned char)(0xC0 | encode));
4622 emit_int8(shift & 0xFF);
4623 }
4624
4625 void Assembler::psrad(XMMRegister dst, int shift) {
4626 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4627 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
4628 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, false);
4629 emit_int8(0x72);
4630 emit_int8((unsigned char)(0xC0 | encode));
4631 emit_int8(shift & 0xFF);
4632 }
4633
4634 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
4635 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4636 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66,
4637 (VM_Version::supports_avx512bw() == false));
4638 }
4639
4640 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
4641 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4642 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66);
4643 }
4644
4645 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4646 assert(UseAVX > 0, "requires some form of AVX");
4647 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4648 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector_len,
4649 (VM_Version::supports_avx512bw() == false));
4650 emit_int8(shift & 0xFF);
4651 }
4652
4653 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4654 assert(UseAVX > 0, "requires some form of AVX");
4655 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4656 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector_len);
4657 emit_int8(shift & 0xFF);
4658 }
4659
4660 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4661 assert(UseAVX > 0, "requires some form of AVX");
4662 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector_len,
4663 (VM_Version::supports_avx512bw() == false));
4664 }
4665
4666 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4667 assert(UseAVX > 0, "requires some form of AVX");
4668 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector_len);
4669 }
4670
4671
4672 // AND packed integers
4673 void Assembler::pand(XMMRegister dst, XMMRegister src) {
4674 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4675 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66);
4676 }
4677
4678 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4679 assert(UseAVX > 0, "requires some form of AVX");
4680 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector_len);
4681 }
4682
4683 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4684 assert(UseAVX > 0, "requires some form of AVX");
4685 if (VM_Version::supports_evex()) {
4686 tuple_type = EVEX_FV;
4687 input_size_in_bits = EVEX_32bit;
4688 }
4689 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector_len);
4690 }
4691
4692 void Assembler::por(XMMRegister dst, XMMRegister src) {
4693 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4694 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66);
4695 }
4696
4697 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4698 assert(UseAVX > 0, "requires some form of AVX");
4699 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector_len);
4700 }
4701
4702 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4703 assert(UseAVX > 0, "requires some form of AVX");
4704 if (VM_Version::supports_evex()) {
4705 tuple_type = EVEX_FV;
4706 input_size_in_bits = EVEX_32bit;
4707 }
4708 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector_len);
4709 }
4710
4711 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
4712 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4713 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66);
4714 }
4715
4716 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4717 assert(UseAVX > 0, "requires some form of AVX");
4718 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector_len);
4719 }
4720
4721 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4722 assert(UseAVX > 0, "requires some form of AVX");
4723 if (VM_Version::supports_evex()) {
4724 tuple_type = EVEX_FV;
4725 input_size_in_bits = EVEX_32bit;
4726 }
4727 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector_len);
4728 }
4729
4730
4731 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4732 assert(VM_Version::supports_avx(), "");
4733 int vector_len = AVX_256bit;
4734 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4735 emit_int8(0x18);
4736 emit_int8((unsigned char)(0xC0 | encode));
4737 // 0x00 - insert into lower 128 bits
4738 // 0x01 - insert into upper 128 bits
4739 emit_int8(0x01);
4740 }
4741
4742 void Assembler::vinsertf64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4743 assert(VM_Version::supports_evex(), "");
4744 int vector_len = AVX_512bit;
4745 int src_enc = src->encoding();
4746 int dst_enc = dst->encoding();
4747 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4748 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66,
4749 VEX_OPCODE_0F_3A, true, vector_len, false, false);
4750 emit_int8(0x1A);
4751 emit_int8((unsigned char)(0xC0 | encode));
4752 // 0x00 - insert into lower 256 bits
4753 // 0x01 - insert into upper 256 bits
4754 emit_int8(0x01);
4755 }
4756
4757 void Assembler::vinsertf64x4h(XMMRegister dst, Address src) {
4758 assert(VM_Version::supports_avx(), "");
4759 if (VM_Version::supports_evex()) {
4760 tuple_type = EVEX_T4;
4761 input_size_in_bits = EVEX_64bit;
4762 }
4763 InstructionMark im(this);
4764 int vector_len = AVX_512bit;
4765 assert(dst != xnoreg, "sanity");
4766 int dst_enc = dst->encoding();
4767 // swap src<->dst for encoding
4768 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, true, vector_len);
4769 emit_int8(0x1A);
4770 emit_operand(dst, src);
4771 // 0x01 - insert into upper 128 bits
4772 emit_int8(0x01);
4773 }
4774
4775 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
4776 assert(VM_Version::supports_avx(), "");
4777 if (VM_Version::supports_evex()) {
4778 tuple_type = EVEX_T4;
4779 input_size_in_bits = EVEX_32bit;
4780 }
4781 InstructionMark im(this);
4782 int vector_len = AVX_256bit;
4783 assert(dst != xnoreg, "sanity");
4784 int dst_enc = dst->encoding();
4785 // swap src<->dst for encoding
4786 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4787 emit_int8(0x18);
4788 emit_operand(dst, src);
4789 // 0x01 - insert into upper 128 bits
4790 emit_int8(0x01);
4791 }
4792
4793 void Assembler::vextractf128h(XMMRegister dst, XMMRegister src) {
4794 assert(VM_Version::supports_avx(), "");
4795 int vector_len = AVX_256bit;
4796 int encode = vex_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4797 emit_int8(0x19);
4798 emit_int8((unsigned char)(0xC0 | encode));
4799 // 0x00 - insert into lower 128 bits
4800 // 0x01 - insert into upper 128 bits
4801 emit_int8(0x01);
4802 }
4803
4804 void Assembler::vextractf128h(Address dst, XMMRegister src) {
4805 assert(VM_Version::supports_avx(), "");
4806 if (VM_Version::supports_evex()) {
4807 tuple_type = EVEX_T4;
4808 input_size_in_bits = EVEX_32bit;
4809 }
4810 InstructionMark im(this);
4811 int vector_len = AVX_256bit;
4812 assert(src != xnoreg, "sanity");
4813 int src_enc = src->encoding();
4814 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4815 emit_int8(0x19);
4816 emit_operand(src, dst);
4817 // 0x01 - extract from upper 128 bits
4818 emit_int8(0x01);
4819 }
4820
4821 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4822 assert(VM_Version::supports_avx2(), "");
4823 int vector_len = AVX_256bit;
4824 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4825 emit_int8(0x38);
4826 emit_int8((unsigned char)(0xC0 | encode));
4827 // 0x00 - insert into lower 128 bits
4828 // 0x01 - insert into upper 128 bits
4829 emit_int8(0x01);
4830 }
4831
4832 void Assembler::vinserti64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4833 assert(VM_Version::supports_evex(), "");
4834 int vector_len = AVX_512bit;
4835 int src_enc = src->encoding();
4836 int dst_enc = dst->encoding();
4837 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4838 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4839 VM_Version::supports_avx512dq(), vector_len, false, false);
4840 emit_int8(0x38);
4841 emit_int8((unsigned char)(0xC0 | encode));
4842 // 0x00 - insert into lower 256 bits
4843 // 0x01 - insert into upper 256 bits
4844 emit_int8(0x01);
4845 }
4846
4847 void Assembler::vinserti128h(XMMRegister dst, Address src) {
4848 assert(VM_Version::supports_avx2(), "");
4849 if (VM_Version::supports_evex()) {
4850 tuple_type = EVEX_T4;
4851 input_size_in_bits = EVEX_32bit;
4852 }
4853 InstructionMark im(this);
4854 int vector_len = AVX_256bit;
4855 assert(dst != xnoreg, "sanity");
4856 int dst_enc = dst->encoding();
4857 // swap src<->dst for encoding
4858 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4859 emit_int8(0x38);
4860 emit_operand(dst, src);
4861 // 0x01 - insert into upper 128 bits
4862 emit_int8(0x01);
4863 }
4864
4865 void Assembler::vextracti128h(XMMRegister dst, XMMRegister src) {
4866 assert(VM_Version::supports_avx(), "");
4867 int vector_len = AVX_256bit;
4868 int encode = vex_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4869 emit_int8(0x39);
4870 emit_int8((unsigned char)(0xC0 | encode));
4871 // 0x00 - insert into lower 128 bits
4872 // 0x01 - insert into upper 128 bits
4873 emit_int8(0x01);
4874 }
4875
4876 void Assembler::vextracti128h(Address dst, XMMRegister src) {
4877 assert(VM_Version::supports_avx2(), "");
4878 if (VM_Version::supports_evex()) {
4879 tuple_type = EVEX_T4;
4880 input_size_in_bits = EVEX_32bit;
4881 }
4882 InstructionMark im(this);
4883 int vector_len = AVX_256bit;
4884 assert(src != xnoreg, "sanity");
4885 int src_enc = src->encoding();
4886 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4887 emit_int8(0x39);
4888 emit_operand(src, dst);
4889 // 0x01 - extract from upper 128 bits
4890 emit_int8(0x01);
4891 }
4892
4893 void Assembler::vextracti64x4h(XMMRegister dst, XMMRegister src) {
4894 assert(VM_Version::supports_evex(), "");
4895 int vector_len = AVX_512bit;
4896 int src_enc = src->encoding();
4897 int dst_enc = dst->encoding();
4898 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4899 true, vector_len, false, false);
4900 emit_int8(0x3B);
4901 emit_int8((unsigned char)(0xC0 | encode));
4902 // 0x01 - extract from upper 256 bits
4903 emit_int8(0x01);
4904 }
4905
4906 void Assembler::vextracti64x2h(XMMRegister dst, XMMRegister src, int value) {
4907 assert(VM_Version::supports_evex(), "");
4908 int vector_len = AVX_512bit;
4909 int src_enc = src->encoding();
4910 int dst_enc = dst->encoding();
4911 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4912 VM_Version::supports_avx512dq(), vector_len, false, false);
4913 emit_int8(0x39);
4914 emit_int8((unsigned char)(0xC0 | encode));
4915 // 0x01 - extract from bits 255:128
4916 // 0x02 - extract from bits 383:256
4917 // 0x03 - extract from bits 511:384
4918 emit_int8(value & 0x3);
4919 }
4920
4921 void Assembler::vextractf64x4h(XMMRegister dst, XMMRegister src) {
4922 assert(VM_Version::supports_evex(), "");
4923 int vector_len = AVX_512bit;
4924 int src_enc = src->encoding();
4925 int dst_enc = dst->encoding();
4926 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4927 VM_Version::supports_avx512dq(), vector_len, false, false);
4928 emit_int8(0x1B);
4929 emit_int8((unsigned char)(0xC0 | encode));
4930 // 0x01 - extract from upper 256 bits
4931 emit_int8(0x01);
4932 }
4933
4934 void Assembler::vextractf64x4h(Address dst, XMMRegister src) {
4935 assert(VM_Version::supports_avx2(), "");
4936 tuple_type = EVEX_T4;
4937 input_size_in_bits = EVEX_64bit;
4938 InstructionMark im(this);
4939 int vector_len = AVX_512bit;
4940 assert(src != xnoreg, "sanity");
4941 int src_enc = src->encoding();
4942 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4943 VM_Version::supports_avx512dq(), vector_len);
4944 emit_int8(0x1B);
4945 emit_operand(src, dst);
4946 // 0x01 - extract from upper 128 bits
4947 emit_int8(0x01);
4948 }
4949
4950 void Assembler::vextractf32x4h(XMMRegister dst, XMMRegister src, int value) {
4951 assert(VM_Version::supports_evex(), "");
4952 int vector_len = AVX_512bit;
4953 int src_enc = src->encoding();
4954 int dst_enc = dst->encoding();
4955 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66,
4956 VEX_OPCODE_0F_3A, false, vector_len, false, false);
4957 emit_int8(0x19);
4958 emit_int8((unsigned char)(0xC0 | encode));
4959 // 0x01 - extract from bits 255:128
4960 // 0x02 - extract from bits 383:256
4961 // 0x03 - extract from bits 511:384
4962 emit_int8(value & 0x3);
4963 }
4964
4965 void Assembler::vextractf64x2h(XMMRegister dst, XMMRegister src, int value) {
4966 assert(VM_Version::supports_evex(), "");
4967 int vector_len = AVX_512bit;
4968 int src_enc = src->encoding();
4969 int dst_enc = dst->encoding();
4970 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4971 VM_Version::supports_avx512dq(), vector_len, false, false);
4972 emit_int8(0x19);
4973 emit_int8((unsigned char)(0xC0 | encode));
4974 // 0x01 - extract from bits 255:128
4975 // 0x02 - extract from bits 383:256
4976 // 0x03 - extract from bits 511:384
4977 emit_int8(value & 0x3);
4978 }
4979
4980 // duplicate 4-bytes integer data from src into 8 locations in dest
4981 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
4982 assert(VM_Version::supports_avx2(), "");
4983 int vector_len = AVX_256bit;
4984 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
4985 vector_len, VEX_OPCODE_0F_38, false);
4986 emit_int8(0x58);
4987 emit_int8((unsigned char)(0xC0 | encode));
4988 }
4989
4990 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
4991 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
4992 assert(VM_Version::supports_evex(), "");
4993 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
4994 vector_len, VEX_OPCODE_0F_38, false);
4995 emit_int8(0x78);
4996 emit_int8((unsigned char)(0xC0 | encode));
4997 }
4998
4999 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
5000 assert(VM_Version::supports_evex(), "");
5001 tuple_type = EVEX_T1S;
5002 input_size_in_bits = EVEX_8bit;
5003 InstructionMark im(this);
5004 assert(dst != xnoreg, "sanity");
5005 int dst_enc = dst->encoding();
5006 // swap src<->dst for encoding
5007 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector_len);
5008 emit_int8(0x78);
5009 emit_operand(dst, src);
5010 }
5011
5012 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
5013 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
5014 assert(VM_Version::supports_evex(), "");
5015 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
5016 vector_len, VEX_OPCODE_0F_38, false);
5017 emit_int8(0x79);
5018 emit_int8((unsigned char)(0xC0 | encode));
5019 }
5020
5021 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
5022 assert(VM_Version::supports_evex(), "");
5023 tuple_type = EVEX_T1S;
5024 input_size_in_bits = EVEX_16bit;
5025 InstructionMark im(this);
5026 assert(dst != xnoreg, "sanity");
5027 int dst_enc = dst->encoding();
5028 // swap src<->dst for encoding
5029 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector_len);
5030 emit_int8(0x79);
5031 emit_operand(dst, src);
5032 }
5033
5034 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5035 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
5036 assert(VM_Version::supports_evex(), "");
5037 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
5038 vector_len, VEX_OPCODE_0F_38, false);
5039 emit_int8(0x58);
5040 emit_int8((unsigned char)(0xC0 | encode));
5041 }
5042
5043 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
5044 assert(VM_Version::supports_evex(), "");
5045 tuple_type = EVEX_T1S;
5046 input_size_in_bits = EVEX_32bit;
5047 InstructionMark im(this);
5048 assert(dst != xnoreg, "sanity");
5049 int dst_enc = dst->encoding();
5050 // swap src<->dst for encoding
5051 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector_len);
5052 emit_int8(0x58);
5053 emit_operand(dst, src);
5054 }
5055
5056 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5057 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
5058 assert(VM_Version::supports_evex(), "");
5059 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5060 VEX_OPCODE_0F_38, true, vector_len, false, false);
5061 emit_int8(0x59);
5062 emit_int8((unsigned char)(0xC0 | encode));
5063 }
5064
5065 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
5066 assert(VM_Version::supports_evex(), "");
5067 tuple_type = EVEX_T1S;
5068 input_size_in_bits = EVEX_64bit;
5069 InstructionMark im(this);
5070 assert(dst != xnoreg, "sanity");
5071 int dst_enc = dst->encoding();
5072 // swap src<->dst for encoding
5073 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, true, vector_len);
5074 emit_int8(0x59);
5075 emit_operand(dst, src);
5076 }
5077
5078 // duplicate single precision fp from src into 4|8|16 locations in dest : requires AVX512VL
5079 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
5080 assert(VM_Version::supports_evex(), "");
5081 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5082 VEX_OPCODE_0F_38, false, vector_len, false, false);
5083 emit_int8(0x18);
5084 emit_int8((unsigned char)(0xC0 | encode));
5085 }
5086
5087 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
5088 assert(VM_Version::supports_evex(), "");
5089 tuple_type = EVEX_T1S;
5090 input_size_in_bits = EVEX_32bit;
5091 InstructionMark im(this);
5092 assert(dst != xnoreg, "sanity");
5093 int dst_enc = dst->encoding();
5094 // swap src<->dst for encoding
5095 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector_len);
5096 emit_int8(0x18);
5097 emit_operand(dst, src);
5098 }
5099
5100 // duplicate double precision fp from src into 2|4|8 locations in dest : requires AVX512VL
5101 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
5102 assert(VM_Version::supports_evex(), "");
5103 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5104 VEX_OPCODE_0F_38, true, vector_len, false, false);
5105 emit_int8(0x19);
5106 emit_int8((unsigned char)(0xC0 | encode));
5107 }
5108
5109 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
5110 assert(VM_Version::supports_evex(), "");
5111 tuple_type = EVEX_T1S;
5112 input_size_in_bits = EVEX_64bit;
5113 InstructionMark im(this);
5114 assert(dst != xnoreg, "sanity");
5115 int dst_enc = dst->encoding();
5116 // swap src<->dst for encoding
5117 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, true, vector_len);
5118 emit_int8(0x19);
5119 emit_operand(dst, src);
5120 }
5121
5122 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
5123 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
5124 assert(VM_Version::supports_evex(), "");
5125 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5126 VEX_OPCODE_0F_38, false, vector_len, false, false);
5127 emit_int8(0x7A);
5128 emit_int8((unsigned char)(0xC0 | encode));
5129 }
5130
5131 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
5132 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
5133 assert(VM_Version::supports_evex(), "");
5134 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5135 VEX_OPCODE_0F_38, false, vector_len, false, false);
5136 emit_int8(0x7B);
5137 emit_int8((unsigned char)(0xC0 | encode));
5138 }
5139
5140 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5141 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
5142 assert(VM_Version::supports_evex(), "");
5143 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5144 VEX_OPCODE_0F_38, false, vector_len, false, false);
5145 emit_int8(0x7C);
5146 emit_int8((unsigned char)(0xC0 | encode));
5147 }
5148
5149 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5150 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
5151 assert(VM_Version::supports_evex(), "");
5152 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5153 VEX_OPCODE_0F_38, true, vector_len, false, false);
5154 emit_int8(0x7C);
5155 emit_int8((unsigned char)(0xC0 | encode));
5156 }
5157
5158 // Carry-Less Multiplication Quadword
5159 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
5160 assert(VM_Version::supports_clmul(), "");
5161 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
5162 VEX_OPCODE_0F_3A, false, AVX_128bit, true);
5163 emit_int8(0x44);
5164 emit_int8((unsigned char)(0xC0 | encode));
5165 emit_int8((unsigned char)mask);
5166 }
5167
5168 // Carry-Less Multiplication Quadword
5169 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
5170 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
5171 int vector_len = AVX_128bit;
5172 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66,
5173 vector_len, VEX_OPCODE_0F_3A, true);
5174 emit_int8(0x44);
5175 emit_int8((unsigned char)(0xC0 | encode));
5176 emit_int8((unsigned char)mask);
5177 }
5178
5179 void Assembler::vzeroupper() {
5180 assert(VM_Version::supports_avx(), "");
5181 if (UseAVX < 3)
5182 {
5183 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
5184 emit_int8(0x77);
5185 }
5186 }
5187
5188
5189 #ifndef _LP64
5190 // 32bit only pieces of the assembler
5191
5192 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
5193 // NO PREFIX AS NEVER 64BIT
5194 InstructionMark im(this);
5195 emit_int8((unsigned char)0x81);
5196 emit_int8((unsigned char)(0xF8 | src1->encoding()));
5197 emit_data(imm32, rspec, 0);
5198 }
5199
5200 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
5201 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
5202 InstructionMark im(this);
5203 emit_int8((unsigned char)0x81);
5204 emit_operand(rdi, src1);
5205 emit_data(imm32, rspec, 0);
5206 }
5207
5208 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
5209 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
5210 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
5211 void Assembler::cmpxchg8(Address adr) {
5212 InstructionMark im(this);
5213 emit_int8(0x0F);
5214 emit_int8((unsigned char)0xC7);
5215 emit_operand(rcx, adr);
5216 }
5217
5218 void Assembler::decl(Register dst) {
5219 // Don't use it directly. Use MacroAssembler::decrementl() instead.
5220 emit_int8(0x48 | dst->encoding());
5221 }
5222
5223 #endif // _LP64
5224
5225 // 64bit typically doesn't use the x87 but needs to for the trig funcs
5226
5227 void Assembler::fabs() {
5228 emit_int8((unsigned char)0xD9);
5229 emit_int8((unsigned char)0xE1);
5230 }
5231
5232 void Assembler::fadd(int i) {
5233 emit_farith(0xD8, 0xC0, i);
5234 }
5235
5236 void Assembler::fadd_d(Address src) {
5237 InstructionMark im(this);
5238 emit_int8((unsigned char)0xDC);
5239 emit_operand32(rax, src);
5240 }
5241
5242 void Assembler::fadd_s(Address src) {
5243 InstructionMark im(this);
5244 emit_int8((unsigned char)0xD8);
5245 emit_operand32(rax, src);
5246 }
5247
5248 void Assembler::fadda(int i) {
5249 emit_farith(0xDC, 0xC0, i);
5250 }
5251
5252 void Assembler::faddp(int i) {
5253 emit_farith(0xDE, 0xC0, i);
5254 }
5255
5256 void Assembler::fchs() {
5257 emit_int8((unsigned char)0xD9);
5258 emit_int8((unsigned char)0xE0);
5259 }
5260
5261 void Assembler::fcom(int i) {
5262 emit_farith(0xD8, 0xD0, i);
5263 }
5264
5265 void Assembler::fcomp(int i) {
5266 emit_farith(0xD8, 0xD8, i);
5267 }
5268
5269 void Assembler::fcomp_d(Address src) {
5270 InstructionMark im(this);
5271 emit_int8((unsigned char)0xDC);
5272 emit_operand32(rbx, src);
5273 }
5274
5275 void Assembler::fcomp_s(Address src) {
5276 InstructionMark im(this);
5277 emit_int8((unsigned char)0xD8);
5278 emit_operand32(rbx, src);
5279 }
5280
5281 void Assembler::fcompp() {
5282 emit_int8((unsigned char)0xDE);
5283 emit_int8((unsigned char)0xD9);
5284 }
5285
5286 void Assembler::fcos() {
5287 emit_int8((unsigned char)0xD9);
5288 emit_int8((unsigned char)0xFF);
5289 }
5290
5291 void Assembler::fdecstp() {
5292 emit_int8((unsigned char)0xD9);
5293 emit_int8((unsigned char)0xF6);
5294 }
5295
5296 void Assembler::fdiv(int i) {
5297 emit_farith(0xD8, 0xF0, i);
5298 }
5299
5300 void Assembler::fdiv_d(Address src) {
5301 InstructionMark im(this);
5302 emit_int8((unsigned char)0xDC);
5303 emit_operand32(rsi, src);
5304 }
5305
5306 void Assembler::fdiv_s(Address src) {
5307 InstructionMark im(this);
5308 emit_int8((unsigned char)0xD8);
5309 emit_operand32(rsi, src);
5310 }
5311
5312 void Assembler::fdiva(int i) {
5313 emit_farith(0xDC, 0xF8, i);
5314 }
5315
5316 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
5317 // is erroneous for some of the floating-point instructions below.
5318
5319 void Assembler::fdivp(int i) {
5320 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
5321 }
5322
5323 void Assembler::fdivr(int i) {
5324 emit_farith(0xD8, 0xF8, i);
5325 }
5326
5327 void Assembler::fdivr_d(Address src) {
5328 InstructionMark im(this);
5329 emit_int8((unsigned char)0xDC);
5330 emit_operand32(rdi, src);
5331 }
5332
5333 void Assembler::fdivr_s(Address src) {
5334 InstructionMark im(this);
5335 emit_int8((unsigned char)0xD8);
5336 emit_operand32(rdi, src);
5337 }
5338
5339 void Assembler::fdivra(int i) {
5340 emit_farith(0xDC, 0xF0, i);
5341 }
5342
5343 void Assembler::fdivrp(int i) {
5344 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
5345 }
5346
5347 void Assembler::ffree(int i) {
5348 emit_farith(0xDD, 0xC0, i);
5349 }
5350
5351 void Assembler::fild_d(Address adr) {
5352 InstructionMark im(this);
5353 emit_int8((unsigned char)0xDF);
5354 emit_operand32(rbp, adr);
5355 }
5356
5357 void Assembler::fild_s(Address adr) {
5358 InstructionMark im(this);
5359 emit_int8((unsigned char)0xDB);
5360 emit_operand32(rax, adr);
5361 }
5362
5363 void Assembler::fincstp() {
5364 emit_int8((unsigned char)0xD9);
5365 emit_int8((unsigned char)0xF7);
5366 }
5367
5368 void Assembler::finit() {
5369 emit_int8((unsigned char)0x9B);
5370 emit_int8((unsigned char)0xDB);
5371 emit_int8((unsigned char)0xE3);
5372 }
5373
5374 void Assembler::fist_s(Address adr) {
5375 InstructionMark im(this);
5376 emit_int8((unsigned char)0xDB);
5377 emit_operand32(rdx, adr);
5378 }
5379
5380 void Assembler::fistp_d(Address adr) {
5381 InstructionMark im(this);
5382 emit_int8((unsigned char)0xDF);
5383 emit_operand32(rdi, adr);
5384 }
5385
5386 void Assembler::fistp_s(Address adr) {
5387 InstructionMark im(this);
5388 emit_int8((unsigned char)0xDB);
5389 emit_operand32(rbx, adr);
5390 }
5391
5392 void Assembler::fld1() {
5393 emit_int8((unsigned char)0xD9);
5394 emit_int8((unsigned char)0xE8);
5395 }
5396
5397 void Assembler::fld_d(Address adr) {
5398 InstructionMark im(this);
5399 emit_int8((unsigned char)0xDD);
5400 emit_operand32(rax, adr);
5401 }
5402
5403 void Assembler::fld_s(Address adr) {
5404 InstructionMark im(this);
5405 emit_int8((unsigned char)0xD9);
5406 emit_operand32(rax, adr);
5407 }
5408
5409
5410 void Assembler::fld_s(int index) {
5411 emit_farith(0xD9, 0xC0, index);
5412 }
5413
5414 void Assembler::fld_x(Address adr) {
5415 InstructionMark im(this);
5416 emit_int8((unsigned char)0xDB);
5417 emit_operand32(rbp, adr);
5418 }
5419
5420 void Assembler::fldcw(Address src) {
5421 InstructionMark im(this);
5422 emit_int8((unsigned char)0xD9);
5423 emit_operand32(rbp, src);
5424 }
5425
5426 void Assembler::fldenv(Address src) {
5427 InstructionMark im(this);
5428 emit_int8((unsigned char)0xD9);
5429 emit_operand32(rsp, src);
5430 }
5431
5432 void Assembler::fldlg2() {
5433 emit_int8((unsigned char)0xD9);
5434 emit_int8((unsigned char)0xEC);
5435 }
5436
5437 void Assembler::fldln2() {
5438 emit_int8((unsigned char)0xD9);
5439 emit_int8((unsigned char)0xED);
5440 }
5441
5442 void Assembler::fldz() {
5443 emit_int8((unsigned char)0xD9);
5444 emit_int8((unsigned char)0xEE);
5445 }
5446
5447 void Assembler::flog() {
5448 fldln2();
5449 fxch();
5450 fyl2x();
5451 }
5452
5453 void Assembler::flog10() {
5454 fldlg2();
5455 fxch();
5456 fyl2x();
5457 }
5458
5459 void Assembler::fmul(int i) {
5460 emit_farith(0xD8, 0xC8, i);
5461 }
5462
5463 void Assembler::fmul_d(Address src) {
5464 InstructionMark im(this);
5465 emit_int8((unsigned char)0xDC);
5466 emit_operand32(rcx, src);
5467 }
5468
5469 void Assembler::fmul_s(Address src) {
5470 InstructionMark im(this);
5471 emit_int8((unsigned char)0xD8);
5472 emit_operand32(rcx, src);
5473 }
5474
5475 void Assembler::fmula(int i) {
5476 emit_farith(0xDC, 0xC8, i);
5477 }
5478
5479 void Assembler::fmulp(int i) {
5480 emit_farith(0xDE, 0xC8, i);
5481 }
5482
5483 void Assembler::fnsave(Address dst) {
5484 InstructionMark im(this);
5485 emit_int8((unsigned char)0xDD);
5486 emit_operand32(rsi, dst);
5487 }
5488
5489 void Assembler::fnstcw(Address src) {
5490 InstructionMark im(this);
5491 emit_int8((unsigned char)0x9B);
5492 emit_int8((unsigned char)0xD9);
5493 emit_operand32(rdi, src);
5494 }
5495
5496 void Assembler::fnstsw_ax() {
5497 emit_int8((unsigned char)0xDF);
5498 emit_int8((unsigned char)0xE0);
5499 }
5500
5501 void Assembler::fprem() {
5502 emit_int8((unsigned char)0xD9);
5503 emit_int8((unsigned char)0xF8);
5504 }
5505
5506 void Assembler::fprem1() {
5507 emit_int8((unsigned char)0xD9);
5508 emit_int8((unsigned char)0xF5);
5509 }
5510
5511 void Assembler::frstor(Address src) {
5512 InstructionMark im(this);
5513 emit_int8((unsigned char)0xDD);
5514 emit_operand32(rsp, src);
5515 }
5516
5517 void Assembler::fsin() {
5518 emit_int8((unsigned char)0xD9);
5519 emit_int8((unsigned char)0xFE);
5520 }
5521
5522 void Assembler::fsqrt() {
5523 emit_int8((unsigned char)0xD9);
5524 emit_int8((unsigned char)0xFA);
5525 }
5526
5527 void Assembler::fst_d(Address adr) {
5528 InstructionMark im(this);
5529 emit_int8((unsigned char)0xDD);
5530 emit_operand32(rdx, adr);
5531 }
5532
5533 void Assembler::fst_s(Address adr) {
5534 InstructionMark im(this);
5535 emit_int8((unsigned char)0xD9);
5536 emit_operand32(rdx, adr);
5537 }
5538
5539 void Assembler::fstp_d(Address adr) {
5540 InstructionMark im(this);
5541 emit_int8((unsigned char)0xDD);
5542 emit_operand32(rbx, adr);
5543 }
5544
5545 void Assembler::fstp_d(int index) {
5546 emit_farith(0xDD, 0xD8, index);
5547 }
5548
5549 void Assembler::fstp_s(Address adr) {
5550 InstructionMark im(this);
5551 emit_int8((unsigned char)0xD9);
5552 emit_operand32(rbx, adr);
5553 }
5554
5555 void Assembler::fstp_x(Address adr) {
5556 InstructionMark im(this);
5557 emit_int8((unsigned char)0xDB);
5558 emit_operand32(rdi, adr);
5559 }
5560
5561 void Assembler::fsub(int i) {
5562 emit_farith(0xD8, 0xE0, i);
5563 }
5564
5565 void Assembler::fsub_d(Address src) {
5566 InstructionMark im(this);
5567 emit_int8((unsigned char)0xDC);
5568 emit_operand32(rsp, src);
5569 }
5570
5571 void Assembler::fsub_s(Address src) {
5572 InstructionMark im(this);
5573 emit_int8((unsigned char)0xD8);
5574 emit_operand32(rsp, src);
5575 }
5576
5577 void Assembler::fsuba(int i) {
5578 emit_farith(0xDC, 0xE8, i);
5579 }
5580
5581 void Assembler::fsubp(int i) {
5582 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
5583 }
5584
5585 void Assembler::fsubr(int i) {
5586 emit_farith(0xD8, 0xE8, i);
5587 }
5588
5589 void Assembler::fsubr_d(Address src) {
5590 InstructionMark im(this);
5591 emit_int8((unsigned char)0xDC);
5592 emit_operand32(rbp, src);
5593 }
5594
5595 void Assembler::fsubr_s(Address src) {
5596 InstructionMark im(this);
5597 emit_int8((unsigned char)0xD8);
5598 emit_operand32(rbp, src);
5599 }
5600
5601 void Assembler::fsubra(int i) {
5602 emit_farith(0xDC, 0xE0, i);
5603 }
5604
5605 void Assembler::fsubrp(int i) {
5606 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
5607 }
5608
5609 void Assembler::ftan() {
5610 emit_int8((unsigned char)0xD9);
5611 emit_int8((unsigned char)0xF2);
5612 emit_int8((unsigned char)0xDD);
5613 emit_int8((unsigned char)0xD8);
5614 }
5615
5616 void Assembler::ftst() {
5617 emit_int8((unsigned char)0xD9);
5618 emit_int8((unsigned char)0xE4);
5619 }
5620
5621 void Assembler::fucomi(int i) {
5622 // make sure the instruction is supported (introduced for P6, together with cmov)
5623 guarantee(VM_Version::supports_cmov(), "illegal instruction");
5624 emit_farith(0xDB, 0xE8, i);
5625 }
5626
5627 void Assembler::fucomip(int i) {
5628 // make sure the instruction is supported (introduced for P6, together with cmov)
5629 guarantee(VM_Version::supports_cmov(), "illegal instruction");
5630 emit_farith(0xDF, 0xE8, i);
5631 }
5632
5633 void Assembler::fwait() {
5634 emit_int8((unsigned char)0x9B);
5635 }
5636
5637 void Assembler::fxch(int i) {
5638 emit_farith(0xD9, 0xC8, i);
5639 }
5640
5641 void Assembler::fyl2x() {
5642 emit_int8((unsigned char)0xD9);
5643 emit_int8((unsigned char)0xF1);
5644 }
5645
5646 void Assembler::frndint() {
5647 emit_int8((unsigned char)0xD9);
5648 emit_int8((unsigned char)0xFC);
5649 }
5650
5651 void Assembler::f2xm1() {
5652 emit_int8((unsigned char)0xD9);
5653 emit_int8((unsigned char)0xF0);
5654 }
5655
5656 void Assembler::fldl2e() {
5657 emit_int8((unsigned char)0xD9);
5658 emit_int8((unsigned char)0xEA);
5659 }
5660
5661 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
5662 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
5663 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
5664 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
5665
5666 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
5667 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
5668 if (pre > 0) {
5669 emit_int8(simd_pre[pre]);
5670 }
5671 if (rex_w) {
5672 prefixq(adr, xreg);
5673 } else {
5674 prefix(adr, xreg);
5675 }
5676 if (opc > 0) {
5677 emit_int8(0x0F);
5678 int opc2 = simd_opc[opc];
5679 if (opc2 > 0) {
5680 emit_int8(opc2);
5681 }
5682 }
5683 }
5684
5685 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
5686 if (pre > 0) {
5687 emit_int8(simd_pre[pre]);
5688 }
5689 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) :
5690 prefix_and_encode(dst_enc, src_enc);
5691 if (opc > 0) {
5692 emit_int8(0x0F);
5693 int opc2 = simd_opc[opc];
5694 if (opc2 > 0) {
5695 emit_int8(opc2);
5696 }
5697 }
5698 return encode;
5699 }
5700
5701
5702 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, int vector_len) {
5703 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
5704 prefix(VEX_3bytes);
5705
5706 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
5707 byte1 = (~byte1) & 0xE0;
5708 byte1 |= opc;
5709 emit_int8(byte1);
5710
5711 int byte2 = ((~nds_enc) & 0xf) << 3;
5712 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
5713 emit_int8(byte2);
5714 } else {
5715 prefix(VEX_2bytes);
5716
5717 int byte1 = vex_r ? VEX_R : 0;
5718 byte1 = (~byte1) & 0x80;
5719 byte1 |= ((~nds_enc) & 0xf) << 3;
5720 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
5721 emit_int8(byte1);
5722 }
5723 }
5724
5725 // This is a 4 byte encoding
5726 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, bool evex_r, bool evex_v,
5727 int nds_enc, VexSimdPrefix pre, VexOpcode opc,
5728 bool is_extended_context, bool is_merge_context,
5729 int vector_len, bool no_mask_reg ){
5730 // EVEX 0x62 prefix
5731 prefix(EVEX_4bytes);
5732 evex_encoding = (vex_w ? VEX_W : 0) | (evex_r ? EVEX_Rb : 0);
5733
5734 // P0: byte 2, initialized to RXBR`00mm
5735 // instead of not'd
5736 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
5737 byte2 = (~byte2) & 0xF0;
5738 // confine opc opcode extensions in mm bits to lower two bits
5739 // of form {0F, 0F_38, 0F_3A}
5740 byte2 |= opc;
5741 emit_int8(byte2);
5742
5743 // P1: byte 3 as Wvvvv1pp
5744 int byte3 = ((~nds_enc) & 0xf) << 3;
5745 // p[10] is always 1
5746 byte3 |= EVEX_F;
5747 byte3 |= (vex_w & 1) << 7;
5748 // confine pre opcode extensions in pp bits to lower two bits
5749 // of form {66, F3, F2}
5750 byte3 |= pre;
5751 emit_int8(byte3);
5752
5753 // P2: byte 4 as zL'Lbv'aaa
5754 int byte4 = (no_mask_reg) ? 0 : 1; // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
5755 // EVEX.v` for extending EVEX.vvvv or VIDX
5756 byte4 |= (evex_v ? 0: EVEX_V);
5757 // third EXEC.b for broadcast actions
5758 byte4 |= (is_extended_context ? EVEX_Rb : 0);
5759 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
5760 byte4 |= ((vector_len) & 0x3) << 5;
5761 // last is EVEX.z for zero/merge actions
5762 byte4 |= (is_merge_context ? EVEX_Z : 0);
5763 emit_int8(byte4);
5764 }
5765
5766 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre,
5767 VexOpcode opc, bool vex_w, int vector_len, bool legacy_mode, bool no_mask_reg) {
5768 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
5769 bool vex_b = adr.base_needs_rex();
5770 bool vex_x = adr.index_needs_rex();
5771 avx_vector_len = vector_len;
5772
5773 // if vector length is turned off, revert to AVX for vectors smaller than AVX_512bit
5774 if (VM_Version::supports_avx512vl() == false) {
5775 switch (vector_len) {
5776 case AVX_128bit:
5777 case AVX_256bit:
5778 legacy_mode = true;
5779 break;
5780 }
5781 }
5782
5783 if ((UseAVX > 2) && (legacy_mode == false))
5784 {
5785 bool evex_r = (xreg_enc >= 16);
5786 bool evex_v = (nds_enc >= 16);
5787 is_evex_instruction = true;
5788 evex_prefix(vex_r, vex_b, vex_x, vex_w, evex_r, evex_v, nds_enc, pre, opc, false, false, vector_len, no_mask_reg);
5789 } else {
5790 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector_len);
5791 }
5792 }
5793
5794 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,
5795 bool vex_w, int vector_len, bool legacy_mode, bool no_mask_reg ) {
5796 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
5797 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
5798 bool vex_x = false;
5799 avx_vector_len = vector_len;
5800
5801 // if vector length is turned off, revert to AVX for vectors smaller than AVX_512bit
5802 if (VM_Version::supports_avx512vl() == false) {
5803 switch (vector_len) {
5804 case AVX_128bit:
5805 case AVX_256bit:
5806 legacy_mode = true;
5807 break;
5808 }
5809 }
5810
5811 if ((UseAVX > 2) && (legacy_mode == false))
5812 {
5813 bool evex_r = (dst_enc >= 16);
5814 bool evex_v = (nds_enc >= 16);
5815 // can use vex_x as bank extender on rm encoding
5816 vex_x = (src_enc >= 16);
5817 evex_prefix(vex_r, vex_b, vex_x, vex_w, evex_r, evex_v, nds_enc, pre, opc, false, false, vector_len, no_mask_reg);
5818 } else {
5819 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector_len);
5820 }
5821
5822 // return modrm byte components for operands
5823 return (((dst_enc & 7) << 3) | (src_enc & 7));
5824 }
5825
5826
5827 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
5828 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len, bool legacy_mode) {
5829 if (UseAVX > 0) {
5830 int xreg_enc = xreg->encoding();
5831 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5832 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector_len, legacy_mode, no_mask_reg);
5833 } else {
5834 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
5835 rex_prefix(adr, xreg, pre, opc, rex_w);
5836 }
5837 }
5838
5839 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
5840 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len, bool legacy_mode) {
5841 int dst_enc = dst->encoding();
5842 int src_enc = src->encoding();
5843 if (UseAVX > 0) {
5844 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5845 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, legacy_mode, no_mask_reg);
5846 } else {
5847 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
5848 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w);
5849 }
5850 }
5851
5852 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, KRegister src, VexSimdPrefix pre,
5853 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len) {
5854 int dst_enc = dst->encoding();
5855 int src_enc = src->encoding();
5856 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5857 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, true, no_mask_reg);
5858 }
5859
5860 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, Register src, VexSimdPrefix pre,
5861 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len) {
5862 int dst_enc = dst->encoding();
5863 int src_enc = src->encoding();
5864 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5865 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, true, no_mask_reg);
5866 }
5867
5868 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
5869 InstructionMark im(this);
5870 simd_prefix(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, false, AVX_128bit, legacy_mode);
5871 emit_int8(opcode);
5872 emit_operand(dst, src);
5873 }
5874
5875 void Assembler::emit_simd_arith_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg) {
5876 InstructionMark im(this);
5877 simd_prefix_q(dst, dst, src, pre, no_mask_reg);
5878 emit_int8(opcode);
5879 emit_operand(dst, src);
5880 }
5881
5882 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
5883 int encode = simd_prefix_and_encode(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, false, AVX_128bit, legacy_mode);
5884 emit_int8(opcode);
5885 emit_int8((unsigned char)(0xC0 | encode));
5886 }
5887
5888 void Assembler::emit_simd_arith_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg) {
5889 int encode = simd_prefix_and_encode(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, true, AVX_128bit);
5890 emit_int8(opcode);
5891 emit_int8((unsigned char)(0xC0 | encode));
5892 }
5893
5894 // Versions with no second source register (non-destructive source).
5895 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool opNoRegMask) {
5896 InstructionMark im(this);
5897 simd_prefix(dst, xnoreg, src, pre, opNoRegMask);
5898 emit_int8(opcode);
5899 emit_operand(dst, src);
5900 }
5901
5902 void Assembler::emit_simd_arith_nonds_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool opNoRegMask) {
5903 InstructionMark im(this);
5904 simd_prefix_q(dst, xnoreg, src, pre, opNoRegMask);
5905 emit_int8(opcode);
5906 emit_operand(dst, src);
5907 }
5908
5909 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
5910 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre, no_mask_reg, VEX_OPCODE_0F, legacy_mode, AVX_128bit);
5911 emit_int8(opcode);
5912 emit_int8((unsigned char)(0xC0 | encode));
5913 }
5914
5915 void Assembler::emit_simd_arith_nonds_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg) {
5916 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre, no_mask_reg, VEX_OPCODE_0F, true, AVX_128bit);
5917 emit_int8(opcode);
5918 emit_int8((unsigned char)(0xC0 | encode));
5919 }
5920
5921 // 3-operands AVX instructions
5922 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, Address src,
5923 VexSimdPrefix pre, int vector_len, bool no_mask_reg, bool legacy_mode) {
5924 InstructionMark im(this);
5925 vex_prefix(dst, nds, src, pre, vector_len, no_mask_reg, legacy_mode);
5926 emit_int8(opcode);
5927 emit_operand(dst, src);
5928 }
5929
5930 void Assembler::emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds,
5931 Address src, VexSimdPrefix pre, int vector_len, bool no_mask_reg) {
5932 InstructionMark im(this);
5933 vex_prefix_q(dst, nds, src, pre, vector_len, no_mask_reg);
5934 emit_int8(opcode);
5935 emit_operand(dst, src);
5936 }
5937
5938 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
5939 VexSimdPrefix pre, int vector_len, bool no_mask_reg, bool legacy_mode) {
5940 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector_len, VEX_OPCODE_0F, false, no_mask_reg);
5941 emit_int8(opcode);
5942 emit_int8((unsigned char)(0xC0 | encode));
5943 }
5944
5945 void Assembler::emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
5946 VexSimdPrefix pre, int vector_len, bool no_mask_reg) {
5947 int src_enc = src->encoding();
5948 int dst_enc = dst->encoding();
5949 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5950 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, VEX_OPCODE_0F, true, vector_len, false, no_mask_reg);
5951 emit_int8(opcode);
5952 emit_int8((unsigned char)(0xC0 | encode));
5953 }
5954
5955 #ifndef _LP64
5956
5957 void Assembler::incl(Register dst) {
5958 // Don't use it directly. Use MacroAssembler::incrementl() instead.
5959 emit_int8(0x40 | dst->encoding());
5960 }
5961
5962 void Assembler::lea(Register dst, Address src) {
5963 leal(dst, src);
5964 }
5965
5966 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
5967 InstructionMark im(this);
5968 emit_int8((unsigned char)0xC7);
5969 emit_operand(rax, dst);
5970 emit_data((int)imm32, rspec, 0);
5971 }
5972
5973 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
5974 InstructionMark im(this);
5975 int encode = prefix_and_encode(dst->encoding());
5976 emit_int8((unsigned char)(0xB8 | encode));
5977 emit_data((int)imm32, rspec, 0);
5978 }
5979
5980 void Assembler::popa() { // 32bit
5981 emit_int8(0x61);
5982 }
5983
5984 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
5985 InstructionMark im(this);
5986 emit_int8(0x68);
5987 emit_data(imm32, rspec, 0);
5988 }
5989
5990 void Assembler::pusha() { // 32bit
5991 emit_int8(0x60);
5992 }
5993
5994 void Assembler::set_byte_if_not_zero(Register dst) {
5995 emit_int8(0x0F);
5996 emit_int8((unsigned char)0x95);
5997 emit_int8((unsigned char)(0xE0 | dst->encoding()));
5998 }
5999
6000 void Assembler::shldl(Register dst, Register src) {
6001 emit_int8(0x0F);
6002 emit_int8((unsigned char)0xA5);
6003 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6004 }
6005
6006 void Assembler::shrdl(Register dst, Register src) {
6007 emit_int8(0x0F);
6008 emit_int8((unsigned char)0xAD);
6009 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6010 }
6011
6012 #else // LP64
6013
6014 void Assembler::set_byte_if_not_zero(Register dst) {
6015 int enc = prefix_and_encode(dst->encoding(), true);
6016 emit_int8(0x0F);
6017 emit_int8((unsigned char)0x95);
6018 emit_int8((unsigned char)(0xE0 | enc));
6019 }
6020
6021 // 64bit only pieces of the assembler
6022 // This should only be used by 64bit instructions that can use rip-relative
6023 // it cannot be used by instructions that want an immediate value.
6024
6025 bool Assembler::reachable(AddressLiteral adr) {
6026 int64_t disp;
6027 // None will force a 64bit literal to the code stream. Likely a placeholder
6028 // for something that will be patched later and we need to certain it will
6029 // always be reachable.
6030 if (adr.reloc() == relocInfo::none) {
6031 return false;
6032 }
6033 if (adr.reloc() == relocInfo::internal_word_type) {
6034 // This should be rip relative and easily reachable.
6035 return true;
6036 }
6037 if (adr.reloc() == relocInfo::virtual_call_type ||
6038 adr.reloc() == relocInfo::opt_virtual_call_type ||
6039 adr.reloc() == relocInfo::static_call_type ||
6040 adr.reloc() == relocInfo::static_stub_type ) {
6041 // This should be rip relative within the code cache and easily
6042 // reachable until we get huge code caches. (At which point
6043 // ic code is going to have issues).
6044 return true;
6045 }
6046 if (adr.reloc() != relocInfo::external_word_type &&
6047 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
6048 adr.reloc() != relocInfo::poll_type && // relocs to identify them
6049 adr.reloc() != relocInfo::runtime_call_type ) {
6050 return false;
6051 }
6052
6053 // Stress the correction code
6054 if (ForceUnreachable) {
6055 // Must be runtimecall reloc, see if it is in the codecache
6056 // Flipping stuff in the codecache to be unreachable causes issues
6057 // with things like inline caches where the additional instructions
6058 // are not handled.
6059 if (CodeCache::find_blob(adr._target) == NULL) {
6060 return false;
6061 }
6062 }
6063 // For external_word_type/runtime_call_type if it is reachable from where we
6064 // are now (possibly a temp buffer) and where we might end up
6065 // anywhere in the codeCache then we are always reachable.
6066 // This would have to change if we ever save/restore shared code
6067 // to be more pessimistic.
6068 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
6069 if (!is_simm32(disp)) return false;
6070 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
6071 if (!is_simm32(disp)) return false;
6072
6073 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
6074
6075 // Because rip relative is a disp + address_of_next_instruction and we
6076 // don't know the value of address_of_next_instruction we apply a fudge factor
6077 // to make sure we will be ok no matter the size of the instruction we get placed into.
6078 // We don't have to fudge the checks above here because they are already worst case.
6079
6080 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
6081 // + 4 because better safe than sorry.
6082 const int fudge = 12 + 4;
6083 if (disp < 0) {
6084 disp -= fudge;
6085 } else {
6086 disp += fudge;
6087 }
6088 return is_simm32(disp);
6089 }
6090
6091 // Check if the polling page is not reachable from the code cache using rip-relative
6092 // addressing.
6093 bool Assembler::is_polling_page_far() {
6094 intptr_t addr = (intptr_t)os::get_polling_page();
6095 return ForceUnreachable ||
6096 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
6097 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
6098 }
6099
6100 void Assembler::emit_data64(jlong data,
6101 relocInfo::relocType rtype,
6102 int format) {
6103 if (rtype == relocInfo::none) {
6104 emit_int64(data);
6105 } else {
6106 emit_data64(data, Relocation::spec_simple(rtype), format);
6107 }
6108 }
6109
6110 void Assembler::emit_data64(jlong data,
6111 RelocationHolder const& rspec,
6112 int format) {
6113 assert(imm_operand == 0, "default format must be immediate in this file");
6114 assert(imm_operand == format, "must be immediate");
6115 assert(inst_mark() != NULL, "must be inside InstructionMark");
6116 // Do not use AbstractAssembler::relocate, which is not intended for
6117 // embedded words. Instead, relocate to the enclosing instruction.
6118 code_section()->relocate(inst_mark(), rspec, format);
6119 #ifdef ASSERT
6120 check_relocation(rspec, format);
6121 #endif
6122 emit_int64(data);
6123 }
6124
6125 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
6126 if (reg_enc >= 8) {
6127 prefix(REX_B);
6128 reg_enc -= 8;
6129 } else if (byteinst && reg_enc >= 4) {
6130 prefix(REX);
6131 }
6132 return reg_enc;
6133 }
6134
6135 int Assembler::prefixq_and_encode(int reg_enc) {
6136 if (reg_enc < 8) {
6137 prefix(REX_W);
6138 } else {
6139 prefix(REX_WB);
6140 reg_enc -= 8;
6141 }
6142 return reg_enc;
6143 }
6144
6145 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
6146 if (dst_enc < 8) {
6147 if (src_enc >= 8) {
6148 prefix(REX_B);
6149 src_enc -= 8;
6150 } else if (byteinst && src_enc >= 4) {
6151 prefix(REX);
6152 }
6153 } else {
6154 if (src_enc < 8) {
6155 prefix(REX_R);
6156 } else {
6157 prefix(REX_RB);
6158 src_enc -= 8;
6159 }
6160 dst_enc -= 8;
6161 }
6162 return dst_enc << 3 | src_enc;
6163 }
6164
6165 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
6166 if (dst_enc < 8) {
6167 if (src_enc < 8) {
6168 prefix(REX_W);
6169 } else {
6170 prefix(REX_WB);
6171 src_enc -= 8;
6172 }
6173 } else {
6174 if (src_enc < 8) {
6175 prefix(REX_WR);
6176 } else {
6177 prefix(REX_WRB);
6178 src_enc -= 8;
6179 }
6180 dst_enc -= 8;
6181 }
6182 return dst_enc << 3 | src_enc;
6183 }
6184
6185 void Assembler::prefix(Register reg) {
6186 if (reg->encoding() >= 8) {
6187 prefix(REX_B);
6188 }
6189 }
6190
6191 void Assembler::prefix(Address adr) {
6192 if (adr.base_needs_rex()) {
6193 if (adr.index_needs_rex()) {
6194 prefix(REX_XB);
6195 } else {
6196 prefix(REX_B);
6197 }
6198 } else {
6199 if (adr.index_needs_rex()) {
6200 prefix(REX_X);
6201 }
6202 }
6203 }
6204
6205 void Assembler::prefixq(Address adr) {
6206 if (adr.base_needs_rex()) {
6207 if (adr.index_needs_rex()) {
6208 prefix(REX_WXB);
6209 } else {
6210 prefix(REX_WB);
6211 }
6212 } else {
6213 if (adr.index_needs_rex()) {
6214 prefix(REX_WX);
6215 } else {
6216 prefix(REX_W);
6217 }
6218 }
6219 }
6220
6221
6222 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
6223 if (reg->encoding() < 8) {
6224 if (adr.base_needs_rex()) {
6225 if (adr.index_needs_rex()) {
6226 prefix(REX_XB);
6227 } else {
6228 prefix(REX_B);
6229 }
6230 } else {
6231 if (adr.index_needs_rex()) {
6232 prefix(REX_X);
6233 } else if (byteinst && reg->encoding() >= 4 ) {
6234 prefix(REX);
6235 }
6236 }
6237 } else {
6238 if (adr.base_needs_rex()) {
6239 if (adr.index_needs_rex()) {
6240 prefix(REX_RXB);
6241 } else {
6242 prefix(REX_RB);
6243 }
6244 } else {
6245 if (adr.index_needs_rex()) {
6246 prefix(REX_RX);
6247 } else {
6248 prefix(REX_R);
6249 }
6250 }
6251 }
6252 }
6253
6254 void Assembler::prefixq(Address adr, Register src) {
6255 if (src->encoding() < 8) {
6256 if (adr.base_needs_rex()) {
6257 if (adr.index_needs_rex()) {
6258 prefix(REX_WXB);
6259 } else {
6260 prefix(REX_WB);
6261 }
6262 } else {
6263 if (adr.index_needs_rex()) {
6264 prefix(REX_WX);
6265 } else {
6266 prefix(REX_W);
6267 }
6268 }
6269 } else {
6270 if (adr.base_needs_rex()) {
6271 if (adr.index_needs_rex()) {
6272 prefix(REX_WRXB);
6273 } else {
6274 prefix(REX_WRB);
6275 }
6276 } else {
6277 if (adr.index_needs_rex()) {
6278 prefix(REX_WRX);
6279 } else {
6280 prefix(REX_WR);
6281 }
6282 }
6283 }
6284 }
6285
6286 void Assembler::prefix(Address adr, XMMRegister reg) {
6287 if (reg->encoding() < 8) {
6288 if (adr.base_needs_rex()) {
6289 if (adr.index_needs_rex()) {
6290 prefix(REX_XB);
6291 } else {
6292 prefix(REX_B);
6293 }
6294 } else {
6295 if (adr.index_needs_rex()) {
6296 prefix(REX_X);
6297 }
6298 }
6299 } else {
6300 if (adr.base_needs_rex()) {
6301 if (adr.index_needs_rex()) {
6302 prefix(REX_RXB);
6303 } else {
6304 prefix(REX_RB);
6305 }
6306 } else {
6307 if (adr.index_needs_rex()) {
6308 prefix(REX_RX);
6309 } else {
6310 prefix(REX_R);
6311 }
6312 }
6313 }
6314 }
6315
6316 void Assembler::prefixq(Address adr, XMMRegister src) {
6317 if (src->encoding() < 8) {
6318 if (adr.base_needs_rex()) {
6319 if (adr.index_needs_rex()) {
6320 prefix(REX_WXB);
6321 } else {
6322 prefix(REX_WB);
6323 }
6324 } else {
6325 if (adr.index_needs_rex()) {
6326 prefix(REX_WX);
6327 } else {
6328 prefix(REX_W);
6329 }
6330 }
6331 } else {
6332 if (adr.base_needs_rex()) {
6333 if (adr.index_needs_rex()) {
6334 prefix(REX_WRXB);
6335 } else {
6336 prefix(REX_WRB);
6337 }
6338 } else {
6339 if (adr.index_needs_rex()) {
6340 prefix(REX_WRX);
6341 } else {
6342 prefix(REX_WR);
6343 }
6344 }
6345 }
6346 }
6347
6348 void Assembler::adcq(Register dst, int32_t imm32) {
6349 (void) prefixq_and_encode(dst->encoding());
6350 emit_arith(0x81, 0xD0, dst, imm32);
6351 }
6352
6353 void Assembler::adcq(Register dst, Address src) {
6354 InstructionMark im(this);
6355 prefixq(src, dst);
6356 emit_int8(0x13);
6357 emit_operand(dst, src);
6358 }
6359
6360 void Assembler::adcq(Register dst, Register src) {
6361 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6362 emit_arith(0x13, 0xC0, dst, src);
6363 }
6364
6365 void Assembler::addq(Address dst, int32_t imm32) {
6366 InstructionMark im(this);
6367 prefixq(dst);
6368 emit_arith_operand(0x81, rax, dst,imm32);
6369 }
6370
6371 void Assembler::addq(Address dst, Register src) {
6372 InstructionMark im(this);
6373 prefixq(dst, src);
6374 emit_int8(0x01);
6375 emit_operand(src, dst);
6376 }
6377
6378 void Assembler::addq(Register dst, int32_t imm32) {
6379 (void) prefixq_and_encode(dst->encoding());
6380 emit_arith(0x81, 0xC0, dst, imm32);
6381 }
6382
6383 void Assembler::addq(Register dst, Address src) {
6384 InstructionMark im(this);
6385 prefixq(src, dst);
6386 emit_int8(0x03);
6387 emit_operand(dst, src);
6388 }
6389
6390 void Assembler::addq(Register dst, Register src) {
6391 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6392 emit_arith(0x03, 0xC0, dst, src);
6393 }
6394
6395 void Assembler::adcxq(Register dst, Register src) {
6396 //assert(VM_Version::supports_adx(), "adx instructions not supported");
6397 emit_int8((unsigned char)0x66);
6398 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6399 emit_int8(0x0F);
6400 emit_int8(0x38);
6401 emit_int8((unsigned char)0xF6);
6402 emit_int8((unsigned char)(0xC0 | encode));
6403 }
6404
6405 void Assembler::adoxq(Register dst, Register src) {
6406 //assert(VM_Version::supports_adx(), "adx instructions not supported");
6407 emit_int8((unsigned char)0xF3);
6408 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6409 emit_int8(0x0F);
6410 emit_int8(0x38);
6411 emit_int8((unsigned char)0xF6);
6412 emit_int8((unsigned char)(0xC0 | encode));
6413 }
6414
6415 void Assembler::andq(Address dst, int32_t imm32) {
6416 InstructionMark im(this);
6417 prefixq(dst);
6418 emit_int8((unsigned char)0x81);
6419 emit_operand(rsp, dst, 4);
6420 emit_int32(imm32);
6421 }
6422
6423 void Assembler::andq(Register dst, int32_t imm32) {
6424 (void) prefixq_and_encode(dst->encoding());
6425 emit_arith(0x81, 0xE0, dst, imm32);
6426 }
6427
6428 void Assembler::andq(Register dst, Address src) {
6429 InstructionMark im(this);
6430 prefixq(src, dst);
6431 emit_int8(0x23);
6432 emit_operand(dst, src);
6433 }
6434
6435 void Assembler::andq(Register dst, Register src) {
6436 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6437 emit_arith(0x23, 0xC0, dst, src);
6438 }
6439
6440 void Assembler::andnq(Register dst, Register src1, Register src2) {
6441 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6442 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(),
6443 VEX_SIMD_NONE, VEX_OPCODE_0F_38, true, AVX_128bit,
6444 true, false);
6445 emit_int8((unsigned char)0xF2);
6446 emit_int8((unsigned char)(0xC0 | encode));
6447 }
6448
6449 void Assembler::andnq(Register dst, Register src1, Address src2) {
6450 InstructionMark im(this);
6451 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6452 vex_prefix(src2, src1->encoding(), dst->encoding(),
6453 VEX_SIMD_NONE, VEX_OPCODE_0F_38, true,
6454 AVX_128bit, true, false);
6455 emit_int8((unsigned char)0xF2);
6456 emit_operand(dst, src2);
6457 }
6458
6459 void Assembler::bsfq(Register dst, Register src) {
6460 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6461 emit_int8(0x0F);
6462 emit_int8((unsigned char)0xBC);
6463 emit_int8((unsigned char)(0xC0 | encode));
6464 }
6465
6466 void Assembler::bsrq(Register dst, Register src) {
6467 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6468 emit_int8(0x0F);
6469 emit_int8((unsigned char)0xBD);
6470 emit_int8((unsigned char)(0xC0 | encode));
6471 }
6472
6473 void Assembler::bswapq(Register reg) {
6474 int encode = prefixq_and_encode(reg->encoding());
6475 emit_int8(0x0F);
6476 emit_int8((unsigned char)(0xC8 | encode));
6477 }
6478
6479 void Assembler::blsiq(Register dst, Register src) {
6480 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6481 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(),
6482 VEX_SIMD_NONE, VEX_OPCODE_0F_38, true, AVX_128bit,
6483 true, false);
6484 emit_int8((unsigned char)0xF3);
6485 emit_int8((unsigned char)(0xC0 | encode));
6486 }
6487
6488 void Assembler::blsiq(Register dst, Address src) {
6489 InstructionMark im(this);
6490 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6491 vex_prefix(src, dst->encoding(), rbx->encoding(),
6492 VEX_SIMD_NONE, VEX_OPCODE_0F_38, true,
6493 AVX_128bit, true, false);
6494 emit_int8((unsigned char)0xF3);
6495 emit_operand(rbx, src);
6496 }
6497
6498 void Assembler::blsmskq(Register dst, Register src) {
6499 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6500 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(),
6501 VEX_SIMD_NONE, VEX_OPCODE_0F_38, true, AVX_128bit,
6502 true, false);
6503 emit_int8((unsigned char)0xF3);
6504 emit_int8((unsigned char)(0xC0 | encode));
6505 }
6506
6507 void Assembler::blsmskq(Register dst, Address src) {
6508 InstructionMark im(this);
6509 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6510 vex_prefix(src, dst->encoding(), rdx->encoding(),
6511 VEX_SIMD_NONE, VEX_OPCODE_0F_38, true,
6512 AVX_128bit, true, false);
6513 emit_int8((unsigned char)0xF3);
6514 emit_operand(rdx, src);
6515 }
6516
6517 void Assembler::blsrq(Register dst, Register src) {
6518 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6519 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(),
6520 VEX_SIMD_NONE, VEX_OPCODE_0F_38, true, AVX_128bit,
6521 true, false);
6522 emit_int8((unsigned char)0xF3);
6523 emit_int8((unsigned char)(0xC0 | encode));
6524 }
6525
6526 void Assembler::blsrq(Register dst, Address src) {
6527 InstructionMark im(this);
6528 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6529 vex_prefix(src, dst->encoding(), rcx->encoding(),
6530 VEX_SIMD_NONE, VEX_OPCODE_0F_38, true,
6531 AVX_128bit, true, false);
6532 emit_int8((unsigned char)0xF3);
6533 emit_operand(rcx, src);
6534 }
6535
6536 void Assembler::cdqq() {
6537 prefix(REX_W);
6538 emit_int8((unsigned char)0x99);
6539 }
6540
6541 void Assembler::clflush(Address adr) {
6542 prefix(adr);
6543 emit_int8(0x0F);
6544 emit_int8((unsigned char)0xAE);
6545 emit_operand(rdi, adr);
6546 }
6547
6548 void Assembler::cmovq(Condition cc, Register dst, Register src) {
6549 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6550 emit_int8(0x0F);
6551 emit_int8(0x40 | cc);
6552 emit_int8((unsigned char)(0xC0 | encode));
6553 }
6554
6555 void Assembler::cmovq(Condition cc, Register dst, Address src) {
6556 InstructionMark im(this);
6557 prefixq(src, dst);
6558 emit_int8(0x0F);
6559 emit_int8(0x40 | cc);
6560 emit_operand(dst, src);
6561 }
6562
6563 void Assembler::cmpq(Address dst, int32_t imm32) {
6564 InstructionMark im(this);
6565 prefixq(dst);
6566 emit_int8((unsigned char)0x81);
6567 emit_operand(rdi, dst, 4);
6568 emit_int32(imm32);
6569 }
6570
6571 void Assembler::cmpq(Register dst, int32_t imm32) {
6572 (void) prefixq_and_encode(dst->encoding());
6573 emit_arith(0x81, 0xF8, dst, imm32);
6574 }
6575
6576 void Assembler::cmpq(Address dst, Register src) {
6577 InstructionMark im(this);
6578 prefixq(dst, src);
6579 emit_int8(0x3B);
6580 emit_operand(src, dst);
6581 }
6582
6583 void Assembler::cmpq(Register dst, Register src) {
6584 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6585 emit_arith(0x3B, 0xC0, dst, src);
6586 }
6587
6588 void Assembler::cmpq(Register dst, Address src) {
6589 InstructionMark im(this);
6590 prefixq(src, dst);
6591 emit_int8(0x3B);
6592 emit_operand(dst, src);
6593 }
6594
6595 void Assembler::cmpxchgq(Register reg, Address adr) {
6596 InstructionMark im(this);
6597 prefixq(adr, reg);
6598 emit_int8(0x0F);
6599 emit_int8((unsigned char)0xB1);
6600 emit_operand(reg, adr);
6601 }
6602
6603 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
6604 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6605 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2, true);
6606 emit_int8(0x2A);
6607 emit_int8((unsigned char)(0xC0 | encode));
6608 }
6609
6610 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
6611 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6612 if (VM_Version::supports_evex()) {
6613 tuple_type = EVEX_T1S;
6614 input_size_in_bits = EVEX_32bit;
6615 }
6616 InstructionMark im(this);
6617 simd_prefix_q(dst, dst, src, VEX_SIMD_F2, true);
6618 emit_int8(0x2A);
6619 emit_operand(dst, src);
6620 }
6621
6622 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
6623 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6624 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3, true);
6625 emit_int8(0x2A);
6626 emit_int8((unsigned char)(0xC0 | encode));
6627 }
6628
6629 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
6630 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6631 if (VM_Version::supports_evex()) {
6632 tuple_type = EVEX_T1S;
6633 input_size_in_bits = EVEX_32bit;
6634 }
6635 InstructionMark im(this);
6636 simd_prefix_q(dst, dst, src, VEX_SIMD_F3, true);
6637 emit_int8(0x2A);
6638 emit_operand(dst, src);
6639 }
6640
6641 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
6642 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6643 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, true);
6644 emit_int8(0x2C);
6645 emit_int8((unsigned char)(0xC0 | encode));
6646 }
6647
6648 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
6649 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6650 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, true);
6651 emit_int8(0x2C);
6652 emit_int8((unsigned char)(0xC0 | encode));
6653 }
6654
6655 void Assembler::decl(Register dst) {
6656 // Don't use it directly. Use MacroAssembler::decrementl() instead.
6657 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
6658 int encode = prefix_and_encode(dst->encoding());
6659 emit_int8((unsigned char)0xFF);
6660 emit_int8((unsigned char)(0xC8 | encode));
6661 }
6662
6663 void Assembler::decq(Register dst) {
6664 // Don't use it directly. Use MacroAssembler::decrementq() instead.
6665 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
6666 int encode = prefixq_and_encode(dst->encoding());
6667 emit_int8((unsigned char)0xFF);
6668 emit_int8(0xC8 | encode);
6669 }
6670
6671 void Assembler::decq(Address dst) {
6672 // Don't use it directly. Use MacroAssembler::decrementq() instead.
6673 InstructionMark im(this);
6674 prefixq(dst);
6675 emit_int8((unsigned char)0xFF);
6676 emit_operand(rcx, dst);
6677 }
6678
6679 void Assembler::fxrstor(Address src) {
6680 prefixq(src);
6681 emit_int8(0x0F);
6682 emit_int8((unsigned char)0xAE);
6683 emit_operand(as_Register(1), src);
6684 }
6685
6686 void Assembler::fxsave(Address dst) {
6687 prefixq(dst);
6688 emit_int8(0x0F);
6689 emit_int8((unsigned char)0xAE);
6690 emit_operand(as_Register(0), dst);
6691 }
6692
6693 void Assembler::idivq(Register src) {
6694 int encode = prefixq_and_encode(src->encoding());
6695 emit_int8((unsigned char)0xF7);
6696 emit_int8((unsigned char)(0xF8 | encode));
6697 }
6698
6699 void Assembler::imulq(Register dst, Register src) {
6700 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6701 emit_int8(0x0F);
6702 emit_int8((unsigned char)0xAF);
6703 emit_int8((unsigned char)(0xC0 | encode));
6704 }
6705
6706 void Assembler::imulq(Register dst, Register src, int value) {
6707 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6708 if (is8bit(value)) {
6709 emit_int8(0x6B);
6710 emit_int8((unsigned char)(0xC0 | encode));
6711 emit_int8(value & 0xFF);
6712 } else {
6713 emit_int8(0x69);
6714 emit_int8((unsigned char)(0xC0 | encode));
6715 emit_int32(value);
6716 }
6717 }
6718
6719 void Assembler::imulq(Register dst, Address src) {
6720 InstructionMark im(this);
6721 prefixq(src, dst);
6722 emit_int8(0x0F);
6723 emit_int8((unsigned char) 0xAF);
6724 emit_operand(dst, src);
6725 }
6726
6727 void Assembler::incl(Register dst) {
6728 // Don't use it directly. Use MacroAssembler::incrementl() instead.
6729 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
6730 int encode = prefix_and_encode(dst->encoding());
6731 emit_int8((unsigned char)0xFF);
6732 emit_int8((unsigned char)(0xC0 | encode));
6733 }
6734
6735 void Assembler::incq(Register dst) {
6736 // Don't use it directly. Use MacroAssembler::incrementq() instead.
6737 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
6738 int encode = prefixq_and_encode(dst->encoding());
6739 emit_int8((unsigned char)0xFF);
6740 emit_int8((unsigned char)(0xC0 | encode));
6741 }
6742
6743 void Assembler::incq(Address dst) {
6744 // Don't use it directly. Use MacroAssembler::incrementq() instead.
6745 InstructionMark im(this);
6746 prefixq(dst);
6747 emit_int8((unsigned char)0xFF);
6748 emit_operand(rax, dst);
6749 }
6750
6751 void Assembler::lea(Register dst, Address src) {
6752 leaq(dst, src);
6753 }
6754
6755 void Assembler::leaq(Register dst, Address src) {
6756 InstructionMark im(this);
6757 prefixq(src, dst);
6758 emit_int8((unsigned char)0x8D);
6759 emit_operand(dst, src);
6760 }
6761
6762 void Assembler::mov64(Register dst, int64_t imm64) {
6763 InstructionMark im(this);
6764 int encode = prefixq_and_encode(dst->encoding());
6765 emit_int8((unsigned char)(0xB8 | encode));
6766 emit_int64(imm64);
6767 }
6768
6769 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
6770 InstructionMark im(this);
6771 int encode = prefixq_and_encode(dst->encoding());
6772 emit_int8(0xB8 | encode);
6773 emit_data64(imm64, rspec);
6774 }
6775
6776 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
6777 InstructionMark im(this);
6778 int encode = prefix_and_encode(dst->encoding());
6779 emit_int8((unsigned char)(0xB8 | encode));
6780 emit_data((int)imm32, rspec, narrow_oop_operand);
6781 }
6782
6783 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
6784 InstructionMark im(this);
6785 prefix(dst);
6786 emit_int8((unsigned char)0xC7);
6787 emit_operand(rax, dst, 4);
6788 emit_data((int)imm32, rspec, narrow_oop_operand);
6789 }
6790
6791 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
6792 InstructionMark im(this);
6793 int encode = prefix_and_encode(src1->encoding());
6794 emit_int8((unsigned char)0x81);
6795 emit_int8((unsigned char)(0xF8 | encode));
6796 emit_data((int)imm32, rspec, narrow_oop_operand);
6797 }
6798
6799 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
6800 InstructionMark im(this);
6801 prefix(src1);
6802 emit_int8((unsigned char)0x81);
6803 emit_operand(rax, src1, 4);
6804 emit_data((int)imm32, rspec, narrow_oop_operand);
6805 }
6806
6807 void Assembler::lzcntq(Register dst, Register src) {
6808 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
6809 emit_int8((unsigned char)0xF3);
6810 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6811 emit_int8(0x0F);
6812 emit_int8((unsigned char)0xBD);
6813 emit_int8((unsigned char)(0xC0 | encode));
6814 }
6815
6816 void Assembler::movdq(XMMRegister dst, Register src) {
6817 // table D-1 says MMX/SSE2
6818 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6819 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66, true);
6820 emit_int8(0x6E);
6821 emit_int8((unsigned char)(0xC0 | encode));
6822 }
6823
6824 void Assembler::movdq(Register dst, XMMRegister src) {
6825 // table D-1 says MMX/SSE2
6826 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6827 // swap src/dst to get correct prefix
6828 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66, true);
6829 emit_int8(0x7E);
6830 emit_int8((unsigned char)(0xC0 | encode));
6831 }
6832
6833 void Assembler::movq(Register dst, Register src) {
6834 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6835 emit_int8((unsigned char)0x8B);
6836 emit_int8((unsigned char)(0xC0 | encode));
6837 }
6838
6839 void Assembler::movq(Register dst, Address src) {
6840 InstructionMark im(this);
6841 prefixq(src, dst);
6842 emit_int8((unsigned char)0x8B);
6843 emit_operand(dst, src);
6844 }
6845
6846 void Assembler::movq(Address dst, Register src) {
6847 InstructionMark im(this);
6848 prefixq(dst, src);
6849 emit_int8((unsigned char)0x89);
6850 emit_operand(src, dst);
6851 }
6852
6853 void Assembler::movsbq(Register dst, Address src) {
6854 InstructionMark im(this);
6855 prefixq(src, dst);
6856 emit_int8(0x0F);
6857 emit_int8((unsigned char)0xBE);
6858 emit_operand(dst, src);
6859 }
6860
6861 void Assembler::movsbq(Register dst, Register src) {
6862 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6863 emit_int8(0x0F);
6864 emit_int8((unsigned char)0xBE);
6865 emit_int8((unsigned char)(0xC0 | encode));
6866 }
6867
6868 void Assembler::movslq(Register dst, int32_t imm32) {
6869 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
6870 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
6871 // as a result we shouldn't use until tested at runtime...
6872 ShouldNotReachHere();
6873 InstructionMark im(this);
6874 int encode = prefixq_and_encode(dst->encoding());
6875 emit_int8((unsigned char)(0xC7 | encode));
6876 emit_int32(imm32);
6877 }
6878
6879 void Assembler::movslq(Address dst, int32_t imm32) {
6880 assert(is_simm32(imm32), "lost bits");
6881 InstructionMark im(this);
6882 prefixq(dst);
6883 emit_int8((unsigned char)0xC7);
6884 emit_operand(rax, dst, 4);
6885 emit_int32(imm32);
6886 }
6887
6888 void Assembler::movslq(Register dst, Address src) {
6889 InstructionMark im(this);
6890 prefixq(src, dst);
6891 emit_int8(0x63);
6892 emit_operand(dst, src);
6893 }
6894
6895 void Assembler::movslq(Register dst, Register src) {
6896 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6897 emit_int8(0x63);
6898 emit_int8((unsigned char)(0xC0 | encode));
6899 }
6900
6901 void Assembler::movswq(Register dst, Address src) {
6902 InstructionMark im(this);
6903 prefixq(src, dst);
6904 emit_int8(0x0F);
6905 emit_int8((unsigned char)0xBF);
6906 emit_operand(dst, src);
6907 }
6908
6909 void Assembler::movswq(Register dst, Register src) {
6910 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6911 emit_int8((unsigned char)0x0F);
6912 emit_int8((unsigned char)0xBF);
6913 emit_int8((unsigned char)(0xC0 | encode));
6914 }
6915
6916 void Assembler::movzbq(Register dst, Address src) {
6917 InstructionMark im(this);
6918 prefixq(src, dst);
6919 emit_int8((unsigned char)0x0F);
6920 emit_int8((unsigned char)0xB6);
6921 emit_operand(dst, src);
6922 }
6923
6924 void Assembler::movzbq(Register dst, Register src) {
6925 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6926 emit_int8(0x0F);
6927 emit_int8((unsigned char)0xB6);
6928 emit_int8(0xC0 | encode);
6929 }
6930
6931 void Assembler::movzwq(Register dst, Address src) {
6932 InstructionMark im(this);
6933 prefixq(src, dst);
6934 emit_int8((unsigned char)0x0F);
6935 emit_int8((unsigned char)0xB7);
6936 emit_operand(dst, src);
6937 }
6938
6939 void Assembler::movzwq(Register dst, Register src) {
6940 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6941 emit_int8((unsigned char)0x0F);
6942 emit_int8((unsigned char)0xB7);
6943 emit_int8((unsigned char)(0xC0 | encode));
6944 }
6945
6946 void Assembler::mulq(Address src) {
6947 InstructionMark im(this);
6948 prefixq(src);
6949 emit_int8((unsigned char)0xF7);
6950 emit_operand(rsp, src);
6951 }
6952
6953 void Assembler::mulq(Register src) {
6954 int encode = prefixq_and_encode(src->encoding());
6955 emit_int8((unsigned char)0xF7);
6956 emit_int8((unsigned char)(0xE0 | encode));
6957 }
6958
6959 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
6960 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
6961 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(),
6962 VEX_SIMD_F2, VEX_OPCODE_0F_38, true, AVX_128bit, true, false);
6963 emit_int8((unsigned char)0xF6);
6964 emit_int8((unsigned char)(0xC0 | encode));
6965 }
6966
6967 void Assembler::negq(Register dst) {
6968 int encode = prefixq_and_encode(dst->encoding());
6969 emit_int8((unsigned char)0xF7);
6970 emit_int8((unsigned char)(0xD8 | encode));
6971 }
6972
6973 void Assembler::notq(Register dst) {
6974 int encode = prefixq_and_encode(dst->encoding());
6975 emit_int8((unsigned char)0xF7);
6976 emit_int8((unsigned char)(0xD0 | encode));
6977 }
6978
6979 void Assembler::orq(Address dst, int32_t imm32) {
6980 InstructionMark im(this);
6981 prefixq(dst);
6982 emit_int8((unsigned char)0x81);
6983 emit_operand(rcx, dst, 4);
6984 emit_int32(imm32);
6985 }
6986
6987 void Assembler::orq(Register dst, int32_t imm32) {
6988 (void) prefixq_and_encode(dst->encoding());
6989 emit_arith(0x81, 0xC8, dst, imm32);
6990 }
6991
6992 void Assembler::orq(Register dst, Address src) {
6993 InstructionMark im(this);
6994 prefixq(src, dst);
6995 emit_int8(0x0B);
6996 emit_operand(dst, src);
6997 }
6998
6999 void Assembler::orq(Register dst, Register src) {
7000 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7001 emit_arith(0x0B, 0xC0, dst, src);
7002 }
7003
7004 void Assembler::popa() { // 64bit
7005 movq(r15, Address(rsp, 0));
7006 movq(r14, Address(rsp, wordSize));
7007 movq(r13, Address(rsp, 2 * wordSize));
7008 movq(r12, Address(rsp, 3 * wordSize));
7009 movq(r11, Address(rsp, 4 * wordSize));
7010 movq(r10, Address(rsp, 5 * wordSize));
7011 movq(r9, Address(rsp, 6 * wordSize));
7012 movq(r8, Address(rsp, 7 * wordSize));
7013 movq(rdi, Address(rsp, 8 * wordSize));
7014 movq(rsi, Address(rsp, 9 * wordSize));
7015 movq(rbp, Address(rsp, 10 * wordSize));
7016 // skip rsp
7017 movq(rbx, Address(rsp, 12 * wordSize));
7018 movq(rdx, Address(rsp, 13 * wordSize));
7019 movq(rcx, Address(rsp, 14 * wordSize));
7020 movq(rax, Address(rsp, 15 * wordSize));
7021
7022 addq(rsp, 16 * wordSize);
7023 }
7024
7025 void Assembler::popcntq(Register dst, Address src) {
7026 assert(VM_Version::supports_popcnt(), "must support");
7027 InstructionMark im(this);
7028 emit_int8((unsigned char)0xF3);
7029 prefixq(src, dst);
7030 emit_int8((unsigned char)0x0F);
7031 emit_int8((unsigned char)0xB8);
7032 emit_operand(dst, src);
7033 }
7034
7035 void Assembler::popcntq(Register dst, Register src) {
7036 assert(VM_Version::supports_popcnt(), "must support");
7037 emit_int8((unsigned char)0xF3);
7038 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7039 emit_int8((unsigned char)0x0F);
7040 emit_int8((unsigned char)0xB8);
7041 emit_int8((unsigned char)(0xC0 | encode));
7042 }
7043
7044 void Assembler::popq(Address dst) {
7045 InstructionMark im(this);
7046 prefixq(dst);
7047 emit_int8((unsigned char)0x8F);
7048 emit_operand(rax, dst);
7049 }
7050
7051 void Assembler::pusha() { // 64bit
7052 // we have to store original rsp. ABI says that 128 bytes
7053 // below rsp are local scratch.
7054 movq(Address(rsp, -5 * wordSize), rsp);
7055
7056 subq(rsp, 16 * wordSize);
7057
7058 movq(Address(rsp, 15 * wordSize), rax);
7059 movq(Address(rsp, 14 * wordSize), rcx);
7060 movq(Address(rsp, 13 * wordSize), rdx);
7061 movq(Address(rsp, 12 * wordSize), rbx);
7062 // skip rsp
7063 movq(Address(rsp, 10 * wordSize), rbp);
7064 movq(Address(rsp, 9 * wordSize), rsi);
7065 movq(Address(rsp, 8 * wordSize), rdi);
7066 movq(Address(rsp, 7 * wordSize), r8);
7067 movq(Address(rsp, 6 * wordSize), r9);
7068 movq(Address(rsp, 5 * wordSize), r10);
7069 movq(Address(rsp, 4 * wordSize), r11);
7070 movq(Address(rsp, 3 * wordSize), r12);
7071 movq(Address(rsp, 2 * wordSize), r13);
7072 movq(Address(rsp, wordSize), r14);
7073 movq(Address(rsp, 0), r15);
7074 }
7075
7076 void Assembler::pushq(Address src) {
7077 InstructionMark im(this);
7078 prefixq(src);
7079 emit_int8((unsigned char)0xFF);
7080 emit_operand(rsi, src);
7081 }
7082
7083 void Assembler::rclq(Register dst, int imm8) {
7084 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7085 int encode = prefixq_and_encode(dst->encoding());
7086 if (imm8 == 1) {
7087 emit_int8((unsigned char)0xD1);
7088 emit_int8((unsigned char)(0xD0 | encode));
7089 } else {
7090 emit_int8((unsigned char)0xC1);
7091 emit_int8((unsigned char)(0xD0 | encode));
7092 emit_int8(imm8);
7093 }
7094 }
7095
7096 void Assembler::rorq(Register dst, int imm8) {
7097 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7098 int encode = prefixq_and_encode(dst->encoding());
7099 if (imm8 == 1) {
7100 emit_int8((unsigned char)0xD1);
7101 emit_int8((unsigned char)(0xC8 | encode));
7102 } else {
7103 emit_int8((unsigned char)0xC1);
7104 emit_int8((unsigned char)(0xc8 | encode));
7105 emit_int8(imm8);
7106 }
7107 }
7108
7109 void Assembler::rorxq(Register dst, Register src, int imm8) {
7110 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
7111 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2,
7112 VEX_OPCODE_0F_3A, true, AVX_128bit, true, false);
7113 emit_int8((unsigned char)0xF0);
7114 emit_int8((unsigned char)(0xC0 | encode));
7115 emit_int8(imm8);
7116 }
7117
7118 void Assembler::sarq(Register dst, int imm8) {
7119 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7120 int encode = prefixq_and_encode(dst->encoding());
7121 if (imm8 == 1) {
7122 emit_int8((unsigned char)0xD1);
7123 emit_int8((unsigned char)(0xF8 | encode));
7124 } else {
7125 emit_int8((unsigned char)0xC1);
7126 emit_int8((unsigned char)(0xF8 | encode));
7127 emit_int8(imm8);
7128 }
7129 }
7130
7131 void Assembler::sarq(Register dst) {
7132 int encode = prefixq_and_encode(dst->encoding());
7133 emit_int8((unsigned char)0xD3);
7134 emit_int8((unsigned char)(0xF8 | encode));
7135 }
7136
7137 void Assembler::sbbq(Address dst, int32_t imm32) {
7138 InstructionMark im(this);
7139 prefixq(dst);
7140 emit_arith_operand(0x81, rbx, dst, imm32);
7141 }
7142
7143 void Assembler::sbbq(Register dst, int32_t imm32) {
7144 (void) prefixq_and_encode(dst->encoding());
7145 emit_arith(0x81, 0xD8, dst, imm32);
7146 }
7147
7148 void Assembler::sbbq(Register dst, Address src) {
7149 InstructionMark im(this);
7150 prefixq(src, dst);
7151 emit_int8(0x1B);
7152 emit_operand(dst, src);
7153 }
7154
7155 void Assembler::sbbq(Register dst, Register src) {
7156 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7157 emit_arith(0x1B, 0xC0, dst, src);
7158 }
7159
7160 void Assembler::shlq(Register dst, int imm8) {
7161 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7162 int encode = prefixq_and_encode(dst->encoding());
7163 if (imm8 == 1) {
7164 emit_int8((unsigned char)0xD1);
7165 emit_int8((unsigned char)(0xE0 | encode));
7166 } else {
7167 emit_int8((unsigned char)0xC1);
7168 emit_int8((unsigned char)(0xE0 | encode));
7169 emit_int8(imm8);
7170 }
7171 }
7172
7173 void Assembler::shlq(Register dst) {
7174 int encode = prefixq_and_encode(dst->encoding());
7175 emit_int8((unsigned char)0xD3);
7176 emit_int8((unsigned char)(0xE0 | encode));
7177 }
7178
7179 void Assembler::shrq(Register dst, int imm8) {
7180 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7181 int encode = prefixq_and_encode(dst->encoding());
7182 emit_int8((unsigned char)0xC1);
7183 emit_int8((unsigned char)(0xE8 | encode));
7184 emit_int8(imm8);
7185 }
7186
7187 void Assembler::shrq(Register dst) {
7188 int encode = prefixq_and_encode(dst->encoding());
7189 emit_int8((unsigned char)0xD3);
7190 emit_int8(0xE8 | encode);
7191 }
7192
7193 void Assembler::subq(Address dst, int32_t imm32) {
7194 InstructionMark im(this);
7195 prefixq(dst);
7196 emit_arith_operand(0x81, rbp, dst, imm32);
7197 }
7198
7199 void Assembler::subq(Address dst, Register src) {
7200 InstructionMark im(this);
7201 prefixq(dst, src);
7202 emit_int8(0x29);
7203 emit_operand(src, dst);
7204 }
7205
7206 void Assembler::subq(Register dst, int32_t imm32) {
7207 (void) prefixq_and_encode(dst->encoding());
7208 emit_arith(0x81, 0xE8, dst, imm32);
7209 }
7210
7211 // Force generation of a 4 byte immediate value even if it fits into 8bit
7212 void Assembler::subq_imm32(Register dst, int32_t imm32) {
7213 (void) prefixq_and_encode(dst->encoding());
7214 emit_arith_imm32(0x81, 0xE8, dst, imm32);
7215 }
7216
7217 void Assembler::subq(Register dst, Address src) {
7218 InstructionMark im(this);
7219 prefixq(src, dst);
7220 emit_int8(0x2B);
7221 emit_operand(dst, src);
7222 }
7223
7224 void Assembler::subq(Register dst, Register src) {
7225 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7226 emit_arith(0x2B, 0xC0, dst, src);
7227 }
7228
7229 void Assembler::testq(Register dst, int32_t imm32) {
7230 // not using emit_arith because test
7231 // doesn't support sign-extension of
7232 // 8bit operands
7233 int encode = dst->encoding();
7234 if (encode == 0) {
7235 prefix(REX_W);
7236 emit_int8((unsigned char)0xA9);
7237 } else {
7238 encode = prefixq_and_encode(encode);
7239 emit_int8((unsigned char)0xF7);
7240 emit_int8((unsigned char)(0xC0 | encode));
7241 }
7242 emit_int32(imm32);
7243 }
7244
7245 void Assembler::testq(Register dst, Register src) {
7246 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7247 emit_arith(0x85, 0xC0, dst, src);
7248 }
7249
7250 void Assembler::xaddq(Address dst, Register src) {
7251 InstructionMark im(this);
7252 prefixq(dst, src);
7253 emit_int8(0x0F);
7254 emit_int8((unsigned char)0xC1);
7255 emit_operand(src, dst);
7256 }
7257
7258 void Assembler::xchgq(Register dst, Address src) {
7259 InstructionMark im(this);
7260 prefixq(src, dst);
7261 emit_int8((unsigned char)0x87);
7262 emit_operand(dst, src);
7263 }
7264
7265 void Assembler::xchgq(Register dst, Register src) {
7266 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7267 emit_int8((unsigned char)0x87);
7268 emit_int8((unsigned char)(0xc0 | encode));
7269 }
7270
7271 void Assembler::xorq(Register dst, Register src) {
7272 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7273 emit_arith(0x33, 0xC0, dst, src);
7274 }
7275
7276 void Assembler::xorq(Register dst, Address src) {
7277 InstructionMark im(this);
7278 prefixq(src, dst);
7279 emit_int8(0x33);
7280 emit_operand(dst, src);
7281 }
7282
7283 #endif // !LP64