src/cpu/x86/vm/assembler_x86.cpp

*** 2892,2901 ****
--- 2892,2910 ----
    emit_int8(0x16);
    emit_int8((unsigned char)(0xC0 | encode));
    emit_int8(imm8);
  }
  
+ void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
+   assert(VM_Version::supports_sse2(), "");
+   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
+                                       false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
+   emit_int8(0x15);
+   emit_int8((unsigned char)(0xC0 | encode));
+   emit_int8(imm8);
+ }
+ 
  void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
    assert(VM_Version::supports_sse4_1(), "");
    int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
                                        false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
    emit_int8(0x22);
*** 2910,2919 ****
--- 2919,2937 ----
    emit_int8(0x22);
    emit_int8((unsigned char)(0xC0 | encode));
    emit_int8(imm8);
  }
  
+ void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
+   assert(VM_Version::supports_sse2(), "");
+   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, true, VEX_OPCODE_0F,
+                                       false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
+   emit_int8((unsigned char)0xC4);
+   emit_int8((unsigned char)(0xC0 | encode));
+   emit_int8(imm8);
+ }
+ 
  void Assembler::pmovzxbw(XMMRegister dst, Address src) {
    assert(VM_Version::supports_sse4_1(), "");
    if (VM_Version::supports_evex()) {
      tuple_type = EVEX_HVM;
    }
*** 3897,3906 ****
--- 3915,3933 ----
    } else {
      emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
    }
  }
  
+ void Assembler::mulpd(XMMRegister dst, Address src) {
+   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+   if (VM_Version::supports_evex()) {
+     emit_simd_arith_q(0x59, dst, src, VEX_SIMD_66);
+   } else {
+     emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
+   }
+ }
+ 
  void Assembler::mulps(XMMRegister dst, XMMRegister src) {
    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
    emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE);
  }
  
*** 4056,4065 ****
--- 4083,4110 ----
    }
    emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector_len,
                   (VM_Version::supports_avx512dq() == false));
  }
  
+ void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
+   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+   if (VM_Version::supports_evex()) {
+     emit_simd_arith_q(0x15, dst, src, VEX_SIMD_66);
+   } else {
+     emit_simd_arith(0x15, dst, src, VEX_SIMD_66);
+   }
+ }
+ 
+ void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
+   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+   if (VM_Version::supports_evex()) {
+     emit_simd_arith_q(0x14, dst, src, VEX_SIMD_66);
+   } else {
+     emit_simd_arith(0x14, dst, src, VEX_SIMD_66);
+   }
+ }
+ 
  void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
    if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
      emit_simd_arith_q(0x57, dst, src, VEX_SIMD_66);
    } else {
*** 4674,4683 ****
--- 4719,4737 ----
  void Assembler::pand(XMMRegister dst, XMMRegister src) {
    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
    emit_simd_arith(0xDB, dst, src, VEX_SIMD_66);
  }
  
+ void Assembler::pandn(XMMRegister dst, XMMRegister src) {
+   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+   if (VM_Version::supports_evex()) {
+     emit_simd_arith_q(0xDF, dst, src, VEX_SIMD_66);
+   } else {
+     emit_simd_arith(0xDF, dst, src, VEX_SIMD_66);
+   }
+ }
+ 
  void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
    assert(UseAVX > 0, "requires some form of AVX");
    emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector_len);
  }