1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "compiler/disassembler.hpp"
29 #include "gc/shared/cardTableModRefBS.hpp"
30 #include "gc/shared/collectedHeap.inline.hpp"
31 #include "interpreter/interpreter.hpp"
32 #include "memory/resourceArea.hpp"
33 #include "memory/universe.hpp"
34 #include "prims/methodHandles.hpp"
35 #include "runtime/biasedLocking.hpp"
36 #include "runtime/interfaceSupport.hpp"
37 #include "runtime/objectMonitor.hpp"
38 #include "runtime/os.hpp"
39 #include "runtime/sharedRuntime.hpp"
40 #include "runtime/stubRoutines.hpp"
41 #include "utilities/macros.hpp"
42 #if INCLUDE_ALL_GCS
43 #include "gc/g1/g1CollectedHeap.inline.hpp"
44 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
45 #include "gc/g1/heapRegion.hpp"
46 #endif // INCLUDE_ALL_GCS
47
48 #ifdef PRODUCT
49 #define BLOCK_COMMENT(str) /* nothing */
50 #define STOP(error) stop(error)
51 #else
52 #define BLOCK_COMMENT(str) block_comment(str)
53 #define STOP(error) block_comment(error); stop(error)
54 #endif
55
56 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
57
58 PRAGMA_FORMAT_MUTE_WARNINGS_FOR_GCC
59
60 #ifdef ASSERT
61 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
62 #endif
63
64 static Assembler::Condition reverse[] = {
65 Assembler::noOverflow /* overflow = 0x0 */ ,
66 Assembler::overflow /* noOverflow = 0x1 */ ,
67 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
68 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
69 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
70 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
71 Assembler::above /* belowEqual = 0x6 */ ,
72 Assembler::belowEqual /* above = 0x7 */ ,
73 Assembler::positive /* negative = 0x8 */ ,
74 Assembler::negative /* positive = 0x9 */ ,
75 Assembler::noParity /* parity = 0xa */ ,
76 Assembler::parity /* noParity = 0xb */ ,
77 Assembler::greaterEqual /* less = 0xc */ ,
78 Assembler::less /* greaterEqual = 0xd */ ,
79 Assembler::greater /* lessEqual = 0xe */ ,
80 Assembler::lessEqual /* greater = 0xf, */
81
82 };
83
84
85 // Implementation of MacroAssembler
86
87 // First all the versions that have distinct versions depending on 32/64 bit
88 // Unless the difference is trivial (1 line or so).
89
90 #ifndef _LP64
91
92 // 32bit versions
93
94 Address MacroAssembler::as_Address(AddressLiteral adr) {
95 return Address(adr.target(), adr.rspec());
96 }
97
98 Address MacroAssembler::as_Address(ArrayAddress adr) {
99 return Address::make_array(adr);
100 }
101
102 void MacroAssembler::call_VM_leaf_base(address entry_point,
103 int number_of_arguments) {
104 call(RuntimeAddress(entry_point));
105 increment(rsp, number_of_arguments * wordSize);
106 }
107
108 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
109 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
110 }
111
112 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
113 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
114 }
115
116 void MacroAssembler::cmpoop(Address src1, jobject obj) {
117 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
118 }
119
120 void MacroAssembler::cmpoop(Register src1, jobject obj) {
121 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
122 }
123
124 void MacroAssembler::extend_sign(Register hi, Register lo) {
125 // According to Intel Doc. AP-526, "Integer Divide", p.18.
126 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
127 cdql();
128 } else {
129 movl(hi, lo);
130 sarl(hi, 31);
131 }
132 }
133
134 void MacroAssembler::jC2(Register tmp, Label& L) {
135 // set parity bit if FPU flag C2 is set (via rax)
136 save_rax(tmp);
137 fwait(); fnstsw_ax();
138 sahf();
139 restore_rax(tmp);
140 // branch
141 jcc(Assembler::parity, L);
142 }
143
144 void MacroAssembler::jnC2(Register tmp, Label& L) {
145 // set parity bit if FPU flag C2 is set (via rax)
146 save_rax(tmp);
147 fwait(); fnstsw_ax();
148 sahf();
149 restore_rax(tmp);
150 // branch
151 jcc(Assembler::noParity, L);
152 }
153
154 // 32bit can do a case table jump in one instruction but we no longer allow the base
155 // to be installed in the Address class
156 void MacroAssembler::jump(ArrayAddress entry) {
157 jmp(as_Address(entry));
158 }
159
160 // Note: y_lo will be destroyed
161 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
162 // Long compare for Java (semantics as described in JVM spec.)
163 Label high, low, done;
164
165 cmpl(x_hi, y_hi);
166 jcc(Assembler::less, low);
167 jcc(Assembler::greater, high);
168 // x_hi is the return register
169 xorl(x_hi, x_hi);
170 cmpl(x_lo, y_lo);
171 jcc(Assembler::below, low);
172 jcc(Assembler::equal, done);
173
174 bind(high);
175 xorl(x_hi, x_hi);
176 increment(x_hi);
177 jmp(done);
178
179 bind(low);
180 xorl(x_hi, x_hi);
181 decrementl(x_hi);
182
183 bind(done);
184 }
185
186 void MacroAssembler::lea(Register dst, AddressLiteral src) {
187 mov_literal32(dst, (int32_t)src.target(), src.rspec());
188 }
189
190 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
191 // leal(dst, as_Address(adr));
192 // see note in movl as to why we must use a move
193 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
194 }
195
196 void MacroAssembler::leave() {
197 mov(rsp, rbp);
198 pop(rbp);
199 }
200
201 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
202 // Multiplication of two Java long values stored on the stack
203 // as illustrated below. Result is in rdx:rax.
204 //
205 // rsp ---> [ ?? ] \ \
206 // .... | y_rsp_offset |
207 // [ y_lo ] / (in bytes) | x_rsp_offset
208 // [ y_hi ] | (in bytes)
209 // .... |
210 // [ x_lo ] /
211 // [ x_hi ]
212 // ....
213 //
214 // Basic idea: lo(result) = lo(x_lo * y_lo)
215 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
216 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
217 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
218 Label quick;
219 // load x_hi, y_hi and check if quick
220 // multiplication is possible
221 movl(rbx, x_hi);
222 movl(rcx, y_hi);
223 movl(rax, rbx);
224 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
225 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
226 // do full multiplication
227 // 1st step
228 mull(y_lo); // x_hi * y_lo
229 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
230 // 2nd step
231 movl(rax, x_lo);
232 mull(rcx); // x_lo * y_hi
233 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
234 // 3rd step
235 bind(quick); // note: rbx, = 0 if quick multiply!
236 movl(rax, x_lo);
237 mull(y_lo); // x_lo * y_lo
238 addl(rdx, rbx); // correct hi(x_lo * y_lo)
239 }
240
241 void MacroAssembler::lneg(Register hi, Register lo) {
242 negl(lo);
243 adcl(hi, 0);
244 negl(hi);
245 }
246
247 void MacroAssembler::lshl(Register hi, Register lo) {
248 // Java shift left long support (semantics as described in JVM spec., p.305)
249 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
250 // shift value is in rcx !
251 assert(hi != rcx, "must not use rcx");
252 assert(lo != rcx, "must not use rcx");
253 const Register s = rcx; // shift count
254 const int n = BitsPerWord;
255 Label L;
256 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
257 cmpl(s, n); // if (s < n)
258 jcc(Assembler::less, L); // else (s >= n)
259 movl(hi, lo); // x := x << n
260 xorl(lo, lo);
261 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
262 bind(L); // s (mod n) < n
263 shldl(hi, lo); // x := x << s
264 shll(lo);
265 }
266
267
268 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
269 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
270 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
271 assert(hi != rcx, "must not use rcx");
272 assert(lo != rcx, "must not use rcx");
273 const Register s = rcx; // shift count
274 const int n = BitsPerWord;
275 Label L;
276 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
277 cmpl(s, n); // if (s < n)
278 jcc(Assembler::less, L); // else (s >= n)
279 movl(lo, hi); // x := x >> n
280 if (sign_extension) sarl(hi, 31);
281 else xorl(hi, hi);
282 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
283 bind(L); // s (mod n) < n
284 shrdl(lo, hi); // x := x >> s
285 if (sign_extension) sarl(hi);
286 else shrl(hi);
287 }
288
289 void MacroAssembler::movoop(Register dst, jobject obj) {
290 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
291 }
292
293 void MacroAssembler::movoop(Address dst, jobject obj) {
294 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
295 }
296
297 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
298 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
299 }
300
301 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
302 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
303 }
304
305 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
306 // scratch register is not used,
307 // it is defined to match parameters of 64-bit version of this method.
308 if (src.is_lval()) {
309 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
310 } else {
311 movl(dst, as_Address(src));
312 }
313 }
314
315 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
316 movl(as_Address(dst), src);
317 }
318
319 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
320 movl(dst, as_Address(src));
321 }
322
323 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
324 void MacroAssembler::movptr(Address dst, intptr_t src) {
325 movl(dst, src);
326 }
327
328
329 void MacroAssembler::pop_callee_saved_registers() {
330 pop(rcx);
331 pop(rdx);
332 pop(rdi);
333 pop(rsi);
334 }
335
336 void MacroAssembler::pop_fTOS() {
337 fld_d(Address(rsp, 0));
338 addl(rsp, 2 * wordSize);
339 }
340
341 void MacroAssembler::push_callee_saved_registers() {
342 push(rsi);
343 push(rdi);
344 push(rdx);
345 push(rcx);
346 }
347
348 void MacroAssembler::push_fTOS() {
349 subl(rsp, 2 * wordSize);
350 fstp_d(Address(rsp, 0));
351 }
352
353
354 void MacroAssembler::pushoop(jobject obj) {
355 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
356 }
357
358 void MacroAssembler::pushklass(Metadata* obj) {
359 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
360 }
361
362 void MacroAssembler::pushptr(AddressLiteral src) {
363 if (src.is_lval()) {
364 push_literal32((int32_t)src.target(), src.rspec());
365 } else {
366 pushl(as_Address(src));
367 }
368 }
369
370 void MacroAssembler::set_word_if_not_zero(Register dst) {
371 xorl(dst, dst);
372 set_byte_if_not_zero(dst);
373 }
374
375 static void pass_arg0(MacroAssembler* masm, Register arg) {
376 masm->push(arg);
377 }
378
379 static void pass_arg1(MacroAssembler* masm, Register arg) {
380 masm->push(arg);
381 }
382
383 static void pass_arg2(MacroAssembler* masm, Register arg) {
384 masm->push(arg);
385 }
386
387 static void pass_arg3(MacroAssembler* masm, Register arg) {
388 masm->push(arg);
389 }
390
391 #ifndef PRODUCT
392 extern "C" void findpc(intptr_t x);
393 #endif
394
395 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
396 // In order to get locks to work, we need to fake a in_VM state
397 JavaThread* thread = JavaThread::current();
398 JavaThreadState saved_state = thread->thread_state();
399 thread->set_thread_state(_thread_in_vm);
400 if (ShowMessageBoxOnError) {
401 JavaThread* thread = JavaThread::current();
402 JavaThreadState saved_state = thread->thread_state();
403 thread->set_thread_state(_thread_in_vm);
404 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
405 ttyLocker ttyl;
406 BytecodeCounter::print();
407 }
408 // To see where a verify_oop failed, get $ebx+40/X for this frame.
409 // This is the value of eip which points to where verify_oop will return.
410 if (os::message_box(msg, "Execution stopped, print registers?")) {
411 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
412 BREAKPOINT;
413 }
414 } else {
415 ttyLocker ttyl;
416 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
417 }
418 // Don't assert holding the ttyLock
419 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
420 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
421 }
422
423 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
424 ttyLocker ttyl;
425 FlagSetting fs(Debugging, true);
426 tty->print_cr("eip = 0x%08x", eip);
427 #ifndef PRODUCT
428 if ((WizardMode || Verbose) && PrintMiscellaneous) {
429 tty->cr();
430 findpc(eip);
431 tty->cr();
432 }
433 #endif
434 #define PRINT_REG(rax) \
435 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
436 PRINT_REG(rax);
437 PRINT_REG(rbx);
438 PRINT_REG(rcx);
439 PRINT_REG(rdx);
440 PRINT_REG(rdi);
441 PRINT_REG(rsi);
442 PRINT_REG(rbp);
443 PRINT_REG(rsp);
444 #undef PRINT_REG
445 // Print some words near top of staack.
446 int* dump_sp = (int*) rsp;
447 for (int col1 = 0; col1 < 8; col1++) {
448 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
449 os::print_location(tty, *dump_sp++);
450 }
451 for (int row = 0; row < 16; row++) {
452 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
453 for (int col = 0; col < 8; col++) {
454 tty->print(" 0x%08x", *dump_sp++);
455 }
456 tty->cr();
457 }
458 // Print some instructions around pc:
459 Disassembler::decode((address)eip-64, (address)eip);
460 tty->print_cr("--------");
461 Disassembler::decode((address)eip, (address)eip+32);
462 }
463
464 void MacroAssembler::stop(const char* msg) {
465 ExternalAddress message((address)msg);
466 // push address of message
467 pushptr(message.addr());
468 { Label L; call(L, relocInfo::none); bind(L); } // push eip
469 pusha(); // push registers
470 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
471 hlt();
472 }
473
474 void MacroAssembler::warn(const char* msg) {
475 push_CPU_state();
476
477 ExternalAddress message((address) msg);
478 // push address of message
479 pushptr(message.addr());
480
481 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
482 addl(rsp, wordSize); // discard argument
483 pop_CPU_state();
484 }
485
486 void MacroAssembler::print_state() {
487 { Label L; call(L, relocInfo::none); bind(L); } // push eip
488 pusha(); // push registers
489
490 push_CPU_state();
491 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
492 pop_CPU_state();
493
494 popa();
495 addl(rsp, wordSize);
496 }
497
498 #else // _LP64
499
500 // 64 bit versions
501
502 Address MacroAssembler::as_Address(AddressLiteral adr) {
503 // amd64 always does this as a pc-rel
504 // we can be absolute or disp based on the instruction type
505 // jmp/call are displacements others are absolute
506 assert(!adr.is_lval(), "must be rval");
507 assert(reachable(adr), "must be");
508 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
509
510 }
511
512 Address MacroAssembler::as_Address(ArrayAddress adr) {
513 AddressLiteral base = adr.base();
514 lea(rscratch1, base);
515 Address index = adr.index();
516 assert(index._disp == 0, "must not have disp"); // maybe it can?
517 Address array(rscratch1, index._index, index._scale, index._disp);
518 return array;
519 }
520
521 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
522 Label L, E;
523
524 #ifdef _WIN64
525 // Windows always allocates space for it's register args
526 assert(num_args <= 4, "only register arguments supported");
527 subq(rsp, frame::arg_reg_save_area_bytes);
528 #endif
529
530 // Align stack if necessary
531 testl(rsp, 15);
532 jcc(Assembler::zero, L);
533
534 subq(rsp, 8);
535 {
536 call(RuntimeAddress(entry_point));
537 }
538 addq(rsp, 8);
539 jmp(E);
540
541 bind(L);
542 {
543 call(RuntimeAddress(entry_point));
544 }
545
546 bind(E);
547
548 #ifdef _WIN64
549 // restore stack pointer
550 addq(rsp, frame::arg_reg_save_area_bytes);
551 #endif
552
553 }
554
555 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
556 assert(!src2.is_lval(), "should use cmpptr");
557
558 if (reachable(src2)) {
559 cmpq(src1, as_Address(src2));
560 } else {
561 lea(rscratch1, src2);
562 Assembler::cmpq(src1, Address(rscratch1, 0));
563 }
564 }
565
566 int MacroAssembler::corrected_idivq(Register reg) {
567 // Full implementation of Java ldiv and lrem; checks for special
568 // case as described in JVM spec., p.243 & p.271. The function
569 // returns the (pc) offset of the idivl instruction - may be needed
570 // for implicit exceptions.
571 //
572 // normal case special case
573 //
574 // input : rax: dividend min_long
575 // reg: divisor (may not be eax/edx) -1
576 //
577 // output: rax: quotient (= rax idiv reg) min_long
578 // rdx: remainder (= rax irem reg) 0
579 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
580 static const int64_t min_long = 0x8000000000000000;
581 Label normal_case, special_case;
582
583 // check for special case
584 cmp64(rax, ExternalAddress((address) &min_long));
585 jcc(Assembler::notEqual, normal_case);
586 xorl(rdx, rdx); // prepare rdx for possible special case (where
587 // remainder = 0)
588 cmpq(reg, -1);
589 jcc(Assembler::equal, special_case);
590
591 // handle normal case
592 bind(normal_case);
593 cdqq();
594 int idivq_offset = offset();
595 idivq(reg);
596
597 // normal and special case exit
598 bind(special_case);
599
600 return idivq_offset;
601 }
602
603 void MacroAssembler::decrementq(Register reg, int value) {
604 if (value == min_jint) { subq(reg, value); return; }
605 if (value < 0) { incrementq(reg, -value); return; }
606 if (value == 0) { ; return; }
607 if (value == 1 && UseIncDec) { decq(reg) ; return; }
608 /* else */ { subq(reg, value) ; return; }
609 }
610
611 void MacroAssembler::decrementq(Address dst, int value) {
612 if (value == min_jint) { subq(dst, value); return; }
613 if (value < 0) { incrementq(dst, -value); return; }
614 if (value == 0) { ; return; }
615 if (value == 1 && UseIncDec) { decq(dst) ; return; }
616 /* else */ { subq(dst, value) ; return; }
617 }
618
619 void MacroAssembler::incrementq(AddressLiteral dst) {
620 if (reachable(dst)) {
621 incrementq(as_Address(dst));
622 } else {
623 lea(rscratch1, dst);
624 incrementq(Address(rscratch1, 0));
625 }
626 }
627
628 void MacroAssembler::incrementq(Register reg, int value) {
629 if (value == min_jint) { addq(reg, value); return; }
630 if (value < 0) { decrementq(reg, -value); return; }
631 if (value == 0) { ; return; }
632 if (value == 1 && UseIncDec) { incq(reg) ; return; }
633 /* else */ { addq(reg, value) ; return; }
634 }
635
636 void MacroAssembler::incrementq(Address dst, int value) {
637 if (value == min_jint) { addq(dst, value); return; }
638 if (value < 0) { decrementq(dst, -value); return; }
639 if (value == 0) { ; return; }
640 if (value == 1 && UseIncDec) { incq(dst) ; return; }
641 /* else */ { addq(dst, value) ; return; }
642 }
643
644 // 32bit can do a case table jump in one instruction but we no longer allow the base
645 // to be installed in the Address class
646 void MacroAssembler::jump(ArrayAddress entry) {
647 lea(rscratch1, entry.base());
648 Address dispatch = entry.index();
649 assert(dispatch._base == noreg, "must be");
650 dispatch._base = rscratch1;
651 jmp(dispatch);
652 }
653
654 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
655 ShouldNotReachHere(); // 64bit doesn't use two regs
656 cmpq(x_lo, y_lo);
657 }
658
659 void MacroAssembler::lea(Register dst, AddressLiteral src) {
660 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
661 }
662
663 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
664 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
665 movptr(dst, rscratch1);
666 }
667
668 void MacroAssembler::leave() {
669 // %%% is this really better? Why not on 32bit too?
670 emit_int8((unsigned char)0xC9); // LEAVE
671 }
672
673 void MacroAssembler::lneg(Register hi, Register lo) {
674 ShouldNotReachHere(); // 64bit doesn't use two regs
675 negq(lo);
676 }
677
678 void MacroAssembler::movoop(Register dst, jobject obj) {
679 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
680 }
681
682 void MacroAssembler::movoop(Address dst, jobject obj) {
683 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
684 movq(dst, rscratch1);
685 }
686
687 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
688 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
689 }
690
691 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
692 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
693 movq(dst, rscratch1);
694 }
695
696 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
697 if (src.is_lval()) {
698 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
699 } else {
700 if (reachable(src)) {
701 movq(dst, as_Address(src));
702 } else {
703 lea(scratch, src);
704 movq(dst, Address(scratch, 0));
705 }
706 }
707 }
708
709 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
710 movq(as_Address(dst), src);
711 }
712
713 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
714 movq(dst, as_Address(src));
715 }
716
717 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
718 void MacroAssembler::movptr(Address dst, intptr_t src) {
719 mov64(rscratch1, src);
720 movq(dst, rscratch1);
721 }
722
723 // These are mostly for initializing NULL
724 void MacroAssembler::movptr(Address dst, int32_t src) {
725 movslq(dst, src);
726 }
727
728 void MacroAssembler::movptr(Register dst, int32_t src) {
729 mov64(dst, (intptr_t)src);
730 }
731
732 void MacroAssembler::pushoop(jobject obj) {
733 movoop(rscratch1, obj);
734 push(rscratch1);
735 }
736
737 void MacroAssembler::pushklass(Metadata* obj) {
738 mov_metadata(rscratch1, obj);
739 push(rscratch1);
740 }
741
742 void MacroAssembler::pushptr(AddressLiteral src) {
743 lea(rscratch1, src);
744 if (src.is_lval()) {
745 push(rscratch1);
746 } else {
747 pushq(Address(rscratch1, 0));
748 }
749 }
750
751 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
752 bool clear_pc) {
753 // we must set sp to zero to clear frame
754 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
755 // must clear fp, so that compiled frames are not confused; it is
756 // possible that we need it only for debugging
757 if (clear_fp) {
758 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
759 }
760
761 if (clear_pc) {
762 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
763 }
764 }
765
766 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
767 Register last_java_fp,
768 address last_java_pc) {
769 // determine last_java_sp register
770 if (!last_java_sp->is_valid()) {
771 last_java_sp = rsp;
772 }
773
774 // last_java_fp is optional
775 if (last_java_fp->is_valid()) {
776 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
777 last_java_fp);
778 }
779
780 // last_java_pc is optional
781 if (last_java_pc != NULL) {
782 Address java_pc(r15_thread,
783 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
784 lea(rscratch1, InternalAddress(last_java_pc));
785 movptr(java_pc, rscratch1);
786 }
787
788 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
789 }
790
791 static void pass_arg0(MacroAssembler* masm, Register arg) {
792 if (c_rarg0 != arg ) {
793 masm->mov(c_rarg0, arg);
794 }
795 }
796
797 static void pass_arg1(MacroAssembler* masm, Register arg) {
798 if (c_rarg1 != arg ) {
799 masm->mov(c_rarg1, arg);
800 }
801 }
802
803 static void pass_arg2(MacroAssembler* masm, Register arg) {
804 if (c_rarg2 != arg ) {
805 masm->mov(c_rarg2, arg);
806 }
807 }
808
809 static void pass_arg3(MacroAssembler* masm, Register arg) {
810 if (c_rarg3 != arg ) {
811 masm->mov(c_rarg3, arg);
812 }
813 }
814
815 void MacroAssembler::stop(const char* msg) {
816 address rip = pc();
817 pusha(); // get regs on stack
818 lea(c_rarg0, ExternalAddress((address) msg));
819 lea(c_rarg1, InternalAddress(rip));
820 movq(c_rarg2, rsp); // pass pointer to regs array
821 andq(rsp, -16); // align stack as required by ABI
822 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
823 hlt();
824 }
825
826 void MacroAssembler::warn(const char* msg) {
827 push(rbp);
828 movq(rbp, rsp);
829 andq(rsp, -16); // align stack as required by push_CPU_state and call
830 push_CPU_state(); // keeps alignment at 16 bytes
831 lea(c_rarg0, ExternalAddress((address) msg));
832 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
833 pop_CPU_state();
834 mov(rsp, rbp);
835 pop(rbp);
836 }
837
838 void MacroAssembler::print_state() {
839 address rip = pc();
840 pusha(); // get regs on stack
841 push(rbp);
842 movq(rbp, rsp);
843 andq(rsp, -16); // align stack as required by push_CPU_state and call
844 push_CPU_state(); // keeps alignment at 16 bytes
845
846 lea(c_rarg0, InternalAddress(rip));
847 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
848 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
849
850 pop_CPU_state();
851 mov(rsp, rbp);
852 pop(rbp);
853 popa();
854 }
855
856 #ifndef PRODUCT
857 extern "C" void findpc(intptr_t x);
858 #endif
859
860 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
861 // In order to get locks to work, we need to fake a in_VM state
862 if (ShowMessageBoxOnError) {
863 JavaThread* thread = JavaThread::current();
864 JavaThreadState saved_state = thread->thread_state();
865 thread->set_thread_state(_thread_in_vm);
866 #ifndef PRODUCT
867 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
868 ttyLocker ttyl;
869 BytecodeCounter::print();
870 }
871 #endif
872 // To see where a verify_oop failed, get $ebx+40/X for this frame.
873 // XXX correct this offset for amd64
874 // This is the value of eip which points to where verify_oop will return.
875 if (os::message_box(msg, "Execution stopped, print registers?")) {
876 print_state64(pc, regs);
877 BREAKPOINT;
878 assert(false, "start up GDB");
879 }
880 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
881 } else {
882 ttyLocker ttyl;
883 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
884 msg);
885 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
886 }
887 }
888
889 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
890 ttyLocker ttyl;
891 FlagSetting fs(Debugging, true);
892 tty->print_cr("rip = 0x%016lx", pc);
893 #ifndef PRODUCT
894 tty->cr();
895 findpc(pc);
896 tty->cr();
897 #endif
898 #define PRINT_REG(rax, value) \
899 { tty->print("%s = ", #rax); os::print_location(tty, value); }
900 PRINT_REG(rax, regs[15]);
901 PRINT_REG(rbx, regs[12]);
902 PRINT_REG(rcx, regs[14]);
903 PRINT_REG(rdx, regs[13]);
904 PRINT_REG(rdi, regs[8]);
905 PRINT_REG(rsi, regs[9]);
906 PRINT_REG(rbp, regs[10]);
907 PRINT_REG(rsp, regs[11]);
908 PRINT_REG(r8 , regs[7]);
909 PRINT_REG(r9 , regs[6]);
910 PRINT_REG(r10, regs[5]);
911 PRINT_REG(r11, regs[4]);
912 PRINT_REG(r12, regs[3]);
913 PRINT_REG(r13, regs[2]);
914 PRINT_REG(r14, regs[1]);
915 PRINT_REG(r15, regs[0]);
916 #undef PRINT_REG
917 // Print some words near top of staack.
918 int64_t* rsp = (int64_t*) regs[11];
919 int64_t* dump_sp = rsp;
920 for (int col1 = 0; col1 < 8; col1++) {
921 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
922 os::print_location(tty, *dump_sp++);
923 }
924 for (int row = 0; row < 25; row++) {
925 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
926 for (int col = 0; col < 4; col++) {
927 tty->print(" 0x%016lx", *dump_sp++);
928 }
929 tty->cr();
930 }
931 // Print some instructions around pc:
932 Disassembler::decode((address)pc-64, (address)pc);
933 tty->print_cr("--------");
934 Disassembler::decode((address)pc, (address)pc+32);
935 }
936
937 #endif // _LP64
938
939 // Now versions that are common to 32/64 bit
940
941 void MacroAssembler::addptr(Register dst, int32_t imm32) {
942 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
943 }
944
945 void MacroAssembler::addptr(Register dst, Register src) {
946 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
947 }
948
949 void MacroAssembler::addptr(Address dst, Register src) {
950 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
951 }
952
953 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
954 if (reachable(src)) {
955 Assembler::addsd(dst, as_Address(src));
956 } else {
957 lea(rscratch1, src);
958 Assembler::addsd(dst, Address(rscratch1, 0));
959 }
960 }
961
962 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
963 if (reachable(src)) {
964 addss(dst, as_Address(src));
965 } else {
966 lea(rscratch1, src);
967 addss(dst, Address(rscratch1, 0));
968 }
969 }
970
971 void MacroAssembler::align(int modulus) {
972 if (offset() % modulus != 0) {
973 nop(modulus - (offset() % modulus));
974 }
975 }
976
977 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
978 // Used in sign-masking with aligned address.
979 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
980 if (reachable(src)) {
981 Assembler::andpd(dst, as_Address(src));
982 } else {
983 lea(rscratch1, src);
984 Assembler::andpd(dst, Address(rscratch1, 0));
985 }
986 }
987
988 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
989 // Used in sign-masking with aligned address.
990 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
991 if (reachable(src)) {
992 Assembler::andps(dst, as_Address(src));
993 } else {
994 lea(rscratch1, src);
995 Assembler::andps(dst, Address(rscratch1, 0));
996 }
997 }
998
999 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1000 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1001 }
1002
1003 void MacroAssembler::atomic_incl(Address counter_addr) {
1004 if (os::is_MP())
1005 lock();
1006 incrementl(counter_addr);
1007 }
1008
1009 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1010 if (reachable(counter_addr)) {
1011 atomic_incl(as_Address(counter_addr));
1012 } else {
1013 lea(scr, counter_addr);
1014 atomic_incl(Address(scr, 0));
1015 }
1016 }
1017
1018 #ifdef _LP64
1019 void MacroAssembler::atomic_incq(Address counter_addr) {
1020 if (os::is_MP())
1021 lock();
1022 incrementq(counter_addr);
1023 }
1024
1025 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1026 if (reachable(counter_addr)) {
1027 atomic_incq(as_Address(counter_addr));
1028 } else {
1029 lea(scr, counter_addr);
1030 atomic_incq(Address(scr, 0));
1031 }
1032 }
1033 #endif
1034
1035 // Writes to stack successive pages until offset reached to check for
1036 // stack overflow + shadow pages. This clobbers tmp.
1037 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1038 movptr(tmp, rsp);
1039 // Bang stack for total size given plus shadow page size.
1040 // Bang one page at a time because large size can bang beyond yellow and
1041 // red zones.
1042 Label loop;
1043 bind(loop);
1044 movl(Address(tmp, (-os::vm_page_size())), size );
1045 subptr(tmp, os::vm_page_size());
1046 subl(size, os::vm_page_size());
1047 jcc(Assembler::greater, loop);
1048
1049 // Bang down shadow pages too.
1050 // At this point, (tmp-0) is the last address touched, so don't
1051 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1052 // was post-decremented.) Skip this address by starting at i=1, and
1053 // touch a few more pages below. N.B. It is important to touch all
1054 // the way down to and including i=StackShadowPages.
1055 for (int i = 1; i < StackShadowPages; i++) {
1056 // this could be any sized move but this is can be a debugging crumb
1057 // so the bigger the better.
1058 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1059 }
1060 }
1061
1062 int MacroAssembler::biased_locking_enter(Register lock_reg,
1063 Register obj_reg,
1064 Register swap_reg,
1065 Register tmp_reg,
1066 bool swap_reg_contains_mark,
1067 Label& done,
1068 Label* slow_case,
1069 BiasedLockingCounters* counters) {
1070 assert(UseBiasedLocking, "why call this otherwise?");
1071 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1072 assert(tmp_reg != noreg, "tmp_reg must be supplied");
1073 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1074 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1075 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1076 Address saved_mark_addr(lock_reg, 0);
1077
1078 if (PrintBiasedLockingStatistics && counters == NULL) {
1079 counters = BiasedLocking::counters();
1080 }
1081 // Biased locking
1082 // See whether the lock is currently biased toward our thread and
1083 // whether the epoch is still valid
1084 // Note that the runtime guarantees sufficient alignment of JavaThread
1085 // pointers to allow age to be placed into low bits
1086 // First check to see whether biasing is even enabled for this object
1087 Label cas_label;
1088 int null_check_offset = -1;
1089 if (!swap_reg_contains_mark) {
1090 null_check_offset = offset();
1091 movptr(swap_reg, mark_addr);
1092 }
1093 movptr(tmp_reg, swap_reg);
1094 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1095 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1096 jcc(Assembler::notEqual, cas_label);
1097 // The bias pattern is present in the object's header. Need to check
1098 // whether the bias owner and the epoch are both still current.
1099 #ifndef _LP64
1100 // Note that because there is no current thread register on x86_32 we
1101 // need to store off the mark word we read out of the object to
1102 // avoid reloading it and needing to recheck invariants below. This
1103 // store is unfortunate but it makes the overall code shorter and
1104 // simpler.
1105 movptr(saved_mark_addr, swap_reg);
1106 #endif
1107 if (swap_reg_contains_mark) {
1108 null_check_offset = offset();
1109 }
1110 load_prototype_header(tmp_reg, obj_reg);
1111 #ifdef _LP64
1112 orptr(tmp_reg, r15_thread);
1113 xorptr(tmp_reg, swap_reg);
1114 Register header_reg = tmp_reg;
1115 #else
1116 xorptr(tmp_reg, swap_reg);
1117 get_thread(swap_reg);
1118 xorptr(swap_reg, tmp_reg);
1119 Register header_reg = swap_reg;
1120 #endif
1121 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1122 if (counters != NULL) {
1123 cond_inc32(Assembler::zero,
1124 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1125 }
1126 jcc(Assembler::equal, done);
1127
1128 Label try_revoke_bias;
1129 Label try_rebias;
1130
1131 // At this point we know that the header has the bias pattern and
1132 // that we are not the bias owner in the current epoch. We need to
1133 // figure out more details about the state of the header in order to
1134 // know what operations can be legally performed on the object's
1135 // header.
1136
1137 // If the low three bits in the xor result aren't clear, that means
1138 // the prototype header is no longer biased and we have to revoke
1139 // the bias on this object.
1140 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1141 jccb(Assembler::notZero, try_revoke_bias);
1142
1143 // Biasing is still enabled for this data type. See whether the
1144 // epoch of the current bias is still valid, meaning that the epoch
1145 // bits of the mark word are equal to the epoch bits of the
1146 // prototype header. (Note that the prototype header's epoch bits
1147 // only change at a safepoint.) If not, attempt to rebias the object
1148 // toward the current thread. Note that we must be absolutely sure
1149 // that the current epoch is invalid in order to do this because
1150 // otherwise the manipulations it performs on the mark word are
1151 // illegal.
1152 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1153 jccb(Assembler::notZero, try_rebias);
1154
1155 // The epoch of the current bias is still valid but we know nothing
1156 // about the owner; it might be set or it might be clear. Try to
1157 // acquire the bias of the object using an atomic operation. If this
1158 // fails we will go in to the runtime to revoke the object's bias.
1159 // Note that we first construct the presumed unbiased header so we
1160 // don't accidentally blow away another thread's valid bias.
1161 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1162 andptr(swap_reg,
1163 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1164 #ifdef _LP64
1165 movptr(tmp_reg, swap_reg);
1166 orptr(tmp_reg, r15_thread);
1167 #else
1168 get_thread(tmp_reg);
1169 orptr(tmp_reg, swap_reg);
1170 #endif
1171 if (os::is_MP()) {
1172 lock();
1173 }
1174 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1175 // If the biasing toward our thread failed, this means that
1176 // another thread succeeded in biasing it toward itself and we
1177 // need to revoke that bias. The revocation will occur in the
1178 // interpreter runtime in the slow case.
1179 if (counters != NULL) {
1180 cond_inc32(Assembler::zero,
1181 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1182 }
1183 if (slow_case != NULL) {
1184 jcc(Assembler::notZero, *slow_case);
1185 }
1186 jmp(done);
1187
1188 bind(try_rebias);
1189 // At this point we know the epoch has expired, meaning that the
1190 // current "bias owner", if any, is actually invalid. Under these
1191 // circumstances _only_, we are allowed to use the current header's
1192 // value as the comparison value when doing the cas to acquire the
1193 // bias in the current epoch. In other words, we allow transfer of
1194 // the bias from one thread to another directly in this situation.
1195 //
1196 // FIXME: due to a lack of registers we currently blow away the age
1197 // bits in this situation. Should attempt to preserve them.
1198 load_prototype_header(tmp_reg, obj_reg);
1199 #ifdef _LP64
1200 orptr(tmp_reg, r15_thread);
1201 #else
1202 get_thread(swap_reg);
1203 orptr(tmp_reg, swap_reg);
1204 movptr(swap_reg, saved_mark_addr);
1205 #endif
1206 if (os::is_MP()) {
1207 lock();
1208 }
1209 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1210 // If the biasing toward our thread failed, then another thread
1211 // succeeded in biasing it toward itself and we need to revoke that
1212 // bias. The revocation will occur in the runtime in the slow case.
1213 if (counters != NULL) {
1214 cond_inc32(Assembler::zero,
1215 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1216 }
1217 if (slow_case != NULL) {
1218 jcc(Assembler::notZero, *slow_case);
1219 }
1220 jmp(done);
1221
1222 bind(try_revoke_bias);
1223 // The prototype mark in the klass doesn't have the bias bit set any
1224 // more, indicating that objects of this data type are not supposed
1225 // to be biased any more. We are going to try to reset the mark of
1226 // this object to the prototype value and fall through to the
1227 // CAS-based locking scheme. Note that if our CAS fails, it means
1228 // that another thread raced us for the privilege of revoking the
1229 // bias of this particular object, so it's okay to continue in the
1230 // normal locking code.
1231 //
1232 // FIXME: due to a lack of registers we currently blow away the age
1233 // bits in this situation. Should attempt to preserve them.
1234 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1235 load_prototype_header(tmp_reg, obj_reg);
1236 if (os::is_MP()) {
1237 lock();
1238 }
1239 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1240 // Fall through to the normal CAS-based lock, because no matter what
1241 // the result of the above CAS, some thread must have succeeded in
1242 // removing the bias bit from the object's header.
1243 if (counters != NULL) {
1244 cond_inc32(Assembler::zero,
1245 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1246 }
1247
1248 bind(cas_label);
1249
1250 return null_check_offset;
1251 }
1252
1253 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1254 assert(UseBiasedLocking, "why call this otherwise?");
1255
1256 // Check for biased locking unlock case, which is a no-op
1257 // Note: we do not have to check the thread ID for two reasons.
1258 // First, the interpreter checks for IllegalMonitorStateException at
1259 // a higher level. Second, if the bias was revoked while we held the
1260 // lock, the object could not be rebiased toward another thread, so
1261 // the bias bit would be clear.
1262 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1263 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1264 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1265 jcc(Assembler::equal, done);
1266 }
1267
1268 #ifdef COMPILER2
1269
1270 #if INCLUDE_RTM_OPT
1271
1272 // Update rtm_counters based on abort status
1273 // input: abort_status
1274 // rtm_counters (RTMLockingCounters*)
1275 // flags are killed
1276 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1277
1278 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1279 if (PrintPreciseRTMLockingStatistics) {
1280 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1281 Label check_abort;
1282 testl(abort_status, (1<<i));
1283 jccb(Assembler::equal, check_abort);
1284 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1285 bind(check_abort);
1286 }
1287 }
1288 }
1289
1290 // Branch if (random & (count-1) != 0), count is 2^n
1291 // tmp, scr and flags are killed
1292 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1293 assert(tmp == rax, "");
1294 assert(scr == rdx, "");
1295 rdtsc(); // modifies EDX:EAX
1296 andptr(tmp, count-1);
1297 jccb(Assembler::notZero, brLabel);
1298 }
1299
1300 // Perform abort ratio calculation, set no_rtm bit if high ratio
1301 // input: rtm_counters_Reg (RTMLockingCounters* address)
1302 // tmpReg, rtm_counters_Reg and flags are killed
1303 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1304 Register rtm_counters_Reg,
1305 RTMLockingCounters* rtm_counters,
1306 Metadata* method_data) {
1307 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1308
1309 if (RTMLockingCalculationDelay > 0) {
1310 // Delay calculation
1311 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1312 testptr(tmpReg, tmpReg);
1313 jccb(Assembler::equal, L_done);
1314 }
1315 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1316 // Aborted transactions = abort_count * 100
1317 // All transactions = total_count * RTMTotalCountIncrRate
1318 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1319
1320 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1321 cmpptr(tmpReg, RTMAbortThreshold);
1322 jccb(Assembler::below, L_check_always_rtm2);
1323 imulptr(tmpReg, tmpReg, 100);
1324
1325 Register scrReg = rtm_counters_Reg;
1326 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1327 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1328 imulptr(scrReg, scrReg, RTMAbortRatio);
1329 cmpptr(tmpReg, scrReg);
1330 jccb(Assembler::below, L_check_always_rtm1);
1331 if (method_data != NULL) {
1332 // set rtm_state to "no rtm" in MDO
1333 mov_metadata(tmpReg, method_data);
1334 if (os::is_MP()) {
1335 lock();
1336 }
1337 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1338 }
1339 jmpb(L_done);
1340 bind(L_check_always_rtm1);
1341 // Reload RTMLockingCounters* address
1342 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1343 bind(L_check_always_rtm2);
1344 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1345 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1346 jccb(Assembler::below, L_done);
1347 if (method_data != NULL) {
1348 // set rtm_state to "always rtm" in MDO
1349 mov_metadata(tmpReg, method_data);
1350 if (os::is_MP()) {
1351 lock();
1352 }
1353 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1354 }
1355 bind(L_done);
1356 }
1357
1358 // Update counters and perform abort ratio calculation
1359 // input: abort_status_Reg
1360 // rtm_counters_Reg, flags are killed
1361 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1362 Register rtm_counters_Reg,
1363 RTMLockingCounters* rtm_counters,
1364 Metadata* method_data,
1365 bool profile_rtm) {
1366
1367 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1368 // update rtm counters based on rax value at abort
1369 // reads abort_status_Reg, updates flags
1370 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1371 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1372 if (profile_rtm) {
1373 // Save abort status because abort_status_Reg is used by following code.
1374 if (RTMRetryCount > 0) {
1375 push(abort_status_Reg);
1376 }
1377 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1378 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1379 // restore abort status
1380 if (RTMRetryCount > 0) {
1381 pop(abort_status_Reg);
1382 }
1383 }
1384 }
1385
1386 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1387 // inputs: retry_count_Reg
1388 // : abort_status_Reg
1389 // output: retry_count_Reg decremented by 1
1390 // flags are killed
1391 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1392 Label doneRetry;
1393 assert(abort_status_Reg == rax, "");
1394 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1395 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1396 // if reason is in 0x6 and retry count != 0 then retry
1397 andptr(abort_status_Reg, 0x6);
1398 jccb(Assembler::zero, doneRetry);
1399 testl(retry_count_Reg, retry_count_Reg);
1400 jccb(Assembler::zero, doneRetry);
1401 pause();
1402 decrementl(retry_count_Reg);
1403 jmp(retryLabel);
1404 bind(doneRetry);
1405 }
1406
1407 // Spin and retry if lock is busy,
1408 // inputs: box_Reg (monitor address)
1409 // : retry_count_Reg
1410 // output: retry_count_Reg decremented by 1
1411 // : clear z flag if retry count exceeded
1412 // tmp_Reg, scr_Reg, flags are killed
1413 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1414 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1415 Label SpinLoop, SpinExit, doneRetry;
1416 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1417
1418 testl(retry_count_Reg, retry_count_Reg);
1419 jccb(Assembler::zero, doneRetry);
1420 decrementl(retry_count_Reg);
1421 movptr(scr_Reg, RTMSpinLoopCount);
1422
1423 bind(SpinLoop);
1424 pause();
1425 decrementl(scr_Reg);
1426 jccb(Assembler::lessEqual, SpinExit);
1427 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1428 testptr(tmp_Reg, tmp_Reg);
1429 jccb(Assembler::notZero, SpinLoop);
1430
1431 bind(SpinExit);
1432 jmp(retryLabel);
1433 bind(doneRetry);
1434 incrementl(retry_count_Reg); // clear z flag
1435 }
1436
1437 // Use RTM for normal stack locks
1438 // Input: objReg (object to lock)
1439 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1440 Register retry_on_abort_count_Reg,
1441 RTMLockingCounters* stack_rtm_counters,
1442 Metadata* method_data, bool profile_rtm,
1443 Label& DONE_LABEL, Label& IsInflated) {
1444 assert(UseRTMForStackLocks, "why call this otherwise?");
1445 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1446 assert(tmpReg == rax, "");
1447 assert(scrReg == rdx, "");
1448 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1449
1450 if (RTMRetryCount > 0) {
1451 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1452 bind(L_rtm_retry);
1453 }
1454 movptr(tmpReg, Address(objReg, 0));
1455 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1456 jcc(Assembler::notZero, IsInflated);
1457
1458 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1459 Label L_noincrement;
1460 if (RTMTotalCountIncrRate > 1) {
1461 // tmpReg, scrReg and flags are killed
1462 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1463 }
1464 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1465 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1466 bind(L_noincrement);
1467 }
1468 xbegin(L_on_abort);
1469 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1470 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1471 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1472 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1473
1474 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1475 if (UseRTMXendForLockBusy) {
1476 xend();
1477 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1478 jmp(L_decrement_retry);
1479 }
1480 else {
1481 xabort(0);
1482 }
1483 bind(L_on_abort);
1484 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1485 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1486 }
1487 bind(L_decrement_retry);
1488 if (RTMRetryCount > 0) {
1489 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1490 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1491 }
1492 }
1493
1494 // Use RTM for inflating locks
1495 // inputs: objReg (object to lock)
1496 // boxReg (on-stack box address (displaced header location) - KILLED)
1497 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1498 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1499 Register scrReg, Register retry_on_busy_count_Reg,
1500 Register retry_on_abort_count_Reg,
1501 RTMLockingCounters* rtm_counters,
1502 Metadata* method_data, bool profile_rtm,
1503 Label& DONE_LABEL) {
1504 assert(UseRTMLocking, "why call this otherwise?");
1505 assert(tmpReg == rax, "");
1506 assert(scrReg == rdx, "");
1507 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1508 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1509
1510 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1511 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1512 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1513
1514 if (RTMRetryCount > 0) {
1515 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1516 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1517 bind(L_rtm_retry);
1518 }
1519 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1520 Label L_noincrement;
1521 if (RTMTotalCountIncrRate > 1) {
1522 // tmpReg, scrReg and flags are killed
1523 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1524 }
1525 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1526 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1527 bind(L_noincrement);
1528 }
1529 xbegin(L_on_abort);
1530 movptr(tmpReg, Address(objReg, 0));
1531 movptr(tmpReg, Address(tmpReg, owner_offset));
1532 testptr(tmpReg, tmpReg);
1533 jcc(Assembler::zero, DONE_LABEL);
1534 if (UseRTMXendForLockBusy) {
1535 xend();
1536 jmp(L_decrement_retry);
1537 }
1538 else {
1539 xabort(0);
1540 }
1541 bind(L_on_abort);
1542 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1543 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1544 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1545 }
1546 if (RTMRetryCount > 0) {
1547 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1548 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1549 }
1550
1551 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1552 testptr(tmpReg, tmpReg) ;
1553 jccb(Assembler::notZero, L_decrement_retry) ;
1554
1555 // Appears unlocked - try to swing _owner from null to non-null.
1556 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1557 #ifdef _LP64
1558 Register threadReg = r15_thread;
1559 #else
1560 get_thread(scrReg);
1561 Register threadReg = scrReg;
1562 #endif
1563 if (os::is_MP()) {
1564 lock();
1565 }
1566 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1567
1568 if (RTMRetryCount > 0) {
1569 // success done else retry
1570 jccb(Assembler::equal, DONE_LABEL) ;
1571 bind(L_decrement_retry);
1572 // Spin and retry if lock is busy.
1573 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1574 }
1575 else {
1576 bind(L_decrement_retry);
1577 }
1578 }
1579
1580 #endif // INCLUDE_RTM_OPT
1581
1582 // Fast_Lock and Fast_Unlock used by C2
1583
1584 // Because the transitions from emitted code to the runtime
1585 // monitorenter/exit helper stubs are so slow it's critical that
1586 // we inline both the stack-locking fast-path and the inflated fast path.
1587 //
1588 // See also: cmpFastLock and cmpFastUnlock.
1589 //
1590 // What follows is a specialized inline transliteration of the code
1591 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1592 // another option would be to emit TrySlowEnter and TrySlowExit methods
1593 // at startup-time. These methods would accept arguments as
1594 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1595 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1596 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1597 // In practice, however, the # of lock sites is bounded and is usually small.
1598 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1599 // if the processor uses simple bimodal branch predictors keyed by EIP
1600 // Since the helper routines would be called from multiple synchronization
1601 // sites.
1602 //
1603 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1604 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1605 // to those specialized methods. That'd give us a mostly platform-independent
1606 // implementation that the JITs could optimize and inline at their pleasure.
1607 // Done correctly, the only time we'd need to cross to native could would be
1608 // to park() or unpark() threads. We'd also need a few more unsafe operators
1609 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1610 // (b) explicit barriers or fence operations.
1611 //
1612 // TODO:
1613 //
1614 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1615 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1616 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1617 // the lock operators would typically be faster than reifying Self.
1618 //
1619 // * Ideally I'd define the primitives as:
1620 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1621 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1622 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1623 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1624 // Furthermore the register assignments are overconstrained, possibly resulting in
1625 // sub-optimal code near the synchronization site.
1626 //
1627 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1628 // Alternately, use a better sp-proximity test.
1629 //
1630 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1631 // Either one is sufficient to uniquely identify a thread.
1632 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1633 //
1634 // * Intrinsify notify() and notifyAll() for the common cases where the
1635 // object is locked by the calling thread but the waitlist is empty.
1636 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1637 //
1638 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1639 // But beware of excessive branch density on AMD Opterons.
1640 //
1641 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1642 // or failure of the fast-path. If the fast-path fails then we pass
1643 // control to the slow-path, typically in C. In Fast_Lock and
1644 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1645 // will emit a conditional branch immediately after the node.
1646 // So we have branches to branches and lots of ICC.ZF games.
1647 // Instead, it might be better to have C2 pass a "FailureLabel"
1648 // into Fast_Lock and Fast_Unlock. In the case of success, control
1649 // will drop through the node. ICC.ZF is undefined at exit.
1650 // In the case of failure, the node will branch directly to the
1651 // FailureLabel
1652
1653
1654 // obj: object to lock
1655 // box: on-stack box address (displaced header location) - KILLED
1656 // rax,: tmp -- KILLED
1657 // scr: tmp -- KILLED
1658 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1659 Register scrReg, Register cx1Reg, Register cx2Reg,
1660 BiasedLockingCounters* counters,
1661 RTMLockingCounters* rtm_counters,
1662 RTMLockingCounters* stack_rtm_counters,
1663 Metadata* method_data,
1664 bool use_rtm, bool profile_rtm) {
1665 // Ensure the register assignents are disjoint
1666 assert(tmpReg == rax, "");
1667
1668 if (use_rtm) {
1669 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1670 } else {
1671 assert(cx1Reg == noreg, "");
1672 assert(cx2Reg == noreg, "");
1673 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1674 }
1675
1676 if (counters != NULL) {
1677 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1678 }
1679 if (EmitSync & 1) {
1680 // set box->dhw = markOopDesc::unused_mark()
1681 // Force all sync thru slow-path: slow_enter() and slow_exit()
1682 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1683 cmpptr (rsp, (int32_t)NULL_WORD);
1684 } else {
1685 // Possible cases that we'll encounter in fast_lock
1686 // ------------------------------------------------
1687 // * Inflated
1688 // -- unlocked
1689 // -- Locked
1690 // = by self
1691 // = by other
1692 // * biased
1693 // -- by Self
1694 // -- by other
1695 // * neutral
1696 // * stack-locked
1697 // -- by self
1698 // = sp-proximity test hits
1699 // = sp-proximity test generates false-negative
1700 // -- by other
1701 //
1702
1703 Label IsInflated, DONE_LABEL;
1704
1705 // it's stack-locked, biased or neutral
1706 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1707 // order to reduce the number of conditional branches in the most common cases.
1708 // Beware -- there's a subtle invariant that fetch of the markword
1709 // at [FETCH], below, will never observe a biased encoding (*101b).
1710 // If this invariant is not held we risk exclusion (safety) failure.
1711 if (UseBiasedLocking && !UseOptoBiasInlining) {
1712 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1713 }
1714
1715 #if INCLUDE_RTM_OPT
1716 if (UseRTMForStackLocks && use_rtm) {
1717 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1718 stack_rtm_counters, method_data, profile_rtm,
1719 DONE_LABEL, IsInflated);
1720 }
1721 #endif // INCLUDE_RTM_OPT
1722
1723 movptr(tmpReg, Address(objReg, 0)); // [FETCH]
1724 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1725 jccb(Assembler::notZero, IsInflated);
1726
1727 // Attempt stack-locking ...
1728 orptr (tmpReg, markOopDesc::unlocked_value);
1729 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1730 if (os::is_MP()) {
1731 lock();
1732 }
1733 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
1734 if (counters != NULL) {
1735 cond_inc32(Assembler::equal,
1736 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1737 }
1738 jcc(Assembler::equal, DONE_LABEL); // Success
1739
1740 // Recursive locking.
1741 // The object is stack-locked: markword contains stack pointer to BasicLock.
1742 // Locked by current thread if difference with current SP is less than one page.
1743 subptr(tmpReg, rsp);
1744 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1745 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1746 movptr(Address(boxReg, 0), tmpReg);
1747 if (counters != NULL) {
1748 cond_inc32(Assembler::equal,
1749 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1750 }
1751 jmp(DONE_LABEL);
1752
1753 bind(IsInflated);
1754 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1755
1756 #if INCLUDE_RTM_OPT
1757 // Use the same RTM locking code in 32- and 64-bit VM.
1758 if (use_rtm) {
1759 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1760 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1761 } else {
1762 #endif // INCLUDE_RTM_OPT
1763
1764 #ifndef _LP64
1765 // The object is inflated.
1766
1767 // boxReg refers to the on-stack BasicLock in the current frame.
1768 // We'd like to write:
1769 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices.
1770 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1771 // additional latency as we have another ST in the store buffer that must drain.
1772
1773 if (EmitSync & 8192) {
1774 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1775 get_thread (scrReg);
1776 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1777 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1778 if (os::is_MP()) {
1779 lock();
1780 }
1781 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1782 } else
1783 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1784 // register juggle because we need tmpReg for cmpxchgptr below
1785 movptr(scrReg, boxReg);
1786 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1787
1788 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1789 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1790 // prefetchw [eax + Offset(_owner)-2]
1791 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1792 }
1793
1794 if ((EmitSync & 64) == 0) {
1795 // Optimistic form: consider XORL tmpReg,tmpReg
1796 movptr(tmpReg, NULL_WORD);
1797 } else {
1798 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1799 // Test-And-CAS instead of CAS
1800 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1801 testptr(tmpReg, tmpReg); // Locked ?
1802 jccb (Assembler::notZero, DONE_LABEL);
1803 }
1804
1805 // Appears unlocked - try to swing _owner from null to non-null.
1806 // Ideally, I'd manifest "Self" with get_thread and then attempt
1807 // to CAS the register containing Self into m->Owner.
1808 // But we don't have enough registers, so instead we can either try to CAS
1809 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1810 // we later store "Self" into m->Owner. Transiently storing a stack address
1811 // (rsp or the address of the box) into m->owner is harmless.
1812 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1813 if (os::is_MP()) {
1814 lock();
1815 }
1816 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1817 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1818 // If we weren't able to swing _owner from NULL to the BasicLock
1819 // then take the slow path.
1820 jccb (Assembler::notZero, DONE_LABEL);
1821 // update _owner from BasicLock to thread
1822 get_thread (scrReg); // beware: clobbers ICCs
1823 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1824 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1825
1826 // If the CAS fails we can either retry or pass control to the slow-path.
1827 // We use the latter tactic.
1828 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1829 // If the CAS was successful ...
1830 // Self has acquired the lock
1831 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1832 // Intentional fall-through into DONE_LABEL ...
1833 } else {
1834 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1835 movptr(boxReg, tmpReg);
1836
1837 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1838 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1839 // prefetchw [eax + Offset(_owner)-2]
1840 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1841 }
1842
1843 if ((EmitSync & 64) == 0) {
1844 // Optimistic form
1845 xorptr (tmpReg, tmpReg);
1846 } else {
1847 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1848 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1849 testptr(tmpReg, tmpReg); // Locked ?
1850 jccb (Assembler::notZero, DONE_LABEL);
1851 }
1852
1853 // Appears unlocked - try to swing _owner from null to non-null.
1854 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1855 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1856 get_thread (scrReg);
1857 if (os::is_MP()) {
1858 lock();
1859 }
1860 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1861
1862 // If the CAS fails we can either retry or pass control to the slow-path.
1863 // We use the latter tactic.
1864 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1865 // If the CAS was successful ...
1866 // Self has acquired the lock
1867 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1868 // Intentional fall-through into DONE_LABEL ...
1869 }
1870 #else // _LP64
1871 // It's inflated
1872 movq(scrReg, tmpReg);
1873 xorq(tmpReg, tmpReg);
1874
1875 if (os::is_MP()) {
1876 lock();
1877 }
1878 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1879 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1880 // Without cast to int32_t movptr will destroy r10 which is typically obj.
1881 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1882 // Intentional fall-through into DONE_LABEL ...
1883 // Propagate ICC.ZF from CAS above into DONE_LABEL.
1884 #endif // _LP64
1885 #if INCLUDE_RTM_OPT
1886 } // use_rtm()
1887 #endif
1888 // DONE_LABEL is a hot target - we'd really like to place it at the
1889 // start of cache line by padding with NOPs.
1890 // See the AMD and Intel software optimization manuals for the
1891 // most efficient "long" NOP encodings.
1892 // Unfortunately none of our alignment mechanisms suffice.
1893 bind(DONE_LABEL);
1894
1895 // At DONE_LABEL the icc ZFlag is set as follows ...
1896 // Fast_Unlock uses the same protocol.
1897 // ZFlag == 1 -> Success
1898 // ZFlag == 0 -> Failure - force control through the slow-path
1899 }
1900 }
1901
1902 // obj: object to unlock
1903 // box: box address (displaced header location), killed. Must be EAX.
1904 // tmp: killed, cannot be obj nor box.
1905 //
1906 // Some commentary on balanced locking:
1907 //
1908 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1909 // Methods that don't have provably balanced locking are forced to run in the
1910 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1911 // The interpreter provides two properties:
1912 // I1: At return-time the interpreter automatically and quietly unlocks any
1913 // objects acquired the current activation (frame). Recall that the
1914 // interpreter maintains an on-stack list of locks currently held by
1915 // a frame.
1916 // I2: If a method attempts to unlock an object that is not held by the
1917 // the frame the interpreter throws IMSX.
1918 //
1919 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1920 // B() doesn't have provably balanced locking so it runs in the interpreter.
1921 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1922 // is still locked by A().
1923 //
1924 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1925 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1926 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1927 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1928 // Arguably given that the spec legislates the JNI case as undefined our implementation
1929 // could reasonably *avoid* checking owner in Fast_Unlock().
1930 // In the interest of performance we elide m->Owner==Self check in unlock.
1931 // A perfectly viable alternative is to elide the owner check except when
1932 // Xcheck:jni is enabled.
1933
1934 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1935 assert(boxReg == rax, "");
1936 assert_different_registers(objReg, boxReg, tmpReg);
1937
1938 if (EmitSync & 4) {
1939 // Disable - inhibit all inlining. Force control through the slow-path
1940 cmpptr (rsp, 0);
1941 } else {
1942 Label DONE_LABEL, Stacked, CheckSucc;
1943
1944 // Critically, the biased locking test must have precedence over
1945 // and appear before the (box->dhw == 0) recursive stack-lock test.
1946 if (UseBiasedLocking && !UseOptoBiasInlining) {
1947 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1948 }
1949
1950 #if INCLUDE_RTM_OPT
1951 if (UseRTMForStackLocks && use_rtm) {
1952 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1953 Label L_regular_unlock;
1954 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1955 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1956 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1957 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
1958 xend(); // otherwise end...
1959 jmp(DONE_LABEL); // ... and we're done
1960 bind(L_regular_unlock);
1961 }
1962 #endif
1963
1964 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
1965 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
1966 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword
1967 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
1968 jccb (Assembler::zero, Stacked);
1969
1970 // It's inflated.
1971 #if INCLUDE_RTM_OPT
1972 if (use_rtm) {
1973 Label L_regular_inflated_unlock;
1974 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1975 movptr(boxReg, Address(tmpReg, owner_offset));
1976 testptr(boxReg, boxReg);
1977 jccb(Assembler::notZero, L_regular_inflated_unlock);
1978 xend();
1979 jmpb(DONE_LABEL);
1980 bind(L_regular_inflated_unlock);
1981 }
1982 #endif
1983
1984 // Despite our balanced locking property we still check that m->_owner == Self
1985 // as java routines or native JNI code called by this thread might
1986 // have released the lock.
1987 // Refer to the comments in synchronizer.cpp for how we might encode extra
1988 // state in _succ so we can avoid fetching EntryList|cxq.
1989 //
1990 // I'd like to add more cases in fast_lock() and fast_unlock() --
1991 // such as recursive enter and exit -- but we have to be wary of
1992 // I$ bloat, T$ effects and BP$ effects.
1993 //
1994 // If there's no contention try a 1-0 exit. That is, exit without
1995 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
1996 // we detect and recover from the race that the 1-0 exit admits.
1997 //
1998 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
1999 // before it STs null into _owner, releasing the lock. Updates
2000 // to data protected by the critical section must be visible before
2001 // we drop the lock (and thus before any other thread could acquire
2002 // the lock and observe the fields protected by the lock).
2003 // IA32's memory-model is SPO, so STs are ordered with respect to
2004 // each other and there's no need for an explicit barrier (fence).
2005 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2006 #ifndef _LP64
2007 get_thread (boxReg);
2008 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2009 // prefetchw [ebx + Offset(_owner)-2]
2010 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2011 }
2012
2013 // Note that we could employ various encoding schemes to reduce
2014 // the number of loads below (currently 4) to just 2 or 3.
2015 // Refer to the comments in synchronizer.cpp.
2016 // In practice the chain of fetches doesn't seem to impact performance, however.
2017 xorptr(boxReg, boxReg);
2018 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2019 // Attempt to reduce branch density - AMD's branch predictor.
2020 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2021 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2022 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2023 jccb (Assembler::notZero, DONE_LABEL);
2024 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2025 jmpb (DONE_LABEL);
2026 } else {
2027 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2028 jccb (Assembler::notZero, DONE_LABEL);
2029 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2030 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2031 jccb (Assembler::notZero, CheckSucc);
2032 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2033 jmpb (DONE_LABEL);
2034 }
2035
2036 // The Following code fragment (EmitSync & 65536) improves the performance of
2037 // contended applications and contended synchronization microbenchmarks.
2038 // Unfortunately the emission of the code - even though not executed - causes regressions
2039 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2040 // with an equal number of never-executed NOPs results in the same regression.
2041 // We leave it off by default.
2042
2043 if ((EmitSync & 65536) != 0) {
2044 Label LSuccess, LGoSlowPath ;
2045
2046 bind (CheckSucc);
2047
2048 // Optional pre-test ... it's safe to elide this
2049 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2050 jccb(Assembler::zero, LGoSlowPath);
2051
2052 // We have a classic Dekker-style idiom:
2053 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2054 // There are a number of ways to implement the barrier:
2055 // (1) lock:andl &m->_owner, 0
2056 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2057 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2058 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2059 // (2) If supported, an explicit MFENCE is appealing.
2060 // In older IA32 processors MFENCE is slower than lock:add or xchg
2061 // particularly if the write-buffer is full as might be the case if
2062 // if stores closely precede the fence or fence-equivalent instruction.
2063 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2064 // as the situation has changed with Nehalem and Shanghai.
2065 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2066 // The $lines underlying the top-of-stack should be in M-state.
2067 // The locked add instruction is serializing, of course.
2068 // (4) Use xchg, which is serializing
2069 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2070 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2071 // The integer condition codes will tell us if succ was 0.
2072 // Since _succ and _owner should reside in the same $line and
2073 // we just stored into _owner, it's likely that the $line
2074 // remains in M-state for the lock:orl.
2075 //
2076 // We currently use (3), although it's likely that switching to (2)
2077 // is correct for the future.
2078
2079 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2080 if (os::is_MP()) {
2081 lock(); addptr(Address(rsp, 0), 0);
2082 }
2083 // Ratify _succ remains non-null
2084 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0);
2085 jccb (Assembler::notZero, LSuccess);
2086
2087 xorptr(boxReg, boxReg); // box is really EAX
2088 if (os::is_MP()) { lock(); }
2089 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2090 // There's no successor so we tried to regrab the lock with the
2091 // placeholder value. If that didn't work, then another thread
2092 // grabbed the lock so we're done (and exit was a success).
2093 jccb (Assembler::notEqual, LSuccess);
2094 // Since we're low on registers we installed rsp as a placeholding in _owner.
2095 // Now install Self over rsp. This is safe as we're transitioning from
2096 // non-null to non=null
2097 get_thread (boxReg);
2098 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg);
2099 // Intentional fall-through into LGoSlowPath ...
2100
2101 bind (LGoSlowPath);
2102 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2103 jmpb (DONE_LABEL);
2104
2105 bind (LSuccess);
2106 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2107 jmpb (DONE_LABEL);
2108 }
2109
2110 bind (Stacked);
2111 // It's not inflated and it's not recursively stack-locked and it's not biased.
2112 // It must be stack-locked.
2113 // Try to reset the header to displaced header.
2114 // The "box" value on the stack is stable, so we can reload
2115 // and be assured we observe the same value as above.
2116 movptr(tmpReg, Address(boxReg, 0));
2117 if (os::is_MP()) {
2118 lock();
2119 }
2120 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2121 // Intention fall-thru into DONE_LABEL
2122
2123 // DONE_LABEL is a hot target - we'd really like to place it at the
2124 // start of cache line by padding with NOPs.
2125 // See the AMD and Intel software optimization manuals for the
2126 // most efficient "long" NOP encodings.
2127 // Unfortunately none of our alignment mechanisms suffice.
2128 if ((EmitSync & 65536) == 0) {
2129 bind (CheckSucc);
2130 }
2131 #else // _LP64
2132 // It's inflated
2133 if (EmitSync & 1024) {
2134 // Emit code to check that _owner == Self
2135 // We could fold the _owner test into subsequent code more efficiently
2136 // than using a stand-alone check, but since _owner checking is off by
2137 // default we don't bother. We also might consider predicating the
2138 // _owner==Self check on Xcheck:jni or running on a debug build.
2139 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2140 xorptr(boxReg, r15_thread);
2141 } else {
2142 xorptr(boxReg, boxReg);
2143 }
2144 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2145 jccb (Assembler::notZero, DONE_LABEL);
2146 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2147 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2148 jccb (Assembler::notZero, CheckSucc);
2149 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2150 jmpb (DONE_LABEL);
2151
2152 if ((EmitSync & 65536) == 0) {
2153 // Try to avoid passing control into the slow_path ...
2154 Label LSuccess, LGoSlowPath ;
2155 bind (CheckSucc);
2156
2157 // The following optional optimization can be elided if necessary
2158 // Effectively: if (succ == null) goto SlowPath
2159 // The code reduces the window for a race, however,
2160 // and thus benefits performance.
2161 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2162 jccb (Assembler::zero, LGoSlowPath);
2163
2164 if ((EmitSync & 16) && os::is_MP()) {
2165 orptr(boxReg, boxReg);
2166 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2167 } else {
2168 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2169 if (os::is_MP()) {
2170 // Memory barrier/fence
2171 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2172 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2173 // This is faster on Nehalem and AMD Shanghai/Barcelona.
2174 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2175 // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2176 // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2177 lock(); addl(Address(rsp, 0), 0);
2178 }
2179 }
2180 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2181 jccb (Assembler::notZero, LSuccess);
2182
2183 // Rare inopportune interleaving - race.
2184 // The successor vanished in the small window above.
2185 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2186 // We need to ensure progress and succession.
2187 // Try to reacquire the lock.
2188 // If that fails then the new owner is responsible for succession and this
2189 // thread needs to take no further action and can exit via the fast path (success).
2190 // If the re-acquire succeeds then pass control into the slow path.
2191 // As implemented, this latter mode is horrible because we generated more
2192 // coherence traffic on the lock *and* artifically extended the critical section
2193 // length while by virtue of passing control into the slow path.
2194
2195 // box is really RAX -- the following CMPXCHG depends on that binding
2196 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2197 movptr(boxReg, (int32_t)NULL_WORD);
2198 if (os::is_MP()) { lock(); }
2199 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2200 // There's no successor so we tried to regrab the lock.
2201 // If that didn't work, then another thread grabbed the
2202 // lock so we're done (and exit was a success).
2203 jccb (Assembler::notEqual, LSuccess);
2204 // Intentional fall-through into slow-path
2205
2206 bind (LGoSlowPath);
2207 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2208 jmpb (DONE_LABEL);
2209
2210 bind (LSuccess);
2211 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2212 jmpb (DONE_LABEL);
2213 }
2214
2215 bind (Stacked);
2216 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2217 if (os::is_MP()) { lock(); }
2218 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2219
2220 if (EmitSync & 65536) {
2221 bind (CheckSucc);
2222 }
2223 #endif
2224 bind(DONE_LABEL);
2225 }
2226 }
2227 #endif // COMPILER2
2228
2229 void MacroAssembler::c2bool(Register x) {
2230 // implements x == 0 ? 0 : 1
2231 // note: must only look at least-significant byte of x
2232 // since C-style booleans are stored in one byte
2233 // only! (was bug)
2234 andl(x, 0xFF);
2235 setb(Assembler::notZero, x);
2236 }
2237
2238 // Wouldn't need if AddressLiteral version had new name
2239 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2240 Assembler::call(L, rtype);
2241 }
2242
2243 void MacroAssembler::call(Register entry) {
2244 Assembler::call(entry);
2245 }
2246
2247 void MacroAssembler::call(AddressLiteral entry) {
2248 if (reachable(entry)) {
2249 Assembler::call_literal(entry.target(), entry.rspec());
2250 } else {
2251 lea(rscratch1, entry);
2252 Assembler::call(rscratch1);
2253 }
2254 }
2255
2256 void MacroAssembler::ic_call(address entry) {
2257 RelocationHolder rh = virtual_call_Relocation::spec(pc());
2258 movptr(rax, (intptr_t)Universe::non_oop_word());
2259 call(AddressLiteral(entry, rh));
2260 }
2261
2262 // Implementation of call_VM versions
2263
2264 void MacroAssembler::call_VM(Register oop_result,
2265 address entry_point,
2266 bool check_exceptions) {
2267 Label C, E;
2268 call(C, relocInfo::none);
2269 jmp(E);
2270
2271 bind(C);
2272 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2273 ret(0);
2274
2275 bind(E);
2276 }
2277
2278 void MacroAssembler::call_VM(Register oop_result,
2279 address entry_point,
2280 Register arg_1,
2281 bool check_exceptions) {
2282 Label C, E;
2283 call(C, relocInfo::none);
2284 jmp(E);
2285
2286 bind(C);
2287 pass_arg1(this, arg_1);
2288 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2289 ret(0);
2290
2291 bind(E);
2292 }
2293
2294 void MacroAssembler::call_VM(Register oop_result,
2295 address entry_point,
2296 Register arg_1,
2297 Register arg_2,
2298 bool check_exceptions) {
2299 Label C, E;
2300 call(C, relocInfo::none);
2301 jmp(E);
2302
2303 bind(C);
2304
2305 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2306
2307 pass_arg2(this, arg_2);
2308 pass_arg1(this, arg_1);
2309 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2310 ret(0);
2311
2312 bind(E);
2313 }
2314
2315 void MacroAssembler::call_VM(Register oop_result,
2316 address entry_point,
2317 Register arg_1,
2318 Register arg_2,
2319 Register arg_3,
2320 bool check_exceptions) {
2321 Label C, E;
2322 call(C, relocInfo::none);
2323 jmp(E);
2324
2325 bind(C);
2326
2327 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2328 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2329 pass_arg3(this, arg_3);
2330
2331 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2332 pass_arg2(this, arg_2);
2333
2334 pass_arg1(this, arg_1);
2335 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2336 ret(0);
2337
2338 bind(E);
2339 }
2340
2341 void MacroAssembler::call_VM(Register oop_result,
2342 Register last_java_sp,
2343 address entry_point,
2344 int number_of_arguments,
2345 bool check_exceptions) {
2346 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2347 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2348 }
2349
2350 void MacroAssembler::call_VM(Register oop_result,
2351 Register last_java_sp,
2352 address entry_point,
2353 Register arg_1,
2354 bool check_exceptions) {
2355 pass_arg1(this, arg_1);
2356 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2357 }
2358
2359 void MacroAssembler::call_VM(Register oop_result,
2360 Register last_java_sp,
2361 address entry_point,
2362 Register arg_1,
2363 Register arg_2,
2364 bool check_exceptions) {
2365
2366 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2367 pass_arg2(this, arg_2);
2368 pass_arg1(this, arg_1);
2369 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2370 }
2371
2372 void MacroAssembler::call_VM(Register oop_result,
2373 Register last_java_sp,
2374 address entry_point,
2375 Register arg_1,
2376 Register arg_2,
2377 Register arg_3,
2378 bool check_exceptions) {
2379 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2380 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2381 pass_arg3(this, arg_3);
2382 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2383 pass_arg2(this, arg_2);
2384 pass_arg1(this, arg_1);
2385 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2386 }
2387
2388 void MacroAssembler::super_call_VM(Register oop_result,
2389 Register last_java_sp,
2390 address entry_point,
2391 int number_of_arguments,
2392 bool check_exceptions) {
2393 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2394 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2395 }
2396
2397 void MacroAssembler::super_call_VM(Register oop_result,
2398 Register last_java_sp,
2399 address entry_point,
2400 Register arg_1,
2401 bool check_exceptions) {
2402 pass_arg1(this, arg_1);
2403 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2404 }
2405
2406 void MacroAssembler::super_call_VM(Register oop_result,
2407 Register last_java_sp,
2408 address entry_point,
2409 Register arg_1,
2410 Register arg_2,
2411 bool check_exceptions) {
2412
2413 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2414 pass_arg2(this, arg_2);
2415 pass_arg1(this, arg_1);
2416 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2417 }
2418
2419 void MacroAssembler::super_call_VM(Register oop_result,
2420 Register last_java_sp,
2421 address entry_point,
2422 Register arg_1,
2423 Register arg_2,
2424 Register arg_3,
2425 bool check_exceptions) {
2426 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2427 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2428 pass_arg3(this, arg_3);
2429 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2430 pass_arg2(this, arg_2);
2431 pass_arg1(this, arg_1);
2432 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2433 }
2434
2435 void MacroAssembler::call_VM_base(Register oop_result,
2436 Register java_thread,
2437 Register last_java_sp,
2438 address entry_point,
2439 int number_of_arguments,
2440 bool check_exceptions) {
2441 // determine java_thread register
2442 if (!java_thread->is_valid()) {
2443 #ifdef _LP64
2444 java_thread = r15_thread;
2445 #else
2446 java_thread = rdi;
2447 get_thread(java_thread);
2448 #endif // LP64
2449 }
2450 // determine last_java_sp register
2451 if (!last_java_sp->is_valid()) {
2452 last_java_sp = rsp;
2453 }
2454 // debugging support
2455 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2456 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2457 #ifdef ASSERT
2458 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2459 // r12 is the heapbase.
2460 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2461 #endif // ASSERT
2462
2463 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2464 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2465
2466 // push java thread (becomes first argument of C function)
2467
2468 NOT_LP64(push(java_thread); number_of_arguments++);
2469 LP64_ONLY(mov(c_rarg0, r15_thread));
2470
2471 // set last Java frame before call
2472 assert(last_java_sp != rbp, "can't use ebp/rbp");
2473
2474 // Only interpreter should have to set fp
2475 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2476
2477 // do the call, remove parameters
2478 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2479
2480 // restore the thread (cannot use the pushed argument since arguments
2481 // may be overwritten by C code generated by an optimizing compiler);
2482 // however can use the register value directly if it is callee saved.
2483 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2484 // rdi & rsi (also r15) are callee saved -> nothing to do
2485 #ifdef ASSERT
2486 guarantee(java_thread != rax, "change this code");
2487 push(rax);
2488 { Label L;
2489 get_thread(rax);
2490 cmpptr(java_thread, rax);
2491 jcc(Assembler::equal, L);
2492 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2493 bind(L);
2494 }
2495 pop(rax);
2496 #endif
2497 } else {
2498 get_thread(java_thread);
2499 }
2500 // reset last Java frame
2501 // Only interpreter should have to clear fp
2502 reset_last_Java_frame(java_thread, true, false);
2503
2504 #ifndef CC_INTERP
2505 // C++ interp handles this in the interpreter
2506 check_and_handle_popframe(java_thread);
2507 check_and_handle_earlyret(java_thread);
2508 #endif /* CC_INTERP */
2509
2510 if (check_exceptions) {
2511 // check for pending exceptions (java_thread is set upon return)
2512 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2513 #ifndef _LP64
2514 jump_cc(Assembler::notEqual,
2515 RuntimeAddress(StubRoutines::forward_exception_entry()));
2516 #else
2517 // This used to conditionally jump to forward_exception however it is
2518 // possible if we relocate that the branch will not reach. So we must jump
2519 // around so we can always reach
2520
2521 Label ok;
2522 jcc(Assembler::equal, ok);
2523 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2524 bind(ok);
2525 #endif // LP64
2526 }
2527
2528 // get oop result if there is one and reset the value in the thread
2529 if (oop_result->is_valid()) {
2530 get_vm_result(oop_result, java_thread);
2531 }
2532 }
2533
2534 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2535
2536 // Calculate the value for last_Java_sp
2537 // somewhat subtle. call_VM does an intermediate call
2538 // which places a return address on the stack just under the
2539 // stack pointer as the user finsihed with it. This allows
2540 // use to retrieve last_Java_pc from last_Java_sp[-1].
2541 // On 32bit we then have to push additional args on the stack to accomplish
2542 // the actual requested call. On 64bit call_VM only can use register args
2543 // so the only extra space is the return address that call_VM created.
2544 // This hopefully explains the calculations here.
2545
2546 #ifdef _LP64
2547 // We've pushed one address, correct last_Java_sp
2548 lea(rax, Address(rsp, wordSize));
2549 #else
2550 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2551 #endif // LP64
2552
2553 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2554
2555 }
2556
2557 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2558 call_VM_leaf_base(entry_point, number_of_arguments);
2559 }
2560
2561 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2562 pass_arg0(this, arg_0);
2563 call_VM_leaf(entry_point, 1);
2564 }
2565
2566 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2567
2568 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2569 pass_arg1(this, arg_1);
2570 pass_arg0(this, arg_0);
2571 call_VM_leaf(entry_point, 2);
2572 }
2573
2574 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2575 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2576 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2577 pass_arg2(this, arg_2);
2578 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2579 pass_arg1(this, arg_1);
2580 pass_arg0(this, arg_0);
2581 call_VM_leaf(entry_point, 3);
2582 }
2583
2584 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2585 pass_arg0(this, arg_0);
2586 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2587 }
2588
2589 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2590
2591 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2592 pass_arg1(this, arg_1);
2593 pass_arg0(this, arg_0);
2594 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2595 }
2596
2597 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2598 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2599 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2600 pass_arg2(this, arg_2);
2601 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2602 pass_arg1(this, arg_1);
2603 pass_arg0(this, arg_0);
2604 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2605 }
2606
2607 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2608 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2609 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2610 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2611 pass_arg3(this, arg_3);
2612 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2613 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2614 pass_arg2(this, arg_2);
2615 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2616 pass_arg1(this, arg_1);
2617 pass_arg0(this, arg_0);
2618 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2619 }
2620
2621 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2622 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2623 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2624 verify_oop(oop_result, "broken oop in call_VM_base");
2625 }
2626
2627 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2628 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2629 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2630 }
2631
2632 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2633 }
2634
2635 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2636 }
2637
2638 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2639 if (reachable(src1)) {
2640 cmpl(as_Address(src1), imm);
2641 } else {
2642 lea(rscratch1, src1);
2643 cmpl(Address(rscratch1, 0), imm);
2644 }
2645 }
2646
2647 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2648 assert(!src2.is_lval(), "use cmpptr");
2649 if (reachable(src2)) {
2650 cmpl(src1, as_Address(src2));
2651 } else {
2652 lea(rscratch1, src2);
2653 cmpl(src1, Address(rscratch1, 0));
2654 }
2655 }
2656
2657 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2658 Assembler::cmpl(src1, imm);
2659 }
2660
2661 void MacroAssembler::cmp32(Register src1, Address src2) {
2662 Assembler::cmpl(src1, src2);
2663 }
2664
2665 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2666 ucomisd(opr1, opr2);
2667
2668 Label L;
2669 if (unordered_is_less) {
2670 movl(dst, -1);
2671 jcc(Assembler::parity, L);
2672 jcc(Assembler::below , L);
2673 movl(dst, 0);
2674 jcc(Assembler::equal , L);
2675 increment(dst);
2676 } else { // unordered is greater
2677 movl(dst, 1);
2678 jcc(Assembler::parity, L);
2679 jcc(Assembler::above , L);
2680 movl(dst, 0);
2681 jcc(Assembler::equal , L);
2682 decrementl(dst);
2683 }
2684 bind(L);
2685 }
2686
2687 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2688 ucomiss(opr1, opr2);
2689
2690 Label L;
2691 if (unordered_is_less) {
2692 movl(dst, -1);
2693 jcc(Assembler::parity, L);
2694 jcc(Assembler::below , L);
2695 movl(dst, 0);
2696 jcc(Assembler::equal , L);
2697 increment(dst);
2698 } else { // unordered is greater
2699 movl(dst, 1);
2700 jcc(Assembler::parity, L);
2701 jcc(Assembler::above , L);
2702 movl(dst, 0);
2703 jcc(Assembler::equal , L);
2704 decrementl(dst);
2705 }
2706 bind(L);
2707 }
2708
2709
2710 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2711 if (reachable(src1)) {
2712 cmpb(as_Address(src1), imm);
2713 } else {
2714 lea(rscratch1, src1);
2715 cmpb(Address(rscratch1, 0), imm);
2716 }
2717 }
2718
2719 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2720 #ifdef _LP64
2721 if (src2.is_lval()) {
2722 movptr(rscratch1, src2);
2723 Assembler::cmpq(src1, rscratch1);
2724 } else if (reachable(src2)) {
2725 cmpq(src1, as_Address(src2));
2726 } else {
2727 lea(rscratch1, src2);
2728 Assembler::cmpq(src1, Address(rscratch1, 0));
2729 }
2730 #else
2731 if (src2.is_lval()) {
2732 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2733 } else {
2734 cmpl(src1, as_Address(src2));
2735 }
2736 #endif // _LP64
2737 }
2738
2739 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2740 assert(src2.is_lval(), "not a mem-mem compare");
2741 #ifdef _LP64
2742 // moves src2's literal address
2743 movptr(rscratch1, src2);
2744 Assembler::cmpq(src1, rscratch1);
2745 #else
2746 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2747 #endif // _LP64
2748 }
2749
2750 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2751 if (reachable(adr)) {
2752 if (os::is_MP())
2753 lock();
2754 cmpxchgptr(reg, as_Address(adr));
2755 } else {
2756 lea(rscratch1, adr);
2757 if (os::is_MP())
2758 lock();
2759 cmpxchgptr(reg, Address(rscratch1, 0));
2760 }
2761 }
2762
2763 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2764 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2765 }
2766
2767 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2768 if (reachable(src)) {
2769 Assembler::comisd(dst, as_Address(src));
2770 } else {
2771 lea(rscratch1, src);
2772 Assembler::comisd(dst, Address(rscratch1, 0));
2773 }
2774 }
2775
2776 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2777 if (reachable(src)) {
2778 Assembler::comiss(dst, as_Address(src));
2779 } else {
2780 lea(rscratch1, src);
2781 Assembler::comiss(dst, Address(rscratch1, 0));
2782 }
2783 }
2784
2785
2786 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2787 Condition negated_cond = negate_condition(cond);
2788 Label L;
2789 jcc(negated_cond, L);
2790 pushf(); // Preserve flags
2791 atomic_incl(counter_addr);
2792 popf();
2793 bind(L);
2794 }
2795
2796 int MacroAssembler::corrected_idivl(Register reg) {
2797 // Full implementation of Java idiv and irem; checks for
2798 // special case as described in JVM spec., p.243 & p.271.
2799 // The function returns the (pc) offset of the idivl
2800 // instruction - may be needed for implicit exceptions.
2801 //
2802 // normal case special case
2803 //
2804 // input : rax,: dividend min_int
2805 // reg: divisor (may not be rax,/rdx) -1
2806 //
2807 // output: rax,: quotient (= rax, idiv reg) min_int
2808 // rdx: remainder (= rax, irem reg) 0
2809 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2810 const int min_int = 0x80000000;
2811 Label normal_case, special_case;
2812
2813 // check for special case
2814 cmpl(rax, min_int);
2815 jcc(Assembler::notEqual, normal_case);
2816 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2817 cmpl(reg, -1);
2818 jcc(Assembler::equal, special_case);
2819
2820 // handle normal case
2821 bind(normal_case);
2822 cdql();
2823 int idivl_offset = offset();
2824 idivl(reg);
2825
2826 // normal and special case exit
2827 bind(special_case);
2828
2829 return idivl_offset;
2830 }
2831
2832
2833
2834 void MacroAssembler::decrementl(Register reg, int value) {
2835 if (value == min_jint) {subl(reg, value) ; return; }
2836 if (value < 0) { incrementl(reg, -value); return; }
2837 if (value == 0) { ; return; }
2838 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2839 /* else */ { subl(reg, value) ; return; }
2840 }
2841
2842 void MacroAssembler::decrementl(Address dst, int value) {
2843 if (value == min_jint) {subl(dst, value) ; return; }
2844 if (value < 0) { incrementl(dst, -value); return; }
2845 if (value == 0) { ; return; }
2846 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2847 /* else */ { subl(dst, value) ; return; }
2848 }
2849
2850 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2851 assert (shift_value > 0, "illegal shift value");
2852 Label _is_positive;
2853 testl (reg, reg);
2854 jcc (Assembler::positive, _is_positive);
2855 int offset = (1 << shift_value) - 1 ;
2856
2857 if (offset == 1) {
2858 incrementl(reg);
2859 } else {
2860 addl(reg, offset);
2861 }
2862
2863 bind (_is_positive);
2864 sarl(reg, shift_value);
2865 }
2866
2867 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2868 if (reachable(src)) {
2869 Assembler::divsd(dst, as_Address(src));
2870 } else {
2871 lea(rscratch1, src);
2872 Assembler::divsd(dst, Address(rscratch1, 0));
2873 }
2874 }
2875
2876 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2877 if (reachable(src)) {
2878 Assembler::divss(dst, as_Address(src));
2879 } else {
2880 lea(rscratch1, src);
2881 Assembler::divss(dst, Address(rscratch1, 0));
2882 }
2883 }
2884
2885 // !defined(COMPILER2) is because of stupid core builds
2886 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2)
2887 void MacroAssembler::empty_FPU_stack() {
2888 if (VM_Version::supports_mmx()) {
2889 emms();
2890 } else {
2891 for (int i = 8; i-- > 0; ) ffree(i);
2892 }
2893 }
2894 #endif // !LP64 || C1 || !C2
2895
2896
2897 // Defines obj, preserves var_size_in_bytes
2898 void MacroAssembler::eden_allocate(Register obj,
2899 Register var_size_in_bytes,
2900 int con_size_in_bytes,
2901 Register t1,
2902 Label& slow_case) {
2903 assert(obj == rax, "obj must be in rax, for cmpxchg");
2904 assert_different_registers(obj, var_size_in_bytes, t1);
2905 if (!Universe::heap()->supports_inline_contig_alloc()) {
2906 jmp(slow_case);
2907 } else {
2908 Register end = t1;
2909 Label retry;
2910 bind(retry);
2911 ExternalAddress heap_top((address) Universe::heap()->top_addr());
2912 movptr(obj, heap_top);
2913 if (var_size_in_bytes == noreg) {
2914 lea(end, Address(obj, con_size_in_bytes));
2915 } else {
2916 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2917 }
2918 // if end < obj then we wrapped around => object too long => slow case
2919 cmpptr(end, obj);
2920 jcc(Assembler::below, slow_case);
2921 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
2922 jcc(Assembler::above, slow_case);
2923 // Compare obj with the top addr, and if still equal, store the new top addr in
2924 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2925 // it otherwise. Use lock prefix for atomicity on MPs.
2926 locked_cmpxchgptr(end, heap_top);
2927 jcc(Assembler::notEqual, retry);
2928 }
2929 }
2930
2931 void MacroAssembler::enter() {
2932 push(rbp);
2933 mov(rbp, rsp);
2934 }
2935
2936 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2937 void MacroAssembler::fat_nop() {
2938 if (UseAddressNop) {
2939 addr_nop_5();
2940 } else {
2941 emit_int8(0x26); // es:
2942 emit_int8(0x2e); // cs:
2943 emit_int8(0x64); // fs:
2944 emit_int8(0x65); // gs:
2945 emit_int8((unsigned char)0x90);
2946 }
2947 }
2948
2949 void MacroAssembler::fcmp(Register tmp) {
2950 fcmp(tmp, 1, true, true);
2951 }
2952
2953 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2954 assert(!pop_right || pop_left, "usage error");
2955 if (VM_Version::supports_cmov()) {
2956 assert(tmp == noreg, "unneeded temp");
2957 if (pop_left) {
2958 fucomip(index);
2959 } else {
2960 fucomi(index);
2961 }
2962 if (pop_right) {
2963 fpop();
2964 }
2965 } else {
2966 assert(tmp != noreg, "need temp");
2967 if (pop_left) {
2968 if (pop_right) {
2969 fcompp();
2970 } else {
2971 fcomp(index);
2972 }
2973 } else {
2974 fcom(index);
2975 }
2976 // convert FPU condition into eflags condition via rax,
2977 save_rax(tmp);
2978 fwait(); fnstsw_ax();
2979 sahf();
2980 restore_rax(tmp);
2981 }
2982 // condition codes set as follows:
2983 //
2984 // CF (corresponds to C0) if x < y
2985 // PF (corresponds to C2) if unordered
2986 // ZF (corresponds to C3) if x = y
2987 }
2988
2989 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2990 fcmp2int(dst, unordered_is_less, 1, true, true);
2991 }
2992
2993 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2994 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2995 Label L;
2996 if (unordered_is_less) {
2997 movl(dst, -1);
2998 jcc(Assembler::parity, L);
2999 jcc(Assembler::below , L);
3000 movl(dst, 0);
3001 jcc(Assembler::equal , L);
3002 increment(dst);
3003 } else { // unordered is greater
3004 movl(dst, 1);
3005 jcc(Assembler::parity, L);
3006 jcc(Assembler::above , L);
3007 movl(dst, 0);
3008 jcc(Assembler::equal , L);
3009 decrementl(dst);
3010 }
3011 bind(L);
3012 }
3013
3014 void MacroAssembler::fld_d(AddressLiteral src) {
3015 fld_d(as_Address(src));
3016 }
3017
3018 void MacroAssembler::fld_s(AddressLiteral src) {
3019 fld_s(as_Address(src));
3020 }
3021
3022 void MacroAssembler::fld_x(AddressLiteral src) {
3023 Assembler::fld_x(as_Address(src));
3024 }
3025
3026 void MacroAssembler::fldcw(AddressLiteral src) {
3027 Assembler::fldcw(as_Address(src));
3028 }
3029
3030 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
3031 if (reachable(src)) {
3032 Assembler::mulpd(dst, as_Address(src));
3033 } else {
3034 lea(rscratch1, src);
3035 Assembler::mulpd(dst, Address(rscratch1, 0));
3036 }
3037 }
3038
3039 void MacroAssembler::pow_exp_core_encoding() {
3040 // kills rax, rcx, rdx
3041 subptr(rsp,sizeof(jdouble));
3042 // computes 2^X. Stack: X ...
3043 // f2xm1 computes 2^X-1 but only operates on -1<=X<=1. Get int(X) and
3044 // keep it on the thread's stack to compute 2^int(X) later
3045 // then compute 2^(X-int(X)) as (2^(X-int(X)-1+1)
3046 // final result is obtained with: 2^X = 2^int(X) * 2^(X-int(X))
3047 fld_s(0); // Stack: X X ...
3048 frndint(); // Stack: int(X) X ...
3049 fsuba(1); // Stack: int(X) X-int(X) ...
3050 fistp_s(Address(rsp,0)); // move int(X) as integer to thread's stack. Stack: X-int(X) ...
3051 f2xm1(); // Stack: 2^(X-int(X))-1 ...
3052 fld1(); // Stack: 1 2^(X-int(X))-1 ...
3053 faddp(1); // Stack: 2^(X-int(X))
3054 // computes 2^(int(X)): add exponent bias (1023) to int(X), then
3055 // shift int(X)+1023 to exponent position.
3056 // Exponent is limited to 11 bits if int(X)+1023 does not fit in 11
3057 // bits, set result to NaN. 0x000 and 0x7FF are reserved exponent
3058 // values so detect them and set result to NaN.
3059 movl(rax,Address(rsp,0));
3060 movl(rcx, -2048); // 11 bit mask and valid NaN binary encoding
3061 addl(rax, 1023);
3062 movl(rdx,rax);
3063 shll(rax,20);
3064 // Check that 0 < int(X)+1023 < 2047. Otherwise set rax to NaN.
3065 addl(rdx,1);
3066 // Check that 1 < int(X)+1023+1 < 2048
3067 // in 3 steps:
3068 // 1- (int(X)+1023+1)&-2048 == 0 => 0 <= int(X)+1023+1 < 2048
3069 // 2- (int(X)+1023+1)&-2048 != 0
3070 // 3- (int(X)+1023+1)&-2048 != 1
3071 // Do 2- first because addl just updated the flags.
3072 cmov32(Assembler::equal,rax,rcx);
3073 cmpl(rdx,1);
3074 cmov32(Assembler::equal,rax,rcx);
3075 testl(rdx,rcx);
3076 cmov32(Assembler::notEqual,rax,rcx);
3077 movl(Address(rsp,4),rax);
3078 movl(Address(rsp,0),0);
3079 fmul_d(Address(rsp,0)); // Stack: 2^X ...
3080 addptr(rsp,sizeof(jdouble));
3081 }
3082
3083 void MacroAssembler::increase_precision() {
3084 subptr(rsp, BytesPerWord);
3085 fnstcw(Address(rsp, 0));
3086 movl(rax, Address(rsp, 0));
3087 orl(rax, 0x300);
3088 push(rax);
3089 fldcw(Address(rsp, 0));
3090 pop(rax);
3091 }
3092
3093 void MacroAssembler::restore_precision() {
3094 fldcw(Address(rsp, 0));
3095 addptr(rsp, BytesPerWord);
3096 }
3097
3098 void MacroAssembler::fast_pow() {
3099 // computes X^Y = 2^(Y * log2(X))
3100 // if fast computation is not possible, result is NaN. Requires
3101 // fallback from user of this macro.
3102 // increase precision for intermediate steps of the computation
3103 BLOCK_COMMENT("fast_pow {");
3104 increase_precision();
3105 fyl2x(); // Stack: (Y*log2(X)) ...
3106 pow_exp_core_encoding(); // Stack: exp(X) ...
3107 restore_precision();
3108 BLOCK_COMMENT("} fast_pow");
3109 }
3110
3111 void MacroAssembler::pow_or_exp(int num_fpu_regs_in_use) {
3112 // kills rax, rcx, rdx
3113 // pow and exp needs 2 extra registers on the fpu stack.
3114 Label slow_case, done;
3115 Register tmp = noreg;
3116 if (!VM_Version::supports_cmov()) {
3117 // fcmp needs a temporary so preserve rdx,
3118 tmp = rdx;
3119 }
3120 Register tmp2 = rax;
3121 Register tmp3 = rcx;
3122
3123 // Stack: X Y
3124 Label x_negative, y_not_2;
3125
3126 static double two = 2.0;
3127 ExternalAddress two_addr((address)&two);
3128
3129 // constant maybe too far on 64 bit
3130 lea(tmp2, two_addr);
3131 fld_d(Address(tmp2, 0)); // Stack: 2 X Y
3132 fcmp(tmp, 2, true, false); // Stack: X Y
3133 jcc(Assembler::parity, y_not_2);
3134 jcc(Assembler::notEqual, y_not_2);
3135
3136 fxch(); fpop(); // Stack: X
3137 fmul(0); // Stack: X*X
3138
3139 jmp(done);
3140
3141 bind(y_not_2);
3142
3143 fldz(); // Stack: 0 X Y
3144 fcmp(tmp, 1, true, false); // Stack: X Y
3145 jcc(Assembler::above, x_negative);
3146
3147 // X >= 0
3148
3149 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
3150 fld_s(1); // Stack: X Y X Y
3151 fast_pow(); // Stack: X^Y X Y
3152 fcmp(tmp, 0, false, false); // Stack: X^Y X Y
3153 // X^Y not equal to itself: X^Y is NaN go to slow case.
3154 jcc(Assembler::parity, slow_case);
3155 // get rid of duplicate arguments. Stack: X^Y
3156 if (num_fpu_regs_in_use > 0) {
3157 fxch(); fpop();
3158 fxch(); fpop();
3159 } else {
3160 ffree(2);
3161 ffree(1);
3162 }
3163 jmp(done);
3164
3165 // X <= 0
3166 bind(x_negative);
3167
3168 fld_s(1); // Stack: Y X Y
3169 frndint(); // Stack: int(Y) X Y
3170 fcmp(tmp, 2, false, false); // Stack: int(Y) X Y
3171 jcc(Assembler::notEqual, slow_case);
3172
3173 subptr(rsp, 8);
3174
3175 // For X^Y, when X < 0, Y has to be an integer and the final
3176 // result depends on whether it's odd or even. We just checked
3177 // that int(Y) == Y. We move int(Y) to gp registers as a 64 bit
3178 // integer to test its parity. If int(Y) is huge and doesn't fit
3179 // in the 64 bit integer range, the integer indefinite value will
3180 // end up in the gp registers. Huge numbers are all even, the
3181 // integer indefinite number is even so it's fine.
3182
3183 #ifdef ASSERT
3184 // Let's check we don't end up with an integer indefinite number
3185 // when not expected. First test for huge numbers: check whether
3186 // int(Y)+1 == int(Y) which is true for very large numbers and
3187 // those are all even. A 64 bit integer is guaranteed to not
3188 // overflow for numbers where y+1 != y (when precision is set to
3189 // double precision).
3190 Label y_not_huge;
3191
3192 fld1(); // Stack: 1 int(Y) X Y
3193 fadd(1); // Stack: 1+int(Y) int(Y) X Y
3194
3195 #ifdef _LP64
3196 // trip to memory to force the precision down from double extended
3197 // precision
3198 fstp_d(Address(rsp, 0));
3199 fld_d(Address(rsp, 0));
3200 #endif
3201
3202 fcmp(tmp, 1, true, false); // Stack: int(Y) X Y
3203 #endif
3204
3205 // move int(Y) as 64 bit integer to thread's stack
3206 fistp_d(Address(rsp,0)); // Stack: X Y
3207
3208 #ifdef ASSERT
3209 jcc(Assembler::notEqual, y_not_huge);
3210
3211 // Y is huge so we know it's even. It may not fit in a 64 bit
3212 // integer and we don't want the debug code below to see the
3213 // integer indefinite value so overwrite int(Y) on the thread's
3214 // stack with 0.
3215 movl(Address(rsp, 0), 0);
3216 movl(Address(rsp, 4), 0);
3217
3218 bind(y_not_huge);
3219 #endif
3220
3221 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
3222 fld_s(1); // Stack: X Y X Y
3223 fabs(); // Stack: abs(X) Y X Y
3224 fast_pow(); // Stack: abs(X)^Y X Y
3225 fcmp(tmp, 0, false, false); // Stack: abs(X)^Y X Y
3226 // abs(X)^Y not equal to itself: abs(X)^Y is NaN go to slow case.
3227
3228 pop(tmp2);
3229 NOT_LP64(pop(tmp3));
3230 jcc(Assembler::parity, slow_case);
3231
3232 #ifdef ASSERT
3233 // Check that int(Y) is not integer indefinite value (int
3234 // overflow). Shouldn't happen because for values that would
3235 // overflow, 1+int(Y)==Y which was tested earlier.
3236 #ifndef _LP64
3237 {
3238 Label integer;
3239 testl(tmp2, tmp2);
3240 jcc(Assembler::notZero, integer);
3241 cmpl(tmp3, 0x80000000);
3242 jcc(Assembler::notZero, integer);
3243 STOP("integer indefinite value shouldn't be seen here");
3244 bind(integer);
3245 }
3246 #else
3247 {
3248 Label integer;
3249 mov(tmp3, tmp2); // preserve tmp2 for parity check below
3250 shlq(tmp3, 1);
3251 jcc(Assembler::carryClear, integer);
3252 jcc(Assembler::notZero, integer);
3253 STOP("integer indefinite value shouldn't be seen here");
3254 bind(integer);
3255 }
3256 #endif
3257 #endif
3258
3259 // get rid of duplicate arguments. Stack: X^Y
3260 if (num_fpu_regs_in_use > 0) {
3261 fxch(); fpop();
3262 fxch(); fpop();
3263 } else {
3264 ffree(2);
3265 ffree(1);
3266 }
3267
3268 testl(tmp2, 1);
3269 jcc(Assembler::zero, done); // X <= 0, Y even: X^Y = abs(X)^Y
3270 // X <= 0, Y even: X^Y = -abs(X)^Y
3271
3272 fchs(); // Stack: -abs(X)^Y Y
3273 jmp(done);
3274
3275 // slow case: runtime call
3276 bind(slow_case);
3277
3278 fpop(); // pop incorrect result or int(Y)
3279
3280 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dpow), 2, num_fpu_regs_in_use);
3281
3282 // Come here with result in F-TOS
3283 bind(done);
3284 }
3285
3286 void MacroAssembler::fpop() {
3287 ffree();
3288 fincstp();
3289 }
3290
3291 void MacroAssembler::fremr(Register tmp) {
3292 save_rax(tmp);
3293 { Label L;
3294 bind(L);
3295 fprem();
3296 fwait(); fnstsw_ax();
3297 #ifdef _LP64
3298 testl(rax, 0x400);
3299 jcc(Assembler::notEqual, L);
3300 #else
3301 sahf();
3302 jcc(Assembler::parity, L);
3303 #endif // _LP64
3304 }
3305 restore_rax(tmp);
3306 // Result is in ST0.
3307 // Note: fxch & fpop to get rid of ST1
3308 // (otherwise FPU stack could overflow eventually)
3309 fxch(1);
3310 fpop();
3311 }
3312
3313
3314 void MacroAssembler::incrementl(AddressLiteral dst) {
3315 if (reachable(dst)) {
3316 incrementl(as_Address(dst));
3317 } else {
3318 lea(rscratch1, dst);
3319 incrementl(Address(rscratch1, 0));
3320 }
3321 }
3322
3323 void MacroAssembler::incrementl(ArrayAddress dst) {
3324 incrementl(as_Address(dst));
3325 }
3326
3327 void MacroAssembler::incrementl(Register reg, int value) {
3328 if (value == min_jint) {addl(reg, value) ; return; }
3329 if (value < 0) { decrementl(reg, -value); return; }
3330 if (value == 0) { ; return; }
3331 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3332 /* else */ { addl(reg, value) ; return; }
3333 }
3334
3335 void MacroAssembler::incrementl(Address dst, int value) {
3336 if (value == min_jint) {addl(dst, value) ; return; }
3337 if (value < 0) { decrementl(dst, -value); return; }
3338 if (value == 0) { ; return; }
3339 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3340 /* else */ { addl(dst, value) ; return; }
3341 }
3342
3343 void MacroAssembler::jump(AddressLiteral dst) {
3344 if (reachable(dst)) {
3345 jmp_literal(dst.target(), dst.rspec());
3346 } else {
3347 lea(rscratch1, dst);
3348 jmp(rscratch1);
3349 }
3350 }
3351
3352 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3353 if (reachable(dst)) {
3354 InstructionMark im(this);
3355 relocate(dst.reloc());
3356 const int short_size = 2;
3357 const int long_size = 6;
3358 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3359 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3360 // 0111 tttn #8-bit disp
3361 emit_int8(0x70 | cc);
3362 emit_int8((offs - short_size) & 0xFF);
3363 } else {
3364 // 0000 1111 1000 tttn #32-bit disp
3365 emit_int8(0x0F);
3366 emit_int8((unsigned char)(0x80 | cc));
3367 emit_int32(offs - long_size);
3368 }
3369 } else {
3370 #ifdef ASSERT
3371 warning("reversing conditional branch");
3372 #endif /* ASSERT */
3373 Label skip;
3374 jccb(reverse[cc], skip);
3375 lea(rscratch1, dst);
3376 Assembler::jmp(rscratch1);
3377 bind(skip);
3378 }
3379 }
3380
3381 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3382 if (reachable(src)) {
3383 Assembler::ldmxcsr(as_Address(src));
3384 } else {
3385 lea(rscratch1, src);
3386 Assembler::ldmxcsr(Address(rscratch1, 0));
3387 }
3388 }
3389
3390 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3391 int off;
3392 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3393 off = offset();
3394 movsbl(dst, src); // movsxb
3395 } else {
3396 off = load_unsigned_byte(dst, src);
3397 shll(dst, 24);
3398 sarl(dst, 24);
3399 }
3400 return off;
3401 }
3402
3403 // Note: load_signed_short used to be called load_signed_word.
3404 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3405 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3406 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3407 int MacroAssembler::load_signed_short(Register dst, Address src) {
3408 int off;
3409 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3410 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3411 // version but this is what 64bit has always done. This seems to imply
3412 // that users are only using 32bits worth.
3413 off = offset();
3414 movswl(dst, src); // movsxw
3415 } else {
3416 off = load_unsigned_short(dst, src);
3417 shll(dst, 16);
3418 sarl(dst, 16);
3419 }
3420 return off;
3421 }
3422
3423 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3424 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3425 // and "3.9 Partial Register Penalties", p. 22).
3426 int off;
3427 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3428 off = offset();
3429 movzbl(dst, src); // movzxb
3430 } else {
3431 xorl(dst, dst);
3432 off = offset();
3433 movb(dst, src);
3434 }
3435 return off;
3436 }
3437
3438 // Note: load_unsigned_short used to be called load_unsigned_word.
3439 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3440 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3441 // and "3.9 Partial Register Penalties", p. 22).
3442 int off;
3443 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3444 off = offset();
3445 movzwl(dst, src); // movzxw
3446 } else {
3447 xorl(dst, dst);
3448 off = offset();
3449 movw(dst, src);
3450 }
3451 return off;
3452 }
3453
3454 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3455 switch (size_in_bytes) {
3456 #ifndef _LP64
3457 case 8:
3458 assert(dst2 != noreg, "second dest register required");
3459 movl(dst, src);
3460 movl(dst2, src.plus_disp(BytesPerInt));
3461 break;
3462 #else
3463 case 8: movq(dst, src); break;
3464 #endif
3465 case 4: movl(dst, src); break;
3466 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3467 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3468 default: ShouldNotReachHere();
3469 }
3470 }
3471
3472 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3473 switch (size_in_bytes) {
3474 #ifndef _LP64
3475 case 8:
3476 assert(src2 != noreg, "second source register required");
3477 movl(dst, src);
3478 movl(dst.plus_disp(BytesPerInt), src2);
3479 break;
3480 #else
3481 case 8: movq(dst, src); break;
3482 #endif
3483 case 4: movl(dst, src); break;
3484 case 2: movw(dst, src); break;
3485 case 1: movb(dst, src); break;
3486 default: ShouldNotReachHere();
3487 }
3488 }
3489
3490 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3491 if (reachable(dst)) {
3492 movl(as_Address(dst), src);
3493 } else {
3494 lea(rscratch1, dst);
3495 movl(Address(rscratch1, 0), src);
3496 }
3497 }
3498
3499 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3500 if (reachable(src)) {
3501 movl(dst, as_Address(src));
3502 } else {
3503 lea(rscratch1, src);
3504 movl(dst, Address(rscratch1, 0));
3505 }
3506 }
3507
3508 // C++ bool manipulation
3509
3510 void MacroAssembler::movbool(Register dst, Address src) {
3511 if(sizeof(bool) == 1)
3512 movb(dst, src);
3513 else if(sizeof(bool) == 2)
3514 movw(dst, src);
3515 else if(sizeof(bool) == 4)
3516 movl(dst, src);
3517 else
3518 // unsupported
3519 ShouldNotReachHere();
3520 }
3521
3522 void MacroAssembler::movbool(Address dst, bool boolconst) {
3523 if(sizeof(bool) == 1)
3524 movb(dst, (int) boolconst);
3525 else if(sizeof(bool) == 2)
3526 movw(dst, (int) boolconst);
3527 else if(sizeof(bool) == 4)
3528 movl(dst, (int) boolconst);
3529 else
3530 // unsupported
3531 ShouldNotReachHere();
3532 }
3533
3534 void MacroAssembler::movbool(Address dst, Register src) {
3535 if(sizeof(bool) == 1)
3536 movb(dst, src);
3537 else if(sizeof(bool) == 2)
3538 movw(dst, src);
3539 else if(sizeof(bool) == 4)
3540 movl(dst, src);
3541 else
3542 // unsupported
3543 ShouldNotReachHere();
3544 }
3545
3546 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3547 movb(as_Address(dst), src);
3548 }
3549
3550 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3551 if (reachable(src)) {
3552 movdl(dst, as_Address(src));
3553 } else {
3554 lea(rscratch1, src);
3555 movdl(dst, Address(rscratch1, 0));
3556 }
3557 }
3558
3559 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3560 if (reachable(src)) {
3561 movq(dst, as_Address(src));
3562 } else {
3563 lea(rscratch1, src);
3564 movq(dst, Address(rscratch1, 0));
3565 }
3566 }
3567
3568 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3569 if (reachable(src)) {
3570 if (UseXmmLoadAndClearUpper) {
3571 movsd (dst, as_Address(src));
3572 } else {
3573 movlpd(dst, as_Address(src));
3574 }
3575 } else {
3576 lea(rscratch1, src);
3577 if (UseXmmLoadAndClearUpper) {
3578 movsd (dst, Address(rscratch1, 0));
3579 } else {
3580 movlpd(dst, Address(rscratch1, 0));
3581 }
3582 }
3583 }
3584
3585 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3586 if (reachable(src)) {
3587 movss(dst, as_Address(src));
3588 } else {
3589 lea(rscratch1, src);
3590 movss(dst, Address(rscratch1, 0));
3591 }
3592 }
3593
3594 void MacroAssembler::movptr(Register dst, Register src) {
3595 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3596 }
3597
3598 void MacroAssembler::movptr(Register dst, Address src) {
3599 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3600 }
3601
3602 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3603 void MacroAssembler::movptr(Register dst, intptr_t src) {
3604 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3605 }
3606
3607 void MacroAssembler::movptr(Address dst, Register src) {
3608 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3609 }
3610
3611 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) {
3612 if (reachable(src)) {
3613 Assembler::movdqu(dst, as_Address(src));
3614 } else {
3615 lea(rscratch1, src);
3616 Assembler::movdqu(dst, Address(rscratch1, 0));
3617 }
3618 }
3619
3620 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3621 if (reachable(src)) {
3622 Assembler::movdqa(dst, as_Address(src));
3623 } else {
3624 lea(rscratch1, src);
3625 Assembler::movdqa(dst, Address(rscratch1, 0));
3626 }
3627 }
3628
3629 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3630 if (reachable(src)) {
3631 Assembler::movsd(dst, as_Address(src));
3632 } else {
3633 lea(rscratch1, src);
3634 Assembler::movsd(dst, Address(rscratch1, 0));
3635 }
3636 }
3637
3638 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3639 if (reachable(src)) {
3640 Assembler::movss(dst, as_Address(src));
3641 } else {
3642 lea(rscratch1, src);
3643 Assembler::movss(dst, Address(rscratch1, 0));
3644 }
3645 }
3646
3647 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3648 if (reachable(src)) {
3649 Assembler::mulsd(dst, as_Address(src));
3650 } else {
3651 lea(rscratch1, src);
3652 Assembler::mulsd(dst, Address(rscratch1, 0));
3653 }
3654 }
3655
3656 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3657 if (reachable(src)) {
3658 Assembler::mulss(dst, as_Address(src));
3659 } else {
3660 lea(rscratch1, src);
3661 Assembler::mulss(dst, Address(rscratch1, 0));
3662 }
3663 }
3664
3665 void MacroAssembler::null_check(Register reg, int offset) {
3666 if (needs_explicit_null_check(offset)) {
3667 // provoke OS NULL exception if reg = NULL by
3668 // accessing M[reg] w/o changing any (non-CC) registers
3669 // NOTE: cmpl is plenty here to provoke a segv
3670 cmpptr(rax, Address(reg, 0));
3671 // Note: should probably use testl(rax, Address(reg, 0));
3672 // may be shorter code (however, this version of
3673 // testl needs to be implemented first)
3674 } else {
3675 // nothing to do, (later) access of M[reg + offset]
3676 // will provoke OS NULL exception if reg = NULL
3677 }
3678 }
3679
3680 void MacroAssembler::os_breakpoint() {
3681 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3682 // (e.g., MSVC can't call ps() otherwise)
3683 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3684 }
3685
3686 void MacroAssembler::pop_CPU_state() {
3687 pop_FPU_state();
3688 pop_IU_state();
3689 }
3690
3691 void MacroAssembler::pop_FPU_state() {
3692 NOT_LP64(frstor(Address(rsp, 0));)
3693 LP64_ONLY(fxrstor(Address(rsp, 0));)
3694 addptr(rsp, FPUStateSizeInWords * wordSize);
3695 }
3696
3697 void MacroAssembler::pop_IU_state() {
3698 popa();
3699 LP64_ONLY(addq(rsp, 8));
3700 popf();
3701 }
3702
3703 // Save Integer and Float state
3704 // Warning: Stack must be 16 byte aligned (64bit)
3705 void MacroAssembler::push_CPU_state() {
3706 push_IU_state();
3707 push_FPU_state();
3708 }
3709
3710 void MacroAssembler::push_FPU_state() {
3711 subptr(rsp, FPUStateSizeInWords * wordSize);
3712 #ifndef _LP64
3713 fnsave(Address(rsp, 0));
3714 fwait();
3715 #else
3716 fxsave(Address(rsp, 0));
3717 #endif // LP64
3718 }
3719
3720 void MacroAssembler::push_IU_state() {
3721 // Push flags first because pusha kills them
3722 pushf();
3723 // Make sure rsp stays 16-byte aligned
3724 LP64_ONLY(subq(rsp, 8));
3725 pusha();
3726 }
3727
3728 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
3729 // determine java_thread register
3730 if (!java_thread->is_valid()) {
3731 java_thread = rdi;
3732 get_thread(java_thread);
3733 }
3734 // we must set sp to zero to clear frame
3735 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3736 if (clear_fp) {
3737 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3738 }
3739
3740 if (clear_pc)
3741 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3742
3743 }
3744
3745 void MacroAssembler::restore_rax(Register tmp) {
3746 if (tmp == noreg) pop(rax);
3747 else if (tmp != rax) mov(rax, tmp);
3748 }
3749
3750 void MacroAssembler::round_to(Register reg, int modulus) {
3751 addptr(reg, modulus - 1);
3752 andptr(reg, -modulus);
3753 }
3754
3755 void MacroAssembler::save_rax(Register tmp) {
3756 if (tmp == noreg) push(rax);
3757 else if (tmp != rax) mov(tmp, rax);
3758 }
3759
3760 // Write serialization page so VM thread can do a pseudo remote membar.
3761 // We use the current thread pointer to calculate a thread specific
3762 // offset to write to within the page. This minimizes bus traffic
3763 // due to cache line collision.
3764 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3765 movl(tmp, thread);
3766 shrl(tmp, os::get_serialize_page_shift_count());
3767 andl(tmp, (os::vm_page_size() - sizeof(int)));
3768
3769 Address index(noreg, tmp, Address::times_1);
3770 ExternalAddress page(os::get_memory_serialize_page());
3771
3772 // Size of store must match masking code above
3773 movl(as_Address(ArrayAddress(page, index)), tmp);
3774 }
3775
3776 // Calls to C land
3777 //
3778 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3779 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3780 // has to be reset to 0. This is required to allow proper stack traversal.
3781 void MacroAssembler::set_last_Java_frame(Register java_thread,
3782 Register last_java_sp,
3783 Register last_java_fp,
3784 address last_java_pc) {
3785 // determine java_thread register
3786 if (!java_thread->is_valid()) {
3787 java_thread = rdi;
3788 get_thread(java_thread);
3789 }
3790 // determine last_java_sp register
3791 if (!last_java_sp->is_valid()) {
3792 last_java_sp = rsp;
3793 }
3794
3795 // last_java_fp is optional
3796
3797 if (last_java_fp->is_valid()) {
3798 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3799 }
3800
3801 // last_java_pc is optional
3802
3803 if (last_java_pc != NULL) {
3804 lea(Address(java_thread,
3805 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3806 InternalAddress(last_java_pc));
3807
3808 }
3809 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3810 }
3811
3812 void MacroAssembler::shlptr(Register dst, int imm8) {
3813 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3814 }
3815
3816 void MacroAssembler::shrptr(Register dst, int imm8) {
3817 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3818 }
3819
3820 void MacroAssembler::sign_extend_byte(Register reg) {
3821 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3822 movsbl(reg, reg); // movsxb
3823 } else {
3824 shll(reg, 24);
3825 sarl(reg, 24);
3826 }
3827 }
3828
3829 void MacroAssembler::sign_extend_short(Register reg) {
3830 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3831 movswl(reg, reg); // movsxw
3832 } else {
3833 shll(reg, 16);
3834 sarl(reg, 16);
3835 }
3836 }
3837
3838 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3839 assert(reachable(src), "Address should be reachable");
3840 testl(dst, as_Address(src));
3841 }
3842
3843 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3844 if (reachable(src)) {
3845 Assembler::sqrtsd(dst, as_Address(src));
3846 } else {
3847 lea(rscratch1, src);
3848 Assembler::sqrtsd(dst, Address(rscratch1, 0));
3849 }
3850 }
3851
3852 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3853 if (reachable(src)) {
3854 Assembler::sqrtss(dst, as_Address(src));
3855 } else {
3856 lea(rscratch1, src);
3857 Assembler::sqrtss(dst, Address(rscratch1, 0));
3858 }
3859 }
3860
3861 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
3862 if (reachable(src)) {
3863 Assembler::subsd(dst, as_Address(src));
3864 } else {
3865 lea(rscratch1, src);
3866 Assembler::subsd(dst, Address(rscratch1, 0));
3867 }
3868 }
3869
3870 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
3871 if (reachable(src)) {
3872 Assembler::subss(dst, as_Address(src));
3873 } else {
3874 lea(rscratch1, src);
3875 Assembler::subss(dst, Address(rscratch1, 0));
3876 }
3877 }
3878
3879 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
3880 if (reachable(src)) {
3881 Assembler::ucomisd(dst, as_Address(src));
3882 } else {
3883 lea(rscratch1, src);
3884 Assembler::ucomisd(dst, Address(rscratch1, 0));
3885 }
3886 }
3887
3888 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3889 if (reachable(src)) {
3890 Assembler::ucomiss(dst, as_Address(src));
3891 } else {
3892 lea(rscratch1, src);
3893 Assembler::ucomiss(dst, Address(rscratch1, 0));
3894 }
3895 }
3896
3897 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
3898 // Used in sign-bit flipping with aligned address.
3899 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3900 if (reachable(src)) {
3901 Assembler::xorpd(dst, as_Address(src));
3902 } else {
3903 lea(rscratch1, src);
3904 Assembler::xorpd(dst, Address(rscratch1, 0));
3905 }
3906 }
3907
3908 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
3909 // Used in sign-bit flipping with aligned address.
3910 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3911 if (reachable(src)) {
3912 Assembler::xorps(dst, as_Address(src));
3913 } else {
3914 lea(rscratch1, src);
3915 Assembler::xorps(dst, Address(rscratch1, 0));
3916 }
3917 }
3918
3919 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
3920 // Used in sign-bit flipping with aligned address.
3921 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3922 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3923 if (reachable(src)) {
3924 Assembler::pshufb(dst, as_Address(src));
3925 } else {
3926 lea(rscratch1, src);
3927 Assembler::pshufb(dst, Address(rscratch1, 0));
3928 }
3929 }
3930
3931 // AVX 3-operands instructions
3932
3933 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3934 if (reachable(src)) {
3935 vaddsd(dst, nds, as_Address(src));
3936 } else {
3937 lea(rscratch1, src);
3938 vaddsd(dst, nds, Address(rscratch1, 0));
3939 }
3940 }
3941
3942 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3943 if (reachable(src)) {
3944 vaddss(dst, nds, as_Address(src));
3945 } else {
3946 lea(rscratch1, src);
3947 vaddss(dst, nds, Address(rscratch1, 0));
3948 }
3949 }
3950
3951 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
3952 if (reachable(src)) {
3953 vandpd(dst, nds, as_Address(src), vector_len);
3954 } else {
3955 lea(rscratch1, src);
3956 vandpd(dst, nds, Address(rscratch1, 0), vector_len);
3957 }
3958 }
3959
3960 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
3961 if (reachable(src)) {
3962 vandps(dst, nds, as_Address(src), vector_len);
3963 } else {
3964 lea(rscratch1, src);
3965 vandps(dst, nds, Address(rscratch1, 0), vector_len);
3966 }
3967 }
3968
3969 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3970 if (reachable(src)) {
3971 vdivsd(dst, nds, as_Address(src));
3972 } else {
3973 lea(rscratch1, src);
3974 vdivsd(dst, nds, Address(rscratch1, 0));
3975 }
3976 }
3977
3978 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3979 if (reachable(src)) {
3980 vdivss(dst, nds, as_Address(src));
3981 } else {
3982 lea(rscratch1, src);
3983 vdivss(dst, nds, Address(rscratch1, 0));
3984 }
3985 }
3986
3987 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3988 if (reachable(src)) {
3989 vmulsd(dst, nds, as_Address(src));
3990 } else {
3991 lea(rscratch1, src);
3992 vmulsd(dst, nds, Address(rscratch1, 0));
3993 }
3994 }
3995
3996 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3997 if (reachable(src)) {
3998 vmulss(dst, nds, as_Address(src));
3999 } else {
4000 lea(rscratch1, src);
4001 vmulss(dst, nds, Address(rscratch1, 0));
4002 }
4003 }
4004
4005 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4006 if (reachable(src)) {
4007 vsubsd(dst, nds, as_Address(src));
4008 } else {
4009 lea(rscratch1, src);
4010 vsubsd(dst, nds, Address(rscratch1, 0));
4011 }
4012 }
4013
4014 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4015 if (reachable(src)) {
4016 vsubss(dst, nds, as_Address(src));
4017 } else {
4018 lea(rscratch1, src);
4019 vsubss(dst, nds, Address(rscratch1, 0));
4020 }
4021 }
4022
4023 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4024 if (reachable(src)) {
4025 vxorpd(dst, nds, as_Address(src), vector_len);
4026 } else {
4027 lea(rscratch1, src);
4028 vxorpd(dst, nds, Address(rscratch1, 0), vector_len);
4029 }
4030 }
4031
4032 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4033 if (reachable(src)) {
4034 vxorps(dst, nds, as_Address(src), vector_len);
4035 } else {
4036 lea(rscratch1, src);
4037 vxorps(dst, nds, Address(rscratch1, 0), vector_len);
4038 }
4039 }
4040
4041
4042 //////////////////////////////////////////////////////////////////////////////////
4043 #if INCLUDE_ALL_GCS
4044
4045 void MacroAssembler::g1_write_barrier_pre(Register obj,
4046 Register pre_val,
4047 Register thread,
4048 Register tmp,
4049 bool tosca_live,
4050 bool expand_call) {
4051
4052 // If expand_call is true then we expand the call_VM_leaf macro
4053 // directly to skip generating the check by
4054 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
4055
4056 #ifdef _LP64
4057 assert(thread == r15_thread, "must be");
4058 #endif // _LP64
4059
4060 Label done;
4061 Label runtime;
4062
4063 assert(pre_val != noreg, "check this code");
4064
4065 if (obj != noreg) {
4066 assert_different_registers(obj, pre_val, tmp);
4067 assert(pre_val != rax, "check this code");
4068 }
4069
4070 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4071 PtrQueue::byte_offset_of_active()));
4072 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4073 PtrQueue::byte_offset_of_index()));
4074 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4075 PtrQueue::byte_offset_of_buf()));
4076
4077
4078 // Is marking active?
4079 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
4080 cmpl(in_progress, 0);
4081 } else {
4082 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
4083 cmpb(in_progress, 0);
4084 }
4085 jcc(Assembler::equal, done);
4086
4087 // Do we need to load the previous value?
4088 if (obj != noreg) {
4089 load_heap_oop(pre_val, Address(obj, 0));
4090 }
4091
4092 // Is the previous value null?
4093 cmpptr(pre_val, (int32_t) NULL_WORD);
4094 jcc(Assembler::equal, done);
4095
4096 // Can we store original value in the thread's buffer?
4097 // Is index == 0?
4098 // (The index field is typed as size_t.)
4099
4100 movptr(tmp, index); // tmp := *index_adr
4101 cmpptr(tmp, 0); // tmp == 0?
4102 jcc(Assembler::equal, runtime); // If yes, goto runtime
4103
4104 subptr(tmp, wordSize); // tmp := tmp - wordSize
4105 movptr(index, tmp); // *index_adr := tmp
4106 addptr(tmp, buffer); // tmp := tmp + *buffer_adr
4107
4108 // Record the previous value
4109 movptr(Address(tmp, 0), pre_val);
4110 jmp(done);
4111
4112 bind(runtime);
4113 // save the live input values
4114 if(tosca_live) push(rax);
4115
4116 if (obj != noreg && obj != rax)
4117 push(obj);
4118
4119 if (pre_val != rax)
4120 push(pre_val);
4121
4122 // Calling the runtime using the regular call_VM_leaf mechanism generates
4123 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
4124 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
4125 //
4126 // If we care generating the pre-barrier without a frame (e.g. in the
4127 // intrinsified Reference.get() routine) then ebp might be pointing to
4128 // the caller frame and so this check will most likely fail at runtime.
4129 //
4130 // Expanding the call directly bypasses the generation of the check.
4131 // So when we do not have have a full interpreter frame on the stack
4132 // expand_call should be passed true.
4133
4134 NOT_LP64( push(thread); )
4135
4136 if (expand_call) {
4137 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
4138 pass_arg1(this, thread);
4139 pass_arg0(this, pre_val);
4140 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
4141 } else {
4142 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
4143 }
4144
4145 NOT_LP64( pop(thread); )
4146
4147 // save the live input values
4148 if (pre_val != rax)
4149 pop(pre_val);
4150
4151 if (obj != noreg && obj != rax)
4152 pop(obj);
4153
4154 if(tosca_live) pop(rax);
4155
4156 bind(done);
4157 }
4158
4159 void MacroAssembler::g1_write_barrier_post(Register store_addr,
4160 Register new_val,
4161 Register thread,
4162 Register tmp,
4163 Register tmp2) {
4164 #ifdef _LP64
4165 assert(thread == r15_thread, "must be");
4166 #endif // _LP64
4167
4168 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
4169 PtrQueue::byte_offset_of_index()));
4170 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
4171 PtrQueue::byte_offset_of_buf()));
4172
4173 CardTableModRefBS* ct =
4174 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set());
4175 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
4176
4177 Label done;
4178 Label runtime;
4179
4180 // Does store cross heap regions?
4181
4182 movptr(tmp, store_addr);
4183 xorptr(tmp, new_val);
4184 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
4185 jcc(Assembler::equal, done);
4186
4187 // crosses regions, storing NULL?
4188
4189 cmpptr(new_val, (int32_t) NULL_WORD);
4190 jcc(Assembler::equal, done);
4191
4192 // storing region crossing non-NULL, is card already dirty?
4193
4194 const Register card_addr = tmp;
4195 const Register cardtable = tmp2;
4196
4197 movptr(card_addr, store_addr);
4198 shrptr(card_addr, CardTableModRefBS::card_shift);
4199 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
4200 // a valid address and therefore is not properly handled by the relocation code.
4201 movptr(cardtable, (intptr_t)ct->byte_map_base);
4202 addptr(card_addr, cardtable);
4203
4204 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
4205 jcc(Assembler::equal, done);
4206
4207 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4208 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
4209 jcc(Assembler::equal, done);
4210
4211
4212 // storing a region crossing, non-NULL oop, card is clean.
4213 // dirty card and log.
4214
4215 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
4216
4217 cmpl(queue_index, 0);
4218 jcc(Assembler::equal, runtime);
4219 subl(queue_index, wordSize);
4220 movptr(tmp2, buffer);
4221 #ifdef _LP64
4222 movslq(rscratch1, queue_index);
4223 addq(tmp2, rscratch1);
4224 movq(Address(tmp2, 0), card_addr);
4225 #else
4226 addl(tmp2, queue_index);
4227 movl(Address(tmp2, 0), card_addr);
4228 #endif
4229 jmp(done);
4230
4231 bind(runtime);
4232 // save the live input values
4233 push(store_addr);
4234 push(new_val);
4235 #ifdef _LP64
4236 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
4237 #else
4238 push(thread);
4239 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
4240 pop(thread);
4241 #endif
4242 pop(new_val);
4243 pop(store_addr);
4244
4245 bind(done);
4246 }
4247
4248 #endif // INCLUDE_ALL_GCS
4249 //////////////////////////////////////////////////////////////////////////////////
4250
4251
4252 void MacroAssembler::store_check(Register obj, Address dst) {
4253 store_check(obj);
4254 }
4255
4256 void MacroAssembler::store_check(Register obj) {
4257 // Does a store check for the oop in register obj. The content of
4258 // register obj is destroyed afterwards.
4259
4260 BarrierSet* bs = Universe::heap()->barrier_set();
4261 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
4262
4263 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
4264 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
4265
4266 shrptr(obj, CardTableModRefBS::card_shift);
4267
4268 Address card_addr;
4269
4270 // The calculation for byte_map_base is as follows:
4271 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
4272 // So this essentially converts an address to a displacement and it will
4273 // never need to be relocated. On 64bit however the value may be too
4274 // large for a 32bit displacement.
4275 intptr_t disp = (intptr_t) ct->byte_map_base;
4276 if (is_simm32(disp)) {
4277 card_addr = Address(noreg, obj, Address::times_1, disp);
4278 } else {
4279 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative
4280 // displacement and done in a single instruction given favorable mapping and a
4281 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation
4282 // entry and that entry is not properly handled by the relocation code.
4283 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none);
4284 Address index(noreg, obj, Address::times_1);
4285 card_addr = as_Address(ArrayAddress(cardtable, index));
4286 }
4287
4288 int dirty = CardTableModRefBS::dirty_card_val();
4289 if (UseCondCardMark) {
4290 Label L_already_dirty;
4291 if (UseConcMarkSweepGC) {
4292 membar(Assembler::StoreLoad);
4293 }
4294 cmpb(card_addr, dirty);
4295 jcc(Assembler::equal, L_already_dirty);
4296 movb(card_addr, dirty);
4297 bind(L_already_dirty);
4298 } else {
4299 movb(card_addr, dirty);
4300 }
4301 }
4302
4303 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4304 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4305 }
4306
4307 // Force generation of a 4 byte immediate value even if it fits into 8bit
4308 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4309 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4310 }
4311
4312 void MacroAssembler::subptr(Register dst, Register src) {
4313 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4314 }
4315
4316 // C++ bool manipulation
4317 void MacroAssembler::testbool(Register dst) {
4318 if(sizeof(bool) == 1)
4319 testb(dst, 0xff);
4320 else if(sizeof(bool) == 2) {
4321 // testw implementation needed for two byte bools
4322 ShouldNotReachHere();
4323 } else if(sizeof(bool) == 4)
4324 testl(dst, dst);
4325 else
4326 // unsupported
4327 ShouldNotReachHere();
4328 }
4329
4330 void MacroAssembler::testptr(Register dst, Register src) {
4331 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4332 }
4333
4334 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4335 void MacroAssembler::tlab_allocate(Register obj,
4336 Register var_size_in_bytes,
4337 int con_size_in_bytes,
4338 Register t1,
4339 Register t2,
4340 Label& slow_case) {
4341 assert_different_registers(obj, t1, t2);
4342 assert_different_registers(obj, var_size_in_bytes, t1);
4343 Register end = t2;
4344 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
4345
4346 verify_tlab();
4347
4348 NOT_LP64(get_thread(thread));
4349
4350 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
4351 if (var_size_in_bytes == noreg) {
4352 lea(end, Address(obj, con_size_in_bytes));
4353 } else {
4354 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
4355 }
4356 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
4357 jcc(Assembler::above, slow_case);
4358
4359 // update the tlab top pointer
4360 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
4361
4362 // recover var_size_in_bytes if necessary
4363 if (var_size_in_bytes == end) {
4364 subptr(var_size_in_bytes, obj);
4365 }
4366 verify_tlab();
4367 }
4368
4369 // Preserves rbx, and rdx.
4370 Register MacroAssembler::tlab_refill(Label& retry,
4371 Label& try_eden,
4372 Label& slow_case) {
4373 Register top = rax;
4374 Register t1 = rcx;
4375 Register t2 = rsi;
4376 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
4377 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
4378 Label do_refill, discard_tlab;
4379
4380 if (!Universe::heap()->supports_inline_contig_alloc()) {
4381 // No allocation in the shared eden.
4382 jmp(slow_case);
4383 }
4384
4385 NOT_LP64(get_thread(thread_reg));
4386
4387 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4388 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4389
4390 // calculate amount of free space
4391 subptr(t1, top);
4392 shrptr(t1, LogHeapWordSize);
4393
4394 // Retain tlab and allocate object in shared space if
4395 // the amount free in the tlab is too large to discard.
4396 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
4397 jcc(Assembler::lessEqual, discard_tlab);
4398
4399 // Retain
4400 // %%% yuck as movptr...
4401 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
4402 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
4403 if (TLABStats) {
4404 // increment number of slow_allocations
4405 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
4406 }
4407 jmp(try_eden);
4408
4409 bind(discard_tlab);
4410 if (TLABStats) {
4411 // increment number of refills
4412 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
4413 // accumulate wastage -- t1 is amount free in tlab
4414 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
4415 }
4416
4417 // if tlab is currently allocated (top or end != null) then
4418 // fill [top, end + alignment_reserve) with array object
4419 testptr(top, top);
4420 jcc(Assembler::zero, do_refill);
4421
4422 // set up the mark word
4423 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
4424 // set the length to the remaining space
4425 subptr(t1, typeArrayOopDesc::header_size(T_INT));
4426 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
4427 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
4428 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
4429 // set klass to intArrayKlass
4430 // dubious reloc why not an oop reloc?
4431 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
4432 // store klass last. concurrent gcs assumes klass length is valid if
4433 // klass field is not null.
4434 store_klass(top, t1);
4435
4436 movptr(t1, top);
4437 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4438 incr_allocated_bytes(thread_reg, t1, 0);
4439
4440 // refill the tlab with an eden allocation
4441 bind(do_refill);
4442 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4443 shlptr(t1, LogHeapWordSize);
4444 // allocate new tlab, address returned in top
4445 eden_allocate(top, t1, 0, t2, slow_case);
4446
4447 // Check that t1 was preserved in eden_allocate.
4448 #ifdef ASSERT
4449 if (UseTLAB) {
4450 Label ok;
4451 Register tsize = rsi;
4452 assert_different_registers(tsize, thread_reg, t1);
4453 push(tsize);
4454 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4455 shlptr(tsize, LogHeapWordSize);
4456 cmpptr(t1, tsize);
4457 jcc(Assembler::equal, ok);
4458 STOP("assert(t1 != tlab size)");
4459 should_not_reach_here();
4460
4461 bind(ok);
4462 pop(tsize);
4463 }
4464 #endif
4465 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
4466 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
4467 addptr(top, t1);
4468 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
4469 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
4470 verify_tlab();
4471 jmp(retry);
4472
4473 return thread_reg; // for use by caller
4474 }
4475
4476 void MacroAssembler::incr_allocated_bytes(Register thread,
4477 Register var_size_in_bytes,
4478 int con_size_in_bytes,
4479 Register t1) {
4480 if (!thread->is_valid()) {
4481 #ifdef _LP64
4482 thread = r15_thread;
4483 #else
4484 assert(t1->is_valid(), "need temp reg");
4485 thread = t1;
4486 get_thread(thread);
4487 #endif
4488 }
4489
4490 #ifdef _LP64
4491 if (var_size_in_bytes->is_valid()) {
4492 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
4493 } else {
4494 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
4495 }
4496 #else
4497 if (var_size_in_bytes->is_valid()) {
4498 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
4499 } else {
4500 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
4501 }
4502 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
4503 #endif
4504 }
4505
4506 void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) {
4507 pusha();
4508
4509 // if we are coming from c1, xmm registers may be live
4510 int off = 0;
4511 if (UseSSE == 1) {
4512 subptr(rsp, sizeof(jdouble)*8);
4513 movflt(Address(rsp,off++*sizeof(jdouble)),xmm0);
4514 movflt(Address(rsp,off++*sizeof(jdouble)),xmm1);
4515 movflt(Address(rsp,off++*sizeof(jdouble)),xmm2);
4516 movflt(Address(rsp,off++*sizeof(jdouble)),xmm3);
4517 movflt(Address(rsp,off++*sizeof(jdouble)),xmm4);
4518 movflt(Address(rsp,off++*sizeof(jdouble)),xmm5);
4519 movflt(Address(rsp,off++*sizeof(jdouble)),xmm6);
4520 movflt(Address(rsp,off++*sizeof(jdouble)),xmm7);
4521 } else if (UseSSE >= 2) {
4522 if (UseAVX > 2) {
4523 movl(rbx, 0xffff);
4524 #ifdef _LP64
4525 kmovql(k1, rbx);
4526 #else
4527 kmovdl(k1, rbx);
4528 #endif
4529 }
4530 #ifdef COMPILER2
4531 if (MaxVectorSize > 16) {
4532 assert(UseAVX > 0, "256bit vectors are supported only with AVX");
4533 // Save upper half of YMM registes
4534 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4535 vextractf128h(Address(rsp, 0),xmm0);
4536 vextractf128h(Address(rsp, 16),xmm1);
4537 vextractf128h(Address(rsp, 32),xmm2);
4538 vextractf128h(Address(rsp, 48),xmm3);
4539 vextractf128h(Address(rsp, 64),xmm4);
4540 vextractf128h(Address(rsp, 80),xmm5);
4541 vextractf128h(Address(rsp, 96),xmm6);
4542 vextractf128h(Address(rsp,112),xmm7);
4543 #ifdef _LP64
4544 vextractf128h(Address(rsp,128),xmm8);
4545 vextractf128h(Address(rsp,144),xmm9);
4546 vextractf128h(Address(rsp,160),xmm10);
4547 vextractf128h(Address(rsp,176),xmm11);
4548 vextractf128h(Address(rsp,192),xmm12);
4549 vextractf128h(Address(rsp,208),xmm13);
4550 vextractf128h(Address(rsp,224),xmm14);
4551 vextractf128h(Address(rsp,240),xmm15);
4552 #endif
4553 }
4554 #endif
4555 // Save whole 128bit (16 bytes) XMM regiters
4556 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4557 movdqu(Address(rsp,off++*16),xmm0);
4558 movdqu(Address(rsp,off++*16),xmm1);
4559 movdqu(Address(rsp,off++*16),xmm2);
4560 movdqu(Address(rsp,off++*16),xmm3);
4561 movdqu(Address(rsp,off++*16),xmm4);
4562 movdqu(Address(rsp,off++*16),xmm5);
4563 movdqu(Address(rsp,off++*16),xmm6);
4564 movdqu(Address(rsp,off++*16),xmm7);
4565 #ifdef _LP64
4566 movdqu(Address(rsp,off++*16),xmm8);
4567 movdqu(Address(rsp,off++*16),xmm9);
4568 movdqu(Address(rsp,off++*16),xmm10);
4569 movdqu(Address(rsp,off++*16),xmm11);
4570 movdqu(Address(rsp,off++*16),xmm12);
4571 movdqu(Address(rsp,off++*16),xmm13);
4572 movdqu(Address(rsp,off++*16),xmm14);
4573 movdqu(Address(rsp,off++*16),xmm15);
4574 #endif
4575 }
4576
4577 // Preserve registers across runtime call
4578 int incoming_argument_and_return_value_offset = -1;
4579 if (num_fpu_regs_in_use > 1) {
4580 // Must preserve all other FPU regs (could alternatively convert
4581 // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash
4582 // FPU state, but can not trust C compiler)
4583 NEEDS_CLEANUP;
4584 // NOTE that in this case we also push the incoming argument(s) to
4585 // the stack and restore it later; we also use this stack slot to
4586 // hold the return value from dsin, dcos etc.
4587 for (int i = 0; i < num_fpu_regs_in_use; i++) {
4588 subptr(rsp, sizeof(jdouble));
4589 fstp_d(Address(rsp, 0));
4590 }
4591 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
4592 for (int i = nb_args-1; i >= 0; i--) {
4593 fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble)));
4594 }
4595 }
4596
4597 subptr(rsp, nb_args*sizeof(jdouble));
4598 for (int i = 0; i < nb_args; i++) {
4599 fstp_d(Address(rsp, i*sizeof(jdouble)));
4600 }
4601
4602 #ifdef _LP64
4603 if (nb_args > 0) {
4604 movdbl(xmm0, Address(rsp, 0));
4605 }
4606 if (nb_args > 1) {
4607 movdbl(xmm1, Address(rsp, sizeof(jdouble)));
4608 }
4609 assert(nb_args <= 2, "unsupported number of args");
4610 #endif // _LP64
4611
4612 // NOTE: we must not use call_VM_leaf here because that requires a
4613 // complete interpreter frame in debug mode -- same bug as 4387334
4614 // MacroAssembler::call_VM_leaf_base is perfectly safe and will
4615 // do proper 64bit abi
4616
4617 NEEDS_CLEANUP;
4618 // Need to add stack banging before this runtime call if it needs to
4619 // be taken; however, there is no generic stack banging routine at
4620 // the MacroAssembler level
4621
4622 MacroAssembler::call_VM_leaf_base(runtime_entry, 0);
4623
4624 #ifdef _LP64
4625 movsd(Address(rsp, 0), xmm0);
4626 fld_d(Address(rsp, 0));
4627 #endif // _LP64
4628 addptr(rsp, sizeof(jdouble) * nb_args);
4629 if (num_fpu_regs_in_use > 1) {
4630 // Must save return value to stack and then restore entire FPU
4631 // stack except incoming arguments
4632 fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
4633 for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) {
4634 fld_d(Address(rsp, 0));
4635 addptr(rsp, sizeof(jdouble));
4636 }
4637 fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble)));
4638 addptr(rsp, sizeof(jdouble) * nb_args);
4639 }
4640
4641 off = 0;
4642 if (UseSSE == 1) {
4643 movflt(xmm0, Address(rsp,off++*sizeof(jdouble)));
4644 movflt(xmm1, Address(rsp,off++*sizeof(jdouble)));
4645 movflt(xmm2, Address(rsp,off++*sizeof(jdouble)));
4646 movflt(xmm3, Address(rsp,off++*sizeof(jdouble)));
4647 movflt(xmm4, Address(rsp,off++*sizeof(jdouble)));
4648 movflt(xmm5, Address(rsp,off++*sizeof(jdouble)));
4649 movflt(xmm6, Address(rsp,off++*sizeof(jdouble)));
4650 movflt(xmm7, Address(rsp,off++*sizeof(jdouble)));
4651 addptr(rsp, sizeof(jdouble)*8);
4652 } else if (UseSSE >= 2) {
4653 // Restore whole 128bit (16 bytes) XMM regiters
4654 movdqu(xmm0, Address(rsp,off++*16));
4655 movdqu(xmm1, Address(rsp,off++*16));
4656 movdqu(xmm2, Address(rsp,off++*16));
4657 movdqu(xmm3, Address(rsp,off++*16));
4658 movdqu(xmm4, Address(rsp,off++*16));
4659 movdqu(xmm5, Address(rsp,off++*16));
4660 movdqu(xmm6, Address(rsp,off++*16));
4661 movdqu(xmm7, Address(rsp,off++*16));
4662 #ifdef _LP64
4663 movdqu(xmm8, Address(rsp,off++*16));
4664 movdqu(xmm9, Address(rsp,off++*16));
4665 movdqu(xmm10, Address(rsp,off++*16));
4666 movdqu(xmm11, Address(rsp,off++*16));
4667 movdqu(xmm12, Address(rsp,off++*16));
4668 movdqu(xmm13, Address(rsp,off++*16));
4669 movdqu(xmm14, Address(rsp,off++*16));
4670 movdqu(xmm15, Address(rsp,off++*16));
4671 #endif
4672 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4673 #ifdef COMPILER2
4674 if (MaxVectorSize > 16) {
4675 // Restore upper half of YMM registes.
4676 vinsertf128h(xmm0, Address(rsp, 0));
4677 vinsertf128h(xmm1, Address(rsp, 16));
4678 vinsertf128h(xmm2, Address(rsp, 32));
4679 vinsertf128h(xmm3, Address(rsp, 48));
4680 vinsertf128h(xmm4, Address(rsp, 64));
4681 vinsertf128h(xmm5, Address(rsp, 80));
4682 vinsertf128h(xmm6, Address(rsp, 96));
4683 vinsertf128h(xmm7, Address(rsp,112));
4684 #ifdef _LP64
4685 vinsertf128h(xmm8, Address(rsp,128));
4686 vinsertf128h(xmm9, Address(rsp,144));
4687 vinsertf128h(xmm10, Address(rsp,160));
4688 vinsertf128h(xmm11, Address(rsp,176));
4689 vinsertf128h(xmm12, Address(rsp,192));
4690 vinsertf128h(xmm13, Address(rsp,208));
4691 vinsertf128h(xmm14, Address(rsp,224));
4692 vinsertf128h(xmm15, Address(rsp,240));
4693 #endif
4694 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4695 }
4696 #endif
4697 }
4698 popa();
4699 }
4700
4701 static const double pi_4 = 0.7853981633974483;
4702
4703 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
4704 // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
4705 // was attempted in this code; unfortunately it appears that the
4706 // switch to 80-bit precision and back causes this to be
4707 // unprofitable compared with simply performing a runtime call if
4708 // the argument is out of the (-pi/4, pi/4) range.
4709
4710 Register tmp = noreg;
4711 if (!VM_Version::supports_cmov()) {
4712 // fcmp needs a temporary so preserve rbx,
4713 tmp = rbx;
4714 push(tmp);
4715 }
4716
4717 Label slow_case, done;
4718
4719 ExternalAddress pi4_adr = (address)&pi_4;
4720 if (reachable(pi4_adr)) {
4721 // x ?<= pi/4
4722 fld_d(pi4_adr);
4723 fld_s(1); // Stack: X PI/4 X
4724 fabs(); // Stack: |X| PI/4 X
4725 fcmp(tmp);
4726 jcc(Assembler::above, slow_case);
4727
4728 // fastest case: -pi/4 <= x <= pi/4
4729 switch(trig) {
4730 case 's':
4731 fsin();
4732 break;
4733 case 'c':
4734 fcos();
4735 break;
4736 case 't':
4737 ftan();
4738 break;
4739 default:
4740 assert(false, "bad intrinsic");
4741 break;
4742 }
4743 jmp(done);
4744 }
4745
4746 // slow case: runtime call
4747 bind(slow_case);
4748
4749 switch(trig) {
4750 case 's':
4751 {
4752 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use);
4753 }
4754 break;
4755 case 'c':
4756 {
4757 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use);
4758 }
4759 break;
4760 case 't':
4761 {
4762 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use);
4763 }
4764 break;
4765 default:
4766 assert(false, "bad intrinsic");
4767 break;
4768 }
4769
4770 // Come here with result in F-TOS
4771 bind(done);
4772
4773 if (tmp != noreg) {
4774 pop(tmp);
4775 }
4776 }
4777
4778
4779 // Look up the method for a megamorphic invokeinterface call.
4780 // The target method is determined by <intf_klass, itable_index>.
4781 // The receiver klass is in recv_klass.
4782 // On success, the result will be in method_result, and execution falls through.
4783 // On failure, execution transfers to the given label.
4784 void MacroAssembler::lookup_interface_method(Register recv_klass,
4785 Register intf_klass,
4786 RegisterOrConstant itable_index,
4787 Register method_result,
4788 Register scan_temp,
4789 Label& L_no_such_interface) {
4790 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
4791 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4792 "caller must use same register for non-constant itable index as for method");
4793
4794 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4795 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize;
4796 int itentry_off = itableMethodEntry::method_offset_in_bytes();
4797 int scan_step = itableOffsetEntry::size() * wordSize;
4798 int vte_size = vtableEntry::size() * wordSize;
4799 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4800 assert(vte_size == wordSize, "else adjust times_vte_scale");
4801
4802 movl(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize));
4803
4804 // %%% Could store the aligned, prescaled offset in the klassoop.
4805 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4806 if (HeapWordsPerLong > 1) {
4807 // Round up to align_object_offset boundary
4808 // see code for InstanceKlass::start_of_itable!
4809 round_to(scan_temp, BytesPerLong);
4810 }
4811
4812 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4813 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4814 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4815
4816 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
4817 // if (scan->interface() == intf) {
4818 // result = (klass + scan->offset() + itable_index);
4819 // }
4820 // }
4821 Label search, found_method;
4822
4823 for (int peel = 1; peel >= 0; peel--) {
4824 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
4825 cmpptr(intf_klass, method_result);
4826
4827 if (peel) {
4828 jccb(Assembler::equal, found_method);
4829 } else {
4830 jccb(Assembler::notEqual, search);
4831 // (invert the test to fall through to found_method...)
4832 }
4833
4834 if (!peel) break;
4835
4836 bind(search);
4837
4838 // Check that the previous entry is non-null. A null entry means that
4839 // the receiver class doesn't implement the interface, and wasn't the
4840 // same as when the caller was compiled.
4841 testptr(method_result, method_result);
4842 jcc(Assembler::zero, L_no_such_interface);
4843 addptr(scan_temp, scan_step);
4844 }
4845
4846 bind(found_method);
4847
4848 // Got a hit.
4849 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
4850 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4851 }
4852
4853
4854 // virtual method calling
4855 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4856 RegisterOrConstant vtable_index,
4857 Register method_result) {
4858 const int base = InstanceKlass::vtable_start_offset() * wordSize;
4859 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4860 Address vtable_entry_addr(recv_klass,
4861 vtable_index, Address::times_ptr,
4862 base + vtableEntry::method_offset_in_bytes());
4863 movptr(method_result, vtable_entry_addr);
4864 }
4865
4866
4867 void MacroAssembler::check_klass_subtype(Register sub_klass,
4868 Register super_klass,
4869 Register temp_reg,
4870 Label& L_success) {
4871 Label L_failure;
4872 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
4873 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
4874 bind(L_failure);
4875 }
4876
4877
4878 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4879 Register super_klass,
4880 Register temp_reg,
4881 Label* L_success,
4882 Label* L_failure,
4883 Label* L_slow_path,
4884 RegisterOrConstant super_check_offset) {
4885 assert_different_registers(sub_klass, super_klass, temp_reg);
4886 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4887 if (super_check_offset.is_register()) {
4888 assert_different_registers(sub_klass, super_klass,
4889 super_check_offset.as_register());
4890 } else if (must_load_sco) {
4891 assert(temp_reg != noreg, "supply either a temp or a register offset");
4892 }
4893
4894 Label L_fallthrough;
4895 int label_nulls = 0;
4896 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
4897 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
4898 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
4899 assert(label_nulls <= 1, "at most one NULL in the batch");
4900
4901 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4902 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4903 Address super_check_offset_addr(super_klass, sco_offset);
4904
4905 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4906 // range of a jccb. If this routine grows larger, reconsider at
4907 // least some of these.
4908 #define local_jcc(assembler_cond, label) \
4909 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4910 else jcc( assembler_cond, label) /*omit semi*/
4911
4912 // Hacked jmp, which may only be used just before L_fallthrough.
4913 #define final_jmp(label) \
4914 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4915 else jmp(label) /*omit semi*/
4916
4917 // If the pointers are equal, we are done (e.g., String[] elements).
4918 // This self-check enables sharing of secondary supertype arrays among
4919 // non-primary types such as array-of-interface. Otherwise, each such
4920 // type would need its own customized SSA.
4921 // We move this check to the front of the fast path because many
4922 // type checks are in fact trivially successful in this manner,
4923 // so we get a nicely predicted branch right at the start of the check.
4924 cmpptr(sub_klass, super_klass);
4925 local_jcc(Assembler::equal, *L_success);
4926
4927 // Check the supertype display:
4928 if (must_load_sco) {
4929 // Positive movl does right thing on LP64.
4930 movl(temp_reg, super_check_offset_addr);
4931 super_check_offset = RegisterOrConstant(temp_reg);
4932 }
4933 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4934 cmpptr(super_klass, super_check_addr); // load displayed supertype
4935
4936 // This check has worked decisively for primary supers.
4937 // Secondary supers are sought in the super_cache ('super_cache_addr').
4938 // (Secondary supers are interfaces and very deeply nested subtypes.)
4939 // This works in the same check above because of a tricky aliasing
4940 // between the super_cache and the primary super display elements.
4941 // (The 'super_check_addr' can address either, as the case requires.)
4942 // Note that the cache is updated below if it does not help us find
4943 // what we need immediately.
4944 // So if it was a primary super, we can just fail immediately.
4945 // Otherwise, it's the slow path for us (no success at this point).
4946
4947 if (super_check_offset.is_register()) {
4948 local_jcc(Assembler::equal, *L_success);
4949 cmpl(super_check_offset.as_register(), sc_offset);
4950 if (L_failure == &L_fallthrough) {
4951 local_jcc(Assembler::equal, *L_slow_path);
4952 } else {
4953 local_jcc(Assembler::notEqual, *L_failure);
4954 final_jmp(*L_slow_path);
4955 }
4956 } else if (super_check_offset.as_constant() == sc_offset) {
4957 // Need a slow path; fast failure is impossible.
4958 if (L_slow_path == &L_fallthrough) {
4959 local_jcc(Assembler::equal, *L_success);
4960 } else {
4961 local_jcc(Assembler::notEqual, *L_slow_path);
4962 final_jmp(*L_success);
4963 }
4964 } else {
4965 // No slow path; it's a fast decision.
4966 if (L_failure == &L_fallthrough) {
4967 local_jcc(Assembler::equal, *L_success);
4968 } else {
4969 local_jcc(Assembler::notEqual, *L_failure);
4970 final_jmp(*L_success);
4971 }
4972 }
4973
4974 bind(L_fallthrough);
4975
4976 #undef local_jcc
4977 #undef final_jmp
4978 }
4979
4980
4981 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4982 Register super_klass,
4983 Register temp_reg,
4984 Register temp2_reg,
4985 Label* L_success,
4986 Label* L_failure,
4987 bool set_cond_codes) {
4988 assert_different_registers(sub_klass, super_klass, temp_reg);
4989 if (temp2_reg != noreg)
4990 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4991 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4992
4993 Label L_fallthrough;
4994 int label_nulls = 0;
4995 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
4996 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
4997 assert(label_nulls <= 1, "at most one NULL in the batch");
4998
4999 // a couple of useful fields in sub_klass:
5000 int ss_offset = in_bytes(Klass::secondary_supers_offset());
5001 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5002 Address secondary_supers_addr(sub_klass, ss_offset);
5003 Address super_cache_addr( sub_klass, sc_offset);
5004
5005 // Do a linear scan of the secondary super-klass chain.
5006 // This code is rarely used, so simplicity is a virtue here.
5007 // The repne_scan instruction uses fixed registers, which we must spill.
5008 // Don't worry too much about pre-existing connections with the input regs.
5009
5010 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
5011 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
5012
5013 // Get super_klass value into rax (even if it was in rdi or rcx).
5014 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
5015 if (super_klass != rax || UseCompressedOops) {
5016 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
5017 mov(rax, super_klass);
5018 }
5019 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
5020 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
5021
5022 #ifndef PRODUCT
5023 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
5024 ExternalAddress pst_counter_addr((address) pst_counter);
5025 NOT_LP64( incrementl(pst_counter_addr) );
5026 LP64_ONLY( lea(rcx, pst_counter_addr) );
5027 LP64_ONLY( incrementl(Address(rcx, 0)) );
5028 #endif //PRODUCT
5029
5030 // We will consult the secondary-super array.
5031 movptr(rdi, secondary_supers_addr);
5032 // Load the array length. (Positive movl does right thing on LP64.)
5033 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
5034 // Skip to start of data.
5035 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
5036
5037 // Scan RCX words at [RDI] for an occurrence of RAX.
5038 // Set NZ/Z based on last compare.
5039 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
5040 // not change flags (only scas instruction which is repeated sets flags).
5041 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
5042
5043 testptr(rax,rax); // Set Z = 0
5044 repne_scan();
5045
5046 // Unspill the temp. registers:
5047 if (pushed_rdi) pop(rdi);
5048 if (pushed_rcx) pop(rcx);
5049 if (pushed_rax) pop(rax);
5050
5051 if (set_cond_codes) {
5052 // Special hack for the AD files: rdi is guaranteed non-zero.
5053 assert(!pushed_rdi, "rdi must be left non-NULL");
5054 // Also, the condition codes are properly set Z/NZ on succeed/failure.
5055 }
5056
5057 if (L_failure == &L_fallthrough)
5058 jccb(Assembler::notEqual, *L_failure);
5059 else jcc(Assembler::notEqual, *L_failure);
5060
5061 // Success. Cache the super we found and proceed in triumph.
5062 movptr(super_cache_addr, super_klass);
5063
5064 if (L_success != &L_fallthrough) {
5065 jmp(*L_success);
5066 }
5067
5068 #undef IS_A_TEMP
5069
5070 bind(L_fallthrough);
5071 }
5072
5073
5074 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5075 if (VM_Version::supports_cmov()) {
5076 cmovl(cc, dst, src);
5077 } else {
5078 Label L;
5079 jccb(negate_condition(cc), L);
5080 movl(dst, src);
5081 bind(L);
5082 }
5083 }
5084
5085 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5086 if (VM_Version::supports_cmov()) {
5087 cmovl(cc, dst, src);
5088 } else {
5089 Label L;
5090 jccb(negate_condition(cc), L);
5091 movl(dst, src);
5092 bind(L);
5093 }
5094 }
5095
5096 void MacroAssembler::verify_oop(Register reg, const char* s) {
5097 if (!VerifyOops) return;
5098
5099 // Pass register number to verify_oop_subroutine
5100 const char* b = NULL;
5101 {
5102 ResourceMark rm;
5103 stringStream ss;
5104 ss.print("verify_oop: %s: %s", reg->name(), s);
5105 b = code_string(ss.as_string());
5106 }
5107 BLOCK_COMMENT("verify_oop {");
5108 #ifdef _LP64
5109 push(rscratch1); // save r10, trashed by movptr()
5110 #endif
5111 push(rax); // save rax,
5112 push(reg); // pass register argument
5113 ExternalAddress buffer((address) b);
5114 // avoid using pushptr, as it modifies scratch registers
5115 // and our contract is not to modify anything
5116 movptr(rax, buffer.addr());
5117 push(rax);
5118 // call indirectly to solve generation ordering problem
5119 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5120 call(rax);
5121 // Caller pops the arguments (oop, message) and restores rax, r10
5122 BLOCK_COMMENT("} verify_oop");
5123 }
5124
5125
5126 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
5127 Register tmp,
5128 int offset) {
5129 intptr_t value = *delayed_value_addr;
5130 if (value != 0)
5131 return RegisterOrConstant(value + offset);
5132
5133 // load indirectly to solve generation ordering problem
5134 movptr(tmp, ExternalAddress((address) delayed_value_addr));
5135
5136 #ifdef ASSERT
5137 { Label L;
5138 testptr(tmp, tmp);
5139 if (WizardMode) {
5140 const char* buf = NULL;
5141 {
5142 ResourceMark rm;
5143 stringStream ss;
5144 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
5145 buf = code_string(ss.as_string());
5146 }
5147 jcc(Assembler::notZero, L);
5148 STOP(buf);
5149 } else {
5150 jccb(Assembler::notZero, L);
5151 hlt();
5152 }
5153 bind(L);
5154 }
5155 #endif
5156
5157 if (offset != 0)
5158 addptr(tmp, offset);
5159
5160 return RegisterOrConstant(tmp);
5161 }
5162
5163
5164 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5165 int extra_slot_offset) {
5166 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5167 int stackElementSize = Interpreter::stackElementSize;
5168 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5169 #ifdef ASSERT
5170 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5171 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5172 #endif
5173 Register scale_reg = noreg;
5174 Address::ScaleFactor scale_factor = Address::no_scale;
5175 if (arg_slot.is_constant()) {
5176 offset += arg_slot.as_constant() * stackElementSize;
5177 } else {
5178 scale_reg = arg_slot.as_register();
5179 scale_factor = Address::times(stackElementSize);
5180 }
5181 offset += wordSize; // return PC is on stack
5182 return Address(rsp, scale_reg, scale_factor, offset);
5183 }
5184
5185
5186 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
5187 if (!VerifyOops) return;
5188
5189 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
5190 // Pass register number to verify_oop_subroutine
5191 const char* b = NULL;
5192 {
5193 ResourceMark rm;
5194 stringStream ss;
5195 ss.print("verify_oop_addr: %s", s);
5196 b = code_string(ss.as_string());
5197 }
5198 #ifdef _LP64
5199 push(rscratch1); // save r10, trashed by movptr()
5200 #endif
5201 push(rax); // save rax,
5202 // addr may contain rsp so we will have to adjust it based on the push
5203 // we just did (and on 64 bit we do two pushes)
5204 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5205 // stores rax into addr which is backwards of what was intended.
5206 if (addr.uses(rsp)) {
5207 lea(rax, addr);
5208 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5209 } else {
5210 pushptr(addr);
5211 }
5212
5213 ExternalAddress buffer((address) b);
5214 // pass msg argument
5215 // avoid using pushptr, as it modifies scratch registers
5216 // and our contract is not to modify anything
5217 movptr(rax, buffer.addr());
5218 push(rax);
5219
5220 // call indirectly to solve generation ordering problem
5221 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5222 call(rax);
5223 // Caller pops the arguments (addr, message) and restores rax, r10.
5224 }
5225
5226 void MacroAssembler::verify_tlab() {
5227 #ifdef ASSERT
5228 if (UseTLAB && VerifyOops) {
5229 Label next, ok;
5230 Register t1 = rsi;
5231 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5232
5233 push(t1);
5234 NOT_LP64(push(thread_reg));
5235 NOT_LP64(get_thread(thread_reg));
5236
5237 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5238 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5239 jcc(Assembler::aboveEqual, next);
5240 STOP("assert(top >= start)");
5241 should_not_reach_here();
5242
5243 bind(next);
5244 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5245 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5246 jcc(Assembler::aboveEqual, ok);
5247 STOP("assert(top <= end)");
5248 should_not_reach_here();
5249
5250 bind(ok);
5251 NOT_LP64(pop(thread_reg));
5252 pop(t1);
5253 }
5254 #endif
5255 }
5256
5257 class ControlWord {
5258 public:
5259 int32_t _value;
5260
5261 int rounding_control() const { return (_value >> 10) & 3 ; }
5262 int precision_control() const { return (_value >> 8) & 3 ; }
5263 bool precision() const { return ((_value >> 5) & 1) != 0; }
5264 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5265 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5266 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5267 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5268 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5269
5270 void print() const {
5271 // rounding control
5272 const char* rc;
5273 switch (rounding_control()) {
5274 case 0: rc = "round near"; break;
5275 case 1: rc = "round down"; break;
5276 case 2: rc = "round up "; break;
5277 case 3: rc = "chop "; break;
5278 };
5279 // precision control
5280 const char* pc;
5281 switch (precision_control()) {
5282 case 0: pc = "24 bits "; break;
5283 case 1: pc = "reserved"; break;
5284 case 2: pc = "53 bits "; break;
5285 case 3: pc = "64 bits "; break;
5286 };
5287 // flags
5288 char f[9];
5289 f[0] = ' ';
5290 f[1] = ' ';
5291 f[2] = (precision ()) ? 'P' : 'p';
5292 f[3] = (underflow ()) ? 'U' : 'u';
5293 f[4] = (overflow ()) ? 'O' : 'o';
5294 f[5] = (zero_divide ()) ? 'Z' : 'z';
5295 f[6] = (denormalized()) ? 'D' : 'd';
5296 f[7] = (invalid ()) ? 'I' : 'i';
5297 f[8] = '\x0';
5298 // output
5299 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5300 }
5301
5302 };
5303
5304 class StatusWord {
5305 public:
5306 int32_t _value;
5307
5308 bool busy() const { return ((_value >> 15) & 1) != 0; }
5309 bool C3() const { return ((_value >> 14) & 1) != 0; }
5310 bool C2() const { return ((_value >> 10) & 1) != 0; }
5311 bool C1() const { return ((_value >> 9) & 1) != 0; }
5312 bool C0() const { return ((_value >> 8) & 1) != 0; }
5313 int top() const { return (_value >> 11) & 7 ; }
5314 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5315 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5316 bool precision() const { return ((_value >> 5) & 1) != 0; }
5317 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5318 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5319 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5320 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5321 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5322
5323 void print() const {
5324 // condition codes
5325 char c[5];
5326 c[0] = (C3()) ? '3' : '-';
5327 c[1] = (C2()) ? '2' : '-';
5328 c[2] = (C1()) ? '1' : '-';
5329 c[3] = (C0()) ? '0' : '-';
5330 c[4] = '\x0';
5331 // flags
5332 char f[9];
5333 f[0] = (error_status()) ? 'E' : '-';
5334 f[1] = (stack_fault ()) ? 'S' : '-';
5335 f[2] = (precision ()) ? 'P' : '-';
5336 f[3] = (underflow ()) ? 'U' : '-';
5337 f[4] = (overflow ()) ? 'O' : '-';
5338 f[5] = (zero_divide ()) ? 'Z' : '-';
5339 f[6] = (denormalized()) ? 'D' : '-';
5340 f[7] = (invalid ()) ? 'I' : '-';
5341 f[8] = '\x0';
5342 // output
5343 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5344 }
5345
5346 };
5347
5348 class TagWord {
5349 public:
5350 int32_t _value;
5351
5352 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5353
5354 void print() const {
5355 printf("%04x", _value & 0xFFFF);
5356 }
5357
5358 };
5359
5360 class FPU_Register {
5361 public:
5362 int32_t _m0;
5363 int32_t _m1;
5364 int16_t _ex;
5365
5366 bool is_indefinite() const {
5367 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5368 }
5369
5370 void print() const {
5371 char sign = (_ex < 0) ? '-' : '+';
5372 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5373 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5374 };
5375
5376 };
5377
5378 class FPU_State {
5379 public:
5380 enum {
5381 register_size = 10,
5382 number_of_registers = 8,
5383 register_mask = 7
5384 };
5385
5386 ControlWord _control_word;
5387 StatusWord _status_word;
5388 TagWord _tag_word;
5389 int32_t _error_offset;
5390 int32_t _error_selector;
5391 int32_t _data_offset;
5392 int32_t _data_selector;
5393 int8_t _register[register_size * number_of_registers];
5394
5395 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5396 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5397
5398 const char* tag_as_string(int tag) const {
5399 switch (tag) {
5400 case 0: return "valid";
5401 case 1: return "zero";
5402 case 2: return "special";
5403 case 3: return "empty";
5404 }
5405 ShouldNotReachHere();
5406 return NULL;
5407 }
5408
5409 void print() const {
5410 // print computation registers
5411 { int t = _status_word.top();
5412 for (int i = 0; i < number_of_registers; i++) {
5413 int j = (i - t) & register_mask;
5414 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5415 st(j)->print();
5416 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5417 }
5418 }
5419 printf("\n");
5420 // print control registers
5421 printf("ctrl = "); _control_word.print(); printf("\n");
5422 printf("stat = "); _status_word .print(); printf("\n");
5423 printf("tags = "); _tag_word .print(); printf("\n");
5424 }
5425
5426 };
5427
5428 class Flag_Register {
5429 public:
5430 int32_t _value;
5431
5432 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5433 bool direction() const { return ((_value >> 10) & 1) != 0; }
5434 bool sign() const { return ((_value >> 7) & 1) != 0; }
5435 bool zero() const { return ((_value >> 6) & 1) != 0; }
5436 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5437 bool parity() const { return ((_value >> 2) & 1) != 0; }
5438 bool carry() const { return ((_value >> 0) & 1) != 0; }
5439
5440 void print() const {
5441 // flags
5442 char f[8];
5443 f[0] = (overflow ()) ? 'O' : '-';
5444 f[1] = (direction ()) ? 'D' : '-';
5445 f[2] = (sign ()) ? 'S' : '-';
5446 f[3] = (zero ()) ? 'Z' : '-';
5447 f[4] = (auxiliary_carry()) ? 'A' : '-';
5448 f[5] = (parity ()) ? 'P' : '-';
5449 f[6] = (carry ()) ? 'C' : '-';
5450 f[7] = '\x0';
5451 // output
5452 printf("%08x flags = %s", _value, f);
5453 }
5454
5455 };
5456
5457 class IU_Register {
5458 public:
5459 int32_t _value;
5460
5461 void print() const {
5462 printf("%08x %11d", _value, _value);
5463 }
5464
5465 };
5466
5467 class IU_State {
5468 public:
5469 Flag_Register _eflags;
5470 IU_Register _rdi;
5471 IU_Register _rsi;
5472 IU_Register _rbp;
5473 IU_Register _rsp;
5474 IU_Register _rbx;
5475 IU_Register _rdx;
5476 IU_Register _rcx;
5477 IU_Register _rax;
5478
5479 void print() const {
5480 // computation registers
5481 printf("rax, = "); _rax.print(); printf("\n");
5482 printf("rbx, = "); _rbx.print(); printf("\n");
5483 printf("rcx = "); _rcx.print(); printf("\n");
5484 printf("rdx = "); _rdx.print(); printf("\n");
5485 printf("rdi = "); _rdi.print(); printf("\n");
5486 printf("rsi = "); _rsi.print(); printf("\n");
5487 printf("rbp, = "); _rbp.print(); printf("\n");
5488 printf("rsp = "); _rsp.print(); printf("\n");
5489 printf("\n");
5490 // control registers
5491 printf("flgs = "); _eflags.print(); printf("\n");
5492 }
5493 };
5494
5495
5496 class CPU_State {
5497 public:
5498 FPU_State _fpu_state;
5499 IU_State _iu_state;
5500
5501 void print() const {
5502 printf("--------------------------------------------------\n");
5503 _iu_state .print();
5504 printf("\n");
5505 _fpu_state.print();
5506 printf("--------------------------------------------------\n");
5507 }
5508
5509 };
5510
5511
5512 static void _print_CPU_state(CPU_State* state) {
5513 state->print();
5514 };
5515
5516
5517 void MacroAssembler::print_CPU_state() {
5518 push_CPU_state();
5519 push(rsp); // pass CPU state
5520 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5521 addptr(rsp, wordSize); // discard argument
5522 pop_CPU_state();
5523 }
5524
5525
5526 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5527 static int counter = 0;
5528 FPU_State* fs = &state->_fpu_state;
5529 counter++;
5530 // For leaf calls, only verify that the top few elements remain empty.
5531 // We only need 1 empty at the top for C2 code.
5532 if( stack_depth < 0 ) {
5533 if( fs->tag_for_st(7) != 3 ) {
5534 printf("FPR7 not empty\n");
5535 state->print();
5536 assert(false, "error");
5537 return false;
5538 }
5539 return true; // All other stack states do not matter
5540 }
5541
5542 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
5543 "bad FPU control word");
5544
5545 // compute stack depth
5546 int i = 0;
5547 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5548 int d = i;
5549 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5550 // verify findings
5551 if (i != FPU_State::number_of_registers) {
5552 // stack not contiguous
5553 printf("%s: stack not contiguous at ST%d\n", s, i);
5554 state->print();
5555 assert(false, "error");
5556 return false;
5557 }
5558 // check if computed stack depth corresponds to expected stack depth
5559 if (stack_depth < 0) {
5560 // expected stack depth is -stack_depth or less
5561 if (d > -stack_depth) {
5562 // too many elements on the stack
5563 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5564 state->print();
5565 assert(false, "error");
5566 return false;
5567 }
5568 } else {
5569 // expected stack depth is stack_depth
5570 if (d != stack_depth) {
5571 // wrong stack depth
5572 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5573 state->print();
5574 assert(false, "error");
5575 return false;
5576 }
5577 }
5578 // everything is cool
5579 return true;
5580 }
5581
5582
5583 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5584 if (!VerifyFPU) return;
5585 push_CPU_state();
5586 push(rsp); // pass CPU state
5587 ExternalAddress msg((address) s);
5588 // pass message string s
5589 pushptr(msg.addr());
5590 push(stack_depth); // pass stack depth
5591 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5592 addptr(rsp, 3 * wordSize); // discard arguments
5593 // check for error
5594 { Label L;
5595 testl(rax, rax);
5596 jcc(Assembler::notZero, L);
5597 int3(); // break if error condition
5598 bind(L);
5599 }
5600 pop_CPU_state();
5601 }
5602
5603 void MacroAssembler::restore_cpu_control_state_after_jni() {
5604 // Either restore the MXCSR register after returning from the JNI Call
5605 // or verify that it wasn't changed (with -Xcheck:jni flag).
5606 if (VM_Version::supports_sse()) {
5607 if (RestoreMXCSROnJNICalls) {
5608 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
5609 } else if (CheckJNICalls) {
5610 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5611 }
5612 }
5613 if (VM_Version::supports_avx()) {
5614 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5615 vzeroupper();
5616 }
5617
5618 #ifndef _LP64
5619 // Either restore the x87 floating pointer control word after returning
5620 // from the JNI call or verify that it wasn't changed.
5621 if (CheckJNICalls) {
5622 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5623 }
5624 #endif // _LP64
5625 }
5626
5627
5628 void MacroAssembler::load_klass(Register dst, Register src) {
5629 #ifdef _LP64
5630 if (UseCompressedClassPointers) {
5631 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5632 decode_klass_not_null(dst);
5633 } else
5634 #endif
5635 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5636 }
5637
5638 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5639 load_klass(dst, src);
5640 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5641 }
5642
5643 void MacroAssembler::store_klass(Register dst, Register src) {
5644 #ifdef _LP64
5645 if (UseCompressedClassPointers) {
5646 encode_klass_not_null(src);
5647 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5648 } else
5649 #endif
5650 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5651 }
5652
5653 void MacroAssembler::load_heap_oop(Register dst, Address src) {
5654 #ifdef _LP64
5655 // FIXME: Must change all places where we try to load the klass.
5656 if (UseCompressedOops) {
5657 movl(dst, src);
5658 decode_heap_oop(dst);
5659 } else
5660 #endif
5661 movptr(dst, src);
5662 }
5663
5664 // Doesn't do verfication, generates fixed size code
5665 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
5666 #ifdef _LP64
5667 if (UseCompressedOops) {
5668 movl(dst, src);
5669 decode_heap_oop_not_null(dst);
5670 } else
5671 #endif
5672 movptr(dst, src);
5673 }
5674
5675 void MacroAssembler::store_heap_oop(Address dst, Register src) {
5676 #ifdef _LP64
5677 if (UseCompressedOops) {
5678 assert(!dst.uses(src), "not enough registers");
5679 encode_heap_oop(src);
5680 movl(dst, src);
5681 } else
5682 #endif
5683 movptr(dst, src);
5684 }
5685
5686 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
5687 assert_different_registers(src1, tmp);
5688 #ifdef _LP64
5689 if (UseCompressedOops) {
5690 bool did_push = false;
5691 if (tmp == noreg) {
5692 tmp = rax;
5693 push(tmp);
5694 did_push = true;
5695 assert(!src2.uses(rsp), "can't push");
5696 }
5697 load_heap_oop(tmp, src2);
5698 cmpptr(src1, tmp);
5699 if (did_push) pop(tmp);
5700 } else
5701 #endif
5702 cmpptr(src1, src2);
5703 }
5704
5705 // Used for storing NULLs.
5706 void MacroAssembler::store_heap_oop_null(Address dst) {
5707 #ifdef _LP64
5708 if (UseCompressedOops) {
5709 movl(dst, (int32_t)NULL_WORD);
5710 } else {
5711 movslq(dst, (int32_t)NULL_WORD);
5712 }
5713 #else
5714 movl(dst, (int32_t)NULL_WORD);
5715 #endif
5716 }
5717
5718 #ifdef _LP64
5719 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5720 if (UseCompressedClassPointers) {
5721 // Store to klass gap in destination
5722 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5723 }
5724 }
5725
5726 #ifdef ASSERT
5727 void MacroAssembler::verify_heapbase(const char* msg) {
5728 assert (UseCompressedOops, "should be compressed");
5729 assert (Universe::heap() != NULL, "java heap should be initialized");
5730 if (CheckCompressedOops) {
5731 Label ok;
5732 push(rscratch1); // cmpptr trashes rscratch1
5733 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
5734 jcc(Assembler::equal, ok);
5735 STOP(msg);
5736 bind(ok);
5737 pop(rscratch1);
5738 }
5739 }
5740 #endif
5741
5742 // Algorithm must match oop.inline.hpp encode_heap_oop.
5743 void MacroAssembler::encode_heap_oop(Register r) {
5744 #ifdef ASSERT
5745 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5746 #endif
5747 verify_oop(r, "broken oop in encode_heap_oop");
5748 if (Universe::narrow_oop_base() == NULL) {
5749 if (Universe::narrow_oop_shift() != 0) {
5750 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5751 shrq(r, LogMinObjAlignmentInBytes);
5752 }
5753 return;
5754 }
5755 testq(r, r);
5756 cmovq(Assembler::equal, r, r12_heapbase);
5757 subq(r, r12_heapbase);
5758 shrq(r, LogMinObjAlignmentInBytes);
5759 }
5760
5761 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5762 #ifdef ASSERT
5763 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5764 if (CheckCompressedOops) {
5765 Label ok;
5766 testq(r, r);
5767 jcc(Assembler::notEqual, ok);
5768 STOP("null oop passed to encode_heap_oop_not_null");
5769 bind(ok);
5770 }
5771 #endif
5772 verify_oop(r, "broken oop in encode_heap_oop_not_null");
5773 if (Universe::narrow_oop_base() != NULL) {
5774 subq(r, r12_heapbase);
5775 }
5776 if (Universe::narrow_oop_shift() != 0) {
5777 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5778 shrq(r, LogMinObjAlignmentInBytes);
5779 }
5780 }
5781
5782 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5783 #ifdef ASSERT
5784 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5785 if (CheckCompressedOops) {
5786 Label ok;
5787 testq(src, src);
5788 jcc(Assembler::notEqual, ok);
5789 STOP("null oop passed to encode_heap_oop_not_null2");
5790 bind(ok);
5791 }
5792 #endif
5793 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
5794 if (dst != src) {
5795 movq(dst, src);
5796 }
5797 if (Universe::narrow_oop_base() != NULL) {
5798 subq(dst, r12_heapbase);
5799 }
5800 if (Universe::narrow_oop_shift() != 0) {
5801 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5802 shrq(dst, LogMinObjAlignmentInBytes);
5803 }
5804 }
5805
5806 void MacroAssembler::decode_heap_oop(Register r) {
5807 #ifdef ASSERT
5808 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5809 #endif
5810 if (Universe::narrow_oop_base() == NULL) {
5811 if (Universe::narrow_oop_shift() != 0) {
5812 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5813 shlq(r, LogMinObjAlignmentInBytes);
5814 }
5815 } else {
5816 Label done;
5817 shlq(r, LogMinObjAlignmentInBytes);
5818 jccb(Assembler::equal, done);
5819 addq(r, r12_heapbase);
5820 bind(done);
5821 }
5822 verify_oop(r, "broken oop in decode_heap_oop");
5823 }
5824
5825 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5826 // Note: it will change flags
5827 assert (UseCompressedOops, "should only be used for compressed headers");
5828 assert (Universe::heap() != NULL, "java heap should be initialized");
5829 // Cannot assert, unverified entry point counts instructions (see .ad file)
5830 // vtableStubs also counts instructions in pd_code_size_limit.
5831 // Also do not verify_oop as this is called by verify_oop.
5832 if (Universe::narrow_oop_shift() != 0) {
5833 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5834 shlq(r, LogMinObjAlignmentInBytes);
5835 if (Universe::narrow_oop_base() != NULL) {
5836 addq(r, r12_heapbase);
5837 }
5838 } else {
5839 assert (Universe::narrow_oop_base() == NULL, "sanity");
5840 }
5841 }
5842
5843 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5844 // Note: it will change flags
5845 assert (UseCompressedOops, "should only be used for compressed headers");
5846 assert (Universe::heap() != NULL, "java heap should be initialized");
5847 // Cannot assert, unverified entry point counts instructions (see .ad file)
5848 // vtableStubs also counts instructions in pd_code_size_limit.
5849 // Also do not verify_oop as this is called by verify_oop.
5850 if (Universe::narrow_oop_shift() != 0) {
5851 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5852 if (LogMinObjAlignmentInBytes == Address::times_8) {
5853 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5854 } else {
5855 if (dst != src) {
5856 movq(dst, src);
5857 }
5858 shlq(dst, LogMinObjAlignmentInBytes);
5859 if (Universe::narrow_oop_base() != NULL) {
5860 addq(dst, r12_heapbase);
5861 }
5862 }
5863 } else {
5864 assert (Universe::narrow_oop_base() == NULL, "sanity");
5865 if (dst != src) {
5866 movq(dst, src);
5867 }
5868 }
5869 }
5870
5871 void MacroAssembler::encode_klass_not_null(Register r) {
5872 if (Universe::narrow_klass_base() != NULL) {
5873 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5874 assert(r != r12_heapbase, "Encoding a klass in r12");
5875 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5876 subq(r, r12_heapbase);
5877 }
5878 if (Universe::narrow_klass_shift() != 0) {
5879 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5880 shrq(r, LogKlassAlignmentInBytes);
5881 }
5882 if (Universe::narrow_klass_base() != NULL) {
5883 reinit_heapbase();
5884 }
5885 }
5886
5887 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5888 if (dst == src) {
5889 encode_klass_not_null(src);
5890 } else {
5891 if (Universe::narrow_klass_base() != NULL) {
5892 mov64(dst, (int64_t)Universe::narrow_klass_base());
5893 negq(dst);
5894 addq(dst, src);
5895 } else {
5896 movptr(dst, src);
5897 }
5898 if (Universe::narrow_klass_shift() != 0) {
5899 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5900 shrq(dst, LogKlassAlignmentInBytes);
5901 }
5902 }
5903 }
5904
5905 // Function instr_size_for_decode_klass_not_null() counts the instructions
5906 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
5907 // when (Universe::heap() != NULL). Hence, if the instructions they
5908 // generate change, then this method needs to be updated.
5909 int MacroAssembler::instr_size_for_decode_klass_not_null() {
5910 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
5911 if (Universe::narrow_klass_base() != NULL) {
5912 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
5913 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
5914 } else {
5915 // longest load decode klass function, mov64, leaq
5916 return 16;
5917 }
5918 }
5919
5920 // !!! If the instructions that get generated here change then function
5921 // instr_size_for_decode_klass_not_null() needs to get updated.
5922 void MacroAssembler::decode_klass_not_null(Register r) {
5923 // Note: it will change flags
5924 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5925 assert(r != r12_heapbase, "Decoding a klass in r12");
5926 // Cannot assert, unverified entry point counts instructions (see .ad file)
5927 // vtableStubs also counts instructions in pd_code_size_limit.
5928 // Also do not verify_oop as this is called by verify_oop.
5929 if (Universe::narrow_klass_shift() != 0) {
5930 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5931 shlq(r, LogKlassAlignmentInBytes);
5932 }
5933 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5934 if (Universe::narrow_klass_base() != NULL) {
5935 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5936 addq(r, r12_heapbase);
5937 reinit_heapbase();
5938 }
5939 }
5940
5941 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5942 // Note: it will change flags
5943 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5944 if (dst == src) {
5945 decode_klass_not_null(dst);
5946 } else {
5947 // Cannot assert, unverified entry point counts instructions (see .ad file)
5948 // vtableStubs also counts instructions in pd_code_size_limit.
5949 // Also do not verify_oop as this is called by verify_oop.
5950 mov64(dst, (int64_t)Universe::narrow_klass_base());
5951 if (Universe::narrow_klass_shift() != 0) {
5952 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5953 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
5954 leaq(dst, Address(dst, src, Address::times_8, 0));
5955 } else {
5956 addq(dst, src);
5957 }
5958 }
5959 }
5960
5961 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5962 assert (UseCompressedOops, "should only be used for compressed headers");
5963 assert (Universe::heap() != NULL, "java heap should be initialized");
5964 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5965 int oop_index = oop_recorder()->find_index(obj);
5966 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5967 mov_narrow_oop(dst, oop_index, rspec);
5968 }
5969
5970 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5971 assert (UseCompressedOops, "should only be used for compressed headers");
5972 assert (Universe::heap() != NULL, "java heap should be initialized");
5973 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5974 int oop_index = oop_recorder()->find_index(obj);
5975 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5976 mov_narrow_oop(dst, oop_index, rspec);
5977 }
5978
5979 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5980 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5981 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5982 int klass_index = oop_recorder()->find_index(k);
5983 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5984 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
5985 }
5986
5987 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
5988 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5989 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5990 int klass_index = oop_recorder()->find_index(k);
5991 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5992 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
5993 }
5994
5995 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
5996 assert (UseCompressedOops, "should only be used for compressed headers");
5997 assert (Universe::heap() != NULL, "java heap should be initialized");
5998 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5999 int oop_index = oop_recorder()->find_index(obj);
6000 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6001 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6002 }
6003
6004 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6005 assert (UseCompressedOops, "should only be used for compressed headers");
6006 assert (Universe::heap() != NULL, "java heap should be initialized");
6007 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6008 int oop_index = oop_recorder()->find_index(obj);
6009 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6010 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6011 }
6012
6013 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6014 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6015 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6016 int klass_index = oop_recorder()->find_index(k);
6017 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6018 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6019 }
6020
6021 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6022 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6023 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6024 int klass_index = oop_recorder()->find_index(k);
6025 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6026 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6027 }
6028
6029 void MacroAssembler::reinit_heapbase() {
6030 if (UseCompressedOops || UseCompressedClassPointers) {
6031 if (Universe::heap() != NULL) {
6032 if (Universe::narrow_oop_base() == NULL) {
6033 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6034 } else {
6035 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
6036 }
6037 } else {
6038 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6039 }
6040 }
6041 }
6042
6043 #endif // _LP64
6044
6045
6046 // C2 compiled method's prolog code.
6047 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
6048
6049 // WARNING: Initial instruction MUST be 5 bytes or longer so that
6050 // NativeJump::patch_verified_entry will be able to patch out the entry
6051 // code safely. The push to verify stack depth is ok at 5 bytes,
6052 // the frame allocation can be either 3 or 6 bytes. So if we don't do
6053 // stack bang then we must use the 6 byte frame allocation even if
6054 // we have no frame. :-(
6055 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
6056
6057 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6058 // Remove word for return addr
6059 framesize -= wordSize;
6060 stack_bang_size -= wordSize;
6061
6062 // Calls to C2R adapters often do not accept exceptional returns.
6063 // We require that their callers must bang for them. But be careful, because
6064 // some VM calls (such as call site linkage) can use several kilobytes of
6065 // stack. But the stack safety zone should account for that.
6066 // See bugs 4446381, 4468289, 4497237.
6067 if (stack_bang_size > 0) {
6068 generate_stack_overflow_check(stack_bang_size);
6069
6070 // We always push rbp, so that on return to interpreter rbp, will be
6071 // restored correctly and we can correct the stack.
6072 push(rbp);
6073 // Save caller's stack pointer into RBP if the frame pointer is preserved.
6074 if (PreserveFramePointer) {
6075 mov(rbp, rsp);
6076 }
6077 // Remove word for ebp
6078 framesize -= wordSize;
6079
6080 // Create frame
6081 if (framesize) {
6082 subptr(rsp, framesize);
6083 }
6084 } else {
6085 // Create frame (force generation of a 4 byte immediate value)
6086 subptr_imm32(rsp, framesize);
6087
6088 // Save RBP register now.
6089 framesize -= wordSize;
6090 movptr(Address(rsp, framesize), rbp);
6091 // Save caller's stack pointer into RBP if the frame pointer is preserved.
6092 if (PreserveFramePointer) {
6093 movptr(rbp, rsp);
6094 addptr(rbp, framesize + wordSize);
6095 }
6096 }
6097
6098 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
6099 framesize -= wordSize;
6100 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
6101 }
6102
6103 #ifndef _LP64
6104 // If method sets FPU control word do it now
6105 if (fp_mode_24b) {
6106 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
6107 }
6108 if (UseSSE >= 2 && VerifyFPU) {
6109 verify_FPU(0, "FPU stack must be clean on entry");
6110 }
6111 #endif
6112
6113 #ifdef ASSERT
6114 if (VerifyStackAtCalls) {
6115 Label L;
6116 push(rax);
6117 mov(rax, rsp);
6118 andptr(rax, StackAlignmentInBytes-1);
6119 cmpptr(rax, StackAlignmentInBytes-wordSize);
6120 pop(rax);
6121 jcc(Assembler::equal, L);
6122 STOP("Stack is not properly aligned!");
6123 bind(L);
6124 }
6125 #endif
6126
6127 }
6128
6129 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp) {
6130 // cnt - number of qwords (8-byte words).
6131 // base - start address, qword aligned.
6132 assert(base==rdi, "base register must be edi for rep stos");
6133 assert(tmp==rax, "tmp register must be eax for rep stos");
6134 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6135
6136 xorptr(tmp, tmp);
6137 if (UseFastStosb) {
6138 shlptr(cnt,3); // convert to number of bytes
6139 rep_stosb();
6140 } else {
6141 NOT_LP64(shlptr(cnt,1);) // convert to number of dwords for 32-bit VM
6142 rep_stos();
6143 }
6144 }
6145
6146 // IndexOf for constant substrings with size >= 8 chars
6147 // which don't need to be loaded through stack.
6148 void MacroAssembler::string_indexofC8(Register str1, Register str2,
6149 Register cnt1, Register cnt2,
6150 int int_cnt2, Register result,
6151 XMMRegister vec, Register tmp) {
6152 ShortBranchVerifier sbv(this);
6153 assert(UseSSE42Intrinsics, "SSE4.2 is required");
6154
6155 // This method uses pcmpestri instruction with bound registers
6156 // inputs:
6157 // xmm - substring
6158 // rax - substring length (elements count)
6159 // mem - scanned string
6160 // rdx - string length (elements count)
6161 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6162 // outputs:
6163 // rcx - matched index in string
6164 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6165
6166 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
6167 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
6168 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
6169
6170 // Note, inline_string_indexOf() generates checks:
6171 // if (substr.count > string.count) return -1;
6172 // if (substr.count == 0) return 0;
6173 assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars");
6174
6175 // Load substring.
6176 movdqu(vec, Address(str2, 0));
6177 movl(cnt2, int_cnt2);
6178 movptr(result, str1); // string addr
6179
6180 if (int_cnt2 > 8) {
6181 jmpb(SCAN_TO_SUBSTR);
6182
6183 // Reload substr for rescan, this code
6184 // is executed only for large substrings (> 8 chars)
6185 bind(RELOAD_SUBSTR);
6186 movdqu(vec, Address(str2, 0));
6187 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
6188
6189 bind(RELOAD_STR);
6190 // We came here after the beginning of the substring was
6191 // matched but the rest of it was not so we need to search
6192 // again. Start from the next element after the previous match.
6193
6194 // cnt2 is number of substring reminding elements and
6195 // cnt1 is number of string reminding elements when cmp failed.
6196 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
6197 subl(cnt1, cnt2);
6198 addl(cnt1, int_cnt2);
6199 movl(cnt2, int_cnt2); // Now restore cnt2
6200
6201 decrementl(cnt1); // Shift to next element
6202 cmpl(cnt1, cnt2);
6203 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6204
6205 addptr(result, 2);
6206
6207 } // (int_cnt2 > 8)
6208
6209 // Scan string for start of substr in 16-byte vectors
6210 bind(SCAN_TO_SUBSTR);
6211 pcmpestri(vec, Address(result, 0), 0x0d);
6212 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6213 subl(cnt1, 8);
6214 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6215 cmpl(cnt1, cnt2);
6216 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6217 addptr(result, 16);
6218 jmpb(SCAN_TO_SUBSTR);
6219
6220 // Found a potential substr
6221 bind(FOUND_CANDIDATE);
6222 // Matched whole vector if first element matched (tmp(rcx) == 0).
6223 if (int_cnt2 == 8) {
6224 jccb(Assembler::overflow, RET_FOUND); // OF == 1
6225 } else { // int_cnt2 > 8
6226 jccb(Assembler::overflow, FOUND_SUBSTR);
6227 }
6228 // After pcmpestri tmp(rcx) contains matched element index
6229 // Compute start addr of substr
6230 lea(result, Address(result, tmp, Address::times_2));
6231
6232 // Make sure string is still long enough
6233 subl(cnt1, tmp);
6234 cmpl(cnt1, cnt2);
6235 if (int_cnt2 == 8) {
6236 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6237 } else { // int_cnt2 > 8
6238 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
6239 }
6240 // Left less then substring.
6241
6242 bind(RET_NOT_FOUND);
6243 movl(result, -1);
6244 jmpb(EXIT);
6245
6246 if (int_cnt2 > 8) {
6247 // This code is optimized for the case when whole substring
6248 // is matched if its head is matched.
6249 bind(MATCH_SUBSTR_HEAD);
6250 pcmpestri(vec, Address(result, 0), 0x0d);
6251 // Reload only string if does not match
6252 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0
6253
6254 Label CONT_SCAN_SUBSTR;
6255 // Compare the rest of substring (> 8 chars).
6256 bind(FOUND_SUBSTR);
6257 // First 8 chars are already matched.
6258 negptr(cnt2);
6259 addptr(cnt2, 8);
6260
6261 bind(SCAN_SUBSTR);
6262 subl(cnt1, 8);
6263 cmpl(cnt2, -8); // Do not read beyond substring
6264 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
6265 // Back-up strings to avoid reading beyond substring:
6266 // cnt1 = cnt1 - cnt2 + 8
6267 addl(cnt1, cnt2); // cnt2 is negative
6268 addl(cnt1, 8);
6269 movl(cnt2, 8); negptr(cnt2);
6270 bind(CONT_SCAN_SUBSTR);
6271 if (int_cnt2 < (int)G) {
6272 movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2));
6273 pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d);
6274 } else {
6275 // calculate index in register to avoid integer overflow (int_cnt2*2)
6276 movl(tmp, int_cnt2);
6277 addptr(tmp, cnt2);
6278 movdqu(vec, Address(str2, tmp, Address::times_2, 0));
6279 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d);
6280 }
6281 // Need to reload strings pointers if not matched whole vector
6282 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6283 addptr(cnt2, 8);
6284 jcc(Assembler::negative, SCAN_SUBSTR);
6285 // Fall through if found full substring
6286
6287 } // (int_cnt2 > 8)
6288
6289 bind(RET_FOUND);
6290 // Found result if we matched full small substring.
6291 // Compute substr offset
6292 subptr(result, str1);
6293 shrl(result, 1); // index
6294 bind(EXIT);
6295
6296 } // string_indexofC8
6297
6298 // Small strings are loaded through stack if they cross page boundary.
6299 void MacroAssembler::string_indexof(Register str1, Register str2,
6300 Register cnt1, Register cnt2,
6301 int int_cnt2, Register result,
6302 XMMRegister vec, Register tmp) {
6303 ShortBranchVerifier sbv(this);
6304 assert(UseSSE42Intrinsics, "SSE4.2 is required");
6305 //
6306 // int_cnt2 is length of small (< 8 chars) constant substring
6307 // or (-1) for non constant substring in which case its length
6308 // is in cnt2 register.
6309 //
6310 // Note, inline_string_indexOf() generates checks:
6311 // if (substr.count > string.count) return -1;
6312 // if (substr.count == 0) return 0;
6313 //
6314 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0");
6315
6316 // This method uses pcmpestri instruction with bound registers
6317 // inputs:
6318 // xmm - substring
6319 // rax - substring length (elements count)
6320 // mem - scanned string
6321 // rdx - string length (elements count)
6322 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6323 // outputs:
6324 // rcx - matched index in string
6325 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6326
6327 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
6328 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
6329 FOUND_CANDIDATE;
6330
6331 { //========================================================
6332 // We don't know where these strings are located
6333 // and we can't read beyond them. Load them through stack.
6334 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
6335
6336 movptr(tmp, rsp); // save old SP
6337
6338 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
6339 if (int_cnt2 == 1) { // One char
6340 load_unsigned_short(result, Address(str2, 0));
6341 movdl(vec, result); // move 32 bits
6342 } else if (int_cnt2 == 2) { // Two chars
6343 movdl(vec, Address(str2, 0)); // move 32 bits
6344 } else if (int_cnt2 == 4) { // Four chars
6345 movq(vec, Address(str2, 0)); // move 64 bits
6346 } else { // cnt2 = { 3, 5, 6, 7 }
6347 // Array header size is 12 bytes in 32-bit VM
6348 // + 6 bytes for 3 chars == 18 bytes,
6349 // enough space to load vec and shift.
6350 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
6351 movdqu(vec, Address(str2, (int_cnt2*2)-16));
6352 psrldq(vec, 16-(int_cnt2*2));
6353 }
6354 } else { // not constant substring
6355 cmpl(cnt2, 8);
6356 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
6357
6358 // We can read beyond string if srt+16 does not cross page boundary
6359 // since heaps are aligned and mapped by pages.
6360 assert(os::vm_page_size() < (int)G, "default page should be small");
6361 movl(result, str2); // We need only low 32 bits
6362 andl(result, (os::vm_page_size()-1));
6363 cmpl(result, (os::vm_page_size()-16));
6364 jccb(Assembler::belowEqual, CHECK_STR);
6365
6366 // Move small strings to stack to allow load 16 bytes into vec.
6367 subptr(rsp, 16);
6368 int stk_offset = wordSize-2;
6369 push(cnt2);
6370
6371 bind(COPY_SUBSTR);
6372 load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2));
6373 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
6374 decrement(cnt2);
6375 jccb(Assembler::notZero, COPY_SUBSTR);
6376
6377 pop(cnt2);
6378 movptr(str2, rsp); // New substring address
6379 } // non constant
6380
6381 bind(CHECK_STR);
6382 cmpl(cnt1, 8);
6383 jccb(Assembler::aboveEqual, BIG_STRINGS);
6384
6385 // Check cross page boundary.
6386 movl(result, str1); // We need only low 32 bits
6387 andl(result, (os::vm_page_size()-1));
6388 cmpl(result, (os::vm_page_size()-16));
6389 jccb(Assembler::belowEqual, BIG_STRINGS);
6390
6391 subptr(rsp, 16);
6392 int stk_offset = -2;
6393 if (int_cnt2 < 0) { // not constant
6394 push(cnt2);
6395 stk_offset += wordSize;
6396 }
6397 movl(cnt2, cnt1);
6398
6399 bind(COPY_STR);
6400 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2));
6401 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
6402 decrement(cnt2);
6403 jccb(Assembler::notZero, COPY_STR);
6404
6405 if (int_cnt2 < 0) { // not constant
6406 pop(cnt2);
6407 }
6408 movptr(str1, rsp); // New string address
6409
6410 bind(BIG_STRINGS);
6411 // Load substring.
6412 if (int_cnt2 < 0) { // -1
6413 movdqu(vec, Address(str2, 0));
6414 push(cnt2); // substr count
6415 push(str2); // substr addr
6416 push(str1); // string addr
6417 } else {
6418 // Small (< 8 chars) constant substrings are loaded already.
6419 movl(cnt2, int_cnt2);
6420 }
6421 push(tmp); // original SP
6422
6423 } // Finished loading
6424
6425 //========================================================
6426 // Start search
6427 //
6428
6429 movptr(result, str1); // string addr
6430
6431 if (int_cnt2 < 0) { // Only for non constant substring
6432 jmpb(SCAN_TO_SUBSTR);
6433
6434 // SP saved at sp+0
6435 // String saved at sp+1*wordSize
6436 // Substr saved at sp+2*wordSize
6437 // Substr count saved at sp+3*wordSize
6438
6439 // Reload substr for rescan, this code
6440 // is executed only for large substrings (> 8 chars)
6441 bind(RELOAD_SUBSTR);
6442 movptr(str2, Address(rsp, 2*wordSize));
6443 movl(cnt2, Address(rsp, 3*wordSize));
6444 movdqu(vec, Address(str2, 0));
6445 // We came here after the beginning of the substring was
6446 // matched but the rest of it was not so we need to search
6447 // again. Start from the next element after the previous match.
6448 subptr(str1, result); // Restore counter
6449 shrl(str1, 1);
6450 addl(cnt1, str1);
6451 decrementl(cnt1); // Shift to next element
6452 cmpl(cnt1, cnt2);
6453 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6454
6455 addptr(result, 2);
6456 } // non constant
6457
6458 // Scan string for start of substr in 16-byte vectors
6459 bind(SCAN_TO_SUBSTR);
6460 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6461 pcmpestri(vec, Address(result, 0), 0x0d);
6462 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6463 subl(cnt1, 8);
6464 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6465 cmpl(cnt1, cnt2);
6466 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6467 addptr(result, 16);
6468
6469 bind(ADJUST_STR);
6470 cmpl(cnt1, 8); // Do not read beyond string
6471 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6472 // Back-up string to avoid reading beyond string.
6473 lea(result, Address(result, cnt1, Address::times_2, -16));
6474 movl(cnt1, 8);
6475 jmpb(SCAN_TO_SUBSTR);
6476
6477 // Found a potential substr
6478 bind(FOUND_CANDIDATE);
6479 // After pcmpestri tmp(rcx) contains matched element index
6480
6481 // Make sure string is still long enough
6482 subl(cnt1, tmp);
6483 cmpl(cnt1, cnt2);
6484 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
6485 // Left less then substring.
6486
6487 bind(RET_NOT_FOUND);
6488 movl(result, -1);
6489 jmpb(CLEANUP);
6490
6491 bind(FOUND_SUBSTR);
6492 // Compute start addr of substr
6493 lea(result, Address(result, tmp, Address::times_2));
6494
6495 if (int_cnt2 > 0) { // Constant substring
6496 // Repeat search for small substring (< 8 chars)
6497 // from new point without reloading substring.
6498 // Have to check that we don't read beyond string.
6499 cmpl(tmp, 8-int_cnt2);
6500 jccb(Assembler::greater, ADJUST_STR);
6501 // Fall through if matched whole substring.
6502 } else { // non constant
6503 assert(int_cnt2 == -1, "should be != 0");
6504
6505 addl(tmp, cnt2);
6506 // Found result if we matched whole substring.
6507 cmpl(tmp, 8);
6508 jccb(Assembler::lessEqual, RET_FOUND);
6509
6510 // Repeat search for small substring (<= 8 chars)
6511 // from new point 'str1' without reloading substring.
6512 cmpl(cnt2, 8);
6513 // Have to check that we don't read beyond string.
6514 jccb(Assembler::lessEqual, ADJUST_STR);
6515
6516 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
6517 // Compare the rest of substring (> 8 chars).
6518 movptr(str1, result);
6519
6520 cmpl(tmp, cnt2);
6521 // First 8 chars are already matched.
6522 jccb(Assembler::equal, CHECK_NEXT);
6523
6524 bind(SCAN_SUBSTR);
6525 pcmpestri(vec, Address(str1, 0), 0x0d);
6526 // Need to reload strings pointers if not matched whole vector
6527 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6528
6529 bind(CHECK_NEXT);
6530 subl(cnt2, 8);
6531 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
6532 addptr(str1, 16);
6533 addptr(str2, 16);
6534 subl(cnt1, 8);
6535 cmpl(cnt2, 8); // Do not read beyond substring
6536 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
6537 // Back-up strings to avoid reading beyond substring.
6538 lea(str2, Address(str2, cnt2, Address::times_2, -16));
6539 lea(str1, Address(str1, cnt2, Address::times_2, -16));
6540 subl(cnt1, cnt2);
6541 movl(cnt2, 8);
6542 addl(cnt1, 8);
6543 bind(CONT_SCAN_SUBSTR);
6544 movdqu(vec, Address(str2, 0));
6545 jmpb(SCAN_SUBSTR);
6546
6547 bind(RET_FOUND_LONG);
6548 movptr(str1, Address(rsp, wordSize));
6549 } // non constant
6550
6551 bind(RET_FOUND);
6552 // Compute substr offset
6553 subptr(result, str1);
6554 shrl(result, 1); // index
6555
6556 bind(CLEANUP);
6557 pop(rsp); // restore SP
6558
6559 } // string_indexof
6560
6561 // Compare strings.
6562 void MacroAssembler::string_compare(Register str1, Register str2,
6563 Register cnt1, Register cnt2, Register result,
6564 XMMRegister vec1) {
6565 ShortBranchVerifier sbv(this);
6566 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
6567
6568 // Compute the minimum of the string lengths and the
6569 // difference of the string lengths (stack).
6570 // Do the conditional move stuff
6571 movl(result, cnt1);
6572 subl(cnt1, cnt2);
6573 push(cnt1);
6574 cmov32(Assembler::lessEqual, cnt2, result);
6575
6576 // Is the minimum length zero?
6577 testl(cnt2, cnt2);
6578 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6579
6580 // Compare first characters
6581 load_unsigned_short(result, Address(str1, 0));
6582 load_unsigned_short(cnt1, Address(str2, 0));
6583 subl(result, cnt1);
6584 jcc(Assembler::notZero, POP_LABEL);
6585 cmpl(cnt2, 1);
6586 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6587
6588 // Check if the strings start at the same location.
6589 cmpptr(str1, str2);
6590 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6591
6592 Address::ScaleFactor scale = Address::times_2;
6593 int stride = 8;
6594
6595 if (UseAVX >= 2 && UseSSE42Intrinsics) {
6596 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
6597 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
6598 Label COMPARE_TAIL_LONG;
6599 int pcmpmask = 0x19;
6600
6601 // Setup to compare 16-chars (32-bytes) vectors,
6602 // start from first character again because it has aligned address.
6603 int stride2 = 16;
6604 int adr_stride = stride << scale;
6605
6606 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6607 // rax and rdx are used by pcmpestri as elements counters
6608 movl(result, cnt2);
6609 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
6610 jcc(Assembler::zero, COMPARE_TAIL_LONG);
6611
6612 // fast path : compare first 2 8-char vectors.
6613 bind(COMPARE_16_CHARS);
6614 movdqu(vec1, Address(str1, 0));
6615 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6616 jccb(Assembler::below, COMPARE_INDEX_CHAR);
6617
6618 movdqu(vec1, Address(str1, adr_stride));
6619 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
6620 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
6621 addl(cnt1, stride);
6622
6623 // Compare the characters at index in cnt1
6624 bind(COMPARE_INDEX_CHAR); //cnt1 has the offset of the mismatching character
6625 load_unsigned_short(result, Address(str1, cnt1, scale));
6626 load_unsigned_short(cnt2, Address(str2, cnt1, scale));
6627 subl(result, cnt2);
6628 jmp(POP_LABEL);
6629
6630 // Setup the registers to start vector comparison loop
6631 bind(COMPARE_WIDE_VECTORS);
6632 lea(str1, Address(str1, result, scale));
6633 lea(str2, Address(str2, result, scale));
6634 subl(result, stride2);
6635 subl(cnt2, stride2);
6636 jccb(Assembler::zero, COMPARE_WIDE_TAIL);
6637 negptr(result);
6638
6639 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
6640 bind(COMPARE_WIDE_VECTORS_LOOP);
6641 vmovdqu(vec1, Address(str1, result, scale));
6642 vpxor(vec1, Address(str2, result, scale));
6643 vptest(vec1, vec1);
6644 jccb(Assembler::notZero, VECTOR_NOT_EQUAL);
6645 addptr(result, stride2);
6646 subl(cnt2, stride2);
6647 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
6648 // clean upper bits of YMM registers
6649 vpxor(vec1, vec1);
6650
6651 // compare wide vectors tail
6652 bind(COMPARE_WIDE_TAIL);
6653 testptr(result, result);
6654 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6655
6656 movl(result, stride2);
6657 movl(cnt2, result);
6658 negptr(result);
6659 jmpb(COMPARE_WIDE_VECTORS_LOOP);
6660
6661 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
6662 bind(VECTOR_NOT_EQUAL);
6663 // clean upper bits of YMM registers
6664 vpxor(vec1, vec1);
6665 lea(str1, Address(str1, result, scale));
6666 lea(str2, Address(str2, result, scale));
6667 jmp(COMPARE_16_CHARS);
6668
6669 // Compare tail chars, length between 1 to 15 chars
6670 bind(COMPARE_TAIL_LONG);
6671 movl(cnt2, result);
6672 cmpl(cnt2, stride);
6673 jccb(Assembler::less, COMPARE_SMALL_STR);
6674
6675 movdqu(vec1, Address(str1, 0));
6676 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6677 jcc(Assembler::below, COMPARE_INDEX_CHAR);
6678 subptr(cnt2, stride);
6679 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6680 lea(str1, Address(str1, result, scale));
6681 lea(str2, Address(str2, result, scale));
6682 negptr(cnt2);
6683 jmpb(WHILE_HEAD_LABEL);
6684
6685 bind(COMPARE_SMALL_STR);
6686 } else if (UseSSE42Intrinsics) {
6687 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
6688 int pcmpmask = 0x19;
6689 // Setup to compare 8-char (16-byte) vectors,
6690 // start from first character again because it has aligned address.
6691 movl(result, cnt2);
6692 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
6693 jccb(Assembler::zero, COMPARE_TAIL);
6694
6695 lea(str1, Address(str1, result, scale));
6696 lea(str2, Address(str2, result, scale));
6697 negptr(result);
6698
6699 // pcmpestri
6700 // inputs:
6701 // vec1- substring
6702 // rax - negative string length (elements count)
6703 // mem - scanned string
6704 // rdx - string length (elements count)
6705 // pcmpmask - cmp mode: 11000 (string compare with negated result)
6706 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
6707 // outputs:
6708 // rcx - first mismatched element index
6709 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6710
6711 bind(COMPARE_WIDE_VECTORS);
6712 movdqu(vec1, Address(str1, result, scale));
6713 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6714 // After pcmpestri cnt1(rcx) contains mismatched element index
6715
6716 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
6717 addptr(result, stride);
6718 subptr(cnt2, stride);
6719 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
6720
6721 // compare wide vectors tail
6722 testptr(result, result);
6723 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6724
6725 movl(cnt2, stride);
6726 movl(result, stride);
6727 negptr(result);
6728 movdqu(vec1, Address(str1, result, scale));
6729 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6730 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
6731
6732 // Mismatched characters in the vectors
6733 bind(VECTOR_NOT_EQUAL);
6734 addptr(cnt1, result);
6735 load_unsigned_short(result, Address(str1, cnt1, scale));
6736 load_unsigned_short(cnt2, Address(str2, cnt1, scale));
6737 subl(result, cnt2);
6738 jmpb(POP_LABEL);
6739
6740 bind(COMPARE_TAIL); // limit is zero
6741 movl(cnt2, result);
6742 // Fallthru to tail compare
6743 }
6744 // Shift str2 and str1 to the end of the arrays, negate min
6745 lea(str1, Address(str1, cnt2, scale));
6746 lea(str2, Address(str2, cnt2, scale));
6747 decrementl(cnt2); // first character was compared already
6748 negptr(cnt2);
6749
6750 // Compare the rest of the elements
6751 bind(WHILE_HEAD_LABEL);
6752 load_unsigned_short(result, Address(str1, cnt2, scale, 0));
6753 load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0));
6754 subl(result, cnt1);
6755 jccb(Assembler::notZero, POP_LABEL);
6756 increment(cnt2);
6757 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
6758
6759 // Strings are equal up to min length. Return the length difference.
6760 bind(LENGTH_DIFF_LABEL);
6761 pop(result);
6762 jmpb(DONE_LABEL);
6763
6764 // Discard the stored length difference
6765 bind(POP_LABEL);
6766 pop(cnt1);
6767
6768 // That's it
6769 bind(DONE_LABEL);
6770 }
6771
6772 // Compare char[] arrays aligned to 4 bytes or substrings.
6773 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
6774 Register limit, Register result, Register chr,
6775 XMMRegister vec1, XMMRegister vec2) {
6776 ShortBranchVerifier sbv(this);
6777 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
6778
6779 int length_offset = arrayOopDesc::length_offset_in_bytes();
6780 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
6781
6782 // Check the input args
6783 cmpptr(ary1, ary2);
6784 jcc(Assembler::equal, TRUE_LABEL);
6785
6786 if (is_array_equ) {
6787 // Need additional checks for arrays_equals.
6788 testptr(ary1, ary1);
6789 jcc(Assembler::zero, FALSE_LABEL);
6790 testptr(ary2, ary2);
6791 jcc(Assembler::zero, FALSE_LABEL);
6792
6793 // Check the lengths
6794 movl(limit, Address(ary1, length_offset));
6795 cmpl(limit, Address(ary2, length_offset));
6796 jcc(Assembler::notEqual, FALSE_LABEL);
6797 }
6798
6799 // count == 0
6800 testl(limit, limit);
6801 jcc(Assembler::zero, TRUE_LABEL);
6802
6803 if (is_array_equ) {
6804 // Load array address
6805 lea(ary1, Address(ary1, base_offset));
6806 lea(ary2, Address(ary2, base_offset));
6807 }
6808
6809 shll(limit, 1); // byte count != 0
6810 movl(result, limit); // copy
6811
6812 if (UseAVX >= 2) {
6813 // With AVX2, use 32-byte vector compare
6814 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6815
6816 // Compare 32-byte vectors
6817 andl(result, 0x0000001e); // tail count (in bytes)
6818 andl(limit, 0xffffffe0); // vector count (in bytes)
6819 jccb(Assembler::zero, COMPARE_TAIL);
6820
6821 lea(ary1, Address(ary1, limit, Address::times_1));
6822 lea(ary2, Address(ary2, limit, Address::times_1));
6823 negptr(limit);
6824
6825 bind(COMPARE_WIDE_VECTORS);
6826 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
6827 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
6828 vpxor(vec1, vec2);
6829
6830 vptest(vec1, vec1);
6831 jccb(Assembler::notZero, FALSE_LABEL);
6832 addptr(limit, 32);
6833 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6834
6835 testl(result, result);
6836 jccb(Assembler::zero, TRUE_LABEL);
6837
6838 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
6839 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
6840 vpxor(vec1, vec2);
6841
6842 vptest(vec1, vec1);
6843 jccb(Assembler::notZero, FALSE_LABEL);
6844 jmpb(TRUE_LABEL);
6845
6846 bind(COMPARE_TAIL); // limit is zero
6847 movl(limit, result);
6848 // Fallthru to tail compare
6849 } else if (UseSSE42Intrinsics) {
6850 // With SSE4.2, use double quad vector compare
6851 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6852
6853 // Compare 16-byte vectors
6854 andl(result, 0x0000000e); // tail count (in bytes)
6855 andl(limit, 0xfffffff0); // vector count (in bytes)
6856 jccb(Assembler::zero, COMPARE_TAIL);
6857
6858 lea(ary1, Address(ary1, limit, Address::times_1));
6859 lea(ary2, Address(ary2, limit, Address::times_1));
6860 negptr(limit);
6861
6862 bind(COMPARE_WIDE_VECTORS);
6863 movdqu(vec1, Address(ary1, limit, Address::times_1));
6864 movdqu(vec2, Address(ary2, limit, Address::times_1));
6865 pxor(vec1, vec2);
6866
6867 ptest(vec1, vec1);
6868 jccb(Assembler::notZero, FALSE_LABEL);
6869 addptr(limit, 16);
6870 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6871
6872 testl(result, result);
6873 jccb(Assembler::zero, TRUE_LABEL);
6874
6875 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
6876 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
6877 pxor(vec1, vec2);
6878
6879 ptest(vec1, vec1);
6880 jccb(Assembler::notZero, FALSE_LABEL);
6881 jmpb(TRUE_LABEL);
6882
6883 bind(COMPARE_TAIL); // limit is zero
6884 movl(limit, result);
6885 // Fallthru to tail compare
6886 }
6887
6888 // Compare 4-byte vectors
6889 andl(limit, 0xfffffffc); // vector count (in bytes)
6890 jccb(Assembler::zero, COMPARE_CHAR);
6891
6892 lea(ary1, Address(ary1, limit, Address::times_1));
6893 lea(ary2, Address(ary2, limit, Address::times_1));
6894 negptr(limit);
6895
6896 bind(COMPARE_VECTORS);
6897 movl(chr, Address(ary1, limit, Address::times_1));
6898 cmpl(chr, Address(ary2, limit, Address::times_1));
6899 jccb(Assembler::notEqual, FALSE_LABEL);
6900 addptr(limit, 4);
6901 jcc(Assembler::notZero, COMPARE_VECTORS);
6902
6903 // Compare trailing char (final 2 bytes), if any
6904 bind(COMPARE_CHAR);
6905 testl(result, 0x2); // tail char
6906 jccb(Assembler::zero, TRUE_LABEL);
6907 load_unsigned_short(chr, Address(ary1, 0));
6908 load_unsigned_short(limit, Address(ary2, 0));
6909 cmpl(chr, limit);
6910 jccb(Assembler::notEqual, FALSE_LABEL);
6911
6912 bind(TRUE_LABEL);
6913 movl(result, 1); // return true
6914 jmpb(DONE);
6915
6916 bind(FALSE_LABEL);
6917 xorl(result, result); // return false
6918
6919 // That's it
6920 bind(DONE);
6921 if (UseAVX >= 2) {
6922 // clean upper bits of YMM registers
6923 vpxor(vec1, vec1);
6924 vpxor(vec2, vec2);
6925 }
6926 }
6927
6928 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6929 Register to, Register value, Register count,
6930 Register rtmp, XMMRegister xtmp) {
6931 ShortBranchVerifier sbv(this);
6932 assert_different_registers(to, value, count, rtmp);
6933 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
6934 Label L_fill_2_bytes, L_fill_4_bytes;
6935
6936 int shift = -1;
6937 switch (t) {
6938 case T_BYTE:
6939 shift = 2;
6940 break;
6941 case T_SHORT:
6942 shift = 1;
6943 break;
6944 case T_INT:
6945 shift = 0;
6946 break;
6947 default: ShouldNotReachHere();
6948 }
6949
6950 if (t == T_BYTE) {
6951 andl(value, 0xff);
6952 movl(rtmp, value);
6953 shll(rtmp, 8);
6954 orl(value, rtmp);
6955 }
6956 if (t == T_SHORT) {
6957 andl(value, 0xffff);
6958 }
6959 if (t == T_BYTE || t == T_SHORT) {
6960 movl(rtmp, value);
6961 shll(rtmp, 16);
6962 orl(value, rtmp);
6963 }
6964
6965 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
6966 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6967 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6968 // align source address at 4 bytes address boundary
6969 if (t == T_BYTE) {
6970 // One byte misalignment happens only for byte arrays
6971 testptr(to, 1);
6972 jccb(Assembler::zero, L_skip_align1);
6973 movb(Address(to, 0), value);
6974 increment(to);
6975 decrement(count);
6976 BIND(L_skip_align1);
6977 }
6978 // Two bytes misalignment happens only for byte and short (char) arrays
6979 testptr(to, 2);
6980 jccb(Assembler::zero, L_skip_align2);
6981 movw(Address(to, 0), value);
6982 addptr(to, 2);
6983 subl(count, 1<<(shift-1));
6984 BIND(L_skip_align2);
6985 }
6986 if (UseSSE < 2) {
6987 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6988 // Fill 32-byte chunks
6989 subl(count, 8 << shift);
6990 jcc(Assembler::less, L_check_fill_8_bytes);
6991 align(16);
6992
6993 BIND(L_fill_32_bytes_loop);
6994
6995 for (int i = 0; i < 32; i += 4) {
6996 movl(Address(to, i), value);
6997 }
6998
6999 addptr(to, 32);
7000 subl(count, 8 << shift);
7001 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7002 BIND(L_check_fill_8_bytes);
7003 addl(count, 8 << shift);
7004 jccb(Assembler::zero, L_exit);
7005 jmpb(L_fill_8_bytes);
7006
7007 //
7008 // length is too short, just fill qwords
7009 //
7010 BIND(L_fill_8_bytes_loop);
7011 movl(Address(to, 0), value);
7012 movl(Address(to, 4), value);
7013 addptr(to, 8);
7014 BIND(L_fill_8_bytes);
7015 subl(count, 1 << (shift + 1));
7016 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7017 // fall through to fill 4 bytes
7018 } else {
7019 Label L_fill_32_bytes;
7020 if (!UseUnalignedLoadStores) {
7021 // align to 8 bytes, we know we are 4 byte aligned to start
7022 testptr(to, 4);
7023 jccb(Assembler::zero, L_fill_32_bytes);
7024 movl(Address(to, 0), value);
7025 addptr(to, 4);
7026 subl(count, 1<<shift);
7027 }
7028 BIND(L_fill_32_bytes);
7029 {
7030 assert( UseSSE >= 2, "supported cpu only" );
7031 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7032 if (UseAVX > 2) {
7033 movl(rtmp, 0xffff);
7034 #ifdef _LP64
7035 kmovql(k1, rtmp);
7036 #else
7037 kmovdl(k1, rtmp);
7038 #endif
7039 }
7040 movdl(xtmp, value);
7041 if (UseAVX > 2 && UseUnalignedLoadStores) {
7042 // Fill 64-byte chunks
7043 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
7044 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
7045
7046 subl(count, 16 << shift);
7047 jcc(Assembler::less, L_check_fill_32_bytes);
7048 align(16);
7049
7050 BIND(L_fill_64_bytes_loop);
7051 evmovdqu(Address(to, 0), xtmp, Assembler::AVX_512bit);
7052 addptr(to, 64);
7053 subl(count, 16 << shift);
7054 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7055
7056 BIND(L_check_fill_32_bytes);
7057 addl(count, 8 << shift);
7058 jccb(Assembler::less, L_check_fill_8_bytes);
7059 evmovdqu(Address(to, 0), xtmp, Assembler::AVX_256bit);
7060 addptr(to, 32);
7061 subl(count, 8 << shift);
7062
7063 BIND(L_check_fill_8_bytes);
7064 } else if (UseAVX == 2 && UseUnalignedLoadStores) {
7065 // Fill 64-byte chunks
7066 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
7067 vpbroadcastd(xtmp, xtmp);
7068
7069 subl(count, 16 << shift);
7070 jcc(Assembler::less, L_check_fill_32_bytes);
7071 align(16);
7072
7073 BIND(L_fill_64_bytes_loop);
7074 vmovdqu(Address(to, 0), xtmp);
7075 vmovdqu(Address(to, 32), xtmp);
7076 addptr(to, 64);
7077 subl(count, 16 << shift);
7078 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7079
7080 BIND(L_check_fill_32_bytes);
7081 addl(count, 8 << shift);
7082 jccb(Assembler::less, L_check_fill_8_bytes);
7083 vmovdqu(Address(to, 0), xtmp);
7084 addptr(to, 32);
7085 subl(count, 8 << shift);
7086
7087 BIND(L_check_fill_8_bytes);
7088 // clean upper bits of YMM registers
7089 movdl(xtmp, value);
7090 pshufd(xtmp, xtmp, 0);
7091 } else {
7092 // Fill 32-byte chunks
7093 pshufd(xtmp, xtmp, 0);
7094
7095 subl(count, 8 << shift);
7096 jcc(Assembler::less, L_check_fill_8_bytes);
7097 align(16);
7098
7099 BIND(L_fill_32_bytes_loop);
7100
7101 if (UseUnalignedLoadStores) {
7102 movdqu(Address(to, 0), xtmp);
7103 movdqu(Address(to, 16), xtmp);
7104 } else {
7105 movq(Address(to, 0), xtmp);
7106 movq(Address(to, 8), xtmp);
7107 movq(Address(to, 16), xtmp);
7108 movq(Address(to, 24), xtmp);
7109 }
7110
7111 addptr(to, 32);
7112 subl(count, 8 << shift);
7113 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7114
7115 BIND(L_check_fill_8_bytes);
7116 }
7117 addl(count, 8 << shift);
7118 jccb(Assembler::zero, L_exit);
7119 jmpb(L_fill_8_bytes);
7120
7121 //
7122 // length is too short, just fill qwords
7123 //
7124 BIND(L_fill_8_bytes_loop);
7125 movq(Address(to, 0), xtmp);
7126 addptr(to, 8);
7127 BIND(L_fill_8_bytes);
7128 subl(count, 1 << (shift + 1));
7129 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7130 }
7131 }
7132 // fill trailing 4 bytes
7133 BIND(L_fill_4_bytes);
7134 testl(count, 1<<shift);
7135 jccb(Assembler::zero, L_fill_2_bytes);
7136 movl(Address(to, 0), value);
7137 if (t == T_BYTE || t == T_SHORT) {
7138 addptr(to, 4);
7139 BIND(L_fill_2_bytes);
7140 // fill trailing 2 bytes
7141 testl(count, 1<<(shift-1));
7142 jccb(Assembler::zero, L_fill_byte);
7143 movw(Address(to, 0), value);
7144 if (t == T_BYTE) {
7145 addptr(to, 2);
7146 BIND(L_fill_byte);
7147 // fill trailing byte
7148 testl(count, 1);
7149 jccb(Assembler::zero, L_exit);
7150 movb(Address(to, 0), value);
7151 } else {
7152 BIND(L_fill_byte);
7153 }
7154 } else {
7155 BIND(L_fill_2_bytes);
7156 }
7157 BIND(L_exit);
7158 }
7159
7160 // encode char[] to byte[] in ISO_8859_1
7161 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7162 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7163 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7164 Register tmp5, Register result) {
7165 // rsi: src
7166 // rdi: dst
7167 // rdx: len
7168 // rcx: tmp5
7169 // rax: result
7170 ShortBranchVerifier sbv(this);
7171 assert_different_registers(src, dst, len, tmp5, result);
7172 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7173
7174 // set result
7175 xorl(result, result);
7176 // check for zero length
7177 testl(len, len);
7178 jcc(Assembler::zero, L_done);
7179 movl(result, len);
7180
7181 // Setup pointers
7182 lea(src, Address(src, len, Address::times_2)); // char[]
7183 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7184 negptr(len);
7185
7186 if (UseSSE42Intrinsics || UseAVX >= 2) {
7187 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
7188 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7189
7190 if (UseAVX >= 2) {
7191 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7192 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7193 movdl(tmp1Reg, tmp5);
7194 vpbroadcastd(tmp1Reg, tmp1Reg);
7195 jmpb(L_chars_32_check);
7196
7197 bind(L_copy_32_chars);
7198 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7199 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7200 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7201 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7202 jccb(Assembler::notZero, L_copy_32_chars_exit);
7203 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7204 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
7205 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7206
7207 bind(L_chars_32_check);
7208 addptr(len, 32);
7209 jccb(Assembler::lessEqual, L_copy_32_chars);
7210
7211 bind(L_copy_32_chars_exit);
7212 subptr(len, 16);
7213 jccb(Assembler::greater, L_copy_16_chars_exit);
7214
7215 } else if (UseSSE42Intrinsics) {
7216 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7217 movdl(tmp1Reg, tmp5);
7218 pshufd(tmp1Reg, tmp1Reg, 0);
7219 jmpb(L_chars_16_check);
7220 }
7221
7222 bind(L_copy_16_chars);
7223 if (UseAVX >= 2) {
7224 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7225 vptest(tmp2Reg, tmp1Reg);
7226 jccb(Assembler::notZero, L_copy_16_chars_exit);
7227 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
7228 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
7229 } else {
7230 if (UseAVX > 0) {
7231 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7232 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7233 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
7234 } else {
7235 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7236 por(tmp2Reg, tmp3Reg);
7237 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7238 por(tmp2Reg, tmp4Reg);
7239 }
7240 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7241 jccb(Assembler::notZero, L_copy_16_chars_exit);
7242 packuswb(tmp3Reg, tmp4Reg);
7243 }
7244 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7245
7246 bind(L_chars_16_check);
7247 addptr(len, 16);
7248 jccb(Assembler::lessEqual, L_copy_16_chars);
7249
7250 bind(L_copy_16_chars_exit);
7251 if (UseAVX >= 2) {
7252 // clean upper bits of YMM registers
7253 vpxor(tmp2Reg, tmp2Reg);
7254 vpxor(tmp3Reg, tmp3Reg);
7255 vpxor(tmp4Reg, tmp4Reg);
7256 movdl(tmp1Reg, tmp5);
7257 pshufd(tmp1Reg, tmp1Reg, 0);
7258 }
7259 subptr(len, 8);
7260 jccb(Assembler::greater, L_copy_8_chars_exit);
7261
7262 bind(L_copy_8_chars);
7263 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7264 ptest(tmp3Reg, tmp1Reg);
7265 jccb(Assembler::notZero, L_copy_8_chars_exit);
7266 packuswb(tmp3Reg, tmp1Reg);
7267 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7268 addptr(len, 8);
7269 jccb(Assembler::lessEqual, L_copy_8_chars);
7270
7271 bind(L_copy_8_chars_exit);
7272 subptr(len, 8);
7273 jccb(Assembler::zero, L_done);
7274 }
7275
7276 bind(L_copy_1_char);
7277 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7278 testl(tmp5, 0xff00); // check if Unicode char
7279 jccb(Assembler::notZero, L_copy_1_char_exit);
7280 movb(Address(dst, len, Address::times_1, 0), tmp5);
7281 addptr(len, 1);
7282 jccb(Assembler::less, L_copy_1_char);
7283
7284 bind(L_copy_1_char_exit);
7285 addptr(result, len); // len is negative count of not processed elements
7286 bind(L_done);
7287 }
7288
7289 #ifdef _LP64
7290 /**
7291 * Helper for multiply_to_len().
7292 */
7293 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7294 addq(dest_lo, src1);
7295 adcq(dest_hi, 0);
7296 addq(dest_lo, src2);
7297 adcq(dest_hi, 0);
7298 }
7299
7300 /**
7301 * Multiply 64 bit by 64 bit first loop.
7302 */
7303 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7304 Register y, Register y_idx, Register z,
7305 Register carry, Register product,
7306 Register idx, Register kdx) {
7307 //
7308 // jlong carry, x[], y[], z[];
7309 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7310 // huge_128 product = y[idx] * x[xstart] + carry;
7311 // z[kdx] = (jlong)product;
7312 // carry = (jlong)(product >>> 64);
7313 // }
7314 // z[xstart] = carry;
7315 //
7316
7317 Label L_first_loop, L_first_loop_exit;
7318 Label L_one_x, L_one_y, L_multiply;
7319
7320 decrementl(xstart);
7321 jcc(Assembler::negative, L_one_x);
7322
7323 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7324 rorq(x_xstart, 32); // convert big-endian to little-endian
7325
7326 bind(L_first_loop);
7327 decrementl(idx);
7328 jcc(Assembler::negative, L_first_loop_exit);
7329 decrementl(idx);
7330 jcc(Assembler::negative, L_one_y);
7331 movq(y_idx, Address(y, idx, Address::times_4, 0));
7332 rorq(y_idx, 32); // convert big-endian to little-endian
7333 bind(L_multiply);
7334 movq(product, x_xstart);
7335 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7336 addq(product, carry);
7337 adcq(rdx, 0);
7338 subl(kdx, 2);
7339 movl(Address(z, kdx, Address::times_4, 4), product);
7340 shrq(product, 32);
7341 movl(Address(z, kdx, Address::times_4, 0), product);
7342 movq(carry, rdx);
7343 jmp(L_first_loop);
7344
7345 bind(L_one_y);
7346 movl(y_idx, Address(y, 0));
7347 jmp(L_multiply);
7348
7349 bind(L_one_x);
7350 movl(x_xstart, Address(x, 0));
7351 jmp(L_first_loop);
7352
7353 bind(L_first_loop_exit);
7354 }
7355
7356 /**
7357 * Multiply 64 bit by 64 bit and add 128 bit.
7358 */
7359 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7360 Register yz_idx, Register idx,
7361 Register carry, Register product, int offset) {
7362 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7363 // z[kdx] = (jlong)product;
7364
7365 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7366 rorq(yz_idx, 32); // convert big-endian to little-endian
7367 movq(product, x_xstart);
7368 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7369 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7370 rorq(yz_idx, 32); // convert big-endian to little-endian
7371
7372 add2_with_carry(rdx, product, carry, yz_idx);
7373
7374 movl(Address(z, idx, Address::times_4, offset+4), product);
7375 shrq(product, 32);
7376 movl(Address(z, idx, Address::times_4, offset), product);
7377
7378 }
7379
7380 /**
7381 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7382 */
7383 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7384 Register yz_idx, Register idx, Register jdx,
7385 Register carry, Register product,
7386 Register carry2) {
7387 // jlong carry, x[], y[], z[];
7388 // int kdx = ystart+1;
7389 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7390 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7391 // z[kdx+idx+1] = (jlong)product;
7392 // jlong carry2 = (jlong)(product >>> 64);
7393 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7394 // z[kdx+idx] = (jlong)product;
7395 // carry = (jlong)(product >>> 64);
7396 // }
7397 // idx += 2;
7398 // if (idx > 0) {
7399 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7400 // z[kdx+idx] = (jlong)product;
7401 // carry = (jlong)(product >>> 64);
7402 // }
7403 //
7404
7405 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7406
7407 movl(jdx, idx);
7408 andl(jdx, 0xFFFFFFFC);
7409 shrl(jdx, 2);
7410
7411 bind(L_third_loop);
7412 subl(jdx, 1);
7413 jcc(Assembler::negative, L_third_loop_exit);
7414 subl(idx, 4);
7415
7416 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7417 movq(carry2, rdx);
7418
7419 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7420 movq(carry, rdx);
7421 jmp(L_third_loop);
7422
7423 bind (L_third_loop_exit);
7424
7425 andl (idx, 0x3);
7426 jcc(Assembler::zero, L_post_third_loop_done);
7427
7428 Label L_check_1;
7429 subl(idx, 2);
7430 jcc(Assembler::negative, L_check_1);
7431
7432 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7433 movq(carry, rdx);
7434
7435 bind (L_check_1);
7436 addl (idx, 0x2);
7437 andl (idx, 0x1);
7438 subl(idx, 1);
7439 jcc(Assembler::negative, L_post_third_loop_done);
7440
7441 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7442 movq(product, x_xstart);
7443 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7444 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7445
7446 add2_with_carry(rdx, product, yz_idx, carry);
7447
7448 movl(Address(z, idx, Address::times_4, 0), product);
7449 shrq(product, 32);
7450
7451 shlq(rdx, 32);
7452 orq(product, rdx);
7453 movq(carry, product);
7454
7455 bind(L_post_third_loop_done);
7456 }
7457
7458 /**
7459 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7460 *
7461 */
7462 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7463 Register carry, Register carry2,
7464 Register idx, Register jdx,
7465 Register yz_idx1, Register yz_idx2,
7466 Register tmp, Register tmp3, Register tmp4) {
7467 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7468
7469 // jlong carry, x[], y[], z[];
7470 // int kdx = ystart+1;
7471 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7472 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7473 // jlong carry2 = (jlong)(tmp3 >>> 64);
7474 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7475 // carry = (jlong)(tmp4 >>> 64);
7476 // z[kdx+idx+1] = (jlong)tmp3;
7477 // z[kdx+idx] = (jlong)tmp4;
7478 // }
7479 // idx += 2;
7480 // if (idx > 0) {
7481 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7482 // z[kdx+idx] = (jlong)yz_idx1;
7483 // carry = (jlong)(yz_idx1 >>> 64);
7484 // }
7485 //
7486
7487 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7488
7489 movl(jdx, idx);
7490 andl(jdx, 0xFFFFFFFC);
7491 shrl(jdx, 2);
7492
7493 bind(L_third_loop);
7494 subl(jdx, 1);
7495 jcc(Assembler::negative, L_third_loop_exit);
7496 subl(idx, 4);
7497
7498 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7499 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7500 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7501 rorxq(yz_idx2, yz_idx2, 32);
7502
7503 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7504 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7505
7506 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7507 rorxq(yz_idx1, yz_idx1, 32);
7508 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7509 rorxq(yz_idx2, yz_idx2, 32);
7510
7511 if (VM_Version::supports_adx()) {
7512 adcxq(tmp3, carry);
7513 adoxq(tmp3, yz_idx1);
7514
7515 adcxq(tmp4, tmp);
7516 adoxq(tmp4, yz_idx2);
7517
7518 movl(carry, 0); // does not affect flags
7519 adcxq(carry2, carry);
7520 adoxq(carry2, carry);
7521 } else {
7522 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7523 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7524 }
7525 movq(carry, carry2);
7526
7527 movl(Address(z, idx, Address::times_4, 12), tmp3);
7528 shrq(tmp3, 32);
7529 movl(Address(z, idx, Address::times_4, 8), tmp3);
7530
7531 movl(Address(z, idx, Address::times_4, 4), tmp4);
7532 shrq(tmp4, 32);
7533 movl(Address(z, idx, Address::times_4, 0), tmp4);
7534
7535 jmp(L_third_loop);
7536
7537 bind (L_third_loop_exit);
7538
7539 andl (idx, 0x3);
7540 jcc(Assembler::zero, L_post_third_loop_done);
7541
7542 Label L_check_1;
7543 subl(idx, 2);
7544 jcc(Assembler::negative, L_check_1);
7545
7546 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7547 rorxq(yz_idx1, yz_idx1, 32);
7548 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7549 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7550 rorxq(yz_idx2, yz_idx2, 32);
7551
7552 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7553
7554 movl(Address(z, idx, Address::times_4, 4), tmp3);
7555 shrq(tmp3, 32);
7556 movl(Address(z, idx, Address::times_4, 0), tmp3);
7557 movq(carry, tmp4);
7558
7559 bind (L_check_1);
7560 addl (idx, 0x2);
7561 andl (idx, 0x1);
7562 subl(idx, 1);
7563 jcc(Assembler::negative, L_post_third_loop_done);
7564 movl(tmp4, Address(y, idx, Address::times_4, 0));
7565 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7566 movl(tmp4, Address(z, idx, Address::times_4, 0));
7567
7568 add2_with_carry(carry2, tmp3, tmp4, carry);
7569
7570 movl(Address(z, idx, Address::times_4, 0), tmp3);
7571 shrq(tmp3, 32);
7572
7573 shlq(carry2, 32);
7574 orq(tmp3, carry2);
7575 movq(carry, tmp3);
7576
7577 bind(L_post_third_loop_done);
7578 }
7579
7580 /**
7581 * Code for BigInteger::multiplyToLen() instrinsic.
7582 *
7583 * rdi: x
7584 * rax: xlen
7585 * rsi: y
7586 * rcx: ylen
7587 * r8: z
7588 * r11: zlen
7589 * r12: tmp1
7590 * r13: tmp2
7591 * r14: tmp3
7592 * r15: tmp4
7593 * rbx: tmp5
7594 *
7595 */
7596 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
7597 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7598 ShortBranchVerifier sbv(this);
7599 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7600
7601 push(tmp1);
7602 push(tmp2);
7603 push(tmp3);
7604 push(tmp4);
7605 push(tmp5);
7606
7607 push(xlen);
7608 push(zlen);
7609
7610 const Register idx = tmp1;
7611 const Register kdx = tmp2;
7612 const Register xstart = tmp3;
7613
7614 const Register y_idx = tmp4;
7615 const Register carry = tmp5;
7616 const Register product = xlen;
7617 const Register x_xstart = zlen; // reuse register
7618
7619 // First Loop.
7620 //
7621 // final static long LONG_MASK = 0xffffffffL;
7622 // int xstart = xlen - 1;
7623 // int ystart = ylen - 1;
7624 // long carry = 0;
7625 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7626 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7627 // z[kdx] = (int)product;
7628 // carry = product >>> 32;
7629 // }
7630 // z[xstart] = (int)carry;
7631 //
7632
7633 movl(idx, ylen); // idx = ylen;
7634 movl(kdx, zlen); // kdx = xlen+ylen;
7635 xorq(carry, carry); // carry = 0;
7636
7637 Label L_done;
7638
7639 movl(xstart, xlen);
7640 decrementl(xstart);
7641 jcc(Assembler::negative, L_done);
7642
7643 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7644
7645 Label L_second_loop;
7646 testl(kdx, kdx);
7647 jcc(Assembler::zero, L_second_loop);
7648
7649 Label L_carry;
7650 subl(kdx, 1);
7651 jcc(Assembler::zero, L_carry);
7652
7653 movl(Address(z, kdx, Address::times_4, 0), carry);
7654 shrq(carry, 32);
7655 subl(kdx, 1);
7656
7657 bind(L_carry);
7658 movl(Address(z, kdx, Address::times_4, 0), carry);
7659
7660 // Second and third (nested) loops.
7661 //
7662 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7663 // carry = 0;
7664 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7665 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7666 // (z[k] & LONG_MASK) + carry;
7667 // z[k] = (int)product;
7668 // carry = product >>> 32;
7669 // }
7670 // z[i] = (int)carry;
7671 // }
7672 //
7673 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7674
7675 const Register jdx = tmp1;
7676
7677 bind(L_second_loop);
7678 xorl(carry, carry); // carry = 0;
7679 movl(jdx, ylen); // j = ystart+1
7680
7681 subl(xstart, 1); // i = xstart-1;
7682 jcc(Assembler::negative, L_done);
7683
7684 push (z);
7685
7686 Label L_last_x;
7687 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7688 subl(xstart, 1); // i = xstart-1;
7689 jcc(Assembler::negative, L_last_x);
7690
7691 if (UseBMI2Instructions) {
7692 movq(rdx, Address(x, xstart, Address::times_4, 0));
7693 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7694 } else {
7695 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7696 rorq(x_xstart, 32); // convert big-endian to little-endian
7697 }
7698
7699 Label L_third_loop_prologue;
7700 bind(L_third_loop_prologue);
7701
7702 push (x);
7703 push (xstart);
7704 push (ylen);
7705
7706
7707 if (UseBMI2Instructions) {
7708 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7709 } else { // !UseBMI2Instructions
7710 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7711 }
7712
7713 pop(ylen);
7714 pop(xlen);
7715 pop(x);
7716 pop(z);
7717
7718 movl(tmp3, xlen);
7719 addl(tmp3, 1);
7720 movl(Address(z, tmp3, Address::times_4, 0), carry);
7721 subl(tmp3, 1);
7722 jccb(Assembler::negative, L_done);
7723
7724 shrq(carry, 32);
7725 movl(Address(z, tmp3, Address::times_4, 0), carry);
7726 jmp(L_second_loop);
7727
7728 // Next infrequent code is moved outside loops.
7729 bind(L_last_x);
7730 if (UseBMI2Instructions) {
7731 movl(rdx, Address(x, 0));
7732 } else {
7733 movl(x_xstart, Address(x, 0));
7734 }
7735 jmp(L_third_loop_prologue);
7736
7737 bind(L_done);
7738
7739 pop(zlen);
7740 pop(xlen);
7741
7742 pop(tmp5);
7743 pop(tmp4);
7744 pop(tmp3);
7745 pop(tmp2);
7746 pop(tmp1);
7747 }
7748
7749 //Helper functions for square_to_len()
7750
7751 /**
7752 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7753 * Preserves x and z and modifies rest of the registers.
7754 */
7755
7756 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7757 // Perform square and right shift by 1
7758 // Handle odd xlen case first, then for even xlen do the following
7759 // jlong carry = 0;
7760 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7761 // huge_128 product = x[j:j+1] * x[j:j+1];
7762 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7763 // z[i+2:i+3] = (jlong)(product >>> 1);
7764 // carry = (jlong)product;
7765 // }
7766
7767 xorq(tmp5, tmp5); // carry
7768 xorq(rdxReg, rdxReg);
7769 xorl(tmp1, tmp1); // index for x
7770 xorl(tmp4, tmp4); // index for z
7771
7772 Label L_first_loop, L_first_loop_exit;
7773
7774 testl(xlen, 1);
7775 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7776
7777 // Square and right shift by 1 the odd element using 32 bit multiply
7778 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7779 imulq(raxReg, raxReg);
7780 shrq(raxReg, 1);
7781 adcq(tmp5, 0);
7782 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7783 incrementl(tmp1);
7784 addl(tmp4, 2);
7785
7786 // Square and right shift by 1 the rest using 64 bit multiply
7787 bind(L_first_loop);
7788 cmpptr(tmp1, xlen);
7789 jccb(Assembler::equal, L_first_loop_exit);
7790
7791 // Square
7792 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7793 rorq(raxReg, 32); // convert big-endian to little-endian
7794 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7795
7796 // Right shift by 1 and save carry
7797 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7798 rcrq(rdxReg, 1);
7799 rcrq(raxReg, 1);
7800 adcq(tmp5, 0);
7801
7802 // Store result in z
7803 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7804 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7805
7806 // Update indices for x and z
7807 addl(tmp1, 2);
7808 addl(tmp4, 4);
7809 jmp(L_first_loop);
7810
7811 bind(L_first_loop_exit);
7812 }
7813
7814
7815 /**
7816 * Perform the following multiply add operation using BMI2 instructions
7817 * carry:sum = sum + op1*op2 + carry
7818 * op2 should be in rdx
7819 * op2 is preserved, all other registers are modified
7820 */
7821 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7822 // assert op2 is rdx
7823 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7824 addq(sum, carry);
7825 adcq(tmp2, 0);
7826 addq(sum, op1);
7827 adcq(tmp2, 0);
7828 movq(carry, tmp2);
7829 }
7830
7831 /**
7832 * Perform the following multiply add operation:
7833 * carry:sum = sum + op1*op2 + carry
7834 * Preserves op1, op2 and modifies rest of registers
7835 */
7836 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7837 // rdx:rax = op1 * op2
7838 movq(raxReg, op2);
7839 mulq(op1);
7840
7841 // rdx:rax = sum + carry + rdx:rax
7842 addq(sum, carry);
7843 adcq(rdxReg, 0);
7844 addq(sum, raxReg);
7845 adcq(rdxReg, 0);
7846
7847 // carry:sum = rdx:sum
7848 movq(carry, rdxReg);
7849 }
7850
7851 /**
7852 * Add 64 bit long carry into z[] with carry propogation.
7853 * Preserves z and carry register values and modifies rest of registers.
7854 *
7855 */
7856 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7857 Label L_fourth_loop, L_fourth_loop_exit;
7858
7859 movl(tmp1, 1);
7860 subl(zlen, 2);
7861 addq(Address(z, zlen, Address::times_4, 0), carry);
7862
7863 bind(L_fourth_loop);
7864 jccb(Assembler::carryClear, L_fourth_loop_exit);
7865 subl(zlen, 2);
7866 jccb(Assembler::negative, L_fourth_loop_exit);
7867 addq(Address(z, zlen, Address::times_4, 0), tmp1);
7868 jmp(L_fourth_loop);
7869 bind(L_fourth_loop_exit);
7870 }
7871
7872 /**
7873 * Shift z[] left by 1 bit.
7874 * Preserves x, len, z and zlen registers and modifies rest of the registers.
7875 *
7876 */
7877 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7878
7879 Label L_fifth_loop, L_fifth_loop_exit;
7880
7881 // Fifth loop
7882 // Perform primitiveLeftShift(z, zlen, 1)
7883
7884 const Register prev_carry = tmp1;
7885 const Register new_carry = tmp4;
7886 const Register value = tmp2;
7887 const Register zidx = tmp3;
7888
7889 // int zidx, carry;
7890 // long value;
7891 // carry = 0;
7892 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7893 // (carry:value) = (z[i] << 1) | carry ;
7894 // z[i] = value;
7895 // }
7896
7897 movl(zidx, zlen);
7898 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7899
7900 bind(L_fifth_loop);
7901 decl(zidx); // Use decl to preserve carry flag
7902 decl(zidx);
7903 jccb(Assembler::negative, L_fifth_loop_exit);
7904
7905 if (UseBMI2Instructions) {
7906 movq(value, Address(z, zidx, Address::times_4, 0));
7907 rclq(value, 1);
7908 rorxq(value, value, 32);
7909 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7910 }
7911 else {
7912 // clear new_carry
7913 xorl(new_carry, new_carry);
7914
7915 // Shift z[i] by 1, or in previous carry and save new carry
7916 movq(value, Address(z, zidx, Address::times_4, 0));
7917 shlq(value, 1);
7918 adcl(new_carry, 0);
7919
7920 orq(value, prev_carry);
7921 rorq(value, 0x20);
7922 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7923
7924 // Set previous carry = new carry
7925 movl(prev_carry, new_carry);
7926 }
7927 jmp(L_fifth_loop);
7928
7929 bind(L_fifth_loop_exit);
7930 }
7931
7932
7933 /**
7934 * Code for BigInteger::squareToLen() intrinsic
7935 *
7936 * rdi: x
7937 * rsi: len
7938 * r8: z
7939 * rcx: zlen
7940 * r12: tmp1
7941 * r13: tmp2
7942 * r14: tmp3
7943 * r15: tmp4
7944 * rbx: tmp5
7945 *
7946 */
7947 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7948
7949 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply;
7950 push(tmp1);
7951 push(tmp2);
7952 push(tmp3);
7953 push(tmp4);
7954 push(tmp5);
7955
7956 // First loop
7957 // Store the squares, right shifted one bit (i.e., divided by 2).
7958 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
7959
7960 // Add in off-diagonal sums.
7961 //
7962 // Second, third (nested) and fourth loops.
7963 // zlen +=2;
7964 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
7965 // carry = 0;
7966 // long op2 = x[xidx:xidx+1];
7967 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
7968 // k -= 2;
7969 // long op1 = x[j:j+1];
7970 // long sum = z[k:k+1];
7971 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
7972 // z[k:k+1] = sum;
7973 // }
7974 // add_one_64(z, k, carry, tmp_regs);
7975 // }
7976
7977 const Register carry = tmp5;
7978 const Register sum = tmp3;
7979 const Register op1 = tmp4;
7980 Register op2 = tmp2;
7981
7982 push(zlen);
7983 push(len);
7984 addl(zlen,2);
7985 bind(L_second_loop);
7986 xorq(carry, carry);
7987 subl(zlen, 4);
7988 subl(len, 2);
7989 push(zlen);
7990 push(len);
7991 cmpl(len, 0);
7992 jccb(Assembler::lessEqual, L_second_loop_exit);
7993
7994 // Multiply an array by one 64 bit long.
7995 if (UseBMI2Instructions) {
7996 op2 = rdxReg;
7997 movq(op2, Address(x, len, Address::times_4, 0));
7998 rorxq(op2, op2, 32);
7999 }
8000 else {
8001 movq(op2, Address(x, len, Address::times_4, 0));
8002 rorq(op2, 32);
8003 }
8004
8005 bind(L_third_loop);
8006 decrementl(len);
8007 jccb(Assembler::negative, L_third_loop_exit);
8008 decrementl(len);
8009 jccb(Assembler::negative, L_last_x);
8010
8011 movq(op1, Address(x, len, Address::times_4, 0));
8012 rorq(op1, 32);
8013
8014 bind(L_multiply);
8015 subl(zlen, 2);
8016 movq(sum, Address(z, zlen, Address::times_4, 0));
8017
8018 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8019 if (UseBMI2Instructions) {
8020 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8021 }
8022 else {
8023 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8024 }
8025
8026 movq(Address(z, zlen, Address::times_4, 0), sum);
8027
8028 jmp(L_third_loop);
8029 bind(L_third_loop_exit);
8030
8031 // Fourth loop
8032 // Add 64 bit long carry into z with carry propogation.
8033 // Uses offsetted zlen.
8034 add_one_64(z, zlen, carry, tmp1);
8035
8036 pop(len);
8037 pop(zlen);
8038 jmp(L_second_loop);
8039
8040 // Next infrequent code is moved outside loops.
8041 bind(L_last_x);
8042 movl(op1, Address(x, 0));
8043 jmp(L_multiply);
8044
8045 bind(L_second_loop_exit);
8046 pop(len);
8047 pop(zlen);
8048 pop(len);
8049 pop(zlen);
8050
8051 // Fifth loop
8052 // Shift z left 1 bit.
8053 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8054
8055 // z[zlen-1] |= x[len-1] & 1;
8056 movl(tmp3, Address(x, len, Address::times_4, -4));
8057 andl(tmp3, 1);
8058 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8059
8060 pop(tmp5);
8061 pop(tmp4);
8062 pop(tmp3);
8063 pop(tmp2);
8064 pop(tmp1);
8065 }
8066
8067 /**
8068 * Helper function for mul_add()
8069 * Multiply the in[] by int k and add to out[] starting at offset offs using
8070 * 128 bit by 32 bit multiply and return the carry in tmp5.
8071 * Only quad int aligned length of in[] is operated on in this function.
8072 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8073 * This function preserves out, in and k registers.
8074 * len and offset point to the appropriate index in "in" & "out" correspondingly
8075 * tmp5 has the carry.
8076 * other registers are temporary and are modified.
8077 *
8078 */
8079 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8080 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8081 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8082
8083 Label L_first_loop, L_first_loop_exit;
8084
8085 movl(tmp1, len);
8086 shrl(tmp1, 2);
8087
8088 bind(L_first_loop);
8089 subl(tmp1, 1);
8090 jccb(Assembler::negative, L_first_loop_exit);
8091
8092 subl(len, 4);
8093 subl(offset, 4);
8094
8095 Register op2 = tmp2;
8096 const Register sum = tmp3;
8097 const Register op1 = tmp4;
8098 const Register carry = tmp5;
8099
8100 if (UseBMI2Instructions) {
8101 op2 = rdxReg;
8102 }
8103
8104 movq(op1, Address(in, len, Address::times_4, 8));
8105 rorq(op1, 32);
8106 movq(sum, Address(out, offset, Address::times_4, 8));
8107 rorq(sum, 32);
8108 if (UseBMI2Instructions) {
8109 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8110 }
8111 else {
8112 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8113 }
8114 // Store back in big endian from little endian
8115 rorq(sum, 0x20);
8116 movq(Address(out, offset, Address::times_4, 8), sum);
8117
8118 movq(op1, Address(in, len, Address::times_4, 0));
8119 rorq(op1, 32);
8120 movq(sum, Address(out, offset, Address::times_4, 0));
8121 rorq(sum, 32);
8122 if (UseBMI2Instructions) {
8123 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8124 }
8125 else {
8126 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8127 }
8128 // Store back in big endian from little endian
8129 rorq(sum, 0x20);
8130 movq(Address(out, offset, Address::times_4, 0), sum);
8131
8132 jmp(L_first_loop);
8133 bind(L_first_loop_exit);
8134 }
8135
8136 /**
8137 * Code for BigInteger::mulAdd() intrinsic
8138 *
8139 * rdi: out
8140 * rsi: in
8141 * r11: offs (out.length - offset)
8142 * rcx: len
8143 * r8: k
8144 * r12: tmp1
8145 * r13: tmp2
8146 * r14: tmp3
8147 * r15: tmp4
8148 * rbx: tmp5
8149 * Multiply the in[] by word k and add to out[], return the carry in rax
8150 */
8151 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8152 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8153 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8154
8155 Label L_carry, L_last_in, L_done;
8156
8157 // carry = 0;
8158 // for (int j=len-1; j >= 0; j--) {
8159 // long product = (in[j] & LONG_MASK) * kLong +
8160 // (out[offs] & LONG_MASK) + carry;
8161 // out[offs--] = (int)product;
8162 // carry = product >>> 32;
8163 // }
8164 //
8165 push(tmp1);
8166 push(tmp2);
8167 push(tmp3);
8168 push(tmp4);
8169 push(tmp5);
8170
8171 Register op2 = tmp2;
8172 const Register sum = tmp3;
8173 const Register op1 = tmp4;
8174 const Register carry = tmp5;
8175
8176 if (UseBMI2Instructions) {
8177 op2 = rdxReg;
8178 movl(op2, k);
8179 }
8180 else {
8181 movl(op2, k);
8182 }
8183
8184 xorq(carry, carry);
8185
8186 //First loop
8187
8188 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8189 //The carry is in tmp5
8190 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8191
8192 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8193 decrementl(len);
8194 jccb(Assembler::negative, L_carry);
8195 decrementl(len);
8196 jccb(Assembler::negative, L_last_in);
8197
8198 movq(op1, Address(in, len, Address::times_4, 0));
8199 rorq(op1, 32);
8200
8201 subl(offs, 2);
8202 movq(sum, Address(out, offs, Address::times_4, 0));
8203 rorq(sum, 32);
8204
8205 if (UseBMI2Instructions) {
8206 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8207 }
8208 else {
8209 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8210 }
8211
8212 // Store back in big endian from little endian
8213 rorq(sum, 0x20);
8214 movq(Address(out, offs, Address::times_4, 0), sum);
8215
8216 testl(len, len);
8217 jccb(Assembler::zero, L_carry);
8218
8219 //Multiply the last in[] entry, if any
8220 bind(L_last_in);
8221 movl(op1, Address(in, 0));
8222 movl(sum, Address(out, offs, Address::times_4, -4));
8223
8224 movl(raxReg, k);
8225 mull(op1); //tmp4 * eax -> edx:eax
8226 addl(sum, carry);
8227 adcl(rdxReg, 0);
8228 addl(sum, raxReg);
8229 adcl(rdxReg, 0);
8230 movl(carry, rdxReg);
8231
8232 movl(Address(out, offs, Address::times_4, -4), sum);
8233
8234 bind(L_carry);
8235 //return tmp5/carry as carry in rax
8236 movl(rax, carry);
8237
8238 bind(L_done);
8239 pop(tmp5);
8240 pop(tmp4);
8241 pop(tmp3);
8242 pop(tmp2);
8243 pop(tmp1);
8244 }
8245 #endif
8246
8247 /**
8248 * Emits code to update CRC-32 with a byte value according to constants in table
8249 *
8250 * @param [in,out]crc Register containing the crc.
8251 * @param [in]val Register containing the byte to fold into the CRC.
8252 * @param [in]table Register containing the table of crc constants.
8253 *
8254 * uint32_t crc;
8255 * val = crc_table[(val ^ crc) & 0xFF];
8256 * crc = val ^ (crc >> 8);
8257 *
8258 */
8259 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8260 xorl(val, crc);
8261 andl(val, 0xFF);
8262 shrl(crc, 8); // unsigned shift
8263 xorl(crc, Address(table, val, Address::times_4, 0));
8264 }
8265
8266 /**
8267 * Fold 128-bit data chunk
8268 */
8269 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8270 if (UseAVX > 0) {
8271 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8272 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8273 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8274 pxor(xcrc, xtmp);
8275 } else {
8276 movdqa(xtmp, xcrc);
8277 pclmulhdq(xtmp, xK); // [123:64]
8278 pclmulldq(xcrc, xK); // [63:0]
8279 pxor(xcrc, xtmp);
8280 movdqu(xtmp, Address(buf, offset));
8281 pxor(xcrc, xtmp);
8282 }
8283 }
8284
8285 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8286 if (UseAVX > 0) {
8287 vpclmulhdq(xtmp, xK, xcrc);
8288 vpclmulldq(xcrc, xK, xcrc);
8289 pxor(xcrc, xbuf);
8290 pxor(xcrc, xtmp);
8291 } else {
8292 movdqa(xtmp, xcrc);
8293 pclmulhdq(xtmp, xK);
8294 pclmulldq(xcrc, xK);
8295 pxor(xcrc, xbuf);
8296 pxor(xcrc, xtmp);
8297 }
8298 }
8299
8300 /**
8301 * 8-bit folds to compute 32-bit CRC
8302 *
8303 * uint64_t xcrc;
8304 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8305 */
8306 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8307 movdl(tmp, xcrc);
8308 andl(tmp, 0xFF);
8309 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8310 psrldq(xcrc, 1); // unsigned shift one byte
8311 pxor(xcrc, xtmp);
8312 }
8313
8314 /**
8315 * uint32_t crc;
8316 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8317 */
8318 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8319 movl(tmp, crc);
8320 andl(tmp, 0xFF);
8321 shrl(crc, 8);
8322 xorl(crc, Address(table, tmp, Address::times_4, 0));
8323 }
8324
8325 /**
8326 * @param crc register containing existing CRC (32-bit)
8327 * @param buf register pointing to input byte buffer (byte*)
8328 * @param len register containing number of bytes
8329 * @param table register that will contain address of CRC table
8330 * @param tmp scratch register
8331 */
8332 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8333 assert_different_registers(crc, buf, len, table, tmp, rax);
8334
8335 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8336 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8337
8338 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8339 notl(crc); // ~crc
8340 cmpl(len, 16);
8341 jcc(Assembler::less, L_tail);
8342
8343 // Align buffer to 16 bytes
8344 movl(tmp, buf);
8345 andl(tmp, 0xF);
8346 jccb(Assembler::zero, L_aligned);
8347 subl(tmp, 16);
8348 addl(len, tmp);
8349
8350 align(4);
8351 BIND(L_align_loop);
8352 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8353 update_byte_crc32(crc, rax, table);
8354 increment(buf);
8355 incrementl(tmp);
8356 jccb(Assembler::less, L_align_loop);
8357
8358 BIND(L_aligned);
8359 movl(tmp, len); // save
8360 shrl(len, 4);
8361 jcc(Assembler::zero, L_tail_restore);
8362
8363 // Fold crc into first bytes of vector
8364 movdqa(xmm1, Address(buf, 0));
8365 movdl(rax, xmm1);
8366 xorl(crc, rax);
8367 pinsrd(xmm1, crc, 0);
8368 addptr(buf, 16);
8369 subl(len, 4); // len > 0
8370 jcc(Assembler::less, L_fold_tail);
8371
8372 movdqa(xmm2, Address(buf, 0));
8373 movdqa(xmm3, Address(buf, 16));
8374 movdqa(xmm4, Address(buf, 32));
8375 addptr(buf, 48);
8376 subl(len, 3);
8377 jcc(Assembler::lessEqual, L_fold_512b);
8378
8379 // Fold total 512 bits of polynomial on each iteration,
8380 // 128 bits per each of 4 parallel streams.
8381 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
8382
8383 align(32);
8384 BIND(L_fold_512b_loop);
8385 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8386 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8387 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8388 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8389 addptr(buf, 64);
8390 subl(len, 4);
8391 jcc(Assembler::greater, L_fold_512b_loop);
8392
8393 // Fold 512 bits to 128 bits.
8394 BIND(L_fold_512b);
8395 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
8396 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8397 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8398 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8399
8400 // Fold the rest of 128 bits data chunks
8401 BIND(L_fold_tail);
8402 addl(len, 3);
8403 jccb(Assembler::lessEqual, L_fold_128b);
8404 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
8405
8406 BIND(L_fold_tail_loop);
8407 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8408 addptr(buf, 16);
8409 decrementl(len);
8410 jccb(Assembler::greater, L_fold_tail_loop);
8411
8412 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8413 BIND(L_fold_128b);
8414 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
8415 if (UseAVX > 0) {
8416 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8417 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8418 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8419 } else {
8420 movdqa(xmm2, xmm0);
8421 pclmulqdq(xmm2, xmm1, 0x1);
8422 movdqa(xmm3, xmm0);
8423 pand(xmm3, xmm2);
8424 pclmulqdq(xmm0, xmm3, 0x1);
8425 }
8426 psrldq(xmm1, 8);
8427 psrldq(xmm2, 4);
8428 pxor(xmm0, xmm1);
8429 pxor(xmm0, xmm2);
8430
8431 // 8 8-bit folds to compute 32-bit CRC.
8432 for (int j = 0; j < 4; j++) {
8433 fold_8bit_crc32(xmm0, table, xmm1, rax);
8434 }
8435 movdl(crc, xmm0); // mov 32 bits to general register
8436 for (int j = 0; j < 4; j++) {
8437 fold_8bit_crc32(crc, table, rax);
8438 }
8439
8440 BIND(L_tail_restore);
8441 movl(len, tmp); // restore
8442 BIND(L_tail);
8443 andl(len, 0xf);
8444 jccb(Assembler::zero, L_exit);
8445
8446 // Fold the rest of bytes
8447 align(4);
8448 BIND(L_tail_loop);
8449 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8450 update_byte_crc32(crc, rax, table);
8451 increment(buf);
8452 decrementl(len);
8453 jccb(Assembler::greater, L_tail_loop);
8454
8455 BIND(L_exit);
8456 notl(crc); // ~c
8457 }
8458
8459 #undef BIND
8460 #undef BLOCK_COMMENT
8461
8462
8463 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
8464 switch (cond) {
8465 // Note some conditions are synonyms for others
8466 case Assembler::zero: return Assembler::notZero;
8467 case Assembler::notZero: return Assembler::zero;
8468 case Assembler::less: return Assembler::greaterEqual;
8469 case Assembler::lessEqual: return Assembler::greater;
8470 case Assembler::greater: return Assembler::lessEqual;
8471 case Assembler::greaterEqual: return Assembler::less;
8472 case Assembler::below: return Assembler::aboveEqual;
8473 case Assembler::belowEqual: return Assembler::above;
8474 case Assembler::above: return Assembler::belowEqual;
8475 case Assembler::aboveEqual: return Assembler::below;
8476 case Assembler::overflow: return Assembler::noOverflow;
8477 case Assembler::noOverflow: return Assembler::overflow;
8478 case Assembler::negative: return Assembler::positive;
8479 case Assembler::positive: return Assembler::negative;
8480 case Assembler::parity: return Assembler::noParity;
8481 case Assembler::noParity: return Assembler::parity;
8482 }
8483 ShouldNotReachHere(); return Assembler::overflow;
8484 }
8485
8486 SkipIfEqual::SkipIfEqual(
8487 MacroAssembler* masm, const bool* flag_addr, bool value) {
8488 _masm = masm;
8489 _masm->cmp8(ExternalAddress((address)flag_addr), value);
8490 _masm->jcc(Assembler::equal, _label);
8491 }
8492
8493 SkipIfEqual::~SkipIfEqual() {
8494 _masm->bind(_label);
8495 }