9890
9891 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9892 predicate (UseSSE>=2);
9893 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9894 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9895 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9896 ins_encode %{
9897 __ subptr(rsp, 8);
9898 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9899 __ fld_d(Address(rsp, 0));
9900 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9901 __ fld_d(Address(rsp, 0));
9902 __ fast_pow();
9903 __ fstp_d(Address(rsp, 0));
9904 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9905 __ addptr(rsp, 8);
9906 %}
9907 ins_pipe( pipe_slow );
9908 %}
9909
9910
9911 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9912 predicate (UseSSE<=1);
9913 match(Set dpr1 (ExpD dpr1));
9914 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9915 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
9916 ins_encode %{
9917 __ fast_exp();
9918 %}
9919 ins_pipe( pipe_slow );
9920 %}
9921
9922 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9923 predicate (UseSSE>=2);
9924 match(Set dst (ExpD src));
9925 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9926 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
9927 ins_encode %{
9928 __ subptr(rsp, 8);
9929 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9930 __ fld_d(Address(rsp, 0));
9931 __ fast_exp();
9932 __ fstp_d(Address(rsp, 0));
9933 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9934 __ addptr(rsp, 8);
9935 %}
9936 ins_pipe( pipe_slow );
9937 %}
9938
9939 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
9940 predicate (UseSSE<=1);
9941 // The source Double operand on FPU stack
9942 match(Set dst (Log10D src));
9943 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9944 // fxch ; swap ST(0) with ST(1)
9945 // fyl2x ; compute log_10(2) * log_2(x)
9946 format %{ "FLDLG2 \t\t\t#Log10\n\t"
9947 "FXCH \n\t"
9948 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
9949 %}
9950 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
9951 Opcode(0xD9), Opcode(0xC9), // fxch
9952 Opcode(0xD9), Opcode(0xF1)); // fyl2x
9953
9954 ins_pipe( pipe_slow );
9955 %}
9956
9957 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
9958 predicate (UseSSE>=2);
|
9890
9891 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9892 predicate (UseSSE>=2);
9893 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9894 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9895 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9896 ins_encode %{
9897 __ subptr(rsp, 8);
9898 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9899 __ fld_d(Address(rsp, 0));
9900 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9901 __ fld_d(Address(rsp, 0));
9902 __ fast_pow();
9903 __ fstp_d(Address(rsp, 0));
9904 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9905 __ addptr(rsp, 8);
9906 %}
9907 ins_pipe( pipe_slow );
9908 %}
9909
9910 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
9911 predicate (UseSSE<=1);
9912 // The source Double operand on FPU stack
9913 match(Set dst (Log10D src));
9914 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9915 // fxch ; swap ST(0) with ST(1)
9916 // fyl2x ; compute log_10(2) * log_2(x)
9917 format %{ "FLDLG2 \t\t\t#Log10\n\t"
9918 "FXCH \n\t"
9919 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
9920 %}
9921 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
9922 Opcode(0xD9), Opcode(0xC9), // fxch
9923 Opcode(0xD9), Opcode(0xF1)); // fyl2x
9924
9925 ins_pipe( pipe_slow );
9926 %}
9927
9928 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
9929 predicate (UseSSE>=2);
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