1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP
26 #define CPU_X86_VM_ASSEMBLER_X86_HPP
27
28 #include "asm/register.hpp"
29 #include "vm_version_x86.hpp"
30
31 class BiasedLockingCounters;
32
33 // Contains all the definitions needed for x86 assembly code generation.
34
35 // Calling convention
36 class Argument VALUE_OBJ_CLASS_SPEC {
37 public:
38 enum {
39 #ifdef _LP64
40 #ifdef _WIN64
41 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
42 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
43 #else
44 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
45 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
46 #endif // _WIN64
47 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
48 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
49 #else
50 n_register_parameters = 0 // 0 registers used to pass arguments
51 #endif // _LP64
52 };
53 };
54
55
56 #ifdef _LP64
57 // Symbolically name the register arguments used by the c calling convention.
58 // Windows is different from linux/solaris. So much for standards...
59
60 #ifdef _WIN64
61
62 REGISTER_DECLARATION(Register, c_rarg0, rcx);
63 REGISTER_DECLARATION(Register, c_rarg1, rdx);
64 REGISTER_DECLARATION(Register, c_rarg2, r8);
65 REGISTER_DECLARATION(Register, c_rarg3, r9);
66
67 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
68 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
69 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
70 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
71
72 #else
73
74 REGISTER_DECLARATION(Register, c_rarg0, rdi);
75 REGISTER_DECLARATION(Register, c_rarg1, rsi);
76 REGISTER_DECLARATION(Register, c_rarg2, rdx);
77 REGISTER_DECLARATION(Register, c_rarg3, rcx);
78 REGISTER_DECLARATION(Register, c_rarg4, r8);
79 REGISTER_DECLARATION(Register, c_rarg5, r9);
80
81 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
82 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
83 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
84 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
85 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
86 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
87 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
88 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
89
90 #endif // _WIN64
91
92 // Symbolically name the register arguments used by the Java calling convention.
93 // We have control over the convention for java so we can do what we please.
94 // What pleases us is to offset the java calling convention so that when
95 // we call a suitable jni method the arguments are lined up and we don't
96 // have to do little shuffling. A suitable jni method is non-static and a
97 // small number of arguments (two fewer args on windows)
98 //
99 // |-------------------------------------------------------|
100 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
101 // |-------------------------------------------------------|
102 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
103 // | rdi rsi rdx rcx r8 r9 | solaris/linux
104 // |-------------------------------------------------------|
105 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
106 // |-------------------------------------------------------|
107
108 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
109 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
110 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
111 // Windows runs out of register args here
112 #ifdef _WIN64
113 REGISTER_DECLARATION(Register, j_rarg3, rdi);
114 REGISTER_DECLARATION(Register, j_rarg4, rsi);
115 #else
116 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
117 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
118 #endif /* _WIN64 */
119 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
120
121 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
122 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
123 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
124 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
125 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
126 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
127 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
128 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
129
130 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
131 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
132
133 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
134 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
135
136 #else
137 // rscratch1 will apear in 32bit code that is dead but of course must compile
138 // Using noreg ensures if the dead code is incorrectly live and executed it
139 // will cause an assertion failure
140 #define rscratch1 noreg
141 #define rscratch2 noreg
142
143 #endif // _LP64
144
145 // JSR 292
146 // On x86, the SP does not have to be saved when invoking method handle intrinsics
147 // or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg.
148 REGISTER_DECLARATION(Register, rbp_mh_SP_save, noreg);
149
150 // Address is an abstraction used to represent a memory location
151 // using any of the amd64 addressing modes with one object.
152 //
153 // Note: A register location is represented via a Register, not
154 // via an address for efficiency & simplicity reasons.
155
156 class ArrayAddress;
157
158 class Address VALUE_OBJ_CLASS_SPEC {
159 public:
160 enum ScaleFactor {
161 no_scale = -1,
162 times_1 = 0,
163 times_2 = 1,
164 times_4 = 2,
165 times_8 = 3,
166 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
167 };
168 static ScaleFactor times(int size) {
169 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
170 if (size == 8) return times_8;
171 if (size == 4) return times_4;
172 if (size == 2) return times_2;
173 return times_1;
174 }
175 static int scale_size(ScaleFactor scale) {
176 assert(scale != no_scale, "");
177 assert(((1 << (int)times_1) == 1 &&
178 (1 << (int)times_2) == 2 &&
179 (1 << (int)times_4) == 4 &&
180 (1 << (int)times_8) == 8), "");
181 return (1 << (int)scale);
182 }
183
184 private:
185 Register _base;
186 Register _index;
187 ScaleFactor _scale;
188 int _disp;
189 RelocationHolder _rspec;
190
191 // Easily misused constructors make them private
192 // %%% can we make these go away?
193 NOT_LP64(Address(address loc, RelocationHolder spec);)
194 Address(int disp, address loc, relocInfo::relocType rtype);
195 Address(int disp, address loc, RelocationHolder spec);
196
197 public:
198
199 int disp() { return _disp; }
200 // creation
201 Address()
202 : _base(noreg),
203 _index(noreg),
204 _scale(no_scale),
205 _disp(0) {
206 }
207
208 // No default displacement otherwise Register can be implicitly
209 // converted to 0(Register) which is quite a different animal.
210
211 Address(Register base, int disp)
212 : _base(base),
213 _index(noreg),
214 _scale(no_scale),
215 _disp(disp) {
216 }
217
218 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
219 : _base (base),
220 _index(index),
221 _scale(scale),
222 _disp (disp) {
223 assert(!index->is_valid() == (scale == Address::no_scale),
224 "inconsistent address");
225 }
226
227 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
228 : _base (base),
229 _index(index.register_or_noreg()),
230 _scale(scale),
231 _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
232 if (!index.is_register()) scale = Address::no_scale;
233 assert(!_index->is_valid() == (scale == Address::no_scale),
234 "inconsistent address");
235 }
236
237 Address plus_disp(int disp) const {
238 Address a = (*this);
239 a._disp += disp;
240 return a;
241 }
242 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
243 Address a = (*this);
244 a._disp += disp.constant_or_zero() * scale_size(scale);
245 if (disp.is_register()) {
246 assert(!a.index()->is_valid(), "competing indexes");
247 a._index = disp.as_register();
248 a._scale = scale;
249 }
250 return a;
251 }
252 bool is_same_address(Address a) const {
253 // disregard _rspec
254 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
255 }
256
257 // The following two overloads are used in connection with the
258 // ByteSize type (see sizes.hpp). They simplify the use of
259 // ByteSize'd arguments in assembly code. Note that their equivalent
260 // for the optimized build are the member functions with int disp
261 // argument since ByteSize is mapped to an int type in that case.
262 //
263 // Note: DO NOT introduce similar overloaded functions for WordSize
264 // arguments as in the optimized mode, both ByteSize and WordSize
265 // are mapped to the same type and thus the compiler cannot make a
266 // distinction anymore (=> compiler errors).
267
268 #ifdef ASSERT
269 Address(Register base, ByteSize disp)
270 : _base(base),
271 _index(noreg),
272 _scale(no_scale),
273 _disp(in_bytes(disp)) {
274 }
275
276 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
277 : _base(base),
278 _index(index),
279 _scale(scale),
280 _disp(in_bytes(disp)) {
281 assert(!index->is_valid() == (scale == Address::no_scale),
282 "inconsistent address");
283 }
284
285 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
286 : _base (base),
287 _index(index.register_or_noreg()),
288 _scale(scale),
289 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
290 if (!index.is_register()) scale = Address::no_scale;
291 assert(!_index->is_valid() == (scale == Address::no_scale),
292 "inconsistent address");
293 }
294
295 #endif // ASSERT
296
297 // accessors
298 bool uses(Register reg) const { return _base == reg || _index == reg; }
299 Register base() const { return _base; }
300 Register index() const { return _index; }
301 ScaleFactor scale() const { return _scale; }
302 int disp() const { return _disp; }
303
304 // Convert the raw encoding form into the form expected by the constructor for
305 // Address. An index of 4 (rsp) corresponds to having no index, so convert
306 // that to noreg for the Address constructor.
307 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
308
309 static Address make_array(ArrayAddress);
310
311 private:
312 bool base_needs_rex() const {
313 return _base != noreg && _base->encoding() >= 8;
314 }
315
316 bool index_needs_rex() const {
317 return _index != noreg &&_index->encoding() >= 8;
318 }
319
320 relocInfo::relocType reloc() const { return _rspec.type(); }
321
322 friend class Assembler;
323 friend class MacroAssembler;
324 friend class LIR_Assembler; // base/index/scale/disp
325 };
326
327 //
328 // AddressLiteral has been split out from Address because operands of this type
329 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
330 // the few instructions that need to deal with address literals are unique and the
331 // MacroAssembler does not have to implement every instruction in the Assembler
332 // in order to search for address literals that may need special handling depending
333 // on the instruction and the platform. As small step on the way to merging i486/amd64
334 // directories.
335 //
336 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
337 friend class ArrayAddress;
338 RelocationHolder _rspec;
339 // Typically we use AddressLiterals we want to use their rval
340 // However in some situations we want the lval (effect address) of the item.
341 // We provide a special factory for making those lvals.
342 bool _is_lval;
343
344 // If the target is far we'll need to load the ea of this to
345 // a register to reach it. Otherwise if near we can do rip
346 // relative addressing.
347
348 address _target;
349
350 protected:
351 // creation
352 AddressLiteral()
353 : _is_lval(false),
354 _target(NULL)
355 {}
356
357 public:
358
359
360 AddressLiteral(address target, relocInfo::relocType rtype);
361
362 AddressLiteral(address target, RelocationHolder const& rspec)
363 : _rspec(rspec),
364 _is_lval(false),
365 _target(target)
366 {}
367
368 AddressLiteral addr() {
369 AddressLiteral ret = *this;
370 ret._is_lval = true;
371 return ret;
372 }
373
374
375 private:
376
377 address target() { return _target; }
378 bool is_lval() { return _is_lval; }
379
380 relocInfo::relocType reloc() const { return _rspec.type(); }
381 const RelocationHolder& rspec() const { return _rspec; }
382
383 friend class Assembler;
384 friend class MacroAssembler;
385 friend class Address;
386 friend class LIR_Assembler;
387 };
388
389 // Convience classes
390 class RuntimeAddress: public AddressLiteral {
391
392 public:
393
394 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
395
396 };
397
398 class ExternalAddress: public AddressLiteral {
399 private:
400 static relocInfo::relocType reloc_for_target(address target) {
401 // Sometimes ExternalAddress is used for values which aren't
402 // exactly addresses, like the card table base.
403 // external_word_type can't be used for values in the first page
404 // so just skip the reloc in that case.
405 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
406 }
407
408 public:
409
410 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
411
412 };
413
414 class InternalAddress: public AddressLiteral {
415
416 public:
417
418 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
419
420 };
421
422 // x86 can do array addressing as a single operation since disp can be an absolute
423 // address amd64 can't. We create a class that expresses the concept but does extra
424 // magic on amd64 to get the final result
425
426 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
427 private:
428
429 AddressLiteral _base;
430 Address _index;
431
432 public:
433
434 ArrayAddress() {};
435 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
436 AddressLiteral base() { return _base; }
437 Address index() { return _index; }
438
439 };
440
441 // 64-bit refect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes
442 // See fxsave and xsave(EVEX enabled) documentation for layout
443 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY(2688 / wordSize);
444
445 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
446 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
447 // is what you get. The Assembler is generating code into a CodeBuffer.
448
449 class Assembler : public AbstractAssembler {
450 friend class AbstractAssembler; // for the non-virtual hack
451 friend class LIR_Assembler; // as_Address()
452 friend class StubGenerator;
453
454 public:
455 enum Condition { // The x86 condition codes used for conditional jumps/moves.
456 zero = 0x4,
457 notZero = 0x5,
458 equal = 0x4,
459 notEqual = 0x5,
460 less = 0xc,
461 lessEqual = 0xe,
462 greater = 0xf,
463 greaterEqual = 0xd,
464 below = 0x2,
465 belowEqual = 0x6,
466 above = 0x7,
467 aboveEqual = 0x3,
468 overflow = 0x0,
469 noOverflow = 0x1,
470 carrySet = 0x2,
471 carryClear = 0x3,
472 negative = 0x8,
473 positive = 0x9,
474 parity = 0xa,
475 noParity = 0xb
476 };
477
478 enum Prefix {
479 // segment overrides
480 CS_segment = 0x2e,
481 SS_segment = 0x36,
482 DS_segment = 0x3e,
483 ES_segment = 0x26,
484 FS_segment = 0x64,
485 GS_segment = 0x65,
486
487 REX = 0x40,
488
489 REX_B = 0x41,
490 REX_X = 0x42,
491 REX_XB = 0x43,
492 REX_R = 0x44,
493 REX_RB = 0x45,
494 REX_RX = 0x46,
495 REX_RXB = 0x47,
496
497 REX_W = 0x48,
498
499 REX_WB = 0x49,
500 REX_WX = 0x4A,
501 REX_WXB = 0x4B,
502 REX_WR = 0x4C,
503 REX_WRB = 0x4D,
504 REX_WRX = 0x4E,
505 REX_WRXB = 0x4F,
506
507 VEX_3bytes = 0xC4,
508 VEX_2bytes = 0xC5,
509 EVEX_4bytes = 0x62
510 };
511
512 enum VexPrefix {
513 VEX_B = 0x20,
514 VEX_X = 0x40,
515 VEX_R = 0x80,
516 VEX_W = 0x80
517 };
518
519 enum ExexPrefix {
520 EVEX_F = 0x04,
521 EVEX_V = 0x08,
522 EVEX_Rb = 0x10,
523 EVEX_X = 0x40,
524 EVEX_Z = 0x80
525 };
526
527 enum VexSimdPrefix {
528 VEX_SIMD_NONE = 0x0,
529 VEX_SIMD_66 = 0x1,
530 VEX_SIMD_F3 = 0x2,
531 VEX_SIMD_F2 = 0x3
532 };
533
534 enum VexOpcode {
535 VEX_OPCODE_NONE = 0x0,
536 VEX_OPCODE_0F = 0x1,
537 VEX_OPCODE_0F_38 = 0x2,
538 VEX_OPCODE_0F_3A = 0x3
539 };
540
541 enum AvxVectorLen {
542 AVX_128bit = 0x0,
543 AVX_256bit = 0x1,
544 AVX_512bit = 0x2,
545 AVX_NoVec = 0x4
546 };
547
548 enum EvexTupleType {
549 EVEX_FV = 0,
550 EVEX_HV = 4,
551 EVEX_FVM = 6,
552 EVEX_T1S = 7,
553 EVEX_T1F = 11,
554 EVEX_T2 = 13,
555 EVEX_T4 = 15,
556 EVEX_T8 = 17,
557 EVEX_HVM = 18,
558 EVEX_QVM = 19,
559 EVEX_OVM = 20,
560 EVEX_M128 = 21,
561 EVEX_DUP = 22,
562 EVEX_ETUP = 23
563 };
564
565 enum EvexInputSizeInBits {
566 EVEX_8bit = 0,
567 EVEX_16bit = 1,
568 EVEX_32bit = 2,
569 EVEX_64bit = 3
570 };
571
572 enum WhichOperand {
573 // input to locate_operand, and format code for relocations
574 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
575 disp32_operand = 1, // embedded 32-bit displacement or address
576 call32_operand = 2, // embedded 32-bit self-relative displacement
577 #ifndef _LP64
578 _WhichOperand_limit = 3
579 #else
580 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
581 _WhichOperand_limit = 4
582 #endif
583 };
584
585
586
587 // NOTE: The general philopsophy of the declarations here is that 64bit versions
588 // of instructions are freely declared without the need for wrapping them an ifdef.
589 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
590 // In the .cpp file the implementations are wrapped so that they are dropped out
591 // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL
592 // to the size it was prior to merging up the 32bit and 64bit assemblers.
593 //
594 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
595 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
596
597 private:
598
599 int _evex_encoding;
600 int _input_size_in_bits;
601 int _avx_vector_len;
602 int _tuple_type;
603 bool _is_evex_instruction;
604 bool _legacy_mode_bw;
605 bool _legacy_mode_dq;
606 bool _legacy_mode_vl;
607 bool _legacy_mode_vlbw;
608 bool _instruction_uses_vl;
609
610 // 64bit prefixes
611 int prefix_and_encode(int reg_enc, bool byteinst = false);
612 int prefixq_and_encode(int reg_enc);
613
614 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
615 int prefixq_and_encode(int dst_enc, int src_enc);
616
617 void prefix(Register reg);
618 void prefix(Address adr);
619 void prefixq(Address adr);
620
621 void prefix(Address adr, Register reg, bool byteinst = false);
622 void prefix(Address adr, XMMRegister reg);
623 void prefixq(Address adr, Register reg);
624 void prefixq(Address adr, XMMRegister reg);
625
626 void prefetch_prefix(Address src);
627
628 void rex_prefix(Address adr, XMMRegister xreg,
629 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
630 int rex_prefix_and_encode(int dst_enc, int src_enc,
631 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
632
633 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w,
634 int nds_enc, VexSimdPrefix pre, VexOpcode opc,
635 int vector_len);
636
637 void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, bool evex_r, bool evex_v,
638 int nds_enc, VexSimdPrefix pre, VexOpcode opc,
639 bool is_extended_context, bool is_merge_context,
640 int vector_len, bool no_mask_reg );
641
642 void vex_prefix(Address adr, int nds_enc, int xreg_enc,
643 VexSimdPrefix pre, VexOpcode opc,
644 bool vex_w, int vector_len,
645 bool legacy_mode = false, bool no_mask_reg = false);
646
647 void vex_prefix(XMMRegister dst, XMMRegister nds, Address src,
648 VexSimdPrefix pre, int vector_len = AVX_128bit,
649 bool no_mask_reg = false, bool legacy_mode = false) {
650 int dst_enc = dst->encoding();
651 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
652 vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector_len, legacy_mode, no_mask_reg);
653 }
654
655 void vex_prefix_q(XMMRegister dst, XMMRegister nds, Address src,
656 VexSimdPrefix pre, int vector_len = AVX_128bit,
657 bool no_mask_reg = false) {
658 int dst_enc = dst->encoding();
659 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
660 vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, true, vector_len, false, no_mask_reg);
661 }
662
663 void vex_prefix_0F38(Register dst, Register nds, Address src, bool no_mask_reg = false) {
664 bool vex_w = false;
665 int vector_len = AVX_128bit;
666 vex_prefix(src, nds->encoding(), dst->encoding(),
667 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w,
668 vector_len, no_mask_reg);
669 }
670
671 void vex_prefix_0F38_legacy(Register dst, Register nds, Address src, bool no_mask_reg = false) {
672 bool vex_w = false;
673 int vector_len = AVX_128bit;
674 vex_prefix(src, nds->encoding(), dst->encoding(),
675 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w,
676 vector_len, true, no_mask_reg);
677 }
678
679 void vex_prefix_0F38_q(Register dst, Register nds, Address src, bool no_mask_reg = false) {
680 bool vex_w = true;
681 int vector_len = AVX_128bit;
682 vex_prefix(src, nds->encoding(), dst->encoding(),
683 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w,
684 vector_len, no_mask_reg);
685 }
686
687 void vex_prefix_0F38_q_legacy(Register dst, Register nds, Address src, bool no_mask_reg = false) {
688 bool vex_w = true;
689 int vector_len = AVX_128bit;
690 vex_prefix(src, nds->encoding(), dst->encoding(),
691 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w,
692 vector_len, true, no_mask_reg);
693 }
694
695 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
696 VexSimdPrefix pre, VexOpcode opc,
697 bool vex_w, int vector_len,
698 bool legacy_mode, bool no_mask_reg);
699
700 int vex_prefix_0F38_and_encode(Register dst, Register nds, Register src, bool no_mask_reg = false) {
701 bool vex_w = false;
702 int vector_len = AVX_128bit;
703 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
704 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector_len,
705 false, no_mask_reg);
706 }
707
708 int vex_prefix_0F38_and_encode_legacy(Register dst, Register nds, Register src, bool no_mask_reg = false) {
709 bool vex_w = false;
710 int vector_len = AVX_128bit;
711 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
712 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector_len,
713 true, no_mask_reg);
714 }
715
716 int vex_prefix_0F38_and_encode_q(Register dst, Register nds, Register src, bool no_mask_reg = false) {
717 bool vex_w = true;
718 int vector_len = AVX_128bit;
719 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
720 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector_len,
721 false, no_mask_reg);
722 }
723
724 int vex_prefix_0F38_and_encode_q_legacy(Register dst, Register nds, Register src, bool no_mask_reg = false) {
725 bool vex_w = true;
726 int vector_len = AVX_128bit;
727 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
728 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector_len,
729 true, no_mask_reg);
730 }
731
732 int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
733 VexSimdPrefix pre, int vector_len = AVX_128bit,
734 VexOpcode opc = VEX_OPCODE_0F, bool legacy_mode = false,
735 bool no_mask_reg = false) {
736 int src_enc = src->encoding();
737 int dst_enc = dst->encoding();
738 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
739 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, false, vector_len, legacy_mode, no_mask_reg);
740 }
741
742 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr,
743 VexSimdPrefix pre, bool no_mask_reg, VexOpcode opc = VEX_OPCODE_0F,
744 bool rex_w = false, int vector_len = AVX_128bit, bool legacy_mode = false);
745
746 void simd_prefix(XMMRegister dst, Address src, VexSimdPrefix pre,
747 bool no_mask_reg, VexOpcode opc = VEX_OPCODE_0F) {
748 simd_prefix(dst, xnoreg, src, pre, no_mask_reg, opc);
749 }
750
751 void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg) {
752 simd_prefix(src, dst, pre, no_mask_reg);
753 }
754 void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src,
755 VexSimdPrefix pre, bool no_mask_reg = false) {
756 bool rex_w = true;
757 simd_prefix(dst, nds, src, pre, no_mask_reg, VEX_OPCODE_0F, rex_w);
758 }
759
760 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
761 VexSimdPrefix pre, bool no_mask_reg,
762 VexOpcode opc = VEX_OPCODE_0F,
763 bool rex_w = false, int vector_len = AVX_128bit,
764 bool legacy_mode = false);
765
766 int kreg_prefix_and_encode(KRegister dst, KRegister nds, KRegister src,
767 VexSimdPrefix pre, bool no_mask_reg,
768 VexOpcode opc = VEX_OPCODE_0F,
769 bool rex_w = false, int vector_len = AVX_128bit);
770
771 int kreg_prefix_and_encode(KRegister dst, KRegister nds, Register src,
772 VexSimdPrefix pre, bool no_mask_reg,
773 VexOpcode opc = VEX_OPCODE_0F,
774 bool rex_w = false, int vector_len = AVX_128bit);
775
776 // Move/convert 32-bit integer value.
777 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src,
778 VexSimdPrefix pre, bool no_mask_reg) {
779 // It is OK to cast from Register to XMMRegister to pass argument here
780 // since only encoding is used in simd_prefix_and_encode() and number of
781 // Gen and Xmm registers are the same.
782 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, no_mask_reg, VEX_OPCODE_0F);
783 }
784 int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre, bool no_mask_reg) {
785 return simd_prefix_and_encode(dst, xnoreg, src, pre, no_mask_reg);
786 }
787 int simd_prefix_and_encode(Register dst, XMMRegister src,
788 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
789 bool no_mask_reg = false) {
790 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, no_mask_reg, opc);
791 }
792
793 // Move/convert 64-bit integer value.
794 int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src,
795 VexSimdPrefix pre, bool no_mask_reg = false) {
796 bool rex_w = true;
797 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, no_mask_reg, VEX_OPCODE_0F, rex_w);
798 }
799 int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre, bool no_mask_reg) {
800 return simd_prefix_and_encode_q(dst, xnoreg, src, pre, no_mask_reg);
801 }
802 int simd_prefix_and_encode_q(Register dst, XMMRegister src,
803 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
804 bool no_mask_reg = false) {
805 bool rex_w = true;
806 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, no_mask_reg, opc, rex_w);
807 }
808
809 // Helper functions for groups of instructions
810 void emit_arith_b(int op1, int op2, Register dst, int imm8);
811
812 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
813 // Force generation of a 4 byte immediate value even if it fits into 8bit
814 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
815 void emit_arith(int op1, int op2, Register dst, Register src);
816
817 void emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg = false, bool legacy_mode = false);
818 void emit_simd_arith_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg = false);
819 void emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg = false, bool legacy_mode = false);
820 void emit_simd_arith_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg = false);
821 void emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg = false);
822 void emit_simd_arith_nonds_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg = false);
823 void emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg = false, bool legacy_mode = false);
824 void emit_simd_arith_nonds_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg = false);
825 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
826 Address src, VexSimdPrefix pre, int vector_len,
827 bool no_mask_reg = false, bool legacy_mode = false);
828 void emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds,
829 Address src, VexSimdPrefix pre, int vector_len,
830 bool no_mask_reg = false);
831 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
832 XMMRegister src, VexSimdPrefix pre, int vector_len,
833 bool no_mask_reg = false, bool legacy_mode = false);
834 void emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds,
835 XMMRegister src, VexSimdPrefix pre, int vector_len,
836 bool no_mask_reg = false);
837
838 bool emit_compressed_disp_byte(int &disp);
839
840 void emit_operand(Register reg,
841 Register base, Register index, Address::ScaleFactor scale,
842 int disp,
843 RelocationHolder const& rspec,
844 int rip_relative_correction = 0);
845
846 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
847
848 // operands that only take the original 32bit registers
849 void emit_operand32(Register reg, Address adr);
850
851 void emit_operand(XMMRegister reg,
852 Register base, Register index, Address::ScaleFactor scale,
853 int disp,
854 RelocationHolder const& rspec);
855
856 void emit_operand(XMMRegister reg, Address adr);
857
858 void emit_operand(MMXRegister reg, Address adr);
859
860 // workaround gcc (3.2.1-7) bug
861 void emit_operand(Address adr, MMXRegister reg);
862
863
864 // Immediate-to-memory forms
865 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
866
867 void emit_farith(int b1, int b2, int i);
868
869
870 protected:
871 #ifdef ASSERT
872 void check_relocation(RelocationHolder const& rspec, int format);
873 #endif
874
875 void emit_data(jint data, relocInfo::relocType rtype, int format);
876 void emit_data(jint data, RelocationHolder const& rspec, int format);
877 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
878 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
879
880 bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
881
882 // These are all easily abused and hence protected
883
884 // 32BIT ONLY SECTION
885 #ifndef _LP64
886 // Make these disappear in 64bit mode since they would never be correct
887 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
888 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
889
890 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
891 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
892
893 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
894 #else
895 // 64BIT ONLY SECTION
896 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
897
898 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
899 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
900
901 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
902 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
903 #endif // _LP64
904
905 // These are unique in that we are ensured by the caller that the 32bit
906 // relative in these instructions will always be able to reach the potentially
907 // 64bit address described by entry. Since they can take a 64bit address they
908 // don't have the 32 suffix like the other instructions in this class.
909
910 void call_literal(address entry, RelocationHolder const& rspec);
911 void jmp_literal(address entry, RelocationHolder const& rspec);
912
913 // Avoid using directly section
914 // Instructions in this section are actually usable by anyone without danger
915 // of failure but have performance issues that are addressed my enhanced
916 // instructions which will do the proper thing base on the particular cpu.
917 // We protect them because we don't trust you...
918
919 // Don't use next inc() and dec() methods directly. INC & DEC instructions
920 // could cause a partial flag stall since they don't set CF flag.
921 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
922 // which call inc() & dec() or add() & sub() in accordance with
923 // the product flag UseIncDec value.
924
925 void decl(Register dst);
926 void decl(Address dst);
927 void decq(Register dst);
928 void decq(Address dst);
929
930 void incl(Register dst);
931 void incl(Address dst);
932 void incq(Register dst);
933 void incq(Address dst);
934
935 // New cpus require use of movsd and movss to avoid partial register stall
936 // when loading from memory. But for old Opteron use movlpd instead of movsd.
937 // The selection is done in MacroAssembler::movdbl() and movflt().
938
939 // Move Scalar Single-Precision Floating-Point Values
940 void movss(XMMRegister dst, Address src);
941 void movss(XMMRegister dst, XMMRegister src);
942 void movss(Address dst, XMMRegister src);
943
944 // Move Scalar Double-Precision Floating-Point Values
945 void movsd(XMMRegister dst, Address src);
946 void movsd(XMMRegister dst, XMMRegister src);
947 void movsd(Address dst, XMMRegister src);
948 void movlpd(XMMRegister dst, Address src);
949
950 // New cpus require use of movaps and movapd to avoid partial register stall
951 // when moving between registers.
952 void movaps(XMMRegister dst, XMMRegister src);
953 void movapd(XMMRegister dst, XMMRegister src);
954
955 // End avoid using directly
956
957
958 // Instruction prefixes
959 void prefix(Prefix p);
960
961 public:
962
963 // Creation
964 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
965 init_attributes();
966 }
967
968 // Decoding
969 static address locate_operand(address inst, WhichOperand which);
970 static address locate_next_instruction(address inst);
971
972 // Utilities
973 static bool is_polling_page_far() NOT_LP64({ return false;});
974 static bool query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
975 int cur_tuple_type, int in_size_in_bits, int cur_encoding);
976
977 // Generic instructions
978 // Does 32bit or 64bit as needed for the platform. In some sense these
979 // belong in macro assembler but there is no need for both varieties to exist
980
981 void init_attributes(void) {
982 _evex_encoding = 0;
983 _input_size_in_bits = 0;
984 _avx_vector_len = AVX_NoVec;
985 _tuple_type = EVEX_ETUP;
986 _is_evex_instruction = false;
987 _legacy_mode_bw = (VM_Version::supports_avx512bw() == false);
988 _legacy_mode_dq = (VM_Version::supports_avx512dq() == false);
989 _legacy_mode_vl = (VM_Version::supports_avx512vl() == false);
990 _legacy_mode_vlbw = (VM_Version::supports_avx512vlbw() == false);
991 _instruction_uses_vl = false;
992 }
993
994 void lea(Register dst, Address src);
995
996 void mov(Register dst, Register src);
997
998 void pusha();
999 void popa();
1000
1001 void pushf();
1002 void popf();
1003
1004 void push(int32_t imm32);
1005
1006 void push(Register src);
1007
1008 void pop(Register dst);
1009
1010 // These are dummies to prevent surprise implicit conversions to Register
1011 void push(void* v);
1012 void pop(void* v);
1013
1014 // These do register sized moves/scans
1015 void rep_mov();
1016 void rep_stos();
1017 void rep_stosb();
1018 void repne_scan();
1019 #ifdef _LP64
1020 void repne_scanl();
1021 #endif
1022
1023 // Vanilla instructions in lexical order
1024
1025 void adcl(Address dst, int32_t imm32);
1026 void adcl(Address dst, Register src);
1027 void adcl(Register dst, int32_t imm32);
1028 void adcl(Register dst, Address src);
1029 void adcl(Register dst, Register src);
1030
1031 void adcq(Register dst, int32_t imm32);
1032 void adcq(Register dst, Address src);
1033 void adcq(Register dst, Register src);
1034
1035 void addl(Address dst, int32_t imm32);
1036 void addl(Address dst, Register src);
1037 void addl(Register dst, int32_t imm32);
1038 void addl(Register dst, Address src);
1039 void addl(Register dst, Register src);
1040
1041 void addq(Address dst, int32_t imm32);
1042 void addq(Address dst, Register src);
1043 void addq(Register dst, int32_t imm32);
1044 void addq(Register dst, Address src);
1045 void addq(Register dst, Register src);
1046
1047 #ifdef _LP64
1048 //Add Unsigned Integers with Carry Flag
1049 void adcxq(Register dst, Register src);
1050
1051 //Add Unsigned Integers with Overflow Flag
1052 void adoxq(Register dst, Register src);
1053 #endif
1054
1055 void addr_nop_4();
1056 void addr_nop_5();
1057 void addr_nop_7();
1058 void addr_nop_8();
1059
1060 // Add Scalar Double-Precision Floating-Point Values
1061 void addsd(XMMRegister dst, Address src);
1062 void addsd(XMMRegister dst, XMMRegister src);
1063
1064 // Add Scalar Single-Precision Floating-Point Values
1065 void addss(XMMRegister dst, Address src);
1066 void addss(XMMRegister dst, XMMRegister src);
1067
1068 // AES instructions
1069 void aesdec(XMMRegister dst, Address src);
1070 void aesdec(XMMRegister dst, XMMRegister src);
1071 void aesdeclast(XMMRegister dst, Address src);
1072 void aesdeclast(XMMRegister dst, XMMRegister src);
1073 void aesenc(XMMRegister dst, Address src);
1074 void aesenc(XMMRegister dst, XMMRegister src);
1075 void aesenclast(XMMRegister dst, Address src);
1076 void aesenclast(XMMRegister dst, XMMRegister src);
1077
1078
1079 void andl(Address dst, int32_t imm32);
1080 void andl(Register dst, int32_t imm32);
1081 void andl(Register dst, Address src);
1082 void andl(Register dst, Register src);
1083
1084 void andq(Address dst, int32_t imm32);
1085 void andq(Register dst, int32_t imm32);
1086 void andq(Register dst, Address src);
1087 void andq(Register dst, Register src);
1088
1089 // BMI instructions
1090 void andnl(Register dst, Register src1, Register src2);
1091 void andnl(Register dst, Register src1, Address src2);
1092 void andnq(Register dst, Register src1, Register src2);
1093 void andnq(Register dst, Register src1, Address src2);
1094
1095 void blsil(Register dst, Register src);
1096 void blsil(Register dst, Address src);
1097 void blsiq(Register dst, Register src);
1098 void blsiq(Register dst, Address src);
1099
1100 void blsmskl(Register dst, Register src);
1101 void blsmskl(Register dst, Address src);
1102 void blsmskq(Register dst, Register src);
1103 void blsmskq(Register dst, Address src);
1104
1105 void blsrl(Register dst, Register src);
1106 void blsrl(Register dst, Address src);
1107 void blsrq(Register dst, Register src);
1108 void blsrq(Register dst, Address src);
1109
1110 void bsfl(Register dst, Register src);
1111 void bsrl(Register dst, Register src);
1112
1113 #ifdef _LP64
1114 void bsfq(Register dst, Register src);
1115 void bsrq(Register dst, Register src);
1116 #endif
1117
1118 void bswapl(Register reg);
1119
1120 void bswapq(Register reg);
1121
1122 void call(Label& L, relocInfo::relocType rtype);
1123 void call(Register reg); // push pc; pc <- reg
1124 void call(Address adr); // push pc; pc <- adr
1125
1126 void cdql();
1127
1128 void cdqq();
1129
1130 void cld();
1131
1132 void clflush(Address adr);
1133
1134 void cmovl(Condition cc, Register dst, Register src);
1135 void cmovl(Condition cc, Register dst, Address src);
1136
1137 void cmovq(Condition cc, Register dst, Register src);
1138 void cmovq(Condition cc, Register dst, Address src);
1139
1140
1141 void cmpb(Address dst, int imm8);
1142
1143 void cmpl(Address dst, int32_t imm32);
1144
1145 void cmpl(Register dst, int32_t imm32);
1146 void cmpl(Register dst, Register src);
1147 void cmpl(Register dst, Address src);
1148
1149 void cmpq(Address dst, int32_t imm32);
1150 void cmpq(Address dst, Register src);
1151
1152 void cmpq(Register dst, int32_t imm32);
1153 void cmpq(Register dst, Register src);
1154 void cmpq(Register dst, Address src);
1155
1156 // these are dummies used to catch attempting to convert NULL to Register
1157 void cmpl(Register dst, void* junk); // dummy
1158 void cmpq(Register dst, void* junk); // dummy
1159
1160 void cmpw(Address dst, int imm16);
1161
1162 void cmpxchg8 (Address adr);
1163
1164 void cmpxchgb(Register reg, Address adr);
1165 void cmpxchgl(Register reg, Address adr);
1166
1167 void cmpxchgq(Register reg, Address adr);
1168
1169 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1170 void comisd(XMMRegister dst, Address src);
1171 void comisd(XMMRegister dst, XMMRegister src);
1172
1173 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1174 void comiss(XMMRegister dst, Address src);
1175 void comiss(XMMRegister dst, XMMRegister src);
1176
1177 // Identify processor type and features
1178 void cpuid();
1179
1180 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
1181 void cvtsd2ss(XMMRegister dst, XMMRegister src);
1182 void cvtsd2ss(XMMRegister dst, Address src);
1183
1184 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
1185 void cvtsi2sdl(XMMRegister dst, Register src);
1186 void cvtsi2sdl(XMMRegister dst, Address src);
1187 void cvtsi2sdq(XMMRegister dst, Register src);
1188 void cvtsi2sdq(XMMRegister dst, Address src);
1189
1190 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
1191 void cvtsi2ssl(XMMRegister dst, Register src);
1192 void cvtsi2ssl(XMMRegister dst, Address src);
1193 void cvtsi2ssq(XMMRegister dst, Register src);
1194 void cvtsi2ssq(XMMRegister dst, Address src);
1195
1196 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
1197 void cvtdq2pd(XMMRegister dst, XMMRegister src);
1198
1199 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
1200 void cvtdq2ps(XMMRegister dst, XMMRegister src);
1201
1202 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
1203 void cvtss2sd(XMMRegister dst, XMMRegister src);
1204 void cvtss2sd(XMMRegister dst, Address src);
1205
1206 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
1207 void cvttsd2sil(Register dst, Address src);
1208 void cvttsd2sil(Register dst, XMMRegister src);
1209 void cvttsd2siq(Register dst, XMMRegister src);
1210
1211 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
1212 void cvttss2sil(Register dst, XMMRegister src);
1213 void cvttss2siq(Register dst, XMMRegister src);
1214
1215 // Divide Scalar Double-Precision Floating-Point Values
1216 void divsd(XMMRegister dst, Address src);
1217 void divsd(XMMRegister dst, XMMRegister src);
1218
1219 // Divide Scalar Single-Precision Floating-Point Values
1220 void divss(XMMRegister dst, Address src);
1221 void divss(XMMRegister dst, XMMRegister src);
1222
1223 void emms();
1224
1225 void fabs();
1226
1227 void fadd(int i);
1228
1229 void fadd_d(Address src);
1230 void fadd_s(Address src);
1231
1232 // "Alternate" versions of x87 instructions place result down in FPU
1233 // stack instead of on TOS
1234
1235 void fadda(int i); // "alternate" fadd
1236 void faddp(int i = 1);
1237
1238 void fchs();
1239
1240 void fcom(int i);
1241
1242 void fcomp(int i = 1);
1243 void fcomp_d(Address src);
1244 void fcomp_s(Address src);
1245
1246 void fcompp();
1247
1248 void fcos();
1249
1250 void fdecstp();
1251
1252 void fdiv(int i);
1253 void fdiv_d(Address src);
1254 void fdivr_s(Address src);
1255 void fdiva(int i); // "alternate" fdiv
1256 void fdivp(int i = 1);
1257
1258 void fdivr(int i);
1259 void fdivr_d(Address src);
1260 void fdiv_s(Address src);
1261
1262 void fdivra(int i); // "alternate" reversed fdiv
1263
1264 void fdivrp(int i = 1);
1265
1266 void ffree(int i = 0);
1267
1268 void fild_d(Address adr);
1269 void fild_s(Address adr);
1270
1271 void fincstp();
1272
1273 void finit();
1274
1275 void fist_s (Address adr);
1276 void fistp_d(Address adr);
1277 void fistp_s(Address adr);
1278
1279 void fld1();
1280
1281 void fld_d(Address adr);
1282 void fld_s(Address adr);
1283 void fld_s(int index);
1284 void fld_x(Address adr); // extended-precision (80-bit) format
1285
1286 void fldcw(Address src);
1287
1288 void fldenv(Address src);
1289
1290 void fldlg2();
1291
1292 void fldln2();
1293
1294 void fldz();
1295
1296 void flog();
1297 void flog10();
1298
1299 void fmul(int i);
1300
1301 void fmul_d(Address src);
1302 void fmul_s(Address src);
1303
1304 void fmula(int i); // "alternate" fmul
1305
1306 void fmulp(int i = 1);
1307
1308 void fnsave(Address dst);
1309
1310 void fnstcw(Address src);
1311
1312 void fnstsw_ax();
1313
1314 void fprem();
1315 void fprem1();
1316
1317 void frstor(Address src);
1318
1319 void fsin();
1320
1321 void fsqrt();
1322
1323 void fst_d(Address adr);
1324 void fst_s(Address adr);
1325
1326 void fstp_d(Address adr);
1327 void fstp_d(int index);
1328 void fstp_s(Address adr);
1329 void fstp_x(Address adr); // extended-precision (80-bit) format
1330
1331 void fsub(int i);
1332 void fsub_d(Address src);
1333 void fsub_s(Address src);
1334
1335 void fsuba(int i); // "alternate" fsub
1336
1337 void fsubp(int i = 1);
1338
1339 void fsubr(int i);
1340 void fsubr_d(Address src);
1341 void fsubr_s(Address src);
1342
1343 void fsubra(int i); // "alternate" reversed fsub
1344
1345 void fsubrp(int i = 1);
1346
1347 void ftan();
1348
1349 void ftst();
1350
1351 void fucomi(int i = 1);
1352 void fucomip(int i = 1);
1353
1354 void fwait();
1355
1356 void fxch(int i = 1);
1357
1358 void fxrstor(Address src);
1359 void xrstor(Address src);
1360
1361 void fxsave(Address dst);
1362 void xsave(Address dst);
1363
1364 void fyl2x();
1365 void frndint();
1366 void f2xm1();
1367 void fldl2e();
1368
1369 void hlt();
1370
1371 void idivl(Register src);
1372 void divl(Register src); // Unsigned division
1373
1374 #ifdef _LP64
1375 void idivq(Register src);
1376 #endif
1377
1378 void imull(Register dst, Register src);
1379 void imull(Register dst, Register src, int value);
1380 void imull(Register dst, Address src);
1381
1382 #ifdef _LP64
1383 void imulq(Register dst, Register src);
1384 void imulq(Register dst, Register src, int value);
1385 void imulq(Register dst, Address src);
1386 #endif
1387
1388 // jcc is the generic conditional branch generator to run-
1389 // time routines, jcc is used for branches to labels. jcc
1390 // takes a branch opcode (cc) and a label (L) and generates
1391 // either a backward branch or a forward branch and links it
1392 // to the label fixup chain. Usage:
1393 //
1394 // Label L; // unbound label
1395 // jcc(cc, L); // forward branch to unbound label
1396 // bind(L); // bind label to the current pc
1397 // jcc(cc, L); // backward branch to bound label
1398 // bind(L); // illegal: a label may be bound only once
1399 //
1400 // Note: The same Label can be used for forward and backward branches
1401 // but it may be bound only once.
1402
1403 void jcc(Condition cc, Label& L, bool maybe_short = true);
1404
1405 // Conditional jump to a 8-bit offset to L.
1406 // WARNING: be very careful using this for forward jumps. If the label is
1407 // not bound within an 8-bit offset of this instruction, a run-time error
1408 // will occur.
1409 void jccb(Condition cc, Label& L);
1410
1411 void jmp(Address entry); // pc <- entry
1412
1413 // Label operations & relative jumps (PPUM Appendix D)
1414 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L
1415
1416 void jmp(Register entry); // pc <- entry
1417
1418 // Unconditional 8-bit offset jump to L.
1419 // WARNING: be very careful using this for forward jumps. If the label is
1420 // not bound within an 8-bit offset of this instruction, a run-time error
1421 // will occur.
1422 void jmpb(Label& L);
1423
1424 void ldmxcsr( Address src );
1425
1426 void leal(Register dst, Address src);
1427
1428 void leaq(Register dst, Address src);
1429
1430 void lfence();
1431
1432 void lock();
1433
1434 void lzcntl(Register dst, Register src);
1435
1436 #ifdef _LP64
1437 void lzcntq(Register dst, Register src);
1438 #endif
1439
1440 enum Membar_mask_bits {
1441 StoreStore = 1 << 3,
1442 LoadStore = 1 << 2,
1443 StoreLoad = 1 << 1,
1444 LoadLoad = 1 << 0
1445 };
1446
1447 // Serializes memory and blows flags
1448 void membar(Membar_mask_bits order_constraint) {
1449 if (os::is_MP()) {
1450 // We only have to handle StoreLoad
1451 if (order_constraint & StoreLoad) {
1452 // All usable chips support "locked" instructions which suffice
1453 // as barriers, and are much faster than the alternative of
1454 // using cpuid instruction. We use here a locked add [esp-C],0.
1455 // This is conveniently otherwise a no-op except for blowing
1456 // flags, and introducing a false dependency on target memory
1457 // location. We can't do anything with flags, but we can avoid
1458 // memory dependencies in the current method by locked-adding
1459 // somewhere else on the stack. Doing [esp+C] will collide with
1460 // something on stack in current method, hence we go for [esp-C].
1461 // It is convenient since it is almost always in data cache, for
1462 // any small C. We need to step back from SP to avoid data
1463 // dependencies with other things on below SP (callee-saves, for
1464 // example). Without a clear way to figure out the minimal safe
1465 // distance from SP, it makes sense to step back the complete
1466 // cache line, as this will also avoid possible second-order effects
1467 // with locked ops against the cache line. Our choice of offset
1468 // is bounded by x86 operand encoding, which should stay within
1469 // [-128; +127] to have the 8-byte displacement encoding.
1470 //
1471 // Any change to this code may need to revisit other places in
1472 // the code where this idiom is used, in particular the
1473 // orderAccess code.
1474
1475 int offset = -VM_Version::L1_line_size();
1476 if (offset < -128) {
1477 offset = -128;
1478 }
1479
1480 lock();
1481 addl(Address(rsp, offset), 0);// Assert the lock# signal here
1482 }
1483 }
1484 }
1485
1486 void mfence();
1487
1488 // Moves
1489
1490 void mov64(Register dst, int64_t imm64);
1491
1492 void movb(Address dst, Register src);
1493 void movb(Address dst, int imm8);
1494 void movb(Register dst, Address src);
1495
1496 void kmovql(KRegister dst, KRegister src);
1497 void kmovql(KRegister dst, Register src);
1498 void kmovdl(KRegister dst, Register src);
1499 void kmovwl(KRegister dst, Register src);
1500 void kmovql(Address dst, KRegister src);
1501 void kmovql(KRegister dst, Address src);
1502
1503 void movdl(XMMRegister dst, Register src);
1504 void movdl(Register dst, XMMRegister src);
1505 void movdl(XMMRegister dst, Address src);
1506 void movdl(Address dst, XMMRegister src);
1507
1508 // Move Double Quadword
1509 void movdq(XMMRegister dst, Register src);
1510 void movdq(Register dst, XMMRegister src);
1511
1512 // Move Aligned Double Quadword
1513 void movdqa(XMMRegister dst, XMMRegister src);
1514 void movdqa(XMMRegister dst, Address src);
1515
1516 // Move Unaligned Double Quadword
1517 void movdqu(Address dst, XMMRegister src);
1518 void movdqu(XMMRegister dst, Address src);
1519 void movdqu(XMMRegister dst, XMMRegister src);
1520
1521 // Move Unaligned 256bit Vector
1522 void vmovdqu(Address dst, XMMRegister src);
1523 void vmovdqu(XMMRegister dst, Address src);
1524 void vmovdqu(XMMRegister dst, XMMRegister src);
1525
1526 // Move Unaligned 512bit Vector
1527 void evmovdqul(Address dst, XMMRegister src, int vector_len);
1528 void evmovdqul(XMMRegister dst, Address src, int vector_len);
1529 void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len);
1530 void evmovdquq(Address dst, XMMRegister src, int vector_len);
1531 void evmovdquq(XMMRegister dst, Address src, int vector_len);
1532 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len);
1533
1534 // Move lower 64bit to high 64bit in 128bit register
1535 void movlhps(XMMRegister dst, XMMRegister src);
1536
1537 void movl(Register dst, int32_t imm32);
1538 void movl(Address dst, int32_t imm32);
1539 void movl(Register dst, Register src);
1540 void movl(Register dst, Address src);
1541 void movl(Address dst, Register src);
1542
1543 // These dummies prevent using movl from converting a zero (like NULL) into Register
1544 // by giving the compiler two choices it can't resolve
1545
1546 void movl(Address dst, void* junk);
1547 void movl(Register dst, void* junk);
1548
1549 #ifdef _LP64
1550 void movq(Register dst, Register src);
1551 void movq(Register dst, Address src);
1552 void movq(Address dst, Register src);
1553 #endif
1554
1555 void movq(Address dst, MMXRegister src );
1556 void movq(MMXRegister dst, Address src );
1557
1558 #ifdef _LP64
1559 // These dummies prevent using movq from converting a zero (like NULL) into Register
1560 // by giving the compiler two choices it can't resolve
1561
1562 void movq(Address dst, void* dummy);
1563 void movq(Register dst, void* dummy);
1564 #endif
1565
1566 // Move Quadword
1567 void movq(Address dst, XMMRegister src);
1568 void movq(XMMRegister dst, Address src);
1569
1570 void movsbl(Register dst, Address src);
1571 void movsbl(Register dst, Register src);
1572
1573 #ifdef _LP64
1574 void movsbq(Register dst, Address src);
1575 void movsbq(Register dst, Register src);
1576
1577 // Move signed 32bit immediate to 64bit extending sign
1578 void movslq(Address dst, int32_t imm64);
1579 void movslq(Register dst, int32_t imm64);
1580
1581 void movslq(Register dst, Address src);
1582 void movslq(Register dst, Register src);
1583 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1584 #endif
1585
1586 void movswl(Register dst, Address src);
1587 void movswl(Register dst, Register src);
1588
1589 #ifdef _LP64
1590 void movswq(Register dst, Address src);
1591 void movswq(Register dst, Register src);
1592 #endif
1593
1594 void movw(Address dst, int imm16);
1595 void movw(Register dst, Address src);
1596 void movw(Address dst, Register src);
1597
1598 void movzbl(Register dst, Address src);
1599 void movzbl(Register dst, Register src);
1600
1601 #ifdef _LP64
1602 void movzbq(Register dst, Address src);
1603 void movzbq(Register dst, Register src);
1604 #endif
1605
1606 void movzwl(Register dst, Address src);
1607 void movzwl(Register dst, Register src);
1608
1609 #ifdef _LP64
1610 void movzwq(Register dst, Address src);
1611 void movzwq(Register dst, Register src);
1612 #endif
1613
1614 // Unsigned multiply with RAX destination register
1615 void mull(Address src);
1616 void mull(Register src);
1617
1618 #ifdef _LP64
1619 void mulq(Address src);
1620 void mulq(Register src);
1621 void mulxq(Register dst1, Register dst2, Register src);
1622 #endif
1623
1624 // Multiply Scalar Double-Precision Floating-Point Values
1625 void mulsd(XMMRegister dst, Address src);
1626 void mulsd(XMMRegister dst, XMMRegister src);
1627
1628 // Multiply Scalar Single-Precision Floating-Point Values
1629 void mulss(XMMRegister dst, Address src);
1630 void mulss(XMMRegister dst, XMMRegister src);
1631
1632 void negl(Register dst);
1633
1634 #ifdef _LP64
1635 void negq(Register dst);
1636 #endif
1637
1638 void nop(int i = 1);
1639
1640 void notl(Register dst);
1641
1642 #ifdef _LP64
1643 void notq(Register dst);
1644 #endif
1645
1646 void orl(Address dst, int32_t imm32);
1647 void orl(Register dst, int32_t imm32);
1648 void orl(Register dst, Address src);
1649 void orl(Register dst, Register src);
1650 void orl(Address dst, Register src);
1651
1652 void orq(Address dst, int32_t imm32);
1653 void orq(Register dst, int32_t imm32);
1654 void orq(Register dst, Address src);
1655 void orq(Register dst, Register src);
1656
1657 // Pack with unsigned saturation
1658 void packuswb(XMMRegister dst, XMMRegister src);
1659 void packuswb(XMMRegister dst, Address src);
1660 void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1661
1662 // Pemutation of 64bit words
1663 void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1664 void vpermq(XMMRegister dst, XMMRegister src, int imm8);
1665
1666 void pause();
1667
1668 // SSE4.2 string instructions
1669 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1670 void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1671
1672 // SSE 4.1 extract
1673 void pextrd(Register dst, XMMRegister src, int imm8);
1674 void pextrq(Register dst, XMMRegister src, int imm8);
1675 // SSE 2 extract
1676 void pextrw(Register dst, XMMRegister src, int imm8);
1677
1678 // SSE 4.1 insert
1679 void pinsrd(XMMRegister dst, Register src, int imm8);
1680 void pinsrq(XMMRegister dst, Register src, int imm8);
1681 // SSE 2 insert
1682 void pinsrw(XMMRegister dst, Register src, int imm8);
1683
1684 // SSE4.1 packed move
1685 void pmovzxbw(XMMRegister dst, XMMRegister src);
1686 void pmovzxbw(XMMRegister dst, Address src);
1687
1688 #ifndef _LP64 // no 32bit push/pop on amd64
1689 void popl(Address dst);
1690 #endif
1691
1692 #ifdef _LP64
1693 void popq(Address dst);
1694 #endif
1695
1696 void popcntl(Register dst, Address src);
1697 void popcntl(Register dst, Register src);
1698
1699 #ifdef _LP64
1700 void popcntq(Register dst, Address src);
1701 void popcntq(Register dst, Register src);
1702 #endif
1703
1704 // Prefetches (SSE, SSE2, 3DNOW only)
1705
1706 void prefetchnta(Address src);
1707 void prefetchr(Address src);
1708 void prefetcht0(Address src);
1709 void prefetcht1(Address src);
1710 void prefetcht2(Address src);
1711 void prefetchw(Address src);
1712
1713 // Shuffle Bytes
1714 void pshufb(XMMRegister dst, XMMRegister src);
1715 void pshufb(XMMRegister dst, Address src);
1716
1717 // Shuffle Packed Doublewords
1718 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1719 void pshufd(XMMRegister dst, Address src, int mode);
1720
1721 // Shuffle Packed Low Words
1722 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1723 void pshuflw(XMMRegister dst, Address src, int mode);
1724
1725 // Shift Right by bytes Logical DoubleQuadword Immediate
1726 void psrldq(XMMRegister dst, int shift);
1727 // Shift Left by bytes Logical DoubleQuadword Immediate
1728 void pslldq(XMMRegister dst, int shift);
1729
1730 // Logical Compare 128bit
1731 void ptest(XMMRegister dst, XMMRegister src);
1732 void ptest(XMMRegister dst, Address src);
1733 // Logical Compare 256bit
1734 void vptest(XMMRegister dst, XMMRegister src);
1735 void vptest(XMMRegister dst, Address src);
1736
1737 // Interleave Low Bytes
1738 void punpcklbw(XMMRegister dst, XMMRegister src);
1739 void punpcklbw(XMMRegister dst, Address src);
1740
1741 // Interleave Low Doublewords
1742 void punpckldq(XMMRegister dst, XMMRegister src);
1743 void punpckldq(XMMRegister dst, Address src);
1744
1745 // Interleave Low Quadwords
1746 void punpcklqdq(XMMRegister dst, XMMRegister src);
1747
1748 #ifndef _LP64 // no 32bit push/pop on amd64
1749 void pushl(Address src);
1750 #endif
1751
1752 void pushq(Address src);
1753
1754 void rcll(Register dst, int imm8);
1755
1756 void rclq(Register dst, int imm8);
1757
1758 void rcrq(Register dst, int imm8);
1759
1760 void rdtsc();
1761
1762 void ret(int imm16);
1763
1764 #ifdef _LP64
1765 void rorq(Register dst, int imm8);
1766 void rorxq(Register dst, Register src, int imm8);
1767 #endif
1768
1769 void sahf();
1770
1771 void sarl(Register dst, int imm8);
1772 void sarl(Register dst);
1773
1774 void sarq(Register dst, int imm8);
1775 void sarq(Register dst);
1776
1777 void sbbl(Address dst, int32_t imm32);
1778 void sbbl(Register dst, int32_t imm32);
1779 void sbbl(Register dst, Address src);
1780 void sbbl(Register dst, Register src);
1781
1782 void sbbq(Address dst, int32_t imm32);
1783 void sbbq(Register dst, int32_t imm32);
1784 void sbbq(Register dst, Address src);
1785 void sbbq(Register dst, Register src);
1786
1787 void setb(Condition cc, Register dst);
1788
1789 void shldl(Register dst, Register src);
1790
1791 void shll(Register dst, int imm8);
1792 void shll(Register dst);
1793
1794 void shlq(Register dst, int imm8);
1795 void shlq(Register dst);
1796
1797 void shrdl(Register dst, Register src);
1798
1799 void shrl(Register dst, int imm8);
1800 void shrl(Register dst);
1801
1802 void shrq(Register dst, int imm8);
1803 void shrq(Register dst);
1804
1805 void smovl(); // QQQ generic?
1806
1807 // Compute Square Root of Scalar Double-Precision Floating-Point Value
1808 void sqrtsd(XMMRegister dst, Address src);
1809 void sqrtsd(XMMRegister dst, XMMRegister src);
1810
1811 // Compute Square Root of Scalar Single-Precision Floating-Point Value
1812 void sqrtss(XMMRegister dst, Address src);
1813 void sqrtss(XMMRegister dst, XMMRegister src);
1814
1815 void std();
1816
1817 void stmxcsr( Address dst );
1818
1819 void subl(Address dst, int32_t imm32);
1820 void subl(Address dst, Register src);
1821 void subl(Register dst, int32_t imm32);
1822 void subl(Register dst, Address src);
1823 void subl(Register dst, Register src);
1824
1825 void subq(Address dst, int32_t imm32);
1826 void subq(Address dst, Register src);
1827 void subq(Register dst, int32_t imm32);
1828 void subq(Register dst, Address src);
1829 void subq(Register dst, Register src);
1830
1831 // Force generation of a 4 byte immediate value even if it fits into 8bit
1832 void subl_imm32(Register dst, int32_t imm32);
1833 void subq_imm32(Register dst, int32_t imm32);
1834
1835 // Subtract Scalar Double-Precision Floating-Point Values
1836 void subsd(XMMRegister dst, Address src);
1837 void subsd(XMMRegister dst, XMMRegister src);
1838
1839 // Subtract Scalar Single-Precision Floating-Point Values
1840 void subss(XMMRegister dst, Address src);
1841 void subss(XMMRegister dst, XMMRegister src);
1842
1843 void testb(Register dst, int imm8);
1844
1845 void testl(Register dst, int32_t imm32);
1846 void testl(Register dst, Register src);
1847 void testl(Register dst, Address src);
1848
1849 void testq(Register dst, int32_t imm32);
1850 void testq(Register dst, Register src);
1851
1852 // BMI - count trailing zeros
1853 void tzcntl(Register dst, Register src);
1854 void tzcntq(Register dst, Register src);
1855
1856 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1857 void ucomisd(XMMRegister dst, Address src);
1858 void ucomisd(XMMRegister dst, XMMRegister src);
1859
1860 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1861 void ucomiss(XMMRegister dst, Address src);
1862 void ucomiss(XMMRegister dst, XMMRegister src);
1863
1864 void xabort(int8_t imm8);
1865
1866 void xaddl(Address dst, Register src);
1867
1868 void xaddq(Address dst, Register src);
1869
1870 void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none);
1871
1872 void xchgl(Register reg, Address adr);
1873 void xchgl(Register dst, Register src);
1874
1875 void xchgq(Register reg, Address adr);
1876 void xchgq(Register dst, Register src);
1877
1878 void xend();
1879
1880 // Get Value of Extended Control Register
1881 void xgetbv();
1882
1883 void xorl(Register dst, int32_t imm32);
1884 void xorl(Register dst, Address src);
1885 void xorl(Register dst, Register src);
1886
1887 void xorq(Register dst, Address src);
1888 void xorq(Register dst, Register src);
1889
1890 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1891
1892 // AVX 3-operands scalar instructions (encoded with VEX prefix)
1893
1894 void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
1895 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1896 void vaddss(XMMRegister dst, XMMRegister nds, Address src);
1897 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1898 void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
1899 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1900 void vdivss(XMMRegister dst, XMMRegister nds, Address src);
1901 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1902 void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
1903 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1904 void vmulss(XMMRegister dst, XMMRegister nds, Address src);
1905 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1906 void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
1907 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1908 void vsubss(XMMRegister dst, XMMRegister nds, Address src);
1909 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1910
1911
1912 //====================VECTOR ARITHMETIC=====================================
1913
1914 // Add Packed Floating-Point Values
1915 void addpd(XMMRegister dst, XMMRegister src);
1916 void addps(XMMRegister dst, XMMRegister src);
1917 void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1918 void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1919 void vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1920 void vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1921
1922 // Subtract Packed Floating-Point Values
1923 void subpd(XMMRegister dst, XMMRegister src);
1924 void subps(XMMRegister dst, XMMRegister src);
1925 void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1926 void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1927 void vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1928 void vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1929
1930 // Multiply Packed Floating-Point Values
1931 void mulpd(XMMRegister dst, XMMRegister src);
1932 void mulpd(XMMRegister dst, Address src);
1933 void mulps(XMMRegister dst, XMMRegister src);
1934 void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1935 void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1936 void vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1937 void vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1938
1939 // Divide Packed Floating-Point Values
1940 void divpd(XMMRegister dst, XMMRegister src);
1941 void divps(XMMRegister dst, XMMRegister src);
1942 void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1943 void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1944 void vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1945 void vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1946
1947 // Sqrt Packed Floating-Point Values - Double precision only
1948 void vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len);
1949 void vsqrtpd(XMMRegister dst, Address src, int vector_len);
1950
1951 // Bitwise Logical AND of Packed Floating-Point Values
1952 void andpd(XMMRegister dst, XMMRegister src);
1953 void andps(XMMRegister dst, XMMRegister src);
1954 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1955 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1956 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1957 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1958
1959 void unpckhpd(XMMRegister dst, XMMRegister src);
1960 void unpcklpd(XMMRegister dst, XMMRegister src);
1961
1962 // Bitwise Logical XOR of Packed Floating-Point Values
1963 void xorpd(XMMRegister dst, XMMRegister src);
1964 void xorps(XMMRegister dst, XMMRegister src);
1965 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1966 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1967 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1968 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1969
1970 // Add horizontal packed integers
1971 void vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1972 void vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1973 void phaddw(XMMRegister dst, XMMRegister src);
1974 void phaddd(XMMRegister dst, XMMRegister src);
1975
1976 // Add packed integers
1977 void paddb(XMMRegister dst, XMMRegister src);
1978 void paddw(XMMRegister dst, XMMRegister src);
1979 void paddd(XMMRegister dst, XMMRegister src);
1980 void paddq(XMMRegister dst, XMMRegister src);
1981 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1982 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1983 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1984 void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1985 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1986 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1987 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1988 void vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1989
1990 // Sub packed integers
1991 void psubb(XMMRegister dst, XMMRegister src);
1992 void psubw(XMMRegister dst, XMMRegister src);
1993 void psubd(XMMRegister dst, XMMRegister src);
1994 void psubq(XMMRegister dst, XMMRegister src);
1995 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1996 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1997 void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1998 void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1999 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2000 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2001 void vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2002 void vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2003
2004 // Multiply packed integers (only shorts and ints)
2005 void pmullw(XMMRegister dst, XMMRegister src);
2006 void pmulld(XMMRegister dst, XMMRegister src);
2007 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2008 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2009 void vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2010 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2011 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2012 void vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2013
2014 // Shift left packed integers
2015 void psllw(XMMRegister dst, int shift);
2016 void pslld(XMMRegister dst, int shift);
2017 void psllq(XMMRegister dst, int shift);
2018 void psllw(XMMRegister dst, XMMRegister shift);
2019 void pslld(XMMRegister dst, XMMRegister shift);
2020 void psllq(XMMRegister dst, XMMRegister shift);
2021 void vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2022 void vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2023 void vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2024 void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2025 void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2026 void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2027
2028 // Logical shift right packed integers
2029 void psrlw(XMMRegister dst, int shift);
2030 void psrld(XMMRegister dst, int shift);
2031 void psrlq(XMMRegister dst, int shift);
2032 void psrlw(XMMRegister dst, XMMRegister shift);
2033 void psrld(XMMRegister dst, XMMRegister shift);
2034 void psrlq(XMMRegister dst, XMMRegister shift);
2035 void vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2036 void vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2037 void vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2038 void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2039 void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2040 void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2041
2042 // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
2043 void psraw(XMMRegister dst, int shift);
2044 void psrad(XMMRegister dst, int shift);
2045 void psraw(XMMRegister dst, XMMRegister shift);
2046 void psrad(XMMRegister dst, XMMRegister shift);
2047 void vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2048 void vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2049 void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2050 void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2051
2052 // And packed integers
2053 void pand(XMMRegister dst, XMMRegister src);
2054 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2055 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2056
2057 // Andn packed integers
2058 void pandn(XMMRegister dst, XMMRegister src);
2059
2060 // Or packed integers
2061 void por(XMMRegister dst, XMMRegister src);
2062 void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2063 void vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2064
2065 // Xor packed integers
2066 void pxor(XMMRegister dst, XMMRegister src);
2067 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2068 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2069
2070 // Copy low 128bit into high 128bit of YMM registers.
2071 void vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src);
2072 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src);
2073 void vextractf128h(XMMRegister dst, XMMRegister src);
2074 void vextracti128h(XMMRegister dst, XMMRegister src);
2075
2076 // Load/store high 128bit of YMM registers which does not destroy other half.
2077 void vinsertf128h(XMMRegister dst, Address src);
2078 void vinserti128h(XMMRegister dst, Address src);
2079 void vextractf128h(Address dst, XMMRegister src);
2080 void vextracti128h(Address dst, XMMRegister src);
2081
2082 // Copy low 256bit into high 256bit of ZMM registers.
2083 void vinserti64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src);
2084 void vinsertf64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src);
2085 void vextracti64x4h(XMMRegister dst, XMMRegister src);
2086 void vextractf64x4h(XMMRegister dst, XMMRegister src);
2087 void vextractf64x4h(Address dst, XMMRegister src);
2088 void vinsertf64x4h(XMMRegister dst, Address src);
2089
2090 // Copy targeted 128bit segments of the ZMM registers
2091 void vextracti64x2h(XMMRegister dst, XMMRegister src, int value);
2092 void vextractf64x2h(XMMRegister dst, XMMRegister src, int value);
2093 void vextractf32x4h(XMMRegister dst, XMMRegister src, int value);
2094 void vextractf32x4h(Address dst, XMMRegister src, int value);
2095 void vinsertf32x4h(XMMRegister dst, XMMRegister nds, XMMRegister src, int value);
2096 void vinsertf32x4h(XMMRegister dst, Address src, int value);
2097
2098 // duplicate 4-bytes integer data from src into 8 locations in dest
2099 void vpbroadcastd(XMMRegister dst, XMMRegister src);
2100
2101 // duplicate n-bytes integer data from src into vector_len locations in dest
2102 void evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len);
2103 void evpbroadcastb(XMMRegister dst, Address src, int vector_len);
2104 void evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
2105 void evpbroadcastw(XMMRegister dst, Address src, int vector_len);
2106 void evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len);
2107 void evpbroadcastd(XMMRegister dst, Address src, int vector_len);
2108 void evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len);
2109 void evpbroadcastq(XMMRegister dst, Address src, int vector_len);
2110
2111 void evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len);
2112 void evpbroadcastss(XMMRegister dst, Address src, int vector_len);
2113 void evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len);
2114 void evpbroadcastsd(XMMRegister dst, Address src, int vector_len);
2115
2116 void evpbroadcastb(XMMRegister dst, Register src, int vector_len);
2117 void evpbroadcastw(XMMRegister dst, Register src, int vector_len);
2118 void evpbroadcastd(XMMRegister dst, Register src, int vector_len);
2119 void evpbroadcastq(XMMRegister dst, Register src, int vector_len);
2120
2121 // Carry-Less Multiplication Quadword
2122 void pclmulqdq(XMMRegister dst, XMMRegister src, int mask);
2123 void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask);
2124
2125 // AVX instruction which is used to clear upper 128 bits of YMM registers and
2126 // to avoid transaction penalty between AVX and SSE states. There is no
2127 // penalty if legacy SSE instructions are encoded using VEX prefix because
2128 // they always clear upper 128 bits. It should be used before calling
2129 // runtime code and native libraries.
2130 void vzeroupper();
2131
2132 protected:
2133 // Next instructions require address alignment 16 bytes SSE mode.
2134 // They should be called only from corresponding MacroAssembler instructions.
2135 void andpd(XMMRegister dst, Address src);
2136 void andps(XMMRegister dst, Address src);
2137 void xorpd(XMMRegister dst, Address src);
2138 void xorps(XMMRegister dst, Address src);
2139
2140 };
2141
2142 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP