1 /*
2 * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_InstructionPrinter.hpp"
27 #include "c1/c1_LIR.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_ValueStack.hpp"
30 #include "ci/ciInstance.hpp"
31 #include "runtime/sharedRuntime.hpp"
32
33 Register LIR_OprDesc::as_register() const {
34 return FrameMap::cpu_rnr2reg(cpu_regnr());
35 }
36
37 Register LIR_OprDesc::as_register_lo() const {
38 return FrameMap::cpu_rnr2reg(cpu_regnrLo());
39 }
40
41 Register LIR_OprDesc::as_register_hi() const {
42 return FrameMap::cpu_rnr2reg(cpu_regnrHi());
43 }
44
45 #if defined(X86)
46
47 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
48 return FrameMap::nr2xmmreg(xmm_regnr());
49 }
50
51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
52 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
53 return FrameMap::nr2xmmreg(xmm_regnrLo());
54 }
55
56 #endif // X86
57
58 #if defined(SPARC) || defined(PPC)
59
60 FloatRegister LIR_OprDesc::as_float_reg() const {
61 return FrameMap::nr2floatreg(fpu_regnr());
62 }
63
64 FloatRegister LIR_OprDesc::as_double_reg() const {
65 return FrameMap::nr2floatreg(fpu_regnrHi());
66 }
67
68 #endif
69
70 #if defined(ARM) || defined (AARCH64)
71
72 FloatRegister LIR_OprDesc::as_float_reg() const {
73 return as_FloatRegister(fpu_regnr());
74 }
75
76 FloatRegister LIR_OprDesc::as_double_reg() const {
77 return as_FloatRegister(fpu_regnrLo());
78 }
79
80 #endif
81
82
83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
84
85 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
86 ValueTag tag = type->tag();
87 switch (tag) {
88 case metaDataTag : {
89 ClassConstant* c = type->as_ClassConstant();
90 if (c != NULL && !c->value()->is_loaded()) {
91 return LIR_OprFact::metadataConst(NULL);
92 } else if (c != NULL) {
93 return LIR_OprFact::metadataConst(c->value()->constant_encoding());
94 } else {
95 MethodConstant* m = type->as_MethodConstant();
96 assert (m != NULL, "not a class or a method?");
97 return LIR_OprFact::metadataConst(m->value()->constant_encoding());
98 }
99 }
100 case objectTag : {
101 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
102 }
103 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
104 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value());
105 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
106 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value());
107 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
108 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
109 }
110 }
111
112
113 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) {
114 switch (type->tag()) {
115 case objectTag: return LIR_OprFact::oopConst(NULL);
116 case addressTag:return LIR_OprFact::addressConst(0);
117 case intTag: return LIR_OprFact::intConst(0);
118 case floatTag: return LIR_OprFact::floatConst(0.0);
119 case longTag: return LIR_OprFact::longConst(0);
120 case doubleTag: return LIR_OprFact::doubleConst(0.0);
121 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
122 }
123 return illegalOpr;
124 }
125
126
127
128 //---------------------------------------------------
129
130
131 LIR_Address::Scale LIR_Address::scale(BasicType type) {
132 int elem_size = type2aelembytes(type);
133 switch (elem_size) {
134 case 1: return LIR_Address::times_1;
135 case 2: return LIR_Address::times_2;
136 case 4: return LIR_Address::times_4;
137 case 8: return LIR_Address::times_8;
138 }
139 ShouldNotReachHere();
140 return LIR_Address::times_1;
141 }
142
143
144 #ifndef PRODUCT
145 void LIR_Address::verify0() const {
146 #if defined(SPARC) || defined(PPC)
147 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
148 assert(disp() == 0 || index()->is_illegal(), "can't have both");
149 #endif
150 #ifdef _LP64
151 assert(base()->is_cpu_register(), "wrong base operand");
152 #ifndef AARCH64
153 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
154 #else
155 assert(index()->is_illegal() || index()->is_double_cpu() || index()->is_single_cpu(), "wrong index operand");
156 #endif
157 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
158 "wrong type for addresses");
159 #else
160 assert(base()->is_single_cpu(), "wrong base operand");
161 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
162 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
163 "wrong type for addresses");
164 #endif
165 }
166 #endif
167
168
169 //---------------------------------------------------
170
171 char LIR_OprDesc::type_char(BasicType t) {
172 switch (t) {
173 case T_ARRAY:
174 t = T_OBJECT;
175 case T_BOOLEAN:
176 case T_CHAR:
177 case T_FLOAT:
178 case T_DOUBLE:
179 case T_BYTE:
180 case T_SHORT:
181 case T_INT:
182 case T_LONG:
183 case T_OBJECT:
184 case T_ADDRESS:
185 case T_VOID:
186 return ::type2char(t);
187 case T_METADATA:
188 return 'M';
189 case T_ILLEGAL:
190 return '?';
191
192 default:
193 ShouldNotReachHere();
194 return '?';
195 }
196 }
197
198 #ifndef PRODUCT
199 void LIR_OprDesc::validate_type() const {
200
201 #ifdef ASSERT
202 if (!is_pointer() && !is_illegal()) {
203 OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160
204 switch (as_BasicType(type_field())) {
205 case T_LONG:
206 assert((kindfield == cpu_register || kindfield == stack_value) &&
207 size_field() == double_size, "must match");
208 break;
209 case T_FLOAT:
210 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
211 assert((kindfield == fpu_register || kindfield == stack_value
212 ARM_ONLY(|| kindfield == cpu_register)
213 PPC_ONLY(|| kindfield == cpu_register) ) &&
214 size_field() == single_size, "must match");
215 break;
216 case T_DOUBLE:
217 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
218 assert((kindfield == fpu_register || kindfield == stack_value
219 ARM_ONLY(|| kindfield == cpu_register)
220 PPC_ONLY(|| kindfield == cpu_register) ) &&
221 size_field() == double_size, "must match");
222 break;
223 case T_BOOLEAN:
224 case T_CHAR:
225 case T_BYTE:
226 case T_SHORT:
227 case T_INT:
228 case T_ADDRESS:
229 case T_OBJECT:
230 case T_METADATA:
231 case T_ARRAY:
232 assert((kindfield == cpu_register || kindfield == stack_value) &&
233 size_field() == single_size, "must match");
234 break;
235
236 case T_ILLEGAL:
237 // XXX TKR also means unknown right now
238 // assert(is_illegal(), "must match");
239 break;
240
241 default:
242 ShouldNotReachHere();
243 }
244 }
245 #endif
246
247 }
248 #endif // PRODUCT
249
250
251 bool LIR_OprDesc::is_oop() const {
252 if (is_pointer()) {
253 return pointer()->is_oop_pointer();
254 } else {
255 OprType t= type_field();
256 assert(t != unknown_type, "not set");
257 return t == object_type;
258 }
259 }
260
261
262
263 void LIR_Op2::verify() const {
264 #ifdef ASSERT
265 switch (code()) {
266 case lir_cmove:
267 case lir_xchg:
268 break;
269
270 default:
271 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
272 "can't produce oops from arith");
273 }
274
275 if (TwoOperandLIRForm) {
276 switch (code()) {
277 case lir_add:
278 case lir_sub:
279 case lir_mul:
280 case lir_mul_strictfp:
281 case lir_div:
282 case lir_div_strictfp:
283 case lir_rem:
284 case lir_logic_and:
285 case lir_logic_or:
286 case lir_logic_xor:
287 case lir_shl:
288 case lir_shr:
289 assert(in_opr1() == result_opr(), "opr1 and result must match");
290 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
291 break;
292
293 // special handling for lir_ushr because of write barriers
294 case lir_ushr:
295 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant");
296 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
297 break;
298
299 }
300 }
301 #endif
302 }
303
304
305 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
306 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
307 , _cond(cond)
308 , _type(type)
309 , _label(block->label())
310 , _block(block)
311 , _ublock(NULL)
312 , _stub(NULL) {
313 }
314
315 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
316 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
317 , _cond(cond)
318 , _type(type)
319 , _label(stub->entry())
320 , _block(NULL)
321 , _ublock(NULL)
322 , _stub(stub) {
323 }
324
325 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)
326 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
327 , _cond(cond)
328 , _type(type)
329 , _label(block->label())
330 , _block(block)
331 , _ublock(ublock)
332 , _stub(NULL)
333 {
334 }
335
336 void LIR_OpBranch::change_block(BlockBegin* b) {
337 assert(_block != NULL, "must have old block");
338 assert(_block->label() == label(), "must be equal");
339
340 _block = b;
341 _label = b->label();
342 }
343
344 void LIR_OpBranch::change_ublock(BlockBegin* b) {
345 assert(_ublock != NULL, "must have old block");
346 _ublock = b;
347 }
348
349 void LIR_OpBranch::negate_cond() {
350 switch (_cond) {
351 case lir_cond_equal: _cond = lir_cond_notEqual; break;
352 case lir_cond_notEqual: _cond = lir_cond_equal; break;
353 case lir_cond_less: _cond = lir_cond_greaterEqual; break;
354 case lir_cond_lessEqual: _cond = lir_cond_greater; break;
355 case lir_cond_greaterEqual: _cond = lir_cond_less; break;
356 case lir_cond_greater: _cond = lir_cond_lessEqual; break;
357 default: ShouldNotReachHere();
358 }
359 }
360
361
362 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
363 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
364 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
365 CodeStub* stub)
366
367 : LIR_Op(code, result, NULL)
368 , _object(object)
369 , _array(LIR_OprFact::illegalOpr)
370 , _klass(klass)
371 , _tmp1(tmp1)
372 , _tmp2(tmp2)
373 , _tmp3(tmp3)
374 , _fast_check(fast_check)
375 , _stub(stub)
376 , _info_for_patch(info_for_patch)
377 , _info_for_exception(info_for_exception)
378 , _profiled_method(NULL)
379 , _profiled_bci(-1)
380 , _should_profile(false)
381 {
382 if (code == lir_checkcast) {
383 assert(info_for_exception != NULL, "checkcast throws exceptions");
384 } else if (code == lir_instanceof) {
385 assert(info_for_exception == NULL, "instanceof throws no exceptions");
386 } else {
387 ShouldNotReachHere();
388 }
389 }
390
391
392
393 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)
394 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
395 , _object(object)
396 , _array(array)
397 , _klass(NULL)
398 , _tmp1(tmp1)
399 , _tmp2(tmp2)
400 , _tmp3(tmp3)
401 , _fast_check(false)
402 , _stub(NULL)
403 , _info_for_patch(NULL)
404 , _info_for_exception(info_for_exception)
405 , _profiled_method(NULL)
406 , _profiled_bci(-1)
407 , _should_profile(false)
408 {
409 if (code == lir_store_check) {
410 _stub = new ArrayStoreExceptionStub(object, info_for_exception);
411 assert(info_for_exception != NULL, "store_check throws exceptions");
412 } else {
413 ShouldNotReachHere();
414 }
415 }
416
417
418 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
419 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
420 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
421 , _tmp(tmp)
422 , _src(src)
423 , _src_pos(src_pos)
424 , _dst(dst)
425 , _dst_pos(dst_pos)
426 , _flags(flags)
427 , _expected_type(expected_type)
428 , _length(length) {
429 _stub = new ArrayCopyStub(this);
430 }
431
432 LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res)
433 : LIR_Op(lir_updatecrc32, res, NULL)
434 , _crc(crc)
435 , _val(val) {
436 }
437
438 //-------------------verify--------------------------
439
440 void LIR_Op1::verify() const {
441 switch(code()) {
442 case lir_move:
443 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
444 break;
445 case lir_null_check:
446 assert(in_opr()->is_register(), "must be");
447 break;
448 case lir_return:
449 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
450 break;
451 }
452 }
453
454 void LIR_OpRTCall::verify() const {
455 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
456 }
457
458 //-------------------visits--------------------------
459
460 // complete rework of LIR instruction visitor.
461 // The virtual call for each instruction type is replaced by a big
462 // switch that adds the operands for each instruction
463
464 void LIR_OpVisitState::visit(LIR_Op* op) {
465 // copy information from the LIR_Op
466 reset();
467 set_op(op);
468
469 switch (op->code()) {
470
471 // LIR_Op0
472 case lir_word_align: // result and info always invalid
473 case lir_backwardbranch_target: // result and info always invalid
474 case lir_build_frame: // result and info always invalid
475 case lir_fpop_raw: // result and info always invalid
476 case lir_24bit_FPU: // result and info always invalid
477 case lir_reset_FPU: // result and info always invalid
478 case lir_breakpoint: // result and info always invalid
479 case lir_membar: // result and info always invalid
480 case lir_membar_acquire: // result and info always invalid
481 case lir_membar_release: // result and info always invalid
482 case lir_membar_loadload: // result and info always invalid
483 case lir_membar_storestore: // result and info always invalid
484 case lir_membar_loadstore: // result and info always invalid
485 case lir_membar_storeload: // result and info always invalid
486 {
487 assert(op->as_Op0() != NULL, "must be");
488 assert(op->_info == NULL, "info not used by this instruction");
489 assert(op->_result->is_illegal(), "not used");
490 break;
491 }
492
493 case lir_nop: // may have info, result always invalid
494 case lir_std_entry: // may have result, info always invalid
495 case lir_osr_entry: // may have result, info always invalid
496 case lir_get_thread: // may have result, info always invalid
497 {
498 assert(op->as_Op0() != NULL, "must be");
499 if (op->_info != NULL) do_info(op->_info);
500 if (op->_result->is_valid()) do_output(op->_result);
501 break;
502 }
503
504
505 // LIR_OpLabel
506 case lir_label: // result and info always invalid
507 {
508 assert(op->as_OpLabel() != NULL, "must be");
509 assert(op->_info == NULL, "info not used by this instruction");
510 assert(op->_result->is_illegal(), "not used");
511 break;
512 }
513
514
515 // LIR_Op1
516 case lir_fxch: // input always valid, result and info always invalid
517 case lir_fld: // input always valid, result and info always invalid
518 case lir_ffree: // input always valid, result and info always invalid
519 case lir_push: // input always valid, result and info always invalid
520 case lir_pop: // input always valid, result and info always invalid
521 case lir_return: // input always valid, result and info always invalid
522 case lir_leal: // input and result always valid, info always invalid
523 case lir_neg: // input and result always valid, info always invalid
524 case lir_monaddr: // input and result always valid, info always invalid
525 case lir_null_check: // input and info always valid, result always invalid
526 case lir_move: // input and result always valid, may have info
527 case lir_pack64: // input and result always valid
528 case lir_unpack64: // input and result always valid
529 {
530 assert(op->as_Op1() != NULL, "must be");
531 LIR_Op1* op1 = (LIR_Op1*)op;
532
533 if (op1->_info) do_info(op1->_info);
534 if (op1->_opr->is_valid()) do_input(op1->_opr);
535 if (op1->_result->is_valid()) do_output(op1->_result);
536
537 break;
538 }
539
540 case lir_safepoint:
541 {
542 assert(op->as_Op1() != NULL, "must be");
543 LIR_Op1* op1 = (LIR_Op1*)op;
544
545 assert(op1->_info != NULL, ""); do_info(op1->_info);
546 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
547 assert(op1->_result->is_illegal(), "safepoint does not produce value");
548
549 break;
550 }
551
552 // LIR_OpConvert;
553 case lir_convert: // input and result always valid, info always invalid
554 {
555 assert(op->as_OpConvert() != NULL, "must be");
556 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
557
558 assert(opConvert->_info == NULL, "must be");
559 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
560 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
561 #ifdef PPC
562 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
563 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
564 #endif
565 do_stub(opConvert->_stub);
566
567 break;
568 }
569
570 // LIR_OpBranch;
571 case lir_branch: // may have info, input and result register always invalid
572 case lir_cond_float_branch: // may have info, input and result register always invalid
573 {
574 assert(op->as_OpBranch() != NULL, "must be");
575 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
576
577 if (opBranch->_info != NULL) do_info(opBranch->_info);
578 assert(opBranch->_result->is_illegal(), "not used");
579 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
580
581 break;
582 }
583
584
585 // LIR_OpAllocObj
586 case lir_alloc_object:
587 {
588 assert(op->as_OpAllocObj() != NULL, "must be");
589 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
590
591 if (opAllocObj->_info) do_info(opAllocObj->_info);
592 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
593 do_temp(opAllocObj->_opr);
594 }
595 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
596 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
597 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
598 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
599 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
600 do_stub(opAllocObj->_stub);
601 break;
602 }
603
604
605 // LIR_OpRoundFP;
606 case lir_roundfp: {
607 assert(op->as_OpRoundFP() != NULL, "must be");
608 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
609
610 assert(op->_info == NULL, "info not used by this instruction");
611 assert(opRoundFP->_tmp->is_illegal(), "not used");
612 do_input(opRoundFP->_opr);
613 do_output(opRoundFP->_result);
614
615 break;
616 }
617
618
619 // LIR_Op2
620 case lir_cmp:
621 case lir_cmp_l2i:
622 case lir_ucmp_fd2i:
623 case lir_cmp_fd2i:
624 case lir_add:
625 case lir_sub:
626 case lir_mul:
627 case lir_div:
628 case lir_rem:
629 case lir_sqrt:
630 case lir_abs:
631 case lir_logic_and:
632 case lir_logic_or:
633 case lir_logic_xor:
634 case lir_shl:
635 case lir_shr:
636 case lir_ushr:
637 case lir_xadd:
638 case lir_xchg:
639 case lir_assert:
640 {
641 assert(op->as_Op2() != NULL, "must be");
642 LIR_Op2* op2 = (LIR_Op2*)op;
643 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
644 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
645
646 if (op2->_info) do_info(op2->_info);
647 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
648 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
649 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
650 if (op2->_result->is_valid()) do_output(op2->_result);
651 if (op->code() == lir_xchg || op->code() == lir_xadd) {
652 // on ARM and PPC, return value is loaded first so could
653 // destroy inputs. On other platforms that implement those
654 // (x86, sparc), the extra constrainsts are harmless.
655 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
656 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
657 }
658
659 break;
660 }
661
662 // special handling for cmove: right input operand must not be equal
663 // to the result operand, otherwise the backend fails
664 case lir_cmove:
665 {
666 assert(op->as_Op2() != NULL, "must be");
667 LIR_Op2* op2 = (LIR_Op2*)op;
668
669 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
670 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
671 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
672
673 do_input(op2->_opr1);
674 do_input(op2->_opr2);
675 do_temp(op2->_opr2);
676 do_output(op2->_result);
677
678 break;
679 }
680
681 // vspecial handling for strict operations: register input operands
682 // as temp to guarantee that they do not overlap with other
683 // registers
684 case lir_mul_strictfp:
685 case lir_div_strictfp:
686 {
687 assert(op->as_Op2() != NULL, "must be");
688 LIR_Op2* op2 = (LIR_Op2*)op;
689
690 assert(op2->_info == NULL, "not used");
691 assert(op2->_opr1->is_valid(), "used");
692 assert(op2->_opr2->is_valid(), "used");
693 assert(op2->_result->is_valid(), "used");
694 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
695 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
696
697 do_input(op2->_opr1); do_temp(op2->_opr1);
698 do_input(op2->_opr2); do_temp(op2->_opr2);
699 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
700 do_output(op2->_result);
701
702 break;
703 }
704
705 case lir_throw: {
706 assert(op->as_Op2() != NULL, "must be");
707 LIR_Op2* op2 = (LIR_Op2*)op;
708
709 if (op2->_info) do_info(op2->_info);
710 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
711 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter
712 assert(op2->_result->is_illegal(), "no result");
713 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
714 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
715
716 break;
717 }
718
719 case lir_unwind: {
720 assert(op->as_Op1() != NULL, "must be");
721 LIR_Op1* op1 = (LIR_Op1*)op;
722
723 assert(op1->_info == NULL, "no info");
724 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
725 assert(op1->_result->is_illegal(), "no result");
726
727 break;
728 }
729
730
731 case lir_tan:
732 case lir_sin:
733 case lir_cos:
734 case lir_log:
735 case lir_log10: {
736 assert(op->as_Op2() != NULL, "must be");
737 LIR_Op2* op2 = (LIR_Op2*)op;
738
739 // On x86 tan/sin/cos need two temporary fpu stack slots and
740 // log/log10 need one so handle opr2 and tmp as temp inputs.
741 // Register input operand as temp to guarantee that it doesn't
742 // overlap with the input.
743 assert(op2->_info == NULL, "not used");
744 assert(op2->_tmp5->is_illegal(), "not used");
745 assert(op2->_opr1->is_valid(), "used");
746 do_input(op2->_opr1); do_temp(op2->_opr1);
747
748 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
749 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
750 if (op2->_tmp2->is_valid()) do_temp(op2->_tmp2);
751 if (op2->_tmp3->is_valid()) do_temp(op2->_tmp3);
752 if (op2->_tmp4->is_valid()) do_temp(op2->_tmp4);
753 if (op2->_result->is_valid()) do_output(op2->_result);
754
755 break;
756 }
757
758 case lir_pow: {
759 assert(op->as_Op2() != NULL, "must be");
760 LIR_Op2* op2 = (LIR_Op2*)op;
761
762 // On x86 pow needs two temporary fpu stack slots: tmp1 and
763 // tmp2. Register input operands as temps to guarantee that it
764 // doesn't overlap with the temporary slots.
765 assert(op2->_info == NULL, "not used");
766 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid(), "used");
767 assert(op2->_tmp1->is_valid() && op2->_tmp2->is_valid() && op2->_tmp3->is_valid()
768 && op2->_tmp4->is_valid() && op2->_tmp5->is_valid(), "used");
769 assert(op2->_result->is_valid(), "used");
770
771 do_input(op2->_opr1); do_temp(op2->_opr1);
772 do_input(op2->_opr2); do_temp(op2->_opr2);
773 do_temp(op2->_tmp1);
774 do_temp(op2->_tmp2);
775 do_temp(op2->_tmp3);
776 do_temp(op2->_tmp4);
777 do_temp(op2->_tmp5);
778 do_output(op2->_result);
779
780 break;
781 }
782
783 // LIR_Op3
784 case lir_idiv:
785 case lir_irem: {
786 assert(op->as_Op3() != NULL, "must be");
787 LIR_Op3* op3= (LIR_Op3*)op;
788
789 if (op3->_info) do_info(op3->_info);
790 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
791
792 // second operand is input and temp, so ensure that second operand
793 // and third operand get not the same register
794 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
795 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
796 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
797
798 if (op3->_result->is_valid()) do_output(op3->_result);
799
800 break;
801 }
802
803
804 // LIR_OpJavaCall
805 case lir_static_call:
806 case lir_optvirtual_call:
807 case lir_icvirtual_call:
808 case lir_virtual_call:
809 case lir_dynamic_call: {
810 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
811 assert(opJavaCall != NULL, "must be");
812
813 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
814
815 // only visit register parameters
816 int n = opJavaCall->_arguments->length();
817 for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) {
818 if (!opJavaCall->_arguments->at(i)->is_pointer()) {
819 do_input(*opJavaCall->_arguments->adr_at(i));
820 }
821 }
822
823 if (opJavaCall->_info) do_info(opJavaCall->_info);
824 if (FrameMap::method_handle_invoke_SP_save_opr() != LIR_OprFact::illegalOpr &&
825 opJavaCall->is_method_handle_invoke()) {
826 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
827 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
828 }
829 do_call();
830 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
831
832 break;
833 }
834
835
836 // LIR_OpRTCall
837 case lir_rtcall: {
838 assert(op->as_OpRTCall() != NULL, "must be");
839 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
840
841 // only visit register parameters
842 int n = opRTCall->_arguments->length();
843 for (int i = 0; i < n; i++) {
844 if (!opRTCall->_arguments->at(i)->is_pointer()) {
845 do_input(*opRTCall->_arguments->adr_at(i));
846 }
847 }
848 if (opRTCall->_info) do_info(opRTCall->_info);
849 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
850 do_call();
851 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
852
853 break;
854 }
855
856
857 // LIR_OpArrayCopy
858 case lir_arraycopy: {
859 assert(op->as_OpArrayCopy() != NULL, "must be");
860 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
861
862 assert(opArrayCopy->_result->is_illegal(), "unused");
863 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
864 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
865 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
866 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
867 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
868 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
869 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
870
871 // the implementation of arraycopy always has a call into the runtime
872 do_call();
873
874 break;
875 }
876
877
878 // LIR_OpUpdateCRC32
879 case lir_updatecrc32: {
880 assert(op->as_OpUpdateCRC32() != NULL, "must be");
881 LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op;
882
883 assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc);
884 assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val);
885 assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result);
886 assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32");
887
888 break;
889 }
890
891
892 // LIR_OpLock
893 case lir_lock:
894 case lir_unlock: {
895 assert(op->as_OpLock() != NULL, "must be");
896 LIR_OpLock* opLock = (LIR_OpLock*)op;
897
898 if (opLock->_info) do_info(opLock->_info);
899
900 // TODO: check if these operands really have to be temp
901 // (or if input is sufficient). This may have influence on the oop map!
902 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
903 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
904 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
905
906 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
907 assert(opLock->_result->is_illegal(), "unused");
908
909 do_stub(opLock->_stub);
910
911 break;
912 }
913
914
915 // LIR_OpDelay
916 case lir_delay_slot: {
917 assert(op->as_OpDelay() != NULL, "must be");
918 LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
919
920 visit(opDelay->delay_op());
921 break;
922 }
923
924 // LIR_OpTypeCheck
925 case lir_instanceof:
926 case lir_checkcast:
927 case lir_store_check: {
928 assert(op->as_OpTypeCheck() != NULL, "must be");
929 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
930
931 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception);
932 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch);
933 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object);
934 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) {
935 do_temp(opTypeCheck->_object);
936 }
937 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array);
938 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1);
939 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2);
940 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3);
941 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result);
942 do_stub(opTypeCheck->_stub);
943 break;
944 }
945
946 // LIR_OpCompareAndSwap
947 case lir_cas_long:
948 case lir_cas_obj:
949 case lir_cas_int: {
950 assert(op->as_OpCompareAndSwap() != NULL, "must be");
951 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
952
953 assert(opCompareAndSwap->_addr->is_valid(), "used");
954 assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
955 assert(opCompareAndSwap->_new_value->is_valid(), "used");
956 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
957 do_input(opCompareAndSwap->_addr);
958 do_temp(opCompareAndSwap->_addr);
959 do_input(opCompareAndSwap->_cmp_value);
960 do_temp(opCompareAndSwap->_cmp_value);
961 do_input(opCompareAndSwap->_new_value);
962 do_temp(opCompareAndSwap->_new_value);
963 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
964 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
965 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
966
967 break;
968 }
969
970
971 // LIR_OpAllocArray;
972 case lir_alloc_array: {
973 assert(op->as_OpAllocArray() != NULL, "must be");
974 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
975
976 if (opAllocArray->_info) do_info(opAllocArray->_info);
977 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
978 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
979 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
980 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
981 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
982 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
983 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
984 do_stub(opAllocArray->_stub);
985 break;
986 }
987
988 // LIR_OpProfileCall:
989 case lir_profile_call: {
990 assert(op->as_OpProfileCall() != NULL, "must be");
991 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
992
993 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv);
994 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo);
995 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1);
996 break;
997 }
998
999 // LIR_OpProfileType:
1000 case lir_profile_type: {
1001 assert(op->as_OpProfileType() != NULL, "must be");
1002 LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op;
1003
1004 do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp);
1005 do_input(opProfileType->_obj);
1006 do_temp(opProfileType->_tmp);
1007 break;
1008 }
1009 default:
1010 ShouldNotReachHere();
1011 }
1012 }
1013
1014
1015 void LIR_OpVisitState::do_stub(CodeStub* stub) {
1016 if (stub != NULL) {
1017 stub->visit(this);
1018 }
1019 }
1020
1021 XHandlers* LIR_OpVisitState::all_xhandler() {
1022 XHandlers* result = NULL;
1023
1024 int i;
1025 for (i = 0; i < info_count(); i++) {
1026 if (info_at(i)->exception_handlers() != NULL) {
1027 result = info_at(i)->exception_handlers();
1028 break;
1029 }
1030 }
1031
1032 #ifdef ASSERT
1033 for (i = 0; i < info_count(); i++) {
1034 assert(info_at(i)->exception_handlers() == NULL ||
1035 info_at(i)->exception_handlers() == result,
1036 "only one xhandler list allowed per LIR-operation");
1037 }
1038 #endif
1039
1040 if (result != NULL) {
1041 return result;
1042 } else {
1043 return new XHandlers();
1044 }
1045
1046 return result;
1047 }
1048
1049
1050 #ifdef ASSERT
1051 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
1052 visit(op);
1053
1054 return opr_count(inputMode) == 0 &&
1055 opr_count(outputMode) == 0 &&
1056 opr_count(tempMode) == 0 &&
1057 info_count() == 0 &&
1058 !has_call() &&
1059 !has_slow_case();
1060 }
1061 #endif
1062
1063 //---------------------------------------------------
1064
1065
1066 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
1067 masm->emit_call(this);
1068 }
1069
1070 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
1071 masm->emit_rtcall(this);
1072 }
1073
1074 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
1075 masm->emit_opLabel(this);
1076 }
1077
1078 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
1079 masm->emit_arraycopy(this);
1080 masm->append_code_stub(stub());
1081 }
1082
1083 void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) {
1084 masm->emit_updatecrc32(this);
1085 }
1086
1087 void LIR_Op0::emit_code(LIR_Assembler* masm) {
1088 masm->emit_op0(this);
1089 }
1090
1091 void LIR_Op1::emit_code(LIR_Assembler* masm) {
1092 masm->emit_op1(this);
1093 }
1094
1095 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
1096 masm->emit_alloc_obj(this);
1097 masm->append_code_stub(stub());
1098 }
1099
1100 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
1101 masm->emit_opBranch(this);
1102 if (stub()) {
1103 masm->append_code_stub(stub());
1104 }
1105 }
1106
1107 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
1108 masm->emit_opConvert(this);
1109 if (stub() != NULL) {
1110 masm->append_code_stub(stub());
1111 }
1112 }
1113
1114 void LIR_Op2::emit_code(LIR_Assembler* masm) {
1115 masm->emit_op2(this);
1116 }
1117
1118 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1119 masm->emit_alloc_array(this);
1120 masm->append_code_stub(stub());
1121 }
1122
1123 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1124 masm->emit_opTypeCheck(this);
1125 if (stub()) {
1126 masm->append_code_stub(stub());
1127 }
1128 }
1129
1130 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1131 masm->emit_compare_and_swap(this);
1132 }
1133
1134 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1135 masm->emit_op3(this);
1136 }
1137
1138 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1139 masm->emit_lock(this);
1140 if (stub()) {
1141 masm->append_code_stub(stub());
1142 }
1143 }
1144
1145 #ifdef ASSERT
1146 void LIR_OpAssert::emit_code(LIR_Assembler* masm) {
1147 masm->emit_assert(this);
1148 }
1149 #endif
1150
1151 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1152 masm->emit_delay(this);
1153 }
1154
1155 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1156 masm->emit_profile_call(this);
1157 }
1158
1159 void LIR_OpProfileType::emit_code(LIR_Assembler* masm) {
1160 masm->emit_profile_type(this);
1161 }
1162
1163 // LIR_List
1164 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1165 : _operations(8)
1166 , _compilation(compilation)
1167 #ifndef PRODUCT
1168 , _block(block)
1169 #endif
1170 #ifdef ASSERT
1171 , _file(NULL)
1172 , _line(0)
1173 #endif
1174 { }
1175
1176
1177 #ifdef ASSERT
1178 void LIR_List::set_file_and_line(const char * file, int line) {
1179 const char * f = strrchr(file, '/');
1180 if (f == NULL) f = strrchr(file, '\\');
1181 if (f == NULL) {
1182 f = file;
1183 } else {
1184 f++;
1185 }
1186 _file = f;
1187 _line = line;
1188 }
1189 #endif
1190
1191
1192 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1193 assert(this == buffer->lir_list(), "wrong lir list");
1194 const int n = _operations.length();
1195
1196 if (buffer->number_of_ops() > 0) {
1197 // increase size of instructions list
1198 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1199 // insert ops from buffer into instructions list
1200 int op_index = buffer->number_of_ops() - 1;
1201 int ip_index = buffer->number_of_insertion_points() - 1;
1202 int from_index = n - 1;
1203 int to_index = _operations.length() - 1;
1204 for (; ip_index >= 0; ip_index --) {
1205 int index = buffer->index_at(ip_index);
1206 // make room after insertion point
1207 while (index < from_index) {
1208 _operations.at_put(to_index --, _operations.at(from_index --));
1209 }
1210 // insert ops from buffer
1211 for (int i = buffer->count_at(ip_index); i > 0; i --) {
1212 _operations.at_put(to_index --, buffer->op_at(op_index --));
1213 }
1214 }
1215 }
1216
1217 buffer->finish();
1218 }
1219
1220
1221 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1222 assert(reg->type() == T_OBJECT, "bad reg");
1223 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info));
1224 }
1225
1226 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) {
1227 assert(reg->type() == T_METADATA, "bad reg");
1228 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info));
1229 }
1230
1231 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1232 append(new LIR_Op1(
1233 lir_move,
1234 LIR_OprFact::address(addr),
1235 src,
1236 addr->type(),
1237 patch_code,
1238 info));
1239 }
1240
1241
1242 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1243 append(new LIR_Op1(
1244 lir_move,
1245 LIR_OprFact::address(address),
1246 dst,
1247 address->type(),
1248 patch_code,
1249 info, lir_move_volatile));
1250 }
1251
1252 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1253 append(new LIR_Op1(
1254 lir_move,
1255 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1256 dst,
1257 type,
1258 patch_code,
1259 info, lir_move_volatile));
1260 }
1261
1262
1263 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1264 append(new LIR_Op1(
1265 lir_move,
1266 LIR_OprFact::intConst(v),
1267 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1268 type,
1269 patch_code,
1270 info));
1271 }
1272
1273
1274 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1275 append(new LIR_Op1(
1276 lir_move,
1277 LIR_OprFact::oopConst(o),
1278 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1279 type,
1280 patch_code,
1281 info));
1282 }
1283
1284
1285 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1286 append(new LIR_Op1(
1287 lir_move,
1288 src,
1289 LIR_OprFact::address(addr),
1290 addr->type(),
1291 patch_code,
1292 info));
1293 }
1294
1295
1296 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1297 append(new LIR_Op1(
1298 lir_move,
1299 src,
1300 LIR_OprFact::address(addr),
1301 addr->type(),
1302 patch_code,
1303 info,
1304 lir_move_volatile));
1305 }
1306
1307 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1308 append(new LIR_Op1(
1309 lir_move,
1310 src,
1311 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1312 type,
1313 patch_code,
1314 info, lir_move_volatile));
1315 }
1316
1317
1318 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1319 append(new LIR_Op3(
1320 lir_idiv,
1321 left,
1322 right,
1323 tmp,
1324 res,
1325 info));
1326 }
1327
1328
1329 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1330 append(new LIR_Op3(
1331 lir_idiv,
1332 left,
1333 LIR_OprFact::intConst(right),
1334 tmp,
1335 res,
1336 info));
1337 }
1338
1339
1340 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1341 append(new LIR_Op3(
1342 lir_irem,
1343 left,
1344 right,
1345 tmp,
1346 res,
1347 info));
1348 }
1349
1350
1351 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1352 append(new LIR_Op3(
1353 lir_irem,
1354 left,
1355 LIR_OprFact::intConst(right),
1356 tmp,
1357 res,
1358 info));
1359 }
1360
1361
1362 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1363 append(new LIR_Op2(
1364 lir_cmp,
1365 condition,
1366 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1367 LIR_OprFact::intConst(c),
1368 info));
1369 }
1370
1371
1372 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1373 append(new LIR_Op2(
1374 lir_cmp,
1375 condition,
1376 reg,
1377 LIR_OprFact::address(addr),
1378 info));
1379 }
1380
1381 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1382 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1383 append(new LIR_OpAllocObj(
1384 klass,
1385 dst,
1386 t1,
1387 t2,
1388 t3,
1389 t4,
1390 header_size,
1391 object_size,
1392 init_check,
1393 stub));
1394 }
1395
1396 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1397 append(new LIR_OpAllocArray(
1398 klass,
1399 len,
1400 dst,
1401 t1,
1402 t2,
1403 t3,
1404 t4,
1405 type,
1406 stub));
1407 }
1408
1409 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1410 append(new LIR_Op2(
1411 lir_shl,
1412 value,
1413 count,
1414 dst,
1415 tmp));
1416 }
1417
1418 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1419 append(new LIR_Op2(
1420 lir_shr,
1421 value,
1422 count,
1423 dst,
1424 tmp));
1425 }
1426
1427
1428 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1429 append(new LIR_Op2(
1430 lir_ushr,
1431 value,
1432 count,
1433 dst,
1434 tmp));
1435 }
1436
1437 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1438 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1439 left,
1440 right,
1441 dst));
1442 }
1443
1444 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1445 append(new LIR_OpLock(
1446 lir_lock,
1447 hdr,
1448 obj,
1449 lock,
1450 scratch,
1451 stub,
1452 info));
1453 }
1454
1455 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
1456 append(new LIR_OpLock(
1457 lir_unlock,
1458 hdr,
1459 obj,
1460 lock,
1461 scratch,
1462 stub,
1463 NULL));
1464 }
1465
1466
1467 void check_LIR() {
1468 // cannot do the proper checking as PRODUCT and other modes return different results
1469 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1470 }
1471
1472
1473
1474 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1475 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1476 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
1477 ciMethod* profiled_method, int profiled_bci) {
1478 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1479 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub);
1480 if (profiled_method != NULL) {
1481 c->set_profiled_method(profiled_method);
1482 c->set_profiled_bci(profiled_bci);
1483 c->set_should_profile(true);
1484 }
1485 append(c);
1486 }
1487
1488 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) {
1489 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL);
1490 if (profiled_method != NULL) {
1491 c->set_profiled_method(profiled_method);
1492 c->set_profiled_bci(profiled_bci);
1493 c->set_should_profile(true);
1494 }
1495 append(c);
1496 }
1497
1498
1499 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1500 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1501 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1502 if (profiled_method != NULL) {
1503 c->set_profiled_method(profiled_method);
1504 c->set_profiled_bci(profiled_bci);
1505 c->set_should_profile(true);
1506 }
1507 append(c);
1508 }
1509
1510
1511 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1512 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1513 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1514 }
1515
1516 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1517 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1518 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1519 }
1520
1521 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1522 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1523 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1524 }
1525
1526
1527 #ifdef PRODUCT
1528
1529 void print_LIR(BlockList* blocks) {
1530 }
1531
1532 #else
1533 // LIR_OprDesc
1534 void LIR_OprDesc::print() const {
1535 print(tty);
1536 }
1537
1538 void LIR_OprDesc::print(outputStream* out) const {
1539 if (is_illegal()) {
1540 return;
1541 }
1542
1543 out->print("[");
1544 if (is_pointer()) {
1545 pointer()->print_value_on(out);
1546 } else if (is_single_stack()) {
1547 out->print("stack:%d", single_stack_ix());
1548 } else if (is_double_stack()) {
1549 out->print("dbl_stack:%d",double_stack_ix());
1550 } else if (is_virtual()) {
1551 out->print("R%d", vreg_number());
1552 } else if (is_single_cpu()) {
1553 out->print("%s", as_register()->name());
1554 } else if (is_double_cpu()) {
1555 out->print("%s", as_register_hi()->name());
1556 out->print("%s", as_register_lo()->name());
1557 #if defined(X86)
1558 } else if (is_single_xmm()) {
1559 out->print("%s", as_xmm_float_reg()->name());
1560 } else if (is_double_xmm()) {
1561 out->print("%s", as_xmm_double_reg()->name());
1562 } else if (is_single_fpu()) {
1563 out->print("fpu%d", fpu_regnr());
1564 } else if (is_double_fpu()) {
1565 out->print("fpu%d", fpu_regnrLo());
1566 #elif defined(AARCH64)
1567 } else if (is_single_fpu()) {
1568 out->print("fpu%d", fpu_regnr());
1569 } else if (is_double_fpu()) {
1570 out->print("fpu%d", fpu_regnrLo());
1571 #elif defined(ARM)
1572 } else if (is_single_fpu()) {
1573 out->print("s%d", fpu_regnr());
1574 } else if (is_double_fpu()) {
1575 out->print("d%d", fpu_regnrLo() >> 1);
1576 #else
1577 } else if (is_single_fpu()) {
1578 out->print("%s", as_float_reg()->name());
1579 } else if (is_double_fpu()) {
1580 out->print("%s", as_double_reg()->name());
1581 #endif
1582
1583 } else if (is_illegal()) {
1584 out->print("-");
1585 } else {
1586 out->print("Unknown Operand");
1587 }
1588 if (!is_illegal()) {
1589 out->print("|%c", type_char());
1590 }
1591 if (is_register() && is_last_use()) {
1592 out->print("(last_use)");
1593 }
1594 out->print("]");
1595 }
1596
1597
1598 // LIR_Address
1599 void LIR_Const::print_value_on(outputStream* out) const {
1600 switch (type()) {
1601 case T_ADDRESS:out->print("address:%d",as_jint()); break;
1602 case T_INT: out->print("int:%d", as_jint()); break;
1603 case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break;
1604 case T_FLOAT: out->print("flt:%f", as_jfloat()); break;
1605 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break;
1606 case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject())); break;
1607 case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break;
1608 default: out->print("%3d:0x" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break;
1609 }
1610 }
1611
1612 // LIR_Address
1613 void LIR_Address::print_value_on(outputStream* out) const {
1614 out->print("Base:"); _base->print(out);
1615 if (!_index->is_illegal()) {
1616 out->print(" Index:"); _index->print(out);
1617 switch (scale()) {
1618 case times_1: break;
1619 case times_2: out->print(" * 2"); break;
1620 case times_4: out->print(" * 4"); break;
1621 case times_8: out->print(" * 8"); break;
1622 }
1623 }
1624 out->print(" Disp: " INTX_FORMAT, _disp);
1625 }
1626
1627 // debug output of block header without InstructionPrinter
1628 // (because phi functions are not necessary for LIR)
1629 static void print_block(BlockBegin* x) {
1630 // print block id
1631 BlockEnd* end = x->end();
1632 tty->print("B%d ", x->block_id());
1633
1634 // print flags
1635 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std ");
1636 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr ");
1637 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex ");
1638 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr ");
1639 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb ");
1640 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1641 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
1642
1643 // print block bci range
1644 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci()));
1645
1646 // print predecessors and successors
1647 if (x->number_of_preds() > 0) {
1648 tty->print("preds: ");
1649 for (int i = 0; i < x->number_of_preds(); i ++) {
1650 tty->print("B%d ", x->pred_at(i)->block_id());
1651 }
1652 }
1653
1654 if (x->number_of_sux() > 0) {
1655 tty->print("sux: ");
1656 for (int i = 0; i < x->number_of_sux(); i ++) {
1657 tty->print("B%d ", x->sux_at(i)->block_id());
1658 }
1659 }
1660
1661 // print exception handlers
1662 if (x->number_of_exception_handlers() > 0) {
1663 tty->print("xhandler: ");
1664 for (int i = 0; i < x->number_of_exception_handlers(); i++) {
1665 tty->print("B%d ", x->exception_handler_at(i)->block_id());
1666 }
1667 }
1668
1669 tty->cr();
1670 }
1671
1672 void print_LIR(BlockList* blocks) {
1673 tty->print_cr("LIR:");
1674 int i;
1675 for (i = 0; i < blocks->length(); i++) {
1676 BlockBegin* bb = blocks->at(i);
1677 print_block(bb);
1678 tty->print("__id_Instruction___________________________________________"); tty->cr();
1679 bb->lir()->print_instructions();
1680 }
1681 }
1682
1683 void LIR_List::print_instructions() {
1684 for (int i = 0; i < _operations.length(); i++) {
1685 _operations.at(i)->print(); tty->cr();
1686 }
1687 tty->cr();
1688 }
1689
1690 // LIR_Ops printing routines
1691 // LIR_Op
1692 void LIR_Op::print_on(outputStream* out) const {
1693 if (id() != -1 || PrintCFGToFile) {
1694 out->print("%4d ", id());
1695 } else {
1696 out->print(" ");
1697 }
1698 out->print("%s ", name());
1699 print_instr(out);
1700 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci());
1701 #ifdef ASSERT
1702 if (Verbose && _file != NULL) {
1703 out->print(" (%s:%d)", _file, _line);
1704 }
1705 #endif
1706 }
1707
1708 const char * LIR_Op::name() const {
1709 const char* s = NULL;
1710 switch(code()) {
1711 // LIR_Op0
1712 case lir_membar: s = "membar"; break;
1713 case lir_membar_acquire: s = "membar_acquire"; break;
1714 case lir_membar_release: s = "membar_release"; break;
1715 case lir_membar_loadload: s = "membar_loadload"; break;
1716 case lir_membar_storestore: s = "membar_storestore"; break;
1717 case lir_membar_loadstore: s = "membar_loadstore"; break;
1718 case lir_membar_storeload: s = "membar_storeload"; break;
1719 case lir_word_align: s = "word_align"; break;
1720 case lir_label: s = "label"; break;
1721 case lir_nop: s = "nop"; break;
1722 case lir_backwardbranch_target: s = "backbranch"; break;
1723 case lir_std_entry: s = "std_entry"; break;
1724 case lir_osr_entry: s = "osr_entry"; break;
1725 case lir_build_frame: s = "build_frm"; break;
1726 case lir_fpop_raw: s = "fpop_raw"; break;
1727 case lir_24bit_FPU: s = "24bit_FPU"; break;
1728 case lir_reset_FPU: s = "reset_FPU"; break;
1729 case lir_breakpoint: s = "breakpoint"; break;
1730 case lir_get_thread: s = "get_thread"; break;
1731 // LIR_Op1
1732 case lir_fxch: s = "fxch"; break;
1733 case lir_fld: s = "fld"; break;
1734 case lir_ffree: s = "ffree"; break;
1735 case lir_push: s = "push"; break;
1736 case lir_pop: s = "pop"; break;
1737 case lir_null_check: s = "null_check"; break;
1738 case lir_return: s = "return"; break;
1739 case lir_safepoint: s = "safepoint"; break;
1740 case lir_neg: s = "neg"; break;
1741 case lir_leal: s = "leal"; break;
1742 case lir_branch: s = "branch"; break;
1743 case lir_cond_float_branch: s = "flt_cond_br"; break;
1744 case lir_move: s = "move"; break;
1745 case lir_roundfp: s = "roundfp"; break;
1746 case lir_rtcall: s = "rtcall"; break;
1747 case lir_throw: s = "throw"; break;
1748 case lir_unwind: s = "unwind"; break;
1749 case lir_convert: s = "convert"; break;
1750 case lir_alloc_object: s = "alloc_obj"; break;
1751 case lir_monaddr: s = "mon_addr"; break;
1752 case lir_pack64: s = "pack64"; break;
1753 case lir_unpack64: s = "unpack64"; break;
1754 // LIR_Op2
1755 case lir_cmp: s = "cmp"; break;
1756 case lir_cmp_l2i: s = "cmp_l2i"; break;
1757 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1758 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1759 case lir_cmove: s = "cmove"; break;
1760 case lir_add: s = "add"; break;
1761 case lir_sub: s = "sub"; break;
1762 case lir_mul: s = "mul"; break;
1763 case lir_mul_strictfp: s = "mul_strictfp"; break;
1764 case lir_div: s = "div"; break;
1765 case lir_div_strictfp: s = "div_strictfp"; break;
1766 case lir_rem: s = "rem"; break;
1767 case lir_abs: s = "abs"; break;
1768 case lir_sqrt: s = "sqrt"; break;
1769 case lir_sin: s = "sin"; break;
1770 case lir_cos: s = "cos"; break;
1771 case lir_tan: s = "tan"; break;
1772 case lir_log: s = "log"; break;
1773 case lir_log10: s = "log10"; break;
1774 case lir_pow: s = "pow"; break;
1775 case lir_logic_and: s = "logic_and"; break;
1776 case lir_logic_or: s = "logic_or"; break;
1777 case lir_logic_xor: s = "logic_xor"; break;
1778 case lir_shl: s = "shift_left"; break;
1779 case lir_shr: s = "shift_right"; break;
1780 case lir_ushr: s = "ushift_right"; break;
1781 case lir_alloc_array: s = "alloc_array"; break;
1782 case lir_xadd: s = "xadd"; break;
1783 case lir_xchg: s = "xchg"; break;
1784 // LIR_Op3
1785 case lir_idiv: s = "idiv"; break;
1786 case lir_irem: s = "irem"; break;
1787 // LIR_OpJavaCall
1788 case lir_static_call: s = "static"; break;
1789 case lir_optvirtual_call: s = "optvirtual"; break;
1790 case lir_icvirtual_call: s = "icvirtual"; break;
1791 case lir_virtual_call: s = "virtual"; break;
1792 case lir_dynamic_call: s = "dynamic"; break;
1793 // LIR_OpArrayCopy
1794 case lir_arraycopy: s = "arraycopy"; break;
1795 // LIR_OpUpdateCRC32
1796 case lir_updatecrc32: s = "updatecrc32"; break;
1797 // LIR_OpLock
1798 case lir_lock: s = "lock"; break;
1799 case lir_unlock: s = "unlock"; break;
1800 // LIR_OpDelay
1801 case lir_delay_slot: s = "delay"; break;
1802 // LIR_OpTypeCheck
1803 case lir_instanceof: s = "instanceof"; break;
1804 case lir_checkcast: s = "checkcast"; break;
1805 case lir_store_check: s = "store_check"; break;
1806 // LIR_OpCompareAndSwap
1807 case lir_cas_long: s = "cas_long"; break;
1808 case lir_cas_obj: s = "cas_obj"; break;
1809 case lir_cas_int: s = "cas_int"; break;
1810 // LIR_OpProfileCall
1811 case lir_profile_call: s = "profile_call"; break;
1812 // LIR_OpProfileType
1813 case lir_profile_type: s = "profile_type"; break;
1814 // LIR_OpAssert
1815 #ifdef ASSERT
1816 case lir_assert: s = "assert"; break;
1817 #endif
1818 case lir_none: ShouldNotReachHere();break;
1819 default: s = "illegal_op"; break;
1820 }
1821 return s;
1822 }
1823
1824 // LIR_OpJavaCall
1825 void LIR_OpJavaCall::print_instr(outputStream* out) const {
1826 out->print("call: ");
1827 out->print("[addr: " INTPTR_FORMAT "]", p2i(address()));
1828 if (receiver()->is_valid()) {
1829 out->print(" [recv: "); receiver()->print(out); out->print("]");
1830 }
1831 if (result_opr()->is_valid()) {
1832 out->print(" [result: "); result_opr()->print(out); out->print("]");
1833 }
1834 }
1835
1836 // LIR_OpLabel
1837 void LIR_OpLabel::print_instr(outputStream* out) const {
1838 out->print("[label:" INTPTR_FORMAT "]", p2i(_label));
1839 }
1840
1841 // LIR_OpArrayCopy
1842 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
1843 src()->print(out); out->print(" ");
1844 src_pos()->print(out); out->print(" ");
1845 dst()->print(out); out->print(" ");
1846 dst_pos()->print(out); out->print(" ");
1847 length()->print(out); out->print(" ");
1848 tmp()->print(out); out->print(" ");
1849 }
1850
1851 // LIR_OpUpdateCRC32
1852 void LIR_OpUpdateCRC32::print_instr(outputStream* out) const {
1853 crc()->print(out); out->print(" ");
1854 val()->print(out); out->print(" ");
1855 result_opr()->print(out); out->print(" ");
1856 }
1857
1858 // LIR_OpCompareAndSwap
1859 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
1860 addr()->print(out); out->print(" ");
1861 cmp_value()->print(out); out->print(" ");
1862 new_value()->print(out); out->print(" ");
1863 tmp1()->print(out); out->print(" ");
1864 tmp2()->print(out); out->print(" ");
1865
1866 }
1867
1868 // LIR_Op0
1869 void LIR_Op0::print_instr(outputStream* out) const {
1870 result_opr()->print(out);
1871 }
1872
1873 // LIR_Op1
1874 const char * LIR_Op1::name() const {
1875 if (code() == lir_move) {
1876 switch (move_kind()) {
1877 case lir_move_normal:
1878 return "move";
1879 case lir_move_unaligned:
1880 return "unaligned move";
1881 case lir_move_volatile:
1882 return "volatile_move";
1883 case lir_move_wide:
1884 return "wide_move";
1885 default:
1886 ShouldNotReachHere();
1887 return "illegal_op";
1888 }
1889 } else {
1890 return LIR_Op::name();
1891 }
1892 }
1893
1894
1895 void LIR_Op1::print_instr(outputStream* out) const {
1896 _opr->print(out); out->print(" ");
1897 result_opr()->print(out); out->print(" ");
1898 print_patch_code(out, patch_code());
1899 }
1900
1901
1902 // LIR_Op1
1903 void LIR_OpRTCall::print_instr(outputStream* out) const {
1904 intx a = (intx)addr();
1905 out->print("%s", Runtime1::name_for_address(addr()));
1906 out->print(" ");
1907 tmp()->print(out);
1908 }
1909
1910 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
1911 switch(code) {
1912 case lir_patch_none: break;
1913 case lir_patch_low: out->print("[patch_low]"); break;
1914 case lir_patch_high: out->print("[patch_high]"); break;
1915 case lir_patch_normal: out->print("[patch_normal]"); break;
1916 default: ShouldNotReachHere();
1917 }
1918 }
1919
1920 // LIR_OpBranch
1921 void LIR_OpBranch::print_instr(outputStream* out) const {
1922 print_condition(out, cond()); out->print(" ");
1923 if (block() != NULL) {
1924 out->print("[B%d] ", block()->block_id());
1925 } else if (stub() != NULL) {
1926 out->print("[");
1927 stub()->print_name(out);
1928 out->print(": " INTPTR_FORMAT "]", p2i(stub()));
1929 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
1930 } else {
1931 out->print("[label:" INTPTR_FORMAT "] ", p2i(label()));
1932 }
1933 if (ublock() != NULL) {
1934 out->print("unordered: [B%d] ", ublock()->block_id());
1935 }
1936 }
1937
1938 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1939 switch(cond) {
1940 case lir_cond_equal: out->print("[EQ]"); break;
1941 case lir_cond_notEqual: out->print("[NE]"); break;
1942 case lir_cond_less: out->print("[LT]"); break;
1943 case lir_cond_lessEqual: out->print("[LE]"); break;
1944 case lir_cond_greaterEqual: out->print("[GE]"); break;
1945 case lir_cond_greater: out->print("[GT]"); break;
1946 case lir_cond_belowEqual: out->print("[BE]"); break;
1947 case lir_cond_aboveEqual: out->print("[AE]"); break;
1948 case lir_cond_always: out->print("[AL]"); break;
1949 default: out->print("[%d]",cond); break;
1950 }
1951 }
1952
1953 // LIR_OpConvert
1954 void LIR_OpConvert::print_instr(outputStream* out) const {
1955 print_bytecode(out, bytecode());
1956 in_opr()->print(out); out->print(" ");
1957 result_opr()->print(out); out->print(" ");
1958 #ifdef PPC
1959 if(tmp1()->is_valid()) {
1960 tmp1()->print(out); out->print(" ");
1961 tmp2()->print(out); out->print(" ");
1962 }
1963 #endif
1964 }
1965
1966 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
1967 switch(code) {
1968 case Bytecodes::_d2f: out->print("[d2f] "); break;
1969 case Bytecodes::_d2i: out->print("[d2i] "); break;
1970 case Bytecodes::_d2l: out->print("[d2l] "); break;
1971 case Bytecodes::_f2d: out->print("[f2d] "); break;
1972 case Bytecodes::_f2i: out->print("[f2i] "); break;
1973 case Bytecodes::_f2l: out->print("[f2l] "); break;
1974 case Bytecodes::_i2b: out->print("[i2b] "); break;
1975 case Bytecodes::_i2c: out->print("[i2c] "); break;
1976 case Bytecodes::_i2d: out->print("[i2d] "); break;
1977 case Bytecodes::_i2f: out->print("[i2f] "); break;
1978 case Bytecodes::_i2l: out->print("[i2l] "); break;
1979 case Bytecodes::_i2s: out->print("[i2s] "); break;
1980 case Bytecodes::_l2i: out->print("[l2i] "); break;
1981 case Bytecodes::_l2f: out->print("[l2f] "); break;
1982 case Bytecodes::_l2d: out->print("[l2d] "); break;
1983 default:
1984 out->print("[?%d]",code);
1985 break;
1986 }
1987 }
1988
1989 void LIR_OpAllocObj::print_instr(outputStream* out) const {
1990 klass()->print(out); out->print(" ");
1991 obj()->print(out); out->print(" ");
1992 tmp1()->print(out); out->print(" ");
1993 tmp2()->print(out); out->print(" ");
1994 tmp3()->print(out); out->print(" ");
1995 tmp4()->print(out); out->print(" ");
1996 out->print("[hdr:%d]", header_size()); out->print(" ");
1997 out->print("[obj:%d]", object_size()); out->print(" ");
1998 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
1999 }
2000
2001 void LIR_OpRoundFP::print_instr(outputStream* out) const {
2002 _opr->print(out); out->print(" ");
2003 tmp()->print(out); out->print(" ");
2004 result_opr()->print(out); out->print(" ");
2005 }
2006
2007 // LIR_Op2
2008 void LIR_Op2::print_instr(outputStream* out) const {
2009 if (code() == lir_cmove) {
2010 print_condition(out, condition()); out->print(" ");
2011 }
2012 in_opr1()->print(out); out->print(" ");
2013 in_opr2()->print(out); out->print(" ");
2014 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); }
2015 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); }
2016 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); }
2017 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); }
2018 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); }
2019 result_opr()->print(out);
2020 }
2021
2022 void LIR_OpAllocArray::print_instr(outputStream* out) const {
2023 klass()->print(out); out->print(" ");
2024 len()->print(out); out->print(" ");
2025 obj()->print(out); out->print(" ");
2026 tmp1()->print(out); out->print(" ");
2027 tmp2()->print(out); out->print(" ");
2028 tmp3()->print(out); out->print(" ");
2029 tmp4()->print(out); out->print(" ");
2030 out->print("[type:0x%x]", type()); out->print(" ");
2031 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2032 }
2033
2034
2035 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
2036 object()->print(out); out->print(" ");
2037 if (code() == lir_store_check) {
2038 array()->print(out); out->print(" ");
2039 }
2040 if (code() != lir_store_check) {
2041 klass()->print_name_on(out); out->print(" ");
2042 if (fast_check()) out->print("fast_check ");
2043 }
2044 tmp1()->print(out); out->print(" ");
2045 tmp2()->print(out); out->print(" ");
2046 tmp3()->print(out); out->print(" ");
2047 result_opr()->print(out); out->print(" ");
2048 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
2049 }
2050
2051
2052 // LIR_Op3
2053 void LIR_Op3::print_instr(outputStream* out) const {
2054 in_opr1()->print(out); out->print(" ");
2055 in_opr2()->print(out); out->print(" ");
2056 in_opr3()->print(out); out->print(" ");
2057 result_opr()->print(out);
2058 }
2059
2060
2061 void LIR_OpLock::print_instr(outputStream* out) const {
2062 hdr_opr()->print(out); out->print(" ");
2063 obj_opr()->print(out); out->print(" ");
2064 lock_opr()->print(out); out->print(" ");
2065 if (_scratch->is_valid()) {
2066 _scratch->print(out); out->print(" ");
2067 }
2068 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2069 }
2070
2071 #ifdef ASSERT
2072 void LIR_OpAssert::print_instr(outputStream* out) const {
2073 print_condition(out, condition()); out->print(" ");
2074 in_opr1()->print(out); out->print(" ");
2075 in_opr2()->print(out); out->print(", \"");
2076 out->print("%s", msg()); out->print("\"");
2077 }
2078 #endif
2079
2080
2081 void LIR_OpDelay::print_instr(outputStream* out) const {
2082 _op->print_on(out);
2083 }
2084
2085
2086 // LIR_OpProfileCall
2087 void LIR_OpProfileCall::print_instr(outputStream* out) const {
2088 profiled_method()->name()->print_symbol_on(out);
2089 out->print(".");
2090 profiled_method()->holder()->name()->print_symbol_on(out);
2091 out->print(" @ %d ", profiled_bci());
2092 mdo()->print(out); out->print(" ");
2093 recv()->print(out); out->print(" ");
2094 tmp1()->print(out); out->print(" ");
2095 }
2096
2097 // LIR_OpProfileType
2098 void LIR_OpProfileType::print_instr(outputStream* out) const {
2099 out->print("exact = ");
2100 if (exact_klass() == NULL) {
2101 out->print("unknown");
2102 } else {
2103 exact_klass()->print_name_on(out);
2104 }
2105 out->print(" current = "); ciTypeEntries::print_ciklass(out, current_klass());
2106 out->print(" ");
2107 mdp()->print(out); out->print(" ");
2108 obj()->print(out); out->print(" ");
2109 tmp()->print(out); out->print(" ");
2110 }
2111
2112 #endif // PRODUCT
2113
2114 // Implementation of LIR_InsertionBuffer
2115
2116 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
2117 assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
2118
2119 int i = number_of_insertion_points() - 1;
2120 if (i < 0 || index_at(i) < index) {
2121 append_new(index, 1);
2122 } else {
2123 assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
2124 assert(count_at(i) > 0, "check");
2125 set_count_at(i, count_at(i) + 1);
2126 }
2127 _ops.push(op);
2128
2129 DEBUG_ONLY(verify());
2130 }
2131
2132 #ifdef ASSERT
2133 void LIR_InsertionBuffer::verify() {
2134 int sum = 0;
2135 int prev_idx = -1;
2136
2137 for (int i = 0; i < number_of_insertion_points(); i++) {
2138 assert(prev_idx < index_at(i), "index must be ordered ascending");
2139 sum += count_at(i);
2140 }
2141 assert(sum == number_of_ops(), "wrong total sum");
2142 }
2143 #endif