1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableModRefBS.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc/g1/g1CollectedHeap.inline.hpp"
42 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
59 // -----------------Table 4.5 -------------------- //
60 16, 32, 64, // EVEX_FV(0)
61 4, 4, 4, // EVEX_FV(1) - with Evex.b
62 16, 32, 64, // EVEX_FV(2) - with Evex.w
63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
64 8, 16, 32, // EVEX_HV(0)
65 4, 4, 4, // EVEX_HV(1) - with Evex.b
66 // -----------------Table 4.6 -------------------- //
67 16, 32, 64, // EVEX_FVM(0)
68 1, 1, 1, // EVEX_T1S(0)
69 2, 2, 2, // EVEX_T1S(1)
70 4, 4, 4, // EVEX_T1S(2)
71 8, 8, 8, // EVEX_T1S(3)
72 4, 4, 4, // EVEX_T1F(0)
73 8, 8, 8, // EVEX_T1F(1)
74 8, 8, 8, // EVEX_T2(0)
75 0, 16, 16, // EVEX_T2(1)
76 0, 16, 16, // EVEX_T4(0)
77 0, 0, 32, // EVEX_T4(1)
78 0, 0, 32, // EVEX_T8(0)
79 8, 16, 32, // EVEX_HVM(0)
80 4, 8, 16, // EVEX_QVM(0)
81 2, 4, 8, // EVEX_OVM(0)
82 16, 16, 16, // EVEX_M128(0)
83 8, 32, 64, // EVEX_DUP(0)
84 0, 0, 0 // EVEX_NTUP
85 };
86
87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
88 _is_lval = false;
89 _target = target;
90 switch (rtype) {
91 case relocInfo::oop_type:
92 case relocInfo::metadata_type:
93 // Oops are a special case. Normally they would be their own section
94 // but in cases like icBuffer they are literals in the code stream that
95 // we don't have a section for. We use none so that we get a literal address
96 // which is always patchable.
97 break;
98 case relocInfo::external_word_type:
99 _rspec = external_word_Relocation::spec(target);
100 break;
101 case relocInfo::internal_word_type:
102 _rspec = internal_word_Relocation::spec(target);
103 break;
104 case relocInfo::opt_virtual_call_type:
105 _rspec = opt_virtual_call_Relocation::spec();
106 break;
107 case relocInfo::static_call_type:
108 _rspec = static_call_Relocation::spec();
109 break;
110 case relocInfo::runtime_call_type:
111 _rspec = runtime_call_Relocation::spec();
112 break;
113 case relocInfo::poll_type:
114 case relocInfo::poll_return_type:
115 _rspec = Relocation::spec_simple(rtype);
116 break;
117 case relocInfo::none:
118 break;
119 default:
120 ShouldNotReachHere();
121 break;
122 }
123 }
124
125 // Implementation of Address
126
127 #ifdef _LP64
128
129 Address Address::make_array(ArrayAddress adr) {
130 // Not implementable on 64bit machines
131 // Should have been handled higher up the call chain.
132 ShouldNotReachHere();
133 return Address();
134 }
135
136 // exceedingly dangerous constructor
137 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
138 _base = noreg;
139 _index = noreg;
140 _scale = no_scale;
141 _disp = disp;
142 switch (rtype) {
143 case relocInfo::external_word_type:
144 _rspec = external_word_Relocation::spec(loc);
145 break;
146 case relocInfo::internal_word_type:
147 _rspec = internal_word_Relocation::spec(loc);
148 break;
149 case relocInfo::runtime_call_type:
150 // HMM
151 _rspec = runtime_call_Relocation::spec();
152 break;
153 case relocInfo::poll_type:
154 case relocInfo::poll_return_type:
155 _rspec = Relocation::spec_simple(rtype);
156 break;
157 case relocInfo::none:
158 break;
159 default:
160 ShouldNotReachHere();
161 }
162 }
163 #else // LP64
164
165 Address Address::make_array(ArrayAddress adr) {
166 AddressLiteral base = adr.base();
167 Address index = adr.index();
168 assert(index._disp == 0, "must not have disp"); // maybe it can?
169 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
170 array._rspec = base._rspec;
171 return array;
172 }
173
174 // exceedingly dangerous constructor
175 Address::Address(address loc, RelocationHolder spec) {
176 _base = noreg;
177 _index = noreg;
178 _scale = no_scale;
179 _disp = (intptr_t) loc;
180 _rspec = spec;
181 }
182
183 #endif // _LP64
184
185
186
187 // Convert the raw encoding form into the form expected by the constructor for
188 // Address. An index of 4 (rsp) corresponds to having no index, so convert
189 // that to noreg for the Address constructor.
190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
191 RelocationHolder rspec;
192 if (disp_reloc != relocInfo::none) {
193 rspec = Relocation::spec_simple(disp_reloc);
194 }
195 bool valid_index = index != rsp->encoding();
196 if (valid_index) {
197 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
198 madr._rspec = rspec;
199 return madr;
200 } else {
201 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
202 madr._rspec = rspec;
203 return madr;
204 }
205 }
206
207 // Implementation of Assembler
208
209 int AbstractAssembler::code_fill_byte() {
210 return (u_char)'\xF4'; // hlt
211 }
212
213 // make this go away someday
214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
215 if (rtype == relocInfo::none)
216 emit_int32(data);
217 else
218 emit_data(data, Relocation::spec_simple(rtype), format);
219 }
220
221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
222 assert(imm_operand == 0, "default format must be immediate in this file");
223 assert(inst_mark() != NULL, "must be inside InstructionMark");
224 if (rspec.type() != relocInfo::none) {
225 #ifdef ASSERT
226 check_relocation(rspec, format);
227 #endif
228 // Do not use AbstractAssembler::relocate, which is not intended for
229 // embedded words. Instead, relocate to the enclosing instruction.
230
231 // hack. call32 is too wide for mask so use disp32
232 if (format == call32_operand)
233 code_section()->relocate(inst_mark(), rspec, disp32_operand);
234 else
235 code_section()->relocate(inst_mark(), rspec, format);
236 }
237 emit_int32(data);
238 }
239
240 static int encode(Register r) {
241 int enc = r->encoding();
242 if (enc >= 8) {
243 enc -= 8;
244 }
245 return enc;
246 }
247
248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
249 assert(dst->has_byte_register(), "must have byte register");
250 assert(isByte(op1) && isByte(op2), "wrong opcode");
251 assert(isByte(imm8), "not a byte");
252 assert((op1 & 0x01) == 0, "should be 8bit operation");
253 emit_int8(op1);
254 emit_int8(op2 | encode(dst));
255 emit_int8(imm8);
256 }
257
258
259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
260 assert(isByte(op1) && isByte(op2), "wrong opcode");
261 assert((op1 & 0x01) == 1, "should be 32bit operation");
262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
263 if (is8bit(imm32)) {
264 emit_int8(op1 | 0x02); // set sign bit
265 emit_int8(op2 | encode(dst));
266 emit_int8(imm32 & 0xFF);
267 } else {
268 emit_int8(op1);
269 emit_int8(op2 | encode(dst));
270 emit_int32(imm32);
271 }
272 }
273
274 // Force generation of a 4 byte immediate value even if it fits into 8bit
275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
276 assert(isByte(op1) && isByte(op2), "wrong opcode");
277 assert((op1 & 0x01) == 1, "should be 32bit operation");
278 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
279 emit_int8(op1);
280 emit_int8(op2 | encode(dst));
281 emit_int32(imm32);
282 }
283
284 // immediate-to-memory forms
285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
286 assert((op1 & 0x01) == 1, "should be 32bit operation");
287 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
288 if (is8bit(imm32)) {
289 emit_int8(op1 | 0x02); // set sign bit
290 emit_operand(rm, adr, 1);
291 emit_int8(imm32 & 0xFF);
292 } else {
293 emit_int8(op1);
294 emit_operand(rm, adr, 4);
295 emit_int32(imm32);
296 }
297 }
298
299
300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
301 assert(isByte(op1) && isByte(op2), "wrong opcode");
302 emit_int8(op1);
303 emit_int8(op2 | encode(dst) << 3 | encode(src));
304 }
305
306
307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
309 int mod_idx = 0;
310 // We will test if the displacement fits the compressed format and if so
311 // apply the compression to the displacment iff the result is8bit.
312 if (VM_Version::supports_evex() && is_evex_inst) {
313 switch (cur_tuple_type) {
314 case EVEX_FV:
315 if ((cur_encoding & VEX_W) == VEX_W) {
316 mod_idx += 2 + ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
317 } else {
318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
319 }
320 break;
321
322 case EVEX_HV:
323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
324 break;
325
326 case EVEX_FVM:
327 break;
328
329 case EVEX_T1S:
330 switch (in_size_in_bits) {
331 case EVEX_8bit:
332 break;
333
334 case EVEX_16bit:
335 mod_idx = 1;
336 break;
337
338 case EVEX_32bit:
339 mod_idx = 2;
340 break;
341
342 case EVEX_64bit:
343 mod_idx = 3;
344 break;
345 }
346 break;
347
348 case EVEX_T1F:
349 case EVEX_T2:
350 case EVEX_T4:
351 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
352 break;
353
354 case EVEX_T8:
355 break;
356
357 case EVEX_HVM:
358 break;
359
360 case EVEX_QVM:
361 break;
362
363 case EVEX_OVM:
364 break;
365
366 case EVEX_M128:
367 break;
368
369 case EVEX_DUP:
370 break;
371
372 default:
373 assert(0, "no valid evex tuple_table entry");
374 break;
375 }
376
377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
379 if ((disp % disp_factor) == 0) {
380 int new_disp = disp / disp_factor;
381 if ((-0x80 <= new_disp && new_disp < 0x80)) {
382 disp = new_disp;
383 }
384 } else {
385 return false;
386 }
387 }
388 }
389 return (-0x80 <= disp && disp < 0x80);
390 }
391
392
393 bool Assembler::emit_compressed_disp_byte(int &disp) {
394 int mod_idx = 0;
395 // We will test if the displacement fits the compressed format and if so
396 // apply the compression to the displacment iff the result is8bit.
397 if (VM_Version::supports_evex() && is_evex_instruction) {
398 switch (tuple_type) {
399 case EVEX_FV:
400 if ((evex_encoding & VEX_W) == VEX_W) {
401 mod_idx += 2 + ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
402 } else {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
404 }
405 break;
406
407 case EVEX_HV:
408 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
409 break;
410
411 case EVEX_FVM:
412 break;
413
414 case EVEX_T1S:
415 switch (input_size_in_bits) {
416 case EVEX_8bit:
417 break;
418
419 case EVEX_16bit:
420 mod_idx = 1;
421 break;
422
423 case EVEX_32bit:
424 mod_idx = 2;
425 break;
426
427 case EVEX_64bit:
428 mod_idx = 3;
429 break;
430 }
431 break;
432
433 case EVEX_T1F:
434 case EVEX_T2:
435 case EVEX_T4:
436 mod_idx = (input_size_in_bits == EVEX_64bit) ? 1 : 0;
437 break;
438
439 case EVEX_T8:
440 break;
441
442 case EVEX_HVM:
443 break;
444
445 case EVEX_QVM:
446 break;
447
448 case EVEX_OVM:
449 break;
450
451 case EVEX_M128:
452 break;
453
454 case EVEX_DUP:
455 break;
456
457 default:
458 assert(0, "no valid evex tuple_table entry");
459 break;
460 }
461
462 if (avx_vector_len >= AVX_128bit && avx_vector_len <= AVX_512bit) {
463 int disp_factor = tuple_table[tuple_type + mod_idx][avx_vector_len];
464 if ((disp % disp_factor) == 0) {
465 int new_disp = disp / disp_factor;
466 if (is8bit(new_disp)) {
467 disp = new_disp;
468 }
469 } else {
470 return false;
471 }
472 }
473 }
474 return is8bit(disp);
475 }
476
477
478 void Assembler::emit_operand(Register reg, Register base, Register index,
479 Address::ScaleFactor scale, int disp,
480 RelocationHolder const& rspec,
481 int rip_relative_correction) {
482 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
483
484 // Encode the registers as needed in the fields they are used in
485
486 int regenc = encode(reg) << 3;
487 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
488 int baseenc = base->is_valid() ? encode(base) : 0;
489
490 if (base->is_valid()) {
491 if (index->is_valid()) {
492 assert(scale != Address::no_scale, "inconsistent address");
493 // [base + index*scale + disp]
494 if (disp == 0 && rtype == relocInfo::none &&
495 base != rbp LP64_ONLY(&& base != r13)) {
496 // [base + index*scale]
497 // [00 reg 100][ss index base]
498 assert(index != rsp, "illegal addressing mode");
499 emit_int8(0x04 | regenc);
500 emit_int8(scale << 6 | indexenc | baseenc);
501 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
502 // [base + index*scale + imm8]
503 // [01 reg 100][ss index base] imm8
504 assert(index != rsp, "illegal addressing mode");
505 emit_int8(0x44 | regenc);
506 emit_int8(scale << 6 | indexenc | baseenc);
507 emit_int8(disp & 0xFF);
508 } else {
509 // [base + index*scale + disp32]
510 // [10 reg 100][ss index base] disp32
511 assert(index != rsp, "illegal addressing mode");
512 emit_int8(0x84 | regenc);
513 emit_int8(scale << 6 | indexenc | baseenc);
514 emit_data(disp, rspec, disp32_operand);
515 }
516 } else if (base == rsp LP64_ONLY(|| base == r12)) {
517 // [rsp + disp]
518 if (disp == 0 && rtype == relocInfo::none) {
519 // [rsp]
520 // [00 reg 100][00 100 100]
521 emit_int8(0x04 | regenc);
522 emit_int8(0x24);
523 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
524 // [rsp + imm8]
525 // [01 reg 100][00 100 100] disp8
526 emit_int8(0x44 | regenc);
527 emit_int8(0x24);
528 emit_int8(disp & 0xFF);
529 } else {
530 // [rsp + imm32]
531 // [10 reg 100][00 100 100] disp32
532 emit_int8(0x84 | regenc);
533 emit_int8(0x24);
534 emit_data(disp, rspec, disp32_operand);
535 }
536 } else {
537 // [base + disp]
538 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
539 if (disp == 0 && rtype == relocInfo::none &&
540 base != rbp LP64_ONLY(&& base != r13)) {
541 // [base]
542 // [00 reg base]
543 emit_int8(0x00 | regenc | baseenc);
544 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
545 // [base + disp8]
546 // [01 reg base] disp8
547 emit_int8(0x40 | regenc | baseenc);
548 emit_int8(disp & 0xFF);
549 } else {
550 // [base + disp32]
551 // [10 reg base] disp32
552 emit_int8(0x80 | regenc | baseenc);
553 emit_data(disp, rspec, disp32_operand);
554 }
555 }
556 } else {
557 if (index->is_valid()) {
558 assert(scale != Address::no_scale, "inconsistent address");
559 // [index*scale + disp]
560 // [00 reg 100][ss index 101] disp32
561 assert(index != rsp, "illegal addressing mode");
562 emit_int8(0x04 | regenc);
563 emit_int8(scale << 6 | indexenc | 0x05);
564 emit_data(disp, rspec, disp32_operand);
565 } else if (rtype != relocInfo::none ) {
566 // [disp] (64bit) RIP-RELATIVE (32bit) abs
567 // [00 000 101] disp32
568
569 emit_int8(0x05 | regenc);
570 // Note that the RIP-rel. correction applies to the generated
571 // disp field, but _not_ to the target address in the rspec.
572
573 // disp was created by converting the target address minus the pc
574 // at the start of the instruction. That needs more correction here.
575 // intptr_t disp = target - next_ip;
576 assert(inst_mark() != NULL, "must be inside InstructionMark");
577 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
578 int64_t adjusted = disp;
579 // Do rip-rel adjustment for 64bit
580 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
581 assert(is_simm32(adjusted),
582 "must be 32bit offset (RIP relative address)");
583 emit_data((int32_t) adjusted, rspec, disp32_operand);
584
585 } else {
586 // 32bit never did this, did everything as the rip-rel/disp code above
587 // [disp] ABSOLUTE
588 // [00 reg 100][00 100 101] disp32
589 emit_int8(0x04 | regenc);
590 emit_int8(0x25);
591 emit_data(disp, rspec, disp32_operand);
592 }
593 }
594 is_evex_instruction = false;
595 }
596
597 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
598 Address::ScaleFactor scale, int disp,
599 RelocationHolder const& rspec) {
600 if (UseAVX > 2) {
601 int xreg_enc = reg->encoding();
602 if (xreg_enc > 15) {
603 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
604 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
605 return;
606 }
607 }
608 emit_operand((Register)reg, base, index, scale, disp, rspec);
609 }
610
611 // Secret local extension to Assembler::WhichOperand:
612 #define end_pc_operand (_WhichOperand_limit)
613
614 address Assembler::locate_operand(address inst, WhichOperand which) {
615 // Decode the given instruction, and return the address of
616 // an embedded 32-bit operand word.
617
618 // If "which" is disp32_operand, selects the displacement portion
619 // of an effective address specifier.
620 // If "which" is imm64_operand, selects the trailing immediate constant.
621 // If "which" is call32_operand, selects the displacement of a call or jump.
622 // Caller is responsible for ensuring that there is such an operand,
623 // and that it is 32/64 bits wide.
624
625 // If "which" is end_pc_operand, find the end of the instruction.
626
627 address ip = inst;
628 bool is_64bit = false;
629
630 debug_only(bool has_disp32 = false);
631 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
632
633 again_after_prefix:
634 switch (0xFF & *ip++) {
635
636 // These convenience macros generate groups of "case" labels for the switch.
637 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
638 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
639 case (x)+4: case (x)+5: case (x)+6: case (x)+7
640 #define REP16(x) REP8((x)+0): \
641 case REP8((x)+8)
642
643 case CS_segment:
644 case SS_segment:
645 case DS_segment:
646 case ES_segment:
647 case FS_segment:
648 case GS_segment:
649 // Seems dubious
650 LP64_ONLY(assert(false, "shouldn't have that prefix"));
651 assert(ip == inst+1, "only one prefix allowed");
652 goto again_after_prefix;
653
654 case 0x67:
655 case REX:
656 case REX_B:
657 case REX_X:
658 case REX_XB:
659 case REX_R:
660 case REX_RB:
661 case REX_RX:
662 case REX_RXB:
663 NOT_LP64(assert(false, "64bit prefixes"));
664 goto again_after_prefix;
665
666 case REX_W:
667 case REX_WB:
668 case REX_WX:
669 case REX_WXB:
670 case REX_WR:
671 case REX_WRB:
672 case REX_WRX:
673 case REX_WRXB:
674 NOT_LP64(assert(false, "64bit prefixes"));
675 is_64bit = true;
676 goto again_after_prefix;
677
678 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
679 case 0x88: // movb a, r
680 case 0x89: // movl a, r
681 case 0x8A: // movb r, a
682 case 0x8B: // movl r, a
683 case 0x8F: // popl a
684 debug_only(has_disp32 = true);
685 break;
686
687 case 0x68: // pushq #32
688 if (which == end_pc_operand) {
689 return ip + 4;
690 }
691 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
692 return ip; // not produced by emit_operand
693
694 case 0x66: // movw ... (size prefix)
695 again_after_size_prefix2:
696 switch (0xFF & *ip++) {
697 case REX:
698 case REX_B:
699 case REX_X:
700 case REX_XB:
701 case REX_R:
702 case REX_RB:
703 case REX_RX:
704 case REX_RXB:
705 case REX_W:
706 case REX_WB:
707 case REX_WX:
708 case REX_WXB:
709 case REX_WR:
710 case REX_WRB:
711 case REX_WRX:
712 case REX_WRXB:
713 NOT_LP64(assert(false, "64bit prefix found"));
714 goto again_after_size_prefix2;
715 case 0x8B: // movw r, a
716 case 0x89: // movw a, r
717 debug_only(has_disp32 = true);
718 break;
719 case 0xC7: // movw a, #16
720 debug_only(has_disp32 = true);
721 tail_size = 2; // the imm16
722 break;
723 case 0x0F: // several SSE/SSE2 variants
724 ip--; // reparse the 0x0F
725 goto again_after_prefix;
726 default:
727 ShouldNotReachHere();
728 }
729 break;
730
731 case REP8(0xB8): // movl/q r, #32/#64(oop?)
732 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
733 // these asserts are somewhat nonsensical
734 #ifndef _LP64
735 assert(which == imm_operand || which == disp32_operand,
736 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)));
737 #else
738 assert((which == call32_operand || which == imm_operand) && is_64bit ||
739 which == narrow_oop_operand && !is_64bit,
740 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)));
741 #endif // _LP64
742 return ip;
743
744 case 0x69: // imul r, a, #32
745 case 0xC7: // movl a, #32(oop?)
746 tail_size = 4;
747 debug_only(has_disp32 = true); // has both kinds of operands!
748 break;
749
750 case 0x0F: // movx..., etc.
751 switch (0xFF & *ip++) {
752 case 0x3A: // pcmpestri
753 tail_size = 1;
754 case 0x38: // ptest, pmovzxbw
755 ip++; // skip opcode
756 debug_only(has_disp32 = true); // has both kinds of operands!
757 break;
758
759 case 0x70: // pshufd r, r/a, #8
760 debug_only(has_disp32 = true); // has both kinds of operands!
761 case 0x73: // psrldq r, #8
762 tail_size = 1;
763 break;
764
765 case 0x12: // movlps
766 case 0x28: // movaps
767 case 0x2E: // ucomiss
768 case 0x2F: // comiss
769 case 0x54: // andps
770 case 0x55: // andnps
771 case 0x56: // orps
772 case 0x57: // xorps
773 case 0x6E: // movd
774 case 0x7E: // movd
775 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
776 debug_only(has_disp32 = true);
777 break;
778
779 case 0xAD: // shrd r, a, %cl
780 case 0xAF: // imul r, a
781 case 0xBE: // movsbl r, a (movsxb)
782 case 0xBF: // movswl r, a (movsxw)
783 case 0xB6: // movzbl r, a (movzxb)
784 case 0xB7: // movzwl r, a (movzxw)
785 case REP16(0x40): // cmovl cc, r, a
786 case 0xB0: // cmpxchgb
787 case 0xB1: // cmpxchg
788 case 0xC1: // xaddl
789 case 0xC7: // cmpxchg8
790 case REP16(0x90): // setcc a
791 debug_only(has_disp32 = true);
792 // fall out of the switch to decode the address
793 break;
794
795 case 0xC4: // pinsrw r, a, #8
796 debug_only(has_disp32 = true);
797 case 0xC5: // pextrw r, r, #8
798 tail_size = 1; // the imm8
799 break;
800
801 case 0xAC: // shrd r, a, #8
802 debug_only(has_disp32 = true);
803 tail_size = 1; // the imm8
804 break;
805
806 case REP16(0x80): // jcc rdisp32
807 if (which == end_pc_operand) return ip + 4;
808 assert(which == call32_operand, "jcc has no disp32 or imm");
809 return ip;
810 default:
811 ShouldNotReachHere();
812 }
813 break;
814
815 case 0x81: // addl a, #32; addl r, #32
816 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
817 // on 32bit in the case of cmpl, the imm might be an oop
818 tail_size = 4;
819 debug_only(has_disp32 = true); // has both kinds of operands!
820 break;
821
822 case 0x83: // addl a, #8; addl r, #8
823 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
824 debug_only(has_disp32 = true); // has both kinds of operands!
825 tail_size = 1;
826 break;
827
828 case 0x9B:
829 switch (0xFF & *ip++) {
830 case 0xD9: // fnstcw a
831 debug_only(has_disp32 = true);
832 break;
833 default:
834 ShouldNotReachHere();
835 }
836 break;
837
838 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
839 case REP4(0x10): // adc...
840 case REP4(0x20): // and...
841 case REP4(0x30): // xor...
842 case REP4(0x08): // or...
843 case REP4(0x18): // sbb...
844 case REP4(0x28): // sub...
845 case 0xF7: // mull a
846 case 0x8D: // lea r, a
847 case 0x87: // xchg r, a
848 case REP4(0x38): // cmp...
849 case 0x85: // test r, a
850 debug_only(has_disp32 = true); // has both kinds of operands!
851 break;
852
853 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
854 case 0xC6: // movb a, #8
855 case 0x80: // cmpb a, #8
856 case 0x6B: // imul r, a, #8
857 debug_only(has_disp32 = true); // has both kinds of operands!
858 tail_size = 1; // the imm8
859 break;
860
861 case 0xC4: // VEX_3bytes
862 case 0xC5: // VEX_2bytes
863 assert((UseAVX > 0), "shouldn't have VEX prefix");
864 assert(ip == inst+1, "no prefixes allowed");
865 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
866 // but they have prefix 0x0F and processed when 0x0F processed above.
867 //
868 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
869 // instructions (these instructions are not supported in 64-bit mode).
870 // To distinguish them bits [7:6] are set in the VEX second byte since
871 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
872 // those VEX bits REX and vvvv bits are inverted.
873 //
874 // Fortunately C2 doesn't generate these instructions so we don't need
875 // to check for them in product version.
876
877 // Check second byte
878 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
879
880 // First byte
881 if ((0xFF & *inst) == VEX_3bytes) {
882 ip++; // third byte
883 is_64bit = ((VEX_W & *ip) == VEX_W);
884 }
885 ip++; // opcode
886 // To find the end of instruction (which == end_pc_operand).
887 switch (0xFF & *ip) {
888 case 0x61: // pcmpestri r, r/a, #8
889 case 0x70: // pshufd r, r/a, #8
890 case 0x73: // psrldq r, #8
891 tail_size = 1; // the imm8
892 break;
893 default:
894 break;
895 }
896 ip++; // skip opcode
897 debug_only(has_disp32 = true); // has both kinds of operands!
898 break;
899
900 case 0x62: // EVEX_4bytes
901 assert((UseAVX > 0), "shouldn't have EVEX prefix");
902 assert(ip == inst+1, "no prefixes allowed");
903 // no EVEX collisions, all instructions that have 0x62 opcodes
904 // have EVEX versions and are subopcodes of 0x66
905 ip++; // skip P0 and exmaine W in P1
906 is_64bit = ((VEX_W & *ip) == VEX_W);
907 ip++; // move to P2
908 ip++; // skip P2, move to opcode
909 // To find the end of instruction (which == end_pc_operand).
910 switch (0xFF & *ip) {
911 case 0x61: // pcmpestri r, r/a, #8
912 case 0x70: // pshufd r, r/a, #8
913 case 0x73: // psrldq r, #8
914 tail_size = 1; // the imm8
915 break;
916 default:
917 break;
918 }
919 ip++; // skip opcode
920 debug_only(has_disp32 = true); // has both kinds of operands!
921 break;
922
923 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
924 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
925 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
926 case 0xDD: // fld_d a; fst_d a; fstp_d a
927 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
928 case 0xDF: // fild_d a; fistp_d a
929 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
930 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
931 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
932 debug_only(has_disp32 = true);
933 break;
934
935 case 0xE8: // call rdisp32
936 case 0xE9: // jmp rdisp32
937 if (which == end_pc_operand) return ip + 4;
938 assert(which == call32_operand, "call has no disp32 or imm");
939 return ip;
940
941 case 0xF0: // Lock
942 assert(os::is_MP(), "only on MP");
943 goto again_after_prefix;
944
945 case 0xF3: // For SSE
946 case 0xF2: // For SSE2
947 switch (0xFF & *ip++) {
948 case REX:
949 case REX_B:
950 case REX_X:
951 case REX_XB:
952 case REX_R:
953 case REX_RB:
954 case REX_RX:
955 case REX_RXB:
956 case REX_W:
957 case REX_WB:
958 case REX_WX:
959 case REX_WXB:
960 case REX_WR:
961 case REX_WRB:
962 case REX_WRX:
963 case REX_WRXB:
964 NOT_LP64(assert(false, "found 64bit prefix"));
965 ip++;
966 default:
967 ip++;
968 }
969 debug_only(has_disp32 = true); // has both kinds of operands!
970 break;
971
972 default:
973 ShouldNotReachHere();
974
975 #undef REP8
976 #undef REP16
977 }
978
979 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
980 #ifdef _LP64
981 assert(which != imm_operand, "instruction is not a movq reg, imm64");
982 #else
983 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
984 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
985 #endif // LP64
986 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
987
988 // parse the output of emit_operand
989 int op2 = 0xFF & *ip++;
990 int base = op2 & 0x07;
991 int op3 = -1;
992 const int b100 = 4;
993 const int b101 = 5;
994 if (base == b100 && (op2 >> 6) != 3) {
995 op3 = 0xFF & *ip++;
996 base = op3 & 0x07; // refetch the base
997 }
998 // now ip points at the disp (if any)
999
1000 switch (op2 >> 6) {
1001 case 0:
1002 // [00 reg 100][ss index base]
1003 // [00 reg 100][00 100 esp]
1004 // [00 reg base]
1005 // [00 reg 100][ss index 101][disp32]
1006 // [00 reg 101] [disp32]
1007
1008 if (base == b101) {
1009 if (which == disp32_operand)
1010 return ip; // caller wants the disp32
1011 ip += 4; // skip the disp32
1012 }
1013 break;
1014
1015 case 1:
1016 // [01 reg 100][ss index base][disp8]
1017 // [01 reg 100][00 100 esp][disp8]
1018 // [01 reg base] [disp8]
1019 ip += 1; // skip the disp8
1020 break;
1021
1022 case 2:
1023 // [10 reg 100][ss index base][disp32]
1024 // [10 reg 100][00 100 esp][disp32]
1025 // [10 reg base] [disp32]
1026 if (which == disp32_operand)
1027 return ip; // caller wants the disp32
1028 ip += 4; // skip the disp32
1029 break;
1030
1031 case 3:
1032 // [11 reg base] (not a memory addressing mode)
1033 break;
1034 }
1035
1036 if (which == end_pc_operand) {
1037 return ip + tail_size;
1038 }
1039
1040 #ifdef _LP64
1041 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1042 #else
1043 assert(which == imm_operand, "instruction has only an imm field");
1044 #endif // LP64
1045 return ip;
1046 }
1047
1048 address Assembler::locate_next_instruction(address inst) {
1049 // Secretly share code with locate_operand:
1050 return locate_operand(inst, end_pc_operand);
1051 }
1052
1053
1054 #ifdef ASSERT
1055 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1056 address inst = inst_mark();
1057 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1058 address opnd;
1059
1060 Relocation* r = rspec.reloc();
1061 if (r->type() == relocInfo::none) {
1062 return;
1063 } else if (r->is_call() || format == call32_operand) {
1064 // assert(format == imm32_operand, "cannot specify a nonzero format");
1065 opnd = locate_operand(inst, call32_operand);
1066 } else if (r->is_data()) {
1067 assert(format == imm_operand || format == disp32_operand
1068 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1069 opnd = locate_operand(inst, (WhichOperand)format);
1070 } else {
1071 assert(format == imm_operand, "cannot specify a format");
1072 return;
1073 }
1074 assert(opnd == pc(), "must put operand where relocs can find it");
1075 }
1076 #endif // ASSERT
1077
1078 void Assembler::emit_operand32(Register reg, Address adr) {
1079 assert(reg->encoding() < 8, "no extended registers");
1080 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1081 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1082 adr._rspec);
1083 }
1084
1085 void Assembler::emit_operand(Register reg, Address adr,
1086 int rip_relative_correction) {
1087 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1088 adr._rspec,
1089 rip_relative_correction);
1090 }
1091
1092 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1093 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1094 adr._rspec);
1095 }
1096
1097 // MMX operations
1098 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1099 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1100 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1101 }
1102
1103 // work around gcc (3.2.1-7a) bug
1104 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1105 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1106 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1107 }
1108
1109
1110 void Assembler::emit_farith(int b1, int b2, int i) {
1111 assert(isByte(b1) && isByte(b2), "wrong opcode");
1112 assert(0 <= i && i < 8, "illegal stack offset");
1113 emit_int8(b1);
1114 emit_int8(b2 + i);
1115 }
1116
1117
1118 // Now the Assembler instructions (identical for 32/64 bits)
1119
1120 void Assembler::adcl(Address dst, int32_t imm32) {
1121 InstructionMark im(this);
1122 prefix(dst);
1123 emit_arith_operand(0x81, rdx, dst, imm32);
1124 }
1125
1126 void Assembler::adcl(Address dst, Register src) {
1127 InstructionMark im(this);
1128 prefix(dst, src);
1129 emit_int8(0x11);
1130 emit_operand(src, dst);
1131 }
1132
1133 void Assembler::adcl(Register dst, int32_t imm32) {
1134 prefix(dst);
1135 emit_arith(0x81, 0xD0, dst, imm32);
1136 }
1137
1138 void Assembler::adcl(Register dst, Address src) {
1139 InstructionMark im(this);
1140 prefix(src, dst);
1141 emit_int8(0x13);
1142 emit_operand(dst, src);
1143 }
1144
1145 void Assembler::adcl(Register dst, Register src) {
1146 (void) prefix_and_encode(dst->encoding(), src->encoding());
1147 emit_arith(0x13, 0xC0, dst, src);
1148 }
1149
1150 void Assembler::addl(Address dst, int32_t imm32) {
1151 InstructionMark im(this);
1152 prefix(dst);
1153 emit_arith_operand(0x81, rax, dst, imm32);
1154 }
1155
1156 void Assembler::addl(Address dst, Register src) {
1157 InstructionMark im(this);
1158 prefix(dst, src);
1159 emit_int8(0x01);
1160 emit_operand(src, dst);
1161 }
1162
1163 void Assembler::addl(Register dst, int32_t imm32) {
1164 prefix(dst);
1165 emit_arith(0x81, 0xC0, dst, imm32);
1166 }
1167
1168 void Assembler::addl(Register dst, Address src) {
1169 InstructionMark im(this);
1170 prefix(src, dst);
1171 emit_int8(0x03);
1172 emit_operand(dst, src);
1173 }
1174
1175 void Assembler::addl(Register dst, Register src) {
1176 (void) prefix_and_encode(dst->encoding(), src->encoding());
1177 emit_arith(0x03, 0xC0, dst, src);
1178 }
1179
1180 void Assembler::addr_nop_4() {
1181 assert(UseAddressNop, "no CPU support");
1182 // 4 bytes: NOP DWORD PTR [EAX+0]
1183 emit_int8(0x0F);
1184 emit_int8(0x1F);
1185 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1186 emit_int8(0); // 8-bits offset (1 byte)
1187 }
1188
1189 void Assembler::addr_nop_5() {
1190 assert(UseAddressNop, "no CPU support");
1191 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1192 emit_int8(0x0F);
1193 emit_int8(0x1F);
1194 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1195 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1196 emit_int8(0); // 8-bits offset (1 byte)
1197 }
1198
1199 void Assembler::addr_nop_7() {
1200 assert(UseAddressNop, "no CPU support");
1201 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1202 emit_int8(0x0F);
1203 emit_int8(0x1F);
1204 emit_int8((unsigned char)0x80);
1205 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1206 emit_int32(0); // 32-bits offset (4 bytes)
1207 }
1208
1209 void Assembler::addr_nop_8() {
1210 assert(UseAddressNop, "no CPU support");
1211 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1212 emit_int8(0x0F);
1213 emit_int8(0x1F);
1214 emit_int8((unsigned char)0x84);
1215 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1216 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1217 emit_int32(0); // 32-bits offset (4 bytes)
1218 }
1219
1220 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1221 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1222 if (VM_Version::supports_evex()) {
1223 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_F2);
1224 } else {
1225 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
1226 }
1227 }
1228
1229 void Assembler::addsd(XMMRegister dst, Address src) {
1230 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1231 if (VM_Version::supports_evex()) {
1232 tuple_type = EVEX_T1S;
1233 input_size_in_bits = EVEX_64bit;
1234 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_F2);
1235 } else {
1236 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
1237 }
1238 }
1239
1240 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1241 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1242 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1243 }
1244
1245 void Assembler::addss(XMMRegister dst, Address src) {
1246 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1247 if (VM_Version::supports_evex()) {
1248 tuple_type = EVEX_T1S;
1249 input_size_in_bits = EVEX_32bit;
1250 }
1251 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1252 }
1253
1254 void Assembler::aesdec(XMMRegister dst, Address src) {
1255 assert(VM_Version::supports_aes(), "");
1256 InstructionMark im(this);
1257 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1258 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1259 emit_int8((unsigned char)0xDE);
1260 emit_operand(dst, src);
1261 }
1262
1263 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1264 assert(VM_Version::supports_aes(), "");
1265 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1266 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1267 emit_int8((unsigned char)0xDE);
1268 emit_int8(0xC0 | encode);
1269 }
1270
1271 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1272 assert(VM_Version::supports_aes(), "");
1273 InstructionMark im(this);
1274 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1275 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1276 emit_int8((unsigned char)0xDF);
1277 emit_operand(dst, src);
1278 }
1279
1280 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1281 assert(VM_Version::supports_aes(), "");
1282 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1283 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1284 emit_int8((unsigned char)0xDF);
1285 emit_int8((unsigned char)(0xC0 | encode));
1286 }
1287
1288 void Assembler::aesenc(XMMRegister dst, Address src) {
1289 assert(VM_Version::supports_aes(), "");
1290 InstructionMark im(this);
1291 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1292 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1293 emit_int8((unsigned char)0xDC);
1294 emit_operand(dst, src);
1295 }
1296
1297 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1298 assert(VM_Version::supports_aes(), "");
1299 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1300 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1301 emit_int8((unsigned char)0xDC);
1302 emit_int8(0xC0 | encode);
1303 }
1304
1305 void Assembler::aesenclast(XMMRegister dst, Address src) {
1306 assert(VM_Version::supports_aes(), "");
1307 InstructionMark im(this);
1308 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1309 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1310 emit_int8((unsigned char)0xDD);
1311 emit_operand(dst, src);
1312 }
1313
1314 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1315 assert(VM_Version::supports_aes(), "");
1316 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1317 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1318 emit_int8((unsigned char)0xDD);
1319 emit_int8((unsigned char)(0xC0 | encode));
1320 }
1321
1322
1323 void Assembler::andl(Address dst, int32_t imm32) {
1324 InstructionMark im(this);
1325 prefix(dst);
1326 emit_int8((unsigned char)0x81);
1327 emit_operand(rsp, dst, 4);
1328 emit_int32(imm32);
1329 }
1330
1331 void Assembler::andl(Register dst, int32_t imm32) {
1332 prefix(dst);
1333 emit_arith(0x81, 0xE0, dst, imm32);
1334 }
1335
1336 void Assembler::andl(Register dst, Address src) {
1337 InstructionMark im(this);
1338 prefix(src, dst);
1339 emit_int8(0x23);
1340 emit_operand(dst, src);
1341 }
1342
1343 void Assembler::andl(Register dst, Register src) {
1344 (void) prefix_and_encode(dst->encoding(), src->encoding());
1345 emit_arith(0x23, 0xC0, dst, src);
1346 }
1347
1348 void Assembler::andnl(Register dst, Register src1, Register src2) {
1349 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1350 int encode = vex_prefix_0F38_and_encode_legacy(dst, src1, src2, false);
1351 emit_int8((unsigned char)0xF2);
1352 emit_int8((unsigned char)(0xC0 | encode));
1353 }
1354
1355 void Assembler::andnl(Register dst, Register src1, Address src2) {
1356 InstructionMark im(this);
1357 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1358 vex_prefix_0F38_legacy(dst, src1, src2, false);
1359 emit_int8((unsigned char)0xF2);
1360 emit_operand(dst, src2);
1361 }
1362
1363 void Assembler::bsfl(Register dst, Register src) {
1364 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1365 emit_int8(0x0F);
1366 emit_int8((unsigned char)0xBC);
1367 emit_int8((unsigned char)(0xC0 | encode));
1368 }
1369
1370 void Assembler::bsrl(Register dst, Register src) {
1371 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1372 emit_int8(0x0F);
1373 emit_int8((unsigned char)0xBD);
1374 emit_int8((unsigned char)(0xC0 | encode));
1375 }
1376
1377 void Assembler::bswapl(Register reg) { // bswap
1378 int encode = prefix_and_encode(reg->encoding());
1379 emit_int8(0x0F);
1380 emit_int8((unsigned char)(0xC8 | encode));
1381 }
1382
1383 void Assembler::blsil(Register dst, Register src) {
1384 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1385 int encode = vex_prefix_0F38_and_encode_legacy(rbx, dst, src, false);
1386 emit_int8((unsigned char)0xF3);
1387 emit_int8((unsigned char)(0xC0 | encode));
1388 }
1389
1390 void Assembler::blsil(Register dst, Address src) {
1391 InstructionMark im(this);
1392 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1393 vex_prefix_0F38_legacy(rbx, dst, src, false);
1394 emit_int8((unsigned char)0xF3);
1395 emit_operand(rbx, src);
1396 }
1397
1398 void Assembler::blsmskl(Register dst, Register src) {
1399 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1400 int encode = vex_prefix_0F38_and_encode_legacy(rdx, dst, src, false);
1401 emit_int8((unsigned char)0xF3);
1402 emit_int8((unsigned char)(0xC0 | encode));
1403 }
1404
1405 void Assembler::blsmskl(Register dst, Address src) {
1406 InstructionMark im(this);
1407 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1408 vex_prefix_0F38(rdx, dst, src, false);
1409 emit_int8((unsigned char)0xF3);
1410 emit_operand(rdx, src);
1411 }
1412
1413 void Assembler::blsrl(Register dst, Register src) {
1414 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1415 int encode = vex_prefix_0F38_and_encode_legacy(rcx, dst, src, false);
1416 emit_int8((unsigned char)0xF3);
1417 emit_int8((unsigned char)(0xC0 | encode));
1418 }
1419
1420 void Assembler::blsrl(Register dst, Address src) {
1421 InstructionMark im(this);
1422 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1423 vex_prefix_0F38_legacy(rcx, dst, src, false);
1424 emit_int8((unsigned char)0xF3);
1425 emit_operand(rcx, src);
1426 }
1427
1428 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1429 // suspect disp32 is always good
1430 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1431
1432 if (L.is_bound()) {
1433 const int long_size = 5;
1434 int offs = (int)( target(L) - pc() );
1435 assert(offs <= 0, "assembler error");
1436 InstructionMark im(this);
1437 // 1110 1000 #32-bit disp
1438 emit_int8((unsigned char)0xE8);
1439 emit_data(offs - long_size, rtype, operand);
1440 } else {
1441 InstructionMark im(this);
1442 // 1110 1000 #32-bit disp
1443 L.add_patch_at(code(), locator());
1444
1445 emit_int8((unsigned char)0xE8);
1446 emit_data(int(0), rtype, operand);
1447 }
1448 }
1449
1450 void Assembler::call(Register dst) {
1451 int encode = prefix_and_encode(dst->encoding());
1452 emit_int8((unsigned char)0xFF);
1453 emit_int8((unsigned char)(0xD0 | encode));
1454 }
1455
1456
1457 void Assembler::call(Address adr) {
1458 InstructionMark im(this);
1459 prefix(adr);
1460 emit_int8((unsigned char)0xFF);
1461 emit_operand(rdx, adr);
1462 }
1463
1464 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1465 assert(entry != NULL, "call most probably wrong");
1466 InstructionMark im(this);
1467 emit_int8((unsigned char)0xE8);
1468 intptr_t disp = entry - (pc() + sizeof(int32_t));
1469 assert(is_simm32(disp), "must be 32bit offset (call2)");
1470 // Technically, should use call32_operand, but this format is
1471 // implied by the fact that we're emitting a call instruction.
1472
1473 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1474 emit_data((int) disp, rspec, operand);
1475 }
1476
1477 void Assembler::cdql() {
1478 emit_int8((unsigned char)0x99);
1479 }
1480
1481 void Assembler::cld() {
1482 emit_int8((unsigned char)0xFC);
1483 }
1484
1485 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1486 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1487 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1488 emit_int8(0x0F);
1489 emit_int8(0x40 | cc);
1490 emit_int8((unsigned char)(0xC0 | encode));
1491 }
1492
1493
1494 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1495 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1496 prefix(src, dst);
1497 emit_int8(0x0F);
1498 emit_int8(0x40 | cc);
1499 emit_operand(dst, src);
1500 }
1501
1502 void Assembler::cmpb(Address dst, int imm8) {
1503 InstructionMark im(this);
1504 prefix(dst);
1505 emit_int8((unsigned char)0x80);
1506 emit_operand(rdi, dst, 1);
1507 emit_int8(imm8);
1508 }
1509
1510 void Assembler::cmpl(Address dst, int32_t imm32) {
1511 InstructionMark im(this);
1512 prefix(dst);
1513 emit_int8((unsigned char)0x81);
1514 emit_operand(rdi, dst, 4);
1515 emit_int32(imm32);
1516 }
1517
1518 void Assembler::cmpl(Register dst, int32_t imm32) {
1519 prefix(dst);
1520 emit_arith(0x81, 0xF8, dst, imm32);
1521 }
1522
1523 void Assembler::cmpl(Register dst, Register src) {
1524 (void) prefix_and_encode(dst->encoding(), src->encoding());
1525 emit_arith(0x3B, 0xC0, dst, src);
1526 }
1527
1528
1529 void Assembler::cmpl(Register dst, Address src) {
1530 InstructionMark im(this);
1531 prefix(src, dst);
1532 emit_int8((unsigned char)0x3B);
1533 emit_operand(dst, src);
1534 }
1535
1536 void Assembler::cmpw(Address dst, int imm16) {
1537 InstructionMark im(this);
1538 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1539 emit_int8(0x66);
1540 emit_int8((unsigned char)0x81);
1541 emit_operand(rdi, dst, 2);
1542 emit_int16(imm16);
1543 }
1544
1545 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1546 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1547 // The ZF is set if the compared values were equal, and cleared otherwise.
1548 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1549 InstructionMark im(this);
1550 prefix(adr, reg);
1551 emit_int8(0x0F);
1552 emit_int8((unsigned char)0xB1);
1553 emit_operand(reg, adr);
1554 }
1555
1556 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1557 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1558 // The ZF is set if the compared values were equal, and cleared otherwise.
1559 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1560 InstructionMark im(this);
1561 prefix(adr, reg, true);
1562 emit_int8(0x0F);
1563 emit_int8((unsigned char)0xB0);
1564 emit_operand(reg, adr);
1565 }
1566
1567 void Assembler::comisd(XMMRegister dst, Address src) {
1568 // NOTE: dbx seems to decode this as comiss even though the
1569 // 0x66 is there. Strangly ucomisd comes out correct
1570 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1571 if (VM_Version::supports_evex()) {
1572 tuple_type = EVEX_T1S;
1573 input_size_in_bits = EVEX_64bit;
1574 emit_simd_arith_nonds_q(0x2F, dst, src, VEX_SIMD_66, true);
1575 } else {
1576 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1577 }
1578 }
1579
1580 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1581 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1582 if (VM_Version::supports_evex()) {
1583 emit_simd_arith_nonds_q(0x2F, dst, src, VEX_SIMD_66, true);
1584 } else {
1585 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1586 }
1587 }
1588
1589 void Assembler::comiss(XMMRegister dst, Address src) {
1590 if (VM_Version::supports_evex()) {
1591 tuple_type = EVEX_T1S;
1592 input_size_in_bits = EVEX_32bit;
1593 }
1594 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1595 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE, true);
1596 }
1597
1598 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1599 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1600 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE, true);
1601 }
1602
1603 void Assembler::cpuid() {
1604 emit_int8(0x0F);
1605 emit_int8((unsigned char)0xA2);
1606 }
1607
1608 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1609 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1610 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1611 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1612 //
1613 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1614 //
1615 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1616 //
1617 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1618 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1619 assert(VM_Version::supports_sse4_2(), "");
1620 int8_t w = 0x01;
1621 Prefix p = Prefix_EMPTY;
1622
1623 emit_int8((int8_t)0xF2);
1624 switch (sizeInBytes) {
1625 case 1:
1626 w = 0;
1627 break;
1628 case 2:
1629 case 4:
1630 break;
1631 LP64_ONLY(case 8:)
1632 // This instruction is not valid in 32 bits
1633 // Note:
1634 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1635 //
1636 // Page B - 72 Vol. 2C says
1637 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1638 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1639 // F0!!!
1640 // while 3 - 208 Vol. 2A
1641 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1642 //
1643 // the 0 on a last bit is reserved for a different flavor of this instruction :
1644 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1645 p = REX_W;
1646 break;
1647 default:
1648 assert(0, "Unsupported value for a sizeInBytes argument");
1649 break;
1650 }
1651 LP64_ONLY(prefix(crc, v, p);)
1652 emit_int8((int8_t)0x0F);
1653 emit_int8(0x38);
1654 emit_int8((int8_t)(0xF0 | w));
1655 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1656 }
1657
1658 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1659 assert(VM_Version::supports_sse4_2(), "");
1660 InstructionMark im(this);
1661 int8_t w = 0x01;
1662 Prefix p = Prefix_EMPTY;
1663
1664 emit_int8((int8_t)0xF2);
1665 switch (sizeInBytes) {
1666 case 1:
1667 w = 0;
1668 break;
1669 case 2:
1670 case 4:
1671 break;
1672 LP64_ONLY(case 8:)
1673 // This instruction is not valid in 32 bits
1674 p = REX_W;
1675 break;
1676 default:
1677 assert(0, "Unsupported value for a sizeInBytes argument");
1678 break;
1679 }
1680 LP64_ONLY(prefix(crc, adr, p);)
1681 emit_int8((int8_t)0x0F);
1682 emit_int8(0x38);
1683 emit_int8((int8_t)(0xF0 | w));
1684 emit_operand(crc, adr);
1685 }
1686
1687 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1688 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1689 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3);
1690 }
1691
1692 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1693 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1694 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE);
1695 }
1696
1697 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1698 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1699 if (VM_Version::supports_evex()) {
1700 emit_simd_arith_q(0x5A, dst, src, VEX_SIMD_F2);
1701 } else {
1702 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1703 }
1704 }
1705
1706 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1707 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1708 if (VM_Version::supports_evex()) {
1709 tuple_type = EVEX_T1F;
1710 input_size_in_bits = EVEX_64bit;
1711 emit_simd_arith_q(0x5A, dst, src, VEX_SIMD_F2);
1712 } else {
1713 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1714 }
1715 }
1716
1717 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1718 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1719 int encode = 0;
1720 if (VM_Version::supports_evex()) {
1721 encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2, true);
1722 } else {
1723 encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, false);
1724 }
1725 emit_int8(0x2A);
1726 emit_int8((unsigned char)(0xC0 | encode));
1727 }
1728
1729 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1730 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1731 if (VM_Version::supports_evex()) {
1732 tuple_type = EVEX_T1S;
1733 input_size_in_bits = EVEX_32bit;
1734 emit_simd_arith_q(0x2A, dst, src, VEX_SIMD_F2, true);
1735 } else {
1736 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2);
1737 }
1738 }
1739
1740 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1741 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1742 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, true);
1743 emit_int8(0x2A);
1744 emit_int8((unsigned char)(0xC0 | encode));
1745 }
1746
1747 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1748 if (VM_Version::supports_evex()) {
1749 tuple_type = EVEX_T1S;
1750 input_size_in_bits = EVEX_32bit;
1751 }
1752 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1753 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3, true);
1754 }
1755
1756 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1757 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1758 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1759 }
1760
1761 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1762 if (VM_Version::supports_evex()) {
1763 tuple_type = EVEX_T1S;
1764 input_size_in_bits = EVEX_32bit;
1765 }
1766 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1767 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1768 }
1769
1770
1771 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1772 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1773 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, true);
1774 emit_int8(0x2C);
1775 emit_int8((unsigned char)(0xC0 | encode));
1776 }
1777
1778 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1779 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1780 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, true);
1781 emit_int8(0x2C);
1782 emit_int8((unsigned char)(0xC0 | encode));
1783 }
1784
1785 void Assembler::decl(Address dst) {
1786 // Don't use it directly. Use MacroAssembler::decrement() instead.
1787 InstructionMark im(this);
1788 prefix(dst);
1789 emit_int8((unsigned char)0xFF);
1790 emit_operand(rcx, dst);
1791 }
1792
1793 void Assembler::divsd(XMMRegister dst, Address src) {
1794 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1795 if (VM_Version::supports_evex()) {
1796 tuple_type = EVEX_T1S;
1797 input_size_in_bits = EVEX_64bit;
1798 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_F2);
1799 } else {
1800 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1801 }
1802 }
1803
1804 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1805 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1806 if (VM_Version::supports_evex()) {
1807 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_F2);
1808 } else {
1809 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1810 }
1811 }
1812
1813 void Assembler::divss(XMMRegister dst, Address src) {
1814 if (VM_Version::supports_evex()) {
1815 tuple_type = EVEX_T1S;
1816 input_size_in_bits = EVEX_32bit;
1817 }
1818 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1819 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1820 }
1821
1822 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1823 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1824 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1825 }
1826
1827 void Assembler::emms() {
1828 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1829 emit_int8(0x0F);
1830 emit_int8(0x77);
1831 }
1832
1833 void Assembler::hlt() {
1834 emit_int8((unsigned char)0xF4);
1835 }
1836
1837 void Assembler::idivl(Register src) {
1838 int encode = prefix_and_encode(src->encoding());
1839 emit_int8((unsigned char)0xF7);
1840 emit_int8((unsigned char)(0xF8 | encode));
1841 }
1842
1843 void Assembler::divl(Register src) { // Unsigned
1844 int encode = prefix_and_encode(src->encoding());
1845 emit_int8((unsigned char)0xF7);
1846 emit_int8((unsigned char)(0xF0 | encode));
1847 }
1848
1849 void Assembler::imull(Register dst, Register src) {
1850 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1851 emit_int8(0x0F);
1852 emit_int8((unsigned char)0xAF);
1853 emit_int8((unsigned char)(0xC0 | encode));
1854 }
1855
1856
1857 void Assembler::imull(Register dst, Register src, int value) {
1858 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1859 if (is8bit(value)) {
1860 emit_int8(0x6B);
1861 emit_int8((unsigned char)(0xC0 | encode));
1862 emit_int8(value & 0xFF);
1863 } else {
1864 emit_int8(0x69);
1865 emit_int8((unsigned char)(0xC0 | encode));
1866 emit_int32(value);
1867 }
1868 }
1869
1870 void Assembler::imull(Register dst, Address src) {
1871 InstructionMark im(this);
1872 prefix(src, dst);
1873 emit_int8(0x0F);
1874 emit_int8((unsigned char) 0xAF);
1875 emit_operand(dst, src);
1876 }
1877
1878
1879 void Assembler::incl(Address dst) {
1880 // Don't use it directly. Use MacroAssembler::increment() instead.
1881 InstructionMark im(this);
1882 prefix(dst);
1883 emit_int8((unsigned char)0xFF);
1884 emit_operand(rax, dst);
1885 }
1886
1887 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1888 InstructionMark im(this);
1889 assert((0 <= cc) && (cc < 16), "illegal cc");
1890 if (L.is_bound()) {
1891 address dst = target(L);
1892 assert(dst != NULL, "jcc most probably wrong");
1893
1894 const int short_size = 2;
1895 const int long_size = 6;
1896 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1897 if (maybe_short && is8bit(offs - short_size)) {
1898 // 0111 tttn #8-bit disp
1899 emit_int8(0x70 | cc);
1900 emit_int8((offs - short_size) & 0xFF);
1901 } else {
1902 // 0000 1111 1000 tttn #32-bit disp
1903 assert(is_simm32(offs - long_size),
1904 "must be 32bit offset (call4)");
1905 emit_int8(0x0F);
1906 emit_int8((unsigned char)(0x80 | cc));
1907 emit_int32(offs - long_size);
1908 }
1909 } else {
1910 // Note: could eliminate cond. jumps to this jump if condition
1911 // is the same however, seems to be rather unlikely case.
1912 // Note: use jccb() if label to be bound is very close to get
1913 // an 8-bit displacement
1914 L.add_patch_at(code(), locator());
1915 emit_int8(0x0F);
1916 emit_int8((unsigned char)(0x80 | cc));
1917 emit_int32(0);
1918 }
1919 }
1920
1921 void Assembler::jccb(Condition cc, Label& L) {
1922 if (L.is_bound()) {
1923 const int short_size = 2;
1924 address entry = target(L);
1925 #ifdef ASSERT
1926 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1927 intptr_t delta = short_branch_delta();
1928 if (delta != 0) {
1929 dist += (dist < 0 ? (-delta) :delta);
1930 }
1931 assert(is8bit(dist), "Dispacement too large for a short jmp");
1932 #endif
1933 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1934 // 0111 tttn #8-bit disp
1935 emit_int8(0x70 | cc);
1936 emit_int8((offs - short_size) & 0xFF);
1937 } else {
1938 InstructionMark im(this);
1939 L.add_patch_at(code(), locator());
1940 emit_int8(0x70 | cc);
1941 emit_int8(0);
1942 }
1943 }
1944
1945 void Assembler::jmp(Address adr) {
1946 InstructionMark im(this);
1947 prefix(adr);
1948 emit_int8((unsigned char)0xFF);
1949 emit_operand(rsp, adr);
1950 }
1951
1952 void Assembler::jmp(Label& L, bool maybe_short) {
1953 if (L.is_bound()) {
1954 address entry = target(L);
1955 assert(entry != NULL, "jmp most probably wrong");
1956 InstructionMark im(this);
1957 const int short_size = 2;
1958 const int long_size = 5;
1959 intptr_t offs = entry - pc();
1960 if (maybe_short && is8bit(offs - short_size)) {
1961 emit_int8((unsigned char)0xEB);
1962 emit_int8((offs - short_size) & 0xFF);
1963 } else {
1964 emit_int8((unsigned char)0xE9);
1965 emit_int32(offs - long_size);
1966 }
1967 } else {
1968 // By default, forward jumps are always 32-bit displacements, since
1969 // we can't yet know where the label will be bound. If you're sure that
1970 // the forward jump will not run beyond 256 bytes, use jmpb to
1971 // force an 8-bit displacement.
1972 InstructionMark im(this);
1973 L.add_patch_at(code(), locator());
1974 emit_int8((unsigned char)0xE9);
1975 emit_int32(0);
1976 }
1977 }
1978
1979 void Assembler::jmp(Register entry) {
1980 int encode = prefix_and_encode(entry->encoding());
1981 emit_int8((unsigned char)0xFF);
1982 emit_int8((unsigned char)(0xE0 | encode));
1983 }
1984
1985 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1986 InstructionMark im(this);
1987 emit_int8((unsigned char)0xE9);
1988 assert(dest != NULL, "must have a target");
1989 intptr_t disp = dest - (pc() + sizeof(int32_t));
1990 assert(is_simm32(disp), "must be 32bit offset (jmp)");
1991 emit_data(disp, rspec.reloc(), call32_operand);
1992 }
1993
1994 void Assembler::jmpb(Label& L) {
1995 if (L.is_bound()) {
1996 const int short_size = 2;
1997 address entry = target(L);
1998 assert(entry != NULL, "jmp most probably wrong");
1999 #ifdef ASSERT
2000 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2001 intptr_t delta = short_branch_delta();
2002 if (delta != 0) {
2003 dist += (dist < 0 ? (-delta) :delta);
2004 }
2005 assert(is8bit(dist), "Dispacement too large for a short jmp");
2006 #endif
2007 intptr_t offs = entry - pc();
2008 emit_int8((unsigned char)0xEB);
2009 emit_int8((offs - short_size) & 0xFF);
2010 } else {
2011 InstructionMark im(this);
2012 L.add_patch_at(code(), locator());
2013 emit_int8((unsigned char)0xEB);
2014 emit_int8(0);
2015 }
2016 }
2017
2018 void Assembler::ldmxcsr( Address src) {
2019 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2020 InstructionMark im(this);
2021 prefix(src);
2022 emit_int8(0x0F);
2023 emit_int8((unsigned char)0xAE);
2024 emit_operand(as_Register(2), src);
2025 }
2026
2027 void Assembler::leal(Register dst, Address src) {
2028 InstructionMark im(this);
2029 #ifdef _LP64
2030 emit_int8(0x67); // addr32
2031 prefix(src, dst);
2032 #endif // LP64
2033 emit_int8((unsigned char)0x8D);
2034 emit_operand(dst, src);
2035 }
2036
2037 void Assembler::lfence() {
2038 emit_int8(0x0F);
2039 emit_int8((unsigned char)0xAE);
2040 emit_int8((unsigned char)0xE8);
2041 }
2042
2043 void Assembler::lock() {
2044 emit_int8((unsigned char)0xF0);
2045 }
2046
2047 void Assembler::lzcntl(Register dst, Register src) {
2048 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2049 emit_int8((unsigned char)0xF3);
2050 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2051 emit_int8(0x0F);
2052 emit_int8((unsigned char)0xBD);
2053 emit_int8((unsigned char)(0xC0 | encode));
2054 }
2055
2056 // Emit mfence instruction
2057 void Assembler::mfence() {
2058 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2059 emit_int8(0x0F);
2060 emit_int8((unsigned char)0xAE);
2061 emit_int8((unsigned char)0xF0);
2062 }
2063
2064 void Assembler::mov(Register dst, Register src) {
2065 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2066 }
2067
2068 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2069 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2070 if (VM_Version::supports_evex()) {
2071 emit_simd_arith_nonds_q(0x28, dst, src, VEX_SIMD_66, true);
2072 } else {
2073 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66);
2074 }
2075 }
2076
2077 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2078 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2079 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE);
2080 }
2081
2082 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2083 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2084 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, true, VEX_OPCODE_0F,
2085 false, AVX_128bit);
2086 emit_int8(0x16);
2087 emit_int8((unsigned char)(0xC0 | encode));
2088 }
2089
2090 void Assembler::movb(Register dst, Address src) {
2091 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2092 InstructionMark im(this);
2093 prefix(src, dst, true);
2094 emit_int8((unsigned char)0x8A);
2095 emit_operand(dst, src);
2096 }
2097
2098 void Assembler::kmovq(KRegister dst, KRegister src) {
2099 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2100 int encode = kreg_prefix_and_encode(dst, knoreg, src, VEX_SIMD_NONE,
2101 true, VEX_OPCODE_0F, true);
2102 emit_int8((unsigned char)0x90);
2103 emit_int8((unsigned char)(0xC0 | encode));
2104 }
2105
2106 void Assembler::kmovq(KRegister dst, Address src) {
2107 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2108 int dst_enc = dst->encoding();
2109 int nds_enc = 0;
2110 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_NONE,
2111 VEX_OPCODE_0F, true, AVX_128bit, true, true);
2112 emit_int8((unsigned char)0x90);
2113 emit_operand((Register)dst, src);
2114 }
2115
2116 void Assembler::kmovq(Address dst, KRegister src) {
2117 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2118 int src_enc = src->encoding();
2119 int nds_enc = 0;
2120 vex_prefix(dst, nds_enc, src_enc, VEX_SIMD_NONE,
2121 VEX_OPCODE_0F, true, AVX_128bit, true, true);
2122 emit_int8((unsigned char)0x90);
2123 emit_operand((Register)src, dst);
2124 }
2125
2126 void Assembler::kmovql(KRegister dst, Register src) {
2127 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2128 bool supports_bw = VM_Version::supports_avx512bw();
2129 VexSimdPrefix pre = supports_bw ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2130 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, true,
2131 VEX_OPCODE_0F, supports_bw);
2132 emit_int8((unsigned char)0x92);
2133 emit_int8((unsigned char)(0xC0 | encode));
2134 }
2135
2136 void Assembler::kmovdl(KRegister dst, Register src) {
2137 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2138 VexSimdPrefix pre = VM_Version::supports_avx512bw() ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2139 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, true, VEX_OPCODE_0F, false);
2140 emit_int8((unsigned char)0x92);
2141 emit_int8((unsigned char)(0xC0 | encode));
2142 }
2143
2144 void Assembler::movb(Address dst, int imm8) {
2145 InstructionMark im(this);
2146 prefix(dst);
2147 emit_int8((unsigned char)0xC6);
2148 emit_operand(rax, dst, 1);
2149 emit_int8(imm8);
2150 }
2151
2152
2153 void Assembler::movb(Address dst, Register src) {
2154 assert(src->has_byte_register(), "must have byte register");
2155 InstructionMark im(this);
2156 prefix(dst, src, true);
2157 emit_int8((unsigned char)0x88);
2158 emit_operand(src, dst);
2159 }
2160
2161 void Assembler::movdl(XMMRegister dst, Register src) {
2162 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2163 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, true);
2164 emit_int8(0x6E);
2165 emit_int8((unsigned char)(0xC0 | encode));
2166 }
2167
2168 void Assembler::movdl(Register dst, XMMRegister src) {
2169 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2170 // swap src/dst to get correct prefix
2171 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66, true);
2172 emit_int8(0x7E);
2173 emit_int8((unsigned char)(0xC0 | encode));
2174 }
2175
2176 void Assembler::movdl(XMMRegister dst, Address src) {
2177 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2178 if (VM_Version::supports_evex()) {
2179 tuple_type = EVEX_T1S;
2180 input_size_in_bits = EVEX_32bit;
2181 }
2182 InstructionMark im(this);
2183 simd_prefix(dst, src, VEX_SIMD_66, true, VEX_OPCODE_0F);
2184 emit_int8(0x6E);
2185 emit_operand(dst, src);
2186 }
2187
2188 void Assembler::movdl(Address dst, XMMRegister src) {
2189 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2190 if (VM_Version::supports_evex()) {
2191 tuple_type = EVEX_T1S;
2192 input_size_in_bits = EVEX_32bit;
2193 }
2194 InstructionMark im(this);
2195 simd_prefix(dst, src, VEX_SIMD_66, true);
2196 emit_int8(0x7E);
2197 emit_operand(src, dst);
2198 }
2199
2200 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2201 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2202 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
2203 }
2204
2205 void Assembler::movdqa(XMMRegister dst, Address src) {
2206 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2207 if (VM_Version::supports_evex()) {
2208 tuple_type = EVEX_FVM;
2209 }
2210 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
2211 }
2212
2213 void Assembler::movdqu(XMMRegister dst, Address src) {
2214 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2215 if (VM_Version::supports_evex()) {
2216 tuple_type = EVEX_FVM;
2217 }
2218 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
2219 }
2220
2221 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2222 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2223 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
2224 }
2225
2226 void Assembler::movdqu(Address dst, XMMRegister src) {
2227 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2228 if (VM_Version::supports_evex()) {
2229 tuple_type = EVEX_FVM;
2230 }
2231 InstructionMark im(this);
2232 simd_prefix(dst, src, VEX_SIMD_F3, false);
2233 emit_int8(0x7F);
2234 emit_operand(src, dst);
2235 }
2236
2237 // Move Unaligned 256bit Vector
2238 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2239 assert(UseAVX > 0, "");
2240 if (VM_Version::supports_evex()) {
2241 tuple_type = EVEX_FVM;
2242 }
2243 int vector_len = AVX_256bit;
2244 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector_len);
2245 emit_int8(0x6F);
2246 emit_int8((unsigned char)(0xC0 | encode));
2247 }
2248
2249 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2250 assert(UseAVX > 0, "");
2251 if (VM_Version::supports_evex()) {
2252 tuple_type = EVEX_FVM;
2253 }
2254 InstructionMark im(this);
2255 int vector_len = AVX_256bit;
2256 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector_len, false);
2257 emit_int8(0x6F);
2258 emit_operand(dst, src);
2259 }
2260
2261 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2262 assert(UseAVX > 0, "");
2263 if (VM_Version::supports_evex()) {
2264 tuple_type = EVEX_FVM;
2265 }
2266 InstructionMark im(this);
2267 int vector_len = AVX_256bit;
2268 // swap src<->dst for encoding
2269 assert(src != xnoreg, "sanity");
2270 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector_len, false);
2271 emit_int8(0x7F);
2272 emit_operand(src, dst);
2273 }
2274
2275 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2276 void Assembler::evmovdqu(XMMRegister dst, XMMRegister src, int vector_len) {
2277 assert(UseAVX > 0, "");
2278 int src_enc = src->encoding();
2279 int dst_enc = dst->encoding();
2280 int encode = vex_prefix_and_encode(dst_enc, 0, src_enc, VEX_SIMD_F3, VEX_OPCODE_0F,
2281 true, vector_len, false, false);
2282 emit_int8(0x6F);
2283 emit_int8((unsigned char)(0xC0 | encode));
2284 }
2285
2286 void Assembler::evmovdqu(XMMRegister dst, Address src, int vector_len) {
2287 assert(UseAVX > 0, "");
2288 InstructionMark im(this);
2289 if (VM_Version::supports_evex()) {
2290 tuple_type = EVEX_FVM;
2291 vex_prefix_q(dst, xnoreg, src, VEX_SIMD_F3, vector_len, false);
2292 } else {
2293 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector_len, false);
2294 }
2295 emit_int8(0x6F);
2296 emit_operand(dst, src);
2297 }
2298
2299 void Assembler::evmovdqu(Address dst, XMMRegister src, int vector_len) {
2300 assert(UseAVX > 0, "");
2301 InstructionMark im(this);
2302 assert(src != xnoreg, "sanity");
2303 if (VM_Version::supports_evex()) {
2304 tuple_type = EVEX_FVM;
2305 // swap src<->dst for encoding
2306 vex_prefix_q(src, xnoreg, dst, VEX_SIMD_F3, vector_len, false);
2307 } else {
2308 // swap src<->dst for encoding
2309 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector_len, false);
2310 }
2311 emit_int8(0x7F);
2312 emit_operand(src, dst);
2313 }
2314
2315 // Uses zero extension on 64bit
2316
2317 void Assembler::movl(Register dst, int32_t imm32) {
2318 int encode = prefix_and_encode(dst->encoding());
2319 emit_int8((unsigned char)(0xB8 | encode));
2320 emit_int32(imm32);
2321 }
2322
2323 void Assembler::movl(Register dst, Register src) {
2324 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2325 emit_int8((unsigned char)0x8B);
2326 emit_int8((unsigned char)(0xC0 | encode));
2327 }
2328
2329 void Assembler::movl(Register dst, Address src) {
2330 InstructionMark im(this);
2331 prefix(src, dst);
2332 emit_int8((unsigned char)0x8B);
2333 emit_operand(dst, src);
2334 }
2335
2336 void Assembler::movl(Address dst, int32_t imm32) {
2337 InstructionMark im(this);
2338 prefix(dst);
2339 emit_int8((unsigned char)0xC7);
2340 emit_operand(rax, dst, 4);
2341 emit_int32(imm32);
2342 }
2343
2344 void Assembler::movl(Address dst, Register src) {
2345 InstructionMark im(this);
2346 prefix(dst, src);
2347 emit_int8((unsigned char)0x89);
2348 emit_operand(src, dst);
2349 }
2350
2351 // New cpus require to use movsd and movss to avoid partial register stall
2352 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2353 // The selection is done in MacroAssembler::movdbl() and movflt().
2354 void Assembler::movlpd(XMMRegister dst, Address src) {
2355 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2356 if (VM_Version::supports_evex()) {
2357 tuple_type = EVEX_T1S;
2358 input_size_in_bits = EVEX_32bit;
2359 }
2360 emit_simd_arith(0x12, dst, src, VEX_SIMD_66, true);
2361 }
2362
2363 void Assembler::movq( MMXRegister dst, Address src ) {
2364 assert( VM_Version::supports_mmx(), "" );
2365 emit_int8(0x0F);
2366 emit_int8(0x6F);
2367 emit_operand(dst, src);
2368 }
2369
2370 void Assembler::movq( Address dst, MMXRegister src ) {
2371 assert( VM_Version::supports_mmx(), "" );
2372 emit_int8(0x0F);
2373 emit_int8(0x7F);
2374 // workaround gcc (3.2.1-7a) bug
2375 // In that version of gcc with only an emit_operand(MMX, Address)
2376 // gcc will tail jump and try and reverse the parameters completely
2377 // obliterating dst in the process. By having a version available
2378 // that doesn't need to swap the args at the tail jump the bug is
2379 // avoided.
2380 emit_operand(dst, src);
2381 }
2382
2383 void Assembler::movq(XMMRegister dst, Address src) {
2384 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2385 InstructionMark im(this);
2386 if (VM_Version::supports_evex()) {
2387 tuple_type = EVEX_T1S;
2388 input_size_in_bits = EVEX_64bit;
2389 simd_prefix_q(dst, xnoreg, src, VEX_SIMD_F3, true);
2390 } else {
2391 simd_prefix(dst, src, VEX_SIMD_F3, true, VEX_OPCODE_0F);
2392 }
2393 emit_int8(0x7E);
2394 emit_operand(dst, src);
2395 }
2396
2397 void Assembler::movq(Address dst, XMMRegister src) {
2398 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2399 InstructionMark im(this);
2400 if (VM_Version::supports_evex()) {
2401 tuple_type = EVEX_T1S;
2402 input_size_in_bits = EVEX_64bit;
2403 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, true,
2404 VEX_OPCODE_0F, true, AVX_128bit);
2405 } else {
2406 simd_prefix(dst, src, VEX_SIMD_66, true);
2407 }
2408 emit_int8((unsigned char)0xD6);
2409 emit_operand(src, dst);
2410 }
2411
2412 void Assembler::movsbl(Register dst, Address src) { // movsxb
2413 InstructionMark im(this);
2414 prefix(src, dst);
2415 emit_int8(0x0F);
2416 emit_int8((unsigned char)0xBE);
2417 emit_operand(dst, src);
2418 }
2419
2420 void Assembler::movsbl(Register dst, Register src) { // movsxb
2421 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2422 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
2423 emit_int8(0x0F);
2424 emit_int8((unsigned char)0xBE);
2425 emit_int8((unsigned char)(0xC0 | encode));
2426 }
2427
2428 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2429 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2430 if (VM_Version::supports_evex()) {
2431 emit_simd_arith_q(0x10, dst, src, VEX_SIMD_F2, true);
2432 } else {
2433 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2);
2434 }
2435 }
2436
2437 void Assembler::movsd(XMMRegister dst, Address src) {
2438 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2439 if (VM_Version::supports_evex()) {
2440 tuple_type = EVEX_T1S;
2441 input_size_in_bits = EVEX_64bit;
2442 emit_simd_arith_nonds_q(0x10, dst, src, VEX_SIMD_F2, true);
2443 } else {
2444 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2);
2445 }
2446 }
2447
2448 void Assembler::movsd(Address dst, XMMRegister src) {
2449 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2450 InstructionMark im(this);
2451 if (VM_Version::supports_evex()) {
2452 tuple_type = EVEX_T1S;
2453 input_size_in_bits = EVEX_64bit;
2454 simd_prefix_q(src, xnoreg, dst, VEX_SIMD_F2);
2455 } else {
2456 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, false);
2457 }
2458 emit_int8(0x11);
2459 emit_operand(src, dst);
2460 }
2461
2462 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2463 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2464 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3, true);
2465 }
2466
2467 void Assembler::movss(XMMRegister dst, Address src) {
2468 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2469 if (VM_Version::supports_evex()) {
2470 tuple_type = EVEX_T1S;
2471 input_size_in_bits = EVEX_32bit;
2472 }
2473 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3, true);
2474 }
2475
2476 void Assembler::movss(Address dst, XMMRegister src) {
2477 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2478 if (VM_Version::supports_evex()) {
2479 tuple_type = EVEX_T1S;
2480 input_size_in_bits = EVEX_32bit;
2481 }
2482 InstructionMark im(this);
2483 simd_prefix(dst, src, VEX_SIMD_F3, false);
2484 emit_int8(0x11);
2485 emit_operand(src, dst);
2486 }
2487
2488 void Assembler::movswl(Register dst, Address src) { // movsxw
2489 InstructionMark im(this);
2490 prefix(src, dst);
2491 emit_int8(0x0F);
2492 emit_int8((unsigned char)0xBF);
2493 emit_operand(dst, src);
2494 }
2495
2496 void Assembler::movswl(Register dst, Register src) { // movsxw
2497 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2498 emit_int8(0x0F);
2499 emit_int8((unsigned char)0xBF);
2500 emit_int8((unsigned char)(0xC0 | encode));
2501 }
2502
2503 void Assembler::movw(Address dst, int imm16) {
2504 InstructionMark im(this);
2505
2506 emit_int8(0x66); // switch to 16-bit mode
2507 prefix(dst);
2508 emit_int8((unsigned char)0xC7);
2509 emit_operand(rax, dst, 2);
2510 emit_int16(imm16);
2511 }
2512
2513 void Assembler::movw(Register dst, Address src) {
2514 InstructionMark im(this);
2515 emit_int8(0x66);
2516 prefix(src, dst);
2517 emit_int8((unsigned char)0x8B);
2518 emit_operand(dst, src);
2519 }
2520
2521 void Assembler::movw(Address dst, Register src) {
2522 InstructionMark im(this);
2523 emit_int8(0x66);
2524 prefix(dst, src);
2525 emit_int8((unsigned char)0x89);
2526 emit_operand(src, dst);
2527 }
2528
2529 void Assembler::movzbl(Register dst, Address src) { // movzxb
2530 InstructionMark im(this);
2531 prefix(src, dst);
2532 emit_int8(0x0F);
2533 emit_int8((unsigned char)0xB6);
2534 emit_operand(dst, src);
2535 }
2536
2537 void Assembler::movzbl(Register dst, Register src) { // movzxb
2538 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2539 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
2540 emit_int8(0x0F);
2541 emit_int8((unsigned char)0xB6);
2542 emit_int8(0xC0 | encode);
2543 }
2544
2545 void Assembler::movzwl(Register dst, Address src) { // movzxw
2546 InstructionMark im(this);
2547 prefix(src, dst);
2548 emit_int8(0x0F);
2549 emit_int8((unsigned char)0xB7);
2550 emit_operand(dst, src);
2551 }
2552
2553 void Assembler::movzwl(Register dst, Register src) { // movzxw
2554 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2555 emit_int8(0x0F);
2556 emit_int8((unsigned char)0xB7);
2557 emit_int8(0xC0 | encode);
2558 }
2559
2560 void Assembler::mull(Address src) {
2561 InstructionMark im(this);
2562 prefix(src);
2563 emit_int8((unsigned char)0xF7);
2564 emit_operand(rsp, src);
2565 }
2566
2567 void Assembler::mull(Register src) {
2568 int encode = prefix_and_encode(src->encoding());
2569 emit_int8((unsigned char)0xF7);
2570 emit_int8((unsigned char)(0xE0 | encode));
2571 }
2572
2573 void Assembler::mulsd(XMMRegister dst, Address src) {
2574 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2575 if (VM_Version::supports_evex()) {
2576 tuple_type = EVEX_T1S;
2577 input_size_in_bits = EVEX_64bit;
2578 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_F2);
2579 } else {
2580 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2581 }
2582 }
2583
2584 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2585 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2586 if (VM_Version::supports_evex()) {
2587 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_F2);
2588 } else {
2589 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2590 }
2591 }
2592
2593 void Assembler::mulss(XMMRegister dst, Address src) {
2594 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2595 if (VM_Version::supports_evex()) {
2596 tuple_type = EVEX_T1S;
2597 input_size_in_bits = EVEX_32bit;
2598 }
2599 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2600 }
2601
2602 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2603 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2604 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2605 }
2606
2607 void Assembler::negl(Register dst) {
2608 int encode = prefix_and_encode(dst->encoding());
2609 emit_int8((unsigned char)0xF7);
2610 emit_int8((unsigned char)(0xD8 | encode));
2611 }
2612
2613 void Assembler::nop(int i) {
2614 #ifdef ASSERT
2615 assert(i > 0, " ");
2616 // The fancy nops aren't currently recognized by debuggers making it a
2617 // pain to disassemble code while debugging. If asserts are on clearly
2618 // speed is not an issue so simply use the single byte traditional nop
2619 // to do alignment.
2620
2621 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2622 return;
2623
2624 #endif // ASSERT
2625
2626 if (UseAddressNop && VM_Version::is_intel()) {
2627 //
2628 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2629 // 1: 0x90
2630 // 2: 0x66 0x90
2631 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2632 // 4: 0x0F 0x1F 0x40 0x00
2633 // 5: 0x0F 0x1F 0x44 0x00 0x00
2634 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2635 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2636 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2637 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2638 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2639 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2640
2641 // The rest coding is Intel specific - don't use consecutive address nops
2642
2643 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2644 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2645 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2646 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2647
2648 while(i >= 15) {
2649 // For Intel don't generate consecutive addess nops (mix with regular nops)
2650 i -= 15;
2651 emit_int8(0x66); // size prefix
2652 emit_int8(0x66); // size prefix
2653 emit_int8(0x66); // size prefix
2654 addr_nop_8();
2655 emit_int8(0x66); // size prefix
2656 emit_int8(0x66); // size prefix
2657 emit_int8(0x66); // size prefix
2658 emit_int8((unsigned char)0x90);
2659 // nop
2660 }
2661 switch (i) {
2662 case 14:
2663 emit_int8(0x66); // size prefix
2664 case 13:
2665 emit_int8(0x66); // size prefix
2666 case 12:
2667 addr_nop_8();
2668 emit_int8(0x66); // size prefix
2669 emit_int8(0x66); // size prefix
2670 emit_int8(0x66); // size prefix
2671 emit_int8((unsigned char)0x90);
2672 // nop
2673 break;
2674 case 11:
2675 emit_int8(0x66); // size prefix
2676 case 10:
2677 emit_int8(0x66); // size prefix
2678 case 9:
2679 emit_int8(0x66); // size prefix
2680 case 8:
2681 addr_nop_8();
2682 break;
2683 case 7:
2684 addr_nop_7();
2685 break;
2686 case 6:
2687 emit_int8(0x66); // size prefix
2688 case 5:
2689 addr_nop_5();
2690 break;
2691 case 4:
2692 addr_nop_4();
2693 break;
2694 case 3:
2695 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2696 emit_int8(0x66); // size prefix
2697 case 2:
2698 emit_int8(0x66); // size prefix
2699 case 1:
2700 emit_int8((unsigned char)0x90);
2701 // nop
2702 break;
2703 default:
2704 assert(i == 0, " ");
2705 }
2706 return;
2707 }
2708 if (UseAddressNop && VM_Version::is_amd()) {
2709 //
2710 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2711 // 1: 0x90
2712 // 2: 0x66 0x90
2713 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2714 // 4: 0x0F 0x1F 0x40 0x00
2715 // 5: 0x0F 0x1F 0x44 0x00 0x00
2716 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2717 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2718 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2719 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2720 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2721 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2722
2723 // The rest coding is AMD specific - use consecutive address nops
2724
2725 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2726 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2727 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2728 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2729 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2730 // Size prefixes (0x66) are added for larger sizes
2731
2732 while(i >= 22) {
2733 i -= 11;
2734 emit_int8(0x66); // size prefix
2735 emit_int8(0x66); // size prefix
2736 emit_int8(0x66); // size prefix
2737 addr_nop_8();
2738 }
2739 // Generate first nop for size between 21-12
2740 switch (i) {
2741 case 21:
2742 i -= 1;
2743 emit_int8(0x66); // size prefix
2744 case 20:
2745 case 19:
2746 i -= 1;
2747 emit_int8(0x66); // size prefix
2748 case 18:
2749 case 17:
2750 i -= 1;
2751 emit_int8(0x66); // size prefix
2752 case 16:
2753 case 15:
2754 i -= 8;
2755 addr_nop_8();
2756 break;
2757 case 14:
2758 case 13:
2759 i -= 7;
2760 addr_nop_7();
2761 break;
2762 case 12:
2763 i -= 6;
2764 emit_int8(0x66); // size prefix
2765 addr_nop_5();
2766 break;
2767 default:
2768 assert(i < 12, " ");
2769 }
2770
2771 // Generate second nop for size between 11-1
2772 switch (i) {
2773 case 11:
2774 emit_int8(0x66); // size prefix
2775 case 10:
2776 emit_int8(0x66); // size prefix
2777 case 9:
2778 emit_int8(0x66); // size prefix
2779 case 8:
2780 addr_nop_8();
2781 break;
2782 case 7:
2783 addr_nop_7();
2784 break;
2785 case 6:
2786 emit_int8(0x66); // size prefix
2787 case 5:
2788 addr_nop_5();
2789 break;
2790 case 4:
2791 addr_nop_4();
2792 break;
2793 case 3:
2794 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2795 emit_int8(0x66); // size prefix
2796 case 2:
2797 emit_int8(0x66); // size prefix
2798 case 1:
2799 emit_int8((unsigned char)0x90);
2800 // nop
2801 break;
2802 default:
2803 assert(i == 0, " ");
2804 }
2805 return;
2806 }
2807
2808 // Using nops with size prefixes "0x66 0x90".
2809 // From AMD Optimization Guide:
2810 // 1: 0x90
2811 // 2: 0x66 0x90
2812 // 3: 0x66 0x66 0x90
2813 // 4: 0x66 0x66 0x66 0x90
2814 // 5: 0x66 0x66 0x90 0x66 0x90
2815 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2816 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2817 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2818 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2819 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2820 //
2821 while(i > 12) {
2822 i -= 4;
2823 emit_int8(0x66); // size prefix
2824 emit_int8(0x66);
2825 emit_int8(0x66);
2826 emit_int8((unsigned char)0x90);
2827 // nop
2828 }
2829 // 1 - 12 nops
2830 if(i > 8) {
2831 if(i > 9) {
2832 i -= 1;
2833 emit_int8(0x66);
2834 }
2835 i -= 3;
2836 emit_int8(0x66);
2837 emit_int8(0x66);
2838 emit_int8((unsigned char)0x90);
2839 }
2840 // 1 - 8 nops
2841 if(i > 4) {
2842 if(i > 6) {
2843 i -= 1;
2844 emit_int8(0x66);
2845 }
2846 i -= 3;
2847 emit_int8(0x66);
2848 emit_int8(0x66);
2849 emit_int8((unsigned char)0x90);
2850 }
2851 switch (i) {
2852 case 4:
2853 emit_int8(0x66);
2854 case 3:
2855 emit_int8(0x66);
2856 case 2:
2857 emit_int8(0x66);
2858 case 1:
2859 emit_int8((unsigned char)0x90);
2860 break;
2861 default:
2862 assert(i == 0, " ");
2863 }
2864 }
2865
2866 void Assembler::notl(Register dst) {
2867 int encode = prefix_and_encode(dst->encoding());
2868 emit_int8((unsigned char)0xF7);
2869 emit_int8((unsigned char)(0xD0 | encode));
2870 }
2871
2872 void Assembler::orl(Address dst, int32_t imm32) {
2873 InstructionMark im(this);
2874 prefix(dst);
2875 emit_arith_operand(0x81, rcx, dst, imm32);
2876 }
2877
2878 void Assembler::orl(Register dst, int32_t imm32) {
2879 prefix(dst);
2880 emit_arith(0x81, 0xC8, dst, imm32);
2881 }
2882
2883 void Assembler::orl(Register dst, Address src) {
2884 InstructionMark im(this);
2885 prefix(src, dst);
2886 emit_int8(0x0B);
2887 emit_operand(dst, src);
2888 }
2889
2890 void Assembler::orl(Register dst, Register src) {
2891 (void) prefix_and_encode(dst->encoding(), src->encoding());
2892 emit_arith(0x0B, 0xC0, dst, src);
2893 }
2894
2895 void Assembler::orl(Address dst, Register src) {
2896 InstructionMark im(this);
2897 prefix(dst, src);
2898 emit_int8(0x09);
2899 emit_operand(src, dst);
2900 }
2901
2902 void Assembler::packuswb(XMMRegister dst, Address src) {
2903 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2904 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2905 if (VM_Version::supports_evex()) {
2906 tuple_type = EVEX_FV;
2907 input_size_in_bits = EVEX_32bit;
2908 }
2909 emit_simd_arith(0x67, dst, src, VEX_SIMD_66,
2910 false, (VM_Version::supports_avx512dq() == false));
2911 }
2912
2913 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2914 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2915 emit_simd_arith(0x67, dst, src, VEX_SIMD_66,
2916 false, (VM_Version::supports_avx512dq() == false));
2917 }
2918
2919 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2920 assert(UseAVX > 0, "some form of AVX must be enabled");
2921 emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector_len,
2922 false, (VM_Version::supports_avx512dq() == false));
2923 }
2924
2925 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
2926 assert(VM_Version::supports_avx2(), "");
2927 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false,
2928 VEX_OPCODE_0F_3A, true, vector_len);
2929 emit_int8(0x00);
2930 emit_int8(0xC0 | encode);
2931 emit_int8(imm8);
2932 }
2933
2934 void Assembler::pause() {
2935 emit_int8((unsigned char)0xF3);
2936 emit_int8((unsigned char)0x90);
2937 }
2938
2939 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2940 assert(VM_Version::supports_sse4_2(), "");
2941 InstructionMark im(this);
2942 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, false, VEX_OPCODE_0F_3A,
2943 false, AVX_128bit, true);
2944 emit_int8(0x61);
2945 emit_operand(dst, src);
2946 emit_int8(imm8);
2947 }
2948
2949 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2950 assert(VM_Version::supports_sse4_2(), "");
2951 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false,
2952 VEX_OPCODE_0F_3A, false, AVX_128bit, true);
2953 emit_int8(0x61);
2954 emit_int8((unsigned char)(0xC0 | encode));
2955 emit_int8(imm8);
2956 }
2957
2958 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
2959 assert(VM_Version::supports_sse4_1(), "");
2960 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2961 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2962 emit_int8(0x16);
2963 emit_int8((unsigned char)(0xC0 | encode));
2964 emit_int8(imm8);
2965 }
2966
2967 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
2968 assert(VM_Version::supports_sse4_1(), "");
2969 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2970 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2971 emit_int8(0x16);
2972 emit_int8((unsigned char)(0xC0 | encode));
2973 emit_int8(imm8);
2974 }
2975
2976 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
2977 assert(VM_Version::supports_sse4_1(), "");
2978 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2979 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2980 emit_int8(0x22);
2981 emit_int8((unsigned char)(0xC0 | encode));
2982 emit_int8(imm8);
2983 }
2984
2985 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
2986 assert(VM_Version::supports_sse4_1(), "");
2987 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2988 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2989 emit_int8(0x22);
2990 emit_int8((unsigned char)(0xC0 | encode));
2991 emit_int8(imm8);
2992 }
2993
2994 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
2995 assert(VM_Version::supports_sse4_1(), "");
2996 if (VM_Version::supports_evex()) {
2997 tuple_type = EVEX_HVM;
2998 }
2999 InstructionMark im(this);
3000 simd_prefix(dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38);
3001 emit_int8(0x30);
3002 emit_operand(dst, src);
3003 }
3004
3005 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3006 assert(VM_Version::supports_sse4_1(), "");
3007 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38);
3008 emit_int8(0x30);
3009 emit_int8((unsigned char)(0xC0 | encode));
3010 }
3011
3012 // generic
3013 void Assembler::pop(Register dst) {
3014 int encode = prefix_and_encode(dst->encoding());
3015 emit_int8(0x58 | encode);
3016 }
3017
3018 void Assembler::popcntl(Register dst, Address src) {
3019 assert(VM_Version::supports_popcnt(), "must support");
3020 InstructionMark im(this);
3021 emit_int8((unsigned char)0xF3);
3022 prefix(src, dst);
3023 emit_int8(0x0F);
3024 emit_int8((unsigned char)0xB8);
3025 emit_operand(dst, src);
3026 }
3027
3028 void Assembler::popcntl(Register dst, Register src) {
3029 assert(VM_Version::supports_popcnt(), "must support");
3030 emit_int8((unsigned char)0xF3);
3031 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3032 emit_int8(0x0F);
3033 emit_int8((unsigned char)0xB8);
3034 emit_int8((unsigned char)(0xC0 | encode));
3035 }
3036
3037 void Assembler::popf() {
3038 emit_int8((unsigned char)0x9D);
3039 }
3040
3041 #ifndef _LP64 // no 32bit push/pop on amd64
3042 void Assembler::popl(Address dst) {
3043 // NOTE: this will adjust stack by 8byte on 64bits
3044 InstructionMark im(this);
3045 prefix(dst);
3046 emit_int8((unsigned char)0x8F);
3047 emit_operand(rax, dst);
3048 }
3049 #endif
3050
3051 void Assembler::prefetch_prefix(Address src) {
3052 prefix(src);
3053 emit_int8(0x0F);
3054 }
3055
3056 void Assembler::prefetchnta(Address src) {
3057 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3058 InstructionMark im(this);
3059 prefetch_prefix(src);
3060 emit_int8(0x18);
3061 emit_operand(rax, src); // 0, src
3062 }
3063
3064 void Assembler::prefetchr(Address src) {
3065 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3066 InstructionMark im(this);
3067 prefetch_prefix(src);
3068 emit_int8(0x0D);
3069 emit_operand(rax, src); // 0, src
3070 }
3071
3072 void Assembler::prefetcht0(Address src) {
3073 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3074 InstructionMark im(this);
3075 prefetch_prefix(src);
3076 emit_int8(0x18);
3077 emit_operand(rcx, src); // 1, src
3078 }
3079
3080 void Assembler::prefetcht1(Address src) {
3081 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3082 InstructionMark im(this);
3083 prefetch_prefix(src);
3084 emit_int8(0x18);
3085 emit_operand(rdx, src); // 2, src
3086 }
3087
3088 void Assembler::prefetcht2(Address src) {
3089 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3090 InstructionMark im(this);
3091 prefetch_prefix(src);
3092 emit_int8(0x18);
3093 emit_operand(rbx, src); // 3, src
3094 }
3095
3096 void Assembler::prefetchw(Address src) {
3097 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3098 InstructionMark im(this);
3099 prefetch_prefix(src);
3100 emit_int8(0x0D);
3101 emit_operand(rcx, src); // 1, src
3102 }
3103
3104 void Assembler::prefix(Prefix p) {
3105 emit_int8(p);
3106 }
3107
3108 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3109 assert(VM_Version::supports_ssse3(), "");
3110 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38,
3111 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3112 emit_int8(0x00);
3113 emit_int8((unsigned char)(0xC0 | encode));
3114 }
3115
3116 void Assembler::pshufb(XMMRegister dst, Address src) {
3117 assert(VM_Version::supports_ssse3(), "");
3118 if (VM_Version::supports_evex()) {
3119 tuple_type = EVEX_FVM;
3120 }
3121 InstructionMark im(this);
3122 simd_prefix(dst, dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38,
3123 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3124 emit_int8(0x00);
3125 emit_operand(dst, src);
3126 }
3127
3128 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
3129 assert(isByte(mode), "invalid value");
3130 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3131 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
3132 emit_int8(mode & 0xFF);
3133
3134 }
3135
3136 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
3137 assert(isByte(mode), "invalid value");
3138 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3139 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3140 if (VM_Version::supports_evex()) {
3141 tuple_type = EVEX_FV;
3142 input_size_in_bits = EVEX_32bit;
3143 }
3144 InstructionMark im(this);
3145 simd_prefix(dst, src, VEX_SIMD_66, false);
3146 emit_int8(0x70);
3147 emit_operand(dst, src);
3148 emit_int8(mode & 0xFF);
3149 }
3150
3151 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3152 assert(isByte(mode), "invalid value");
3153 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3154 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2, false,
3155 (VM_Version::supports_avx512bw() == false));
3156 emit_int8(mode & 0xFF);
3157 }
3158
3159 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3160 assert(isByte(mode), "invalid value");
3161 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3162 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3163 if (VM_Version::supports_evex()) {
3164 tuple_type = EVEX_FVM;
3165 }
3166 InstructionMark im(this);
3167 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, false, VEX_OPCODE_0F,
3168 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3169 emit_int8(0x70);
3170 emit_operand(dst, src);
3171 emit_int8(mode & 0xFF);
3172 }
3173
3174 void Assembler::psrldq(XMMRegister dst, int shift) {
3175 // Shift 128 bit value in xmm register by number of bytes.
3176 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3177 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, true, VEX_OPCODE_0F, false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3178 emit_int8(0x73);
3179 emit_int8((unsigned char)(0xC0 | encode));
3180 emit_int8(shift);
3181 }
3182
3183 void Assembler::pslldq(XMMRegister dst, int shift) {
3184 // Shift left 128 bit value in xmm register by number of bytes.
3185 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3186 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, true, VEX_OPCODE_0F, false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3187 emit_int8(0x73);
3188 emit_int8((unsigned char)(0xC0 | encode));
3189 emit_int8(shift);
3190 }
3191
3192 void Assembler::ptest(XMMRegister dst, Address src) {
3193 assert(VM_Version::supports_sse4_1(), "");
3194 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3195 InstructionMark im(this);
3196 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, false,
3197 VEX_OPCODE_0F_38, false, AVX_128bit, true);
3198 emit_int8(0x17);
3199 emit_operand(dst, src);
3200 }
3201
3202 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3203 assert(VM_Version::supports_sse4_1(), "");
3204 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false,
3205 VEX_OPCODE_0F_38, false, AVX_128bit, true);
3206 emit_int8(0x17);
3207 emit_int8((unsigned char)(0xC0 | encode));
3208 }
3209
3210 void Assembler::vptest(XMMRegister dst, Address src) {
3211 assert(VM_Version::supports_avx(), "");
3212 InstructionMark im(this);
3213 int vector_len = AVX_256bit;
3214 assert(dst != xnoreg, "sanity");
3215 int dst_enc = dst->encoding();
3216 // swap src<->dst for encoding
3217 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector_len, true, false);
3218 emit_int8(0x17);
3219 emit_operand(dst, src);
3220 }
3221
3222 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
3223 assert(VM_Version::supports_avx(), "");
3224 int vector_len = AVX_256bit;
3225 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
3226 vector_len, VEX_OPCODE_0F_38, true, false);
3227 emit_int8(0x17);
3228 emit_int8((unsigned char)(0xC0 | encode));
3229 }
3230
3231 void Assembler::punpcklbw(XMMRegister dst, Address src) {
3232 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3233 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3234 if (VM_Version::supports_evex()) {
3235 tuple_type = EVEX_FVM;
3236 }
3237 emit_simd_arith(0x60, dst, src, VEX_SIMD_66, false, (VM_Version::supports_avx512vlbw() == false));
3238 }
3239
3240 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3241 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3242 emit_simd_arith(0x60, dst, src, VEX_SIMD_66, false, (VM_Version::supports_avx512vlbw() == false));
3243 }
3244
3245 void Assembler::punpckldq(XMMRegister dst, Address src) {
3246 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3247 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3248 if (VM_Version::supports_evex()) {
3249 tuple_type = EVEX_FV;
3250 input_size_in_bits = EVEX_32bit;
3251 }
3252 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
3253 }
3254
3255 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
3256 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3257 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
3258 }
3259
3260 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
3261 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3262 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66);
3263 }
3264
3265 void Assembler::push(int32_t imm32) {
3266 // in 64bits we push 64bits onto the stack but only
3267 // take a 32bit immediate
3268 emit_int8(0x68);
3269 emit_int32(imm32);
3270 }
3271
3272 void Assembler::push(Register src) {
3273 int encode = prefix_and_encode(src->encoding());
3274
3275 emit_int8(0x50 | encode);
3276 }
3277
3278 void Assembler::pushf() {
3279 emit_int8((unsigned char)0x9C);
3280 }
3281
3282 #ifndef _LP64 // no 32bit push/pop on amd64
3283 void Assembler::pushl(Address src) {
3284 // Note this will push 64bit on 64bit
3285 InstructionMark im(this);
3286 prefix(src);
3287 emit_int8((unsigned char)0xFF);
3288 emit_operand(rsi, src);
3289 }
3290 #endif
3291
3292 void Assembler::rcll(Register dst, int imm8) {
3293 assert(isShiftCount(imm8), "illegal shift count");
3294 int encode = prefix_and_encode(dst->encoding());
3295 if (imm8 == 1) {
3296 emit_int8((unsigned char)0xD1);
3297 emit_int8((unsigned char)(0xD0 | encode));
3298 } else {
3299 emit_int8((unsigned char)0xC1);
3300 emit_int8((unsigned char)0xD0 | encode);
3301 emit_int8(imm8);
3302 }
3303 }
3304
3305 void Assembler::rdtsc() {
3306 emit_int8((unsigned char)0x0F);
3307 emit_int8((unsigned char)0x31);
3308 }
3309
3310 // copies data from [esi] to [edi] using rcx pointer sized words
3311 // generic
3312 void Assembler::rep_mov() {
3313 emit_int8((unsigned char)0xF3);
3314 // MOVSQ
3315 LP64_ONLY(prefix(REX_W));
3316 emit_int8((unsigned char)0xA5);
3317 }
3318
3319 // sets rcx bytes with rax, value at [edi]
3320 void Assembler::rep_stosb() {
3321 emit_int8((unsigned char)0xF3); // REP
3322 LP64_ONLY(prefix(REX_W));
3323 emit_int8((unsigned char)0xAA); // STOSB
3324 }
3325
3326 // sets rcx pointer sized words with rax, value at [edi]
3327 // generic
3328 void Assembler::rep_stos() {
3329 emit_int8((unsigned char)0xF3); // REP
3330 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
3331 emit_int8((unsigned char)0xAB);
3332 }
3333
3334 // scans rcx pointer sized words at [edi] for occurance of rax,
3335 // generic
3336 void Assembler::repne_scan() { // repne_scan
3337 emit_int8((unsigned char)0xF2);
3338 // SCASQ
3339 LP64_ONLY(prefix(REX_W));
3340 emit_int8((unsigned char)0xAF);
3341 }
3342
3343 #ifdef _LP64
3344 // scans rcx 4 byte words at [edi] for occurance of rax,
3345 // generic
3346 void Assembler::repne_scanl() { // repne_scan
3347 emit_int8((unsigned char)0xF2);
3348 // SCASL
3349 emit_int8((unsigned char)0xAF);
3350 }
3351 #endif
3352
3353 void Assembler::ret(int imm16) {
3354 if (imm16 == 0) {
3355 emit_int8((unsigned char)0xC3);
3356 } else {
3357 emit_int8((unsigned char)0xC2);
3358 emit_int16(imm16);
3359 }
3360 }
3361
3362 void Assembler::sahf() {
3363 #ifdef _LP64
3364 // Not supported in 64bit mode
3365 ShouldNotReachHere();
3366 #endif
3367 emit_int8((unsigned char)0x9E);
3368 }
3369
3370 void Assembler::sarl(Register dst, int imm8) {
3371 int encode = prefix_and_encode(dst->encoding());
3372 assert(isShiftCount(imm8), "illegal shift count");
3373 if (imm8 == 1) {
3374 emit_int8((unsigned char)0xD1);
3375 emit_int8((unsigned char)(0xF8 | encode));
3376 } else {
3377 emit_int8((unsigned char)0xC1);
3378 emit_int8((unsigned char)(0xF8 | encode));
3379 emit_int8(imm8);
3380 }
3381 }
3382
3383 void Assembler::sarl(Register dst) {
3384 int encode = prefix_and_encode(dst->encoding());
3385 emit_int8((unsigned char)0xD3);
3386 emit_int8((unsigned char)(0xF8 | encode));
3387 }
3388
3389 void Assembler::sbbl(Address dst, int32_t imm32) {
3390 InstructionMark im(this);
3391 prefix(dst);
3392 emit_arith_operand(0x81, rbx, dst, imm32);
3393 }
3394
3395 void Assembler::sbbl(Register dst, int32_t imm32) {
3396 prefix(dst);
3397 emit_arith(0x81, 0xD8, dst, imm32);
3398 }
3399
3400
3401 void Assembler::sbbl(Register dst, Address src) {
3402 InstructionMark im(this);
3403 prefix(src, dst);
3404 emit_int8(0x1B);
3405 emit_operand(dst, src);
3406 }
3407
3408 void Assembler::sbbl(Register dst, Register src) {
3409 (void) prefix_and_encode(dst->encoding(), src->encoding());
3410 emit_arith(0x1B, 0xC0, dst, src);
3411 }
3412
3413 void Assembler::setb(Condition cc, Register dst) {
3414 assert(0 <= cc && cc < 16, "illegal cc");
3415 int encode = prefix_and_encode(dst->encoding(), true);
3416 emit_int8(0x0F);
3417 emit_int8((unsigned char)0x90 | cc);
3418 emit_int8((unsigned char)(0xC0 | encode));
3419 }
3420
3421 void Assembler::shll(Register dst, int imm8) {
3422 assert(isShiftCount(imm8), "illegal shift count");
3423 int encode = prefix_and_encode(dst->encoding());
3424 if (imm8 == 1 ) {
3425 emit_int8((unsigned char)0xD1);
3426 emit_int8((unsigned char)(0xE0 | encode));
3427 } else {
3428 emit_int8((unsigned char)0xC1);
3429 emit_int8((unsigned char)(0xE0 | encode));
3430 emit_int8(imm8);
3431 }
3432 }
3433
3434 void Assembler::shll(Register dst) {
3435 int encode = prefix_and_encode(dst->encoding());
3436 emit_int8((unsigned char)0xD3);
3437 emit_int8((unsigned char)(0xE0 | encode));
3438 }
3439
3440 void Assembler::shrl(Register dst, int imm8) {
3441 assert(isShiftCount(imm8), "illegal shift count");
3442 int encode = prefix_and_encode(dst->encoding());
3443 emit_int8((unsigned char)0xC1);
3444 emit_int8((unsigned char)(0xE8 | encode));
3445 emit_int8(imm8);
3446 }
3447
3448 void Assembler::shrl(Register dst) {
3449 int encode = prefix_and_encode(dst->encoding());
3450 emit_int8((unsigned char)0xD3);
3451 emit_int8((unsigned char)(0xE8 | encode));
3452 }
3453
3454 // copies a single word from [esi] to [edi]
3455 void Assembler::smovl() {
3456 emit_int8((unsigned char)0xA5);
3457 }
3458
3459 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
3460 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3461 if (VM_Version::supports_evex()) {
3462 emit_simd_arith_q(0x51, dst, src, VEX_SIMD_F2);
3463 } else {
3464 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
3465 }
3466 }
3467
3468 void Assembler::sqrtsd(XMMRegister dst, Address src) {
3469 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3470 if (VM_Version::supports_evex()) {
3471 tuple_type = EVEX_T1S;
3472 input_size_in_bits = EVEX_64bit;
3473 emit_simd_arith_q(0x51, dst, src, VEX_SIMD_F2);
3474 } else {
3475 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
3476 }
3477 }
3478
3479 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
3480 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3481 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
3482 }
3483
3484 void Assembler::std() {
3485 emit_int8((unsigned char)0xFD);
3486 }
3487
3488 void Assembler::sqrtss(XMMRegister dst, Address src) {
3489 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3490 if (VM_Version::supports_evex()) {
3491 tuple_type = EVEX_T1S;
3492 input_size_in_bits = EVEX_32bit;
3493 }
3494 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
3495 }
3496
3497 void Assembler::stmxcsr( Address dst) {
3498 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3499 InstructionMark im(this);
3500 prefix(dst);
3501 emit_int8(0x0F);
3502 emit_int8((unsigned char)0xAE);
3503 emit_operand(as_Register(3), dst);
3504 }
3505
3506 void Assembler::subl(Address dst, int32_t imm32) {
3507 InstructionMark im(this);
3508 prefix(dst);
3509 emit_arith_operand(0x81, rbp, dst, imm32);
3510 }
3511
3512 void Assembler::subl(Address dst, Register src) {
3513 InstructionMark im(this);
3514 prefix(dst, src);
3515 emit_int8(0x29);
3516 emit_operand(src, dst);
3517 }
3518
3519 void Assembler::subl(Register dst, int32_t imm32) {
3520 prefix(dst);
3521 emit_arith(0x81, 0xE8, dst, imm32);
3522 }
3523
3524 // Force generation of a 4 byte immediate value even if it fits into 8bit
3525 void Assembler::subl_imm32(Register dst, int32_t imm32) {
3526 prefix(dst);
3527 emit_arith_imm32(0x81, 0xE8, dst, imm32);
3528 }
3529
3530 void Assembler::subl(Register dst, Address src) {
3531 InstructionMark im(this);
3532 prefix(src, dst);
3533 emit_int8(0x2B);
3534 emit_operand(dst, src);
3535 }
3536
3537 void Assembler::subl(Register dst, Register src) {
3538 (void) prefix_and_encode(dst->encoding(), src->encoding());
3539 emit_arith(0x2B, 0xC0, dst, src);
3540 }
3541
3542 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
3543 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3544 if (VM_Version::supports_evex()) {
3545 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_F2);
3546 } else {
3547 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
3548 }
3549 }
3550
3551 void Assembler::subsd(XMMRegister dst, Address src) {
3552 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3553 if (VM_Version::supports_evex()) {
3554 tuple_type = EVEX_T1S;
3555 input_size_in_bits = EVEX_64bit;
3556 }
3557 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_F2);
3558 }
3559
3560 void Assembler::subss(XMMRegister dst, XMMRegister src) {
3561 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3562 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
3563 }
3564
3565 void Assembler::subss(XMMRegister dst, Address src) {
3566 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3567 if (VM_Version::supports_evex()) {
3568 tuple_type = EVEX_T1S;
3569 input_size_in_bits = EVEX_32bit;
3570 }
3571 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
3572 }
3573
3574 void Assembler::testb(Register dst, int imm8) {
3575 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
3576 (void) prefix_and_encode(dst->encoding(), true);
3577 emit_arith_b(0xF6, 0xC0, dst, imm8);
3578 }
3579
3580 void Assembler::testl(Register dst, int32_t imm32) {
3581 // not using emit_arith because test
3582 // doesn't support sign-extension of
3583 // 8bit operands
3584 int encode = dst->encoding();
3585 if (encode == 0) {
3586 emit_int8((unsigned char)0xA9);
3587 } else {
3588 encode = prefix_and_encode(encode);
3589 emit_int8((unsigned char)0xF7);
3590 emit_int8((unsigned char)(0xC0 | encode));
3591 }
3592 emit_int32(imm32);
3593 }
3594
3595 void Assembler::testl(Register dst, Register src) {
3596 (void) prefix_and_encode(dst->encoding(), src->encoding());
3597 emit_arith(0x85, 0xC0, dst, src);
3598 }
3599
3600 void Assembler::testl(Register dst, Address src) {
3601 InstructionMark im(this);
3602 prefix(src, dst);
3603 emit_int8((unsigned char)0x85);
3604 emit_operand(dst, src);
3605 }
3606
3607 void Assembler::tzcntl(Register dst, Register src) {
3608 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
3609 emit_int8((unsigned char)0xF3);
3610 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3611 emit_int8(0x0F);
3612 emit_int8((unsigned char)0xBC);
3613 emit_int8((unsigned char)0xC0 | encode);
3614 }
3615
3616 void Assembler::tzcntq(Register dst, Register src) {
3617 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
3618 emit_int8((unsigned char)0xF3);
3619 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3620 emit_int8(0x0F);
3621 emit_int8((unsigned char)0xBC);
3622 emit_int8((unsigned char)(0xC0 | encode));
3623 }
3624
3625 void Assembler::ucomisd(XMMRegister dst, Address src) {
3626 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3627 if (VM_Version::supports_evex()) {
3628 tuple_type = EVEX_T1S;
3629 input_size_in_bits = EVEX_64bit;
3630 emit_simd_arith_nonds_q(0x2E, dst, src, VEX_SIMD_66, true);
3631 } else {
3632 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
3633 }
3634 }
3635
3636 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
3637 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3638 if (VM_Version::supports_evex()) {
3639 emit_simd_arith_nonds_q(0x2E, dst, src, VEX_SIMD_66, true);
3640 } else {
3641 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
3642 }
3643 }
3644
3645 void Assembler::ucomiss(XMMRegister dst, Address src) {
3646 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3647 if (VM_Version::supports_evex()) {
3648 tuple_type = EVEX_T1S;
3649 input_size_in_bits = EVEX_32bit;
3650 }
3651 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE, true);
3652 }
3653
3654 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
3655 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3656 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE, true);
3657 }
3658
3659 void Assembler::xabort(int8_t imm8) {
3660 emit_int8((unsigned char)0xC6);
3661 emit_int8((unsigned char)0xF8);
3662 emit_int8((unsigned char)(imm8 & 0xFF));
3663 }
3664
3665 void Assembler::xaddl(Address dst, Register src) {
3666 InstructionMark im(this);
3667 prefix(dst, src);
3668 emit_int8(0x0F);
3669 emit_int8((unsigned char)0xC1);
3670 emit_operand(src, dst);
3671 }
3672
3673 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
3674 InstructionMark im(this);
3675 relocate(rtype);
3676 if (abort.is_bound()) {
3677 address entry = target(abort);
3678 assert(entry != NULL, "abort entry NULL");
3679 intptr_t offset = entry - pc();
3680 emit_int8((unsigned char)0xC7);
3681 emit_int8((unsigned char)0xF8);
3682 emit_int32(offset - 6); // 2 opcode + 4 address
3683 } else {
3684 abort.add_patch_at(code(), locator());
3685 emit_int8((unsigned char)0xC7);
3686 emit_int8((unsigned char)0xF8);
3687 emit_int32(0);
3688 }
3689 }
3690
3691 void Assembler::xchgl(Register dst, Address src) { // xchg
3692 InstructionMark im(this);
3693 prefix(src, dst);
3694 emit_int8((unsigned char)0x87);
3695 emit_operand(dst, src);
3696 }
3697
3698 void Assembler::xchgl(Register dst, Register src) {
3699 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3700 emit_int8((unsigned char)0x87);
3701 emit_int8((unsigned char)(0xC0 | encode));
3702 }
3703
3704 void Assembler::xend() {
3705 emit_int8((unsigned char)0x0F);
3706 emit_int8((unsigned char)0x01);
3707 emit_int8((unsigned char)0xD5);
3708 }
3709
3710 void Assembler::xgetbv() {
3711 emit_int8(0x0F);
3712 emit_int8(0x01);
3713 emit_int8((unsigned char)0xD0);
3714 }
3715
3716 void Assembler::xorl(Register dst, int32_t imm32) {
3717 prefix(dst);
3718 emit_arith(0x81, 0xF0, dst, imm32);
3719 }
3720
3721 void Assembler::xorl(Register dst, Address src) {
3722 InstructionMark im(this);
3723 prefix(src, dst);
3724 emit_int8(0x33);
3725 emit_operand(dst, src);
3726 }
3727
3728 void Assembler::xorl(Register dst, Register src) {
3729 (void) prefix_and_encode(dst->encoding(), src->encoding());
3730 emit_arith(0x33, 0xC0, dst, src);
3731 }
3732
3733
3734 // AVX 3-operands scalar float-point arithmetic instructions
3735
3736 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
3737 assert(VM_Version::supports_avx(), "");
3738 if (VM_Version::supports_evex()) {
3739 tuple_type = EVEX_T1S;
3740 input_size_in_bits = EVEX_64bit;
3741 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3742 } else {
3743 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3744 }
3745 }
3746
3747 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3748 assert(VM_Version::supports_avx(), "");
3749 if (VM_Version::supports_evex()) {
3750 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3751 } else {
3752 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3753 }
3754 }
3755
3756 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
3757 assert(VM_Version::supports_avx(), "");
3758 if (VM_Version::supports_evex()) {
3759 tuple_type = EVEX_T1S;
3760 input_size_in_bits = EVEX_32bit;
3761 }
3762 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3763 }
3764
3765 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3766 assert(VM_Version::supports_avx(), "");
3767 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3768 }
3769
3770 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
3771 assert(VM_Version::supports_avx(), "");
3772 if (VM_Version::supports_evex()) {
3773 tuple_type = EVEX_T1S;
3774 input_size_in_bits = EVEX_64bit;
3775 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3776 } else {
3777 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3778 }
3779 }
3780
3781 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3782 assert(VM_Version::supports_avx(), "");
3783 if (VM_Version::supports_evex()) {
3784 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3785 } else {
3786 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3787 }
3788 }
3789
3790 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
3791 assert(VM_Version::supports_avx(), "");
3792 if (VM_Version::supports_evex()) {
3793 tuple_type = EVEX_T1S;
3794 input_size_in_bits = EVEX_32bit;
3795 }
3796 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3797 }
3798
3799 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3800 assert(VM_Version::supports_avx(), "");
3801 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3802 }
3803
3804 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
3805 assert(VM_Version::supports_avx(), "");
3806 if (VM_Version::supports_evex()) {
3807 tuple_type = EVEX_T1S;
3808 input_size_in_bits = EVEX_64bit;
3809 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3810 } else {
3811 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3812 }
3813 }
3814
3815 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3816 assert(VM_Version::supports_avx(), "");
3817 if (VM_Version::supports_evex()) {
3818 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3819 } else {
3820 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3821 }
3822 }
3823
3824 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
3825 assert(VM_Version::supports_avx(), "");
3826 if (VM_Version::supports_evex()) {
3827 tuple_type = EVEX_T1S;
3828 input_size_in_bits = EVEX_32bit;
3829 }
3830 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3831 }
3832
3833 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3834 assert(VM_Version::supports_avx(), "");
3835 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3836 }
3837
3838 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
3839 assert(VM_Version::supports_avx(), "");
3840 if (VM_Version::supports_evex()) {
3841 tuple_type = EVEX_T1S;
3842 input_size_in_bits = EVEX_64bit;
3843 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3844 } else {
3845 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3846 }
3847 }
3848
3849 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3850 assert(VM_Version::supports_avx(), "");
3851 if (VM_Version::supports_evex()) {
3852 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3853 } else {
3854 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3855 }
3856 }
3857
3858 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
3859 assert(VM_Version::supports_avx(), "");
3860 if (VM_Version::supports_evex()) {
3861 tuple_type = EVEX_T1S;
3862 input_size_in_bits = EVEX_32bit;
3863 }
3864 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3865 }
3866
3867 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3868 assert(VM_Version::supports_avx(), "");
3869 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3870 }
3871
3872 //====================VECTOR ARITHMETIC=====================================
3873
3874 // Float-point vector arithmetic
3875
3876 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
3877 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3878 if (VM_Version::supports_evex()) {
3879 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_66);
3880 } else {
3881 emit_simd_arith(0x58, dst, src, VEX_SIMD_66);
3882 }
3883 }
3884
3885 void Assembler::addps(XMMRegister dst, XMMRegister src) {
3886 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3887 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE);
3888 }
3889
3890 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3891 assert(VM_Version::supports_avx(), "");
3892 if (VM_Version::supports_evex()) {
3893 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3894 } else {
3895 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3896 }
3897 }
3898
3899 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3900 assert(VM_Version::supports_avx(), "");
3901 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector_len);
3902 }
3903
3904 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3905 assert(VM_Version::supports_avx(), "");
3906 if (VM_Version::supports_evex()) {
3907 tuple_type = EVEX_FV;
3908 input_size_in_bits = EVEX_64bit;
3909 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3910 } else {
3911 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3912 }
3913 }
3914
3915 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3916 assert(VM_Version::supports_avx(), "");
3917 if (VM_Version::supports_evex()) {
3918 tuple_type = EVEX_FV;
3919 input_size_in_bits = EVEX_32bit;
3920 }
3921 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector_len);
3922 }
3923
3924 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
3925 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3926 if (VM_Version::supports_evex()) {
3927 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_66);
3928 } else {
3929 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66);
3930 }
3931 }
3932
3933 void Assembler::subps(XMMRegister dst, XMMRegister src) {
3934 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3935 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE);
3936 }
3937
3938 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3939 assert(VM_Version::supports_avx(), "");
3940 if (VM_Version::supports_evex()) {
3941 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3942 } else {
3943 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3944 }
3945 }
3946
3947 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3948 assert(VM_Version::supports_avx(), "");
3949 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector_len);
3950 }
3951
3952 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3953 assert(VM_Version::supports_avx(), "");
3954 if (VM_Version::supports_evex()) {
3955 tuple_type = EVEX_FV;
3956 input_size_in_bits = EVEX_64bit;
3957 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3958 } else {
3959 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3960 }
3961 }
3962
3963 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3964 assert(VM_Version::supports_avx(), "");
3965 if (VM_Version::supports_evex()) {
3966 tuple_type = EVEX_FV;
3967 input_size_in_bits = EVEX_32bit;
3968 }
3969 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector_len);
3970 }
3971
3972 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
3973 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3974 if (VM_Version::supports_evex()) {
3975 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_66);
3976 } else {
3977 emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
3978 }
3979 }
3980
3981 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
3982 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3983 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE);
3984 }
3985
3986 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3987 assert(VM_Version::supports_avx(), "");
3988 if (VM_Version::supports_evex()) {
3989 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
3990 } else {
3991 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
3992 }
3993 }
3994
3995 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3996 assert(VM_Version::supports_avx(), "");
3997 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector_len);
3998 }
3999
4000 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4001 assert(VM_Version::supports_avx(), "");
4002 if (VM_Version::supports_evex()) {
4003 tuple_type = EVEX_FV;
4004 input_size_in_bits = EVEX_64bit;
4005 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
4006 } else {
4007 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
4008 }
4009 }
4010
4011 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4012 assert(VM_Version::supports_avx(), "");
4013 if (VM_Version::supports_evex()) {
4014 tuple_type = EVEX_FV;
4015 input_size_in_bits = EVEX_32bit;
4016 }
4017 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector_len);
4018 }
4019
4020 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
4021 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4022 if (VM_Version::supports_evex()) {
4023 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_66);
4024 } else {
4025 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66);
4026 }
4027 }
4028
4029 void Assembler::divps(XMMRegister dst, XMMRegister src) {
4030 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4031 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE);
4032 }
4033
4034 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4035 assert(VM_Version::supports_avx(), "");
4036 if (VM_Version::supports_evex()) {
4037 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
4038 } else {
4039 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
4040 }
4041 }
4042
4043 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4044 assert(VM_Version::supports_avx(), "");
4045 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector_len);
4046 }
4047
4048 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4049 assert(VM_Version::supports_avx(), "");
4050 if (VM_Version::supports_evex()) {
4051 tuple_type = EVEX_FV;
4052 input_size_in_bits = EVEX_64bit;
4053 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
4054 } else {
4055 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
4056 }
4057 }
4058
4059 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4060 assert(VM_Version::supports_avx(), "");
4061 if (VM_Version::supports_evex()) {
4062 tuple_type = EVEX_FV;
4063 input_size_in_bits = EVEX_32bit;
4064 }
4065 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector_len);
4066 }
4067
4068 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
4069 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4070 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4071 emit_simd_arith_q(0x54, dst, src, VEX_SIMD_66);
4072 } else {
4073 emit_simd_arith(0x54, dst, src, VEX_SIMD_66, false, true);
4074 }
4075 }
4076
4077 void Assembler::andps(XMMRegister dst, XMMRegister src) {
4078 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4079 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE, false,
4080 (VM_Version::supports_avx512dq() == false));
4081 }
4082
4083 void Assembler::andps(XMMRegister dst, Address src) {
4084 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4085 if (VM_Version::supports_evex()) {
4086 tuple_type = EVEX_FV;
4087 input_size_in_bits = EVEX_32bit;
4088 }
4089 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE,
4090 false, (VM_Version::supports_avx512dq() == false));
4091 }
4092
4093 void Assembler::andpd(XMMRegister dst, Address src) {
4094 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4095 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4096 tuple_type = EVEX_FV;
4097 input_size_in_bits = EVEX_64bit;
4098 emit_simd_arith_q(0x54, dst, src, VEX_SIMD_66);
4099 } else {
4100 emit_simd_arith(0x54, dst, src, VEX_SIMD_66, false, true);
4101 }
4102 }
4103
4104 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4105 assert(VM_Version::supports_avx(), "");
4106 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4107 emit_vex_arith_q(0x54, dst, nds, src, VEX_SIMD_66, vector_len);
4108 } else {
4109 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector_len, true);
4110 }
4111 }
4112
4113 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4114 assert(VM_Version::supports_avx(), "");
4115 bool legacy_mode = (VM_Version::supports_avx512dq() == false);
4116 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector_len, legacy_mode);
4117 }
4118
4119 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4120 assert(VM_Version::supports_avx(), "");
4121 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4122 tuple_type = EVEX_FV;
4123 input_size_in_bits = EVEX_64bit;
4124 emit_vex_arith_q(0x54, dst, nds, src, VEX_SIMD_66, vector_len);
4125 } else {
4126 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector_len, true);
4127 }
4128 }
4129
4130 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4131 assert(VM_Version::supports_avx(), "");
4132 if (VM_Version::supports_evex()) {
4133 tuple_type = EVEX_FV;
4134 input_size_in_bits = EVEX_32bit;
4135 }
4136 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector_len,
4137 (VM_Version::supports_avx512dq() == false));
4138 }
4139
4140 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
4141 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4142 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4143 emit_simd_arith_q(0x57, dst, src, VEX_SIMD_66);
4144 } else {
4145 emit_simd_arith(0x57, dst, src, VEX_SIMD_66, false, true);
4146 }
4147 }
4148
4149 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
4150 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4151 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE,
4152 false, (VM_Version::supports_avx512dq() == false));
4153 }
4154
4155 void Assembler::xorpd(XMMRegister dst, Address src) {
4156 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4157 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4158 tuple_type = EVEX_FV;
4159 input_size_in_bits = EVEX_64bit;
4160 emit_simd_arith_q(0x57, dst, src, VEX_SIMD_66);
4161 } else {
4162 emit_simd_arith(0x57, dst, src, VEX_SIMD_66, false, true);
4163 }
4164 }
4165
4166 void Assembler::xorps(XMMRegister dst, Address src) {
4167 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4168 if (VM_Version::supports_evex()) {
4169 tuple_type = EVEX_FV;
4170 input_size_in_bits = EVEX_32bit;
4171 }
4172 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE, false,
4173 (VM_Version::supports_avx512dq() == false));
4174 }
4175
4176 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4177 assert(VM_Version::supports_avx(), "");
4178 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4179 emit_vex_arith_q(0x57, dst, nds, src, VEX_SIMD_66, vector_len);
4180 } else {
4181 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector_len, true);
4182 }
4183 }
4184
4185 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4186 assert(VM_Version::supports_avx(), "");
4187 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector_len,
4188 (VM_Version::supports_avx512dq() == false));
4189 }
4190
4191 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4192 assert(VM_Version::supports_avx(), "");
4193 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4194 tuple_type = EVEX_FV;
4195 input_size_in_bits = EVEX_64bit;
4196 emit_vex_arith_q(0x57, dst, nds, src, VEX_SIMD_66, vector_len);
4197 } else {
4198 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector_len, true);
4199 }
4200 }
4201
4202 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4203 assert(VM_Version::supports_avx(), "");
4204 if (VM_Version::supports_evex()) {
4205 tuple_type = EVEX_FV;
4206 input_size_in_bits = EVEX_32bit;
4207 }
4208 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector_len,
4209 (VM_Version::supports_avx512dq() == false));
4210 }
4211
4212 // Integer vector arithmetic
4213 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4214 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4215 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4216 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len,
4217 VEX_OPCODE_0F_38, true, false);
4218 emit_int8(0x01);
4219 emit_int8((unsigned char)(0xC0 | encode));
4220 }
4221
4222 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4223 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4224 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4225 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len,
4226 VEX_OPCODE_0F_38, true, false);
4227 emit_int8(0x02);
4228 emit_int8((unsigned char)(0xC0 | encode));
4229 }
4230
4231 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
4232 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4233 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66);
4234 }
4235
4236 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
4237 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4238 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66);
4239 }
4240
4241 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
4242 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4243 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66);
4244 }
4245
4246 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
4247 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4248 if (VM_Version::supports_evex()) {
4249 emit_simd_arith_q(0xD4, dst, src, VEX_SIMD_66);
4250 } else {
4251 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66);
4252 }
4253 }
4254
4255 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
4256 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4257 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
4258 VEX_OPCODE_0F_38, false, AVX_128bit, true);
4259 emit_int8(0x01);
4260 emit_int8((unsigned char)(0xC0 | encode));
4261 }
4262
4263 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
4264 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4265 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
4266 VEX_OPCODE_0F_38, false, AVX_128bit, true);
4267 emit_int8(0x02);
4268 emit_int8((unsigned char)(0xC0 | encode));
4269 }
4270
4271 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4272 assert(UseAVX > 0, "requires some form of AVX");
4273 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector_len,
4274 (VM_Version::supports_avx512bw() == false));
4275 }
4276
4277 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4278 assert(UseAVX > 0, "requires some form of AVX");
4279 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector_len,
4280 (VM_Version::supports_avx512bw() == false));
4281 }
4282
4283 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4284 assert(UseAVX > 0, "requires some form of AVX");
4285 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector_len);
4286 }
4287
4288 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4289 assert(UseAVX > 0, "requires some form of AVX");
4290 if (VM_Version::supports_evex()) {
4291 emit_vex_arith_q(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4292 } else {
4293 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4294 }
4295 }
4296
4297 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4298 assert(UseAVX > 0, "requires some form of AVX");
4299 if (VM_Version::supports_evex()) {
4300 tuple_type = EVEX_FVM;
4301 }
4302 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector_len);
4303 }
4304
4305 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4306 assert(UseAVX > 0, "requires some form of AVX");
4307 if (VM_Version::supports_evex()) {
4308 tuple_type = EVEX_FVM;
4309 }
4310 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector_len);
4311 }
4312
4313 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4314 assert(UseAVX > 0, "requires some form of AVX");
4315 if (VM_Version::supports_evex()) {
4316 tuple_type = EVEX_FV;
4317 input_size_in_bits = EVEX_32bit;
4318 }
4319 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector_len);
4320 }
4321
4322 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4323 assert(UseAVX > 0, "requires some form of AVX");
4324 if (VM_Version::supports_evex()) {
4325 tuple_type = EVEX_FV;
4326 input_size_in_bits = EVEX_64bit;
4327 emit_vex_arith_q(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4328 } else {
4329 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4330 }
4331 }
4332
4333 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
4334 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4335 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66);
4336 }
4337
4338 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
4339 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4340 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66);
4341 }
4342
4343 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
4344 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4345 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66);
4346 }
4347
4348 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
4349 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4350 if (VM_Version::supports_evex()) {
4351 emit_simd_arith_q(0xFB, dst, src, VEX_SIMD_66);
4352 } else {
4353 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66);
4354 }
4355 }
4356
4357 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4358 assert(UseAVX > 0, "requires some form of AVX");
4359 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector_len,
4360 (VM_Version::supports_avx512bw() == false));
4361 }
4362
4363 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4364 assert(UseAVX > 0, "requires some form of AVX");
4365 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector_len,
4366 (VM_Version::supports_avx512bw() == false));
4367 }
4368
4369 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4370 assert(UseAVX > 0, "requires some form of AVX");
4371 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector_len);
4372 }
4373
4374 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4375 assert(UseAVX > 0, "requires some form of AVX");
4376 if (VM_Version::supports_evex()) {
4377 emit_vex_arith_q(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4378 } else {
4379 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4380 }
4381 }
4382
4383 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4384 assert(UseAVX > 0, "requires some form of AVX");
4385 if (VM_Version::supports_evex()) {
4386 tuple_type = EVEX_FVM;
4387 }
4388 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector_len,
4389 (VM_Version::supports_avx512bw() == false));
4390 }
4391
4392 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4393 assert(UseAVX > 0, "requires some form of AVX");
4394 if (VM_Version::supports_evex()) {
4395 tuple_type = EVEX_FVM;
4396 }
4397 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector_len,
4398 (VM_Version::supports_avx512bw() == false));
4399 }
4400
4401 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4402 assert(UseAVX > 0, "requires some form of AVX");
4403 if (VM_Version::supports_evex()) {
4404 tuple_type = EVEX_FV;
4405 input_size_in_bits = EVEX_32bit;
4406 }
4407 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector_len);
4408 }
4409
4410 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4411 assert(UseAVX > 0, "requires some form of AVX");
4412 if (VM_Version::supports_evex()) {
4413 tuple_type = EVEX_FV;
4414 input_size_in_bits = EVEX_64bit;
4415 emit_vex_arith_q(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4416 } else {
4417 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4418 }
4419 }
4420
4421 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
4422 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4423 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66,
4424 (VM_Version::supports_avx512bw() == false));
4425 }
4426
4427 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
4428 assert(VM_Version::supports_sse4_1(), "");
4429 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66,
4430 false, VEX_OPCODE_0F_38);
4431 emit_int8(0x40);
4432 emit_int8((unsigned char)(0xC0 | encode));
4433 }
4434
4435 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4436 assert(UseAVX > 0, "requires some form of AVX");
4437 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector_len,
4438 (VM_Version::supports_avx512bw() == false));
4439 }
4440
4441 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4442 assert(UseAVX > 0, "requires some form of AVX");
4443 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66,
4444 vector_len, VEX_OPCODE_0F_38);
4445 emit_int8(0x40);
4446 emit_int8((unsigned char)(0xC0 | encode));
4447 }
4448
4449 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4450 assert(UseAVX > 2, "requires some form of AVX");
4451 int src_enc = src->encoding();
4452 int dst_enc = dst->encoding();
4453 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4454 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66,
4455 VEX_OPCODE_0F_38, true, vector_len, false, false);
4456 emit_int8(0x40);
4457 emit_int8((unsigned char)(0xC0 | encode));
4458 }
4459
4460 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4461 assert(UseAVX > 0, "requires some form of AVX");
4462 if (VM_Version::supports_evex()) {
4463 tuple_type = EVEX_FVM;
4464 }
4465 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector_len);
4466 }
4467
4468 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4469 assert(UseAVX > 0, "requires some form of AVX");
4470 if (VM_Version::supports_evex()) {
4471 tuple_type = EVEX_FV;
4472 input_size_in_bits = EVEX_32bit;
4473 }
4474 InstructionMark im(this);
4475 int dst_enc = dst->encoding();
4476 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4477 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66,
4478 VEX_OPCODE_0F_38, false, vector_len);
4479 emit_int8(0x40);
4480 emit_operand(dst, src);
4481 }
4482
4483 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4484 assert(UseAVX > 0, "requires some form of AVX");
4485 if (VM_Version::supports_evex()) {
4486 tuple_type = EVEX_FV;
4487 input_size_in_bits = EVEX_64bit;
4488 }
4489 InstructionMark im(this);
4490 int dst_enc = dst->encoding();
4491 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4492 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, true, vector_len);
4493 emit_int8(0x40);
4494 emit_operand(dst, src);
4495 }
4496
4497 // Shift packed integers left by specified number of bits.
4498 void Assembler::psllw(XMMRegister dst, int shift) {
4499 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4500 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
4501 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F,
4502 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
4503 emit_int8(0x71);
4504 emit_int8((unsigned char)(0xC0 | encode));
4505 emit_int8(shift & 0xFF);
4506 }
4507
4508 void Assembler::pslld(XMMRegister dst, int shift) {
4509 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4510 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
4511 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, false);
4512 emit_int8(0x72);
4513 emit_int8((unsigned char)(0xC0 | encode));
4514 emit_int8(shift & 0xFF);
4515 }
4516
4517 void Assembler::psllq(XMMRegister dst, int shift) {
4518 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4519 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
4520 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F, true);
4521 emit_int8(0x73);
4522 emit_int8((unsigned char)(0xC0 | encode));
4523 emit_int8(shift & 0xFF);
4524 }
4525
4526 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
4527 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4528 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66, false,
4529 (VM_Version::supports_avx512bw() == false));
4530 }
4531
4532 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
4533 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4534 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66);
4535 }
4536
4537 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
4538 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4539 if (VM_Version::supports_evex()) {
4540 emit_simd_arith_q(0xF3, dst, shift, VEX_SIMD_66);
4541 } else {
4542 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66);
4543 }
4544 }
4545
4546 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4547 assert(UseAVX > 0, "requires some form of AVX");
4548 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
4549 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector_len,
4550 (VM_Version::supports_avx512bw() == false));
4551 emit_int8(shift & 0xFF);
4552 }
4553
4554 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4555 assert(UseAVX > 0, "requires some form of AVX");
4556 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
4557 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector_len);
4558 emit_int8(shift & 0xFF);
4559 }
4560
4561 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4562 assert(UseAVX > 0, "requires some form of AVX");
4563 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
4564 if (VM_Version::supports_evex()) {
4565 emit_vex_arith_q(0x73, xmm6, dst, src, VEX_SIMD_66, vector_len);
4566 } else {
4567 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector_len);
4568 }
4569 emit_int8(shift & 0xFF);
4570 }
4571
4572 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4573 assert(UseAVX > 0, "requires some form of AVX");
4574 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector_len,
4575 (VM_Version::supports_avx512bw() == false));
4576 }
4577
4578 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4579 assert(UseAVX > 0, "requires some form of AVX");
4580 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector_len);
4581 }
4582
4583 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4584 assert(UseAVX > 0, "requires some form of AVX");
4585 if (VM_Version::supports_evex()) {
4586 emit_vex_arith_q(0xF3, dst, src, shift, VEX_SIMD_66, vector_len);
4587 } else {
4588 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector_len);
4589 }
4590 }
4591
4592 // Shift packed integers logically right by specified number of bits.
4593 void Assembler::psrlw(XMMRegister dst, int shift) {
4594 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4595 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
4596 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F,
4597 (VM_Version::supports_avx512bw() == false));
4598 emit_int8(0x71);
4599 emit_int8((unsigned char)(0xC0 | encode));
4600 emit_int8(shift & 0xFF);
4601 }
4602
4603 void Assembler::psrld(XMMRegister dst, int shift) {
4604 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4605 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
4606 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, false);
4607 emit_int8(0x72);
4608 emit_int8((unsigned char)(0xC0 | encode));
4609 emit_int8(shift & 0xFF);
4610 }
4611
4612 void Assembler::psrlq(XMMRegister dst, int shift) {
4613 // Do not confuse it with psrldq SSE2 instruction which
4614 // shifts 128 bit value in xmm register by number of bytes.
4615 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4616 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4617 int encode = 0;
4618 if (VM_Version::supports_evex() && VM_Version::supports_avx512bw()) {
4619 encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, true, VEX_OPCODE_0F, false);
4620 } else {
4621 encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F, true);
4622 }
4623 emit_int8(0x73);
4624 emit_int8((unsigned char)(0xC0 | encode));
4625 emit_int8(shift & 0xFF);
4626 }
4627
4628 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
4629 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4630 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66, false,
4631 (VM_Version::supports_avx512bw() == false));
4632 }
4633
4634 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
4635 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4636 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66);
4637 }
4638
4639 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
4640 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4641 if (VM_Version::supports_evex()) {
4642 emit_simd_arith_q(0xD3, dst, shift, VEX_SIMD_66);
4643 } else {
4644 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66);
4645 }
4646 }
4647
4648 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4649 assert(UseAVX > 0, "requires some form of AVX");
4650 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4651 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector_len,
4652 (VM_Version::supports_avx512bw() == false));
4653 emit_int8(shift & 0xFF);
4654 }
4655
4656 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4657 assert(UseAVX > 0, "requires some form of AVX");
4658 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4659 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector_len);
4660 emit_int8(shift & 0xFF);
4661 }
4662
4663 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4664 assert(UseAVX > 0, "requires some form of AVX");
4665 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4666 if (VM_Version::supports_evex()) {
4667 emit_vex_arith_q(0x73, xmm2, dst, src, VEX_SIMD_66, vector_len);
4668 } else {
4669 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector_len);
4670 }
4671 emit_int8(shift & 0xFF);
4672 }
4673
4674 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4675 assert(UseAVX > 0, "requires some form of AVX");
4676 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector_len,
4677 (VM_Version::supports_avx512bw() == false));
4678 }
4679
4680 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4681 assert(UseAVX > 0, "requires some form of AVX");
4682 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector_len);
4683 }
4684
4685 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4686 assert(UseAVX > 0, "requires some form of AVX");
4687 if (VM_Version::supports_evex()) {
4688 emit_vex_arith_q(0xD3, dst, src, shift, VEX_SIMD_66, vector_len);
4689 } else {
4690 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector_len);
4691 }
4692 }
4693
4694 // Shift packed integers arithmetically right by specified number of bits.
4695 void Assembler::psraw(XMMRegister dst, int shift) {
4696 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4697 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4698 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F,
4699 (VM_Version::supports_avx512bw() == false));
4700 emit_int8(0x71);
4701 emit_int8((unsigned char)(0xC0 | encode));
4702 emit_int8(shift & 0xFF);
4703 }
4704
4705 void Assembler::psrad(XMMRegister dst, int shift) {
4706 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4707 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
4708 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, false);
4709 emit_int8(0x72);
4710 emit_int8((unsigned char)(0xC0 | encode));
4711 emit_int8(shift & 0xFF);
4712 }
4713
4714 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
4715 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4716 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66,
4717 (VM_Version::supports_avx512bw() == false));
4718 }
4719
4720 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
4721 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4722 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66);
4723 }
4724
4725 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4726 assert(UseAVX > 0, "requires some form of AVX");
4727 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4728 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector_len,
4729 (VM_Version::supports_avx512bw() == false));
4730 emit_int8(shift & 0xFF);
4731 }
4732
4733 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4734 assert(UseAVX > 0, "requires some form of AVX");
4735 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4736 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector_len);
4737 emit_int8(shift & 0xFF);
4738 }
4739
4740 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4741 assert(UseAVX > 0, "requires some form of AVX");
4742 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector_len,
4743 (VM_Version::supports_avx512bw() == false));
4744 }
4745
4746 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4747 assert(UseAVX > 0, "requires some form of AVX");
4748 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector_len);
4749 }
4750
4751
4752 // AND packed integers
4753 void Assembler::pand(XMMRegister dst, XMMRegister src) {
4754 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4755 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66);
4756 }
4757
4758 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4759 assert(UseAVX > 0, "requires some form of AVX");
4760 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector_len);
4761 }
4762
4763 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4764 assert(UseAVX > 0, "requires some form of AVX");
4765 if (VM_Version::supports_evex()) {
4766 tuple_type = EVEX_FV;
4767 input_size_in_bits = EVEX_32bit;
4768 }
4769 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector_len);
4770 }
4771
4772 void Assembler::por(XMMRegister dst, XMMRegister src) {
4773 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4774 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66);
4775 }
4776
4777 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4778 assert(UseAVX > 0, "requires some form of AVX");
4779 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector_len);
4780 }
4781
4782 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4783 assert(UseAVX > 0, "requires some form of AVX");
4784 if (VM_Version::supports_evex()) {
4785 tuple_type = EVEX_FV;
4786 input_size_in_bits = EVEX_32bit;
4787 }
4788 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector_len);
4789 }
4790
4791 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
4792 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4793 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66);
4794 }
4795
4796 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4797 assert(UseAVX > 0, "requires some form of AVX");
4798 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector_len);
4799 }
4800
4801 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4802 assert(UseAVX > 0, "requires some form of AVX");
4803 if (VM_Version::supports_evex()) {
4804 tuple_type = EVEX_FV;
4805 input_size_in_bits = EVEX_32bit;
4806 }
4807 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector_len);
4808 }
4809
4810
4811 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4812 assert(VM_Version::supports_avx(), "");
4813 int vector_len = AVX_256bit;
4814 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4815 emit_int8(0x18);
4816 emit_int8((unsigned char)(0xC0 | encode));
4817 // 0x00 - insert into lower 128 bits
4818 // 0x01 - insert into upper 128 bits
4819 emit_int8(0x01);
4820 }
4821
4822 void Assembler::vinsertf64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4823 assert(VM_Version::supports_evex(), "");
4824 int vector_len = AVX_512bit;
4825 int src_enc = src->encoding();
4826 int dst_enc = dst->encoding();
4827 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4828 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66,
4829 VEX_OPCODE_0F_3A, true, vector_len, false, false);
4830 emit_int8(0x1A);
4831 emit_int8((unsigned char)(0xC0 | encode));
4832 // 0x00 - insert into lower 256 bits
4833 // 0x01 - insert into upper 256 bits
4834 emit_int8(0x01);
4835 }
4836
4837 void Assembler::vinsertf64x4h(XMMRegister dst, Address src) {
4838 assert(VM_Version::supports_avx(), "");
4839 if (VM_Version::supports_evex()) {
4840 tuple_type = EVEX_T4;
4841 input_size_in_bits = EVEX_64bit;
4842 }
4843 InstructionMark im(this);
4844 int vector_len = AVX_512bit;
4845 assert(dst != xnoreg, "sanity");
4846 int dst_enc = dst->encoding();
4847 // swap src<->dst for encoding
4848 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, true, vector_len);
4849 emit_int8(0x1A);
4850 emit_operand(dst, src);
4851 // 0x01 - insert into upper 128 bits
4852 emit_int8(0x01);
4853 }
4854
4855 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
4856 assert(VM_Version::supports_avx(), "");
4857 if (VM_Version::supports_evex()) {
4858 tuple_type = EVEX_T4;
4859 input_size_in_bits = EVEX_32bit;
4860 }
4861 InstructionMark im(this);
4862 int vector_len = AVX_256bit;
4863 assert(dst != xnoreg, "sanity");
4864 int dst_enc = dst->encoding();
4865 // swap src<->dst for encoding
4866 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4867 emit_int8(0x18);
4868 emit_operand(dst, src);
4869 // 0x01 - insert into upper 128 bits
4870 emit_int8(0x01);
4871 }
4872
4873 void Assembler::vextractf128h(XMMRegister dst, XMMRegister src) {
4874 assert(VM_Version::supports_avx(), "");
4875 int vector_len = AVX_256bit;
4876 int encode = vex_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4877 emit_int8(0x19);
4878 emit_int8((unsigned char)(0xC0 | encode));
4879 // 0x00 - insert into lower 128 bits
4880 // 0x01 - insert into upper 128 bits
4881 emit_int8(0x01);
4882 }
4883
4884 void Assembler::vextractf128h(Address dst, XMMRegister src) {
4885 assert(VM_Version::supports_avx(), "");
4886 if (VM_Version::supports_evex()) {
4887 tuple_type = EVEX_T4;
4888 input_size_in_bits = EVEX_32bit;
4889 }
4890 InstructionMark im(this);
4891 int vector_len = AVX_256bit;
4892 assert(src != xnoreg, "sanity");
4893 int src_enc = src->encoding();
4894 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4895 emit_int8(0x19);
4896 emit_operand(src, dst);
4897 // 0x01 - extract from upper 128 bits
4898 emit_int8(0x01);
4899 }
4900
4901 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4902 assert(VM_Version::supports_avx2(), "");
4903 int vector_len = AVX_256bit;
4904 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4905 emit_int8(0x38);
4906 emit_int8((unsigned char)(0xC0 | encode));
4907 // 0x00 - insert into lower 128 bits
4908 // 0x01 - insert into upper 128 bits
4909 emit_int8(0x01);
4910 }
4911
4912 void Assembler::vinserti64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4913 assert(VM_Version::supports_evex(), "");
4914 int vector_len = AVX_512bit;
4915 int src_enc = src->encoding();
4916 int dst_enc = dst->encoding();
4917 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4918 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4919 VM_Version::supports_avx512dq(), vector_len, false, false);
4920 emit_int8(0x38);
4921 emit_int8((unsigned char)(0xC0 | encode));
4922 // 0x00 - insert into lower 256 bits
4923 // 0x01 - insert into upper 256 bits
4924 emit_int8(0x01);
4925 }
4926
4927 void Assembler::vinserti128h(XMMRegister dst, Address src) {
4928 assert(VM_Version::supports_avx2(), "");
4929 if (VM_Version::supports_evex()) {
4930 tuple_type = EVEX_T4;
4931 input_size_in_bits = EVEX_32bit;
4932 }
4933 InstructionMark im(this);
4934 int vector_len = AVX_256bit;
4935 assert(dst != xnoreg, "sanity");
4936 int dst_enc = dst->encoding();
4937 // swap src<->dst for encoding
4938 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4939 emit_int8(0x38);
4940 emit_operand(dst, src);
4941 // 0x01 - insert into upper 128 bits
4942 emit_int8(0x01);
4943 }
4944
4945 void Assembler::vextracti128h(XMMRegister dst, XMMRegister src) {
4946 assert(VM_Version::supports_avx(), "");
4947 int vector_len = AVX_256bit;
4948 int encode = vex_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4949 emit_int8(0x39);
4950 emit_int8((unsigned char)(0xC0 | encode));
4951 // 0x00 - insert into lower 128 bits
4952 // 0x01 - insert into upper 128 bits
4953 emit_int8(0x01);
4954 }
4955
4956 void Assembler::vextracti128h(Address dst, XMMRegister src) {
4957 assert(VM_Version::supports_avx2(), "");
4958 if (VM_Version::supports_evex()) {
4959 tuple_type = EVEX_T4;
4960 input_size_in_bits = EVEX_32bit;
4961 }
4962 InstructionMark im(this);
4963 int vector_len = AVX_256bit;
4964 assert(src != xnoreg, "sanity");
4965 int src_enc = src->encoding();
4966 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4967 emit_int8(0x39);
4968 emit_operand(src, dst);
4969 // 0x01 - extract from upper 128 bits
4970 emit_int8(0x01);
4971 }
4972
4973 void Assembler::vextracti64x4h(XMMRegister dst, XMMRegister src) {
4974 assert(VM_Version::supports_evex(), "");
4975 int vector_len = AVX_512bit;
4976 int src_enc = src->encoding();
4977 int dst_enc = dst->encoding();
4978 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4979 true, vector_len, false, false);
4980 emit_int8(0x3B);
4981 emit_int8((unsigned char)(0xC0 | encode));
4982 // 0x01 - extract from upper 256 bits
4983 emit_int8(0x01);
4984 }
4985
4986 void Assembler::vextracti64x2h(XMMRegister dst, XMMRegister src, int value) {
4987 assert(VM_Version::supports_evex(), "");
4988 int vector_len = AVX_512bit;
4989 int src_enc = src->encoding();
4990 int dst_enc = dst->encoding();
4991 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4992 VM_Version::supports_avx512dq(), vector_len, false, false);
4993 emit_int8(0x39);
4994 emit_int8((unsigned char)(0xC0 | encode));
4995 // 0x01 - extract from bits 255:128
4996 // 0x02 - extract from bits 383:256
4997 // 0x03 - extract from bits 511:384
4998 emit_int8(value & 0x3);
4999 }
5000
5001 void Assembler::vextractf64x4h(XMMRegister dst, XMMRegister src) {
5002 assert(VM_Version::supports_evex(), "");
5003 int vector_len = AVX_512bit;
5004 int src_enc = src->encoding();
5005 int dst_enc = dst->encoding();
5006 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
5007 VM_Version::supports_avx512dq(), vector_len, false, false);
5008 emit_int8(0x1B);
5009 emit_int8((unsigned char)(0xC0 | encode));
5010 // 0x01 - extract from upper 256 bits
5011 emit_int8(0x01);
5012 }
5013
5014 void Assembler::vextractf64x4h(Address dst, XMMRegister src) {
5015 assert(VM_Version::supports_avx2(), "");
5016 tuple_type = EVEX_T4;
5017 input_size_in_bits = EVEX_64bit;
5018 InstructionMark im(this);
5019 int vector_len = AVX_512bit;
5020 assert(src != xnoreg, "sanity");
5021 int src_enc = src->encoding();
5022 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
5023 VM_Version::supports_avx512dq(), vector_len);
5024 emit_int8(0x1B);
5025 emit_operand(src, dst);
5026 // 0x01 - extract from upper 128 bits
5027 emit_int8(0x01);
5028 }
5029
5030 void Assembler::vextractf32x4h(XMMRegister dst, XMMRegister src, int value) {
5031 assert(VM_Version::supports_evex(), "");
5032 int vector_len = AVX_512bit;
5033 int src_enc = src->encoding();
5034 int dst_enc = dst->encoding();
5035 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66,
5036 VEX_OPCODE_0F_3A, false, vector_len, false, false);
5037 emit_int8(0x19);
5038 emit_int8((unsigned char)(0xC0 | encode));
5039 // 0x01 - extract from bits 255:128
5040 // 0x02 - extract from bits 383:256
5041 // 0x03 - extract from bits 511:384
5042 emit_int8(value & 0x3);
5043 }
5044
5045 void Assembler::vextractf64x2h(XMMRegister dst, XMMRegister src, int value) {
5046 assert(VM_Version::supports_evex(), "");
5047 int vector_len = AVX_512bit;
5048 int src_enc = src->encoding();
5049 int dst_enc = dst->encoding();
5050 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
5051 VM_Version::supports_avx512dq(), vector_len, false, false);
5052 emit_int8(0x19);
5053 emit_int8((unsigned char)(0xC0 | encode));
5054 // 0x01 - extract from bits 255:128
5055 // 0x02 - extract from bits 383:256
5056 // 0x03 - extract from bits 511:384
5057 emit_int8(value & 0x3);
5058 }
5059
5060 // duplicate 4-bytes integer data from src into 8 locations in dest
5061 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
5062 assert(VM_Version::supports_avx2(), "");
5063 int vector_len = AVX_256bit;
5064 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
5065 vector_len, VEX_OPCODE_0F_38, false);
5066 emit_int8(0x58);
5067 emit_int8((unsigned char)(0xC0 | encode));
5068 }
5069
5070 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
5071 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
5072 assert(VM_Version::supports_evex(), "");
5073 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
5074 vector_len, VEX_OPCODE_0F_38, false);
5075 emit_int8(0x78);
5076 emit_int8((unsigned char)(0xC0 | encode));
5077 }
5078
5079 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
5080 assert(VM_Version::supports_evex(), "");
5081 tuple_type = EVEX_T1S;
5082 input_size_in_bits = EVEX_8bit;
5083 InstructionMark im(this);
5084 assert(dst != xnoreg, "sanity");
5085 int dst_enc = dst->encoding();
5086 // swap src<->dst for encoding
5087 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector_len);
5088 emit_int8(0x78);
5089 emit_operand(dst, src);
5090 }
5091
5092 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
5093 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
5094 assert(VM_Version::supports_evex(), "");
5095 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
5096 vector_len, VEX_OPCODE_0F_38, false);
5097 emit_int8(0x79);
5098 emit_int8((unsigned char)(0xC0 | encode));
5099 }
5100
5101 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
5102 assert(VM_Version::supports_evex(), "");
5103 tuple_type = EVEX_T1S;
5104 input_size_in_bits = EVEX_16bit;
5105 InstructionMark im(this);
5106 assert(dst != xnoreg, "sanity");
5107 int dst_enc = dst->encoding();
5108 // swap src<->dst for encoding
5109 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector_len);
5110 emit_int8(0x79);
5111 emit_operand(dst, src);
5112 }
5113
5114 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5115 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
5116 assert(VM_Version::supports_evex(), "");
5117 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
5118 vector_len, VEX_OPCODE_0F_38, false);
5119 emit_int8(0x58);
5120 emit_int8((unsigned char)(0xC0 | encode));
5121 }
5122
5123 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
5124 assert(VM_Version::supports_evex(), "");
5125 tuple_type = EVEX_T1S;
5126 input_size_in_bits = EVEX_32bit;
5127 InstructionMark im(this);
5128 assert(dst != xnoreg, "sanity");
5129 int dst_enc = dst->encoding();
5130 // swap src<->dst for encoding
5131 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector_len);
5132 emit_int8(0x58);
5133 emit_operand(dst, src);
5134 }
5135
5136 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5137 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
5138 assert(VM_Version::supports_evex(), "");
5139 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5140 VEX_OPCODE_0F_38, true, vector_len, false, false);
5141 emit_int8(0x59);
5142 emit_int8((unsigned char)(0xC0 | encode));
5143 }
5144
5145 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
5146 assert(VM_Version::supports_evex(), "");
5147 tuple_type = EVEX_T1S;
5148 input_size_in_bits = EVEX_64bit;
5149 InstructionMark im(this);
5150 assert(dst != xnoreg, "sanity");
5151 int dst_enc = dst->encoding();
5152 // swap src<->dst for encoding
5153 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, true, vector_len);
5154 emit_int8(0x59);
5155 emit_operand(dst, src);
5156 }
5157
5158 // duplicate single precision fp from src into 4|8|16 locations in dest : requires AVX512VL
5159 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
5160 assert(VM_Version::supports_evex(), "");
5161 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5162 VEX_OPCODE_0F_38, false, vector_len, false, false);
5163 emit_int8(0x18);
5164 emit_int8((unsigned char)(0xC0 | encode));
5165 }
5166
5167 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
5168 assert(VM_Version::supports_evex(), "");
5169 tuple_type = EVEX_T1S;
5170 input_size_in_bits = EVEX_32bit;
5171 InstructionMark im(this);
5172 assert(dst != xnoreg, "sanity");
5173 int dst_enc = dst->encoding();
5174 // swap src<->dst for encoding
5175 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector_len);
5176 emit_int8(0x18);
5177 emit_operand(dst, src);
5178 }
5179
5180 // duplicate double precision fp from src into 2|4|8 locations in dest : requires AVX512VL
5181 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
5182 assert(VM_Version::supports_evex(), "");
5183 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5184 VEX_OPCODE_0F_38, true, vector_len, false, false);
5185 emit_int8(0x19);
5186 emit_int8((unsigned char)(0xC0 | encode));
5187 }
5188
5189 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
5190 assert(VM_Version::supports_evex(), "");
5191 tuple_type = EVEX_T1S;
5192 input_size_in_bits = EVEX_64bit;
5193 InstructionMark im(this);
5194 assert(dst != xnoreg, "sanity");
5195 int dst_enc = dst->encoding();
5196 // swap src<->dst for encoding
5197 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, true, vector_len);
5198 emit_int8(0x19);
5199 emit_operand(dst, src);
5200 }
5201
5202 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
5203 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
5204 assert(VM_Version::supports_evex(), "");
5205 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5206 VEX_OPCODE_0F_38, false, vector_len, false, false);
5207 emit_int8(0x7A);
5208 emit_int8((unsigned char)(0xC0 | encode));
5209 }
5210
5211 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
5212 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
5213 assert(VM_Version::supports_evex(), "");
5214 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5215 VEX_OPCODE_0F_38, false, vector_len, false, false);
5216 emit_int8(0x7B);
5217 emit_int8((unsigned char)(0xC0 | encode));
5218 }
5219
5220 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5221 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
5222 assert(VM_Version::supports_evex(), "");
5223 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5224 VEX_OPCODE_0F_38, false, vector_len, false, false);
5225 emit_int8(0x7C);
5226 emit_int8((unsigned char)(0xC0 | encode));
5227 }
5228
5229 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5230 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
5231 assert(VM_Version::supports_evex(), "");
5232 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5233 VEX_OPCODE_0F_38, true, vector_len, false, false);
5234 emit_int8(0x7C);
5235 emit_int8((unsigned char)(0xC0 | encode));
5236 }
5237
5238 // Carry-Less Multiplication Quadword
5239 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
5240 assert(VM_Version::supports_clmul(), "");
5241 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
5242 VEX_OPCODE_0F_3A, false, AVX_128bit, true);
5243 emit_int8(0x44);
5244 emit_int8((unsigned char)(0xC0 | encode));
5245 emit_int8((unsigned char)mask);
5246 }
5247
5248 // Carry-Less Multiplication Quadword
5249 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
5250 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
5251 int vector_len = AVX_128bit;
5252 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66,
5253 vector_len, VEX_OPCODE_0F_3A, true);
5254 emit_int8(0x44);
5255 emit_int8((unsigned char)(0xC0 | encode));
5256 emit_int8((unsigned char)mask);
5257 }
5258
5259 void Assembler::vzeroupper() {
5260 assert(VM_Version::supports_avx(), "");
5261 if (UseAVX < 3)
5262 {
5263 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
5264 emit_int8(0x77);
5265 }
5266 }
5267
5268
5269 #ifndef _LP64
5270 // 32bit only pieces of the assembler
5271
5272 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
5273 // NO PREFIX AS NEVER 64BIT
5274 InstructionMark im(this);
5275 emit_int8((unsigned char)0x81);
5276 emit_int8((unsigned char)(0xF8 | src1->encoding()));
5277 emit_data(imm32, rspec, 0);
5278 }
5279
5280 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
5281 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
5282 InstructionMark im(this);
5283 emit_int8((unsigned char)0x81);
5284 emit_operand(rdi, src1);
5285 emit_data(imm32, rspec, 0);
5286 }
5287
5288 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
5289 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
5290 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
5291 void Assembler::cmpxchg8(Address adr) {
5292 InstructionMark im(this);
5293 emit_int8(0x0F);
5294 emit_int8((unsigned char)0xC7);
5295 emit_operand(rcx, adr);
5296 }
5297
5298 void Assembler::decl(Register dst) {
5299 // Don't use it directly. Use MacroAssembler::decrementl() instead.
5300 emit_int8(0x48 | dst->encoding());
5301 }
5302
5303 #endif // _LP64
5304
5305 // 64bit typically doesn't use the x87 but needs to for the trig funcs
5306
5307 void Assembler::fabs() {
5308 emit_int8((unsigned char)0xD9);
5309 emit_int8((unsigned char)0xE1);
5310 }
5311
5312 void Assembler::fadd(int i) {
5313 emit_farith(0xD8, 0xC0, i);
5314 }
5315
5316 void Assembler::fadd_d(Address src) {
5317 InstructionMark im(this);
5318 emit_int8((unsigned char)0xDC);
5319 emit_operand32(rax, src);
5320 }
5321
5322 void Assembler::fadd_s(Address src) {
5323 InstructionMark im(this);
5324 emit_int8((unsigned char)0xD8);
5325 emit_operand32(rax, src);
5326 }
5327
5328 void Assembler::fadda(int i) {
5329 emit_farith(0xDC, 0xC0, i);
5330 }
5331
5332 void Assembler::faddp(int i) {
5333 emit_farith(0xDE, 0xC0, i);
5334 }
5335
5336 void Assembler::fchs() {
5337 emit_int8((unsigned char)0xD9);
5338 emit_int8((unsigned char)0xE0);
5339 }
5340
5341 void Assembler::fcom(int i) {
5342 emit_farith(0xD8, 0xD0, i);
5343 }
5344
5345 void Assembler::fcomp(int i) {
5346 emit_farith(0xD8, 0xD8, i);
5347 }
5348
5349 void Assembler::fcomp_d(Address src) {
5350 InstructionMark im(this);
5351 emit_int8((unsigned char)0xDC);
5352 emit_operand32(rbx, src);
5353 }
5354
5355 void Assembler::fcomp_s(Address src) {
5356 InstructionMark im(this);
5357 emit_int8((unsigned char)0xD8);
5358 emit_operand32(rbx, src);
5359 }
5360
5361 void Assembler::fcompp() {
5362 emit_int8((unsigned char)0xDE);
5363 emit_int8((unsigned char)0xD9);
5364 }
5365
5366 void Assembler::fcos() {
5367 emit_int8((unsigned char)0xD9);
5368 emit_int8((unsigned char)0xFF);
5369 }
5370
5371 void Assembler::fdecstp() {
5372 emit_int8((unsigned char)0xD9);
5373 emit_int8((unsigned char)0xF6);
5374 }
5375
5376 void Assembler::fdiv(int i) {
5377 emit_farith(0xD8, 0xF0, i);
5378 }
5379
5380 void Assembler::fdiv_d(Address src) {
5381 InstructionMark im(this);
5382 emit_int8((unsigned char)0xDC);
5383 emit_operand32(rsi, src);
5384 }
5385
5386 void Assembler::fdiv_s(Address src) {
5387 InstructionMark im(this);
5388 emit_int8((unsigned char)0xD8);
5389 emit_operand32(rsi, src);
5390 }
5391
5392 void Assembler::fdiva(int i) {
5393 emit_farith(0xDC, 0xF8, i);
5394 }
5395
5396 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
5397 // is erroneous for some of the floating-point instructions below.
5398
5399 void Assembler::fdivp(int i) {
5400 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
5401 }
5402
5403 void Assembler::fdivr(int i) {
5404 emit_farith(0xD8, 0xF8, i);
5405 }
5406
5407 void Assembler::fdivr_d(Address src) {
5408 InstructionMark im(this);
5409 emit_int8((unsigned char)0xDC);
5410 emit_operand32(rdi, src);
5411 }
5412
5413 void Assembler::fdivr_s(Address src) {
5414 InstructionMark im(this);
5415 emit_int8((unsigned char)0xD8);
5416 emit_operand32(rdi, src);
5417 }
5418
5419 void Assembler::fdivra(int i) {
5420 emit_farith(0xDC, 0xF0, i);
5421 }
5422
5423 void Assembler::fdivrp(int i) {
5424 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
5425 }
5426
5427 void Assembler::ffree(int i) {
5428 emit_farith(0xDD, 0xC0, i);
5429 }
5430
5431 void Assembler::fild_d(Address adr) {
5432 InstructionMark im(this);
5433 emit_int8((unsigned char)0xDF);
5434 emit_operand32(rbp, adr);
5435 }
5436
5437 void Assembler::fild_s(Address adr) {
5438 InstructionMark im(this);
5439 emit_int8((unsigned char)0xDB);
5440 emit_operand32(rax, adr);
5441 }
5442
5443 void Assembler::fincstp() {
5444 emit_int8((unsigned char)0xD9);
5445 emit_int8((unsigned char)0xF7);
5446 }
5447
5448 void Assembler::finit() {
5449 emit_int8((unsigned char)0x9B);
5450 emit_int8((unsigned char)0xDB);
5451 emit_int8((unsigned char)0xE3);
5452 }
5453
5454 void Assembler::fist_s(Address adr) {
5455 InstructionMark im(this);
5456 emit_int8((unsigned char)0xDB);
5457 emit_operand32(rdx, adr);
5458 }
5459
5460 void Assembler::fistp_d(Address adr) {
5461 InstructionMark im(this);
5462 emit_int8((unsigned char)0xDF);
5463 emit_operand32(rdi, adr);
5464 }
5465
5466 void Assembler::fistp_s(Address adr) {
5467 InstructionMark im(this);
5468 emit_int8((unsigned char)0xDB);
5469 emit_operand32(rbx, adr);
5470 }
5471
5472 void Assembler::fld1() {
5473 emit_int8((unsigned char)0xD9);
5474 emit_int8((unsigned char)0xE8);
5475 }
5476
5477 void Assembler::fld_d(Address adr) {
5478 InstructionMark im(this);
5479 emit_int8((unsigned char)0xDD);
5480 emit_operand32(rax, adr);
5481 }
5482
5483 void Assembler::fld_s(Address adr) {
5484 InstructionMark im(this);
5485 emit_int8((unsigned char)0xD9);
5486 emit_operand32(rax, adr);
5487 }
5488
5489
5490 void Assembler::fld_s(int index) {
5491 emit_farith(0xD9, 0xC0, index);
5492 }
5493
5494 void Assembler::fld_x(Address adr) {
5495 InstructionMark im(this);
5496 emit_int8((unsigned char)0xDB);
5497 emit_operand32(rbp, adr);
5498 }
5499
5500 void Assembler::fldcw(Address src) {
5501 InstructionMark im(this);
5502 emit_int8((unsigned char)0xD9);
5503 emit_operand32(rbp, src);
5504 }
5505
5506 void Assembler::fldenv(Address src) {
5507 InstructionMark im(this);
5508 emit_int8((unsigned char)0xD9);
5509 emit_operand32(rsp, src);
5510 }
5511
5512 void Assembler::fldlg2() {
5513 emit_int8((unsigned char)0xD9);
5514 emit_int8((unsigned char)0xEC);
5515 }
5516
5517 void Assembler::fldln2() {
5518 emit_int8((unsigned char)0xD9);
5519 emit_int8((unsigned char)0xED);
5520 }
5521
5522 void Assembler::fldz() {
5523 emit_int8((unsigned char)0xD9);
5524 emit_int8((unsigned char)0xEE);
5525 }
5526
5527 void Assembler::flog() {
5528 fldln2();
5529 fxch();
5530 fyl2x();
5531 }
5532
5533 void Assembler::flog10() {
5534 fldlg2();
5535 fxch();
5536 fyl2x();
5537 }
5538
5539 void Assembler::fmul(int i) {
5540 emit_farith(0xD8, 0xC8, i);
5541 }
5542
5543 void Assembler::fmul_d(Address src) {
5544 InstructionMark im(this);
5545 emit_int8((unsigned char)0xDC);
5546 emit_operand32(rcx, src);
5547 }
5548
5549 void Assembler::fmul_s(Address src) {
5550 InstructionMark im(this);
5551 emit_int8((unsigned char)0xD8);
5552 emit_operand32(rcx, src);
5553 }
5554
5555 void Assembler::fmula(int i) {
5556 emit_farith(0xDC, 0xC8, i);
5557 }
5558
5559 void Assembler::fmulp(int i) {
5560 emit_farith(0xDE, 0xC8, i);
5561 }
5562
5563 void Assembler::fnsave(Address dst) {
5564 InstructionMark im(this);
5565 emit_int8((unsigned char)0xDD);
5566 emit_operand32(rsi, dst);
5567 }
5568
5569 void Assembler::fnstcw(Address src) {
5570 InstructionMark im(this);
5571 emit_int8((unsigned char)0x9B);
5572 emit_int8((unsigned char)0xD9);
5573 emit_operand32(rdi, src);
5574 }
5575
5576 void Assembler::fnstsw_ax() {
5577 emit_int8((unsigned char)0xDF);
5578 emit_int8((unsigned char)0xE0);
5579 }
5580
5581 void Assembler::fprem() {
5582 emit_int8((unsigned char)0xD9);
5583 emit_int8((unsigned char)0xF8);
5584 }
5585
5586 void Assembler::fprem1() {
5587 emit_int8((unsigned char)0xD9);
5588 emit_int8((unsigned char)0xF5);
5589 }
5590
5591 void Assembler::frstor(Address src) {
5592 InstructionMark im(this);
5593 emit_int8((unsigned char)0xDD);
5594 emit_operand32(rsp, src);
5595 }
5596
5597 void Assembler::fsin() {
5598 emit_int8((unsigned char)0xD9);
5599 emit_int8((unsigned char)0xFE);
5600 }
5601
5602 void Assembler::fsqrt() {
5603 emit_int8((unsigned char)0xD9);
5604 emit_int8((unsigned char)0xFA);
5605 }
5606
5607 void Assembler::fst_d(Address adr) {
5608 InstructionMark im(this);
5609 emit_int8((unsigned char)0xDD);
5610 emit_operand32(rdx, adr);
5611 }
5612
5613 void Assembler::fst_s(Address adr) {
5614 InstructionMark im(this);
5615 emit_int8((unsigned char)0xD9);
5616 emit_operand32(rdx, adr);
5617 }
5618
5619 void Assembler::fstp_d(Address adr) {
5620 InstructionMark im(this);
5621 emit_int8((unsigned char)0xDD);
5622 emit_operand32(rbx, adr);
5623 }
5624
5625 void Assembler::fstp_d(int index) {
5626 emit_farith(0xDD, 0xD8, index);
5627 }
5628
5629 void Assembler::fstp_s(Address adr) {
5630 InstructionMark im(this);
5631 emit_int8((unsigned char)0xD9);
5632 emit_operand32(rbx, adr);
5633 }
5634
5635 void Assembler::fstp_x(Address adr) {
5636 InstructionMark im(this);
5637 emit_int8((unsigned char)0xDB);
5638 emit_operand32(rdi, adr);
5639 }
5640
5641 void Assembler::fsub(int i) {
5642 emit_farith(0xD8, 0xE0, i);
5643 }
5644
5645 void Assembler::fsub_d(Address src) {
5646 InstructionMark im(this);
5647 emit_int8((unsigned char)0xDC);
5648 emit_operand32(rsp, src);
5649 }
5650
5651 void Assembler::fsub_s(Address src) {
5652 InstructionMark im(this);
5653 emit_int8((unsigned char)0xD8);
5654 emit_operand32(rsp, src);
5655 }
5656
5657 void Assembler::fsuba(int i) {
5658 emit_farith(0xDC, 0xE8, i);
5659 }
5660
5661 void Assembler::fsubp(int i) {
5662 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
5663 }
5664
5665 void Assembler::fsubr(int i) {
5666 emit_farith(0xD8, 0xE8, i);
5667 }
5668
5669 void Assembler::fsubr_d(Address src) {
5670 InstructionMark im(this);
5671 emit_int8((unsigned char)0xDC);
5672 emit_operand32(rbp, src);
5673 }
5674
5675 void Assembler::fsubr_s(Address src) {
5676 InstructionMark im(this);
5677 emit_int8((unsigned char)0xD8);
5678 emit_operand32(rbp, src);
5679 }
5680
5681 void Assembler::fsubra(int i) {
5682 emit_farith(0xDC, 0xE0, i);
5683 }
5684
5685 void Assembler::fsubrp(int i) {
5686 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
5687 }
5688
5689 void Assembler::ftan() {
5690 emit_int8((unsigned char)0xD9);
5691 emit_int8((unsigned char)0xF2);
5692 emit_int8((unsigned char)0xDD);
5693 emit_int8((unsigned char)0xD8);
5694 }
5695
5696 void Assembler::ftst() {
5697 emit_int8((unsigned char)0xD9);
5698 emit_int8((unsigned char)0xE4);
5699 }
5700
5701 void Assembler::fucomi(int i) {
5702 // make sure the instruction is supported (introduced for P6, together with cmov)
5703 guarantee(VM_Version::supports_cmov(), "illegal instruction");
5704 emit_farith(0xDB, 0xE8, i);
5705 }
5706
5707 void Assembler::fucomip(int i) {
5708 // make sure the instruction is supported (introduced for P6, together with cmov)
5709 guarantee(VM_Version::supports_cmov(), "illegal instruction");
5710 emit_farith(0xDF, 0xE8, i);
5711 }
5712
5713 void Assembler::fwait() {
5714 emit_int8((unsigned char)0x9B);
5715 }
5716
5717 void Assembler::fxch(int i) {
5718 emit_farith(0xD9, 0xC8, i);
5719 }
5720
5721 void Assembler::fyl2x() {
5722 emit_int8((unsigned char)0xD9);
5723 emit_int8((unsigned char)0xF1);
5724 }
5725
5726 void Assembler::frndint() {
5727 emit_int8((unsigned char)0xD9);
5728 emit_int8((unsigned char)0xFC);
5729 }
5730
5731 void Assembler::f2xm1() {
5732 emit_int8((unsigned char)0xD9);
5733 emit_int8((unsigned char)0xF0);
5734 }
5735
5736 void Assembler::fldl2e() {
5737 emit_int8((unsigned char)0xD9);
5738 emit_int8((unsigned char)0xEA);
5739 }
5740
5741 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
5742 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
5743 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
5744 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
5745
5746 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
5747 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
5748 if (pre > 0) {
5749 emit_int8(simd_pre[pre]);
5750 }
5751 if (rex_w) {
5752 prefixq(adr, xreg);
5753 } else {
5754 prefix(adr, xreg);
5755 }
5756 if (opc > 0) {
5757 emit_int8(0x0F);
5758 int opc2 = simd_opc[opc];
5759 if (opc2 > 0) {
5760 emit_int8(opc2);
5761 }
5762 }
5763 }
5764
5765 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
5766 if (pre > 0) {
5767 emit_int8(simd_pre[pre]);
5768 }
5769 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) :
5770 prefix_and_encode(dst_enc, src_enc);
5771 if (opc > 0) {
5772 emit_int8(0x0F);
5773 int opc2 = simd_opc[opc];
5774 if (opc2 > 0) {
5775 emit_int8(opc2);
5776 }
5777 }
5778 return encode;
5779 }
5780
5781
5782 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, int vector_len) {
5783 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
5784 prefix(VEX_3bytes);
5785
5786 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
5787 byte1 = (~byte1) & 0xE0;
5788 byte1 |= opc;
5789 emit_int8(byte1);
5790
5791 int byte2 = ((~nds_enc) & 0xf) << 3;
5792 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
5793 emit_int8(byte2);
5794 } else {
5795 prefix(VEX_2bytes);
5796
5797 int byte1 = vex_r ? VEX_R : 0;
5798 byte1 = (~byte1) & 0x80;
5799 byte1 |= ((~nds_enc) & 0xf) << 3;
5800 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
5801 emit_int8(byte1);
5802 }
5803 }
5804
5805 // This is a 4 byte encoding
5806 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, bool evex_r, bool evex_v,
5807 int nds_enc, VexSimdPrefix pre, VexOpcode opc,
5808 bool is_extended_context, bool is_merge_context,
5809 int vector_len, bool no_mask_reg ){
5810 // EVEX 0x62 prefix
5811 prefix(EVEX_4bytes);
5812 evex_encoding = (vex_w ? VEX_W : 0) | (evex_r ? EVEX_Rb : 0);
5813
5814 // P0: byte 2, initialized to RXBR`00mm
5815 // instead of not'd
5816 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
5817 byte2 = (~byte2) & 0xF0;
5818 // confine opc opcode extensions in mm bits to lower two bits
5819 // of form {0F, 0F_38, 0F_3A}
5820 byte2 |= opc;
5821 emit_int8(byte2);
5822
5823 // P1: byte 3 as Wvvvv1pp
5824 int byte3 = ((~nds_enc) & 0xf) << 3;
5825 // p[10] is always 1
5826 byte3 |= EVEX_F;
5827 byte3 |= (vex_w & 1) << 7;
5828 // confine pre opcode extensions in pp bits to lower two bits
5829 // of form {66, F3, F2}
5830 byte3 |= pre;
5831 emit_int8(byte3);
5832
5833 // P2: byte 4 as zL'Lbv'aaa
5834 int byte4 = (no_mask_reg) ? 0 : 1; // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
5835 // EVEX.v` for extending EVEX.vvvv or VIDX
5836 byte4 |= (evex_v ? 0: EVEX_V);
5837 // third EXEC.b for broadcast actions
5838 byte4 |= (is_extended_context ? EVEX_Rb : 0);
5839 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
5840 byte4 |= ((vector_len) & 0x3) << 5;
5841 // last is EVEX.z for zero/merge actions
5842 byte4 |= (is_merge_context ? EVEX_Z : 0);
5843 emit_int8(byte4);
5844 }
5845
5846 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre,
5847 VexOpcode opc, bool vex_w, int vector_len, bool legacy_mode, bool no_mask_reg) {
5848 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
5849 bool vex_b = adr.base_needs_rex();
5850 bool vex_x = adr.index_needs_rex();
5851 avx_vector_len = vector_len;
5852
5853 // if vector length is turned off, revert to AVX for vectors smaller than AVX_512bit
5854 if (VM_Version::supports_avx512vl() == false) {
5855 switch (vector_len) {
5856 case AVX_128bit:
5857 case AVX_256bit:
5858 legacy_mode = true;
5859 break;
5860 }
5861 }
5862
5863 if ((UseAVX > 2) && (legacy_mode == false))
5864 {
5865 bool evex_r = (xreg_enc >= 16);
5866 bool evex_v = (nds_enc >= 16);
5867 is_evex_instruction = true;
5868 evex_prefix(vex_r, vex_b, vex_x, vex_w, evex_r, evex_v, nds_enc, pre, opc, false, false, vector_len, no_mask_reg);
5869 } else {
5870 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector_len);
5871 }
5872 }
5873
5874 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,
5875 bool vex_w, int vector_len, bool legacy_mode, bool no_mask_reg ) {
5876 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
5877 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
5878 bool vex_x = false;
5879 avx_vector_len = vector_len;
5880
5881 // if vector length is turned off, revert to AVX for vectors smaller than AVX_512bit
5882 if (VM_Version::supports_avx512vl() == false) {
5883 switch (vector_len) {
5884 case AVX_128bit:
5885 case AVX_256bit:
5886 legacy_mode = true;
5887 break;
5888 }
5889 }
5890
5891 if ((UseAVX > 2) && (legacy_mode == false))
5892 {
5893 bool evex_r = (dst_enc >= 16);
5894 bool evex_v = (nds_enc >= 16);
5895 // can use vex_x as bank extender on rm encoding
5896 vex_x = (src_enc >= 16);
5897 evex_prefix(vex_r, vex_b, vex_x, vex_w, evex_r, evex_v, nds_enc, pre, opc, false, false, vector_len, no_mask_reg);
5898 } else {
5899 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector_len);
5900 }
5901
5902 // return modrm byte components for operands
5903 return (((dst_enc & 7) << 3) | (src_enc & 7));
5904 }
5905
5906
5907 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
5908 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len, bool legacy_mode) {
5909 if (UseAVX > 0) {
5910 int xreg_enc = xreg->encoding();
5911 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5912 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector_len, legacy_mode, no_mask_reg);
5913 } else {
5914 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
5915 rex_prefix(adr, xreg, pre, opc, rex_w);
5916 }
5917 }
5918
5919 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
5920 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len, bool legacy_mode) {
5921 int dst_enc = dst->encoding();
5922 int src_enc = src->encoding();
5923 if (UseAVX > 0) {
5924 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5925 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, legacy_mode, no_mask_reg);
5926 } else {
5927 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
5928 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w);
5929 }
5930 }
5931
5932 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, KRegister src, VexSimdPrefix pre,
5933 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len) {
5934 int dst_enc = dst->encoding();
5935 int src_enc = src->encoding();
5936 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5937 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, true, no_mask_reg);
5938 }
5939
5940 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, Register src, VexSimdPrefix pre,
5941 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len) {
5942 int dst_enc = dst->encoding();
5943 int src_enc = src->encoding();
5944 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5945 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, true, no_mask_reg);
5946 }
5947
5948 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
5949 InstructionMark im(this);
5950 simd_prefix(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, false, AVX_128bit, legacy_mode);
5951 emit_int8(opcode);
5952 emit_operand(dst, src);
5953 }
5954
5955 void Assembler::emit_simd_arith_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg) {
5956 InstructionMark im(this);
5957 simd_prefix_q(dst, dst, src, pre, no_mask_reg);
5958 emit_int8(opcode);
5959 emit_operand(dst, src);
5960 }
5961
5962 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
5963 int encode = simd_prefix_and_encode(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, false, AVX_128bit, legacy_mode);
5964 emit_int8(opcode);
5965 emit_int8((unsigned char)(0xC0 | encode));
5966 }
5967
5968 void Assembler::emit_simd_arith_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg) {
5969 int encode = simd_prefix_and_encode(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, true, AVX_128bit);
5970 emit_int8(opcode);
5971 emit_int8((unsigned char)(0xC0 | encode));
5972 }
5973
5974 // Versions with no second source register (non-destructive source).
5975 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool opNoRegMask) {
5976 InstructionMark im(this);
5977 simd_prefix(dst, xnoreg, src, pre, opNoRegMask);
5978 emit_int8(opcode);
5979 emit_operand(dst, src);
5980 }
5981
5982 void Assembler::emit_simd_arith_nonds_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool opNoRegMask) {
5983 InstructionMark im(this);
5984 simd_prefix_q(dst, xnoreg, src, pre, opNoRegMask);
5985 emit_int8(opcode);
5986 emit_operand(dst, src);
5987 }
5988
5989 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
5990 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre, no_mask_reg, VEX_OPCODE_0F, legacy_mode, AVX_128bit);
5991 emit_int8(opcode);
5992 emit_int8((unsigned char)(0xC0 | encode));
5993 }
5994
5995 void Assembler::emit_simd_arith_nonds_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg) {
5996 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre, no_mask_reg, VEX_OPCODE_0F, true, AVX_128bit);
5997 emit_int8(opcode);
5998 emit_int8((unsigned char)(0xC0 | encode));
5999 }
6000
6001 // 3-operands AVX instructions
6002 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, Address src,
6003 VexSimdPrefix pre, int vector_len, bool no_mask_reg, bool legacy_mode) {
6004 InstructionMark im(this);
6005 vex_prefix(dst, nds, src, pre, vector_len, no_mask_reg, legacy_mode);
6006 emit_int8(opcode);
6007 emit_operand(dst, src);
6008 }
6009
6010 void Assembler::emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds,
6011 Address src, VexSimdPrefix pre, int vector_len, bool no_mask_reg) {
6012 InstructionMark im(this);
6013 vex_prefix_q(dst, nds, src, pre, vector_len, no_mask_reg);
6014 emit_int8(opcode);
6015 emit_operand(dst, src);
6016 }
6017
6018 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
6019 VexSimdPrefix pre, int vector_len, bool no_mask_reg, bool legacy_mode) {
6020 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector_len, VEX_OPCODE_0F, false, no_mask_reg);
6021 emit_int8(opcode);
6022 emit_int8((unsigned char)(0xC0 | encode));
6023 }
6024
6025 void Assembler::emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
6026 VexSimdPrefix pre, int vector_len, bool no_mask_reg) {
6027 int src_enc = src->encoding();
6028 int dst_enc = dst->encoding();
6029 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6030 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, VEX_OPCODE_0F, true, vector_len, false, no_mask_reg);
6031 emit_int8(opcode);
6032 emit_int8((unsigned char)(0xC0 | encode));
6033 }
6034
6035 #ifndef _LP64
6036
6037 void Assembler::incl(Register dst) {
6038 // Don't use it directly. Use MacroAssembler::incrementl() instead.
6039 emit_int8(0x40 | dst->encoding());
6040 }
6041
6042 void Assembler::lea(Register dst, Address src) {
6043 leal(dst, src);
6044 }
6045
6046 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
6047 InstructionMark im(this);
6048 emit_int8((unsigned char)0xC7);
6049 emit_operand(rax, dst);
6050 emit_data((int)imm32, rspec, 0);
6051 }
6052
6053 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
6054 InstructionMark im(this);
6055 int encode = prefix_and_encode(dst->encoding());
6056 emit_int8((unsigned char)(0xB8 | encode));
6057 emit_data((int)imm32, rspec, 0);
6058 }
6059
6060 void Assembler::popa() { // 32bit
6061 emit_int8(0x61);
6062 }
6063
6064 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
6065 InstructionMark im(this);
6066 emit_int8(0x68);
6067 emit_data(imm32, rspec, 0);
6068 }
6069
6070 void Assembler::pusha() { // 32bit
6071 emit_int8(0x60);
6072 }
6073
6074 void Assembler::set_byte_if_not_zero(Register dst) {
6075 emit_int8(0x0F);
6076 emit_int8((unsigned char)0x95);
6077 emit_int8((unsigned char)(0xE0 | dst->encoding()));
6078 }
6079
6080 void Assembler::shldl(Register dst, Register src) {
6081 emit_int8(0x0F);
6082 emit_int8((unsigned char)0xA5);
6083 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6084 }
6085
6086 // 0F A4 / r ib
6087 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
6088 emit_int8(0x0F);
6089 emit_int8((unsigned char)0xA4);
6090 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6091 emit_int8(imm8);
6092 }
6093
6094 void Assembler::shrdl(Register dst, Register src) {
6095 emit_int8(0x0F);
6096 emit_int8((unsigned char)0xAD);
6097 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6098 }
6099
6100 #else // LP64
6101
6102 void Assembler::set_byte_if_not_zero(Register dst) {
6103 int enc = prefix_and_encode(dst->encoding(), true);
6104 emit_int8(0x0F);
6105 emit_int8((unsigned char)0x95);
6106 emit_int8((unsigned char)(0xE0 | enc));
6107 }
6108
6109 // 64bit only pieces of the assembler
6110 // This should only be used by 64bit instructions that can use rip-relative
6111 // it cannot be used by instructions that want an immediate value.
6112
6113 bool Assembler::reachable(AddressLiteral adr) {
6114 int64_t disp;
6115 // None will force a 64bit literal to the code stream. Likely a placeholder
6116 // for something that will be patched later and we need to certain it will
6117 // always be reachable.
6118 if (adr.reloc() == relocInfo::none) {
6119 return false;
6120 }
6121 if (adr.reloc() == relocInfo::internal_word_type) {
6122 // This should be rip relative and easily reachable.
6123 return true;
6124 }
6125 if (adr.reloc() == relocInfo::virtual_call_type ||
6126 adr.reloc() == relocInfo::opt_virtual_call_type ||
6127 adr.reloc() == relocInfo::static_call_type ||
6128 adr.reloc() == relocInfo::static_stub_type ) {
6129 // This should be rip relative within the code cache and easily
6130 // reachable until we get huge code caches. (At which point
6131 // ic code is going to have issues).
6132 return true;
6133 }
6134 if (adr.reloc() != relocInfo::external_word_type &&
6135 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
6136 adr.reloc() != relocInfo::poll_type && // relocs to identify them
6137 adr.reloc() != relocInfo::runtime_call_type ) {
6138 return false;
6139 }
6140
6141 // Stress the correction code
6142 if (ForceUnreachable) {
6143 // Must be runtimecall reloc, see if it is in the codecache
6144 // Flipping stuff in the codecache to be unreachable causes issues
6145 // with things like inline caches where the additional instructions
6146 // are not handled.
6147 if (CodeCache::find_blob(adr._target) == NULL) {
6148 return false;
6149 }
6150 }
6151 // For external_word_type/runtime_call_type if it is reachable from where we
6152 // are now (possibly a temp buffer) and where we might end up
6153 // anywhere in the codeCache then we are always reachable.
6154 // This would have to change if we ever save/restore shared code
6155 // to be more pessimistic.
6156 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
6157 if (!is_simm32(disp)) return false;
6158 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
6159 if (!is_simm32(disp)) return false;
6160
6161 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
6162
6163 // Because rip relative is a disp + address_of_next_instruction and we
6164 // don't know the value of address_of_next_instruction we apply a fudge factor
6165 // to make sure we will be ok no matter the size of the instruction we get placed into.
6166 // We don't have to fudge the checks above here because they are already worst case.
6167
6168 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
6169 // + 4 because better safe than sorry.
6170 const int fudge = 12 + 4;
6171 if (disp < 0) {
6172 disp -= fudge;
6173 } else {
6174 disp += fudge;
6175 }
6176 return is_simm32(disp);
6177 }
6178
6179 // Check if the polling page is not reachable from the code cache using rip-relative
6180 // addressing.
6181 bool Assembler::is_polling_page_far() {
6182 intptr_t addr = (intptr_t)os::get_polling_page();
6183 return ForceUnreachable ||
6184 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
6185 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
6186 }
6187
6188 void Assembler::emit_data64(jlong data,
6189 relocInfo::relocType rtype,
6190 int format) {
6191 if (rtype == relocInfo::none) {
6192 emit_int64(data);
6193 } else {
6194 emit_data64(data, Relocation::spec_simple(rtype), format);
6195 }
6196 }
6197
6198 void Assembler::emit_data64(jlong data,
6199 RelocationHolder const& rspec,
6200 int format) {
6201 assert(imm_operand == 0, "default format must be immediate in this file");
6202 assert(imm_operand == format, "must be immediate");
6203 assert(inst_mark() != NULL, "must be inside InstructionMark");
6204 // Do not use AbstractAssembler::relocate, which is not intended for
6205 // embedded words. Instead, relocate to the enclosing instruction.
6206 code_section()->relocate(inst_mark(), rspec, format);
6207 #ifdef ASSERT
6208 check_relocation(rspec, format);
6209 #endif
6210 emit_int64(data);
6211 }
6212
6213 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
6214 if (reg_enc >= 8) {
6215 prefix(REX_B);
6216 reg_enc -= 8;
6217 } else if (byteinst && reg_enc >= 4) {
6218 prefix(REX);
6219 }
6220 return reg_enc;
6221 }
6222
6223 int Assembler::prefixq_and_encode(int reg_enc) {
6224 if (reg_enc < 8) {
6225 prefix(REX_W);
6226 } else {
6227 prefix(REX_WB);
6228 reg_enc -= 8;
6229 }
6230 return reg_enc;
6231 }
6232
6233 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
6234 if (dst_enc < 8) {
6235 if (src_enc >= 8) {
6236 prefix(REX_B);
6237 src_enc -= 8;
6238 } else if (byteinst && src_enc >= 4) {
6239 prefix(REX);
6240 }
6241 } else {
6242 if (src_enc < 8) {
6243 prefix(REX_R);
6244 } else {
6245 prefix(REX_RB);
6246 src_enc -= 8;
6247 }
6248 dst_enc -= 8;
6249 }
6250 return dst_enc << 3 | src_enc;
6251 }
6252
6253 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
6254 if (dst_enc < 8) {
6255 if (src_enc < 8) {
6256 prefix(REX_W);
6257 } else {
6258 prefix(REX_WB);
6259 src_enc -= 8;
6260 }
6261 } else {
6262 if (src_enc < 8) {
6263 prefix(REX_WR);
6264 } else {
6265 prefix(REX_WRB);
6266 src_enc -= 8;
6267 }
6268 dst_enc -= 8;
6269 }
6270 return dst_enc << 3 | src_enc;
6271 }
6272
6273 void Assembler::prefix(Register reg) {
6274 if (reg->encoding() >= 8) {
6275 prefix(REX_B);
6276 }
6277 }
6278
6279 void Assembler::prefix(Register dst, Register src, Prefix p) {
6280 if (src->encoding() >= 8) {
6281 p = (Prefix)(p | REX_B);
6282 }
6283 if (dst->encoding() >= 8) {
6284 p = (Prefix)( p | REX_R);
6285 }
6286 if (p != Prefix_EMPTY) {
6287 // do not generate an empty prefix
6288 prefix(p);
6289 }
6290 }
6291
6292 void Assembler::prefix(Register dst, Address adr, Prefix p) {
6293 if (adr.base_needs_rex()) {
6294 if (adr.index_needs_rex()) {
6295 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
6296 } else {
6297 prefix(REX_B);
6298 }
6299 } else {
6300 if (adr.index_needs_rex()) {
6301 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
6302 }
6303 }
6304 if (dst->encoding() >= 8) {
6305 p = (Prefix)(p | REX_R);
6306 }
6307 if (p != Prefix_EMPTY) {
6308 // do not generate an empty prefix
6309 prefix(p);
6310 }
6311 }
6312
6313 void Assembler::prefix(Address adr) {
6314 if (adr.base_needs_rex()) {
6315 if (adr.index_needs_rex()) {
6316 prefix(REX_XB);
6317 } else {
6318 prefix(REX_B);
6319 }
6320 } else {
6321 if (adr.index_needs_rex()) {
6322 prefix(REX_X);
6323 }
6324 }
6325 }
6326
6327 void Assembler::prefixq(Address adr) {
6328 if (adr.base_needs_rex()) {
6329 if (adr.index_needs_rex()) {
6330 prefix(REX_WXB);
6331 } else {
6332 prefix(REX_WB);
6333 }
6334 } else {
6335 if (adr.index_needs_rex()) {
6336 prefix(REX_WX);
6337 } else {
6338 prefix(REX_W);
6339 }
6340 }
6341 }
6342
6343
6344 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
6345 if (reg->encoding() < 8) {
6346 if (adr.base_needs_rex()) {
6347 if (adr.index_needs_rex()) {
6348 prefix(REX_XB);
6349 } else {
6350 prefix(REX_B);
6351 }
6352 } else {
6353 if (adr.index_needs_rex()) {
6354 prefix(REX_X);
6355 } else if (byteinst && reg->encoding() >= 4 ) {
6356 prefix(REX);
6357 }
6358 }
6359 } else {
6360 if (adr.base_needs_rex()) {
6361 if (adr.index_needs_rex()) {
6362 prefix(REX_RXB);
6363 } else {
6364 prefix(REX_RB);
6365 }
6366 } else {
6367 if (adr.index_needs_rex()) {
6368 prefix(REX_RX);
6369 } else {
6370 prefix(REX_R);
6371 }
6372 }
6373 }
6374 }
6375
6376 void Assembler::prefixq(Address adr, Register src) {
6377 if (src->encoding() < 8) {
6378 if (adr.base_needs_rex()) {
6379 if (adr.index_needs_rex()) {
6380 prefix(REX_WXB);
6381 } else {
6382 prefix(REX_WB);
6383 }
6384 } else {
6385 if (adr.index_needs_rex()) {
6386 prefix(REX_WX);
6387 } else {
6388 prefix(REX_W);
6389 }
6390 }
6391 } else {
6392 if (adr.base_needs_rex()) {
6393 if (adr.index_needs_rex()) {
6394 prefix(REX_WRXB);
6395 } else {
6396 prefix(REX_WRB);
6397 }
6398 } else {
6399 if (adr.index_needs_rex()) {
6400 prefix(REX_WRX);
6401 } else {
6402 prefix(REX_WR);
6403 }
6404 }
6405 }
6406 }
6407
6408 void Assembler::prefix(Address adr, XMMRegister reg) {
6409 if (reg->encoding() < 8) {
6410 if (adr.base_needs_rex()) {
6411 if (adr.index_needs_rex()) {
6412 prefix(REX_XB);
6413 } else {
6414 prefix(REX_B);
6415 }
6416 } else {
6417 if (adr.index_needs_rex()) {
6418 prefix(REX_X);
6419 }
6420 }
6421 } else {
6422 if (adr.base_needs_rex()) {
6423 if (adr.index_needs_rex()) {
6424 prefix(REX_RXB);
6425 } else {
6426 prefix(REX_RB);
6427 }
6428 } else {
6429 if (adr.index_needs_rex()) {
6430 prefix(REX_RX);
6431 } else {
6432 prefix(REX_R);
6433 }
6434 }
6435 }
6436 }
6437
6438 void Assembler::prefixq(Address adr, XMMRegister src) {
6439 if (src->encoding() < 8) {
6440 if (adr.base_needs_rex()) {
6441 if (adr.index_needs_rex()) {
6442 prefix(REX_WXB);
6443 } else {
6444 prefix(REX_WB);
6445 }
6446 } else {
6447 if (adr.index_needs_rex()) {
6448 prefix(REX_WX);
6449 } else {
6450 prefix(REX_W);
6451 }
6452 }
6453 } else {
6454 if (adr.base_needs_rex()) {
6455 if (adr.index_needs_rex()) {
6456 prefix(REX_WRXB);
6457 } else {
6458 prefix(REX_WRB);
6459 }
6460 } else {
6461 if (adr.index_needs_rex()) {
6462 prefix(REX_WRX);
6463 } else {
6464 prefix(REX_WR);
6465 }
6466 }
6467 }
6468 }
6469
6470 void Assembler::adcq(Register dst, int32_t imm32) {
6471 (void) prefixq_and_encode(dst->encoding());
6472 emit_arith(0x81, 0xD0, dst, imm32);
6473 }
6474
6475 void Assembler::adcq(Register dst, Address src) {
6476 InstructionMark im(this);
6477 prefixq(src, dst);
6478 emit_int8(0x13);
6479 emit_operand(dst, src);
6480 }
6481
6482 void Assembler::adcq(Register dst, Register src) {
6483 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6484 emit_arith(0x13, 0xC0, dst, src);
6485 }
6486
6487 void Assembler::addq(Address dst, int32_t imm32) {
6488 InstructionMark im(this);
6489 prefixq(dst);
6490 emit_arith_operand(0x81, rax, dst,imm32);
6491 }
6492
6493 void Assembler::addq(Address dst, Register src) {
6494 InstructionMark im(this);
6495 prefixq(dst, src);
6496 emit_int8(0x01);
6497 emit_operand(src, dst);
6498 }
6499
6500 void Assembler::addq(Register dst, int32_t imm32) {
6501 (void) prefixq_and_encode(dst->encoding());
6502 emit_arith(0x81, 0xC0, dst, imm32);
6503 }
6504
6505 void Assembler::addq(Register dst, Address src) {
6506 InstructionMark im(this);
6507 prefixq(src, dst);
6508 emit_int8(0x03);
6509 emit_operand(dst, src);
6510 }
6511
6512 void Assembler::addq(Register dst, Register src) {
6513 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6514 emit_arith(0x03, 0xC0, dst, src);
6515 }
6516
6517 void Assembler::adcxq(Register dst, Register src) {
6518 //assert(VM_Version::supports_adx(), "adx instructions not supported");
6519 emit_int8((unsigned char)0x66);
6520 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6521 emit_int8(0x0F);
6522 emit_int8(0x38);
6523 emit_int8((unsigned char)0xF6);
6524 emit_int8((unsigned char)(0xC0 | encode));
6525 }
6526
6527 void Assembler::adoxq(Register dst, Register src) {
6528 //assert(VM_Version::supports_adx(), "adx instructions not supported");
6529 emit_int8((unsigned char)0xF3);
6530 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6531 emit_int8(0x0F);
6532 emit_int8(0x38);
6533 emit_int8((unsigned char)0xF6);
6534 emit_int8((unsigned char)(0xC0 | encode));
6535 }
6536
6537 void Assembler::andq(Address dst, int32_t imm32) {
6538 InstructionMark im(this);
6539 prefixq(dst);
6540 emit_int8((unsigned char)0x81);
6541 emit_operand(rsp, dst, 4);
6542 emit_int32(imm32);
6543 }
6544
6545 void Assembler::andq(Register dst, int32_t imm32) {
6546 (void) prefixq_and_encode(dst->encoding());
6547 emit_arith(0x81, 0xE0, dst, imm32);
6548 }
6549
6550 void Assembler::andq(Register dst, Address src) {
6551 InstructionMark im(this);
6552 prefixq(src, dst);
6553 emit_int8(0x23);
6554 emit_operand(dst, src);
6555 }
6556
6557 void Assembler::andq(Register dst, Register src) {
6558 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6559 emit_arith(0x23, 0xC0, dst, src);
6560 }
6561
6562 void Assembler::andnq(Register dst, Register src1, Register src2) {
6563 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6564 int encode = vex_prefix_0F38_and_encode_q_legacy(dst, src1, src2);
6565 emit_int8((unsigned char)0xF2);
6566 emit_int8((unsigned char)(0xC0 | encode));
6567 }
6568
6569 void Assembler::andnq(Register dst, Register src1, Address src2) {
6570 InstructionMark im(this);
6571 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6572 vex_prefix_0F38_q_legacy(dst, src1, src2);
6573 emit_int8((unsigned char)0xF2);
6574 emit_operand(dst, src2);
6575 }
6576
6577 void Assembler::bsfq(Register dst, Register src) {
6578 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6579 emit_int8(0x0F);
6580 emit_int8((unsigned char)0xBC);
6581 emit_int8((unsigned char)(0xC0 | encode));
6582 }
6583
6584 void Assembler::bsrq(Register dst, Register src) {
6585 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6586 emit_int8(0x0F);
6587 emit_int8((unsigned char)0xBD);
6588 emit_int8((unsigned char)(0xC0 | encode));
6589 }
6590
6591 void Assembler::bswapq(Register reg) {
6592 int encode = prefixq_and_encode(reg->encoding());
6593 emit_int8(0x0F);
6594 emit_int8((unsigned char)(0xC8 | encode));
6595 }
6596
6597 void Assembler::blsiq(Register dst, Register src) {
6598 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6599 int encode = vex_prefix_0F38_and_encode_q_legacy(rbx, dst, src);
6600 emit_int8((unsigned char)0xF3);
6601 emit_int8((unsigned char)(0xC0 | encode));
6602 }
6603
6604 void Assembler::blsiq(Register dst, Address src) {
6605 InstructionMark im(this);
6606 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6607 vex_prefix_0F38_q_legacy(rbx, dst, src);
6608 emit_int8((unsigned char)0xF3);
6609 emit_operand(rbx, src);
6610 }
6611
6612 void Assembler::blsmskq(Register dst, Register src) {
6613 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6614 int encode = vex_prefix_0F38_and_encode_q_legacy(rdx, dst, src);
6615 emit_int8((unsigned char)0xF3);
6616 emit_int8((unsigned char)(0xC0 | encode));
6617 }
6618
6619 void Assembler::blsmskq(Register dst, Address src) {
6620 InstructionMark im(this);
6621 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6622 vex_prefix_0F38_q_legacy(rdx, dst, src);
6623 emit_int8((unsigned char)0xF3);
6624 emit_operand(rdx, src);
6625 }
6626
6627 void Assembler::blsrq(Register dst, Register src) {
6628 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6629 int encode = vex_prefix_0F38_and_encode_q_legacy(rcx, dst, src);
6630 emit_int8((unsigned char)0xF3);
6631 emit_int8((unsigned char)(0xC0 | encode));
6632 }
6633
6634 void Assembler::blsrq(Register dst, Address src) {
6635 InstructionMark im(this);
6636 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6637 vex_prefix_0F38_q_legacy(rcx, dst, src);
6638 emit_int8((unsigned char)0xF3);
6639 emit_operand(rcx, src);
6640 }
6641
6642 void Assembler::cdqq() {
6643 prefix(REX_W);
6644 emit_int8((unsigned char)0x99);
6645 }
6646
6647 void Assembler::clflush(Address adr) {
6648 prefix(adr);
6649 emit_int8(0x0F);
6650 emit_int8((unsigned char)0xAE);
6651 emit_operand(rdi, adr);
6652 }
6653
6654 void Assembler::cmovq(Condition cc, Register dst, Register src) {
6655 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6656 emit_int8(0x0F);
6657 emit_int8(0x40 | cc);
6658 emit_int8((unsigned char)(0xC0 | encode));
6659 }
6660
6661 void Assembler::cmovq(Condition cc, Register dst, Address src) {
6662 InstructionMark im(this);
6663 prefixq(src, dst);
6664 emit_int8(0x0F);
6665 emit_int8(0x40 | cc);
6666 emit_operand(dst, src);
6667 }
6668
6669 void Assembler::cmpq(Address dst, int32_t imm32) {
6670 InstructionMark im(this);
6671 prefixq(dst);
6672 emit_int8((unsigned char)0x81);
6673 emit_operand(rdi, dst, 4);
6674 emit_int32(imm32);
6675 }
6676
6677 void Assembler::cmpq(Register dst, int32_t imm32) {
6678 (void) prefixq_and_encode(dst->encoding());
6679 emit_arith(0x81, 0xF8, dst, imm32);
6680 }
6681
6682 void Assembler::cmpq(Address dst, Register src) {
6683 InstructionMark im(this);
6684 prefixq(dst, src);
6685 emit_int8(0x3B);
6686 emit_operand(src, dst);
6687 }
6688
6689 void Assembler::cmpq(Register dst, Register src) {
6690 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6691 emit_arith(0x3B, 0xC0, dst, src);
6692 }
6693
6694 void Assembler::cmpq(Register dst, Address src) {
6695 InstructionMark im(this);
6696 prefixq(src, dst);
6697 emit_int8(0x3B);
6698 emit_operand(dst, src);
6699 }
6700
6701 void Assembler::cmpxchgq(Register reg, Address adr) {
6702 InstructionMark im(this);
6703 prefixq(adr, reg);
6704 emit_int8(0x0F);
6705 emit_int8((unsigned char)0xB1);
6706 emit_operand(reg, adr);
6707 }
6708
6709 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
6710 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6711 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2, true);
6712 emit_int8(0x2A);
6713 emit_int8((unsigned char)(0xC0 | encode));
6714 }
6715
6716 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
6717 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6718 if (VM_Version::supports_evex()) {
6719 tuple_type = EVEX_T1S;
6720 input_size_in_bits = EVEX_32bit;
6721 }
6722 InstructionMark im(this);
6723 simd_prefix_q(dst, dst, src, VEX_SIMD_F2, true);
6724 emit_int8(0x2A);
6725 emit_operand(dst, src);
6726 }
6727
6728 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
6729 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6730 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3, true);
6731 emit_int8(0x2A);
6732 emit_int8((unsigned char)(0xC0 | encode));
6733 }
6734
6735 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
6736 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6737 if (VM_Version::supports_evex()) {
6738 tuple_type = EVEX_T1S;
6739 input_size_in_bits = EVEX_32bit;
6740 }
6741 InstructionMark im(this);
6742 simd_prefix_q(dst, dst, src, VEX_SIMD_F3, true);
6743 emit_int8(0x2A);
6744 emit_operand(dst, src);
6745 }
6746
6747 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
6748 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6749 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, true);
6750 emit_int8(0x2C);
6751 emit_int8((unsigned char)(0xC0 | encode));
6752 }
6753
6754 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
6755 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6756 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, true);
6757 emit_int8(0x2C);
6758 emit_int8((unsigned char)(0xC0 | encode));
6759 }
6760
6761 void Assembler::decl(Register dst) {
6762 // Don't use it directly. Use MacroAssembler::decrementl() instead.
6763 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
6764 int encode = prefix_and_encode(dst->encoding());
6765 emit_int8((unsigned char)0xFF);
6766 emit_int8((unsigned char)(0xC8 | encode));
6767 }
6768
6769 void Assembler::decq(Register dst) {
6770 // Don't use it directly. Use MacroAssembler::decrementq() instead.
6771 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
6772 int encode = prefixq_and_encode(dst->encoding());
6773 emit_int8((unsigned char)0xFF);
6774 emit_int8(0xC8 | encode);
6775 }
6776
6777 void Assembler::decq(Address dst) {
6778 // Don't use it directly. Use MacroAssembler::decrementq() instead.
6779 InstructionMark im(this);
6780 prefixq(dst);
6781 emit_int8((unsigned char)0xFF);
6782 emit_operand(rcx, dst);
6783 }
6784
6785 void Assembler::fxrstor(Address src) {
6786 prefixq(src);
6787 emit_int8(0x0F);
6788 emit_int8((unsigned char)0xAE);
6789 emit_operand(as_Register(1), src);
6790 }
6791
6792 void Assembler::fxsave(Address dst) {
6793 prefixq(dst);
6794 emit_int8(0x0F);
6795 emit_int8((unsigned char)0xAE);
6796 emit_operand(as_Register(0), dst);
6797 }
6798
6799 void Assembler::idivq(Register src) {
6800 int encode = prefixq_and_encode(src->encoding());
6801 emit_int8((unsigned char)0xF7);
6802 emit_int8((unsigned char)(0xF8 | encode));
6803 }
6804
6805 void Assembler::imulq(Register dst, Register src) {
6806 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6807 emit_int8(0x0F);
6808 emit_int8((unsigned char)0xAF);
6809 emit_int8((unsigned char)(0xC0 | encode));
6810 }
6811
6812 void Assembler::imulq(Register dst, Register src, int value) {
6813 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6814 if (is8bit(value)) {
6815 emit_int8(0x6B);
6816 emit_int8((unsigned char)(0xC0 | encode));
6817 emit_int8(value & 0xFF);
6818 } else {
6819 emit_int8(0x69);
6820 emit_int8((unsigned char)(0xC0 | encode));
6821 emit_int32(value);
6822 }
6823 }
6824
6825 void Assembler::imulq(Register dst, Address src) {
6826 InstructionMark im(this);
6827 prefixq(src, dst);
6828 emit_int8(0x0F);
6829 emit_int8((unsigned char) 0xAF);
6830 emit_operand(dst, src);
6831 }
6832
6833 void Assembler::incl(Register dst) {
6834 // Don't use it directly. Use MacroAssembler::incrementl() instead.
6835 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
6836 int encode = prefix_and_encode(dst->encoding());
6837 emit_int8((unsigned char)0xFF);
6838 emit_int8((unsigned char)(0xC0 | encode));
6839 }
6840
6841 void Assembler::incq(Register dst) {
6842 // Don't use it directly. Use MacroAssembler::incrementq() instead.
6843 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
6844 int encode = prefixq_and_encode(dst->encoding());
6845 emit_int8((unsigned char)0xFF);
6846 emit_int8((unsigned char)(0xC0 | encode));
6847 }
6848
6849 void Assembler::incq(Address dst) {
6850 // Don't use it directly. Use MacroAssembler::incrementq() instead.
6851 InstructionMark im(this);
6852 prefixq(dst);
6853 emit_int8((unsigned char)0xFF);
6854 emit_operand(rax, dst);
6855 }
6856
6857 void Assembler::lea(Register dst, Address src) {
6858 leaq(dst, src);
6859 }
6860
6861 void Assembler::leaq(Register dst, Address src) {
6862 InstructionMark im(this);
6863 prefixq(src, dst);
6864 emit_int8((unsigned char)0x8D);
6865 emit_operand(dst, src);
6866 }
6867
6868 void Assembler::mov64(Register dst, int64_t imm64) {
6869 InstructionMark im(this);
6870 int encode = prefixq_and_encode(dst->encoding());
6871 emit_int8((unsigned char)(0xB8 | encode));
6872 emit_int64(imm64);
6873 }
6874
6875 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
6876 InstructionMark im(this);
6877 int encode = prefixq_and_encode(dst->encoding());
6878 emit_int8(0xB8 | encode);
6879 emit_data64(imm64, rspec);
6880 }
6881
6882 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
6883 InstructionMark im(this);
6884 int encode = prefix_and_encode(dst->encoding());
6885 emit_int8((unsigned char)(0xB8 | encode));
6886 emit_data((int)imm32, rspec, narrow_oop_operand);
6887 }
6888
6889 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
6890 InstructionMark im(this);
6891 prefix(dst);
6892 emit_int8((unsigned char)0xC7);
6893 emit_operand(rax, dst, 4);
6894 emit_data((int)imm32, rspec, narrow_oop_operand);
6895 }
6896
6897 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
6898 InstructionMark im(this);
6899 int encode = prefix_and_encode(src1->encoding());
6900 emit_int8((unsigned char)0x81);
6901 emit_int8((unsigned char)(0xF8 | encode));
6902 emit_data((int)imm32, rspec, narrow_oop_operand);
6903 }
6904
6905 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
6906 InstructionMark im(this);
6907 prefix(src1);
6908 emit_int8((unsigned char)0x81);
6909 emit_operand(rax, src1, 4);
6910 emit_data((int)imm32, rspec, narrow_oop_operand);
6911 }
6912
6913 void Assembler::lzcntq(Register dst, Register src) {
6914 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
6915 emit_int8((unsigned char)0xF3);
6916 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6917 emit_int8(0x0F);
6918 emit_int8((unsigned char)0xBD);
6919 emit_int8((unsigned char)(0xC0 | encode));
6920 }
6921
6922 void Assembler::movdq(XMMRegister dst, Register src) {
6923 // table D-1 says MMX/SSE2
6924 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6925 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66, true);
6926 emit_int8(0x6E);
6927 emit_int8((unsigned char)(0xC0 | encode));
6928 }
6929
6930 void Assembler::movdq(Register dst, XMMRegister src) {
6931 // table D-1 says MMX/SSE2
6932 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6933 // swap src/dst to get correct prefix
6934 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66, true);
6935 emit_int8(0x7E);
6936 emit_int8((unsigned char)(0xC0 | encode));
6937 }
6938
6939 void Assembler::movq(Register dst, Register src) {
6940 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6941 emit_int8((unsigned char)0x8B);
6942 emit_int8((unsigned char)(0xC0 | encode));
6943 }
6944
6945 void Assembler::movq(Register dst, Address src) {
6946 InstructionMark im(this);
6947 prefixq(src, dst);
6948 emit_int8((unsigned char)0x8B);
6949 emit_operand(dst, src);
6950 }
6951
6952 void Assembler::movq(Address dst, Register src) {
6953 InstructionMark im(this);
6954 prefixq(dst, src);
6955 emit_int8((unsigned char)0x89);
6956 emit_operand(src, dst);
6957 }
6958
6959 void Assembler::movsbq(Register dst, Address src) {
6960 InstructionMark im(this);
6961 prefixq(src, dst);
6962 emit_int8(0x0F);
6963 emit_int8((unsigned char)0xBE);
6964 emit_operand(dst, src);
6965 }
6966
6967 void Assembler::movsbq(Register dst, Register src) {
6968 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6969 emit_int8(0x0F);
6970 emit_int8((unsigned char)0xBE);
6971 emit_int8((unsigned char)(0xC0 | encode));
6972 }
6973
6974 void Assembler::movslq(Register dst, int32_t imm32) {
6975 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
6976 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
6977 // as a result we shouldn't use until tested at runtime...
6978 ShouldNotReachHere();
6979 InstructionMark im(this);
6980 int encode = prefixq_and_encode(dst->encoding());
6981 emit_int8((unsigned char)(0xC7 | encode));
6982 emit_int32(imm32);
6983 }
6984
6985 void Assembler::movslq(Address dst, int32_t imm32) {
6986 assert(is_simm32(imm32), "lost bits");
6987 InstructionMark im(this);
6988 prefixq(dst);
6989 emit_int8((unsigned char)0xC7);
6990 emit_operand(rax, dst, 4);
6991 emit_int32(imm32);
6992 }
6993
6994 void Assembler::movslq(Register dst, Address src) {
6995 InstructionMark im(this);
6996 prefixq(src, dst);
6997 emit_int8(0x63);
6998 emit_operand(dst, src);
6999 }
7000
7001 void Assembler::movslq(Register dst, Register src) {
7002 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7003 emit_int8(0x63);
7004 emit_int8((unsigned char)(0xC0 | encode));
7005 }
7006
7007 void Assembler::movswq(Register dst, Address src) {
7008 InstructionMark im(this);
7009 prefixq(src, dst);
7010 emit_int8(0x0F);
7011 emit_int8((unsigned char)0xBF);
7012 emit_operand(dst, src);
7013 }
7014
7015 void Assembler::movswq(Register dst, Register src) {
7016 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7017 emit_int8((unsigned char)0x0F);
7018 emit_int8((unsigned char)0xBF);
7019 emit_int8((unsigned char)(0xC0 | encode));
7020 }
7021
7022 void Assembler::movzbq(Register dst, Address src) {
7023 InstructionMark im(this);
7024 prefixq(src, dst);
7025 emit_int8((unsigned char)0x0F);
7026 emit_int8((unsigned char)0xB6);
7027 emit_operand(dst, src);
7028 }
7029
7030 void Assembler::movzbq(Register dst, Register src) {
7031 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7032 emit_int8(0x0F);
7033 emit_int8((unsigned char)0xB6);
7034 emit_int8(0xC0 | encode);
7035 }
7036
7037 void Assembler::movzwq(Register dst, Address src) {
7038 InstructionMark im(this);
7039 prefixq(src, dst);
7040 emit_int8((unsigned char)0x0F);
7041 emit_int8((unsigned char)0xB7);
7042 emit_operand(dst, src);
7043 }
7044
7045 void Assembler::movzwq(Register dst, Register src) {
7046 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7047 emit_int8((unsigned char)0x0F);
7048 emit_int8((unsigned char)0xB7);
7049 emit_int8((unsigned char)(0xC0 | encode));
7050 }
7051
7052 void Assembler::mulq(Address src) {
7053 InstructionMark im(this);
7054 prefixq(src);
7055 emit_int8((unsigned char)0xF7);
7056 emit_operand(rsp, src);
7057 }
7058
7059 void Assembler::mulq(Register src) {
7060 int encode = prefixq_and_encode(src->encoding());
7061 emit_int8((unsigned char)0xF7);
7062 emit_int8((unsigned char)(0xE0 | encode));
7063 }
7064
7065 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
7066 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
7067 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(),
7068 VEX_SIMD_F2, VEX_OPCODE_0F_38, true, AVX_128bit, true, false);
7069 emit_int8((unsigned char)0xF6);
7070 emit_int8((unsigned char)(0xC0 | encode));
7071 }
7072
7073 void Assembler::negq(Register dst) {
7074 int encode = prefixq_and_encode(dst->encoding());
7075 emit_int8((unsigned char)0xF7);
7076 emit_int8((unsigned char)(0xD8 | encode));
7077 }
7078
7079 void Assembler::notq(Register dst) {
7080 int encode = prefixq_and_encode(dst->encoding());
7081 emit_int8((unsigned char)0xF7);
7082 emit_int8((unsigned char)(0xD0 | encode));
7083 }
7084
7085 void Assembler::orq(Address dst, int32_t imm32) {
7086 InstructionMark im(this);
7087 prefixq(dst);
7088 emit_int8((unsigned char)0x81);
7089 emit_operand(rcx, dst, 4);
7090 emit_int32(imm32);
7091 }
7092
7093 void Assembler::orq(Register dst, int32_t imm32) {
7094 (void) prefixq_and_encode(dst->encoding());
7095 emit_arith(0x81, 0xC8, dst, imm32);
7096 }
7097
7098 void Assembler::orq(Register dst, Address src) {
7099 InstructionMark im(this);
7100 prefixq(src, dst);
7101 emit_int8(0x0B);
7102 emit_operand(dst, src);
7103 }
7104
7105 void Assembler::orq(Register dst, Register src) {
7106 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7107 emit_arith(0x0B, 0xC0, dst, src);
7108 }
7109
7110 void Assembler::popa() { // 64bit
7111 movq(r15, Address(rsp, 0));
7112 movq(r14, Address(rsp, wordSize));
7113 movq(r13, Address(rsp, 2 * wordSize));
7114 movq(r12, Address(rsp, 3 * wordSize));
7115 movq(r11, Address(rsp, 4 * wordSize));
7116 movq(r10, Address(rsp, 5 * wordSize));
7117 movq(r9, Address(rsp, 6 * wordSize));
7118 movq(r8, Address(rsp, 7 * wordSize));
7119 movq(rdi, Address(rsp, 8 * wordSize));
7120 movq(rsi, Address(rsp, 9 * wordSize));
7121 movq(rbp, Address(rsp, 10 * wordSize));
7122 // skip rsp
7123 movq(rbx, Address(rsp, 12 * wordSize));
7124 movq(rdx, Address(rsp, 13 * wordSize));
7125 movq(rcx, Address(rsp, 14 * wordSize));
7126 movq(rax, Address(rsp, 15 * wordSize));
7127
7128 addq(rsp, 16 * wordSize);
7129 }
7130
7131 void Assembler::popcntq(Register dst, Address src) {
7132 assert(VM_Version::supports_popcnt(), "must support");
7133 InstructionMark im(this);
7134 emit_int8((unsigned char)0xF3);
7135 prefixq(src, dst);
7136 emit_int8((unsigned char)0x0F);
7137 emit_int8((unsigned char)0xB8);
7138 emit_operand(dst, src);
7139 }
7140
7141 void Assembler::popcntq(Register dst, Register src) {
7142 assert(VM_Version::supports_popcnt(), "must support");
7143 emit_int8((unsigned char)0xF3);
7144 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7145 emit_int8((unsigned char)0x0F);
7146 emit_int8((unsigned char)0xB8);
7147 emit_int8((unsigned char)(0xC0 | encode));
7148 }
7149
7150 void Assembler::popq(Address dst) {
7151 InstructionMark im(this);
7152 prefixq(dst);
7153 emit_int8((unsigned char)0x8F);
7154 emit_operand(rax, dst);
7155 }
7156
7157 void Assembler::pusha() { // 64bit
7158 // we have to store original rsp. ABI says that 128 bytes
7159 // below rsp are local scratch.
7160 movq(Address(rsp, -5 * wordSize), rsp);
7161
7162 subq(rsp, 16 * wordSize);
7163
7164 movq(Address(rsp, 15 * wordSize), rax);
7165 movq(Address(rsp, 14 * wordSize), rcx);
7166 movq(Address(rsp, 13 * wordSize), rdx);
7167 movq(Address(rsp, 12 * wordSize), rbx);
7168 // skip rsp
7169 movq(Address(rsp, 10 * wordSize), rbp);
7170 movq(Address(rsp, 9 * wordSize), rsi);
7171 movq(Address(rsp, 8 * wordSize), rdi);
7172 movq(Address(rsp, 7 * wordSize), r8);
7173 movq(Address(rsp, 6 * wordSize), r9);
7174 movq(Address(rsp, 5 * wordSize), r10);
7175 movq(Address(rsp, 4 * wordSize), r11);
7176 movq(Address(rsp, 3 * wordSize), r12);
7177 movq(Address(rsp, 2 * wordSize), r13);
7178 movq(Address(rsp, wordSize), r14);
7179 movq(Address(rsp, 0), r15);
7180 }
7181
7182 void Assembler::pushq(Address src) {
7183 InstructionMark im(this);
7184 prefixq(src);
7185 emit_int8((unsigned char)0xFF);
7186 emit_operand(rsi, src);
7187 }
7188
7189 void Assembler::rclq(Register dst, int imm8) {
7190 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7191 int encode = prefixq_and_encode(dst->encoding());
7192 if (imm8 == 1) {
7193 emit_int8((unsigned char)0xD1);
7194 emit_int8((unsigned char)(0xD0 | encode));
7195 } else {
7196 emit_int8((unsigned char)0xC1);
7197 emit_int8((unsigned char)(0xD0 | encode));
7198 emit_int8(imm8);
7199 }
7200 }
7201
7202 void Assembler::rcrq(Register dst, int imm8) {
7203 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7204 int encode = prefixq_and_encode(dst->encoding());
7205 if (imm8 == 1) {
7206 emit_int8((unsigned char)0xD1);
7207 emit_int8((unsigned char)(0xD8 | encode));
7208 } else {
7209 emit_int8((unsigned char)0xC1);
7210 emit_int8((unsigned char)(0xD8 | encode));
7211 emit_int8(imm8);
7212 }
7213 }
7214
7215 void Assembler::rorq(Register dst, int imm8) {
7216 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7217 int encode = prefixq_and_encode(dst->encoding());
7218 if (imm8 == 1) {
7219 emit_int8((unsigned char)0xD1);
7220 emit_int8((unsigned char)(0xC8 | encode));
7221 } else {
7222 emit_int8((unsigned char)0xC1);
7223 emit_int8((unsigned char)(0xc8 | encode));
7224 emit_int8(imm8);
7225 }
7226 }
7227
7228 void Assembler::rorxq(Register dst, Register src, int imm8) {
7229 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
7230 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2,
7231 VEX_OPCODE_0F_3A, true, AVX_128bit, true, false);
7232 emit_int8((unsigned char)0xF0);
7233 emit_int8((unsigned char)(0xC0 | encode));
7234 emit_int8(imm8);
7235 }
7236
7237 void Assembler::sarq(Register dst, int imm8) {
7238 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7239 int encode = prefixq_and_encode(dst->encoding());
7240 if (imm8 == 1) {
7241 emit_int8((unsigned char)0xD1);
7242 emit_int8((unsigned char)(0xF8 | encode));
7243 } else {
7244 emit_int8((unsigned char)0xC1);
7245 emit_int8((unsigned char)(0xF8 | encode));
7246 emit_int8(imm8);
7247 }
7248 }
7249
7250 void Assembler::sarq(Register dst) {
7251 int encode = prefixq_and_encode(dst->encoding());
7252 emit_int8((unsigned char)0xD3);
7253 emit_int8((unsigned char)(0xF8 | encode));
7254 }
7255
7256 void Assembler::sbbq(Address dst, int32_t imm32) {
7257 InstructionMark im(this);
7258 prefixq(dst);
7259 emit_arith_operand(0x81, rbx, dst, imm32);
7260 }
7261
7262 void Assembler::sbbq(Register dst, int32_t imm32) {
7263 (void) prefixq_and_encode(dst->encoding());
7264 emit_arith(0x81, 0xD8, dst, imm32);
7265 }
7266
7267 void Assembler::sbbq(Register dst, Address src) {
7268 InstructionMark im(this);
7269 prefixq(src, dst);
7270 emit_int8(0x1B);
7271 emit_operand(dst, src);
7272 }
7273
7274 void Assembler::sbbq(Register dst, Register src) {
7275 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7276 emit_arith(0x1B, 0xC0, dst, src);
7277 }
7278
7279 void Assembler::shlq(Register dst, int imm8) {
7280 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7281 int encode = prefixq_and_encode(dst->encoding());
7282 if (imm8 == 1) {
7283 emit_int8((unsigned char)0xD1);
7284 emit_int8((unsigned char)(0xE0 | encode));
7285 } else {
7286 emit_int8((unsigned char)0xC1);
7287 emit_int8((unsigned char)(0xE0 | encode));
7288 emit_int8(imm8);
7289 }
7290 }
7291
7292 void Assembler::shlq(Register dst) {
7293 int encode = prefixq_and_encode(dst->encoding());
7294 emit_int8((unsigned char)0xD3);
7295 emit_int8((unsigned char)(0xE0 | encode));
7296 }
7297
7298 void Assembler::shrq(Register dst, int imm8) {
7299 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7300 int encode = prefixq_and_encode(dst->encoding());
7301 emit_int8((unsigned char)0xC1);
7302 emit_int8((unsigned char)(0xE8 | encode));
7303 emit_int8(imm8);
7304 }
7305
7306 void Assembler::shrq(Register dst) {
7307 int encode = prefixq_and_encode(dst->encoding());
7308 emit_int8((unsigned char)0xD3);
7309 emit_int8(0xE8 | encode);
7310 }
7311
7312 void Assembler::subq(Address dst, int32_t imm32) {
7313 InstructionMark im(this);
7314 prefixq(dst);
7315 emit_arith_operand(0x81, rbp, dst, imm32);
7316 }
7317
7318 void Assembler::subq(Address dst, Register src) {
7319 InstructionMark im(this);
7320 prefixq(dst, src);
7321 emit_int8(0x29);
7322 emit_operand(src, dst);
7323 }
7324
7325 void Assembler::subq(Register dst, int32_t imm32) {
7326 (void) prefixq_and_encode(dst->encoding());
7327 emit_arith(0x81, 0xE8, dst, imm32);
7328 }
7329
7330 // Force generation of a 4 byte immediate value even if it fits into 8bit
7331 void Assembler::subq_imm32(Register dst, int32_t imm32) {
7332 (void) prefixq_and_encode(dst->encoding());
7333 emit_arith_imm32(0x81, 0xE8, dst, imm32);
7334 }
7335
7336 void Assembler::subq(Register dst, Address src) {
7337 InstructionMark im(this);
7338 prefixq(src, dst);
7339 emit_int8(0x2B);
7340 emit_operand(dst, src);
7341 }
7342
7343 void Assembler::subq(Register dst, Register src) {
7344 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7345 emit_arith(0x2B, 0xC0, dst, src);
7346 }
7347
7348 void Assembler::testq(Register dst, int32_t imm32) {
7349 // not using emit_arith because test
7350 // doesn't support sign-extension of
7351 // 8bit operands
7352 int encode = dst->encoding();
7353 if (encode == 0) {
7354 prefix(REX_W);
7355 emit_int8((unsigned char)0xA9);
7356 } else {
7357 encode = prefixq_and_encode(encode);
7358 emit_int8((unsigned char)0xF7);
7359 emit_int8((unsigned char)(0xC0 | encode));
7360 }
7361 emit_int32(imm32);
7362 }
7363
7364 void Assembler::testq(Register dst, Register src) {
7365 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7366 emit_arith(0x85, 0xC0, dst, src);
7367 }
7368
7369 void Assembler::xaddq(Address dst, Register src) {
7370 InstructionMark im(this);
7371 prefixq(dst, src);
7372 emit_int8(0x0F);
7373 emit_int8((unsigned char)0xC1);
7374 emit_operand(src, dst);
7375 }
7376
7377 void Assembler::xchgq(Register dst, Address src) {
7378 InstructionMark im(this);
7379 prefixq(src, dst);
7380 emit_int8((unsigned char)0x87);
7381 emit_operand(dst, src);
7382 }
7383
7384 void Assembler::xchgq(Register dst, Register src) {
7385 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7386 emit_int8((unsigned char)0x87);
7387 emit_int8((unsigned char)(0xc0 | encode));
7388 }
7389
7390 void Assembler::xorq(Register dst, Register src) {
7391 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7392 emit_arith(0x33, 0xC0, dst, src);
7393 }
7394
7395 void Assembler::xorq(Register dst, Address src) {
7396 InstructionMark im(this);
7397 prefixq(src, dst);
7398 emit_int8(0x33);
7399 emit_operand(dst, src);
7400 }
7401
7402 #endif // !LP64