648 if (supports_clmul()) {
649 if (FLAG_IS_DEFAULT(UseCLMUL)) {
650 UseCLMUL = true;
651 }
652 } else if (UseCLMUL) {
653 if (!FLAG_IS_DEFAULT(UseCLMUL))
654 warning("CLMUL instructions not available on this CPU (AVX may also be required)");
655 FLAG_SET_DEFAULT(UseCLMUL, false);
656 }
657
658 if (UseCLMUL && (UseSSE > 2)) {
659 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
660 UseCRC32Intrinsics = true;
661 }
662 } else if (UseCRC32Intrinsics) {
663 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
664 warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
665 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
666 }
667
668 // The AES intrinsic stubs require AES instruction support (of course)
669 // but also require sse3 mode for instructions it use.
670 if (UseAES && (UseSSE > 2)) {
671 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
672 UseAESIntrinsics = true;
673 }
674 } else if (UseAESIntrinsics) {
675 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
676 warning("AES intrinsics are not available on this CPU");
677 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
678 }
679
680 // GHASH/GCM intrinsics
681 if (UseCLMUL && (UseSSE > 2)) {
682 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
683 UseGHASHIntrinsics = true;
684 }
685 } else if (UseGHASHIntrinsics) {
686 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
687 warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
688 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
689 }
690
691 if (UseSHA) {
692 warning("SHA instructions are not available on this CPU");
693 FLAG_SET_DEFAULT(UseSHA, false);
694 }
695 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
696 warning("SHA intrinsics are not available on this CPU");
697 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
698 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
699 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
700 }
701
702 if (UseCRC32CIntrinsics) {
703 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics))
704 warning("CRC32C intrinsics are not available on this CPU");
705 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
706 }
707
708 // Adjust RTM (Restricted Transactional Memory) flags
709 if (!supports_rtm() && UseRTMLocking) {
710 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
711 // setting during arguments processing. See use_biased_locking().
712 // VM_Version_init() is executed after UseBiasedLocking is used
713 // in Thread::allocate().
714 vm_exit_during_initialization("RTM instructions are not available on this CPU");
715 }
716
717 #if INCLUDE_RTM_OPT
718 if (UseRTMLocking) {
719 if (is_intel_family_core()) {
720 if ((_model == CPU_MODEL_HASWELL_E3) ||
721 (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) ||
722 (_model == CPU_MODEL_BROADWELL && _stepping < 4)) {
723 // currently a collision between SKL and HSW_E3
724 if (!UnlockExperimentalVMOptions && UseAVX < 3) {
725 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
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648 if (supports_clmul()) {
649 if (FLAG_IS_DEFAULT(UseCLMUL)) {
650 UseCLMUL = true;
651 }
652 } else if (UseCLMUL) {
653 if (!FLAG_IS_DEFAULT(UseCLMUL))
654 warning("CLMUL instructions not available on this CPU (AVX may also be required)");
655 FLAG_SET_DEFAULT(UseCLMUL, false);
656 }
657
658 if (UseCLMUL && (UseSSE > 2)) {
659 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
660 UseCRC32Intrinsics = true;
661 }
662 } else if (UseCRC32Intrinsics) {
663 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
664 warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
665 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
666 }
667
668 if (supports_sse4_2()) {
669 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
670 UseCRC32CIntrinsics = true;
671 }
672 }
673 else if (UseCRC32CIntrinsics) {
674 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
675 warning("CRC32C intrinsics are not available on this CPU");
676 }
677 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
678 }
679
680 // The AES intrinsic stubs require AES instruction support (of course)
681 // but also require sse3 mode for instructions it use.
682 if (UseAES && (UseSSE > 2)) {
683 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
684 UseAESIntrinsics = true;
685 }
686 } else if (UseAESIntrinsics) {
687 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
688 warning("AES intrinsics are not available on this CPU");
689 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
690 }
691
692 // GHASH/GCM intrinsics
693 if (UseCLMUL && (UseSSE > 2)) {
694 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
695 UseGHASHIntrinsics = true;
696 }
697 } else if (UseGHASHIntrinsics) {
698 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
699 warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
700 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
701 }
702
703 if (UseSHA) {
704 warning("SHA instructions are not available on this CPU");
705 FLAG_SET_DEFAULT(UseSHA, false);
706 }
707 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
708 warning("SHA intrinsics are not available on this CPU");
709 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
710 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
711 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
712 }
713
714 // Adjust RTM (Restricted Transactional Memory) flags
715 if (!supports_rtm() && UseRTMLocking) {
716 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
717 // setting during arguments processing. See use_biased_locking().
718 // VM_Version_init() is executed after UseBiasedLocking is used
719 // in Thread::allocate().
720 vm_exit_during_initialization("RTM instructions are not available on this CPU");
721 }
722
723 #if INCLUDE_RTM_OPT
724 if (UseRTMLocking) {
725 if (is_intel_family_core()) {
726 if ((_model == CPU_MODEL_HASWELL_E3) ||
727 (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) ||
728 (_model == CPU_MODEL_BROADWELL && _stepping < 4)) {
729 // currently a collision between SKL and HSW_E3
730 if (!UnlockExperimentalVMOptions && UseAVX < 3) {
731 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
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