< prev index next >

src/cpu/x86/vm/assembler_x86.cpp

Print this page




1588 
1589 void Assembler::comiss(XMMRegister dst, Address src) {
1590   if (VM_Version::supports_evex()) {
1591     tuple_type = EVEX_T1S;
1592     input_size_in_bits = EVEX_32bit;
1593   }
1594   NOT_LP64(assert(VM_Version::supports_sse(), ""));
1595   emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE, true);
1596 }
1597 
1598 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1599   NOT_LP64(assert(VM_Version::supports_sse(), ""));
1600   emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE, true);
1601 }
1602 
1603 void Assembler::cpuid() {
1604   emit_int8(0x0F);
1605   emit_int8((unsigned char)0xA2);
1606 }
1607 















































































1608 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1609   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1610   emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3);
1611 }
1612 
1613 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1614   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1615   emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE);
1616 }
1617 
1618 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1619   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1620   if (VM_Version::supports_evex()) {
1621     emit_simd_arith_q(0x5A, dst, src, VEX_SIMD_F2);
1622   } else {
1623     emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1624   }
1625 }
1626 
1627 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {


5994   emit_int8(0x68);
5995   emit_data(imm32, rspec, 0);
5996 }
5997 
5998 void Assembler::pusha() { // 32bit
5999   emit_int8(0x60);
6000 }
6001 
6002 void Assembler::set_byte_if_not_zero(Register dst) {
6003   emit_int8(0x0F);
6004   emit_int8((unsigned char)0x95);
6005   emit_int8((unsigned char)(0xE0 | dst->encoding()));
6006 }
6007 
6008 void Assembler::shldl(Register dst, Register src) {
6009   emit_int8(0x0F);
6010   emit_int8((unsigned char)0xA5);
6011   emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6012 }
6013 








6014 void Assembler::shrdl(Register dst, Register src) {
6015   emit_int8(0x0F);
6016   emit_int8((unsigned char)0xAD);
6017   emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6018 }
6019 
6020 #else // LP64
6021 
6022 void Assembler::set_byte_if_not_zero(Register dst) {
6023   int enc = prefix_and_encode(dst->encoding(), true);
6024   emit_int8(0x0F);
6025   emit_int8((unsigned char)0x95);
6026   emit_int8((unsigned char)(0xE0 | enc));
6027 }
6028 
6029 // 64bit only pieces of the assembler
6030 // This should only be used by 64bit instructions that can use rip-relative
6031 // it cannot be used by instructions that want an immediate value.
6032 
6033 bool Assembler::reachable(AddressLiteral adr) {


6176       prefix(REX_W);
6177     } else {
6178       prefix(REX_WB);
6179       src_enc -= 8;
6180     }
6181   } else {
6182     if (src_enc < 8) {
6183       prefix(REX_WR);
6184     } else {
6185       prefix(REX_WRB);
6186       src_enc -= 8;
6187     }
6188     dst_enc -= 8;
6189   }
6190   return dst_enc << 3 | src_enc;
6191 }
6192 
6193 void Assembler::prefix(Register reg) {
6194   if (reg->encoding() >= 8) {
6195     prefix(REX_B);


































6196   }
6197 }
6198 
6199 void Assembler::prefix(Address adr) {
6200   if (adr.base_needs_rex()) {
6201     if (adr.index_needs_rex()) {
6202       prefix(REX_XB);
6203     } else {
6204       prefix(REX_B);
6205     }
6206   } else {
6207     if (adr.index_needs_rex()) {
6208       prefix(REX_X);
6209     }
6210   }
6211 }
6212 
6213 void Assembler::prefixq(Address adr) {
6214   if (adr.base_needs_rex()) {
6215     if (adr.index_needs_rex()) {




1588 
1589 void Assembler::comiss(XMMRegister dst, Address src) {
1590   if (VM_Version::supports_evex()) {
1591     tuple_type = EVEX_T1S;
1592     input_size_in_bits = EVEX_32bit;
1593   }
1594   NOT_LP64(assert(VM_Version::supports_sse(), ""));
1595   emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE, true);
1596 }
1597 
1598 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1599   NOT_LP64(assert(VM_Version::supports_sse(), ""));
1600   emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE, true);
1601 }
1602 
1603 void Assembler::cpuid() {
1604   emit_int8(0x0F);
1605   emit_int8((unsigned char)0xA2);
1606 }
1607 
1608 // Opcode / Instruction                      Op /  En  64 - Bit Mode     Compat / Leg Mode Description                  Implemented
1609 // F2 0F 38 F0 / r       CRC32 r32, r / m8   RM        Valid             Valid             Accumulate CRC32 on r / m8.  v
1610 // F2 REX 0F 38 F0 / r   CRC32 r32, r / m8*  RM        Valid             N.E.              Accumulate CRC32 on r / m8.  -
1611 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8   RM        Valid             N.E.              Accumulate CRC32 on r / m8.  -
1612 //
1613 // F2 0F 38 F1 / r       CRC32 r32, r / m16  RM        Valid             Valid             Accumulate CRC32 on r / m16. v
1614 //
1615 // F2 0F 38 F1 / r       CRC32 r32, r / m32  RM        Valid             Valid             Accumulate CRC32 on r / m32. v
1616 //
1617 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64  RM        Valid             N.E.              Accumulate CRC32 on r / m64. v
1618 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1619   assert(VM_Version::supports_sse4_2(), "");
1620   int8_t w = 0x01;
1621   Prefix p = Prefix_EMPTY;
1622 
1623   emit_int8((int8_t)0xF2);
1624   switch (sizeInBytes) {
1625   case 1:
1626     w = 0;
1627     break;
1628   case 2:
1629   case 4:
1630     break;
1631   LP64_ONLY(case 8:)
1632     // This instruction is not valid in 32 bits
1633     // Note:
1634     // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1635     //
1636     // Page B - 72   Vol. 2C says
1637     // qwreg2 to qwreg            1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1638     // mem64 to qwreg             1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1639     //                                                                            F0!!!
1640     // while 3 - 208 Vol. 2A
1641     // F2 REX.W 0F 38 F1 / r       CRC32 r64, r / m64             RM         Valid      N.E.Accumulate CRC32 on r / m64.
1642     //
1643     // the 0 on a last bit is reserved for a different flavor of this instruction :
1644     // F2 REX.W 0F 38 F0 / r       CRC32 r64, r / m8              RM         Valid      N.E.Accumulate CRC32 on r / m8.
1645     p = REX_W;
1646     break;
1647   default:
1648     assert(0, "Unsupported value for a sizeInBytes argument");
1649     break;
1650   }
1651   LP64_ONLY(prefix(crc, v, p);)
1652   emit_int8((int8_t)0x0F);
1653   emit_int8(0x38);
1654   emit_int8((int8_t)(0xF0 | w));
1655   emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1656 }
1657 
1658 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1659   assert(VM_Version::supports_sse4_2(), "");
1660   InstructionMark im(this);
1661   int8_t w = 0x01;
1662   Prefix p = Prefix_EMPTY;
1663 
1664   emit_int8((int8_t)0xF2);
1665   switch (sizeInBytes) {
1666   case 1:
1667     w = 0;
1668     break;
1669   case 2:
1670   case 4:
1671     break;
1672   LP64_ONLY(case 8:)
1673     // This instruction is not valid in 32 bits
1674     p = REX_W;
1675     break;
1676   default:
1677     assert(0, "Unsupported value for a sizeInBytes argument");
1678     break;
1679   }
1680   LP64_ONLY(prefix(crc, adr, p);)
1681   emit_int8((int8_t)0x0F);
1682   emit_int8(0x38);
1683   emit_int8((int8_t)(0xF0 | w));
1684   emit_operand(crc, adr);
1685 }
1686 
1687 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1688   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1689   emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3);
1690 }
1691 
1692 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1693   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1694   emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE);
1695 }
1696 
1697 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1698   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1699   if (VM_Version::supports_evex()) {
1700     emit_simd_arith_q(0x5A, dst, src, VEX_SIMD_F2);
1701   } else {
1702     emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1703   }
1704 }
1705 
1706 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {


6073   emit_int8(0x68);
6074   emit_data(imm32, rspec, 0);
6075 }
6076 
6077 void Assembler::pusha() { // 32bit
6078   emit_int8(0x60);
6079 }
6080 
6081 void Assembler::set_byte_if_not_zero(Register dst) {
6082   emit_int8(0x0F);
6083   emit_int8((unsigned char)0x95);
6084   emit_int8((unsigned char)(0xE0 | dst->encoding()));
6085 }
6086 
6087 void Assembler::shldl(Register dst, Register src) {
6088   emit_int8(0x0F);
6089   emit_int8((unsigned char)0xA5);
6090   emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6091 }
6092 
6093 // 0F A4 / r ib
6094 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
6095   emit_int8(0x0F);
6096   emit_int8((unsigned char)0xA4);
6097   emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6098   emit_int8(imm8);
6099 }
6100 
6101 void Assembler::shrdl(Register dst, Register src) {
6102   emit_int8(0x0F);
6103   emit_int8((unsigned char)0xAD);
6104   emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6105 }
6106 
6107 #else // LP64
6108 
6109 void Assembler::set_byte_if_not_zero(Register dst) {
6110   int enc = prefix_and_encode(dst->encoding(), true);
6111   emit_int8(0x0F);
6112   emit_int8((unsigned char)0x95);
6113   emit_int8((unsigned char)(0xE0 | enc));
6114 }
6115 
6116 // 64bit only pieces of the assembler
6117 // This should only be used by 64bit instructions that can use rip-relative
6118 // it cannot be used by instructions that want an immediate value.
6119 
6120 bool Assembler::reachable(AddressLiteral adr) {


6263       prefix(REX_W);
6264     } else {
6265       prefix(REX_WB);
6266       src_enc -= 8;
6267     }
6268   } else {
6269     if (src_enc < 8) {
6270       prefix(REX_WR);
6271     } else {
6272       prefix(REX_WRB);
6273       src_enc -= 8;
6274     }
6275     dst_enc -= 8;
6276   }
6277   return dst_enc << 3 | src_enc;
6278 }
6279 
6280 void Assembler::prefix(Register reg) {
6281   if (reg->encoding() >= 8) {
6282     prefix(REX_B);
6283   }
6284 }
6285 
6286 void Assembler::prefix(Register dst, Register src, Prefix p) {
6287   if (src->encoding() >= 8) {
6288     p = (Prefix)(p | REX_B);
6289   }
6290   if (dst->encoding() >= 8) {
6291     p = (Prefix)( p | REX_R);
6292   }
6293   if (p != Prefix_EMPTY) {
6294     // do not generate an empty prefix
6295     prefix(p);
6296   }
6297 }
6298 
6299 void Assembler::prefix(Register dst, Address adr, Prefix p) {
6300   if (adr.base_needs_rex()) {
6301     if (adr.index_needs_rex()) {
6302       assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
6303     } else {
6304       prefix(REX_B);
6305     }
6306   } else {
6307     if (adr.index_needs_rex()) {
6308       assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
6309     }
6310   }
6311   if (dst->encoding() >= 8) {
6312     p = (Prefix)(p | REX_R);
6313   }
6314   if (p != Prefix_EMPTY) {
6315     // do not generate an empty prefix
6316     prefix(p);
6317   }
6318 }
6319 
6320 void Assembler::prefix(Address adr) {
6321   if (adr.base_needs_rex()) {
6322     if (adr.index_needs_rex()) {
6323       prefix(REX_XB);
6324     } else {
6325       prefix(REX_B);
6326     }
6327   } else {
6328     if (adr.index_needs_rex()) {
6329       prefix(REX_X);
6330     }
6331   }
6332 }
6333 
6334 void Assembler::prefixq(Address adr) {
6335   if (adr.base_needs_rex()) {
6336     if (adr.index_needs_rex()) {


< prev index next >