1 /* 2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/assembler.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "compiler/disassembler.hpp" 29 #include "gc/shared/cardTableModRefBS.hpp" 30 #include "gc/shared/collectedHeap.inline.hpp" 31 #include "interpreter/interpreter.hpp" 32 #include "memory/resourceArea.hpp" 33 #include "memory/universe.hpp" 34 #include "oops/klass.inline.hpp" 35 #include "prims/methodHandles.hpp" 36 #include "runtime/biasedLocking.hpp" 37 #include "runtime/interfaceSupport.hpp" 38 #include "runtime/objectMonitor.hpp" 39 #include "runtime/os.hpp" 40 #include "runtime/sharedRuntime.hpp" 41 #include "runtime/stubRoutines.hpp" 42 #include "utilities/macros.hpp" 43 #if INCLUDE_ALL_GCS 44 #include "gc/g1/g1CollectedHeap.inline.hpp" 45 #include "gc/g1/g1SATBCardTableModRefBS.hpp" 46 #include "gc/g1/heapRegion.hpp" 47 #endif // INCLUDE_ALL_GCS 48 #include "crc32c.h" 49 50 #ifdef PRODUCT 51 #define BLOCK_COMMENT(str) /* nothing */ 52 #define STOP(error) stop(error) 53 #else 54 #define BLOCK_COMMENT(str) block_comment(str) 55 #define STOP(error) block_comment(error); stop(error) 56 #endif 57 58 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 59 60 PRAGMA_FORMAT_MUTE_WARNINGS_FOR_GCC 61 62 #ifdef ASSERT 63 bool AbstractAssembler::pd_check_instruction_mark() { return true; } 64 #endif 65 66 static Assembler::Condition reverse[] = { 67 Assembler::noOverflow /* overflow = 0x0 */ , 68 Assembler::overflow /* noOverflow = 0x1 */ , 69 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , 70 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , 71 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , 72 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , 73 Assembler::above /* belowEqual = 0x6 */ , 74 Assembler::belowEqual /* above = 0x7 */ , 75 Assembler::positive /* negative = 0x8 */ , 76 Assembler::negative /* positive = 0x9 */ , 77 Assembler::noParity /* parity = 0xa */ , 78 Assembler::parity /* noParity = 0xb */ , 79 Assembler::greaterEqual /* less = 0xc */ , 80 Assembler::less /* greaterEqual = 0xd */ , 81 Assembler::greater /* lessEqual = 0xe */ , 82 Assembler::lessEqual /* greater = 0xf, */ 83 84 }; 85 86 87 // Implementation of MacroAssembler 88 89 // First all the versions that have distinct versions depending on 32/64 bit 90 // Unless the difference is trivial (1 line or so). 91 92 #ifndef _LP64 93 94 // 32bit versions 95 96 Address MacroAssembler::as_Address(AddressLiteral adr) { 97 return Address(adr.target(), adr.rspec()); 98 } 99 100 Address MacroAssembler::as_Address(ArrayAddress adr) { 101 return Address::make_array(adr); 102 } 103 104 void MacroAssembler::call_VM_leaf_base(address entry_point, 105 int number_of_arguments) { 106 call(RuntimeAddress(entry_point)); 107 increment(rsp, number_of_arguments * wordSize); 108 } 109 110 void MacroAssembler::cmpklass(Address src1, Metadata* obj) { 111 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 112 } 113 114 void MacroAssembler::cmpklass(Register src1, Metadata* obj) { 115 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 116 } 117 118 void MacroAssembler::cmpoop(Address src1, jobject obj) { 119 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 120 } 121 122 void MacroAssembler::cmpoop(Register src1, jobject obj) { 123 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 124 } 125 126 void MacroAssembler::extend_sign(Register hi, Register lo) { 127 // According to Intel Doc. AP-526, "Integer Divide", p.18. 128 if (VM_Version::is_P6() && hi == rdx && lo == rax) { 129 cdql(); 130 } else { 131 movl(hi, lo); 132 sarl(hi, 31); 133 } 134 } 135 136 void MacroAssembler::jC2(Register tmp, Label& L) { 137 // set parity bit if FPU flag C2 is set (via rax) 138 save_rax(tmp); 139 fwait(); fnstsw_ax(); 140 sahf(); 141 restore_rax(tmp); 142 // branch 143 jcc(Assembler::parity, L); 144 } 145 146 void MacroAssembler::jnC2(Register tmp, Label& L) { 147 // set parity bit if FPU flag C2 is set (via rax) 148 save_rax(tmp); 149 fwait(); fnstsw_ax(); 150 sahf(); 151 restore_rax(tmp); 152 // branch 153 jcc(Assembler::noParity, L); 154 } 155 156 // 32bit can do a case table jump in one instruction but we no longer allow the base 157 // to be installed in the Address class 158 void MacroAssembler::jump(ArrayAddress entry) { 159 jmp(as_Address(entry)); 160 } 161 162 // Note: y_lo will be destroyed 163 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 164 // Long compare for Java (semantics as described in JVM spec.) 165 Label high, low, done; 166 167 cmpl(x_hi, y_hi); 168 jcc(Assembler::less, low); 169 jcc(Assembler::greater, high); 170 // x_hi is the return register 171 xorl(x_hi, x_hi); 172 cmpl(x_lo, y_lo); 173 jcc(Assembler::below, low); 174 jcc(Assembler::equal, done); 175 176 bind(high); 177 xorl(x_hi, x_hi); 178 increment(x_hi); 179 jmp(done); 180 181 bind(low); 182 xorl(x_hi, x_hi); 183 decrementl(x_hi); 184 185 bind(done); 186 } 187 188 void MacroAssembler::lea(Register dst, AddressLiteral src) { 189 mov_literal32(dst, (int32_t)src.target(), src.rspec()); 190 } 191 192 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 193 // leal(dst, as_Address(adr)); 194 // see note in movl as to why we must use a move 195 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); 196 } 197 198 void MacroAssembler::leave() { 199 mov(rsp, rbp); 200 pop(rbp); 201 } 202 203 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { 204 // Multiplication of two Java long values stored on the stack 205 // as illustrated below. Result is in rdx:rax. 206 // 207 // rsp ---> [ ?? ] \ \ 208 // .... | y_rsp_offset | 209 // [ y_lo ] / (in bytes) | x_rsp_offset 210 // [ y_hi ] | (in bytes) 211 // .... | 212 // [ x_lo ] / 213 // [ x_hi ] 214 // .... 215 // 216 // Basic idea: lo(result) = lo(x_lo * y_lo) 217 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 218 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); 219 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); 220 Label quick; 221 // load x_hi, y_hi and check if quick 222 // multiplication is possible 223 movl(rbx, x_hi); 224 movl(rcx, y_hi); 225 movl(rax, rbx); 226 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 227 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply 228 // do full multiplication 229 // 1st step 230 mull(y_lo); // x_hi * y_lo 231 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, 232 // 2nd step 233 movl(rax, x_lo); 234 mull(rcx); // x_lo * y_hi 235 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, 236 // 3rd step 237 bind(quick); // note: rbx, = 0 if quick multiply! 238 movl(rax, x_lo); 239 mull(y_lo); // x_lo * y_lo 240 addl(rdx, rbx); // correct hi(x_lo * y_lo) 241 } 242 243 void MacroAssembler::lneg(Register hi, Register lo) { 244 negl(lo); 245 adcl(hi, 0); 246 negl(hi); 247 } 248 249 void MacroAssembler::lshl(Register hi, Register lo) { 250 // Java shift left long support (semantics as described in JVM spec., p.305) 251 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) 252 // shift value is in rcx ! 253 assert(hi != rcx, "must not use rcx"); 254 assert(lo != rcx, "must not use rcx"); 255 const Register s = rcx; // shift count 256 const int n = BitsPerWord; 257 Label L; 258 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 259 cmpl(s, n); // if (s < n) 260 jcc(Assembler::less, L); // else (s >= n) 261 movl(hi, lo); // x := x << n 262 xorl(lo, lo); 263 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 264 bind(L); // s (mod n) < n 265 shldl(hi, lo); // x := x << s 266 shll(lo); 267 } 268 269 270 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { 271 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) 272 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) 273 assert(hi != rcx, "must not use rcx"); 274 assert(lo != rcx, "must not use rcx"); 275 const Register s = rcx; // shift count 276 const int n = BitsPerWord; 277 Label L; 278 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 279 cmpl(s, n); // if (s < n) 280 jcc(Assembler::less, L); // else (s >= n) 281 movl(lo, hi); // x := x >> n 282 if (sign_extension) sarl(hi, 31); 283 else xorl(hi, hi); 284 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 285 bind(L); // s (mod n) < n 286 shrdl(lo, hi); // x := x >> s 287 if (sign_extension) sarl(hi); 288 else shrl(hi); 289 } 290 291 void MacroAssembler::movoop(Register dst, jobject obj) { 292 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 293 } 294 295 void MacroAssembler::movoop(Address dst, jobject obj) { 296 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 297 } 298 299 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 300 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 301 } 302 303 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 304 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 305 } 306 307 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 308 // scratch register is not used, 309 // it is defined to match parameters of 64-bit version of this method. 310 if (src.is_lval()) { 311 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); 312 } else { 313 movl(dst, as_Address(src)); 314 } 315 } 316 317 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 318 movl(as_Address(dst), src); 319 } 320 321 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 322 movl(dst, as_Address(src)); 323 } 324 325 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 326 void MacroAssembler::movptr(Address dst, intptr_t src) { 327 movl(dst, src); 328 } 329 330 331 void MacroAssembler::pop_callee_saved_registers() { 332 pop(rcx); 333 pop(rdx); 334 pop(rdi); 335 pop(rsi); 336 } 337 338 void MacroAssembler::pop_fTOS() { 339 fld_d(Address(rsp, 0)); 340 addl(rsp, 2 * wordSize); 341 } 342 343 void MacroAssembler::push_callee_saved_registers() { 344 push(rsi); 345 push(rdi); 346 push(rdx); 347 push(rcx); 348 } 349 350 void MacroAssembler::push_fTOS() { 351 subl(rsp, 2 * wordSize); 352 fstp_d(Address(rsp, 0)); 353 } 354 355 356 void MacroAssembler::pushoop(jobject obj) { 357 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); 358 } 359 360 void MacroAssembler::pushklass(Metadata* obj) { 361 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate()); 362 } 363 364 void MacroAssembler::pushptr(AddressLiteral src) { 365 if (src.is_lval()) { 366 push_literal32((int32_t)src.target(), src.rspec()); 367 } else { 368 pushl(as_Address(src)); 369 } 370 } 371 372 void MacroAssembler::set_word_if_not_zero(Register dst) { 373 xorl(dst, dst); 374 set_byte_if_not_zero(dst); 375 } 376 377 static void pass_arg0(MacroAssembler* masm, Register arg) { 378 masm->push(arg); 379 } 380 381 static void pass_arg1(MacroAssembler* masm, Register arg) { 382 masm->push(arg); 383 } 384 385 static void pass_arg2(MacroAssembler* masm, Register arg) { 386 masm->push(arg); 387 } 388 389 static void pass_arg3(MacroAssembler* masm, Register arg) { 390 masm->push(arg); 391 } 392 393 #ifndef PRODUCT 394 extern "C" void findpc(intptr_t x); 395 #endif 396 397 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { 398 // In order to get locks to work, we need to fake a in_VM state 399 JavaThread* thread = JavaThread::current(); 400 JavaThreadState saved_state = thread->thread_state(); 401 thread->set_thread_state(_thread_in_vm); 402 if (ShowMessageBoxOnError) { 403 JavaThread* thread = JavaThread::current(); 404 JavaThreadState saved_state = thread->thread_state(); 405 thread->set_thread_state(_thread_in_vm); 406 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 407 ttyLocker ttyl; 408 BytecodeCounter::print(); 409 } 410 // To see where a verify_oop failed, get $ebx+40/X for this frame. 411 // This is the value of eip which points to where verify_oop will return. 412 if (os::message_box(msg, "Execution stopped, print registers?")) { 413 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip); 414 BREAKPOINT; 415 } 416 } else { 417 ttyLocker ttyl; 418 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); 419 } 420 // Don't assert holding the ttyLock 421 assert(false, err_msg("DEBUG MESSAGE: %s", msg)); 422 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 423 } 424 425 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) { 426 ttyLocker ttyl; 427 FlagSetting fs(Debugging, true); 428 tty->print_cr("eip = 0x%08x", eip); 429 #ifndef PRODUCT 430 if ((WizardMode || Verbose) && PrintMiscellaneous) { 431 tty->cr(); 432 findpc(eip); 433 tty->cr(); 434 } 435 #endif 436 #define PRINT_REG(rax) \ 437 { tty->print("%s = ", #rax); os::print_location(tty, rax); } 438 PRINT_REG(rax); 439 PRINT_REG(rbx); 440 PRINT_REG(rcx); 441 PRINT_REG(rdx); 442 PRINT_REG(rdi); 443 PRINT_REG(rsi); 444 PRINT_REG(rbp); 445 PRINT_REG(rsp); 446 #undef PRINT_REG 447 // Print some words near top of staack. 448 int* dump_sp = (int*) rsp; 449 for (int col1 = 0; col1 < 8; col1++) { 450 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 451 os::print_location(tty, *dump_sp++); 452 } 453 for (int row = 0; row < 16; row++) { 454 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 455 for (int col = 0; col < 8; col++) { 456 tty->print(" 0x%08x", *dump_sp++); 457 } 458 tty->cr(); 459 } 460 // Print some instructions around pc: 461 Disassembler::decode((address)eip-64, (address)eip); 462 tty->print_cr("--------"); 463 Disassembler::decode((address)eip, (address)eip+32); 464 } 465 466 void MacroAssembler::stop(const char* msg) { 467 ExternalAddress message((address)msg); 468 // push address of message 469 pushptr(message.addr()); 470 { Label L; call(L, relocInfo::none); bind(L); } // push eip 471 pusha(); // push registers 472 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); 473 hlt(); 474 } 475 476 void MacroAssembler::warn(const char* msg) { 477 push_CPU_state(); 478 479 ExternalAddress message((address) msg); 480 // push address of message 481 pushptr(message.addr()); 482 483 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); 484 addl(rsp, wordSize); // discard argument 485 pop_CPU_state(); 486 } 487 488 void MacroAssembler::print_state() { 489 { Label L; call(L, relocInfo::none); bind(L); } // push eip 490 pusha(); // push registers 491 492 push_CPU_state(); 493 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32))); 494 pop_CPU_state(); 495 496 popa(); 497 addl(rsp, wordSize); 498 } 499 500 #else // _LP64 501 502 // 64 bit versions 503 504 Address MacroAssembler::as_Address(AddressLiteral adr) { 505 // amd64 always does this as a pc-rel 506 // we can be absolute or disp based on the instruction type 507 // jmp/call are displacements others are absolute 508 assert(!adr.is_lval(), "must be rval"); 509 assert(reachable(adr), "must be"); 510 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); 511 512 } 513 514 Address MacroAssembler::as_Address(ArrayAddress adr) { 515 AddressLiteral base = adr.base(); 516 lea(rscratch1, base); 517 Address index = adr.index(); 518 assert(index._disp == 0, "must not have disp"); // maybe it can? 519 Address array(rscratch1, index._index, index._scale, index._disp); 520 return array; 521 } 522 523 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { 524 Label L, E; 525 526 #ifdef _WIN64 527 // Windows always allocates space for it's register args 528 assert(num_args <= 4, "only register arguments supported"); 529 subq(rsp, frame::arg_reg_save_area_bytes); 530 #endif 531 532 // Align stack if necessary 533 testl(rsp, 15); 534 jcc(Assembler::zero, L); 535 536 subq(rsp, 8); 537 { 538 call(RuntimeAddress(entry_point)); 539 } 540 addq(rsp, 8); 541 jmp(E); 542 543 bind(L); 544 { 545 call(RuntimeAddress(entry_point)); 546 } 547 548 bind(E); 549 550 #ifdef _WIN64 551 // restore stack pointer 552 addq(rsp, frame::arg_reg_save_area_bytes); 553 #endif 554 555 } 556 557 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { 558 assert(!src2.is_lval(), "should use cmpptr"); 559 560 if (reachable(src2)) { 561 cmpq(src1, as_Address(src2)); 562 } else { 563 lea(rscratch1, src2); 564 Assembler::cmpq(src1, Address(rscratch1, 0)); 565 } 566 } 567 568 int MacroAssembler::corrected_idivq(Register reg) { 569 // Full implementation of Java ldiv and lrem; checks for special 570 // case as described in JVM spec., p.243 & p.271. The function 571 // returns the (pc) offset of the idivl instruction - may be needed 572 // for implicit exceptions. 573 // 574 // normal case special case 575 // 576 // input : rax: dividend min_long 577 // reg: divisor (may not be eax/edx) -1 578 // 579 // output: rax: quotient (= rax idiv reg) min_long 580 // rdx: remainder (= rax irem reg) 0 581 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); 582 static const int64_t min_long = 0x8000000000000000; 583 Label normal_case, special_case; 584 585 // check for special case 586 cmp64(rax, ExternalAddress((address) &min_long)); 587 jcc(Assembler::notEqual, normal_case); 588 xorl(rdx, rdx); // prepare rdx for possible special case (where 589 // remainder = 0) 590 cmpq(reg, -1); 591 jcc(Assembler::equal, special_case); 592 593 // handle normal case 594 bind(normal_case); 595 cdqq(); 596 int idivq_offset = offset(); 597 idivq(reg); 598 599 // normal and special case exit 600 bind(special_case); 601 602 return idivq_offset; 603 } 604 605 void MacroAssembler::decrementq(Register reg, int value) { 606 if (value == min_jint) { subq(reg, value); return; } 607 if (value < 0) { incrementq(reg, -value); return; } 608 if (value == 0) { ; return; } 609 if (value == 1 && UseIncDec) { decq(reg) ; return; } 610 /* else */ { subq(reg, value) ; return; } 611 } 612 613 void MacroAssembler::decrementq(Address dst, int value) { 614 if (value == min_jint) { subq(dst, value); return; } 615 if (value < 0) { incrementq(dst, -value); return; } 616 if (value == 0) { ; return; } 617 if (value == 1 && UseIncDec) { decq(dst) ; return; } 618 /* else */ { subq(dst, value) ; return; } 619 } 620 621 void MacroAssembler::incrementq(AddressLiteral dst) { 622 if (reachable(dst)) { 623 incrementq(as_Address(dst)); 624 } else { 625 lea(rscratch1, dst); 626 incrementq(Address(rscratch1, 0)); 627 } 628 } 629 630 void MacroAssembler::incrementq(Register reg, int value) { 631 if (value == min_jint) { addq(reg, value); return; } 632 if (value < 0) { decrementq(reg, -value); return; } 633 if (value == 0) { ; return; } 634 if (value == 1 && UseIncDec) { incq(reg) ; return; } 635 /* else */ { addq(reg, value) ; return; } 636 } 637 638 void MacroAssembler::incrementq(Address dst, int value) { 639 if (value == min_jint) { addq(dst, value); return; } 640 if (value < 0) { decrementq(dst, -value); return; } 641 if (value == 0) { ; return; } 642 if (value == 1 && UseIncDec) { incq(dst) ; return; } 643 /* else */ { addq(dst, value) ; return; } 644 } 645 646 // 32bit can do a case table jump in one instruction but we no longer allow the base 647 // to be installed in the Address class 648 void MacroAssembler::jump(ArrayAddress entry) { 649 lea(rscratch1, entry.base()); 650 Address dispatch = entry.index(); 651 assert(dispatch._base == noreg, "must be"); 652 dispatch._base = rscratch1; 653 jmp(dispatch); 654 } 655 656 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 657 ShouldNotReachHere(); // 64bit doesn't use two regs 658 cmpq(x_lo, y_lo); 659 } 660 661 void MacroAssembler::lea(Register dst, AddressLiteral src) { 662 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 663 } 664 665 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 666 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); 667 movptr(dst, rscratch1); 668 } 669 670 void MacroAssembler::leave() { 671 // %%% is this really better? Why not on 32bit too? 672 emit_int8((unsigned char)0xC9); // LEAVE 673 } 674 675 void MacroAssembler::lneg(Register hi, Register lo) { 676 ShouldNotReachHere(); // 64bit doesn't use two regs 677 negq(lo); 678 } 679 680 void MacroAssembler::movoop(Register dst, jobject obj) { 681 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 682 } 683 684 void MacroAssembler::movoop(Address dst, jobject obj) { 685 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 686 movq(dst, rscratch1); 687 } 688 689 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 690 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 691 } 692 693 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 694 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 695 movq(dst, rscratch1); 696 } 697 698 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 699 if (src.is_lval()) { 700 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 701 } else { 702 if (reachable(src)) { 703 movq(dst, as_Address(src)); 704 } else { 705 lea(scratch, src); 706 movq(dst, Address(scratch, 0)); 707 } 708 } 709 } 710 711 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 712 movq(as_Address(dst), src); 713 } 714 715 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 716 movq(dst, as_Address(src)); 717 } 718 719 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 720 void MacroAssembler::movptr(Address dst, intptr_t src) { 721 mov64(rscratch1, src); 722 movq(dst, rscratch1); 723 } 724 725 // These are mostly for initializing NULL 726 void MacroAssembler::movptr(Address dst, int32_t src) { 727 movslq(dst, src); 728 } 729 730 void MacroAssembler::movptr(Register dst, int32_t src) { 731 mov64(dst, (intptr_t)src); 732 } 733 734 void MacroAssembler::pushoop(jobject obj) { 735 movoop(rscratch1, obj); 736 push(rscratch1); 737 } 738 739 void MacroAssembler::pushklass(Metadata* obj) { 740 mov_metadata(rscratch1, obj); 741 push(rscratch1); 742 } 743 744 void MacroAssembler::pushptr(AddressLiteral src) { 745 lea(rscratch1, src); 746 if (src.is_lval()) { 747 push(rscratch1); 748 } else { 749 pushq(Address(rscratch1, 0)); 750 } 751 } 752 753 void MacroAssembler::reset_last_Java_frame(bool clear_fp, 754 bool clear_pc) { 755 // we must set sp to zero to clear frame 756 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 757 // must clear fp, so that compiled frames are not confused; it is 758 // possible that we need it only for debugging 759 if (clear_fp) { 760 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 761 } 762 763 if (clear_pc) { 764 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 765 } 766 } 767 768 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 769 Register last_java_fp, 770 address last_java_pc) { 771 // determine last_java_sp register 772 if (!last_java_sp->is_valid()) { 773 last_java_sp = rsp; 774 } 775 776 // last_java_fp is optional 777 if (last_java_fp->is_valid()) { 778 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), 779 last_java_fp); 780 } 781 782 // last_java_pc is optional 783 if (last_java_pc != NULL) { 784 Address java_pc(r15_thread, 785 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); 786 lea(rscratch1, InternalAddress(last_java_pc)); 787 movptr(java_pc, rscratch1); 788 } 789 790 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 791 } 792 793 static void pass_arg0(MacroAssembler* masm, Register arg) { 794 if (c_rarg0 != arg ) { 795 masm->mov(c_rarg0, arg); 796 } 797 } 798 799 static void pass_arg1(MacroAssembler* masm, Register arg) { 800 if (c_rarg1 != arg ) { 801 masm->mov(c_rarg1, arg); 802 } 803 } 804 805 static void pass_arg2(MacroAssembler* masm, Register arg) { 806 if (c_rarg2 != arg ) { 807 masm->mov(c_rarg2, arg); 808 } 809 } 810 811 static void pass_arg3(MacroAssembler* masm, Register arg) { 812 if (c_rarg3 != arg ) { 813 masm->mov(c_rarg3, arg); 814 } 815 } 816 817 void MacroAssembler::stop(const char* msg) { 818 address rip = pc(); 819 pusha(); // get regs on stack 820 lea(c_rarg0, ExternalAddress((address) msg)); 821 lea(c_rarg1, InternalAddress(rip)); 822 movq(c_rarg2, rsp); // pass pointer to regs array 823 andq(rsp, -16); // align stack as required by ABI 824 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); 825 hlt(); 826 } 827 828 void MacroAssembler::warn(const char* msg) { 829 push(rbp); 830 movq(rbp, rsp); 831 andq(rsp, -16); // align stack as required by push_CPU_state and call 832 push_CPU_state(); // keeps alignment at 16 bytes 833 lea(c_rarg0, ExternalAddress((address) msg)); 834 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0); 835 pop_CPU_state(); 836 mov(rsp, rbp); 837 pop(rbp); 838 } 839 840 void MacroAssembler::print_state() { 841 address rip = pc(); 842 pusha(); // get regs on stack 843 push(rbp); 844 movq(rbp, rsp); 845 andq(rsp, -16); // align stack as required by push_CPU_state and call 846 push_CPU_state(); // keeps alignment at 16 bytes 847 848 lea(c_rarg0, InternalAddress(rip)); 849 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array 850 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1); 851 852 pop_CPU_state(); 853 mov(rsp, rbp); 854 pop(rbp); 855 popa(); 856 } 857 858 #ifndef PRODUCT 859 extern "C" void findpc(intptr_t x); 860 #endif 861 862 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { 863 // In order to get locks to work, we need to fake a in_VM state 864 if (ShowMessageBoxOnError) { 865 JavaThread* thread = JavaThread::current(); 866 JavaThreadState saved_state = thread->thread_state(); 867 thread->set_thread_state(_thread_in_vm); 868 #ifndef PRODUCT 869 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 870 ttyLocker ttyl; 871 BytecodeCounter::print(); 872 } 873 #endif 874 // To see where a verify_oop failed, get $ebx+40/X for this frame. 875 // XXX correct this offset for amd64 876 // This is the value of eip which points to where verify_oop will return. 877 if (os::message_box(msg, "Execution stopped, print registers?")) { 878 print_state64(pc, regs); 879 BREAKPOINT; 880 assert(false, "start up GDB"); 881 } 882 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 883 } else { 884 ttyLocker ttyl; 885 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", 886 msg); 887 assert(false, err_msg("DEBUG MESSAGE: %s", msg)); 888 } 889 } 890 891 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) { 892 ttyLocker ttyl; 893 FlagSetting fs(Debugging, true); 894 tty->print_cr("rip = 0x%016lx", pc); 895 #ifndef PRODUCT 896 tty->cr(); 897 findpc(pc); 898 tty->cr(); 899 #endif 900 #define PRINT_REG(rax, value) \ 901 { tty->print("%s = ", #rax); os::print_location(tty, value); } 902 PRINT_REG(rax, regs[15]); 903 PRINT_REG(rbx, regs[12]); 904 PRINT_REG(rcx, regs[14]); 905 PRINT_REG(rdx, regs[13]); 906 PRINT_REG(rdi, regs[8]); 907 PRINT_REG(rsi, regs[9]); 908 PRINT_REG(rbp, regs[10]); 909 PRINT_REG(rsp, regs[11]); 910 PRINT_REG(r8 , regs[7]); 911 PRINT_REG(r9 , regs[6]); 912 PRINT_REG(r10, regs[5]); 913 PRINT_REG(r11, regs[4]); 914 PRINT_REG(r12, regs[3]); 915 PRINT_REG(r13, regs[2]); 916 PRINT_REG(r14, regs[1]); 917 PRINT_REG(r15, regs[0]); 918 #undef PRINT_REG 919 // Print some words near top of staack. 920 int64_t* rsp = (int64_t*) regs[11]; 921 int64_t* dump_sp = rsp; 922 for (int col1 = 0; col1 < 8; col1++) { 923 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); 924 os::print_location(tty, *dump_sp++); 925 } 926 for (int row = 0; row < 25; row++) { 927 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); 928 for (int col = 0; col < 4; col++) { 929 tty->print(" 0x%016lx", *dump_sp++); 930 } 931 tty->cr(); 932 } 933 // Print some instructions around pc: 934 Disassembler::decode((address)pc-64, (address)pc); 935 tty->print_cr("--------"); 936 Disassembler::decode((address)pc, (address)pc+32); 937 } 938 939 #endif // _LP64 940 941 // Now versions that are common to 32/64 bit 942 943 void MacroAssembler::addptr(Register dst, int32_t imm32) { 944 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); 945 } 946 947 void MacroAssembler::addptr(Register dst, Register src) { 948 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 949 } 950 951 void MacroAssembler::addptr(Address dst, Register src) { 952 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 953 } 954 955 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) { 956 if (reachable(src)) { 957 Assembler::addsd(dst, as_Address(src)); 958 } else { 959 lea(rscratch1, src); 960 Assembler::addsd(dst, Address(rscratch1, 0)); 961 } 962 } 963 964 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) { 965 if (reachable(src)) { 966 addss(dst, as_Address(src)); 967 } else { 968 lea(rscratch1, src); 969 addss(dst, Address(rscratch1, 0)); 970 } 971 } 972 973 void MacroAssembler::align(int modulus) { 974 align(modulus, offset()); 975 } 976 977 void MacroAssembler::align(int modulus, int target) { 978 if (target % modulus != 0) { 979 nop(modulus - (target % modulus)); 980 } 981 } 982 983 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { 984 // Used in sign-masking with aligned address. 985 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 986 if (reachable(src)) { 987 Assembler::andpd(dst, as_Address(src)); 988 } else { 989 lea(rscratch1, src); 990 Assembler::andpd(dst, Address(rscratch1, 0)); 991 } 992 } 993 994 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) { 995 // Used in sign-masking with aligned address. 996 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 997 if (reachable(src)) { 998 Assembler::andps(dst, as_Address(src)); 999 } else { 1000 lea(rscratch1, src); 1001 Assembler::andps(dst, Address(rscratch1, 0)); 1002 } 1003 } 1004 1005 void MacroAssembler::andptr(Register dst, int32_t imm32) { 1006 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); 1007 } 1008 1009 void MacroAssembler::atomic_incl(Address counter_addr) { 1010 if (os::is_MP()) 1011 lock(); 1012 incrementl(counter_addr); 1013 } 1014 1015 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) { 1016 if (reachable(counter_addr)) { 1017 atomic_incl(as_Address(counter_addr)); 1018 } else { 1019 lea(scr, counter_addr); 1020 atomic_incl(Address(scr, 0)); 1021 } 1022 } 1023 1024 #ifdef _LP64 1025 void MacroAssembler::atomic_incq(Address counter_addr) { 1026 if (os::is_MP()) 1027 lock(); 1028 incrementq(counter_addr); 1029 } 1030 1031 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) { 1032 if (reachable(counter_addr)) { 1033 atomic_incq(as_Address(counter_addr)); 1034 } else { 1035 lea(scr, counter_addr); 1036 atomic_incq(Address(scr, 0)); 1037 } 1038 } 1039 #endif 1040 1041 // Writes to stack successive pages until offset reached to check for 1042 // stack overflow + shadow pages. This clobbers tmp. 1043 void MacroAssembler::bang_stack_size(Register size, Register tmp) { 1044 movptr(tmp, rsp); 1045 // Bang stack for total size given plus shadow page size. 1046 // Bang one page at a time because large size can bang beyond yellow and 1047 // red zones. 1048 Label loop; 1049 bind(loop); 1050 movl(Address(tmp, (-os::vm_page_size())), size ); 1051 subptr(tmp, os::vm_page_size()); 1052 subl(size, os::vm_page_size()); 1053 jcc(Assembler::greater, loop); 1054 1055 // Bang down shadow pages too. 1056 // At this point, (tmp-0) is the last address touched, so don't 1057 // touch it again. (It was touched as (tmp-pagesize) but then tmp 1058 // was post-decremented.) Skip this address by starting at i=1, and 1059 // touch a few more pages below. N.B. It is important to touch all 1060 // the way down to and including i=StackShadowPages. 1061 for (int i = 1; i < StackShadowPages; i++) { 1062 // this could be any sized move but this is can be a debugging crumb 1063 // so the bigger the better. 1064 movptr(Address(tmp, (-i*os::vm_page_size())), size ); 1065 } 1066 } 1067 1068 int MacroAssembler::biased_locking_enter(Register lock_reg, 1069 Register obj_reg, 1070 Register swap_reg, 1071 Register tmp_reg, 1072 bool swap_reg_contains_mark, 1073 Label& done, 1074 Label* slow_case, 1075 BiasedLockingCounters* counters) { 1076 assert(UseBiasedLocking, "why call this otherwise?"); 1077 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); 1078 assert(tmp_reg != noreg, "tmp_reg must be supplied"); 1079 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); 1080 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); 1081 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); 1082 Address saved_mark_addr(lock_reg, 0); 1083 1084 if (PrintBiasedLockingStatistics && counters == NULL) { 1085 counters = BiasedLocking::counters(); 1086 } 1087 // Biased locking 1088 // See whether the lock is currently biased toward our thread and 1089 // whether the epoch is still valid 1090 // Note that the runtime guarantees sufficient alignment of JavaThread 1091 // pointers to allow age to be placed into low bits 1092 // First check to see whether biasing is even enabled for this object 1093 Label cas_label; 1094 int null_check_offset = -1; 1095 if (!swap_reg_contains_mark) { 1096 null_check_offset = offset(); 1097 movptr(swap_reg, mark_addr); 1098 } 1099 movptr(tmp_reg, swap_reg); 1100 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place); 1101 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern); 1102 jcc(Assembler::notEqual, cas_label); 1103 // The bias pattern is present in the object's header. Need to check 1104 // whether the bias owner and the epoch are both still current. 1105 #ifndef _LP64 1106 // Note that because there is no current thread register on x86_32 we 1107 // need to store off the mark word we read out of the object to 1108 // avoid reloading it and needing to recheck invariants below. This 1109 // store is unfortunate but it makes the overall code shorter and 1110 // simpler. 1111 movptr(saved_mark_addr, swap_reg); 1112 #endif 1113 if (swap_reg_contains_mark) { 1114 null_check_offset = offset(); 1115 } 1116 load_prototype_header(tmp_reg, obj_reg); 1117 #ifdef _LP64 1118 orptr(tmp_reg, r15_thread); 1119 xorptr(tmp_reg, swap_reg); 1120 Register header_reg = tmp_reg; 1121 #else 1122 xorptr(tmp_reg, swap_reg); 1123 get_thread(swap_reg); 1124 xorptr(swap_reg, tmp_reg); 1125 Register header_reg = swap_reg; 1126 #endif 1127 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place)); 1128 if (counters != NULL) { 1129 cond_inc32(Assembler::zero, 1130 ExternalAddress((address) counters->biased_lock_entry_count_addr())); 1131 } 1132 jcc(Assembler::equal, done); 1133 1134 Label try_revoke_bias; 1135 Label try_rebias; 1136 1137 // At this point we know that the header has the bias pattern and 1138 // that we are not the bias owner in the current epoch. We need to 1139 // figure out more details about the state of the header in order to 1140 // know what operations can be legally performed on the object's 1141 // header. 1142 1143 // If the low three bits in the xor result aren't clear, that means 1144 // the prototype header is no longer biased and we have to revoke 1145 // the bias on this object. 1146 testptr(header_reg, markOopDesc::biased_lock_mask_in_place); 1147 jccb(Assembler::notZero, try_revoke_bias); 1148 1149 // Biasing is still enabled for this data type. See whether the 1150 // epoch of the current bias is still valid, meaning that the epoch 1151 // bits of the mark word are equal to the epoch bits of the 1152 // prototype header. (Note that the prototype header's epoch bits 1153 // only change at a safepoint.) If not, attempt to rebias the object 1154 // toward the current thread. Note that we must be absolutely sure 1155 // that the current epoch is invalid in order to do this because 1156 // otherwise the manipulations it performs on the mark word are 1157 // illegal. 1158 testptr(header_reg, markOopDesc::epoch_mask_in_place); 1159 jccb(Assembler::notZero, try_rebias); 1160 1161 // The epoch of the current bias is still valid but we know nothing 1162 // about the owner; it might be set or it might be clear. Try to 1163 // acquire the bias of the object using an atomic operation. If this 1164 // fails we will go in to the runtime to revoke the object's bias. 1165 // Note that we first construct the presumed unbiased header so we 1166 // don't accidentally blow away another thread's valid bias. 1167 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1168 andptr(swap_reg, 1169 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); 1170 #ifdef _LP64 1171 movptr(tmp_reg, swap_reg); 1172 orptr(tmp_reg, r15_thread); 1173 #else 1174 get_thread(tmp_reg); 1175 orptr(tmp_reg, swap_reg); 1176 #endif 1177 if (os::is_MP()) { 1178 lock(); 1179 } 1180 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1181 // If the biasing toward our thread failed, this means that 1182 // another thread succeeded in biasing it toward itself and we 1183 // need to revoke that bias. The revocation will occur in the 1184 // interpreter runtime in the slow case. 1185 if (counters != NULL) { 1186 cond_inc32(Assembler::zero, 1187 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); 1188 } 1189 if (slow_case != NULL) { 1190 jcc(Assembler::notZero, *slow_case); 1191 } 1192 jmp(done); 1193 1194 bind(try_rebias); 1195 // At this point we know the epoch has expired, meaning that the 1196 // current "bias owner", if any, is actually invalid. Under these 1197 // circumstances _only_, we are allowed to use the current header's 1198 // value as the comparison value when doing the cas to acquire the 1199 // bias in the current epoch. In other words, we allow transfer of 1200 // the bias from one thread to another directly in this situation. 1201 // 1202 // FIXME: due to a lack of registers we currently blow away the age 1203 // bits in this situation. Should attempt to preserve them. 1204 load_prototype_header(tmp_reg, obj_reg); 1205 #ifdef _LP64 1206 orptr(tmp_reg, r15_thread); 1207 #else 1208 get_thread(swap_reg); 1209 orptr(tmp_reg, swap_reg); 1210 movptr(swap_reg, saved_mark_addr); 1211 #endif 1212 if (os::is_MP()) { 1213 lock(); 1214 } 1215 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1216 // If the biasing toward our thread failed, then another thread 1217 // succeeded in biasing it toward itself and we need to revoke that 1218 // bias. The revocation will occur in the runtime in the slow case. 1219 if (counters != NULL) { 1220 cond_inc32(Assembler::zero, 1221 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); 1222 } 1223 if (slow_case != NULL) { 1224 jcc(Assembler::notZero, *slow_case); 1225 } 1226 jmp(done); 1227 1228 bind(try_revoke_bias); 1229 // The prototype mark in the klass doesn't have the bias bit set any 1230 // more, indicating that objects of this data type are not supposed 1231 // to be biased any more. We are going to try to reset the mark of 1232 // this object to the prototype value and fall through to the 1233 // CAS-based locking scheme. Note that if our CAS fails, it means 1234 // that another thread raced us for the privilege of revoking the 1235 // bias of this particular object, so it's okay to continue in the 1236 // normal locking code. 1237 // 1238 // FIXME: due to a lack of registers we currently blow away the age 1239 // bits in this situation. Should attempt to preserve them. 1240 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1241 load_prototype_header(tmp_reg, obj_reg); 1242 if (os::is_MP()) { 1243 lock(); 1244 } 1245 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1246 // Fall through to the normal CAS-based lock, because no matter what 1247 // the result of the above CAS, some thread must have succeeded in 1248 // removing the bias bit from the object's header. 1249 if (counters != NULL) { 1250 cond_inc32(Assembler::zero, 1251 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); 1252 } 1253 1254 bind(cas_label); 1255 1256 return null_check_offset; 1257 } 1258 1259 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { 1260 assert(UseBiasedLocking, "why call this otherwise?"); 1261 1262 // Check for biased locking unlock case, which is a no-op 1263 // Note: we do not have to check the thread ID for two reasons. 1264 // First, the interpreter checks for IllegalMonitorStateException at 1265 // a higher level. Second, if the bias was revoked while we held the 1266 // lock, the object could not be rebiased toward another thread, so 1267 // the bias bit would be clear. 1268 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); 1269 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); 1270 cmpptr(temp_reg, markOopDesc::biased_lock_pattern); 1271 jcc(Assembler::equal, done); 1272 } 1273 1274 #ifdef COMPILER2 1275 1276 #if INCLUDE_RTM_OPT 1277 1278 // Update rtm_counters based on abort status 1279 // input: abort_status 1280 // rtm_counters (RTMLockingCounters*) 1281 // flags are killed 1282 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) { 1283 1284 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset())); 1285 if (PrintPreciseRTMLockingStatistics) { 1286 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) { 1287 Label check_abort; 1288 testl(abort_status, (1<<i)); 1289 jccb(Assembler::equal, check_abort); 1290 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx)))); 1291 bind(check_abort); 1292 } 1293 } 1294 } 1295 1296 // Branch if (random & (count-1) != 0), count is 2^n 1297 // tmp, scr and flags are killed 1298 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) { 1299 assert(tmp == rax, ""); 1300 assert(scr == rdx, ""); 1301 rdtsc(); // modifies EDX:EAX 1302 andptr(tmp, count-1); 1303 jccb(Assembler::notZero, brLabel); 1304 } 1305 1306 // Perform abort ratio calculation, set no_rtm bit if high ratio 1307 // input: rtm_counters_Reg (RTMLockingCounters* address) 1308 // tmpReg, rtm_counters_Reg and flags are killed 1309 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg, 1310 Register rtm_counters_Reg, 1311 RTMLockingCounters* rtm_counters, 1312 Metadata* method_data) { 1313 Label L_done, L_check_always_rtm1, L_check_always_rtm2; 1314 1315 if (RTMLockingCalculationDelay > 0) { 1316 // Delay calculation 1317 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg); 1318 testptr(tmpReg, tmpReg); 1319 jccb(Assembler::equal, L_done); 1320 } 1321 // Abort ratio calculation only if abort_count > RTMAbortThreshold 1322 // Aborted transactions = abort_count * 100 1323 // All transactions = total_count * RTMTotalCountIncrRate 1324 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio) 1325 1326 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset())); 1327 cmpptr(tmpReg, RTMAbortThreshold); 1328 jccb(Assembler::below, L_check_always_rtm2); 1329 imulptr(tmpReg, tmpReg, 100); 1330 1331 Register scrReg = rtm_counters_Reg; 1332 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); 1333 imulptr(scrReg, scrReg, RTMTotalCountIncrRate); 1334 imulptr(scrReg, scrReg, RTMAbortRatio); 1335 cmpptr(tmpReg, scrReg); 1336 jccb(Assembler::below, L_check_always_rtm1); 1337 if (method_data != NULL) { 1338 // set rtm_state to "no rtm" in MDO 1339 mov_metadata(tmpReg, method_data); 1340 if (os::is_MP()) { 1341 lock(); 1342 } 1343 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM); 1344 } 1345 jmpb(L_done); 1346 bind(L_check_always_rtm1); 1347 // Reload RTMLockingCounters* address 1348 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); 1349 bind(L_check_always_rtm2); 1350 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); 1351 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate); 1352 jccb(Assembler::below, L_done); 1353 if (method_data != NULL) { 1354 // set rtm_state to "always rtm" in MDO 1355 mov_metadata(tmpReg, method_data); 1356 if (os::is_MP()) { 1357 lock(); 1358 } 1359 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM); 1360 } 1361 bind(L_done); 1362 } 1363 1364 // Update counters and perform abort ratio calculation 1365 // input: abort_status_Reg 1366 // rtm_counters_Reg, flags are killed 1367 void MacroAssembler::rtm_profiling(Register abort_status_Reg, 1368 Register rtm_counters_Reg, 1369 RTMLockingCounters* rtm_counters, 1370 Metadata* method_data, 1371 bool profile_rtm) { 1372 1373 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1374 // update rtm counters based on rax value at abort 1375 // reads abort_status_Reg, updates flags 1376 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); 1377 rtm_counters_update(abort_status_Reg, rtm_counters_Reg); 1378 if (profile_rtm) { 1379 // Save abort status because abort_status_Reg is used by following code. 1380 if (RTMRetryCount > 0) { 1381 push(abort_status_Reg); 1382 } 1383 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1384 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data); 1385 // restore abort status 1386 if (RTMRetryCount > 0) { 1387 pop(abort_status_Reg); 1388 } 1389 } 1390 } 1391 1392 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4) 1393 // inputs: retry_count_Reg 1394 // : abort_status_Reg 1395 // output: retry_count_Reg decremented by 1 1396 // flags are killed 1397 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) { 1398 Label doneRetry; 1399 assert(abort_status_Reg == rax, ""); 1400 // The abort reason bits are in eax (see all states in rtmLocking.hpp) 1401 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4) 1402 // if reason is in 0x6 and retry count != 0 then retry 1403 andptr(abort_status_Reg, 0x6); 1404 jccb(Assembler::zero, doneRetry); 1405 testl(retry_count_Reg, retry_count_Reg); 1406 jccb(Assembler::zero, doneRetry); 1407 pause(); 1408 decrementl(retry_count_Reg); 1409 jmp(retryLabel); 1410 bind(doneRetry); 1411 } 1412 1413 // Spin and retry if lock is busy, 1414 // inputs: box_Reg (monitor address) 1415 // : retry_count_Reg 1416 // output: retry_count_Reg decremented by 1 1417 // : clear z flag if retry count exceeded 1418 // tmp_Reg, scr_Reg, flags are killed 1419 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg, 1420 Register tmp_Reg, Register scr_Reg, Label& retryLabel) { 1421 Label SpinLoop, SpinExit, doneRetry; 1422 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1423 1424 testl(retry_count_Reg, retry_count_Reg); 1425 jccb(Assembler::zero, doneRetry); 1426 decrementl(retry_count_Reg); 1427 movptr(scr_Reg, RTMSpinLoopCount); 1428 1429 bind(SpinLoop); 1430 pause(); 1431 decrementl(scr_Reg); 1432 jccb(Assembler::lessEqual, SpinExit); 1433 movptr(tmp_Reg, Address(box_Reg, owner_offset)); 1434 testptr(tmp_Reg, tmp_Reg); 1435 jccb(Assembler::notZero, SpinLoop); 1436 1437 bind(SpinExit); 1438 jmp(retryLabel); 1439 bind(doneRetry); 1440 incrementl(retry_count_Reg); // clear z flag 1441 } 1442 1443 // Use RTM for normal stack locks 1444 // Input: objReg (object to lock) 1445 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg, 1446 Register retry_on_abort_count_Reg, 1447 RTMLockingCounters* stack_rtm_counters, 1448 Metadata* method_data, bool profile_rtm, 1449 Label& DONE_LABEL, Label& IsInflated) { 1450 assert(UseRTMForStackLocks, "why call this otherwise?"); 1451 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); 1452 assert(tmpReg == rax, ""); 1453 assert(scrReg == rdx, ""); 1454 Label L_rtm_retry, L_decrement_retry, L_on_abort; 1455 1456 if (RTMRetryCount > 0) { 1457 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort 1458 bind(L_rtm_retry); 1459 } 1460 movptr(tmpReg, Address(objReg, 0)); 1461 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased 1462 jcc(Assembler::notZero, IsInflated); 1463 1464 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1465 Label L_noincrement; 1466 if (RTMTotalCountIncrRate > 1) { 1467 // tmpReg, scrReg and flags are killed 1468 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement); 1469 } 1470 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM"); 1471 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg); 1472 bind(L_noincrement); 1473 } 1474 xbegin(L_on_abort); 1475 movptr(tmpReg, Address(objReg, 0)); // fetch markword 1476 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits 1477 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked 1478 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked 1479 1480 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX 1481 if (UseRTMXendForLockBusy) { 1482 xend(); 1483 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry) 1484 jmp(L_decrement_retry); 1485 } 1486 else { 1487 xabort(0); 1488 } 1489 bind(L_on_abort); 1490 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1491 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm); 1492 } 1493 bind(L_decrement_retry); 1494 if (RTMRetryCount > 0) { 1495 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) 1496 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); 1497 } 1498 } 1499 1500 // Use RTM for inflating locks 1501 // inputs: objReg (object to lock) 1502 // boxReg (on-stack box address (displaced header location) - KILLED) 1503 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value) 1504 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg, 1505 Register scrReg, Register retry_on_busy_count_Reg, 1506 Register retry_on_abort_count_Reg, 1507 RTMLockingCounters* rtm_counters, 1508 Metadata* method_data, bool profile_rtm, 1509 Label& DONE_LABEL) { 1510 assert(UseRTMLocking, "why call this otherwise?"); 1511 assert(tmpReg == rax, ""); 1512 assert(scrReg == rdx, ""); 1513 Label L_rtm_retry, L_decrement_retry, L_on_abort; 1514 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1515 1516 // Without cast to int32_t a movptr will destroy r10 which is typically obj 1517 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1518 movptr(boxReg, tmpReg); // Save ObjectMonitor address 1519 1520 if (RTMRetryCount > 0) { 1521 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy 1522 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort 1523 bind(L_rtm_retry); 1524 } 1525 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1526 Label L_noincrement; 1527 if (RTMTotalCountIncrRate > 1) { 1528 // tmpReg, scrReg and flags are killed 1529 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement); 1530 } 1531 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1532 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg); 1533 bind(L_noincrement); 1534 } 1535 xbegin(L_on_abort); 1536 movptr(tmpReg, Address(objReg, 0)); 1537 movptr(tmpReg, Address(tmpReg, owner_offset)); 1538 testptr(tmpReg, tmpReg); 1539 jcc(Assembler::zero, DONE_LABEL); 1540 if (UseRTMXendForLockBusy) { 1541 xend(); 1542 jmp(L_decrement_retry); 1543 } 1544 else { 1545 xabort(0); 1546 } 1547 bind(L_on_abort); 1548 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX 1549 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1550 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm); 1551 } 1552 if (RTMRetryCount > 0) { 1553 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) 1554 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); 1555 } 1556 1557 movptr(tmpReg, Address(boxReg, owner_offset)) ; 1558 testptr(tmpReg, tmpReg) ; 1559 jccb(Assembler::notZero, L_decrement_retry) ; 1560 1561 // Appears unlocked - try to swing _owner from null to non-null. 1562 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1563 #ifdef _LP64 1564 Register threadReg = r15_thread; 1565 #else 1566 get_thread(scrReg); 1567 Register threadReg = scrReg; 1568 #endif 1569 if (os::is_MP()) { 1570 lock(); 1571 } 1572 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg 1573 1574 if (RTMRetryCount > 0) { 1575 // success done else retry 1576 jccb(Assembler::equal, DONE_LABEL) ; 1577 bind(L_decrement_retry); 1578 // Spin and retry if lock is busy. 1579 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry); 1580 } 1581 else { 1582 bind(L_decrement_retry); 1583 } 1584 } 1585 1586 #endif // INCLUDE_RTM_OPT 1587 1588 // Fast_Lock and Fast_Unlock used by C2 1589 1590 // Because the transitions from emitted code to the runtime 1591 // monitorenter/exit helper stubs are so slow it's critical that 1592 // we inline both the stack-locking fast-path and the inflated fast path. 1593 // 1594 // See also: cmpFastLock and cmpFastUnlock. 1595 // 1596 // What follows is a specialized inline transliteration of the code 1597 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat 1598 // another option would be to emit TrySlowEnter and TrySlowExit methods 1599 // at startup-time. These methods would accept arguments as 1600 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure 1601 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply 1602 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. 1603 // In practice, however, the # of lock sites is bounded and is usually small. 1604 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer 1605 // if the processor uses simple bimodal branch predictors keyed by EIP 1606 // Since the helper routines would be called from multiple synchronization 1607 // sites. 1608 // 1609 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" 1610 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites 1611 // to those specialized methods. That'd give us a mostly platform-independent 1612 // implementation that the JITs could optimize and inline at their pleasure. 1613 // Done correctly, the only time we'd need to cross to native could would be 1614 // to park() or unpark() threads. We'd also need a few more unsafe operators 1615 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and 1616 // (b) explicit barriers or fence operations. 1617 // 1618 // TODO: 1619 // 1620 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). 1621 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. 1622 // Given TLAB allocation, Self is usually manifested in a register, so passing it into 1623 // the lock operators would typically be faster than reifying Self. 1624 // 1625 // * Ideally I'd define the primitives as: 1626 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. 1627 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED 1628 // Unfortunately ADLC bugs prevent us from expressing the ideal form. 1629 // Instead, we're stuck with a rather awkward and brittle register assignments below. 1630 // Furthermore the register assignments are overconstrained, possibly resulting in 1631 // sub-optimal code near the synchronization site. 1632 // 1633 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. 1634 // Alternately, use a better sp-proximity test. 1635 // 1636 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. 1637 // Either one is sufficient to uniquely identify a thread. 1638 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. 1639 // 1640 // * Intrinsify notify() and notifyAll() for the common cases where the 1641 // object is locked by the calling thread but the waitlist is empty. 1642 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). 1643 // 1644 // * use jccb and jmpb instead of jcc and jmp to improve code density. 1645 // But beware of excessive branch density on AMD Opterons. 1646 // 1647 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success 1648 // or failure of the fast-path. If the fast-path fails then we pass 1649 // control to the slow-path, typically in C. In Fast_Lock and 1650 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 1651 // will emit a conditional branch immediately after the node. 1652 // So we have branches to branches and lots of ICC.ZF games. 1653 // Instead, it might be better to have C2 pass a "FailureLabel" 1654 // into Fast_Lock and Fast_Unlock. In the case of success, control 1655 // will drop through the node. ICC.ZF is undefined at exit. 1656 // In the case of failure, the node will branch directly to the 1657 // FailureLabel 1658 1659 1660 // obj: object to lock 1661 // box: on-stack box address (displaced header location) - KILLED 1662 // rax,: tmp -- KILLED 1663 // scr: tmp -- KILLED 1664 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg, 1665 Register scrReg, Register cx1Reg, Register cx2Reg, 1666 BiasedLockingCounters* counters, 1667 RTMLockingCounters* rtm_counters, 1668 RTMLockingCounters* stack_rtm_counters, 1669 Metadata* method_data, 1670 bool use_rtm, bool profile_rtm) { 1671 // Ensure the register assignents are disjoint 1672 assert(tmpReg == rax, ""); 1673 1674 if (use_rtm) { 1675 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg); 1676 } else { 1677 assert(cx1Reg == noreg, ""); 1678 assert(cx2Reg == noreg, ""); 1679 assert_different_registers(objReg, boxReg, tmpReg, scrReg); 1680 } 1681 1682 if (counters != NULL) { 1683 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg); 1684 } 1685 if (EmitSync & 1) { 1686 // set box->dhw = markOopDesc::unused_mark() 1687 // Force all sync thru slow-path: slow_enter() and slow_exit() 1688 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1689 cmpptr (rsp, (int32_t)NULL_WORD); 1690 } else { 1691 // Possible cases that we'll encounter in fast_lock 1692 // ------------------------------------------------ 1693 // * Inflated 1694 // -- unlocked 1695 // -- Locked 1696 // = by self 1697 // = by other 1698 // * biased 1699 // -- by Self 1700 // -- by other 1701 // * neutral 1702 // * stack-locked 1703 // -- by self 1704 // = sp-proximity test hits 1705 // = sp-proximity test generates false-negative 1706 // -- by other 1707 // 1708 1709 Label IsInflated, DONE_LABEL; 1710 1711 // it's stack-locked, biased or neutral 1712 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage 1713 // order to reduce the number of conditional branches in the most common cases. 1714 // Beware -- there's a subtle invariant that fetch of the markword 1715 // at [FETCH], below, will never observe a biased encoding (*101b). 1716 // If this invariant is not held we risk exclusion (safety) failure. 1717 if (UseBiasedLocking && !UseOptoBiasInlining) { 1718 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters); 1719 } 1720 1721 #if INCLUDE_RTM_OPT 1722 if (UseRTMForStackLocks && use_rtm) { 1723 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg, 1724 stack_rtm_counters, method_data, profile_rtm, 1725 DONE_LABEL, IsInflated); 1726 } 1727 #endif // INCLUDE_RTM_OPT 1728 1729 movptr(tmpReg, Address(objReg, 0)); // [FETCH] 1730 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased 1731 jccb(Assembler::notZero, IsInflated); 1732 1733 // Attempt stack-locking ... 1734 orptr (tmpReg, markOopDesc::unlocked_value); 1735 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS 1736 if (os::is_MP()) { 1737 lock(); 1738 } 1739 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg 1740 if (counters != NULL) { 1741 cond_inc32(Assembler::equal, 1742 ExternalAddress((address)counters->fast_path_entry_count_addr())); 1743 } 1744 jcc(Assembler::equal, DONE_LABEL); // Success 1745 1746 // Recursive locking. 1747 // The object is stack-locked: markword contains stack pointer to BasicLock. 1748 // Locked by current thread if difference with current SP is less than one page. 1749 subptr(tmpReg, rsp); 1750 // Next instruction set ZFlag == 1 (Success) if difference is less then one page. 1751 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) ); 1752 movptr(Address(boxReg, 0), tmpReg); 1753 if (counters != NULL) { 1754 cond_inc32(Assembler::equal, 1755 ExternalAddress((address)counters->fast_path_entry_count_addr())); 1756 } 1757 jmp(DONE_LABEL); 1758 1759 bind(IsInflated); 1760 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value 1761 1762 #if INCLUDE_RTM_OPT 1763 // Use the same RTM locking code in 32- and 64-bit VM. 1764 if (use_rtm) { 1765 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg, 1766 rtm_counters, method_data, profile_rtm, DONE_LABEL); 1767 } else { 1768 #endif // INCLUDE_RTM_OPT 1769 1770 #ifndef _LP64 1771 // The object is inflated. 1772 1773 // boxReg refers to the on-stack BasicLock in the current frame. 1774 // We'd like to write: 1775 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices. 1776 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers 1777 // additional latency as we have another ST in the store buffer that must drain. 1778 1779 if (EmitSync & 8192) { 1780 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty 1781 get_thread (scrReg); 1782 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 1783 movptr(tmpReg, NULL_WORD); // consider: xor vs mov 1784 if (os::is_MP()) { 1785 lock(); 1786 } 1787 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1788 } else 1789 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS 1790 // register juggle because we need tmpReg for cmpxchgptr below 1791 movptr(scrReg, boxReg); 1792 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 1793 1794 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 1795 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 1796 // prefetchw [eax + Offset(_owner)-2] 1797 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1798 } 1799 1800 if ((EmitSync & 64) == 0) { 1801 // Optimistic form: consider XORL tmpReg,tmpReg 1802 movptr(tmpReg, NULL_WORD); 1803 } else { 1804 // Can suffer RTS->RTO upgrades on shared or cold $ lines 1805 // Test-And-CAS instead of CAS 1806 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner 1807 testptr(tmpReg, tmpReg); // Locked ? 1808 jccb (Assembler::notZero, DONE_LABEL); 1809 } 1810 1811 // Appears unlocked - try to swing _owner from null to non-null. 1812 // Ideally, I'd manifest "Self" with get_thread and then attempt 1813 // to CAS the register containing Self into m->Owner. 1814 // But we don't have enough registers, so instead we can either try to CAS 1815 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds 1816 // we later store "Self" into m->Owner. Transiently storing a stack address 1817 // (rsp or the address of the box) into m->owner is harmless. 1818 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1819 if (os::is_MP()) { 1820 lock(); 1821 } 1822 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1823 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3 1824 // If we weren't able to swing _owner from NULL to the BasicLock 1825 // then take the slow path. 1826 jccb (Assembler::notZero, DONE_LABEL); 1827 // update _owner from BasicLock to thread 1828 get_thread (scrReg); // beware: clobbers ICCs 1829 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg); 1830 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success 1831 1832 // If the CAS fails we can either retry or pass control to the slow-path. 1833 // We use the latter tactic. 1834 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 1835 // If the CAS was successful ... 1836 // Self has acquired the lock 1837 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 1838 // Intentional fall-through into DONE_LABEL ... 1839 } else { 1840 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty 1841 movptr(boxReg, tmpReg); 1842 1843 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 1844 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 1845 // prefetchw [eax + Offset(_owner)-2] 1846 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1847 } 1848 1849 if ((EmitSync & 64) == 0) { 1850 // Optimistic form 1851 xorptr (tmpReg, tmpReg); 1852 } else { 1853 // Can suffer RTS->RTO upgrades on shared or cold $ lines 1854 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner 1855 testptr(tmpReg, tmpReg); // Locked ? 1856 jccb (Assembler::notZero, DONE_LABEL); 1857 } 1858 1859 // Appears unlocked - try to swing _owner from null to non-null. 1860 // Use either "Self" (in scr) or rsp as thread identity in _owner. 1861 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1862 get_thread (scrReg); 1863 if (os::is_MP()) { 1864 lock(); 1865 } 1866 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1867 1868 // If the CAS fails we can either retry or pass control to the slow-path. 1869 // We use the latter tactic. 1870 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 1871 // If the CAS was successful ... 1872 // Self has acquired the lock 1873 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 1874 // Intentional fall-through into DONE_LABEL ... 1875 } 1876 #else // _LP64 1877 // It's inflated 1878 movq(scrReg, tmpReg); 1879 xorq(tmpReg, tmpReg); 1880 1881 if (os::is_MP()) { 1882 lock(); 1883 } 1884 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1885 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark(). 1886 // Without cast to int32_t movptr will destroy r10 which is typically obj. 1887 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1888 // Intentional fall-through into DONE_LABEL ... 1889 // Propagate ICC.ZF from CAS above into DONE_LABEL. 1890 #endif // _LP64 1891 #if INCLUDE_RTM_OPT 1892 } // use_rtm() 1893 #endif 1894 // DONE_LABEL is a hot target - we'd really like to place it at the 1895 // start of cache line by padding with NOPs. 1896 // See the AMD and Intel software optimization manuals for the 1897 // most efficient "long" NOP encodings. 1898 // Unfortunately none of our alignment mechanisms suffice. 1899 bind(DONE_LABEL); 1900 1901 // At DONE_LABEL the icc ZFlag is set as follows ... 1902 // Fast_Unlock uses the same protocol. 1903 // ZFlag == 1 -> Success 1904 // ZFlag == 0 -> Failure - force control through the slow-path 1905 } 1906 } 1907 1908 // obj: object to unlock 1909 // box: box address (displaced header location), killed. Must be EAX. 1910 // tmp: killed, cannot be obj nor box. 1911 // 1912 // Some commentary on balanced locking: 1913 // 1914 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. 1915 // Methods that don't have provably balanced locking are forced to run in the 1916 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. 1917 // The interpreter provides two properties: 1918 // I1: At return-time the interpreter automatically and quietly unlocks any 1919 // objects acquired the current activation (frame). Recall that the 1920 // interpreter maintains an on-stack list of locks currently held by 1921 // a frame. 1922 // I2: If a method attempts to unlock an object that is not held by the 1923 // the frame the interpreter throws IMSX. 1924 // 1925 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). 1926 // B() doesn't have provably balanced locking so it runs in the interpreter. 1927 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O 1928 // is still locked by A(). 1929 // 1930 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: 1931 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter 1932 // should not be unlocked by "normal" java-level locking and vice-versa. The specification 1933 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. 1934 // Arguably given that the spec legislates the JNI case as undefined our implementation 1935 // could reasonably *avoid* checking owner in Fast_Unlock(). 1936 // In the interest of performance we elide m->Owner==Self check in unlock. 1937 // A perfectly viable alternative is to elide the owner check except when 1938 // Xcheck:jni is enabled. 1939 1940 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) { 1941 assert(boxReg == rax, ""); 1942 assert_different_registers(objReg, boxReg, tmpReg); 1943 1944 if (EmitSync & 4) { 1945 // Disable - inhibit all inlining. Force control through the slow-path 1946 cmpptr (rsp, 0); 1947 } else { 1948 Label DONE_LABEL, Stacked, CheckSucc; 1949 1950 // Critically, the biased locking test must have precedence over 1951 // and appear before the (box->dhw == 0) recursive stack-lock test. 1952 if (UseBiasedLocking && !UseOptoBiasInlining) { 1953 biased_locking_exit(objReg, tmpReg, DONE_LABEL); 1954 } 1955 1956 #if INCLUDE_RTM_OPT 1957 if (UseRTMForStackLocks && use_rtm) { 1958 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); 1959 Label L_regular_unlock; 1960 movptr(tmpReg, Address(objReg, 0)); // fetch markword 1961 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits 1962 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked 1963 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock 1964 xend(); // otherwise end... 1965 jmp(DONE_LABEL); // ... and we're done 1966 bind(L_regular_unlock); 1967 } 1968 #endif 1969 1970 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header 1971 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock 1972 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword 1973 testptr(tmpReg, markOopDesc::monitor_value); // Inflated? 1974 jccb (Assembler::zero, Stacked); 1975 1976 // It's inflated. 1977 #if INCLUDE_RTM_OPT 1978 if (use_rtm) { 1979 Label L_regular_inflated_unlock; 1980 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1981 movptr(boxReg, Address(tmpReg, owner_offset)); 1982 testptr(boxReg, boxReg); 1983 jccb(Assembler::notZero, L_regular_inflated_unlock); 1984 xend(); 1985 jmpb(DONE_LABEL); 1986 bind(L_regular_inflated_unlock); 1987 } 1988 #endif 1989 1990 // Despite our balanced locking property we still check that m->_owner == Self 1991 // as java routines or native JNI code called by this thread might 1992 // have released the lock. 1993 // Refer to the comments in synchronizer.cpp for how we might encode extra 1994 // state in _succ so we can avoid fetching EntryList|cxq. 1995 // 1996 // I'd like to add more cases in fast_lock() and fast_unlock() -- 1997 // such as recursive enter and exit -- but we have to be wary of 1998 // I$ bloat, T$ effects and BP$ effects. 1999 // 2000 // If there's no contention try a 1-0 exit. That is, exit without 2001 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how 2002 // we detect and recover from the race that the 1-0 exit admits. 2003 // 2004 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier 2005 // before it STs null into _owner, releasing the lock. Updates 2006 // to data protected by the critical section must be visible before 2007 // we drop the lock (and thus before any other thread could acquire 2008 // the lock and observe the fields protected by the lock). 2009 // IA32's memory-model is SPO, so STs are ordered with respect to 2010 // each other and there's no need for an explicit barrier (fence). 2011 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. 2012 #ifndef _LP64 2013 get_thread (boxReg); 2014 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 2015 // prefetchw [ebx + Offset(_owner)-2] 2016 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2017 } 2018 2019 // Note that we could employ various encoding schemes to reduce 2020 // the number of loads below (currently 4) to just 2 or 3. 2021 // Refer to the comments in synchronizer.cpp. 2022 // In practice the chain of fetches doesn't seem to impact performance, however. 2023 xorptr(boxReg, boxReg); 2024 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { 2025 // Attempt to reduce branch density - AMD's branch predictor. 2026 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2027 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2028 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2029 jccb (Assembler::notZero, DONE_LABEL); 2030 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2031 jmpb (DONE_LABEL); 2032 } else { 2033 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2034 jccb (Assembler::notZero, DONE_LABEL); 2035 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2036 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2037 jccb (Assembler::notZero, CheckSucc); 2038 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2039 jmpb (DONE_LABEL); 2040 } 2041 2042 // The Following code fragment (EmitSync & 65536) improves the performance of 2043 // contended applications and contended synchronization microbenchmarks. 2044 // Unfortunately the emission of the code - even though not executed - causes regressions 2045 // in scimark and jetstream, evidently because of $ effects. Replacing the code 2046 // with an equal number of never-executed NOPs results in the same regression. 2047 // We leave it off by default. 2048 2049 if ((EmitSync & 65536) != 0) { 2050 Label LSuccess, LGoSlowPath ; 2051 2052 bind (CheckSucc); 2053 2054 // Optional pre-test ... it's safe to elide this 2055 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2056 jccb(Assembler::zero, LGoSlowPath); 2057 2058 // We have a classic Dekker-style idiom: 2059 // ST m->_owner = 0 ; MEMBAR; LD m->_succ 2060 // There are a number of ways to implement the barrier: 2061 // (1) lock:andl &m->_owner, 0 2062 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. 2063 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 2064 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 2065 // (2) If supported, an explicit MFENCE is appealing. 2066 // In older IA32 processors MFENCE is slower than lock:add or xchg 2067 // particularly if the write-buffer is full as might be the case if 2068 // if stores closely precede the fence or fence-equivalent instruction. 2069 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences 2070 // as the situation has changed with Nehalem and Shanghai. 2071 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack 2072 // The $lines underlying the top-of-stack should be in M-state. 2073 // The locked add instruction is serializing, of course. 2074 // (4) Use xchg, which is serializing 2075 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works 2076 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. 2077 // The integer condition codes will tell us if succ was 0. 2078 // Since _succ and _owner should reside in the same $line and 2079 // we just stored into _owner, it's likely that the $line 2080 // remains in M-state for the lock:orl. 2081 // 2082 // We currently use (3), although it's likely that switching to (2) 2083 // is correct for the future. 2084 2085 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2086 if (os::is_MP()) { 2087 lock(); addptr(Address(rsp, 0), 0); 2088 } 2089 // Ratify _succ remains non-null 2090 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0); 2091 jccb (Assembler::notZero, LSuccess); 2092 2093 xorptr(boxReg, boxReg); // box is really EAX 2094 if (os::is_MP()) { lock(); } 2095 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2096 // There's no successor so we tried to regrab the lock with the 2097 // placeholder value. If that didn't work, then another thread 2098 // grabbed the lock so we're done (and exit was a success). 2099 jccb (Assembler::notEqual, LSuccess); 2100 // Since we're low on registers we installed rsp as a placeholding in _owner. 2101 // Now install Self over rsp. This is safe as we're transitioning from 2102 // non-null to non=null 2103 get_thread (boxReg); 2104 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg); 2105 // Intentional fall-through into LGoSlowPath ... 2106 2107 bind (LGoSlowPath); 2108 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure 2109 jmpb (DONE_LABEL); 2110 2111 bind (LSuccess); 2112 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success 2113 jmpb (DONE_LABEL); 2114 } 2115 2116 bind (Stacked); 2117 // It's not inflated and it's not recursively stack-locked and it's not biased. 2118 // It must be stack-locked. 2119 // Try to reset the header to displaced header. 2120 // The "box" value on the stack is stable, so we can reload 2121 // and be assured we observe the same value as above. 2122 movptr(tmpReg, Address(boxReg, 0)); 2123 if (os::is_MP()) { 2124 lock(); 2125 } 2126 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box 2127 // Intention fall-thru into DONE_LABEL 2128 2129 // DONE_LABEL is a hot target - we'd really like to place it at the 2130 // start of cache line by padding with NOPs. 2131 // See the AMD and Intel software optimization manuals for the 2132 // most efficient "long" NOP encodings. 2133 // Unfortunately none of our alignment mechanisms suffice. 2134 if ((EmitSync & 65536) == 0) { 2135 bind (CheckSucc); 2136 } 2137 #else // _LP64 2138 // It's inflated 2139 if (EmitSync & 1024) { 2140 // Emit code to check that _owner == Self 2141 // We could fold the _owner test into subsequent code more efficiently 2142 // than using a stand-alone check, but since _owner checking is off by 2143 // default we don't bother. We also might consider predicating the 2144 // _owner==Self check on Xcheck:jni or running on a debug build. 2145 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2146 xorptr(boxReg, r15_thread); 2147 } else { 2148 xorptr(boxReg, boxReg); 2149 } 2150 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2151 jccb (Assembler::notZero, DONE_LABEL); 2152 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2153 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2154 jccb (Assembler::notZero, CheckSucc); 2155 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD); 2156 jmpb (DONE_LABEL); 2157 2158 if ((EmitSync & 65536) == 0) { 2159 // Try to avoid passing control into the slow_path ... 2160 Label LSuccess, LGoSlowPath ; 2161 bind (CheckSucc); 2162 2163 // The following optional optimization can be elided if necessary 2164 // Effectively: if (succ == null) goto SlowPath 2165 // The code reduces the window for a race, however, 2166 // and thus benefits performance. 2167 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2168 jccb (Assembler::zero, LGoSlowPath); 2169 2170 if ((EmitSync & 16) && os::is_MP()) { 2171 orptr(boxReg, boxReg); 2172 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2173 } else { 2174 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD); 2175 if (os::is_MP()) { 2176 // Memory barrier/fence 2177 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ 2178 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack. 2179 // This is faster on Nehalem and AMD Shanghai/Barcelona. 2180 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences 2181 // We might also restructure (ST Owner=0;barrier;LD _Succ) to 2182 // (mov box,0; xchgq box, &m->Owner; LD _succ) . 2183 lock(); addl(Address(rsp, 0), 0); 2184 } 2185 } 2186 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2187 jccb (Assembler::notZero, LSuccess); 2188 2189 // Rare inopportune interleaving - race. 2190 // The successor vanished in the small window above. 2191 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor. 2192 // We need to ensure progress and succession. 2193 // Try to reacquire the lock. 2194 // If that fails then the new owner is responsible for succession and this 2195 // thread needs to take no further action and can exit via the fast path (success). 2196 // If the re-acquire succeeds then pass control into the slow path. 2197 // As implemented, this latter mode is horrible because we generated more 2198 // coherence traffic on the lock *and* artifically extended the critical section 2199 // length while by virtue of passing control into the slow path. 2200 2201 // box is really RAX -- the following CMPXCHG depends on that binding 2202 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R) 2203 movptr(boxReg, (int32_t)NULL_WORD); 2204 if (os::is_MP()) { lock(); } 2205 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2206 // There's no successor so we tried to regrab the lock. 2207 // If that didn't work, then another thread grabbed the 2208 // lock so we're done (and exit was a success). 2209 jccb (Assembler::notEqual, LSuccess); 2210 // Intentional fall-through into slow-path 2211 2212 bind (LGoSlowPath); 2213 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure 2214 jmpb (DONE_LABEL); 2215 2216 bind (LSuccess); 2217 testl (boxReg, 0); // set ICC.ZF=1 to indicate success 2218 jmpb (DONE_LABEL); 2219 } 2220 2221 bind (Stacked); 2222 movptr(tmpReg, Address (boxReg, 0)); // re-fetch 2223 if (os::is_MP()) { lock(); } 2224 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box 2225 2226 if (EmitSync & 65536) { 2227 bind (CheckSucc); 2228 } 2229 #endif 2230 bind(DONE_LABEL); 2231 } 2232 } 2233 #endif // COMPILER2 2234 2235 void MacroAssembler::c2bool(Register x) { 2236 // implements x == 0 ? 0 : 1 2237 // note: must only look at least-significant byte of x 2238 // since C-style booleans are stored in one byte 2239 // only! (was bug) 2240 andl(x, 0xFF); 2241 setb(Assembler::notZero, x); 2242 } 2243 2244 // Wouldn't need if AddressLiteral version had new name 2245 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { 2246 Assembler::call(L, rtype); 2247 } 2248 2249 void MacroAssembler::call(Register entry) { 2250 Assembler::call(entry); 2251 } 2252 2253 void MacroAssembler::call(AddressLiteral entry) { 2254 if (reachable(entry)) { 2255 Assembler::call_literal(entry.target(), entry.rspec()); 2256 } else { 2257 lea(rscratch1, entry); 2258 Assembler::call(rscratch1); 2259 } 2260 } 2261 2262 void MacroAssembler::ic_call(address entry) { 2263 RelocationHolder rh = virtual_call_Relocation::spec(pc()); 2264 movptr(rax, (intptr_t)Universe::non_oop_word()); 2265 call(AddressLiteral(entry, rh)); 2266 } 2267 2268 // Implementation of call_VM versions 2269 2270 void MacroAssembler::call_VM(Register oop_result, 2271 address entry_point, 2272 bool check_exceptions) { 2273 Label C, E; 2274 call(C, relocInfo::none); 2275 jmp(E); 2276 2277 bind(C); 2278 call_VM_helper(oop_result, entry_point, 0, check_exceptions); 2279 ret(0); 2280 2281 bind(E); 2282 } 2283 2284 void MacroAssembler::call_VM(Register oop_result, 2285 address entry_point, 2286 Register arg_1, 2287 bool check_exceptions) { 2288 Label C, E; 2289 call(C, relocInfo::none); 2290 jmp(E); 2291 2292 bind(C); 2293 pass_arg1(this, arg_1); 2294 call_VM_helper(oop_result, entry_point, 1, check_exceptions); 2295 ret(0); 2296 2297 bind(E); 2298 } 2299 2300 void MacroAssembler::call_VM(Register oop_result, 2301 address entry_point, 2302 Register arg_1, 2303 Register arg_2, 2304 bool check_exceptions) { 2305 Label C, E; 2306 call(C, relocInfo::none); 2307 jmp(E); 2308 2309 bind(C); 2310 2311 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2312 2313 pass_arg2(this, arg_2); 2314 pass_arg1(this, arg_1); 2315 call_VM_helper(oop_result, entry_point, 2, check_exceptions); 2316 ret(0); 2317 2318 bind(E); 2319 } 2320 2321 void MacroAssembler::call_VM(Register oop_result, 2322 address entry_point, 2323 Register arg_1, 2324 Register arg_2, 2325 Register arg_3, 2326 bool check_exceptions) { 2327 Label C, E; 2328 call(C, relocInfo::none); 2329 jmp(E); 2330 2331 bind(C); 2332 2333 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2334 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2335 pass_arg3(this, arg_3); 2336 2337 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2338 pass_arg2(this, arg_2); 2339 2340 pass_arg1(this, arg_1); 2341 call_VM_helper(oop_result, entry_point, 3, check_exceptions); 2342 ret(0); 2343 2344 bind(E); 2345 } 2346 2347 void MacroAssembler::call_VM(Register oop_result, 2348 Register last_java_sp, 2349 address entry_point, 2350 int number_of_arguments, 2351 bool check_exceptions) { 2352 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 2353 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 2354 } 2355 2356 void MacroAssembler::call_VM(Register oop_result, 2357 Register last_java_sp, 2358 address entry_point, 2359 Register arg_1, 2360 bool check_exceptions) { 2361 pass_arg1(this, arg_1); 2362 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 2363 } 2364 2365 void MacroAssembler::call_VM(Register oop_result, 2366 Register last_java_sp, 2367 address entry_point, 2368 Register arg_1, 2369 Register arg_2, 2370 bool check_exceptions) { 2371 2372 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2373 pass_arg2(this, arg_2); 2374 pass_arg1(this, arg_1); 2375 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 2376 } 2377 2378 void MacroAssembler::call_VM(Register oop_result, 2379 Register last_java_sp, 2380 address entry_point, 2381 Register arg_1, 2382 Register arg_2, 2383 Register arg_3, 2384 bool check_exceptions) { 2385 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2386 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2387 pass_arg3(this, arg_3); 2388 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2389 pass_arg2(this, arg_2); 2390 pass_arg1(this, arg_1); 2391 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 2392 } 2393 2394 void MacroAssembler::super_call_VM(Register oop_result, 2395 Register last_java_sp, 2396 address entry_point, 2397 int number_of_arguments, 2398 bool check_exceptions) { 2399 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 2400 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 2401 } 2402 2403 void MacroAssembler::super_call_VM(Register oop_result, 2404 Register last_java_sp, 2405 address entry_point, 2406 Register arg_1, 2407 bool check_exceptions) { 2408 pass_arg1(this, arg_1); 2409 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 2410 } 2411 2412 void MacroAssembler::super_call_VM(Register oop_result, 2413 Register last_java_sp, 2414 address entry_point, 2415 Register arg_1, 2416 Register arg_2, 2417 bool check_exceptions) { 2418 2419 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2420 pass_arg2(this, arg_2); 2421 pass_arg1(this, arg_1); 2422 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 2423 } 2424 2425 void MacroAssembler::super_call_VM(Register oop_result, 2426 Register last_java_sp, 2427 address entry_point, 2428 Register arg_1, 2429 Register arg_2, 2430 Register arg_3, 2431 bool check_exceptions) { 2432 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2433 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2434 pass_arg3(this, arg_3); 2435 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2436 pass_arg2(this, arg_2); 2437 pass_arg1(this, arg_1); 2438 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 2439 } 2440 2441 void MacroAssembler::call_VM_base(Register oop_result, 2442 Register java_thread, 2443 Register last_java_sp, 2444 address entry_point, 2445 int number_of_arguments, 2446 bool check_exceptions) { 2447 // determine java_thread register 2448 if (!java_thread->is_valid()) { 2449 #ifdef _LP64 2450 java_thread = r15_thread; 2451 #else 2452 java_thread = rdi; 2453 get_thread(java_thread); 2454 #endif // LP64 2455 } 2456 // determine last_java_sp register 2457 if (!last_java_sp->is_valid()) { 2458 last_java_sp = rsp; 2459 } 2460 // debugging support 2461 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 2462 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); 2463 #ifdef ASSERT 2464 // TraceBytecodes does not use r12 but saves it over the call, so don't verify 2465 // r12 is the heapbase. 2466 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");) 2467 #endif // ASSERT 2468 2469 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); 2470 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); 2471 2472 // push java thread (becomes first argument of C function) 2473 2474 NOT_LP64(push(java_thread); number_of_arguments++); 2475 LP64_ONLY(mov(c_rarg0, r15_thread)); 2476 2477 // set last Java frame before call 2478 assert(last_java_sp != rbp, "can't use ebp/rbp"); 2479 2480 // Only interpreter should have to set fp 2481 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); 2482 2483 // do the call, remove parameters 2484 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); 2485 2486 // restore the thread (cannot use the pushed argument since arguments 2487 // may be overwritten by C code generated by an optimizing compiler); 2488 // however can use the register value directly if it is callee saved. 2489 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { 2490 // rdi & rsi (also r15) are callee saved -> nothing to do 2491 #ifdef ASSERT 2492 guarantee(java_thread != rax, "change this code"); 2493 push(rax); 2494 { Label L; 2495 get_thread(rax); 2496 cmpptr(java_thread, rax); 2497 jcc(Assembler::equal, L); 2498 STOP("MacroAssembler::call_VM_base: rdi not callee saved?"); 2499 bind(L); 2500 } 2501 pop(rax); 2502 #endif 2503 } else { 2504 get_thread(java_thread); 2505 } 2506 // reset last Java frame 2507 // Only interpreter should have to clear fp 2508 reset_last_Java_frame(java_thread, true, false); 2509 2510 #ifndef CC_INTERP 2511 // C++ interp handles this in the interpreter 2512 check_and_handle_popframe(java_thread); 2513 check_and_handle_earlyret(java_thread); 2514 #endif /* CC_INTERP */ 2515 2516 if (check_exceptions) { 2517 // check for pending exceptions (java_thread is set upon return) 2518 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); 2519 #ifndef _LP64 2520 jump_cc(Assembler::notEqual, 2521 RuntimeAddress(StubRoutines::forward_exception_entry())); 2522 #else 2523 // This used to conditionally jump to forward_exception however it is 2524 // possible if we relocate that the branch will not reach. So we must jump 2525 // around so we can always reach 2526 2527 Label ok; 2528 jcc(Assembler::equal, ok); 2529 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 2530 bind(ok); 2531 #endif // LP64 2532 } 2533 2534 // get oop result if there is one and reset the value in the thread 2535 if (oop_result->is_valid()) { 2536 get_vm_result(oop_result, java_thread); 2537 } 2538 } 2539 2540 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 2541 2542 // Calculate the value for last_Java_sp 2543 // somewhat subtle. call_VM does an intermediate call 2544 // which places a return address on the stack just under the 2545 // stack pointer as the user finsihed with it. This allows 2546 // use to retrieve last_Java_pc from last_Java_sp[-1]. 2547 // On 32bit we then have to push additional args on the stack to accomplish 2548 // the actual requested call. On 64bit call_VM only can use register args 2549 // so the only extra space is the return address that call_VM created. 2550 // This hopefully explains the calculations here. 2551 2552 #ifdef _LP64 2553 // We've pushed one address, correct last_Java_sp 2554 lea(rax, Address(rsp, wordSize)); 2555 #else 2556 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); 2557 #endif // LP64 2558 2559 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); 2560 2561 } 2562 2563 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { 2564 call_VM_leaf_base(entry_point, number_of_arguments); 2565 } 2566 2567 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { 2568 pass_arg0(this, arg_0); 2569 call_VM_leaf(entry_point, 1); 2570 } 2571 2572 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2573 2574 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2575 pass_arg1(this, arg_1); 2576 pass_arg0(this, arg_0); 2577 call_VM_leaf(entry_point, 2); 2578 } 2579 2580 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 2581 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2582 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2583 pass_arg2(this, arg_2); 2584 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2585 pass_arg1(this, arg_1); 2586 pass_arg0(this, arg_0); 2587 call_VM_leaf(entry_point, 3); 2588 } 2589 2590 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { 2591 pass_arg0(this, arg_0); 2592 MacroAssembler::call_VM_leaf_base(entry_point, 1); 2593 } 2594 2595 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2596 2597 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2598 pass_arg1(this, arg_1); 2599 pass_arg0(this, arg_0); 2600 MacroAssembler::call_VM_leaf_base(entry_point, 2); 2601 } 2602 2603 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 2604 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2605 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2606 pass_arg2(this, arg_2); 2607 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2608 pass_arg1(this, arg_1); 2609 pass_arg0(this, arg_0); 2610 MacroAssembler::call_VM_leaf_base(entry_point, 3); 2611 } 2612 2613 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { 2614 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg")); 2615 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2616 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2617 pass_arg3(this, arg_3); 2618 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2619 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2620 pass_arg2(this, arg_2); 2621 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2622 pass_arg1(this, arg_1); 2623 pass_arg0(this, arg_0); 2624 MacroAssembler::call_VM_leaf_base(entry_point, 4); 2625 } 2626 2627 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { 2628 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); 2629 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); 2630 verify_oop(oop_result, "broken oop in call_VM_base"); 2631 } 2632 2633 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { 2634 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); 2635 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD); 2636 } 2637 2638 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { 2639 } 2640 2641 void MacroAssembler::check_and_handle_popframe(Register java_thread) { 2642 } 2643 2644 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { 2645 if (reachable(src1)) { 2646 cmpl(as_Address(src1), imm); 2647 } else { 2648 lea(rscratch1, src1); 2649 cmpl(Address(rscratch1, 0), imm); 2650 } 2651 } 2652 2653 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { 2654 assert(!src2.is_lval(), "use cmpptr"); 2655 if (reachable(src2)) { 2656 cmpl(src1, as_Address(src2)); 2657 } else { 2658 lea(rscratch1, src2); 2659 cmpl(src1, Address(rscratch1, 0)); 2660 } 2661 } 2662 2663 void MacroAssembler::cmp32(Register src1, int32_t imm) { 2664 Assembler::cmpl(src1, imm); 2665 } 2666 2667 void MacroAssembler::cmp32(Register src1, Address src2) { 2668 Assembler::cmpl(src1, src2); 2669 } 2670 2671 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 2672 ucomisd(opr1, opr2); 2673 2674 Label L; 2675 if (unordered_is_less) { 2676 movl(dst, -1); 2677 jcc(Assembler::parity, L); 2678 jcc(Assembler::below , L); 2679 movl(dst, 0); 2680 jcc(Assembler::equal , L); 2681 increment(dst); 2682 } else { // unordered is greater 2683 movl(dst, 1); 2684 jcc(Assembler::parity, L); 2685 jcc(Assembler::above , L); 2686 movl(dst, 0); 2687 jcc(Assembler::equal , L); 2688 decrementl(dst); 2689 } 2690 bind(L); 2691 } 2692 2693 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 2694 ucomiss(opr1, opr2); 2695 2696 Label L; 2697 if (unordered_is_less) { 2698 movl(dst, -1); 2699 jcc(Assembler::parity, L); 2700 jcc(Assembler::below , L); 2701 movl(dst, 0); 2702 jcc(Assembler::equal , L); 2703 increment(dst); 2704 } else { // unordered is greater 2705 movl(dst, 1); 2706 jcc(Assembler::parity, L); 2707 jcc(Assembler::above , L); 2708 movl(dst, 0); 2709 jcc(Assembler::equal , L); 2710 decrementl(dst); 2711 } 2712 bind(L); 2713 } 2714 2715 2716 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { 2717 if (reachable(src1)) { 2718 cmpb(as_Address(src1), imm); 2719 } else { 2720 lea(rscratch1, src1); 2721 cmpb(Address(rscratch1, 0), imm); 2722 } 2723 } 2724 2725 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { 2726 #ifdef _LP64 2727 if (src2.is_lval()) { 2728 movptr(rscratch1, src2); 2729 Assembler::cmpq(src1, rscratch1); 2730 } else if (reachable(src2)) { 2731 cmpq(src1, as_Address(src2)); 2732 } else { 2733 lea(rscratch1, src2); 2734 Assembler::cmpq(src1, Address(rscratch1, 0)); 2735 } 2736 #else 2737 if (src2.is_lval()) { 2738 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 2739 } else { 2740 cmpl(src1, as_Address(src2)); 2741 } 2742 #endif // _LP64 2743 } 2744 2745 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { 2746 assert(src2.is_lval(), "not a mem-mem compare"); 2747 #ifdef _LP64 2748 // moves src2's literal address 2749 movptr(rscratch1, src2); 2750 Assembler::cmpq(src1, rscratch1); 2751 #else 2752 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 2753 #endif // _LP64 2754 } 2755 2756 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { 2757 if (reachable(adr)) { 2758 if (os::is_MP()) 2759 lock(); 2760 cmpxchgptr(reg, as_Address(adr)); 2761 } else { 2762 lea(rscratch1, adr); 2763 if (os::is_MP()) 2764 lock(); 2765 cmpxchgptr(reg, Address(rscratch1, 0)); 2766 } 2767 } 2768 2769 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { 2770 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); 2771 } 2772 2773 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { 2774 if (reachable(src)) { 2775 Assembler::comisd(dst, as_Address(src)); 2776 } else { 2777 lea(rscratch1, src); 2778 Assembler::comisd(dst, Address(rscratch1, 0)); 2779 } 2780 } 2781 2782 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { 2783 if (reachable(src)) { 2784 Assembler::comiss(dst, as_Address(src)); 2785 } else { 2786 lea(rscratch1, src); 2787 Assembler::comiss(dst, Address(rscratch1, 0)); 2788 } 2789 } 2790 2791 2792 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { 2793 Condition negated_cond = negate_condition(cond); 2794 Label L; 2795 jcc(negated_cond, L); 2796 pushf(); // Preserve flags 2797 atomic_incl(counter_addr); 2798 popf(); 2799 bind(L); 2800 } 2801 2802 int MacroAssembler::corrected_idivl(Register reg) { 2803 // Full implementation of Java idiv and irem; checks for 2804 // special case as described in JVM spec., p.243 & p.271. 2805 // The function returns the (pc) offset of the idivl 2806 // instruction - may be needed for implicit exceptions. 2807 // 2808 // normal case special case 2809 // 2810 // input : rax,: dividend min_int 2811 // reg: divisor (may not be rax,/rdx) -1 2812 // 2813 // output: rax,: quotient (= rax, idiv reg) min_int 2814 // rdx: remainder (= rax, irem reg) 0 2815 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); 2816 const int min_int = 0x80000000; 2817 Label normal_case, special_case; 2818 2819 // check for special case 2820 cmpl(rax, min_int); 2821 jcc(Assembler::notEqual, normal_case); 2822 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) 2823 cmpl(reg, -1); 2824 jcc(Assembler::equal, special_case); 2825 2826 // handle normal case 2827 bind(normal_case); 2828 cdql(); 2829 int idivl_offset = offset(); 2830 idivl(reg); 2831 2832 // normal and special case exit 2833 bind(special_case); 2834 2835 return idivl_offset; 2836 } 2837 2838 2839 2840 void MacroAssembler::decrementl(Register reg, int value) { 2841 if (value == min_jint) {subl(reg, value) ; return; } 2842 if (value < 0) { incrementl(reg, -value); return; } 2843 if (value == 0) { ; return; } 2844 if (value == 1 && UseIncDec) { decl(reg) ; return; } 2845 /* else */ { subl(reg, value) ; return; } 2846 } 2847 2848 void MacroAssembler::decrementl(Address dst, int value) { 2849 if (value == min_jint) {subl(dst, value) ; return; } 2850 if (value < 0) { incrementl(dst, -value); return; } 2851 if (value == 0) { ; return; } 2852 if (value == 1 && UseIncDec) { decl(dst) ; return; } 2853 /* else */ { subl(dst, value) ; return; } 2854 } 2855 2856 void MacroAssembler::division_with_shift (Register reg, int shift_value) { 2857 assert (shift_value > 0, "illegal shift value"); 2858 Label _is_positive; 2859 testl (reg, reg); 2860 jcc (Assembler::positive, _is_positive); 2861 int offset = (1 << shift_value) - 1 ; 2862 2863 if (offset == 1) { 2864 incrementl(reg); 2865 } else { 2866 addl(reg, offset); 2867 } 2868 2869 bind (_is_positive); 2870 sarl(reg, shift_value); 2871 } 2872 2873 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) { 2874 if (reachable(src)) { 2875 Assembler::divsd(dst, as_Address(src)); 2876 } else { 2877 lea(rscratch1, src); 2878 Assembler::divsd(dst, Address(rscratch1, 0)); 2879 } 2880 } 2881 2882 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) { 2883 if (reachable(src)) { 2884 Assembler::divss(dst, as_Address(src)); 2885 } else { 2886 lea(rscratch1, src); 2887 Assembler::divss(dst, Address(rscratch1, 0)); 2888 } 2889 } 2890 2891 // !defined(COMPILER2) is because of stupid core builds 2892 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) 2893 void MacroAssembler::empty_FPU_stack() { 2894 if (VM_Version::supports_mmx()) { 2895 emms(); 2896 } else { 2897 for (int i = 8; i-- > 0; ) ffree(i); 2898 } 2899 } 2900 #endif // !LP64 || C1 || !C2 2901 2902 2903 // Defines obj, preserves var_size_in_bytes 2904 void MacroAssembler::eden_allocate(Register obj, 2905 Register var_size_in_bytes, 2906 int con_size_in_bytes, 2907 Register t1, 2908 Label& slow_case) { 2909 assert(obj == rax, "obj must be in rax, for cmpxchg"); 2910 assert_different_registers(obj, var_size_in_bytes, t1); 2911 if (!Universe::heap()->supports_inline_contig_alloc()) { 2912 jmp(slow_case); 2913 } else { 2914 Register end = t1; 2915 Label retry; 2916 bind(retry); 2917 ExternalAddress heap_top((address) Universe::heap()->top_addr()); 2918 movptr(obj, heap_top); 2919 if (var_size_in_bytes == noreg) { 2920 lea(end, Address(obj, con_size_in_bytes)); 2921 } else { 2922 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); 2923 } 2924 // if end < obj then we wrapped around => object too long => slow case 2925 cmpptr(end, obj); 2926 jcc(Assembler::below, slow_case); 2927 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); 2928 jcc(Assembler::above, slow_case); 2929 // Compare obj with the top addr, and if still equal, store the new top addr in 2930 // end at the address of the top addr pointer. Sets ZF if was equal, and clears 2931 // it otherwise. Use lock prefix for atomicity on MPs. 2932 locked_cmpxchgptr(end, heap_top); 2933 jcc(Assembler::notEqual, retry); 2934 } 2935 } 2936 2937 void MacroAssembler::enter() { 2938 push(rbp); 2939 mov(rbp, rsp); 2940 } 2941 2942 // A 5 byte nop that is safe for patching (see patch_verified_entry) 2943 void MacroAssembler::fat_nop() { 2944 if (UseAddressNop) { 2945 addr_nop_5(); 2946 } else { 2947 emit_int8(0x26); // es: 2948 emit_int8(0x2e); // cs: 2949 emit_int8(0x64); // fs: 2950 emit_int8(0x65); // gs: 2951 emit_int8((unsigned char)0x90); 2952 } 2953 } 2954 2955 void MacroAssembler::fcmp(Register tmp) { 2956 fcmp(tmp, 1, true, true); 2957 } 2958 2959 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { 2960 assert(!pop_right || pop_left, "usage error"); 2961 if (VM_Version::supports_cmov()) { 2962 assert(tmp == noreg, "unneeded temp"); 2963 if (pop_left) { 2964 fucomip(index); 2965 } else { 2966 fucomi(index); 2967 } 2968 if (pop_right) { 2969 fpop(); 2970 } 2971 } else { 2972 assert(tmp != noreg, "need temp"); 2973 if (pop_left) { 2974 if (pop_right) { 2975 fcompp(); 2976 } else { 2977 fcomp(index); 2978 } 2979 } else { 2980 fcom(index); 2981 } 2982 // convert FPU condition into eflags condition via rax, 2983 save_rax(tmp); 2984 fwait(); fnstsw_ax(); 2985 sahf(); 2986 restore_rax(tmp); 2987 } 2988 // condition codes set as follows: 2989 // 2990 // CF (corresponds to C0) if x < y 2991 // PF (corresponds to C2) if unordered 2992 // ZF (corresponds to C3) if x = y 2993 } 2994 2995 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { 2996 fcmp2int(dst, unordered_is_less, 1, true, true); 2997 } 2998 2999 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { 3000 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); 3001 Label L; 3002 if (unordered_is_less) { 3003 movl(dst, -1); 3004 jcc(Assembler::parity, L); 3005 jcc(Assembler::below , L); 3006 movl(dst, 0); 3007 jcc(Assembler::equal , L); 3008 increment(dst); 3009 } else { // unordered is greater 3010 movl(dst, 1); 3011 jcc(Assembler::parity, L); 3012 jcc(Assembler::above , L); 3013 movl(dst, 0); 3014 jcc(Assembler::equal , L); 3015 decrementl(dst); 3016 } 3017 bind(L); 3018 } 3019 3020 void MacroAssembler::fld_d(AddressLiteral src) { 3021 fld_d(as_Address(src)); 3022 } 3023 3024 void MacroAssembler::fld_s(AddressLiteral src) { 3025 fld_s(as_Address(src)); 3026 } 3027 3028 void MacroAssembler::fld_x(AddressLiteral src) { 3029 Assembler::fld_x(as_Address(src)); 3030 } 3031 3032 void MacroAssembler::fldcw(AddressLiteral src) { 3033 Assembler::fldcw(as_Address(src)); 3034 } 3035 3036 void MacroAssembler::pow_exp_core_encoding() { 3037 // kills rax, rcx, rdx 3038 subptr(rsp,sizeof(jdouble)); 3039 // computes 2^X. Stack: X ... 3040 // f2xm1 computes 2^X-1 but only operates on -1<=X<=1. Get int(X) and 3041 // keep it on the thread's stack to compute 2^int(X) later 3042 // then compute 2^(X-int(X)) as (2^(X-int(X)-1+1) 3043 // final result is obtained with: 2^X = 2^int(X) * 2^(X-int(X)) 3044 fld_s(0); // Stack: X X ... 3045 frndint(); // Stack: int(X) X ... 3046 fsuba(1); // Stack: int(X) X-int(X) ... 3047 fistp_s(Address(rsp,0)); // move int(X) as integer to thread's stack. Stack: X-int(X) ... 3048 f2xm1(); // Stack: 2^(X-int(X))-1 ... 3049 fld1(); // Stack: 1 2^(X-int(X))-1 ... 3050 faddp(1); // Stack: 2^(X-int(X)) 3051 // computes 2^(int(X)): add exponent bias (1023) to int(X), then 3052 // shift int(X)+1023 to exponent position. 3053 // Exponent is limited to 11 bits if int(X)+1023 does not fit in 11 3054 // bits, set result to NaN. 0x000 and 0x7FF are reserved exponent 3055 // values so detect them and set result to NaN. 3056 movl(rax,Address(rsp,0)); 3057 movl(rcx, -2048); // 11 bit mask and valid NaN binary encoding 3058 addl(rax, 1023); 3059 movl(rdx,rax); 3060 shll(rax,20); 3061 // Check that 0 < int(X)+1023 < 2047. Otherwise set rax to NaN. 3062 addl(rdx,1); 3063 // Check that 1 < int(X)+1023+1 < 2048 3064 // in 3 steps: 3065 // 1- (int(X)+1023+1)&-2048 == 0 => 0 <= int(X)+1023+1 < 2048 3066 // 2- (int(X)+1023+1)&-2048 != 0 3067 // 3- (int(X)+1023+1)&-2048 != 1 3068 // Do 2- first because addl just updated the flags. 3069 cmov32(Assembler::equal,rax,rcx); 3070 cmpl(rdx,1); 3071 cmov32(Assembler::equal,rax,rcx); 3072 testl(rdx,rcx); 3073 cmov32(Assembler::notEqual,rax,rcx); 3074 movl(Address(rsp,4),rax); 3075 movl(Address(rsp,0),0); 3076 fmul_d(Address(rsp,0)); // Stack: 2^X ... 3077 addptr(rsp,sizeof(jdouble)); 3078 } 3079 3080 void MacroAssembler::increase_precision() { 3081 subptr(rsp, BytesPerWord); 3082 fnstcw(Address(rsp, 0)); 3083 movl(rax, Address(rsp, 0)); 3084 orl(rax, 0x300); 3085 push(rax); 3086 fldcw(Address(rsp, 0)); 3087 pop(rax); 3088 } 3089 3090 void MacroAssembler::restore_precision() { 3091 fldcw(Address(rsp, 0)); 3092 addptr(rsp, BytesPerWord); 3093 } 3094 3095 void MacroAssembler::fast_pow() { 3096 // computes X^Y = 2^(Y * log2(X)) 3097 // if fast computation is not possible, result is NaN. Requires 3098 // fallback from user of this macro. 3099 // increase precision for intermediate steps of the computation 3100 BLOCK_COMMENT("fast_pow {"); 3101 increase_precision(); 3102 fyl2x(); // Stack: (Y*log2(X)) ... 3103 pow_exp_core_encoding(); // Stack: exp(X) ... 3104 restore_precision(); 3105 BLOCK_COMMENT("} fast_pow"); 3106 } 3107 3108 void MacroAssembler::fast_exp() { 3109 // computes exp(X) = 2^(X * log2(e)) 3110 // if fast computation is not possible, result is NaN. Requires 3111 // fallback from user of this macro. 3112 // increase precision for intermediate steps of the computation 3113 increase_precision(); 3114 fldl2e(); // Stack: log2(e) X ... 3115 fmulp(1); // Stack: (X*log2(e)) ... 3116 pow_exp_core_encoding(); // Stack: exp(X) ... 3117 restore_precision(); 3118 } 3119 3120 void MacroAssembler::pow_or_exp(bool is_exp, int num_fpu_regs_in_use) { 3121 // kills rax, rcx, rdx 3122 // pow and exp needs 2 extra registers on the fpu stack. 3123 Label slow_case, done; 3124 Register tmp = noreg; 3125 if (!VM_Version::supports_cmov()) { 3126 // fcmp needs a temporary so preserve rdx, 3127 tmp = rdx; 3128 } 3129 Register tmp2 = rax; 3130 Register tmp3 = rcx; 3131 3132 if (is_exp) { 3133 // Stack: X 3134 fld_s(0); // duplicate argument for runtime call. Stack: X X 3135 fast_exp(); // Stack: exp(X) X 3136 fcmp(tmp, 0, false, false); // Stack: exp(X) X 3137 // exp(X) not equal to itself: exp(X) is NaN go to slow case. 3138 jcc(Assembler::parity, slow_case); 3139 // get rid of duplicate argument. Stack: exp(X) 3140 if (num_fpu_regs_in_use > 0) { 3141 fxch(); 3142 fpop(); 3143 } else { 3144 ffree(1); 3145 } 3146 jmp(done); 3147 } else { 3148 // Stack: X Y 3149 Label x_negative, y_not_2; 3150 3151 static double two = 2.0; 3152 ExternalAddress two_addr((address)&two); 3153 3154 // constant maybe too far on 64 bit 3155 lea(tmp2, two_addr); 3156 fld_d(Address(tmp2, 0)); // Stack: 2 X Y 3157 fcmp(tmp, 2, true, false); // Stack: X Y 3158 jcc(Assembler::parity, y_not_2); 3159 jcc(Assembler::notEqual, y_not_2); 3160 3161 fxch(); fpop(); // Stack: X 3162 fmul(0); // Stack: X*X 3163 3164 jmp(done); 3165 3166 bind(y_not_2); 3167 3168 fldz(); // Stack: 0 X Y 3169 fcmp(tmp, 1, true, false); // Stack: X Y 3170 jcc(Assembler::above, x_negative); 3171 3172 // X >= 0 3173 3174 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y 3175 fld_s(1); // Stack: X Y X Y 3176 fast_pow(); // Stack: X^Y X Y 3177 fcmp(tmp, 0, false, false); // Stack: X^Y X Y 3178 // X^Y not equal to itself: X^Y is NaN go to slow case. 3179 jcc(Assembler::parity, slow_case); 3180 // get rid of duplicate arguments. Stack: X^Y 3181 if (num_fpu_regs_in_use > 0) { 3182 fxch(); fpop(); 3183 fxch(); fpop(); 3184 } else { 3185 ffree(2); 3186 ffree(1); 3187 } 3188 jmp(done); 3189 3190 // X <= 0 3191 bind(x_negative); 3192 3193 fld_s(1); // Stack: Y X Y 3194 frndint(); // Stack: int(Y) X Y 3195 fcmp(tmp, 2, false, false); // Stack: int(Y) X Y 3196 jcc(Assembler::notEqual, slow_case); 3197 3198 subptr(rsp, 8); 3199 3200 // For X^Y, when X < 0, Y has to be an integer and the final 3201 // result depends on whether it's odd or even. We just checked 3202 // that int(Y) == Y. We move int(Y) to gp registers as a 64 bit 3203 // integer to test its parity. If int(Y) is huge and doesn't fit 3204 // in the 64 bit integer range, the integer indefinite value will 3205 // end up in the gp registers. Huge numbers are all even, the 3206 // integer indefinite number is even so it's fine. 3207 3208 #ifdef ASSERT 3209 // Let's check we don't end up with an integer indefinite number 3210 // when not expected. First test for huge numbers: check whether 3211 // int(Y)+1 == int(Y) which is true for very large numbers and 3212 // those are all even. A 64 bit integer is guaranteed to not 3213 // overflow for numbers where y+1 != y (when precision is set to 3214 // double precision). 3215 Label y_not_huge; 3216 3217 fld1(); // Stack: 1 int(Y) X Y 3218 fadd(1); // Stack: 1+int(Y) int(Y) X Y 3219 3220 #ifdef _LP64 3221 // trip to memory to force the precision down from double extended 3222 // precision 3223 fstp_d(Address(rsp, 0)); 3224 fld_d(Address(rsp, 0)); 3225 #endif 3226 3227 fcmp(tmp, 1, true, false); // Stack: int(Y) X Y 3228 #endif 3229 3230 // move int(Y) as 64 bit integer to thread's stack 3231 fistp_d(Address(rsp,0)); // Stack: X Y 3232 3233 #ifdef ASSERT 3234 jcc(Assembler::notEqual, y_not_huge); 3235 3236 // Y is huge so we know it's even. It may not fit in a 64 bit 3237 // integer and we don't want the debug code below to see the 3238 // integer indefinite value so overwrite int(Y) on the thread's 3239 // stack with 0. 3240 movl(Address(rsp, 0), 0); 3241 movl(Address(rsp, 4), 0); 3242 3243 bind(y_not_huge); 3244 #endif 3245 3246 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y 3247 fld_s(1); // Stack: X Y X Y 3248 fabs(); // Stack: abs(X) Y X Y 3249 fast_pow(); // Stack: abs(X)^Y X Y 3250 fcmp(tmp, 0, false, false); // Stack: abs(X)^Y X Y 3251 // abs(X)^Y not equal to itself: abs(X)^Y is NaN go to slow case. 3252 3253 pop(tmp2); 3254 NOT_LP64(pop(tmp3)); 3255 jcc(Assembler::parity, slow_case); 3256 3257 #ifdef ASSERT 3258 // Check that int(Y) is not integer indefinite value (int 3259 // overflow). Shouldn't happen because for values that would 3260 // overflow, 1+int(Y)==Y which was tested earlier. 3261 #ifndef _LP64 3262 { 3263 Label integer; 3264 testl(tmp2, tmp2); 3265 jcc(Assembler::notZero, integer); 3266 cmpl(tmp3, 0x80000000); 3267 jcc(Assembler::notZero, integer); 3268 STOP("integer indefinite value shouldn't be seen here"); 3269 bind(integer); 3270 } 3271 #else 3272 { 3273 Label integer; 3274 mov(tmp3, tmp2); // preserve tmp2 for parity check below 3275 shlq(tmp3, 1); 3276 jcc(Assembler::carryClear, integer); 3277 jcc(Assembler::notZero, integer); 3278 STOP("integer indefinite value shouldn't be seen here"); 3279 bind(integer); 3280 } 3281 #endif 3282 #endif 3283 3284 // get rid of duplicate arguments. Stack: X^Y 3285 if (num_fpu_regs_in_use > 0) { 3286 fxch(); fpop(); 3287 fxch(); fpop(); 3288 } else { 3289 ffree(2); 3290 ffree(1); 3291 } 3292 3293 testl(tmp2, 1); 3294 jcc(Assembler::zero, done); // X <= 0, Y even: X^Y = abs(X)^Y 3295 // X <= 0, Y even: X^Y = -abs(X)^Y 3296 3297 fchs(); // Stack: -abs(X)^Y Y 3298 jmp(done); 3299 } 3300 3301 // slow case: runtime call 3302 bind(slow_case); 3303 3304 fpop(); // pop incorrect result or int(Y) 3305 3306 fp_runtime_fallback(is_exp ? CAST_FROM_FN_PTR(address, SharedRuntime::dexp) : CAST_FROM_FN_PTR(address, SharedRuntime::dpow), 3307 is_exp ? 1 : 2, num_fpu_regs_in_use); 3308 3309 // Come here with result in F-TOS 3310 bind(done); 3311 } 3312 3313 void MacroAssembler::fpop() { 3314 ffree(); 3315 fincstp(); 3316 } 3317 3318 void MacroAssembler::load_float(Address src) { 3319 if (UseSSE >= 1) { 3320 movflt(xmm0, src); 3321 } else { 3322 LP64_ONLY(ShouldNotReachHere()); 3323 NOT_LP64(fld_s(src)); 3324 } 3325 } 3326 3327 void MacroAssembler::store_float(Address dst) { 3328 if (UseSSE >= 1) { 3329 movflt(dst, xmm0); 3330 } else { 3331 LP64_ONLY(ShouldNotReachHere()); 3332 NOT_LP64(fstp_s(dst)); 3333 } 3334 } 3335 3336 void MacroAssembler::load_double(Address src) { 3337 if (UseSSE >= 2) { 3338 movdbl(xmm0, src); 3339 } else { 3340 LP64_ONLY(ShouldNotReachHere()); 3341 NOT_LP64(fld_d(src)); 3342 } 3343 } 3344 3345 void MacroAssembler::store_double(Address dst) { 3346 if (UseSSE >= 2) { 3347 movdbl(dst, xmm0); 3348 } else { 3349 LP64_ONLY(ShouldNotReachHere()); 3350 NOT_LP64(fstp_d(dst)); 3351 } 3352 } 3353 3354 void MacroAssembler::fremr(Register tmp) { 3355 save_rax(tmp); 3356 { Label L; 3357 bind(L); 3358 fprem(); 3359 fwait(); fnstsw_ax(); 3360 #ifdef _LP64 3361 testl(rax, 0x400); 3362 jcc(Assembler::notEqual, L); 3363 #else 3364 sahf(); 3365 jcc(Assembler::parity, L); 3366 #endif // _LP64 3367 } 3368 restore_rax(tmp); 3369 // Result is in ST0. 3370 // Note: fxch & fpop to get rid of ST1 3371 // (otherwise FPU stack could overflow eventually) 3372 fxch(1); 3373 fpop(); 3374 } 3375 3376 3377 void MacroAssembler::incrementl(AddressLiteral dst) { 3378 if (reachable(dst)) { 3379 incrementl(as_Address(dst)); 3380 } else { 3381 lea(rscratch1, dst); 3382 incrementl(Address(rscratch1, 0)); 3383 } 3384 } 3385 3386 void MacroAssembler::incrementl(ArrayAddress dst) { 3387 incrementl(as_Address(dst)); 3388 } 3389 3390 void MacroAssembler::incrementl(Register reg, int value) { 3391 if (value == min_jint) {addl(reg, value) ; return; } 3392 if (value < 0) { decrementl(reg, -value); return; } 3393 if (value == 0) { ; return; } 3394 if (value == 1 && UseIncDec) { incl(reg) ; return; } 3395 /* else */ { addl(reg, value) ; return; } 3396 } 3397 3398 void MacroAssembler::incrementl(Address dst, int value) { 3399 if (value == min_jint) {addl(dst, value) ; return; } 3400 if (value < 0) { decrementl(dst, -value); return; } 3401 if (value == 0) { ; return; } 3402 if (value == 1 && UseIncDec) { incl(dst) ; return; } 3403 /* else */ { addl(dst, value) ; return; } 3404 } 3405 3406 void MacroAssembler::jump(AddressLiteral dst) { 3407 if (reachable(dst)) { 3408 jmp_literal(dst.target(), dst.rspec()); 3409 } else { 3410 lea(rscratch1, dst); 3411 jmp(rscratch1); 3412 } 3413 } 3414 3415 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { 3416 if (reachable(dst)) { 3417 InstructionMark im(this); 3418 relocate(dst.reloc()); 3419 const int short_size = 2; 3420 const int long_size = 6; 3421 int offs = (intptr_t)dst.target() - ((intptr_t)pc()); 3422 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { 3423 // 0111 tttn #8-bit disp 3424 emit_int8(0x70 | cc); 3425 emit_int8((offs - short_size) & 0xFF); 3426 } else { 3427 // 0000 1111 1000 tttn #32-bit disp 3428 emit_int8(0x0F); 3429 emit_int8((unsigned char)(0x80 | cc)); 3430 emit_int32(offs - long_size); 3431 } 3432 } else { 3433 #ifdef ASSERT 3434 warning("reversing conditional branch"); 3435 #endif /* ASSERT */ 3436 Label skip; 3437 jccb(reverse[cc], skip); 3438 lea(rscratch1, dst); 3439 Assembler::jmp(rscratch1); 3440 bind(skip); 3441 } 3442 } 3443 3444 void MacroAssembler::ldmxcsr(AddressLiteral src) { 3445 if (reachable(src)) { 3446 Assembler::ldmxcsr(as_Address(src)); 3447 } else { 3448 lea(rscratch1, src); 3449 Assembler::ldmxcsr(Address(rscratch1, 0)); 3450 } 3451 } 3452 3453 int MacroAssembler::load_signed_byte(Register dst, Address src) { 3454 int off; 3455 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3456 off = offset(); 3457 movsbl(dst, src); // movsxb 3458 } else { 3459 off = load_unsigned_byte(dst, src); 3460 shll(dst, 24); 3461 sarl(dst, 24); 3462 } 3463 return off; 3464 } 3465 3466 // Note: load_signed_short used to be called load_signed_word. 3467 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler 3468 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. 3469 // The term "word" in HotSpot means a 32- or 64-bit machine word. 3470 int MacroAssembler::load_signed_short(Register dst, Address src) { 3471 int off; 3472 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3473 // This is dubious to me since it seems safe to do a signed 16 => 64 bit 3474 // version but this is what 64bit has always done. This seems to imply 3475 // that users are only using 32bits worth. 3476 off = offset(); 3477 movswl(dst, src); // movsxw 3478 } else { 3479 off = load_unsigned_short(dst, src); 3480 shll(dst, 16); 3481 sarl(dst, 16); 3482 } 3483 return off; 3484 } 3485 3486 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { 3487 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 3488 // and "3.9 Partial Register Penalties", p. 22). 3489 int off; 3490 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { 3491 off = offset(); 3492 movzbl(dst, src); // movzxb 3493 } else { 3494 xorl(dst, dst); 3495 off = offset(); 3496 movb(dst, src); 3497 } 3498 return off; 3499 } 3500 3501 // Note: load_unsigned_short used to be called load_unsigned_word. 3502 int MacroAssembler::load_unsigned_short(Register dst, Address src) { 3503 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 3504 // and "3.9 Partial Register Penalties", p. 22). 3505 int off; 3506 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { 3507 off = offset(); 3508 movzwl(dst, src); // movzxw 3509 } else { 3510 xorl(dst, dst); 3511 off = offset(); 3512 movw(dst, src); 3513 } 3514 return off; 3515 } 3516 3517 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { 3518 switch (size_in_bytes) { 3519 #ifndef _LP64 3520 case 8: 3521 assert(dst2 != noreg, "second dest register required"); 3522 movl(dst, src); 3523 movl(dst2, src.plus_disp(BytesPerInt)); 3524 break; 3525 #else 3526 case 8: movq(dst, src); break; 3527 #endif 3528 case 4: movl(dst, src); break; 3529 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; 3530 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; 3531 default: ShouldNotReachHere(); 3532 } 3533 } 3534 3535 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { 3536 switch (size_in_bytes) { 3537 #ifndef _LP64 3538 case 8: 3539 assert(src2 != noreg, "second source register required"); 3540 movl(dst, src); 3541 movl(dst.plus_disp(BytesPerInt), src2); 3542 break; 3543 #else 3544 case 8: movq(dst, src); break; 3545 #endif 3546 case 4: movl(dst, src); break; 3547 case 2: movw(dst, src); break; 3548 case 1: movb(dst, src); break; 3549 default: ShouldNotReachHere(); 3550 } 3551 } 3552 3553 void MacroAssembler::mov32(AddressLiteral dst, Register src) { 3554 if (reachable(dst)) { 3555 movl(as_Address(dst), src); 3556 } else { 3557 lea(rscratch1, dst); 3558 movl(Address(rscratch1, 0), src); 3559 } 3560 } 3561 3562 void MacroAssembler::mov32(Register dst, AddressLiteral src) { 3563 if (reachable(src)) { 3564 movl(dst, as_Address(src)); 3565 } else { 3566 lea(rscratch1, src); 3567 movl(dst, Address(rscratch1, 0)); 3568 } 3569 } 3570 3571 // C++ bool manipulation 3572 3573 void MacroAssembler::movbool(Register dst, Address src) { 3574 if(sizeof(bool) == 1) 3575 movb(dst, src); 3576 else if(sizeof(bool) == 2) 3577 movw(dst, src); 3578 else if(sizeof(bool) == 4) 3579 movl(dst, src); 3580 else 3581 // unsupported 3582 ShouldNotReachHere(); 3583 } 3584 3585 void MacroAssembler::movbool(Address dst, bool boolconst) { 3586 if(sizeof(bool) == 1) 3587 movb(dst, (int) boolconst); 3588 else if(sizeof(bool) == 2) 3589 movw(dst, (int) boolconst); 3590 else if(sizeof(bool) == 4) 3591 movl(dst, (int) boolconst); 3592 else 3593 // unsupported 3594 ShouldNotReachHere(); 3595 } 3596 3597 void MacroAssembler::movbool(Address dst, Register src) { 3598 if(sizeof(bool) == 1) 3599 movb(dst, src); 3600 else if(sizeof(bool) == 2) 3601 movw(dst, src); 3602 else if(sizeof(bool) == 4) 3603 movl(dst, src); 3604 else 3605 // unsupported 3606 ShouldNotReachHere(); 3607 } 3608 3609 void MacroAssembler::movbyte(ArrayAddress dst, int src) { 3610 movb(as_Address(dst), src); 3611 } 3612 3613 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) { 3614 if (reachable(src)) { 3615 movdl(dst, as_Address(src)); 3616 } else { 3617 lea(rscratch1, src); 3618 movdl(dst, Address(rscratch1, 0)); 3619 } 3620 } 3621 3622 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) { 3623 if (reachable(src)) { 3624 movq(dst, as_Address(src)); 3625 } else { 3626 lea(rscratch1, src); 3627 movq(dst, Address(rscratch1, 0)); 3628 } 3629 } 3630 3631 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { 3632 if (reachable(src)) { 3633 if (UseXmmLoadAndClearUpper) { 3634 movsd (dst, as_Address(src)); 3635 } else { 3636 movlpd(dst, as_Address(src)); 3637 } 3638 } else { 3639 lea(rscratch1, src); 3640 if (UseXmmLoadAndClearUpper) { 3641 movsd (dst, Address(rscratch1, 0)); 3642 } else { 3643 movlpd(dst, Address(rscratch1, 0)); 3644 } 3645 } 3646 } 3647 3648 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { 3649 if (reachable(src)) { 3650 movss(dst, as_Address(src)); 3651 } else { 3652 lea(rscratch1, src); 3653 movss(dst, Address(rscratch1, 0)); 3654 } 3655 } 3656 3657 void MacroAssembler::movptr(Register dst, Register src) { 3658 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3659 } 3660 3661 void MacroAssembler::movptr(Register dst, Address src) { 3662 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3663 } 3664 3665 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 3666 void MacroAssembler::movptr(Register dst, intptr_t src) { 3667 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); 3668 } 3669 3670 void MacroAssembler::movptr(Address dst, Register src) { 3671 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3672 } 3673 3674 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) { 3675 if (reachable(src)) { 3676 Assembler::movdqu(dst, as_Address(src)); 3677 } else { 3678 lea(rscratch1, src); 3679 Assembler::movdqu(dst, Address(rscratch1, 0)); 3680 } 3681 } 3682 3683 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) { 3684 if (reachable(src)) { 3685 Assembler::movdqa(dst, as_Address(src)); 3686 } else { 3687 lea(rscratch1, src); 3688 Assembler::movdqa(dst, Address(rscratch1, 0)); 3689 } 3690 } 3691 3692 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { 3693 if (reachable(src)) { 3694 Assembler::movsd(dst, as_Address(src)); 3695 } else { 3696 lea(rscratch1, src); 3697 Assembler::movsd(dst, Address(rscratch1, 0)); 3698 } 3699 } 3700 3701 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { 3702 if (reachable(src)) { 3703 Assembler::movss(dst, as_Address(src)); 3704 } else { 3705 lea(rscratch1, src); 3706 Assembler::movss(dst, Address(rscratch1, 0)); 3707 } 3708 } 3709 3710 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) { 3711 if (reachable(src)) { 3712 Assembler::mulsd(dst, as_Address(src)); 3713 } else { 3714 lea(rscratch1, src); 3715 Assembler::mulsd(dst, Address(rscratch1, 0)); 3716 } 3717 } 3718 3719 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) { 3720 if (reachable(src)) { 3721 Assembler::mulss(dst, as_Address(src)); 3722 } else { 3723 lea(rscratch1, src); 3724 Assembler::mulss(dst, Address(rscratch1, 0)); 3725 } 3726 } 3727 3728 void MacroAssembler::null_check(Register reg, int offset) { 3729 if (needs_explicit_null_check(offset)) { 3730 // provoke OS NULL exception if reg = NULL by 3731 // accessing M[reg] w/o changing any (non-CC) registers 3732 // NOTE: cmpl is plenty here to provoke a segv 3733 cmpptr(rax, Address(reg, 0)); 3734 // Note: should probably use testl(rax, Address(reg, 0)); 3735 // may be shorter code (however, this version of 3736 // testl needs to be implemented first) 3737 } else { 3738 // nothing to do, (later) access of M[reg + offset] 3739 // will provoke OS NULL exception if reg = NULL 3740 } 3741 } 3742 3743 void MacroAssembler::os_breakpoint() { 3744 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability 3745 // (e.g., MSVC can't call ps() otherwise) 3746 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); 3747 } 3748 3749 void MacroAssembler::pop_CPU_state() { 3750 pop_FPU_state(); 3751 pop_IU_state(); 3752 } 3753 3754 void MacroAssembler::pop_FPU_state() { 3755 NOT_LP64(frstor(Address(rsp, 0));) 3756 LP64_ONLY(fxrstor(Address(rsp, 0));) 3757 addptr(rsp, FPUStateSizeInWords * wordSize); 3758 } 3759 3760 void MacroAssembler::pop_IU_state() { 3761 popa(); 3762 LP64_ONLY(addq(rsp, 8)); 3763 popf(); 3764 } 3765 3766 // Save Integer and Float state 3767 // Warning: Stack must be 16 byte aligned (64bit) 3768 void MacroAssembler::push_CPU_state() { 3769 push_IU_state(); 3770 push_FPU_state(); 3771 } 3772 3773 void MacroAssembler::push_FPU_state() { 3774 subptr(rsp, FPUStateSizeInWords * wordSize); 3775 #ifndef _LP64 3776 fnsave(Address(rsp, 0)); 3777 fwait(); 3778 #else 3779 fxsave(Address(rsp, 0)); 3780 #endif // LP64 3781 } 3782 3783 void MacroAssembler::push_IU_state() { 3784 // Push flags first because pusha kills them 3785 pushf(); 3786 // Make sure rsp stays 16-byte aligned 3787 LP64_ONLY(subq(rsp, 8)); 3788 pusha(); 3789 } 3790 3791 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) { 3792 // determine java_thread register 3793 if (!java_thread->is_valid()) { 3794 java_thread = rdi; 3795 get_thread(java_thread); 3796 } 3797 // we must set sp to zero to clear frame 3798 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 3799 if (clear_fp) { 3800 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 3801 } 3802 3803 if (clear_pc) 3804 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 3805 3806 } 3807 3808 void MacroAssembler::restore_rax(Register tmp) { 3809 if (tmp == noreg) pop(rax); 3810 else if (tmp != rax) mov(rax, tmp); 3811 } 3812 3813 void MacroAssembler::round_to(Register reg, int modulus) { 3814 addptr(reg, modulus - 1); 3815 andptr(reg, -modulus); 3816 } 3817 3818 void MacroAssembler::save_rax(Register tmp) { 3819 if (tmp == noreg) push(rax); 3820 else if (tmp != rax) mov(tmp, rax); 3821 } 3822 3823 // Write serialization page so VM thread can do a pseudo remote membar. 3824 // We use the current thread pointer to calculate a thread specific 3825 // offset to write to within the page. This minimizes bus traffic 3826 // due to cache line collision. 3827 void MacroAssembler::serialize_memory(Register thread, Register tmp) { 3828 movl(tmp, thread); 3829 shrl(tmp, os::get_serialize_page_shift_count()); 3830 andl(tmp, (os::vm_page_size() - sizeof(int))); 3831 3832 Address index(noreg, tmp, Address::times_1); 3833 ExternalAddress page(os::get_memory_serialize_page()); 3834 3835 // Size of store must match masking code above 3836 movl(as_Address(ArrayAddress(page, index)), tmp); 3837 } 3838 3839 // Calls to C land 3840 // 3841 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded 3842 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp 3843 // has to be reset to 0. This is required to allow proper stack traversal. 3844 void MacroAssembler::set_last_Java_frame(Register java_thread, 3845 Register last_java_sp, 3846 Register last_java_fp, 3847 address last_java_pc) { 3848 // determine java_thread register 3849 if (!java_thread->is_valid()) { 3850 java_thread = rdi; 3851 get_thread(java_thread); 3852 } 3853 // determine last_java_sp register 3854 if (!last_java_sp->is_valid()) { 3855 last_java_sp = rsp; 3856 } 3857 3858 // last_java_fp is optional 3859 3860 if (last_java_fp->is_valid()) { 3861 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); 3862 } 3863 3864 // last_java_pc is optional 3865 3866 if (last_java_pc != NULL) { 3867 lea(Address(java_thread, 3868 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), 3869 InternalAddress(last_java_pc)); 3870 3871 } 3872 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 3873 } 3874 3875 void MacroAssembler::shlptr(Register dst, int imm8) { 3876 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); 3877 } 3878 3879 void MacroAssembler::shrptr(Register dst, int imm8) { 3880 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); 3881 } 3882 3883 void MacroAssembler::sign_extend_byte(Register reg) { 3884 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { 3885 movsbl(reg, reg); // movsxb 3886 } else { 3887 shll(reg, 24); 3888 sarl(reg, 24); 3889 } 3890 } 3891 3892 void MacroAssembler::sign_extend_short(Register reg) { 3893 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3894 movswl(reg, reg); // movsxw 3895 } else { 3896 shll(reg, 16); 3897 sarl(reg, 16); 3898 } 3899 } 3900 3901 void MacroAssembler::testl(Register dst, AddressLiteral src) { 3902 assert(reachable(src), "Address should be reachable"); 3903 testl(dst, as_Address(src)); 3904 } 3905 3906 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) { 3907 if (reachable(src)) { 3908 Assembler::sqrtsd(dst, as_Address(src)); 3909 } else { 3910 lea(rscratch1, src); 3911 Assembler::sqrtsd(dst, Address(rscratch1, 0)); 3912 } 3913 } 3914 3915 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) { 3916 if (reachable(src)) { 3917 Assembler::sqrtss(dst, as_Address(src)); 3918 } else { 3919 lea(rscratch1, src); 3920 Assembler::sqrtss(dst, Address(rscratch1, 0)); 3921 } 3922 } 3923 3924 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) { 3925 if (reachable(src)) { 3926 Assembler::subsd(dst, as_Address(src)); 3927 } else { 3928 lea(rscratch1, src); 3929 Assembler::subsd(dst, Address(rscratch1, 0)); 3930 } 3931 } 3932 3933 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) { 3934 if (reachable(src)) { 3935 Assembler::subss(dst, as_Address(src)); 3936 } else { 3937 lea(rscratch1, src); 3938 Assembler::subss(dst, Address(rscratch1, 0)); 3939 } 3940 } 3941 3942 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { 3943 if (reachable(src)) { 3944 Assembler::ucomisd(dst, as_Address(src)); 3945 } else { 3946 lea(rscratch1, src); 3947 Assembler::ucomisd(dst, Address(rscratch1, 0)); 3948 } 3949 } 3950 3951 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { 3952 if (reachable(src)) { 3953 Assembler::ucomiss(dst, as_Address(src)); 3954 } else { 3955 lea(rscratch1, src); 3956 Assembler::ucomiss(dst, Address(rscratch1, 0)); 3957 } 3958 } 3959 3960 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { 3961 // Used in sign-bit flipping with aligned address. 3962 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 3963 if (reachable(src)) { 3964 Assembler::xorpd(dst, as_Address(src)); 3965 } else { 3966 lea(rscratch1, src); 3967 Assembler::xorpd(dst, Address(rscratch1, 0)); 3968 } 3969 } 3970 3971 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { 3972 // Used in sign-bit flipping with aligned address. 3973 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 3974 if (reachable(src)) { 3975 Assembler::xorps(dst, as_Address(src)); 3976 } else { 3977 lea(rscratch1, src); 3978 Assembler::xorps(dst, Address(rscratch1, 0)); 3979 } 3980 } 3981 3982 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) { 3983 // Used in sign-bit flipping with aligned address. 3984 bool aligned_adr = (((intptr_t)src.target() & 15) == 0); 3985 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes"); 3986 if (reachable(src)) { 3987 Assembler::pshufb(dst, as_Address(src)); 3988 } else { 3989 lea(rscratch1, src); 3990 Assembler::pshufb(dst, Address(rscratch1, 0)); 3991 } 3992 } 3993 3994 // AVX 3-operands instructions 3995 3996 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3997 if (reachable(src)) { 3998 vaddsd(dst, nds, as_Address(src)); 3999 } else { 4000 lea(rscratch1, src); 4001 vaddsd(dst, nds, Address(rscratch1, 0)); 4002 } 4003 } 4004 4005 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4006 if (reachable(src)) { 4007 vaddss(dst, nds, as_Address(src)); 4008 } else { 4009 lea(rscratch1, src); 4010 vaddss(dst, nds, Address(rscratch1, 0)); 4011 } 4012 } 4013 4014 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 4015 if (reachable(src)) { 4016 vandpd(dst, nds, as_Address(src), vector_len); 4017 } else { 4018 lea(rscratch1, src); 4019 vandpd(dst, nds, Address(rscratch1, 0), vector_len); 4020 } 4021 } 4022 4023 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 4024 if (reachable(src)) { 4025 vandps(dst, nds, as_Address(src), vector_len); 4026 } else { 4027 lea(rscratch1, src); 4028 vandps(dst, nds, Address(rscratch1, 0), vector_len); 4029 } 4030 } 4031 4032 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4033 if (reachable(src)) { 4034 vdivsd(dst, nds, as_Address(src)); 4035 } else { 4036 lea(rscratch1, src); 4037 vdivsd(dst, nds, Address(rscratch1, 0)); 4038 } 4039 } 4040 4041 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4042 if (reachable(src)) { 4043 vdivss(dst, nds, as_Address(src)); 4044 } else { 4045 lea(rscratch1, src); 4046 vdivss(dst, nds, Address(rscratch1, 0)); 4047 } 4048 } 4049 4050 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4051 if (reachable(src)) { 4052 vmulsd(dst, nds, as_Address(src)); 4053 } else { 4054 lea(rscratch1, src); 4055 vmulsd(dst, nds, Address(rscratch1, 0)); 4056 } 4057 } 4058 4059 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4060 if (reachable(src)) { 4061 vmulss(dst, nds, as_Address(src)); 4062 } else { 4063 lea(rscratch1, src); 4064 vmulss(dst, nds, Address(rscratch1, 0)); 4065 } 4066 } 4067 4068 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4069 if (reachable(src)) { 4070 vsubsd(dst, nds, as_Address(src)); 4071 } else { 4072 lea(rscratch1, src); 4073 vsubsd(dst, nds, Address(rscratch1, 0)); 4074 } 4075 } 4076 4077 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4078 if (reachable(src)) { 4079 vsubss(dst, nds, as_Address(src)); 4080 } else { 4081 lea(rscratch1, src); 4082 vsubss(dst, nds, Address(rscratch1, 0)); 4083 } 4084 } 4085 4086 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 4087 if (reachable(src)) { 4088 vxorpd(dst, nds, as_Address(src), vector_len); 4089 } else { 4090 lea(rscratch1, src); 4091 vxorpd(dst, nds, Address(rscratch1, 0), vector_len); 4092 } 4093 } 4094 4095 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 4096 if (reachable(src)) { 4097 vxorps(dst, nds, as_Address(src), vector_len); 4098 } else { 4099 lea(rscratch1, src); 4100 vxorps(dst, nds, Address(rscratch1, 0), vector_len); 4101 } 4102 } 4103 4104 4105 ////////////////////////////////////////////////////////////////////////////////// 4106 #if INCLUDE_ALL_GCS 4107 4108 void MacroAssembler::g1_write_barrier_pre(Register obj, 4109 Register pre_val, 4110 Register thread, 4111 Register tmp, 4112 bool tosca_live, 4113 bool expand_call) { 4114 4115 // If expand_call is true then we expand the call_VM_leaf macro 4116 // directly to skip generating the check by 4117 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. 4118 4119 #ifdef _LP64 4120 assert(thread == r15_thread, "must be"); 4121 #endif // _LP64 4122 4123 Label done; 4124 Label runtime; 4125 4126 assert(pre_val != noreg, "check this code"); 4127 4128 if (obj != noreg) { 4129 assert_different_registers(obj, pre_val, tmp); 4130 assert(pre_val != rax, "check this code"); 4131 } 4132 4133 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 4134 PtrQueue::byte_offset_of_active())); 4135 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 4136 PtrQueue::byte_offset_of_index())); 4137 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 4138 PtrQueue::byte_offset_of_buf())); 4139 4140 4141 // Is marking active? 4142 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { 4143 cmpl(in_progress, 0); 4144 } else { 4145 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption"); 4146 cmpb(in_progress, 0); 4147 } 4148 jcc(Assembler::equal, done); 4149 4150 // Do we need to load the previous value? 4151 if (obj != noreg) { 4152 load_heap_oop(pre_val, Address(obj, 0)); 4153 } 4154 4155 // Is the previous value null? 4156 cmpptr(pre_val, (int32_t) NULL_WORD); 4157 jcc(Assembler::equal, done); 4158 4159 // Can we store original value in the thread's buffer? 4160 // Is index == 0? 4161 // (The index field is typed as size_t.) 4162 4163 movptr(tmp, index); // tmp := *index_adr 4164 cmpptr(tmp, 0); // tmp == 0? 4165 jcc(Assembler::equal, runtime); // If yes, goto runtime 4166 4167 subptr(tmp, wordSize); // tmp := tmp - wordSize 4168 movptr(index, tmp); // *index_adr := tmp 4169 addptr(tmp, buffer); // tmp := tmp + *buffer_adr 4170 4171 // Record the previous value 4172 movptr(Address(tmp, 0), pre_val); 4173 jmp(done); 4174 4175 bind(runtime); 4176 // save the live input values 4177 if(tosca_live) push(rax); 4178 4179 if (obj != noreg && obj != rax) 4180 push(obj); 4181 4182 if (pre_val != rax) 4183 push(pre_val); 4184 4185 // Calling the runtime using the regular call_VM_leaf mechanism generates 4186 // code (generated by InterpreterMacroAssember::call_VM_leaf_base) 4187 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL. 4188 // 4189 // If we care generating the pre-barrier without a frame (e.g. in the 4190 // intrinsified Reference.get() routine) then ebp might be pointing to 4191 // the caller frame and so this check will most likely fail at runtime. 4192 // 4193 // Expanding the call directly bypasses the generation of the check. 4194 // So when we do not have have a full interpreter frame on the stack 4195 // expand_call should be passed true. 4196 4197 NOT_LP64( push(thread); ) 4198 4199 if (expand_call) { 4200 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); ) 4201 pass_arg1(this, thread); 4202 pass_arg0(this, pre_val); 4203 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2); 4204 } else { 4205 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread); 4206 } 4207 4208 NOT_LP64( pop(thread); ) 4209 4210 // save the live input values 4211 if (pre_val != rax) 4212 pop(pre_val); 4213 4214 if (obj != noreg && obj != rax) 4215 pop(obj); 4216 4217 if(tosca_live) pop(rax); 4218 4219 bind(done); 4220 } 4221 4222 void MacroAssembler::g1_write_barrier_post(Register store_addr, 4223 Register new_val, 4224 Register thread, 4225 Register tmp, 4226 Register tmp2) { 4227 #ifdef _LP64 4228 assert(thread == r15_thread, "must be"); 4229 #endif // _LP64 4230 4231 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 4232 PtrQueue::byte_offset_of_index())); 4233 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 4234 PtrQueue::byte_offset_of_buf())); 4235 4236 CardTableModRefBS* ct = 4237 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set()); 4238 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 4239 4240 Label done; 4241 Label runtime; 4242 4243 // Does store cross heap regions? 4244 4245 movptr(tmp, store_addr); 4246 xorptr(tmp, new_val); 4247 shrptr(tmp, HeapRegion::LogOfHRGrainBytes); 4248 jcc(Assembler::equal, done); 4249 4250 // crosses regions, storing NULL? 4251 4252 cmpptr(new_val, (int32_t) NULL_WORD); 4253 jcc(Assembler::equal, done); 4254 4255 // storing region crossing non-NULL, is card already dirty? 4256 4257 const Register card_addr = tmp; 4258 const Register cardtable = tmp2; 4259 4260 movptr(card_addr, store_addr); 4261 shrptr(card_addr, CardTableModRefBS::card_shift); 4262 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT 4263 // a valid address and therefore is not properly handled by the relocation code. 4264 movptr(cardtable, (intptr_t)ct->byte_map_base); 4265 addptr(card_addr, cardtable); 4266 4267 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val()); 4268 jcc(Assembler::equal, done); 4269 4270 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 4271 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); 4272 jcc(Assembler::equal, done); 4273 4274 4275 // storing a region crossing, non-NULL oop, card is clean. 4276 // dirty card and log. 4277 4278 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); 4279 4280 cmpl(queue_index, 0); 4281 jcc(Assembler::equal, runtime); 4282 subl(queue_index, wordSize); 4283 movptr(tmp2, buffer); 4284 #ifdef _LP64 4285 movslq(rscratch1, queue_index); 4286 addq(tmp2, rscratch1); 4287 movq(Address(tmp2, 0), card_addr); 4288 #else 4289 addl(tmp2, queue_index); 4290 movl(Address(tmp2, 0), card_addr); 4291 #endif 4292 jmp(done); 4293 4294 bind(runtime); 4295 // save the live input values 4296 push(store_addr); 4297 push(new_val); 4298 #ifdef _LP64 4299 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread); 4300 #else 4301 push(thread); 4302 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); 4303 pop(thread); 4304 #endif 4305 pop(new_val); 4306 pop(store_addr); 4307 4308 bind(done); 4309 } 4310 4311 #endif // INCLUDE_ALL_GCS 4312 ////////////////////////////////////////////////////////////////////////////////// 4313 4314 4315 void MacroAssembler::store_check(Register obj, Address dst) { 4316 store_check(obj); 4317 } 4318 4319 void MacroAssembler::store_check(Register obj) { 4320 // Does a store check for the oop in register obj. The content of 4321 // register obj is destroyed afterwards. 4322 4323 BarrierSet* bs = Universe::heap()->barrier_set(); 4324 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); 4325 4326 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs); 4327 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 4328 4329 shrptr(obj, CardTableModRefBS::card_shift); 4330 4331 Address card_addr; 4332 4333 // The calculation for byte_map_base is as follows: 4334 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); 4335 // So this essentially converts an address to a displacement and it will 4336 // never need to be relocated. On 64bit however the value may be too 4337 // large for a 32bit displacement. 4338 intptr_t disp = (intptr_t) ct->byte_map_base; 4339 if (is_simm32(disp)) { 4340 card_addr = Address(noreg, obj, Address::times_1, disp); 4341 } else { 4342 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative 4343 // displacement and done in a single instruction given favorable mapping and a 4344 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation 4345 // entry and that entry is not properly handled by the relocation code. 4346 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none); 4347 Address index(noreg, obj, Address::times_1); 4348 card_addr = as_Address(ArrayAddress(cardtable, index)); 4349 } 4350 4351 int dirty = CardTableModRefBS::dirty_card_val(); 4352 if (UseCondCardMark) { 4353 Label L_already_dirty; 4354 if (UseConcMarkSweepGC) { 4355 membar(Assembler::StoreLoad); 4356 } 4357 cmpb(card_addr, dirty); 4358 jcc(Assembler::equal, L_already_dirty); 4359 movb(card_addr, dirty); 4360 bind(L_already_dirty); 4361 } else { 4362 movb(card_addr, dirty); 4363 } 4364 } 4365 4366 void MacroAssembler::subptr(Register dst, int32_t imm32) { 4367 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); 4368 } 4369 4370 // Force generation of a 4 byte immediate value even if it fits into 8bit 4371 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) { 4372 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32)); 4373 } 4374 4375 void MacroAssembler::subptr(Register dst, Register src) { 4376 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); 4377 } 4378 4379 // C++ bool manipulation 4380 void MacroAssembler::testbool(Register dst) { 4381 if(sizeof(bool) == 1) 4382 testb(dst, 0xff); 4383 else if(sizeof(bool) == 2) { 4384 // testw implementation needed for two byte bools 4385 ShouldNotReachHere(); 4386 } else if(sizeof(bool) == 4) 4387 testl(dst, dst); 4388 else 4389 // unsupported 4390 ShouldNotReachHere(); 4391 } 4392 4393 void MacroAssembler::testptr(Register dst, Register src) { 4394 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); 4395 } 4396 4397 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. 4398 void MacroAssembler::tlab_allocate(Register obj, 4399 Register var_size_in_bytes, 4400 int con_size_in_bytes, 4401 Register t1, 4402 Register t2, 4403 Label& slow_case) { 4404 assert_different_registers(obj, t1, t2); 4405 assert_different_registers(obj, var_size_in_bytes, t1); 4406 Register end = t2; 4407 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread); 4408 4409 verify_tlab(); 4410 4411 NOT_LP64(get_thread(thread)); 4412 4413 movptr(obj, Address(thread, JavaThread::tlab_top_offset())); 4414 if (var_size_in_bytes == noreg) { 4415 lea(end, Address(obj, con_size_in_bytes)); 4416 } else { 4417 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); 4418 } 4419 cmpptr(end, Address(thread, JavaThread::tlab_end_offset())); 4420 jcc(Assembler::above, slow_case); 4421 4422 // update the tlab top pointer 4423 movptr(Address(thread, JavaThread::tlab_top_offset()), end); 4424 4425 // recover var_size_in_bytes if necessary 4426 if (var_size_in_bytes == end) { 4427 subptr(var_size_in_bytes, obj); 4428 } 4429 verify_tlab(); 4430 } 4431 4432 // Preserves rbx, and rdx. 4433 Register MacroAssembler::tlab_refill(Label& retry, 4434 Label& try_eden, 4435 Label& slow_case) { 4436 Register top = rax; 4437 Register t1 = rcx; 4438 Register t2 = rsi; 4439 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread); 4440 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); 4441 Label do_refill, discard_tlab; 4442 4443 if (!Universe::heap()->supports_inline_contig_alloc()) { 4444 // No allocation in the shared eden. 4445 jmp(slow_case); 4446 } 4447 4448 NOT_LP64(get_thread(thread_reg)); 4449 4450 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 4451 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 4452 4453 // calculate amount of free space 4454 subptr(t1, top); 4455 shrptr(t1, LogHeapWordSize); 4456 4457 // Retain tlab and allocate object in shared space if 4458 // the amount free in the tlab is too large to discard. 4459 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 4460 jcc(Assembler::lessEqual, discard_tlab); 4461 4462 // Retain 4463 // %%% yuck as movptr... 4464 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); 4465 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); 4466 if (TLABStats) { 4467 // increment number of slow_allocations 4468 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); 4469 } 4470 jmp(try_eden); 4471 4472 bind(discard_tlab); 4473 if (TLABStats) { 4474 // increment number of refills 4475 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); 4476 // accumulate wastage -- t1 is amount free in tlab 4477 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); 4478 } 4479 4480 // if tlab is currently allocated (top or end != null) then 4481 // fill [top, end + alignment_reserve) with array object 4482 testptr(top, top); 4483 jcc(Assembler::zero, do_refill); 4484 4485 // set up the mark word 4486 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); 4487 // set the length to the remaining space 4488 subptr(t1, typeArrayOopDesc::header_size(T_INT)); 4489 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); 4490 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint))); 4491 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); 4492 // set klass to intArrayKlass 4493 // dubious reloc why not an oop reloc? 4494 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr())); 4495 // store klass last. concurrent gcs assumes klass length is valid if 4496 // klass field is not null. 4497 store_klass(top, t1); 4498 4499 movptr(t1, top); 4500 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 4501 incr_allocated_bytes(thread_reg, t1, 0); 4502 4503 // refill the tlab with an eden allocation 4504 bind(do_refill); 4505 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); 4506 shlptr(t1, LogHeapWordSize); 4507 // allocate new tlab, address returned in top 4508 eden_allocate(top, t1, 0, t2, slow_case); 4509 4510 // Check that t1 was preserved in eden_allocate. 4511 #ifdef ASSERT 4512 if (UseTLAB) { 4513 Label ok; 4514 Register tsize = rsi; 4515 assert_different_registers(tsize, thread_reg, t1); 4516 push(tsize); 4517 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); 4518 shlptr(tsize, LogHeapWordSize); 4519 cmpptr(t1, tsize); 4520 jcc(Assembler::equal, ok); 4521 STOP("assert(t1 != tlab size)"); 4522 should_not_reach_here(); 4523 4524 bind(ok); 4525 pop(tsize); 4526 } 4527 #endif 4528 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); 4529 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); 4530 addptr(top, t1); 4531 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); 4532 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); 4533 verify_tlab(); 4534 jmp(retry); 4535 4536 return thread_reg; // for use by caller 4537 } 4538 4539 void MacroAssembler::incr_allocated_bytes(Register thread, 4540 Register var_size_in_bytes, 4541 int con_size_in_bytes, 4542 Register t1) { 4543 if (!thread->is_valid()) { 4544 #ifdef _LP64 4545 thread = r15_thread; 4546 #else 4547 assert(t1->is_valid(), "need temp reg"); 4548 thread = t1; 4549 get_thread(thread); 4550 #endif 4551 } 4552 4553 #ifdef _LP64 4554 if (var_size_in_bytes->is_valid()) { 4555 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); 4556 } else { 4557 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); 4558 } 4559 #else 4560 if (var_size_in_bytes->is_valid()) { 4561 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); 4562 } else { 4563 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); 4564 } 4565 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0); 4566 #endif 4567 } 4568 4569 void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) { 4570 pusha(); 4571 4572 // if we are coming from c1, xmm registers may be live 4573 int off = 0; 4574 if (UseSSE == 1) { 4575 subptr(rsp, sizeof(jdouble)*8); 4576 movflt(Address(rsp,off++*sizeof(jdouble)),xmm0); 4577 movflt(Address(rsp,off++*sizeof(jdouble)),xmm1); 4578 movflt(Address(rsp,off++*sizeof(jdouble)),xmm2); 4579 movflt(Address(rsp,off++*sizeof(jdouble)),xmm3); 4580 movflt(Address(rsp,off++*sizeof(jdouble)),xmm4); 4581 movflt(Address(rsp,off++*sizeof(jdouble)),xmm5); 4582 movflt(Address(rsp,off++*sizeof(jdouble)),xmm6); 4583 movflt(Address(rsp,off++*sizeof(jdouble)),xmm7); 4584 } else if (UseSSE >= 2) { 4585 if (UseAVX > 2) { 4586 movl(rbx, 0xffff); 4587 #ifdef _LP64 4588 kmovql(k1, rbx); 4589 #else 4590 kmovdl(k1, rbx); 4591 #endif 4592 } 4593 #ifdef COMPILER2 4594 if (MaxVectorSize > 16) { 4595 assert(UseAVX > 0, "256bit vectors are supported only with AVX"); 4596 // Save upper half of YMM registes 4597 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); 4598 vextractf128h(Address(rsp, 0),xmm0); 4599 vextractf128h(Address(rsp, 16),xmm1); 4600 vextractf128h(Address(rsp, 32),xmm2); 4601 vextractf128h(Address(rsp, 48),xmm3); 4602 vextractf128h(Address(rsp, 64),xmm4); 4603 vextractf128h(Address(rsp, 80),xmm5); 4604 vextractf128h(Address(rsp, 96),xmm6); 4605 vextractf128h(Address(rsp,112),xmm7); 4606 #ifdef _LP64 4607 vextractf128h(Address(rsp,128),xmm8); 4608 vextractf128h(Address(rsp,144),xmm9); 4609 vextractf128h(Address(rsp,160),xmm10); 4610 vextractf128h(Address(rsp,176),xmm11); 4611 vextractf128h(Address(rsp,192),xmm12); 4612 vextractf128h(Address(rsp,208),xmm13); 4613 vextractf128h(Address(rsp,224),xmm14); 4614 vextractf128h(Address(rsp,240),xmm15); 4615 #endif 4616 } 4617 #endif 4618 // Save whole 128bit (16 bytes) XMM regiters 4619 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); 4620 movdqu(Address(rsp,off++*16),xmm0); 4621 movdqu(Address(rsp,off++*16),xmm1); 4622 movdqu(Address(rsp,off++*16),xmm2); 4623 movdqu(Address(rsp,off++*16),xmm3); 4624 movdqu(Address(rsp,off++*16),xmm4); 4625 movdqu(Address(rsp,off++*16),xmm5); 4626 movdqu(Address(rsp,off++*16),xmm6); 4627 movdqu(Address(rsp,off++*16),xmm7); 4628 #ifdef _LP64 4629 movdqu(Address(rsp,off++*16),xmm8); 4630 movdqu(Address(rsp,off++*16),xmm9); 4631 movdqu(Address(rsp,off++*16),xmm10); 4632 movdqu(Address(rsp,off++*16),xmm11); 4633 movdqu(Address(rsp,off++*16),xmm12); 4634 movdqu(Address(rsp,off++*16),xmm13); 4635 movdqu(Address(rsp,off++*16),xmm14); 4636 movdqu(Address(rsp,off++*16),xmm15); 4637 #endif 4638 } 4639 4640 // Preserve registers across runtime call 4641 int incoming_argument_and_return_value_offset = -1; 4642 if (num_fpu_regs_in_use > 1) { 4643 // Must preserve all other FPU regs (could alternatively convert 4644 // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash 4645 // FPU state, but can not trust C compiler) 4646 NEEDS_CLEANUP; 4647 // NOTE that in this case we also push the incoming argument(s) to 4648 // the stack and restore it later; we also use this stack slot to 4649 // hold the return value from dsin, dcos etc. 4650 for (int i = 0; i < num_fpu_regs_in_use; i++) { 4651 subptr(rsp, sizeof(jdouble)); 4652 fstp_d(Address(rsp, 0)); 4653 } 4654 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1); 4655 for (int i = nb_args-1; i >= 0; i--) { 4656 fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble))); 4657 } 4658 } 4659 4660 subptr(rsp, nb_args*sizeof(jdouble)); 4661 for (int i = 0; i < nb_args; i++) { 4662 fstp_d(Address(rsp, i*sizeof(jdouble))); 4663 } 4664 4665 #ifdef _LP64 4666 if (nb_args > 0) { 4667 movdbl(xmm0, Address(rsp, 0)); 4668 } 4669 if (nb_args > 1) { 4670 movdbl(xmm1, Address(rsp, sizeof(jdouble))); 4671 } 4672 assert(nb_args <= 2, "unsupported number of args"); 4673 #endif // _LP64 4674 4675 // NOTE: we must not use call_VM_leaf here because that requires a 4676 // complete interpreter frame in debug mode -- same bug as 4387334 4677 // MacroAssembler::call_VM_leaf_base is perfectly safe and will 4678 // do proper 64bit abi 4679 4680 NEEDS_CLEANUP; 4681 // Need to add stack banging before this runtime call if it needs to 4682 // be taken; however, there is no generic stack banging routine at 4683 // the MacroAssembler level 4684 4685 MacroAssembler::call_VM_leaf_base(runtime_entry, 0); 4686 4687 #ifdef _LP64 4688 movsd(Address(rsp, 0), xmm0); 4689 fld_d(Address(rsp, 0)); 4690 #endif // _LP64 4691 addptr(rsp, sizeof(jdouble) * nb_args); 4692 if (num_fpu_regs_in_use > 1) { 4693 // Must save return value to stack and then restore entire FPU 4694 // stack except incoming arguments 4695 fstp_d(Address(rsp, incoming_argument_and_return_value_offset)); 4696 for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) { 4697 fld_d(Address(rsp, 0)); 4698 addptr(rsp, sizeof(jdouble)); 4699 } 4700 fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble))); 4701 addptr(rsp, sizeof(jdouble) * nb_args); 4702 } 4703 4704 off = 0; 4705 if (UseSSE == 1) { 4706 movflt(xmm0, Address(rsp,off++*sizeof(jdouble))); 4707 movflt(xmm1, Address(rsp,off++*sizeof(jdouble))); 4708 movflt(xmm2, Address(rsp,off++*sizeof(jdouble))); 4709 movflt(xmm3, Address(rsp,off++*sizeof(jdouble))); 4710 movflt(xmm4, Address(rsp,off++*sizeof(jdouble))); 4711 movflt(xmm5, Address(rsp,off++*sizeof(jdouble))); 4712 movflt(xmm6, Address(rsp,off++*sizeof(jdouble))); 4713 movflt(xmm7, Address(rsp,off++*sizeof(jdouble))); 4714 addptr(rsp, sizeof(jdouble)*8); 4715 } else if (UseSSE >= 2) { 4716 // Restore whole 128bit (16 bytes) XMM regiters 4717 movdqu(xmm0, Address(rsp,off++*16)); 4718 movdqu(xmm1, Address(rsp,off++*16)); 4719 movdqu(xmm2, Address(rsp,off++*16)); 4720 movdqu(xmm3, Address(rsp,off++*16)); 4721 movdqu(xmm4, Address(rsp,off++*16)); 4722 movdqu(xmm5, Address(rsp,off++*16)); 4723 movdqu(xmm6, Address(rsp,off++*16)); 4724 movdqu(xmm7, Address(rsp,off++*16)); 4725 #ifdef _LP64 4726 movdqu(xmm8, Address(rsp,off++*16)); 4727 movdqu(xmm9, Address(rsp,off++*16)); 4728 movdqu(xmm10, Address(rsp,off++*16)); 4729 movdqu(xmm11, Address(rsp,off++*16)); 4730 movdqu(xmm12, Address(rsp,off++*16)); 4731 movdqu(xmm13, Address(rsp,off++*16)); 4732 movdqu(xmm14, Address(rsp,off++*16)); 4733 movdqu(xmm15, Address(rsp,off++*16)); 4734 #endif 4735 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); 4736 #ifdef COMPILER2 4737 if (MaxVectorSize > 16) { 4738 // Restore upper half of YMM registes. 4739 vinsertf128h(xmm0, Address(rsp, 0)); 4740 vinsertf128h(xmm1, Address(rsp, 16)); 4741 vinsertf128h(xmm2, Address(rsp, 32)); 4742 vinsertf128h(xmm3, Address(rsp, 48)); 4743 vinsertf128h(xmm4, Address(rsp, 64)); 4744 vinsertf128h(xmm5, Address(rsp, 80)); 4745 vinsertf128h(xmm6, Address(rsp, 96)); 4746 vinsertf128h(xmm7, Address(rsp,112)); 4747 #ifdef _LP64 4748 vinsertf128h(xmm8, Address(rsp,128)); 4749 vinsertf128h(xmm9, Address(rsp,144)); 4750 vinsertf128h(xmm10, Address(rsp,160)); 4751 vinsertf128h(xmm11, Address(rsp,176)); 4752 vinsertf128h(xmm12, Address(rsp,192)); 4753 vinsertf128h(xmm13, Address(rsp,208)); 4754 vinsertf128h(xmm14, Address(rsp,224)); 4755 vinsertf128h(xmm15, Address(rsp,240)); 4756 #endif 4757 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); 4758 } 4759 #endif 4760 } 4761 popa(); 4762 } 4763 4764 static const double pi_4 = 0.7853981633974483; 4765 4766 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) { 4767 // A hand-coded argument reduction for values in fabs(pi/4, pi/2) 4768 // was attempted in this code; unfortunately it appears that the 4769 // switch to 80-bit precision and back causes this to be 4770 // unprofitable compared with simply performing a runtime call if 4771 // the argument is out of the (-pi/4, pi/4) range. 4772 4773 Register tmp = noreg; 4774 if (!VM_Version::supports_cmov()) { 4775 // fcmp needs a temporary so preserve rbx, 4776 tmp = rbx; 4777 push(tmp); 4778 } 4779 4780 Label slow_case, done; 4781 4782 ExternalAddress pi4_adr = (address)&pi_4; 4783 if (reachable(pi4_adr)) { 4784 // x ?<= pi/4 4785 fld_d(pi4_adr); 4786 fld_s(1); // Stack: X PI/4 X 4787 fabs(); // Stack: |X| PI/4 X 4788 fcmp(tmp); 4789 jcc(Assembler::above, slow_case); 4790 4791 // fastest case: -pi/4 <= x <= pi/4 4792 switch(trig) { 4793 case 's': 4794 fsin(); 4795 break; 4796 case 'c': 4797 fcos(); 4798 break; 4799 case 't': 4800 ftan(); 4801 break; 4802 default: 4803 assert(false, "bad intrinsic"); 4804 break; 4805 } 4806 jmp(done); 4807 } 4808 4809 // slow case: runtime call 4810 bind(slow_case); 4811 4812 switch(trig) { 4813 case 's': 4814 { 4815 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use); 4816 } 4817 break; 4818 case 'c': 4819 { 4820 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use); 4821 } 4822 break; 4823 case 't': 4824 { 4825 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use); 4826 } 4827 break; 4828 default: 4829 assert(false, "bad intrinsic"); 4830 break; 4831 } 4832 4833 // Come here with result in F-TOS 4834 bind(done); 4835 4836 if (tmp != noreg) { 4837 pop(tmp); 4838 } 4839 } 4840 4841 4842 // Look up the method for a megamorphic invokeinterface call. 4843 // The target method is determined by <intf_klass, itable_index>. 4844 // The receiver klass is in recv_klass. 4845 // On success, the result will be in method_result, and execution falls through. 4846 // On failure, execution transfers to the given label. 4847 void MacroAssembler::lookup_interface_method(Register recv_klass, 4848 Register intf_klass, 4849 RegisterOrConstant itable_index, 4850 Register method_result, 4851 Register scan_temp, 4852 Label& L_no_such_interface) { 4853 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); 4854 assert(itable_index.is_constant() || itable_index.as_register() == method_result, 4855 "caller must use same register for non-constant itable index as for method"); 4856 4857 // Compute start of first itableOffsetEntry (which is at the end of the vtable) 4858 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize; 4859 int itentry_off = itableMethodEntry::method_offset_in_bytes(); 4860 int scan_step = itableOffsetEntry::size() * wordSize; 4861 int vte_size = vtableEntry::size() * wordSize; 4862 Address::ScaleFactor times_vte_scale = Address::times_ptr; 4863 assert(vte_size == wordSize, "else adjust times_vte_scale"); 4864 4865 movl(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize)); 4866 4867 // %%% Could store the aligned, prescaled offset in the klassoop. 4868 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); 4869 if (HeapWordsPerLong > 1) { 4870 // Round up to align_object_offset boundary 4871 // see code for InstanceKlass::start_of_itable! 4872 round_to(scan_temp, BytesPerLong); 4873 } 4874 4875 // Adjust recv_klass by scaled itable_index, so we can free itable_index. 4876 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); 4877 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); 4878 4879 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { 4880 // if (scan->interface() == intf) { 4881 // result = (klass + scan->offset() + itable_index); 4882 // } 4883 // } 4884 Label search, found_method; 4885 4886 for (int peel = 1; peel >= 0; peel--) { 4887 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); 4888 cmpptr(intf_klass, method_result); 4889 4890 if (peel) { 4891 jccb(Assembler::equal, found_method); 4892 } else { 4893 jccb(Assembler::notEqual, search); 4894 // (invert the test to fall through to found_method...) 4895 } 4896 4897 if (!peel) break; 4898 4899 bind(search); 4900 4901 // Check that the previous entry is non-null. A null entry means that 4902 // the receiver class doesn't implement the interface, and wasn't the 4903 // same as when the caller was compiled. 4904 testptr(method_result, method_result); 4905 jcc(Assembler::zero, L_no_such_interface); 4906 addptr(scan_temp, scan_step); 4907 } 4908 4909 bind(found_method); 4910 4911 // Got a hit. 4912 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); 4913 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); 4914 } 4915 4916 4917 // virtual method calling 4918 void MacroAssembler::lookup_virtual_method(Register recv_klass, 4919 RegisterOrConstant vtable_index, 4920 Register method_result) { 4921 const int base = InstanceKlass::vtable_start_offset() * wordSize; 4922 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below"); 4923 Address vtable_entry_addr(recv_klass, 4924 vtable_index, Address::times_ptr, 4925 base + vtableEntry::method_offset_in_bytes()); 4926 movptr(method_result, vtable_entry_addr); 4927 } 4928 4929 4930 void MacroAssembler::check_klass_subtype(Register sub_klass, 4931 Register super_klass, 4932 Register temp_reg, 4933 Label& L_success) { 4934 Label L_failure; 4935 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); 4936 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); 4937 bind(L_failure); 4938 } 4939 4940 4941 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, 4942 Register super_klass, 4943 Register temp_reg, 4944 Label* L_success, 4945 Label* L_failure, 4946 Label* L_slow_path, 4947 RegisterOrConstant super_check_offset) { 4948 assert_different_registers(sub_klass, super_klass, temp_reg); 4949 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); 4950 if (super_check_offset.is_register()) { 4951 assert_different_registers(sub_klass, super_klass, 4952 super_check_offset.as_register()); 4953 } else if (must_load_sco) { 4954 assert(temp_reg != noreg, "supply either a temp or a register offset"); 4955 } 4956 4957 Label L_fallthrough; 4958 int label_nulls = 0; 4959 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 4960 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 4961 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } 4962 assert(label_nulls <= 1, "at most one NULL in the batch"); 4963 4964 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 4965 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 4966 Address super_check_offset_addr(super_klass, sco_offset); 4967 4968 // Hacked jcc, which "knows" that L_fallthrough, at least, is in 4969 // range of a jccb. If this routine grows larger, reconsider at 4970 // least some of these. 4971 #define local_jcc(assembler_cond, label) \ 4972 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ 4973 else jcc( assembler_cond, label) /*omit semi*/ 4974 4975 // Hacked jmp, which may only be used just before L_fallthrough. 4976 #define final_jmp(label) \ 4977 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ 4978 else jmp(label) /*omit semi*/ 4979 4980 // If the pointers are equal, we are done (e.g., String[] elements). 4981 // This self-check enables sharing of secondary supertype arrays among 4982 // non-primary types such as array-of-interface. Otherwise, each such 4983 // type would need its own customized SSA. 4984 // We move this check to the front of the fast path because many 4985 // type checks are in fact trivially successful in this manner, 4986 // so we get a nicely predicted branch right at the start of the check. 4987 cmpptr(sub_klass, super_klass); 4988 local_jcc(Assembler::equal, *L_success); 4989 4990 // Check the supertype display: 4991 if (must_load_sco) { 4992 // Positive movl does right thing on LP64. 4993 movl(temp_reg, super_check_offset_addr); 4994 super_check_offset = RegisterOrConstant(temp_reg); 4995 } 4996 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); 4997 cmpptr(super_klass, super_check_addr); // load displayed supertype 4998 4999 // This check has worked decisively for primary supers. 5000 // Secondary supers are sought in the super_cache ('super_cache_addr'). 5001 // (Secondary supers are interfaces and very deeply nested subtypes.) 5002 // This works in the same check above because of a tricky aliasing 5003 // between the super_cache and the primary super display elements. 5004 // (The 'super_check_addr' can address either, as the case requires.) 5005 // Note that the cache is updated below if it does not help us find 5006 // what we need immediately. 5007 // So if it was a primary super, we can just fail immediately. 5008 // Otherwise, it's the slow path for us (no success at this point). 5009 5010 if (super_check_offset.is_register()) { 5011 local_jcc(Assembler::equal, *L_success); 5012 cmpl(super_check_offset.as_register(), sc_offset); 5013 if (L_failure == &L_fallthrough) { 5014 local_jcc(Assembler::equal, *L_slow_path); 5015 } else { 5016 local_jcc(Assembler::notEqual, *L_failure); 5017 final_jmp(*L_slow_path); 5018 } 5019 } else if (super_check_offset.as_constant() == sc_offset) { 5020 // Need a slow path; fast failure is impossible. 5021 if (L_slow_path == &L_fallthrough) { 5022 local_jcc(Assembler::equal, *L_success); 5023 } else { 5024 local_jcc(Assembler::notEqual, *L_slow_path); 5025 final_jmp(*L_success); 5026 } 5027 } else { 5028 // No slow path; it's a fast decision. 5029 if (L_failure == &L_fallthrough) { 5030 local_jcc(Assembler::equal, *L_success); 5031 } else { 5032 local_jcc(Assembler::notEqual, *L_failure); 5033 final_jmp(*L_success); 5034 } 5035 } 5036 5037 bind(L_fallthrough); 5038 5039 #undef local_jcc 5040 #undef final_jmp 5041 } 5042 5043 5044 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, 5045 Register super_klass, 5046 Register temp_reg, 5047 Register temp2_reg, 5048 Label* L_success, 5049 Label* L_failure, 5050 bool set_cond_codes) { 5051 assert_different_registers(sub_klass, super_klass, temp_reg); 5052 if (temp2_reg != noreg) 5053 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); 5054 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) 5055 5056 Label L_fallthrough; 5057 int label_nulls = 0; 5058 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 5059 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 5060 assert(label_nulls <= 1, "at most one NULL in the batch"); 5061 5062 // a couple of useful fields in sub_klass: 5063 int ss_offset = in_bytes(Klass::secondary_supers_offset()); 5064 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 5065 Address secondary_supers_addr(sub_klass, ss_offset); 5066 Address super_cache_addr( sub_klass, sc_offset); 5067 5068 // Do a linear scan of the secondary super-klass chain. 5069 // This code is rarely used, so simplicity is a virtue here. 5070 // The repne_scan instruction uses fixed registers, which we must spill. 5071 // Don't worry too much about pre-existing connections with the input regs. 5072 5073 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) 5074 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) 5075 5076 // Get super_klass value into rax (even if it was in rdi or rcx). 5077 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; 5078 if (super_klass != rax || UseCompressedOops) { 5079 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } 5080 mov(rax, super_klass); 5081 } 5082 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } 5083 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } 5084 5085 #ifndef PRODUCT 5086 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; 5087 ExternalAddress pst_counter_addr((address) pst_counter); 5088 NOT_LP64( incrementl(pst_counter_addr) ); 5089 LP64_ONLY( lea(rcx, pst_counter_addr) ); 5090 LP64_ONLY( incrementl(Address(rcx, 0)) ); 5091 #endif //PRODUCT 5092 5093 // We will consult the secondary-super array. 5094 movptr(rdi, secondary_supers_addr); 5095 // Load the array length. (Positive movl does right thing on LP64.) 5096 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes())); 5097 // Skip to start of data. 5098 addptr(rdi, Array<Klass*>::base_offset_in_bytes()); 5099 5100 // Scan RCX words at [RDI] for an occurrence of RAX. 5101 // Set NZ/Z based on last compare. 5102 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does 5103 // not change flags (only scas instruction which is repeated sets flags). 5104 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. 5105 5106 testptr(rax,rax); // Set Z = 0 5107 repne_scan(); 5108 5109 // Unspill the temp. registers: 5110 if (pushed_rdi) pop(rdi); 5111 if (pushed_rcx) pop(rcx); 5112 if (pushed_rax) pop(rax); 5113 5114 if (set_cond_codes) { 5115 // Special hack for the AD files: rdi is guaranteed non-zero. 5116 assert(!pushed_rdi, "rdi must be left non-NULL"); 5117 // Also, the condition codes are properly set Z/NZ on succeed/failure. 5118 } 5119 5120 if (L_failure == &L_fallthrough) 5121 jccb(Assembler::notEqual, *L_failure); 5122 else jcc(Assembler::notEqual, *L_failure); 5123 5124 // Success. Cache the super we found and proceed in triumph. 5125 movptr(super_cache_addr, super_klass); 5126 5127 if (L_success != &L_fallthrough) { 5128 jmp(*L_success); 5129 } 5130 5131 #undef IS_A_TEMP 5132 5133 bind(L_fallthrough); 5134 } 5135 5136 5137 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { 5138 if (VM_Version::supports_cmov()) { 5139 cmovl(cc, dst, src); 5140 } else { 5141 Label L; 5142 jccb(negate_condition(cc), L); 5143 movl(dst, src); 5144 bind(L); 5145 } 5146 } 5147 5148 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) { 5149 if (VM_Version::supports_cmov()) { 5150 cmovl(cc, dst, src); 5151 } else { 5152 Label L; 5153 jccb(negate_condition(cc), L); 5154 movl(dst, src); 5155 bind(L); 5156 } 5157 } 5158 5159 void MacroAssembler::verify_oop(Register reg, const char* s) { 5160 if (!VerifyOops) return; 5161 5162 // Pass register number to verify_oop_subroutine 5163 const char* b = NULL; 5164 { 5165 ResourceMark rm; 5166 stringStream ss; 5167 ss.print("verify_oop: %s: %s", reg->name(), s); 5168 b = code_string(ss.as_string()); 5169 } 5170 BLOCK_COMMENT("verify_oop {"); 5171 #ifdef _LP64 5172 push(rscratch1); // save r10, trashed by movptr() 5173 #endif 5174 push(rax); // save rax, 5175 push(reg); // pass register argument 5176 ExternalAddress buffer((address) b); 5177 // avoid using pushptr, as it modifies scratch registers 5178 // and our contract is not to modify anything 5179 movptr(rax, buffer.addr()); 5180 push(rax); 5181 // call indirectly to solve generation ordering problem 5182 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 5183 call(rax); 5184 // Caller pops the arguments (oop, message) and restores rax, r10 5185 BLOCK_COMMENT("} verify_oop"); 5186 } 5187 5188 5189 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, 5190 Register tmp, 5191 int offset) { 5192 intptr_t value = *delayed_value_addr; 5193 if (value != 0) 5194 return RegisterOrConstant(value + offset); 5195 5196 // load indirectly to solve generation ordering problem 5197 movptr(tmp, ExternalAddress((address) delayed_value_addr)); 5198 5199 #ifdef ASSERT 5200 { Label L; 5201 testptr(tmp, tmp); 5202 if (WizardMode) { 5203 const char* buf = NULL; 5204 { 5205 ResourceMark rm; 5206 stringStream ss; 5207 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]); 5208 buf = code_string(ss.as_string()); 5209 } 5210 jcc(Assembler::notZero, L); 5211 STOP(buf); 5212 } else { 5213 jccb(Assembler::notZero, L); 5214 hlt(); 5215 } 5216 bind(L); 5217 } 5218 #endif 5219 5220 if (offset != 0) 5221 addptr(tmp, offset); 5222 5223 return RegisterOrConstant(tmp); 5224 } 5225 5226 5227 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, 5228 int extra_slot_offset) { 5229 // cf. TemplateTable::prepare_invoke(), if (load_receiver). 5230 int stackElementSize = Interpreter::stackElementSize; 5231 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); 5232 #ifdef ASSERT 5233 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); 5234 assert(offset1 - offset == stackElementSize, "correct arithmetic"); 5235 #endif 5236 Register scale_reg = noreg; 5237 Address::ScaleFactor scale_factor = Address::no_scale; 5238 if (arg_slot.is_constant()) { 5239 offset += arg_slot.as_constant() * stackElementSize; 5240 } else { 5241 scale_reg = arg_slot.as_register(); 5242 scale_factor = Address::times(stackElementSize); 5243 } 5244 offset += wordSize; // return PC is on stack 5245 return Address(rsp, scale_reg, scale_factor, offset); 5246 } 5247 5248 5249 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { 5250 if (!VerifyOops) return; 5251 5252 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); 5253 // Pass register number to verify_oop_subroutine 5254 const char* b = NULL; 5255 { 5256 ResourceMark rm; 5257 stringStream ss; 5258 ss.print("verify_oop_addr: %s", s); 5259 b = code_string(ss.as_string()); 5260 } 5261 #ifdef _LP64 5262 push(rscratch1); // save r10, trashed by movptr() 5263 #endif 5264 push(rax); // save rax, 5265 // addr may contain rsp so we will have to adjust it based on the push 5266 // we just did (and on 64 bit we do two pushes) 5267 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which 5268 // stores rax into addr which is backwards of what was intended. 5269 if (addr.uses(rsp)) { 5270 lea(rax, addr); 5271 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord)); 5272 } else { 5273 pushptr(addr); 5274 } 5275 5276 ExternalAddress buffer((address) b); 5277 // pass msg argument 5278 // avoid using pushptr, as it modifies scratch registers 5279 // and our contract is not to modify anything 5280 movptr(rax, buffer.addr()); 5281 push(rax); 5282 5283 // call indirectly to solve generation ordering problem 5284 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 5285 call(rax); 5286 // Caller pops the arguments (addr, message) and restores rax, r10. 5287 } 5288 5289 void MacroAssembler::verify_tlab() { 5290 #ifdef ASSERT 5291 if (UseTLAB && VerifyOops) { 5292 Label next, ok; 5293 Register t1 = rsi; 5294 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); 5295 5296 push(t1); 5297 NOT_LP64(push(thread_reg)); 5298 NOT_LP64(get_thread(thread_reg)); 5299 5300 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 5301 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 5302 jcc(Assembler::aboveEqual, next); 5303 STOP("assert(top >= start)"); 5304 should_not_reach_here(); 5305 5306 bind(next); 5307 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 5308 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 5309 jcc(Assembler::aboveEqual, ok); 5310 STOP("assert(top <= end)"); 5311 should_not_reach_here(); 5312 5313 bind(ok); 5314 NOT_LP64(pop(thread_reg)); 5315 pop(t1); 5316 } 5317 #endif 5318 } 5319 5320 class ControlWord { 5321 public: 5322 int32_t _value; 5323 5324 int rounding_control() const { return (_value >> 10) & 3 ; } 5325 int precision_control() const { return (_value >> 8) & 3 ; } 5326 bool precision() const { return ((_value >> 5) & 1) != 0; } 5327 bool underflow() const { return ((_value >> 4) & 1) != 0; } 5328 bool overflow() const { return ((_value >> 3) & 1) != 0; } 5329 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 5330 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 5331 bool invalid() const { return ((_value >> 0) & 1) != 0; } 5332 5333 void print() const { 5334 // rounding control 5335 const char* rc; 5336 switch (rounding_control()) { 5337 case 0: rc = "round near"; break; 5338 case 1: rc = "round down"; break; 5339 case 2: rc = "round up "; break; 5340 case 3: rc = "chop "; break; 5341 }; 5342 // precision control 5343 const char* pc; 5344 switch (precision_control()) { 5345 case 0: pc = "24 bits "; break; 5346 case 1: pc = "reserved"; break; 5347 case 2: pc = "53 bits "; break; 5348 case 3: pc = "64 bits "; break; 5349 }; 5350 // flags 5351 char f[9]; 5352 f[0] = ' '; 5353 f[1] = ' '; 5354 f[2] = (precision ()) ? 'P' : 'p'; 5355 f[3] = (underflow ()) ? 'U' : 'u'; 5356 f[4] = (overflow ()) ? 'O' : 'o'; 5357 f[5] = (zero_divide ()) ? 'Z' : 'z'; 5358 f[6] = (denormalized()) ? 'D' : 'd'; 5359 f[7] = (invalid ()) ? 'I' : 'i'; 5360 f[8] = '\x0'; 5361 // output 5362 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); 5363 } 5364 5365 }; 5366 5367 class StatusWord { 5368 public: 5369 int32_t _value; 5370 5371 bool busy() const { return ((_value >> 15) & 1) != 0; } 5372 bool C3() const { return ((_value >> 14) & 1) != 0; } 5373 bool C2() const { return ((_value >> 10) & 1) != 0; } 5374 bool C1() const { return ((_value >> 9) & 1) != 0; } 5375 bool C0() const { return ((_value >> 8) & 1) != 0; } 5376 int top() const { return (_value >> 11) & 7 ; } 5377 bool error_status() const { return ((_value >> 7) & 1) != 0; } 5378 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } 5379 bool precision() const { return ((_value >> 5) & 1) != 0; } 5380 bool underflow() const { return ((_value >> 4) & 1) != 0; } 5381 bool overflow() const { return ((_value >> 3) & 1) != 0; } 5382 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 5383 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 5384 bool invalid() const { return ((_value >> 0) & 1) != 0; } 5385 5386 void print() const { 5387 // condition codes 5388 char c[5]; 5389 c[0] = (C3()) ? '3' : '-'; 5390 c[1] = (C2()) ? '2' : '-'; 5391 c[2] = (C1()) ? '1' : '-'; 5392 c[3] = (C0()) ? '0' : '-'; 5393 c[4] = '\x0'; 5394 // flags 5395 char f[9]; 5396 f[0] = (error_status()) ? 'E' : '-'; 5397 f[1] = (stack_fault ()) ? 'S' : '-'; 5398 f[2] = (precision ()) ? 'P' : '-'; 5399 f[3] = (underflow ()) ? 'U' : '-'; 5400 f[4] = (overflow ()) ? 'O' : '-'; 5401 f[5] = (zero_divide ()) ? 'Z' : '-'; 5402 f[6] = (denormalized()) ? 'D' : '-'; 5403 f[7] = (invalid ()) ? 'I' : '-'; 5404 f[8] = '\x0'; 5405 // output 5406 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); 5407 } 5408 5409 }; 5410 5411 class TagWord { 5412 public: 5413 int32_t _value; 5414 5415 int tag_at(int i) const { return (_value >> (i*2)) & 3; } 5416 5417 void print() const { 5418 printf("%04x", _value & 0xFFFF); 5419 } 5420 5421 }; 5422 5423 class FPU_Register { 5424 public: 5425 int32_t _m0; 5426 int32_t _m1; 5427 int16_t _ex; 5428 5429 bool is_indefinite() const { 5430 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; 5431 } 5432 5433 void print() const { 5434 char sign = (_ex < 0) ? '-' : '+'; 5435 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; 5436 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); 5437 }; 5438 5439 }; 5440 5441 class FPU_State { 5442 public: 5443 enum { 5444 register_size = 10, 5445 number_of_registers = 8, 5446 register_mask = 7 5447 }; 5448 5449 ControlWord _control_word; 5450 StatusWord _status_word; 5451 TagWord _tag_word; 5452 int32_t _error_offset; 5453 int32_t _error_selector; 5454 int32_t _data_offset; 5455 int32_t _data_selector; 5456 int8_t _register[register_size * number_of_registers]; 5457 5458 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } 5459 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } 5460 5461 const char* tag_as_string(int tag) const { 5462 switch (tag) { 5463 case 0: return "valid"; 5464 case 1: return "zero"; 5465 case 2: return "special"; 5466 case 3: return "empty"; 5467 } 5468 ShouldNotReachHere(); 5469 return NULL; 5470 } 5471 5472 void print() const { 5473 // print computation registers 5474 { int t = _status_word.top(); 5475 for (int i = 0; i < number_of_registers; i++) { 5476 int j = (i - t) & register_mask; 5477 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); 5478 st(j)->print(); 5479 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); 5480 } 5481 } 5482 printf("\n"); 5483 // print control registers 5484 printf("ctrl = "); _control_word.print(); printf("\n"); 5485 printf("stat = "); _status_word .print(); printf("\n"); 5486 printf("tags = "); _tag_word .print(); printf("\n"); 5487 } 5488 5489 }; 5490 5491 class Flag_Register { 5492 public: 5493 int32_t _value; 5494 5495 bool overflow() const { return ((_value >> 11) & 1) != 0; } 5496 bool direction() const { return ((_value >> 10) & 1) != 0; } 5497 bool sign() const { return ((_value >> 7) & 1) != 0; } 5498 bool zero() const { return ((_value >> 6) & 1) != 0; } 5499 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } 5500 bool parity() const { return ((_value >> 2) & 1) != 0; } 5501 bool carry() const { return ((_value >> 0) & 1) != 0; } 5502 5503 void print() const { 5504 // flags 5505 char f[8]; 5506 f[0] = (overflow ()) ? 'O' : '-'; 5507 f[1] = (direction ()) ? 'D' : '-'; 5508 f[2] = (sign ()) ? 'S' : '-'; 5509 f[3] = (zero ()) ? 'Z' : '-'; 5510 f[4] = (auxiliary_carry()) ? 'A' : '-'; 5511 f[5] = (parity ()) ? 'P' : '-'; 5512 f[6] = (carry ()) ? 'C' : '-'; 5513 f[7] = '\x0'; 5514 // output 5515 printf("%08x flags = %s", _value, f); 5516 } 5517 5518 }; 5519 5520 class IU_Register { 5521 public: 5522 int32_t _value; 5523 5524 void print() const { 5525 printf("%08x %11d", _value, _value); 5526 } 5527 5528 }; 5529 5530 class IU_State { 5531 public: 5532 Flag_Register _eflags; 5533 IU_Register _rdi; 5534 IU_Register _rsi; 5535 IU_Register _rbp; 5536 IU_Register _rsp; 5537 IU_Register _rbx; 5538 IU_Register _rdx; 5539 IU_Register _rcx; 5540 IU_Register _rax; 5541 5542 void print() const { 5543 // computation registers 5544 printf("rax, = "); _rax.print(); printf("\n"); 5545 printf("rbx, = "); _rbx.print(); printf("\n"); 5546 printf("rcx = "); _rcx.print(); printf("\n"); 5547 printf("rdx = "); _rdx.print(); printf("\n"); 5548 printf("rdi = "); _rdi.print(); printf("\n"); 5549 printf("rsi = "); _rsi.print(); printf("\n"); 5550 printf("rbp, = "); _rbp.print(); printf("\n"); 5551 printf("rsp = "); _rsp.print(); printf("\n"); 5552 printf("\n"); 5553 // control registers 5554 printf("flgs = "); _eflags.print(); printf("\n"); 5555 } 5556 }; 5557 5558 5559 class CPU_State { 5560 public: 5561 FPU_State _fpu_state; 5562 IU_State _iu_state; 5563 5564 void print() const { 5565 printf("--------------------------------------------------\n"); 5566 _iu_state .print(); 5567 printf("\n"); 5568 _fpu_state.print(); 5569 printf("--------------------------------------------------\n"); 5570 } 5571 5572 }; 5573 5574 5575 static void _print_CPU_state(CPU_State* state) { 5576 state->print(); 5577 }; 5578 5579 5580 void MacroAssembler::print_CPU_state() { 5581 push_CPU_state(); 5582 push(rsp); // pass CPU state 5583 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); 5584 addptr(rsp, wordSize); // discard argument 5585 pop_CPU_state(); 5586 } 5587 5588 5589 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { 5590 static int counter = 0; 5591 FPU_State* fs = &state->_fpu_state; 5592 counter++; 5593 // For leaf calls, only verify that the top few elements remain empty. 5594 // We only need 1 empty at the top for C2 code. 5595 if( stack_depth < 0 ) { 5596 if( fs->tag_for_st(7) != 3 ) { 5597 printf("FPR7 not empty\n"); 5598 state->print(); 5599 assert(false, "error"); 5600 return false; 5601 } 5602 return true; // All other stack states do not matter 5603 } 5604 5605 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, 5606 "bad FPU control word"); 5607 5608 // compute stack depth 5609 int i = 0; 5610 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; 5611 int d = i; 5612 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; 5613 // verify findings 5614 if (i != FPU_State::number_of_registers) { 5615 // stack not contiguous 5616 printf("%s: stack not contiguous at ST%d\n", s, i); 5617 state->print(); 5618 assert(false, "error"); 5619 return false; 5620 } 5621 // check if computed stack depth corresponds to expected stack depth 5622 if (stack_depth < 0) { 5623 // expected stack depth is -stack_depth or less 5624 if (d > -stack_depth) { 5625 // too many elements on the stack 5626 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); 5627 state->print(); 5628 assert(false, "error"); 5629 return false; 5630 } 5631 } else { 5632 // expected stack depth is stack_depth 5633 if (d != stack_depth) { 5634 // wrong stack depth 5635 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); 5636 state->print(); 5637 assert(false, "error"); 5638 return false; 5639 } 5640 } 5641 // everything is cool 5642 return true; 5643 } 5644 5645 5646 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { 5647 if (!VerifyFPU) return; 5648 push_CPU_state(); 5649 push(rsp); // pass CPU state 5650 ExternalAddress msg((address) s); 5651 // pass message string s 5652 pushptr(msg.addr()); 5653 push(stack_depth); // pass stack depth 5654 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); 5655 addptr(rsp, 3 * wordSize); // discard arguments 5656 // check for error 5657 { Label L; 5658 testl(rax, rax); 5659 jcc(Assembler::notZero, L); 5660 int3(); // break if error condition 5661 bind(L); 5662 } 5663 pop_CPU_state(); 5664 } 5665 5666 void MacroAssembler::restore_cpu_control_state_after_jni() { 5667 // Either restore the MXCSR register after returning from the JNI Call 5668 // or verify that it wasn't changed (with -Xcheck:jni flag). 5669 if (VM_Version::supports_sse()) { 5670 if (RestoreMXCSROnJNICalls) { 5671 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std())); 5672 } else if (CheckJNICalls) { 5673 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry())); 5674 } 5675 } 5676 if (VM_Version::supports_avx()) { 5677 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty. 5678 vzeroupper(); 5679 } 5680 5681 #ifndef _LP64 5682 // Either restore the x87 floating pointer control word after returning 5683 // from the JNI call or verify that it wasn't changed. 5684 if (CheckJNICalls) { 5685 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry())); 5686 } 5687 #endif // _LP64 5688 } 5689 5690 5691 void MacroAssembler::load_klass(Register dst, Register src) { 5692 #ifdef _LP64 5693 if (UseCompressedClassPointers) { 5694 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); 5695 decode_klass_not_null(dst); 5696 } else 5697 #endif 5698 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 5699 } 5700 5701 void MacroAssembler::load_prototype_header(Register dst, Register src) { 5702 load_klass(dst, src); 5703 movptr(dst, Address(dst, Klass::prototype_header_offset())); 5704 } 5705 5706 void MacroAssembler::store_klass(Register dst, Register src) { 5707 #ifdef _LP64 5708 if (UseCompressedClassPointers) { 5709 encode_klass_not_null(src); 5710 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); 5711 } else 5712 #endif 5713 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); 5714 } 5715 5716 void MacroAssembler::load_heap_oop(Register dst, Address src) { 5717 #ifdef _LP64 5718 // FIXME: Must change all places where we try to load the klass. 5719 if (UseCompressedOops) { 5720 movl(dst, src); 5721 decode_heap_oop(dst); 5722 } else 5723 #endif 5724 movptr(dst, src); 5725 } 5726 5727 // Doesn't do verfication, generates fixed size code 5728 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) { 5729 #ifdef _LP64 5730 if (UseCompressedOops) { 5731 movl(dst, src); 5732 decode_heap_oop_not_null(dst); 5733 } else 5734 #endif 5735 movptr(dst, src); 5736 } 5737 5738 void MacroAssembler::store_heap_oop(Address dst, Register src) { 5739 #ifdef _LP64 5740 if (UseCompressedOops) { 5741 assert(!dst.uses(src), "not enough registers"); 5742 encode_heap_oop(src); 5743 movl(dst, src); 5744 } else 5745 #endif 5746 movptr(dst, src); 5747 } 5748 5749 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) { 5750 assert_different_registers(src1, tmp); 5751 #ifdef _LP64 5752 if (UseCompressedOops) { 5753 bool did_push = false; 5754 if (tmp == noreg) { 5755 tmp = rax; 5756 push(tmp); 5757 did_push = true; 5758 assert(!src2.uses(rsp), "can't push"); 5759 } 5760 load_heap_oop(tmp, src2); 5761 cmpptr(src1, tmp); 5762 if (did_push) pop(tmp); 5763 } else 5764 #endif 5765 cmpptr(src1, src2); 5766 } 5767 5768 // Used for storing NULLs. 5769 void MacroAssembler::store_heap_oop_null(Address dst) { 5770 #ifdef _LP64 5771 if (UseCompressedOops) { 5772 movl(dst, (int32_t)NULL_WORD); 5773 } else { 5774 movslq(dst, (int32_t)NULL_WORD); 5775 } 5776 #else 5777 movl(dst, (int32_t)NULL_WORD); 5778 #endif 5779 } 5780 5781 #ifdef _LP64 5782 void MacroAssembler::store_klass_gap(Register dst, Register src) { 5783 if (UseCompressedClassPointers) { 5784 // Store to klass gap in destination 5785 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); 5786 } 5787 } 5788 5789 #ifdef ASSERT 5790 void MacroAssembler::verify_heapbase(const char* msg) { 5791 assert (UseCompressedOops, "should be compressed"); 5792 assert (Universe::heap() != NULL, "java heap should be initialized"); 5793 if (CheckCompressedOops) { 5794 Label ok; 5795 push(rscratch1); // cmpptr trashes rscratch1 5796 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 5797 jcc(Assembler::equal, ok); 5798 STOP(msg); 5799 bind(ok); 5800 pop(rscratch1); 5801 } 5802 } 5803 #endif 5804 5805 // Algorithm must match oop.inline.hpp encode_heap_oop. 5806 void MacroAssembler::encode_heap_oop(Register r) { 5807 #ifdef ASSERT 5808 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); 5809 #endif 5810 verify_oop(r, "broken oop in encode_heap_oop"); 5811 if (Universe::narrow_oop_base() == NULL) { 5812 if (Universe::narrow_oop_shift() != 0) { 5813 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 5814 shrq(r, LogMinObjAlignmentInBytes); 5815 } 5816 return; 5817 } 5818 testq(r, r); 5819 cmovq(Assembler::equal, r, r12_heapbase); 5820 subq(r, r12_heapbase); 5821 shrq(r, LogMinObjAlignmentInBytes); 5822 } 5823 5824 void MacroAssembler::encode_heap_oop_not_null(Register r) { 5825 #ifdef ASSERT 5826 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); 5827 if (CheckCompressedOops) { 5828 Label ok; 5829 testq(r, r); 5830 jcc(Assembler::notEqual, ok); 5831 STOP("null oop passed to encode_heap_oop_not_null"); 5832 bind(ok); 5833 } 5834 #endif 5835 verify_oop(r, "broken oop in encode_heap_oop_not_null"); 5836 if (Universe::narrow_oop_base() != NULL) { 5837 subq(r, r12_heapbase); 5838 } 5839 if (Universe::narrow_oop_shift() != 0) { 5840 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 5841 shrq(r, LogMinObjAlignmentInBytes); 5842 } 5843 } 5844 5845 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { 5846 #ifdef ASSERT 5847 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); 5848 if (CheckCompressedOops) { 5849 Label ok; 5850 testq(src, src); 5851 jcc(Assembler::notEqual, ok); 5852 STOP("null oop passed to encode_heap_oop_not_null2"); 5853 bind(ok); 5854 } 5855 #endif 5856 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); 5857 if (dst != src) { 5858 movq(dst, src); 5859 } 5860 if (Universe::narrow_oop_base() != NULL) { 5861 subq(dst, r12_heapbase); 5862 } 5863 if (Universe::narrow_oop_shift() != 0) { 5864 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 5865 shrq(dst, LogMinObjAlignmentInBytes); 5866 } 5867 } 5868 5869 void MacroAssembler::decode_heap_oop(Register r) { 5870 #ifdef ASSERT 5871 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); 5872 #endif 5873 if (Universe::narrow_oop_base() == NULL) { 5874 if (Universe::narrow_oop_shift() != 0) { 5875 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 5876 shlq(r, LogMinObjAlignmentInBytes); 5877 } 5878 } else { 5879 Label done; 5880 shlq(r, LogMinObjAlignmentInBytes); 5881 jccb(Assembler::equal, done); 5882 addq(r, r12_heapbase); 5883 bind(done); 5884 } 5885 verify_oop(r, "broken oop in decode_heap_oop"); 5886 } 5887 5888 void MacroAssembler::decode_heap_oop_not_null(Register r) { 5889 // Note: it will change flags 5890 assert (UseCompressedOops, "should only be used for compressed headers"); 5891 assert (Universe::heap() != NULL, "java heap should be initialized"); 5892 // Cannot assert, unverified entry point counts instructions (see .ad file) 5893 // vtableStubs also counts instructions in pd_code_size_limit. 5894 // Also do not verify_oop as this is called by verify_oop. 5895 if (Universe::narrow_oop_shift() != 0) { 5896 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 5897 shlq(r, LogMinObjAlignmentInBytes); 5898 if (Universe::narrow_oop_base() != NULL) { 5899 addq(r, r12_heapbase); 5900 } 5901 } else { 5902 assert (Universe::narrow_oop_base() == NULL, "sanity"); 5903 } 5904 } 5905 5906 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { 5907 // Note: it will change flags 5908 assert (UseCompressedOops, "should only be used for compressed headers"); 5909 assert (Universe::heap() != NULL, "java heap should be initialized"); 5910 // Cannot assert, unverified entry point counts instructions (see .ad file) 5911 // vtableStubs also counts instructions in pd_code_size_limit. 5912 // Also do not verify_oop as this is called by verify_oop. 5913 if (Universe::narrow_oop_shift() != 0) { 5914 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 5915 if (LogMinObjAlignmentInBytes == Address::times_8) { 5916 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); 5917 } else { 5918 if (dst != src) { 5919 movq(dst, src); 5920 } 5921 shlq(dst, LogMinObjAlignmentInBytes); 5922 if (Universe::narrow_oop_base() != NULL) { 5923 addq(dst, r12_heapbase); 5924 } 5925 } 5926 } else { 5927 assert (Universe::narrow_oop_base() == NULL, "sanity"); 5928 if (dst != src) { 5929 movq(dst, src); 5930 } 5931 } 5932 } 5933 5934 void MacroAssembler::encode_klass_not_null(Register r) { 5935 if (Universe::narrow_klass_base() != NULL) { 5936 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 5937 assert(r != r12_heapbase, "Encoding a klass in r12"); 5938 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); 5939 subq(r, r12_heapbase); 5940 } 5941 if (Universe::narrow_klass_shift() != 0) { 5942 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 5943 shrq(r, LogKlassAlignmentInBytes); 5944 } 5945 if (Universe::narrow_klass_base() != NULL) { 5946 reinit_heapbase(); 5947 } 5948 } 5949 5950 void MacroAssembler::encode_klass_not_null(Register dst, Register src) { 5951 if (dst == src) { 5952 encode_klass_not_null(src); 5953 } else { 5954 if (Universe::narrow_klass_base() != NULL) { 5955 mov64(dst, (int64_t)Universe::narrow_klass_base()); 5956 negq(dst); 5957 addq(dst, src); 5958 } else { 5959 movptr(dst, src); 5960 } 5961 if (Universe::narrow_klass_shift() != 0) { 5962 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 5963 shrq(dst, LogKlassAlignmentInBytes); 5964 } 5965 } 5966 } 5967 5968 // Function instr_size_for_decode_klass_not_null() counts the instructions 5969 // generated by decode_klass_not_null(register r) and reinit_heapbase(), 5970 // when (Universe::heap() != NULL). Hence, if the instructions they 5971 // generate change, then this method needs to be updated. 5972 int MacroAssembler::instr_size_for_decode_klass_not_null() { 5973 assert (UseCompressedClassPointers, "only for compressed klass ptrs"); 5974 if (Universe::narrow_klass_base() != NULL) { 5975 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()). 5976 return (Universe::narrow_klass_shift() == 0 ? 20 : 24); 5977 } else { 5978 // longest load decode klass function, mov64, leaq 5979 return 16; 5980 } 5981 } 5982 5983 // !!! If the instructions that get generated here change then function 5984 // instr_size_for_decode_klass_not_null() needs to get updated. 5985 void MacroAssembler::decode_klass_not_null(Register r) { 5986 // Note: it will change flags 5987 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 5988 assert(r != r12_heapbase, "Decoding a klass in r12"); 5989 // Cannot assert, unverified entry point counts instructions (see .ad file) 5990 // vtableStubs also counts instructions in pd_code_size_limit. 5991 // Also do not verify_oop as this is called by verify_oop. 5992 if (Universe::narrow_klass_shift() != 0) { 5993 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 5994 shlq(r, LogKlassAlignmentInBytes); 5995 } 5996 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 5997 if (Universe::narrow_klass_base() != NULL) { 5998 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); 5999 addq(r, r12_heapbase); 6000 reinit_heapbase(); 6001 } 6002 } 6003 6004 void MacroAssembler::decode_klass_not_null(Register dst, Register src) { 6005 // Note: it will change flags 6006 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6007 if (dst == src) { 6008 decode_klass_not_null(dst); 6009 } else { 6010 // Cannot assert, unverified entry point counts instructions (see .ad file) 6011 // vtableStubs also counts instructions in pd_code_size_limit. 6012 // Also do not verify_oop as this is called by verify_oop. 6013 mov64(dst, (int64_t)Universe::narrow_klass_base()); 6014 if (Universe::narrow_klass_shift() != 0) { 6015 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6016 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?"); 6017 leaq(dst, Address(dst, src, Address::times_8, 0)); 6018 } else { 6019 addq(dst, src); 6020 } 6021 } 6022 } 6023 6024 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { 6025 assert (UseCompressedOops, "should only be used for compressed headers"); 6026 assert (Universe::heap() != NULL, "java heap should be initialized"); 6027 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6028 int oop_index = oop_recorder()->find_index(obj); 6029 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6030 mov_narrow_oop(dst, oop_index, rspec); 6031 } 6032 6033 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { 6034 assert (UseCompressedOops, "should only be used for compressed headers"); 6035 assert (Universe::heap() != NULL, "java heap should be initialized"); 6036 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6037 int oop_index = oop_recorder()->find_index(obj); 6038 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6039 mov_narrow_oop(dst, oop_index, rspec); 6040 } 6041 6042 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { 6043 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6044 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6045 int klass_index = oop_recorder()->find_index(k); 6046 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6047 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); 6048 } 6049 6050 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) { 6051 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6052 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6053 int klass_index = oop_recorder()->find_index(k); 6054 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6055 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); 6056 } 6057 6058 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { 6059 assert (UseCompressedOops, "should only be used for compressed headers"); 6060 assert (Universe::heap() != NULL, "java heap should be initialized"); 6061 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6062 int oop_index = oop_recorder()->find_index(obj); 6063 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6064 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 6065 } 6066 6067 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { 6068 assert (UseCompressedOops, "should only be used for compressed headers"); 6069 assert (Universe::heap() != NULL, "java heap should be initialized"); 6070 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6071 int oop_index = oop_recorder()->find_index(obj); 6072 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6073 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 6074 } 6075 6076 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) { 6077 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6078 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6079 int klass_index = oop_recorder()->find_index(k); 6080 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6081 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); 6082 } 6083 6084 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) { 6085 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6086 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6087 int klass_index = oop_recorder()->find_index(k); 6088 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6089 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); 6090 } 6091 6092 void MacroAssembler::reinit_heapbase() { 6093 if (UseCompressedOops || UseCompressedClassPointers) { 6094 if (Universe::heap() != NULL) { 6095 if (Universe::narrow_oop_base() == NULL) { 6096 MacroAssembler::xorptr(r12_heapbase, r12_heapbase); 6097 } else { 6098 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base()); 6099 } 6100 } else { 6101 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 6102 } 6103 } 6104 } 6105 6106 #endif // _LP64 6107 6108 6109 // C2 compiled method's prolog code. 6110 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) { 6111 6112 // WARNING: Initial instruction MUST be 5 bytes or longer so that 6113 // NativeJump::patch_verified_entry will be able to patch out the entry 6114 // code safely. The push to verify stack depth is ok at 5 bytes, 6115 // the frame allocation can be either 3 or 6 bytes. So if we don't do 6116 // stack bang then we must use the 6 byte frame allocation even if 6117 // we have no frame. :-( 6118 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect"); 6119 6120 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 6121 // Remove word for return addr 6122 framesize -= wordSize; 6123 stack_bang_size -= wordSize; 6124 6125 // Calls to C2R adapters often do not accept exceptional returns. 6126 // We require that their callers must bang for them. But be careful, because 6127 // some VM calls (such as call site linkage) can use several kilobytes of 6128 // stack. But the stack safety zone should account for that. 6129 // See bugs 4446381, 4468289, 4497237. 6130 if (stack_bang_size > 0) { 6131 generate_stack_overflow_check(stack_bang_size); 6132 6133 // We always push rbp, so that on return to interpreter rbp, will be 6134 // restored correctly and we can correct the stack. 6135 push(rbp); 6136 // Save caller's stack pointer into RBP if the frame pointer is preserved. 6137 if (PreserveFramePointer) { 6138 mov(rbp, rsp); 6139 } 6140 // Remove word for ebp 6141 framesize -= wordSize; 6142 6143 // Create frame 6144 if (framesize) { 6145 subptr(rsp, framesize); 6146 } 6147 } else { 6148 // Create frame (force generation of a 4 byte immediate value) 6149 subptr_imm32(rsp, framesize); 6150 6151 // Save RBP register now. 6152 framesize -= wordSize; 6153 movptr(Address(rsp, framesize), rbp); 6154 // Save caller's stack pointer into RBP if the frame pointer is preserved. 6155 if (PreserveFramePointer) { 6156 movptr(rbp, rsp); 6157 addptr(rbp, framesize + wordSize); 6158 } 6159 } 6160 6161 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth 6162 framesize -= wordSize; 6163 movptr(Address(rsp, framesize), (int32_t)0xbadb100d); 6164 } 6165 6166 #ifndef _LP64 6167 // If method sets FPU control word do it now 6168 if (fp_mode_24b) { 6169 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 6170 } 6171 if (UseSSE >= 2 && VerifyFPU) { 6172 verify_FPU(0, "FPU stack must be clean on entry"); 6173 } 6174 #endif 6175 6176 #ifdef ASSERT 6177 if (VerifyStackAtCalls) { 6178 Label L; 6179 push(rax); 6180 mov(rax, rsp); 6181 andptr(rax, StackAlignmentInBytes-1); 6182 cmpptr(rax, StackAlignmentInBytes-wordSize); 6183 pop(rax); 6184 jcc(Assembler::equal, L); 6185 STOP("Stack is not properly aligned!"); 6186 bind(L); 6187 } 6188 #endif 6189 6190 } 6191 6192 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp) { 6193 // cnt - number of qwords (8-byte words). 6194 // base - start address, qword aligned. 6195 assert(base==rdi, "base register must be edi for rep stos"); 6196 assert(tmp==rax, "tmp register must be eax for rep stos"); 6197 assert(cnt==rcx, "cnt register must be ecx for rep stos"); 6198 6199 xorptr(tmp, tmp); 6200 if (UseFastStosb) { 6201 shlptr(cnt,3); // convert to number of bytes 6202 rep_stosb(); 6203 } else { 6204 NOT_LP64(shlptr(cnt,1);) // convert to number of dwords for 32-bit VM 6205 rep_stos(); 6206 } 6207 } 6208 6209 // IndexOf for constant substrings with size >= 8 chars 6210 // which don't need to be loaded through stack. 6211 void MacroAssembler::string_indexofC8(Register str1, Register str2, 6212 Register cnt1, Register cnt2, 6213 int int_cnt2, Register result, 6214 XMMRegister vec, Register tmp) { 6215 ShortBranchVerifier sbv(this); 6216 assert(UseSSE42Intrinsics, "SSE4.2 is required"); 6217 6218 // This method uses pcmpestri instruction with bound registers 6219 // inputs: 6220 // xmm - substring 6221 // rax - substring length (elements count) 6222 // mem - scanned string 6223 // rdx - string length (elements count) 6224 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 6225 // outputs: 6226 // rcx - matched index in string 6227 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 6228 6229 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, 6230 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR, 6231 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE; 6232 6233 // Note, inline_string_indexOf() generates checks: 6234 // if (substr.count > string.count) return -1; 6235 // if (substr.count == 0) return 0; 6236 assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars"); 6237 6238 // Load substring. 6239 movdqu(vec, Address(str2, 0)); 6240 movl(cnt2, int_cnt2); 6241 movptr(result, str1); // string addr 6242 6243 if (int_cnt2 > 8) { 6244 jmpb(SCAN_TO_SUBSTR); 6245 6246 // Reload substr for rescan, this code 6247 // is executed only for large substrings (> 8 chars) 6248 bind(RELOAD_SUBSTR); 6249 movdqu(vec, Address(str2, 0)); 6250 negptr(cnt2); // Jumped here with negative cnt2, convert to positive 6251 6252 bind(RELOAD_STR); 6253 // We came here after the beginning of the substring was 6254 // matched but the rest of it was not so we need to search 6255 // again. Start from the next element after the previous match. 6256 6257 // cnt2 is number of substring reminding elements and 6258 // cnt1 is number of string reminding elements when cmp failed. 6259 // Restored cnt1 = cnt1 - cnt2 + int_cnt2 6260 subl(cnt1, cnt2); 6261 addl(cnt1, int_cnt2); 6262 movl(cnt2, int_cnt2); // Now restore cnt2 6263 6264 decrementl(cnt1); // Shift to next element 6265 cmpl(cnt1, cnt2); 6266 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 6267 6268 addptr(result, 2); 6269 6270 } // (int_cnt2 > 8) 6271 6272 // Scan string for start of substr in 16-byte vectors 6273 bind(SCAN_TO_SUBSTR); 6274 pcmpestri(vec, Address(result, 0), 0x0d); 6275 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 6276 subl(cnt1, 8); 6277 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 6278 cmpl(cnt1, cnt2); 6279 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 6280 addptr(result, 16); 6281 jmpb(SCAN_TO_SUBSTR); 6282 6283 // Found a potential substr 6284 bind(FOUND_CANDIDATE); 6285 // Matched whole vector if first element matched (tmp(rcx) == 0). 6286 if (int_cnt2 == 8) { 6287 jccb(Assembler::overflow, RET_FOUND); // OF == 1 6288 } else { // int_cnt2 > 8 6289 jccb(Assembler::overflow, FOUND_SUBSTR); 6290 } 6291 // After pcmpestri tmp(rcx) contains matched element index 6292 // Compute start addr of substr 6293 lea(result, Address(result, tmp, Address::times_2)); 6294 6295 // Make sure string is still long enough 6296 subl(cnt1, tmp); 6297 cmpl(cnt1, cnt2); 6298 if (int_cnt2 == 8) { 6299 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 6300 } else { // int_cnt2 > 8 6301 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD); 6302 } 6303 // Left less then substring. 6304 6305 bind(RET_NOT_FOUND); 6306 movl(result, -1); 6307 jmpb(EXIT); 6308 6309 if (int_cnt2 > 8) { 6310 // This code is optimized for the case when whole substring 6311 // is matched if its head is matched. 6312 bind(MATCH_SUBSTR_HEAD); 6313 pcmpestri(vec, Address(result, 0), 0x0d); 6314 // Reload only string if does not match 6315 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0 6316 6317 Label CONT_SCAN_SUBSTR; 6318 // Compare the rest of substring (> 8 chars). 6319 bind(FOUND_SUBSTR); 6320 // First 8 chars are already matched. 6321 negptr(cnt2); 6322 addptr(cnt2, 8); 6323 6324 bind(SCAN_SUBSTR); 6325 subl(cnt1, 8); 6326 cmpl(cnt2, -8); // Do not read beyond substring 6327 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR); 6328 // Back-up strings to avoid reading beyond substring: 6329 // cnt1 = cnt1 - cnt2 + 8 6330 addl(cnt1, cnt2); // cnt2 is negative 6331 addl(cnt1, 8); 6332 movl(cnt2, 8); negptr(cnt2); 6333 bind(CONT_SCAN_SUBSTR); 6334 if (int_cnt2 < (int)G) { 6335 movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2)); 6336 pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d); 6337 } else { 6338 // calculate index in register to avoid integer overflow (int_cnt2*2) 6339 movl(tmp, int_cnt2); 6340 addptr(tmp, cnt2); 6341 movdqu(vec, Address(str2, tmp, Address::times_2, 0)); 6342 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d); 6343 } 6344 // Need to reload strings pointers if not matched whole vector 6345 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 6346 addptr(cnt2, 8); 6347 jcc(Assembler::negative, SCAN_SUBSTR); 6348 // Fall through if found full substring 6349 6350 } // (int_cnt2 > 8) 6351 6352 bind(RET_FOUND); 6353 // Found result if we matched full small substring. 6354 // Compute substr offset 6355 subptr(result, str1); 6356 shrl(result, 1); // index 6357 bind(EXIT); 6358 6359 } // string_indexofC8 6360 6361 // Small strings are loaded through stack if they cross page boundary. 6362 void MacroAssembler::string_indexof(Register str1, Register str2, 6363 Register cnt1, Register cnt2, 6364 int int_cnt2, Register result, 6365 XMMRegister vec, Register tmp) { 6366 ShortBranchVerifier sbv(this); 6367 assert(UseSSE42Intrinsics, "SSE4.2 is required"); 6368 // 6369 // int_cnt2 is length of small (< 8 chars) constant substring 6370 // or (-1) for non constant substring in which case its length 6371 // is in cnt2 register. 6372 // 6373 // Note, inline_string_indexOf() generates checks: 6374 // if (substr.count > string.count) return -1; 6375 // if (substr.count == 0) return 0; 6376 // 6377 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0"); 6378 6379 // This method uses pcmpestri instruction with bound registers 6380 // inputs: 6381 // xmm - substring 6382 // rax - substring length (elements count) 6383 // mem - scanned string 6384 // rdx - string length (elements count) 6385 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 6386 // outputs: 6387 // rcx - matched index in string 6388 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 6389 6390 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR, 6391 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR, 6392 FOUND_CANDIDATE; 6393 6394 { //======================================================== 6395 // We don't know where these strings are located 6396 // and we can't read beyond them. Load them through stack. 6397 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR; 6398 6399 movptr(tmp, rsp); // save old SP 6400 6401 if (int_cnt2 > 0) { // small (< 8 chars) constant substring 6402 if (int_cnt2 == 1) { // One char 6403 load_unsigned_short(result, Address(str2, 0)); 6404 movdl(vec, result); // move 32 bits 6405 } else if (int_cnt2 == 2) { // Two chars 6406 movdl(vec, Address(str2, 0)); // move 32 bits 6407 } else if (int_cnt2 == 4) { // Four chars 6408 movq(vec, Address(str2, 0)); // move 64 bits 6409 } else { // cnt2 = { 3, 5, 6, 7 } 6410 // Array header size is 12 bytes in 32-bit VM 6411 // + 6 bytes for 3 chars == 18 bytes, 6412 // enough space to load vec and shift. 6413 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity"); 6414 movdqu(vec, Address(str2, (int_cnt2*2)-16)); 6415 psrldq(vec, 16-(int_cnt2*2)); 6416 } 6417 } else { // not constant substring 6418 cmpl(cnt2, 8); 6419 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough 6420 6421 // We can read beyond string if srt+16 does not cross page boundary 6422 // since heaps are aligned and mapped by pages. 6423 assert(os::vm_page_size() < (int)G, "default page should be small"); 6424 movl(result, str2); // We need only low 32 bits 6425 andl(result, (os::vm_page_size()-1)); 6426 cmpl(result, (os::vm_page_size()-16)); 6427 jccb(Assembler::belowEqual, CHECK_STR); 6428 6429 // Move small strings to stack to allow load 16 bytes into vec. 6430 subptr(rsp, 16); 6431 int stk_offset = wordSize-2; 6432 push(cnt2); 6433 6434 bind(COPY_SUBSTR); 6435 load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2)); 6436 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result); 6437 decrement(cnt2); 6438 jccb(Assembler::notZero, COPY_SUBSTR); 6439 6440 pop(cnt2); 6441 movptr(str2, rsp); // New substring address 6442 } // non constant 6443 6444 bind(CHECK_STR); 6445 cmpl(cnt1, 8); 6446 jccb(Assembler::aboveEqual, BIG_STRINGS); 6447 6448 // Check cross page boundary. 6449 movl(result, str1); // We need only low 32 bits 6450 andl(result, (os::vm_page_size()-1)); 6451 cmpl(result, (os::vm_page_size()-16)); 6452 jccb(Assembler::belowEqual, BIG_STRINGS); 6453 6454 subptr(rsp, 16); 6455 int stk_offset = -2; 6456 if (int_cnt2 < 0) { // not constant 6457 push(cnt2); 6458 stk_offset += wordSize; 6459 } 6460 movl(cnt2, cnt1); 6461 6462 bind(COPY_STR); 6463 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2)); 6464 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result); 6465 decrement(cnt2); 6466 jccb(Assembler::notZero, COPY_STR); 6467 6468 if (int_cnt2 < 0) { // not constant 6469 pop(cnt2); 6470 } 6471 movptr(str1, rsp); // New string address 6472 6473 bind(BIG_STRINGS); 6474 // Load substring. 6475 if (int_cnt2 < 0) { // -1 6476 movdqu(vec, Address(str2, 0)); 6477 push(cnt2); // substr count 6478 push(str2); // substr addr 6479 push(str1); // string addr 6480 } else { 6481 // Small (< 8 chars) constant substrings are loaded already. 6482 movl(cnt2, int_cnt2); 6483 } 6484 push(tmp); // original SP 6485 6486 } // Finished loading 6487 6488 //======================================================== 6489 // Start search 6490 // 6491 6492 movptr(result, str1); // string addr 6493 6494 if (int_cnt2 < 0) { // Only for non constant substring 6495 jmpb(SCAN_TO_SUBSTR); 6496 6497 // SP saved at sp+0 6498 // String saved at sp+1*wordSize 6499 // Substr saved at sp+2*wordSize 6500 // Substr count saved at sp+3*wordSize 6501 6502 // Reload substr for rescan, this code 6503 // is executed only for large substrings (> 8 chars) 6504 bind(RELOAD_SUBSTR); 6505 movptr(str2, Address(rsp, 2*wordSize)); 6506 movl(cnt2, Address(rsp, 3*wordSize)); 6507 movdqu(vec, Address(str2, 0)); 6508 // We came here after the beginning of the substring was 6509 // matched but the rest of it was not so we need to search 6510 // again. Start from the next element after the previous match. 6511 subptr(str1, result); // Restore counter 6512 shrl(str1, 1); 6513 addl(cnt1, str1); 6514 decrementl(cnt1); // Shift to next element 6515 cmpl(cnt1, cnt2); 6516 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 6517 6518 addptr(result, 2); 6519 } // non constant 6520 6521 // Scan string for start of substr in 16-byte vectors 6522 bind(SCAN_TO_SUBSTR); 6523 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 6524 pcmpestri(vec, Address(result, 0), 0x0d); 6525 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 6526 subl(cnt1, 8); 6527 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 6528 cmpl(cnt1, cnt2); 6529 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 6530 addptr(result, 16); 6531 6532 bind(ADJUST_STR); 6533 cmpl(cnt1, 8); // Do not read beyond string 6534 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 6535 // Back-up string to avoid reading beyond string. 6536 lea(result, Address(result, cnt1, Address::times_2, -16)); 6537 movl(cnt1, 8); 6538 jmpb(SCAN_TO_SUBSTR); 6539 6540 // Found a potential substr 6541 bind(FOUND_CANDIDATE); 6542 // After pcmpestri tmp(rcx) contains matched element index 6543 6544 // Make sure string is still long enough 6545 subl(cnt1, tmp); 6546 cmpl(cnt1, cnt2); 6547 jccb(Assembler::greaterEqual, FOUND_SUBSTR); 6548 // Left less then substring. 6549 6550 bind(RET_NOT_FOUND); 6551 movl(result, -1); 6552 jmpb(CLEANUP); 6553 6554 bind(FOUND_SUBSTR); 6555 // Compute start addr of substr 6556 lea(result, Address(result, tmp, Address::times_2)); 6557 6558 if (int_cnt2 > 0) { // Constant substring 6559 // Repeat search for small substring (< 8 chars) 6560 // from new point without reloading substring. 6561 // Have to check that we don't read beyond string. 6562 cmpl(tmp, 8-int_cnt2); 6563 jccb(Assembler::greater, ADJUST_STR); 6564 // Fall through if matched whole substring. 6565 } else { // non constant 6566 assert(int_cnt2 == -1, "should be != 0"); 6567 6568 addl(tmp, cnt2); 6569 // Found result if we matched whole substring. 6570 cmpl(tmp, 8); 6571 jccb(Assembler::lessEqual, RET_FOUND); 6572 6573 // Repeat search for small substring (<= 8 chars) 6574 // from new point 'str1' without reloading substring. 6575 cmpl(cnt2, 8); 6576 // Have to check that we don't read beyond string. 6577 jccb(Assembler::lessEqual, ADJUST_STR); 6578 6579 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG; 6580 // Compare the rest of substring (> 8 chars). 6581 movptr(str1, result); 6582 6583 cmpl(tmp, cnt2); 6584 // First 8 chars are already matched. 6585 jccb(Assembler::equal, CHECK_NEXT); 6586 6587 bind(SCAN_SUBSTR); 6588 pcmpestri(vec, Address(str1, 0), 0x0d); 6589 // Need to reload strings pointers if not matched whole vector 6590 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 6591 6592 bind(CHECK_NEXT); 6593 subl(cnt2, 8); 6594 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring 6595 addptr(str1, 16); 6596 addptr(str2, 16); 6597 subl(cnt1, 8); 6598 cmpl(cnt2, 8); // Do not read beyond substring 6599 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR); 6600 // Back-up strings to avoid reading beyond substring. 6601 lea(str2, Address(str2, cnt2, Address::times_2, -16)); 6602 lea(str1, Address(str1, cnt2, Address::times_2, -16)); 6603 subl(cnt1, cnt2); 6604 movl(cnt2, 8); 6605 addl(cnt1, 8); 6606 bind(CONT_SCAN_SUBSTR); 6607 movdqu(vec, Address(str2, 0)); 6608 jmpb(SCAN_SUBSTR); 6609 6610 bind(RET_FOUND_LONG); 6611 movptr(str1, Address(rsp, wordSize)); 6612 } // non constant 6613 6614 bind(RET_FOUND); 6615 // Compute substr offset 6616 subptr(result, str1); 6617 shrl(result, 1); // index 6618 6619 bind(CLEANUP); 6620 pop(rsp); // restore SP 6621 6622 } // string_indexof 6623 6624 // Compare strings. 6625 void MacroAssembler::string_compare(Register str1, Register str2, 6626 Register cnt1, Register cnt2, Register result, 6627 XMMRegister vec1) { 6628 ShortBranchVerifier sbv(this); 6629 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; 6630 6631 // Compute the minimum of the string lengths and the 6632 // difference of the string lengths (stack). 6633 // Do the conditional move stuff 6634 movl(result, cnt1); 6635 subl(cnt1, cnt2); 6636 push(cnt1); 6637 cmov32(Assembler::lessEqual, cnt2, result); 6638 6639 // Is the minimum length zero? 6640 testl(cnt2, cnt2); 6641 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 6642 6643 // Compare first characters 6644 load_unsigned_short(result, Address(str1, 0)); 6645 load_unsigned_short(cnt1, Address(str2, 0)); 6646 subl(result, cnt1); 6647 jcc(Assembler::notZero, POP_LABEL); 6648 cmpl(cnt2, 1); 6649 jcc(Assembler::equal, LENGTH_DIFF_LABEL); 6650 6651 // Check if the strings start at the same location. 6652 cmpptr(str1, str2); 6653 jcc(Assembler::equal, LENGTH_DIFF_LABEL); 6654 6655 Address::ScaleFactor scale = Address::times_2; 6656 int stride = 8; 6657 6658 if (UseAVX >= 2 && UseSSE42Intrinsics) { 6659 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR; 6660 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR; 6661 Label COMPARE_TAIL_LONG; 6662 int pcmpmask = 0x19; 6663 6664 // Setup to compare 16-chars (32-bytes) vectors, 6665 // start from first character again because it has aligned address. 6666 int stride2 = 16; 6667 int adr_stride = stride << scale; 6668 6669 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); 6670 // rax and rdx are used by pcmpestri as elements counters 6671 movl(result, cnt2); 6672 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count 6673 jcc(Assembler::zero, COMPARE_TAIL_LONG); 6674 6675 // fast path : compare first 2 8-char vectors. 6676 bind(COMPARE_16_CHARS); 6677 movdqu(vec1, Address(str1, 0)); 6678 pcmpestri(vec1, Address(str2, 0), pcmpmask); 6679 jccb(Assembler::below, COMPARE_INDEX_CHAR); 6680 6681 movdqu(vec1, Address(str1, adr_stride)); 6682 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask); 6683 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS); 6684 addl(cnt1, stride); 6685 6686 // Compare the characters at index in cnt1 6687 bind(COMPARE_INDEX_CHAR); //cnt1 has the offset of the mismatching character 6688 load_unsigned_short(result, Address(str1, cnt1, scale)); 6689 load_unsigned_short(cnt2, Address(str2, cnt1, scale)); 6690 subl(result, cnt2); 6691 jmp(POP_LABEL); 6692 6693 // Setup the registers to start vector comparison loop 6694 bind(COMPARE_WIDE_VECTORS); 6695 lea(str1, Address(str1, result, scale)); 6696 lea(str2, Address(str2, result, scale)); 6697 subl(result, stride2); 6698 subl(cnt2, stride2); 6699 jccb(Assembler::zero, COMPARE_WIDE_TAIL); 6700 negptr(result); 6701 6702 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest) 6703 bind(COMPARE_WIDE_VECTORS_LOOP); 6704 vmovdqu(vec1, Address(str1, result, scale)); 6705 vpxor(vec1, Address(str2, result, scale)); 6706 vptest(vec1, vec1); 6707 jccb(Assembler::notZero, VECTOR_NOT_EQUAL); 6708 addptr(result, stride2); 6709 subl(cnt2, stride2); 6710 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP); 6711 // clean upper bits of YMM registers 6712 vpxor(vec1, vec1); 6713 6714 // compare wide vectors tail 6715 bind(COMPARE_WIDE_TAIL); 6716 testptr(result, result); 6717 jccb(Assembler::zero, LENGTH_DIFF_LABEL); 6718 6719 movl(result, stride2); 6720 movl(cnt2, result); 6721 negptr(result); 6722 jmpb(COMPARE_WIDE_VECTORS_LOOP); 6723 6724 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors. 6725 bind(VECTOR_NOT_EQUAL); 6726 // clean upper bits of YMM registers 6727 vpxor(vec1, vec1); 6728 lea(str1, Address(str1, result, scale)); 6729 lea(str2, Address(str2, result, scale)); 6730 jmp(COMPARE_16_CHARS); 6731 6732 // Compare tail chars, length between 1 to 15 chars 6733 bind(COMPARE_TAIL_LONG); 6734 movl(cnt2, result); 6735 cmpl(cnt2, stride); 6736 jccb(Assembler::less, COMPARE_SMALL_STR); 6737 6738 movdqu(vec1, Address(str1, 0)); 6739 pcmpestri(vec1, Address(str2, 0), pcmpmask); 6740 jcc(Assembler::below, COMPARE_INDEX_CHAR); 6741 subptr(cnt2, stride); 6742 jccb(Assembler::zero, LENGTH_DIFF_LABEL); 6743 lea(str1, Address(str1, result, scale)); 6744 lea(str2, Address(str2, result, scale)); 6745 negptr(cnt2); 6746 jmpb(WHILE_HEAD_LABEL); 6747 6748 bind(COMPARE_SMALL_STR); 6749 } else if (UseSSE42Intrinsics) { 6750 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL; 6751 int pcmpmask = 0x19; 6752 // Setup to compare 8-char (16-byte) vectors, 6753 // start from first character again because it has aligned address. 6754 movl(result, cnt2); 6755 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count 6756 jccb(Assembler::zero, COMPARE_TAIL); 6757 6758 lea(str1, Address(str1, result, scale)); 6759 lea(str2, Address(str2, result, scale)); 6760 negptr(result); 6761 6762 // pcmpestri 6763 // inputs: 6764 // vec1- substring 6765 // rax - negative string length (elements count) 6766 // mem - scanned string 6767 // rdx - string length (elements count) 6768 // pcmpmask - cmp mode: 11000 (string compare with negated result) 6769 // + 00 (unsigned bytes) or + 01 (unsigned shorts) 6770 // outputs: 6771 // rcx - first mismatched element index 6772 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); 6773 6774 bind(COMPARE_WIDE_VECTORS); 6775 movdqu(vec1, Address(str1, result, scale)); 6776 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 6777 // After pcmpestri cnt1(rcx) contains mismatched element index 6778 6779 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1 6780 addptr(result, stride); 6781 subptr(cnt2, stride); 6782 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS); 6783 6784 // compare wide vectors tail 6785 testptr(result, result); 6786 jccb(Assembler::zero, LENGTH_DIFF_LABEL); 6787 6788 movl(cnt2, stride); 6789 movl(result, stride); 6790 negptr(result); 6791 movdqu(vec1, Address(str1, result, scale)); 6792 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 6793 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL); 6794 6795 // Mismatched characters in the vectors 6796 bind(VECTOR_NOT_EQUAL); 6797 addptr(cnt1, result); 6798 load_unsigned_short(result, Address(str1, cnt1, scale)); 6799 load_unsigned_short(cnt2, Address(str2, cnt1, scale)); 6800 subl(result, cnt2); 6801 jmpb(POP_LABEL); 6802 6803 bind(COMPARE_TAIL); // limit is zero 6804 movl(cnt2, result); 6805 // Fallthru to tail compare 6806 } 6807 // Shift str2 and str1 to the end of the arrays, negate min 6808 lea(str1, Address(str1, cnt2, scale)); 6809 lea(str2, Address(str2, cnt2, scale)); 6810 decrementl(cnt2); // first character was compared already 6811 negptr(cnt2); 6812 6813 // Compare the rest of the elements 6814 bind(WHILE_HEAD_LABEL); 6815 load_unsigned_short(result, Address(str1, cnt2, scale, 0)); 6816 load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0)); 6817 subl(result, cnt1); 6818 jccb(Assembler::notZero, POP_LABEL); 6819 increment(cnt2); 6820 jccb(Assembler::notZero, WHILE_HEAD_LABEL); 6821 6822 // Strings are equal up to min length. Return the length difference. 6823 bind(LENGTH_DIFF_LABEL); 6824 pop(result); 6825 jmpb(DONE_LABEL); 6826 6827 // Discard the stored length difference 6828 bind(POP_LABEL); 6829 pop(cnt1); 6830 6831 // That's it 6832 bind(DONE_LABEL); 6833 } 6834 6835 // Compare char[] arrays aligned to 4 bytes or substrings. 6836 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, 6837 Register limit, Register result, Register chr, 6838 XMMRegister vec1, XMMRegister vec2) { 6839 ShortBranchVerifier sbv(this); 6840 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR; 6841 6842 int length_offset = arrayOopDesc::length_offset_in_bytes(); 6843 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); 6844 6845 // Check the input args 6846 cmpptr(ary1, ary2); 6847 jcc(Assembler::equal, TRUE_LABEL); 6848 6849 if (is_array_equ) { 6850 // Need additional checks for arrays_equals. 6851 testptr(ary1, ary1); 6852 jcc(Assembler::zero, FALSE_LABEL); 6853 testptr(ary2, ary2); 6854 jcc(Assembler::zero, FALSE_LABEL); 6855 6856 // Check the lengths 6857 movl(limit, Address(ary1, length_offset)); 6858 cmpl(limit, Address(ary2, length_offset)); 6859 jcc(Assembler::notEqual, FALSE_LABEL); 6860 } 6861 6862 // count == 0 6863 testl(limit, limit); 6864 jcc(Assembler::zero, TRUE_LABEL); 6865 6866 if (is_array_equ) { 6867 // Load array address 6868 lea(ary1, Address(ary1, base_offset)); 6869 lea(ary2, Address(ary2, base_offset)); 6870 } 6871 6872 shll(limit, 1); // byte count != 0 6873 movl(result, limit); // copy 6874 6875 if (UseAVX >= 2) { 6876 // With AVX2, use 32-byte vector compare 6877 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 6878 6879 // Compare 32-byte vectors 6880 andl(result, 0x0000001e); // tail count (in bytes) 6881 andl(limit, 0xffffffe0); // vector count (in bytes) 6882 jccb(Assembler::zero, COMPARE_TAIL); 6883 6884 lea(ary1, Address(ary1, limit, Address::times_1)); 6885 lea(ary2, Address(ary2, limit, Address::times_1)); 6886 negptr(limit); 6887 6888 bind(COMPARE_WIDE_VECTORS); 6889 vmovdqu(vec1, Address(ary1, limit, Address::times_1)); 6890 vmovdqu(vec2, Address(ary2, limit, Address::times_1)); 6891 vpxor(vec1, vec2); 6892 6893 vptest(vec1, vec1); 6894 jccb(Assembler::notZero, FALSE_LABEL); 6895 addptr(limit, 32); 6896 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 6897 6898 testl(result, result); 6899 jccb(Assembler::zero, TRUE_LABEL); 6900 6901 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32)); 6902 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32)); 6903 vpxor(vec1, vec2); 6904 6905 vptest(vec1, vec1); 6906 jccb(Assembler::notZero, FALSE_LABEL); 6907 jmpb(TRUE_LABEL); 6908 6909 bind(COMPARE_TAIL); // limit is zero 6910 movl(limit, result); 6911 // Fallthru to tail compare 6912 } else if (UseSSE42Intrinsics) { 6913 // With SSE4.2, use double quad vector compare 6914 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 6915 6916 // Compare 16-byte vectors 6917 andl(result, 0x0000000e); // tail count (in bytes) 6918 andl(limit, 0xfffffff0); // vector count (in bytes) 6919 jccb(Assembler::zero, COMPARE_TAIL); 6920 6921 lea(ary1, Address(ary1, limit, Address::times_1)); 6922 lea(ary2, Address(ary2, limit, Address::times_1)); 6923 negptr(limit); 6924 6925 bind(COMPARE_WIDE_VECTORS); 6926 movdqu(vec1, Address(ary1, limit, Address::times_1)); 6927 movdqu(vec2, Address(ary2, limit, Address::times_1)); 6928 pxor(vec1, vec2); 6929 6930 ptest(vec1, vec1); 6931 jccb(Assembler::notZero, FALSE_LABEL); 6932 addptr(limit, 16); 6933 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 6934 6935 testl(result, result); 6936 jccb(Assembler::zero, TRUE_LABEL); 6937 6938 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); 6939 movdqu(vec2, Address(ary2, result, Address::times_1, -16)); 6940 pxor(vec1, vec2); 6941 6942 ptest(vec1, vec1); 6943 jccb(Assembler::notZero, FALSE_LABEL); 6944 jmpb(TRUE_LABEL); 6945 6946 bind(COMPARE_TAIL); // limit is zero 6947 movl(limit, result); 6948 // Fallthru to tail compare 6949 } 6950 6951 // Compare 4-byte vectors 6952 andl(limit, 0xfffffffc); // vector count (in bytes) 6953 jccb(Assembler::zero, COMPARE_CHAR); 6954 6955 lea(ary1, Address(ary1, limit, Address::times_1)); 6956 lea(ary2, Address(ary2, limit, Address::times_1)); 6957 negptr(limit); 6958 6959 bind(COMPARE_VECTORS); 6960 movl(chr, Address(ary1, limit, Address::times_1)); 6961 cmpl(chr, Address(ary2, limit, Address::times_1)); 6962 jccb(Assembler::notEqual, FALSE_LABEL); 6963 addptr(limit, 4); 6964 jcc(Assembler::notZero, COMPARE_VECTORS); 6965 6966 // Compare trailing char (final 2 bytes), if any 6967 bind(COMPARE_CHAR); 6968 testl(result, 0x2); // tail char 6969 jccb(Assembler::zero, TRUE_LABEL); 6970 load_unsigned_short(chr, Address(ary1, 0)); 6971 load_unsigned_short(limit, Address(ary2, 0)); 6972 cmpl(chr, limit); 6973 jccb(Assembler::notEqual, FALSE_LABEL); 6974 6975 bind(TRUE_LABEL); 6976 movl(result, 1); // return true 6977 jmpb(DONE); 6978 6979 bind(FALSE_LABEL); 6980 xorl(result, result); // return false 6981 6982 // That's it 6983 bind(DONE); 6984 if (UseAVX >= 2) { 6985 // clean upper bits of YMM registers 6986 vpxor(vec1, vec1); 6987 vpxor(vec2, vec2); 6988 } 6989 } 6990 6991 void MacroAssembler::generate_fill(BasicType t, bool aligned, 6992 Register to, Register value, Register count, 6993 Register rtmp, XMMRegister xtmp) { 6994 ShortBranchVerifier sbv(this); 6995 assert_different_registers(to, value, count, rtmp); 6996 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; 6997 Label L_fill_2_bytes, L_fill_4_bytes; 6998 6999 int shift = -1; 7000 switch (t) { 7001 case T_BYTE: 7002 shift = 2; 7003 break; 7004 case T_SHORT: 7005 shift = 1; 7006 break; 7007 case T_INT: 7008 shift = 0; 7009 break; 7010 default: ShouldNotReachHere(); 7011 } 7012 7013 if (t == T_BYTE) { 7014 andl(value, 0xff); 7015 movl(rtmp, value); 7016 shll(rtmp, 8); 7017 orl(value, rtmp); 7018 } 7019 if (t == T_SHORT) { 7020 andl(value, 0xffff); 7021 } 7022 if (t == T_BYTE || t == T_SHORT) { 7023 movl(rtmp, value); 7024 shll(rtmp, 16); 7025 orl(value, rtmp); 7026 } 7027 7028 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element 7029 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp 7030 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { 7031 // align source address at 4 bytes address boundary 7032 if (t == T_BYTE) { 7033 // One byte misalignment happens only for byte arrays 7034 testptr(to, 1); 7035 jccb(Assembler::zero, L_skip_align1); 7036 movb(Address(to, 0), value); 7037 increment(to); 7038 decrement(count); 7039 BIND(L_skip_align1); 7040 } 7041 // Two bytes misalignment happens only for byte and short (char) arrays 7042 testptr(to, 2); 7043 jccb(Assembler::zero, L_skip_align2); 7044 movw(Address(to, 0), value); 7045 addptr(to, 2); 7046 subl(count, 1<<(shift-1)); 7047 BIND(L_skip_align2); 7048 } 7049 if (UseSSE < 2) { 7050 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 7051 // Fill 32-byte chunks 7052 subl(count, 8 << shift); 7053 jcc(Assembler::less, L_check_fill_8_bytes); 7054 align(16); 7055 7056 BIND(L_fill_32_bytes_loop); 7057 7058 for (int i = 0; i < 32; i += 4) { 7059 movl(Address(to, i), value); 7060 } 7061 7062 addptr(to, 32); 7063 subl(count, 8 << shift); 7064 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 7065 BIND(L_check_fill_8_bytes); 7066 addl(count, 8 << shift); 7067 jccb(Assembler::zero, L_exit); 7068 jmpb(L_fill_8_bytes); 7069 7070 // 7071 // length is too short, just fill qwords 7072 // 7073 BIND(L_fill_8_bytes_loop); 7074 movl(Address(to, 0), value); 7075 movl(Address(to, 4), value); 7076 addptr(to, 8); 7077 BIND(L_fill_8_bytes); 7078 subl(count, 1 << (shift + 1)); 7079 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 7080 // fall through to fill 4 bytes 7081 } else { 7082 Label L_fill_32_bytes; 7083 if (!UseUnalignedLoadStores) { 7084 // align to 8 bytes, we know we are 4 byte aligned to start 7085 testptr(to, 4); 7086 jccb(Assembler::zero, L_fill_32_bytes); 7087 movl(Address(to, 0), value); 7088 addptr(to, 4); 7089 subl(count, 1<<shift); 7090 } 7091 BIND(L_fill_32_bytes); 7092 { 7093 assert( UseSSE >= 2, "supported cpu only" ); 7094 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 7095 if (UseAVX > 2) { 7096 movl(rtmp, 0xffff); 7097 #ifdef _LP64 7098 kmovql(k1, rtmp); 7099 #else 7100 kmovdl(k1, rtmp); 7101 #endif 7102 } 7103 movdl(xtmp, value); 7104 if (UseAVX > 2 && UseUnalignedLoadStores) { 7105 // Fill 64-byte chunks 7106 Label L_fill_64_bytes_loop, L_check_fill_32_bytes; 7107 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit); 7108 7109 subl(count, 16 << shift); 7110 jcc(Assembler::less, L_check_fill_32_bytes); 7111 align(16); 7112 7113 BIND(L_fill_64_bytes_loop); 7114 evmovdqu(Address(to, 0), xtmp, Assembler::AVX_512bit); 7115 addptr(to, 64); 7116 subl(count, 16 << shift); 7117 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 7118 7119 BIND(L_check_fill_32_bytes); 7120 addl(count, 8 << shift); 7121 jccb(Assembler::less, L_check_fill_8_bytes); 7122 evmovdqu(Address(to, 0), xtmp, Assembler::AVX_256bit); 7123 addptr(to, 32); 7124 subl(count, 8 << shift); 7125 7126 BIND(L_check_fill_8_bytes); 7127 } else if (UseAVX == 2 && UseUnalignedLoadStores) { 7128 // Fill 64-byte chunks 7129 Label L_fill_64_bytes_loop, L_check_fill_32_bytes; 7130 vpbroadcastd(xtmp, xtmp); 7131 7132 subl(count, 16 << shift); 7133 jcc(Assembler::less, L_check_fill_32_bytes); 7134 align(16); 7135 7136 BIND(L_fill_64_bytes_loop); 7137 vmovdqu(Address(to, 0), xtmp); 7138 vmovdqu(Address(to, 32), xtmp); 7139 addptr(to, 64); 7140 subl(count, 16 << shift); 7141 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 7142 7143 BIND(L_check_fill_32_bytes); 7144 addl(count, 8 << shift); 7145 jccb(Assembler::less, L_check_fill_8_bytes); 7146 vmovdqu(Address(to, 0), xtmp); 7147 addptr(to, 32); 7148 subl(count, 8 << shift); 7149 7150 BIND(L_check_fill_8_bytes); 7151 // clean upper bits of YMM registers 7152 movdl(xtmp, value); 7153 pshufd(xtmp, xtmp, 0); 7154 } else { 7155 // Fill 32-byte chunks 7156 pshufd(xtmp, xtmp, 0); 7157 7158 subl(count, 8 << shift); 7159 jcc(Assembler::less, L_check_fill_8_bytes); 7160 align(16); 7161 7162 BIND(L_fill_32_bytes_loop); 7163 7164 if (UseUnalignedLoadStores) { 7165 movdqu(Address(to, 0), xtmp); 7166 movdqu(Address(to, 16), xtmp); 7167 } else { 7168 movq(Address(to, 0), xtmp); 7169 movq(Address(to, 8), xtmp); 7170 movq(Address(to, 16), xtmp); 7171 movq(Address(to, 24), xtmp); 7172 } 7173 7174 addptr(to, 32); 7175 subl(count, 8 << shift); 7176 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 7177 7178 BIND(L_check_fill_8_bytes); 7179 } 7180 addl(count, 8 << shift); 7181 jccb(Assembler::zero, L_exit); 7182 jmpb(L_fill_8_bytes); 7183 7184 // 7185 // length is too short, just fill qwords 7186 // 7187 BIND(L_fill_8_bytes_loop); 7188 movq(Address(to, 0), xtmp); 7189 addptr(to, 8); 7190 BIND(L_fill_8_bytes); 7191 subl(count, 1 << (shift + 1)); 7192 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 7193 } 7194 } 7195 // fill trailing 4 bytes 7196 BIND(L_fill_4_bytes); 7197 testl(count, 1<<shift); 7198 jccb(Assembler::zero, L_fill_2_bytes); 7199 movl(Address(to, 0), value); 7200 if (t == T_BYTE || t == T_SHORT) { 7201 addptr(to, 4); 7202 BIND(L_fill_2_bytes); 7203 // fill trailing 2 bytes 7204 testl(count, 1<<(shift-1)); 7205 jccb(Assembler::zero, L_fill_byte); 7206 movw(Address(to, 0), value); 7207 if (t == T_BYTE) { 7208 addptr(to, 2); 7209 BIND(L_fill_byte); 7210 // fill trailing byte 7211 testl(count, 1); 7212 jccb(Assembler::zero, L_exit); 7213 movb(Address(to, 0), value); 7214 } else { 7215 BIND(L_fill_byte); 7216 } 7217 } else { 7218 BIND(L_fill_2_bytes); 7219 } 7220 BIND(L_exit); 7221 } 7222 7223 // encode char[] to byte[] in ISO_8859_1 7224 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len, 7225 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 7226 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 7227 Register tmp5, Register result) { 7228 // rsi: src 7229 // rdi: dst 7230 // rdx: len 7231 // rcx: tmp5 7232 // rax: result 7233 ShortBranchVerifier sbv(this); 7234 assert_different_registers(src, dst, len, tmp5, result); 7235 Label L_done, L_copy_1_char, L_copy_1_char_exit; 7236 7237 // set result 7238 xorl(result, result); 7239 // check for zero length 7240 testl(len, len); 7241 jcc(Assembler::zero, L_done); 7242 movl(result, len); 7243 7244 // Setup pointers 7245 lea(src, Address(src, len, Address::times_2)); // char[] 7246 lea(dst, Address(dst, len, Address::times_1)); // byte[] 7247 negptr(len); 7248 7249 if (UseSSE42Intrinsics || UseAVX >= 2) { 7250 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit; 7251 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit; 7252 7253 if (UseAVX >= 2) { 7254 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit; 7255 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 7256 movdl(tmp1Reg, tmp5); 7257 vpbroadcastd(tmp1Reg, tmp1Reg); 7258 jmpb(L_chars_32_check); 7259 7260 bind(L_copy_32_chars); 7261 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64)); 7262 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32)); 7263 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 7264 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 7265 jccb(Assembler::notZero, L_copy_32_chars_exit); 7266 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 7267 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1); 7268 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg); 7269 7270 bind(L_chars_32_check); 7271 addptr(len, 32); 7272 jccb(Assembler::lessEqual, L_copy_32_chars); 7273 7274 bind(L_copy_32_chars_exit); 7275 subptr(len, 16); 7276 jccb(Assembler::greater, L_copy_16_chars_exit); 7277 7278 } else if (UseSSE42Intrinsics) { 7279 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 7280 movdl(tmp1Reg, tmp5); 7281 pshufd(tmp1Reg, tmp1Reg, 0); 7282 jmpb(L_chars_16_check); 7283 } 7284 7285 bind(L_copy_16_chars); 7286 if (UseAVX >= 2) { 7287 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32)); 7288 vptest(tmp2Reg, tmp1Reg); 7289 jccb(Assembler::notZero, L_copy_16_chars_exit); 7290 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1); 7291 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1); 7292 } else { 7293 if (UseAVX > 0) { 7294 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 7295 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 7296 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0); 7297 } else { 7298 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 7299 por(tmp2Reg, tmp3Reg); 7300 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 7301 por(tmp2Reg, tmp4Reg); 7302 } 7303 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 7304 jccb(Assembler::notZero, L_copy_16_chars_exit); 7305 packuswb(tmp3Reg, tmp4Reg); 7306 } 7307 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg); 7308 7309 bind(L_chars_16_check); 7310 addptr(len, 16); 7311 jccb(Assembler::lessEqual, L_copy_16_chars); 7312 7313 bind(L_copy_16_chars_exit); 7314 if (UseAVX >= 2) { 7315 // clean upper bits of YMM registers 7316 vpxor(tmp2Reg, tmp2Reg); 7317 vpxor(tmp3Reg, tmp3Reg); 7318 vpxor(tmp4Reg, tmp4Reg); 7319 movdl(tmp1Reg, tmp5); 7320 pshufd(tmp1Reg, tmp1Reg, 0); 7321 } 7322 subptr(len, 8); 7323 jccb(Assembler::greater, L_copy_8_chars_exit); 7324 7325 bind(L_copy_8_chars); 7326 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16)); 7327 ptest(tmp3Reg, tmp1Reg); 7328 jccb(Assembler::notZero, L_copy_8_chars_exit); 7329 packuswb(tmp3Reg, tmp1Reg); 7330 movq(Address(dst, len, Address::times_1, -8), tmp3Reg); 7331 addptr(len, 8); 7332 jccb(Assembler::lessEqual, L_copy_8_chars); 7333 7334 bind(L_copy_8_chars_exit); 7335 subptr(len, 8); 7336 jccb(Assembler::zero, L_done); 7337 } 7338 7339 bind(L_copy_1_char); 7340 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0)); 7341 testl(tmp5, 0xff00); // check if Unicode char 7342 jccb(Assembler::notZero, L_copy_1_char_exit); 7343 movb(Address(dst, len, Address::times_1, 0), tmp5); 7344 addptr(len, 1); 7345 jccb(Assembler::less, L_copy_1_char); 7346 7347 bind(L_copy_1_char_exit); 7348 addptr(result, len); // len is negative count of not processed elements 7349 bind(L_done); 7350 } 7351 7352 #ifdef _LP64 7353 /** 7354 * Helper for multiply_to_len(). 7355 */ 7356 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) { 7357 addq(dest_lo, src1); 7358 adcq(dest_hi, 0); 7359 addq(dest_lo, src2); 7360 adcq(dest_hi, 0); 7361 } 7362 7363 /** 7364 * Multiply 64 bit by 64 bit first loop. 7365 */ 7366 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 7367 Register y, Register y_idx, Register z, 7368 Register carry, Register product, 7369 Register idx, Register kdx) { 7370 // 7371 // jlong carry, x[], y[], z[]; 7372 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 7373 // huge_128 product = y[idx] * x[xstart] + carry; 7374 // z[kdx] = (jlong)product; 7375 // carry = (jlong)(product >>> 64); 7376 // } 7377 // z[xstart] = carry; 7378 // 7379 7380 Label L_first_loop, L_first_loop_exit; 7381 Label L_one_x, L_one_y, L_multiply; 7382 7383 decrementl(xstart); 7384 jcc(Assembler::negative, L_one_x); 7385 7386 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 7387 rorq(x_xstart, 32); // convert big-endian to little-endian 7388 7389 bind(L_first_loop); 7390 decrementl(idx); 7391 jcc(Assembler::negative, L_first_loop_exit); 7392 decrementl(idx); 7393 jcc(Assembler::negative, L_one_y); 7394 movq(y_idx, Address(y, idx, Address::times_4, 0)); 7395 rorq(y_idx, 32); // convert big-endian to little-endian 7396 bind(L_multiply); 7397 movq(product, x_xstart); 7398 mulq(y_idx); // product(rax) * y_idx -> rdx:rax 7399 addq(product, carry); 7400 adcq(rdx, 0); 7401 subl(kdx, 2); 7402 movl(Address(z, kdx, Address::times_4, 4), product); 7403 shrq(product, 32); 7404 movl(Address(z, kdx, Address::times_4, 0), product); 7405 movq(carry, rdx); 7406 jmp(L_first_loop); 7407 7408 bind(L_one_y); 7409 movl(y_idx, Address(y, 0)); 7410 jmp(L_multiply); 7411 7412 bind(L_one_x); 7413 movl(x_xstart, Address(x, 0)); 7414 jmp(L_first_loop); 7415 7416 bind(L_first_loop_exit); 7417 } 7418 7419 /** 7420 * Multiply 64 bit by 64 bit and add 128 bit. 7421 */ 7422 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z, 7423 Register yz_idx, Register idx, 7424 Register carry, Register product, int offset) { 7425 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry; 7426 // z[kdx] = (jlong)product; 7427 7428 movq(yz_idx, Address(y, idx, Address::times_4, offset)); 7429 rorq(yz_idx, 32); // convert big-endian to little-endian 7430 movq(product, x_xstart); 7431 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 7432 movq(yz_idx, Address(z, idx, Address::times_4, offset)); 7433 rorq(yz_idx, 32); // convert big-endian to little-endian 7434 7435 add2_with_carry(rdx, product, carry, yz_idx); 7436 7437 movl(Address(z, idx, Address::times_4, offset+4), product); 7438 shrq(product, 32); 7439 movl(Address(z, idx, Address::times_4, offset), product); 7440 7441 } 7442 7443 /** 7444 * Multiply 128 bit by 128 bit. Unrolled inner loop. 7445 */ 7446 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z, 7447 Register yz_idx, Register idx, Register jdx, 7448 Register carry, Register product, 7449 Register carry2) { 7450 // jlong carry, x[], y[], z[]; 7451 // int kdx = ystart+1; 7452 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 7453 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry; 7454 // z[kdx+idx+1] = (jlong)product; 7455 // jlong carry2 = (jlong)(product >>> 64); 7456 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2; 7457 // z[kdx+idx] = (jlong)product; 7458 // carry = (jlong)(product >>> 64); 7459 // } 7460 // idx += 2; 7461 // if (idx > 0) { 7462 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry; 7463 // z[kdx+idx] = (jlong)product; 7464 // carry = (jlong)(product >>> 64); 7465 // } 7466 // 7467 7468 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 7469 7470 movl(jdx, idx); 7471 andl(jdx, 0xFFFFFFFC); 7472 shrl(jdx, 2); 7473 7474 bind(L_third_loop); 7475 subl(jdx, 1); 7476 jcc(Assembler::negative, L_third_loop_exit); 7477 subl(idx, 4); 7478 7479 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8); 7480 movq(carry2, rdx); 7481 7482 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0); 7483 movq(carry, rdx); 7484 jmp(L_third_loop); 7485 7486 bind (L_third_loop_exit); 7487 7488 andl (idx, 0x3); 7489 jcc(Assembler::zero, L_post_third_loop_done); 7490 7491 Label L_check_1; 7492 subl(idx, 2); 7493 jcc(Assembler::negative, L_check_1); 7494 7495 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0); 7496 movq(carry, rdx); 7497 7498 bind (L_check_1); 7499 addl (idx, 0x2); 7500 andl (idx, 0x1); 7501 subl(idx, 1); 7502 jcc(Assembler::negative, L_post_third_loop_done); 7503 7504 movl(yz_idx, Address(y, idx, Address::times_4, 0)); 7505 movq(product, x_xstart); 7506 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 7507 movl(yz_idx, Address(z, idx, Address::times_4, 0)); 7508 7509 add2_with_carry(rdx, product, yz_idx, carry); 7510 7511 movl(Address(z, idx, Address::times_4, 0), product); 7512 shrq(product, 32); 7513 7514 shlq(rdx, 32); 7515 orq(product, rdx); 7516 movq(carry, product); 7517 7518 bind(L_post_third_loop_done); 7519 } 7520 7521 /** 7522 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop. 7523 * 7524 */ 7525 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z, 7526 Register carry, Register carry2, 7527 Register idx, Register jdx, 7528 Register yz_idx1, Register yz_idx2, 7529 Register tmp, Register tmp3, Register tmp4) { 7530 assert(UseBMI2Instructions, "should be used only when BMI2 is available"); 7531 7532 // jlong carry, x[], y[], z[]; 7533 // int kdx = ystart+1; 7534 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 7535 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry; 7536 // jlong carry2 = (jlong)(tmp3 >>> 64); 7537 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2; 7538 // carry = (jlong)(tmp4 >>> 64); 7539 // z[kdx+idx+1] = (jlong)tmp3; 7540 // z[kdx+idx] = (jlong)tmp4; 7541 // } 7542 // idx += 2; 7543 // if (idx > 0) { 7544 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry; 7545 // z[kdx+idx] = (jlong)yz_idx1; 7546 // carry = (jlong)(yz_idx1 >>> 64); 7547 // } 7548 // 7549 7550 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 7551 7552 movl(jdx, idx); 7553 andl(jdx, 0xFFFFFFFC); 7554 shrl(jdx, 2); 7555 7556 bind(L_third_loop); 7557 subl(jdx, 1); 7558 jcc(Assembler::negative, L_third_loop_exit); 7559 subl(idx, 4); 7560 7561 movq(yz_idx1, Address(y, idx, Address::times_4, 8)); 7562 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian 7563 movq(yz_idx2, Address(y, idx, Address::times_4, 0)); 7564 rorxq(yz_idx2, yz_idx2, 32); 7565 7566 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 7567 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp 7568 7569 movq(yz_idx1, Address(z, idx, Address::times_4, 8)); 7570 rorxq(yz_idx1, yz_idx1, 32); 7571 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 7572 rorxq(yz_idx2, yz_idx2, 32); 7573 7574 if (VM_Version::supports_adx()) { 7575 adcxq(tmp3, carry); 7576 adoxq(tmp3, yz_idx1); 7577 7578 adcxq(tmp4, tmp); 7579 adoxq(tmp4, yz_idx2); 7580 7581 movl(carry, 0); // does not affect flags 7582 adcxq(carry2, carry); 7583 adoxq(carry2, carry); 7584 } else { 7585 add2_with_carry(tmp4, tmp3, carry, yz_idx1); 7586 add2_with_carry(carry2, tmp4, tmp, yz_idx2); 7587 } 7588 movq(carry, carry2); 7589 7590 movl(Address(z, idx, Address::times_4, 12), tmp3); 7591 shrq(tmp3, 32); 7592 movl(Address(z, idx, Address::times_4, 8), tmp3); 7593 7594 movl(Address(z, idx, Address::times_4, 4), tmp4); 7595 shrq(tmp4, 32); 7596 movl(Address(z, idx, Address::times_4, 0), tmp4); 7597 7598 jmp(L_third_loop); 7599 7600 bind (L_third_loop_exit); 7601 7602 andl (idx, 0x3); 7603 jcc(Assembler::zero, L_post_third_loop_done); 7604 7605 Label L_check_1; 7606 subl(idx, 2); 7607 jcc(Assembler::negative, L_check_1); 7608 7609 movq(yz_idx1, Address(y, idx, Address::times_4, 0)); 7610 rorxq(yz_idx1, yz_idx1, 32); 7611 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 7612 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 7613 rorxq(yz_idx2, yz_idx2, 32); 7614 7615 add2_with_carry(tmp4, tmp3, carry, yz_idx2); 7616 7617 movl(Address(z, idx, Address::times_4, 4), tmp3); 7618 shrq(tmp3, 32); 7619 movl(Address(z, idx, Address::times_4, 0), tmp3); 7620 movq(carry, tmp4); 7621 7622 bind (L_check_1); 7623 addl (idx, 0x2); 7624 andl (idx, 0x1); 7625 subl(idx, 1); 7626 jcc(Assembler::negative, L_post_third_loop_done); 7627 movl(tmp4, Address(y, idx, Address::times_4, 0)); 7628 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3 7629 movl(tmp4, Address(z, idx, Address::times_4, 0)); 7630 7631 add2_with_carry(carry2, tmp3, tmp4, carry); 7632 7633 movl(Address(z, idx, Address::times_4, 0), tmp3); 7634 shrq(tmp3, 32); 7635 7636 shlq(carry2, 32); 7637 orq(tmp3, carry2); 7638 movq(carry, tmp3); 7639 7640 bind(L_post_third_loop_done); 7641 } 7642 7643 /** 7644 * Code for BigInteger::multiplyToLen() instrinsic. 7645 * 7646 * rdi: x 7647 * rax: xlen 7648 * rsi: y 7649 * rcx: ylen 7650 * r8: z 7651 * r11: zlen 7652 * r12: tmp1 7653 * r13: tmp2 7654 * r14: tmp3 7655 * r15: tmp4 7656 * rbx: tmp5 7657 * 7658 */ 7659 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen, 7660 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) { 7661 ShortBranchVerifier sbv(this); 7662 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx); 7663 7664 push(tmp1); 7665 push(tmp2); 7666 push(tmp3); 7667 push(tmp4); 7668 push(tmp5); 7669 7670 push(xlen); 7671 push(zlen); 7672 7673 const Register idx = tmp1; 7674 const Register kdx = tmp2; 7675 const Register xstart = tmp3; 7676 7677 const Register y_idx = tmp4; 7678 const Register carry = tmp5; 7679 const Register product = xlen; 7680 const Register x_xstart = zlen; // reuse register 7681 7682 // First Loop. 7683 // 7684 // final static long LONG_MASK = 0xffffffffL; 7685 // int xstart = xlen - 1; 7686 // int ystart = ylen - 1; 7687 // long carry = 0; 7688 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 7689 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry; 7690 // z[kdx] = (int)product; 7691 // carry = product >>> 32; 7692 // } 7693 // z[xstart] = (int)carry; 7694 // 7695 7696 movl(idx, ylen); // idx = ylen; 7697 movl(kdx, zlen); // kdx = xlen+ylen; 7698 xorq(carry, carry); // carry = 0; 7699 7700 Label L_done; 7701 7702 movl(xstart, xlen); 7703 decrementl(xstart); 7704 jcc(Assembler::negative, L_done); 7705 7706 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx); 7707 7708 Label L_second_loop; 7709 testl(kdx, kdx); 7710 jcc(Assembler::zero, L_second_loop); 7711 7712 Label L_carry; 7713 subl(kdx, 1); 7714 jcc(Assembler::zero, L_carry); 7715 7716 movl(Address(z, kdx, Address::times_4, 0), carry); 7717 shrq(carry, 32); 7718 subl(kdx, 1); 7719 7720 bind(L_carry); 7721 movl(Address(z, kdx, Address::times_4, 0), carry); 7722 7723 // Second and third (nested) loops. 7724 // 7725 // for (int i = xstart-1; i >= 0; i--) { // Second loop 7726 // carry = 0; 7727 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop 7728 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) + 7729 // (z[k] & LONG_MASK) + carry; 7730 // z[k] = (int)product; 7731 // carry = product >>> 32; 7732 // } 7733 // z[i] = (int)carry; 7734 // } 7735 // 7736 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx 7737 7738 const Register jdx = tmp1; 7739 7740 bind(L_second_loop); 7741 xorl(carry, carry); // carry = 0; 7742 movl(jdx, ylen); // j = ystart+1 7743 7744 subl(xstart, 1); // i = xstart-1; 7745 jcc(Assembler::negative, L_done); 7746 7747 push (z); 7748 7749 Label L_last_x; 7750 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j 7751 subl(xstart, 1); // i = xstart-1; 7752 jcc(Assembler::negative, L_last_x); 7753 7754 if (UseBMI2Instructions) { 7755 movq(rdx, Address(x, xstart, Address::times_4, 0)); 7756 rorxq(rdx, rdx, 32); // convert big-endian to little-endian 7757 } else { 7758 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 7759 rorq(x_xstart, 32); // convert big-endian to little-endian 7760 } 7761 7762 Label L_third_loop_prologue; 7763 bind(L_third_loop_prologue); 7764 7765 push (x); 7766 push (xstart); 7767 push (ylen); 7768 7769 7770 if (UseBMI2Instructions) { 7771 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4); 7772 } else { // !UseBMI2Instructions 7773 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x); 7774 } 7775 7776 pop(ylen); 7777 pop(xlen); 7778 pop(x); 7779 pop(z); 7780 7781 movl(tmp3, xlen); 7782 addl(tmp3, 1); 7783 movl(Address(z, tmp3, Address::times_4, 0), carry); 7784 subl(tmp3, 1); 7785 jccb(Assembler::negative, L_done); 7786 7787 shrq(carry, 32); 7788 movl(Address(z, tmp3, Address::times_4, 0), carry); 7789 jmp(L_second_loop); 7790 7791 // Next infrequent code is moved outside loops. 7792 bind(L_last_x); 7793 if (UseBMI2Instructions) { 7794 movl(rdx, Address(x, 0)); 7795 } else { 7796 movl(x_xstart, Address(x, 0)); 7797 } 7798 jmp(L_third_loop_prologue); 7799 7800 bind(L_done); 7801 7802 pop(zlen); 7803 pop(xlen); 7804 7805 pop(tmp5); 7806 pop(tmp4); 7807 pop(tmp3); 7808 pop(tmp2); 7809 pop(tmp1); 7810 } 7811 7812 //Helper functions for square_to_len() 7813 7814 /** 7815 * Store the squares of x[], right shifted one bit (divided by 2) into z[] 7816 * Preserves x and z and modifies rest of the registers. 7817 */ 7818 7819 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 7820 // Perform square and right shift by 1 7821 // Handle odd xlen case first, then for even xlen do the following 7822 // jlong carry = 0; 7823 // for (int j=0, i=0; j < xlen; j+=2, i+=4) { 7824 // huge_128 product = x[j:j+1] * x[j:j+1]; 7825 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65); 7826 // z[i+2:i+3] = (jlong)(product >>> 1); 7827 // carry = (jlong)product; 7828 // } 7829 7830 xorq(tmp5, tmp5); // carry 7831 xorq(rdxReg, rdxReg); 7832 xorl(tmp1, tmp1); // index for x 7833 xorl(tmp4, tmp4); // index for z 7834 7835 Label L_first_loop, L_first_loop_exit; 7836 7837 testl(xlen, 1); 7838 jccb(Assembler::zero, L_first_loop); //jump if xlen is even 7839 7840 // Square and right shift by 1 the odd element using 32 bit multiply 7841 movl(raxReg, Address(x, tmp1, Address::times_4, 0)); 7842 imulq(raxReg, raxReg); 7843 shrq(raxReg, 1); 7844 adcq(tmp5, 0); 7845 movq(Address(z, tmp4, Address::times_4, 0), raxReg); 7846 incrementl(tmp1); 7847 addl(tmp4, 2); 7848 7849 // Square and right shift by 1 the rest using 64 bit multiply 7850 bind(L_first_loop); 7851 cmpptr(tmp1, xlen); 7852 jccb(Assembler::equal, L_first_loop_exit); 7853 7854 // Square 7855 movq(raxReg, Address(x, tmp1, Address::times_4, 0)); 7856 rorq(raxReg, 32); // convert big-endian to little-endian 7857 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax 7858 7859 // Right shift by 1 and save carry 7860 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1 7861 rcrq(rdxReg, 1); 7862 rcrq(raxReg, 1); 7863 adcq(tmp5, 0); 7864 7865 // Store result in z 7866 movq(Address(z, tmp4, Address::times_4, 0), rdxReg); 7867 movq(Address(z, tmp4, Address::times_4, 8), raxReg); 7868 7869 // Update indices for x and z 7870 addl(tmp1, 2); 7871 addl(tmp4, 4); 7872 jmp(L_first_loop); 7873 7874 bind(L_first_loop_exit); 7875 } 7876 7877 7878 /** 7879 * Perform the following multiply add operation using BMI2 instructions 7880 * carry:sum = sum + op1*op2 + carry 7881 * op2 should be in rdx 7882 * op2 is preserved, all other registers are modified 7883 */ 7884 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) { 7885 // assert op2 is rdx 7886 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1 7887 addq(sum, carry); 7888 adcq(tmp2, 0); 7889 addq(sum, op1); 7890 adcq(tmp2, 0); 7891 movq(carry, tmp2); 7892 } 7893 7894 /** 7895 * Perform the following multiply add operation: 7896 * carry:sum = sum + op1*op2 + carry 7897 * Preserves op1, op2 and modifies rest of registers 7898 */ 7899 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) { 7900 // rdx:rax = op1 * op2 7901 movq(raxReg, op2); 7902 mulq(op1); 7903 7904 // rdx:rax = sum + carry + rdx:rax 7905 addq(sum, carry); 7906 adcq(rdxReg, 0); 7907 addq(sum, raxReg); 7908 adcq(rdxReg, 0); 7909 7910 // carry:sum = rdx:sum 7911 movq(carry, rdxReg); 7912 } 7913 7914 /** 7915 * Add 64 bit long carry into z[] with carry propogation. 7916 * Preserves z and carry register values and modifies rest of registers. 7917 * 7918 */ 7919 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) { 7920 Label L_fourth_loop, L_fourth_loop_exit; 7921 7922 movl(tmp1, 1); 7923 subl(zlen, 2); 7924 addq(Address(z, zlen, Address::times_4, 0), carry); 7925 7926 bind(L_fourth_loop); 7927 jccb(Assembler::carryClear, L_fourth_loop_exit); 7928 subl(zlen, 2); 7929 jccb(Assembler::negative, L_fourth_loop_exit); 7930 addq(Address(z, zlen, Address::times_4, 0), tmp1); 7931 jmp(L_fourth_loop); 7932 bind(L_fourth_loop_exit); 7933 } 7934 7935 /** 7936 * Shift z[] left by 1 bit. 7937 * Preserves x, len, z and zlen registers and modifies rest of the registers. 7938 * 7939 */ 7940 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) { 7941 7942 Label L_fifth_loop, L_fifth_loop_exit; 7943 7944 // Fifth loop 7945 // Perform primitiveLeftShift(z, zlen, 1) 7946 7947 const Register prev_carry = tmp1; 7948 const Register new_carry = tmp4; 7949 const Register value = tmp2; 7950 const Register zidx = tmp3; 7951 7952 // int zidx, carry; 7953 // long value; 7954 // carry = 0; 7955 // for (zidx = zlen-2; zidx >=0; zidx -= 2) { 7956 // (carry:value) = (z[i] << 1) | carry ; 7957 // z[i] = value; 7958 // } 7959 7960 movl(zidx, zlen); 7961 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register 7962 7963 bind(L_fifth_loop); 7964 decl(zidx); // Use decl to preserve carry flag 7965 decl(zidx); 7966 jccb(Assembler::negative, L_fifth_loop_exit); 7967 7968 if (UseBMI2Instructions) { 7969 movq(value, Address(z, zidx, Address::times_4, 0)); 7970 rclq(value, 1); 7971 rorxq(value, value, 32); 7972 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 7973 } 7974 else { 7975 // clear new_carry 7976 xorl(new_carry, new_carry); 7977 7978 // Shift z[i] by 1, or in previous carry and save new carry 7979 movq(value, Address(z, zidx, Address::times_4, 0)); 7980 shlq(value, 1); 7981 adcl(new_carry, 0); 7982 7983 orq(value, prev_carry); 7984 rorq(value, 0x20); 7985 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 7986 7987 // Set previous carry = new carry 7988 movl(prev_carry, new_carry); 7989 } 7990 jmp(L_fifth_loop); 7991 7992 bind(L_fifth_loop_exit); 7993 } 7994 7995 7996 /** 7997 * Code for BigInteger::squareToLen() intrinsic 7998 * 7999 * rdi: x 8000 * rsi: len 8001 * r8: z 8002 * rcx: zlen 8003 * r12: tmp1 8004 * r13: tmp2 8005 * r14: tmp3 8006 * r15: tmp4 8007 * rbx: tmp5 8008 * 8009 */ 8010 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 8011 8012 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply; 8013 push(tmp1); 8014 push(tmp2); 8015 push(tmp3); 8016 push(tmp4); 8017 push(tmp5); 8018 8019 // First loop 8020 // Store the squares, right shifted one bit (i.e., divided by 2). 8021 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg); 8022 8023 // Add in off-diagonal sums. 8024 // 8025 // Second, third (nested) and fourth loops. 8026 // zlen +=2; 8027 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) { 8028 // carry = 0; 8029 // long op2 = x[xidx:xidx+1]; 8030 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) { 8031 // k -= 2; 8032 // long op1 = x[j:j+1]; 8033 // long sum = z[k:k+1]; 8034 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs); 8035 // z[k:k+1] = sum; 8036 // } 8037 // add_one_64(z, k, carry, tmp_regs); 8038 // } 8039 8040 const Register carry = tmp5; 8041 const Register sum = tmp3; 8042 const Register op1 = tmp4; 8043 Register op2 = tmp2; 8044 8045 push(zlen); 8046 push(len); 8047 addl(zlen,2); 8048 bind(L_second_loop); 8049 xorq(carry, carry); 8050 subl(zlen, 4); 8051 subl(len, 2); 8052 push(zlen); 8053 push(len); 8054 cmpl(len, 0); 8055 jccb(Assembler::lessEqual, L_second_loop_exit); 8056 8057 // Multiply an array by one 64 bit long. 8058 if (UseBMI2Instructions) { 8059 op2 = rdxReg; 8060 movq(op2, Address(x, len, Address::times_4, 0)); 8061 rorxq(op2, op2, 32); 8062 } 8063 else { 8064 movq(op2, Address(x, len, Address::times_4, 0)); 8065 rorq(op2, 32); 8066 } 8067 8068 bind(L_third_loop); 8069 decrementl(len); 8070 jccb(Assembler::negative, L_third_loop_exit); 8071 decrementl(len); 8072 jccb(Assembler::negative, L_last_x); 8073 8074 movq(op1, Address(x, len, Address::times_4, 0)); 8075 rorq(op1, 32); 8076 8077 bind(L_multiply); 8078 subl(zlen, 2); 8079 movq(sum, Address(z, zlen, Address::times_4, 0)); 8080 8081 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry. 8082 if (UseBMI2Instructions) { 8083 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2); 8084 } 8085 else { 8086 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 8087 } 8088 8089 movq(Address(z, zlen, Address::times_4, 0), sum); 8090 8091 jmp(L_third_loop); 8092 bind(L_third_loop_exit); 8093 8094 // Fourth loop 8095 // Add 64 bit long carry into z with carry propogation. 8096 // Uses offsetted zlen. 8097 add_one_64(z, zlen, carry, tmp1); 8098 8099 pop(len); 8100 pop(zlen); 8101 jmp(L_second_loop); 8102 8103 // Next infrequent code is moved outside loops. 8104 bind(L_last_x); 8105 movl(op1, Address(x, 0)); 8106 jmp(L_multiply); 8107 8108 bind(L_second_loop_exit); 8109 pop(len); 8110 pop(zlen); 8111 pop(len); 8112 pop(zlen); 8113 8114 // Fifth loop 8115 // Shift z left 1 bit. 8116 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4); 8117 8118 // z[zlen-1] |= x[len-1] & 1; 8119 movl(tmp3, Address(x, len, Address::times_4, -4)); 8120 andl(tmp3, 1); 8121 orl(Address(z, zlen, Address::times_4, -4), tmp3); 8122 8123 pop(tmp5); 8124 pop(tmp4); 8125 pop(tmp3); 8126 pop(tmp2); 8127 pop(tmp1); 8128 } 8129 8130 /** 8131 * Helper function for mul_add() 8132 * Multiply the in[] by int k and add to out[] starting at offset offs using 8133 * 128 bit by 32 bit multiply and return the carry in tmp5. 8134 * Only quad int aligned length of in[] is operated on in this function. 8135 * k is in rdxReg for BMI2Instructions, for others it is in tmp2. 8136 * This function preserves out, in and k registers. 8137 * len and offset point to the appropriate index in "in" & "out" correspondingly 8138 * tmp5 has the carry. 8139 * other registers are temporary and are modified. 8140 * 8141 */ 8142 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in, 8143 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3, 8144 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 8145 8146 Label L_first_loop, L_first_loop_exit; 8147 8148 movl(tmp1, len); 8149 shrl(tmp1, 2); 8150 8151 bind(L_first_loop); 8152 subl(tmp1, 1); 8153 jccb(Assembler::negative, L_first_loop_exit); 8154 8155 subl(len, 4); 8156 subl(offset, 4); 8157 8158 Register op2 = tmp2; 8159 const Register sum = tmp3; 8160 const Register op1 = tmp4; 8161 const Register carry = tmp5; 8162 8163 if (UseBMI2Instructions) { 8164 op2 = rdxReg; 8165 } 8166 8167 movq(op1, Address(in, len, Address::times_4, 8)); 8168 rorq(op1, 32); 8169 movq(sum, Address(out, offset, Address::times_4, 8)); 8170 rorq(sum, 32); 8171 if (UseBMI2Instructions) { 8172 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 8173 } 8174 else { 8175 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 8176 } 8177 // Store back in big endian from little endian 8178 rorq(sum, 0x20); 8179 movq(Address(out, offset, Address::times_4, 8), sum); 8180 8181 movq(op1, Address(in, len, Address::times_4, 0)); 8182 rorq(op1, 32); 8183 movq(sum, Address(out, offset, Address::times_4, 0)); 8184 rorq(sum, 32); 8185 if (UseBMI2Instructions) { 8186 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 8187 } 8188 else { 8189 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 8190 } 8191 // Store back in big endian from little endian 8192 rorq(sum, 0x20); 8193 movq(Address(out, offset, Address::times_4, 0), sum); 8194 8195 jmp(L_first_loop); 8196 bind(L_first_loop_exit); 8197 } 8198 8199 /** 8200 * Code for BigInteger::mulAdd() intrinsic 8201 * 8202 * rdi: out 8203 * rsi: in 8204 * r11: offs (out.length - offset) 8205 * rcx: len 8206 * r8: k 8207 * r12: tmp1 8208 * r13: tmp2 8209 * r14: tmp3 8210 * r15: tmp4 8211 * rbx: tmp5 8212 * Multiply the in[] by word k and add to out[], return the carry in rax 8213 */ 8214 void MacroAssembler::mul_add(Register out, Register in, Register offs, 8215 Register len, Register k, Register tmp1, Register tmp2, Register tmp3, 8216 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 8217 8218 Label L_carry, L_last_in, L_done; 8219 8220 // carry = 0; 8221 // for (int j=len-1; j >= 0; j--) { 8222 // long product = (in[j] & LONG_MASK) * kLong + 8223 // (out[offs] & LONG_MASK) + carry; 8224 // out[offs--] = (int)product; 8225 // carry = product >>> 32; 8226 // } 8227 // 8228 push(tmp1); 8229 push(tmp2); 8230 push(tmp3); 8231 push(tmp4); 8232 push(tmp5); 8233 8234 Register op2 = tmp2; 8235 const Register sum = tmp3; 8236 const Register op1 = tmp4; 8237 const Register carry = tmp5; 8238 8239 if (UseBMI2Instructions) { 8240 op2 = rdxReg; 8241 movl(op2, k); 8242 } 8243 else { 8244 movl(op2, k); 8245 } 8246 8247 xorq(carry, carry); 8248 8249 //First loop 8250 8251 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply 8252 //The carry is in tmp5 8253 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg); 8254 8255 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any 8256 decrementl(len); 8257 jccb(Assembler::negative, L_carry); 8258 decrementl(len); 8259 jccb(Assembler::negative, L_last_in); 8260 8261 movq(op1, Address(in, len, Address::times_4, 0)); 8262 rorq(op1, 32); 8263 8264 subl(offs, 2); 8265 movq(sum, Address(out, offs, Address::times_4, 0)); 8266 rorq(sum, 32); 8267 8268 if (UseBMI2Instructions) { 8269 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 8270 } 8271 else { 8272 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 8273 } 8274 8275 // Store back in big endian from little endian 8276 rorq(sum, 0x20); 8277 movq(Address(out, offs, Address::times_4, 0), sum); 8278 8279 testl(len, len); 8280 jccb(Assembler::zero, L_carry); 8281 8282 //Multiply the last in[] entry, if any 8283 bind(L_last_in); 8284 movl(op1, Address(in, 0)); 8285 movl(sum, Address(out, offs, Address::times_4, -4)); 8286 8287 movl(raxReg, k); 8288 mull(op1); //tmp4 * eax -> edx:eax 8289 addl(sum, carry); 8290 adcl(rdxReg, 0); 8291 addl(sum, raxReg); 8292 adcl(rdxReg, 0); 8293 movl(carry, rdxReg); 8294 8295 movl(Address(out, offs, Address::times_4, -4), sum); 8296 8297 bind(L_carry); 8298 //return tmp5/carry as carry in rax 8299 movl(rax, carry); 8300 8301 bind(L_done); 8302 pop(tmp5); 8303 pop(tmp4); 8304 pop(tmp3); 8305 pop(tmp2); 8306 pop(tmp1); 8307 } 8308 #endif 8309 8310 /** 8311 * Emits code to update CRC-32 with a byte value according to constants in table 8312 * 8313 * @param [in,out]crc Register containing the crc. 8314 * @param [in]val Register containing the byte to fold into the CRC. 8315 * @param [in]table Register containing the table of crc constants. 8316 * 8317 * uint32_t crc; 8318 * val = crc_table[(val ^ crc) & 0xFF]; 8319 * crc = val ^ (crc >> 8); 8320 * 8321 */ 8322 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { 8323 xorl(val, crc); 8324 andl(val, 0xFF); 8325 shrl(crc, 8); // unsigned shift 8326 xorl(crc, Address(table, val, Address::times_4, 0)); 8327 } 8328 8329 /** 8330 * Fold 128-bit data chunk 8331 */ 8332 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) { 8333 if (UseAVX > 0) { 8334 vpclmulhdq(xtmp, xK, xcrc); // [123:64] 8335 vpclmulldq(xcrc, xK, xcrc); // [63:0] 8336 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */); 8337 pxor(xcrc, xtmp); 8338 } else { 8339 movdqa(xtmp, xcrc); 8340 pclmulhdq(xtmp, xK); // [123:64] 8341 pclmulldq(xcrc, xK); // [63:0] 8342 pxor(xcrc, xtmp); 8343 movdqu(xtmp, Address(buf, offset)); 8344 pxor(xcrc, xtmp); 8345 } 8346 } 8347 8348 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) { 8349 if (UseAVX > 0) { 8350 vpclmulhdq(xtmp, xK, xcrc); 8351 vpclmulldq(xcrc, xK, xcrc); 8352 pxor(xcrc, xbuf); 8353 pxor(xcrc, xtmp); 8354 } else { 8355 movdqa(xtmp, xcrc); 8356 pclmulhdq(xtmp, xK); 8357 pclmulldq(xcrc, xK); 8358 pxor(xcrc, xbuf); 8359 pxor(xcrc, xtmp); 8360 } 8361 } 8362 8363 /** 8364 * 8-bit folds to compute 32-bit CRC 8365 * 8366 * uint64_t xcrc; 8367 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8); 8368 */ 8369 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) { 8370 movdl(tmp, xcrc); 8371 andl(tmp, 0xFF); 8372 movdl(xtmp, Address(table, tmp, Address::times_4, 0)); 8373 psrldq(xcrc, 1); // unsigned shift one byte 8374 pxor(xcrc, xtmp); 8375 } 8376 8377 /** 8378 * uint32_t crc; 8379 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8); 8380 */ 8381 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) { 8382 movl(tmp, crc); 8383 andl(tmp, 0xFF); 8384 shrl(crc, 8); 8385 xorl(crc, Address(table, tmp, Address::times_4, 0)); 8386 } 8387 8388 /** 8389 * @param crc register containing existing CRC (32-bit) 8390 * @param buf register pointing to input byte buffer (byte*) 8391 * @param len register containing number of bytes 8392 * @param table register that will contain address of CRC table 8393 * @param tmp scratch register 8394 */ 8395 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) { 8396 assert_different_registers(crc, buf, len, table, tmp, rax); 8397 8398 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned; 8399 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop; 8400 8401 lea(table, ExternalAddress(StubRoutines::crc_table_addr())); 8402 notl(crc); // ~crc 8403 cmpl(len, 16); 8404 jcc(Assembler::less, L_tail); 8405 8406 // Align buffer to 16 bytes 8407 movl(tmp, buf); 8408 andl(tmp, 0xF); 8409 jccb(Assembler::zero, L_aligned); 8410 subl(tmp, 16); 8411 addl(len, tmp); 8412 8413 align(4); 8414 BIND(L_align_loop); 8415 movsbl(rax, Address(buf, 0)); // load byte with sign extension 8416 update_byte_crc32(crc, rax, table); 8417 increment(buf); 8418 incrementl(tmp); 8419 jccb(Assembler::less, L_align_loop); 8420 8421 BIND(L_aligned); 8422 movl(tmp, len); // save 8423 shrl(len, 4); 8424 jcc(Assembler::zero, L_tail_restore); 8425 8426 // Fold crc into first bytes of vector 8427 movdqa(xmm1, Address(buf, 0)); 8428 movdl(rax, xmm1); 8429 xorl(crc, rax); 8430 pinsrd(xmm1, crc, 0); 8431 addptr(buf, 16); 8432 subl(len, 4); // len > 0 8433 jcc(Assembler::less, L_fold_tail); 8434 8435 movdqa(xmm2, Address(buf, 0)); 8436 movdqa(xmm3, Address(buf, 16)); 8437 movdqa(xmm4, Address(buf, 32)); 8438 addptr(buf, 48); 8439 subl(len, 3); 8440 jcc(Assembler::lessEqual, L_fold_512b); 8441 8442 // Fold total 512 bits of polynomial on each iteration, 8443 // 128 bits per each of 4 parallel streams. 8444 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32)); 8445 8446 align(32); 8447 BIND(L_fold_512b_loop); 8448 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 8449 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16); 8450 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32); 8451 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48); 8452 addptr(buf, 64); 8453 subl(len, 4); 8454 jcc(Assembler::greater, L_fold_512b_loop); 8455 8456 // Fold 512 bits to 128 bits. 8457 BIND(L_fold_512b); 8458 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 8459 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2); 8460 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3); 8461 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4); 8462 8463 // Fold the rest of 128 bits data chunks 8464 BIND(L_fold_tail); 8465 addl(len, 3); 8466 jccb(Assembler::lessEqual, L_fold_128b); 8467 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 8468 8469 BIND(L_fold_tail_loop); 8470 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 8471 addptr(buf, 16); 8472 decrementl(len); 8473 jccb(Assembler::greater, L_fold_tail_loop); 8474 8475 // Fold 128 bits in xmm1 down into 32 bits in crc register. 8476 BIND(L_fold_128b); 8477 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr())); 8478 if (UseAVX > 0) { 8479 vpclmulqdq(xmm2, xmm0, xmm1, 0x1); 8480 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */); 8481 vpclmulqdq(xmm0, xmm0, xmm3, 0x1); 8482 } else { 8483 movdqa(xmm2, xmm0); 8484 pclmulqdq(xmm2, xmm1, 0x1); 8485 movdqa(xmm3, xmm0); 8486 pand(xmm3, xmm2); 8487 pclmulqdq(xmm0, xmm3, 0x1); 8488 } 8489 psrldq(xmm1, 8); 8490 psrldq(xmm2, 4); 8491 pxor(xmm0, xmm1); 8492 pxor(xmm0, xmm2); 8493 8494 // 8 8-bit folds to compute 32-bit CRC. 8495 for (int j = 0; j < 4; j++) { 8496 fold_8bit_crc32(xmm0, table, xmm1, rax); 8497 } 8498 movdl(crc, xmm0); // mov 32 bits to general register 8499 for (int j = 0; j < 4; j++) { 8500 fold_8bit_crc32(crc, table, rax); 8501 } 8502 8503 BIND(L_tail_restore); 8504 movl(len, tmp); // restore 8505 BIND(L_tail); 8506 andl(len, 0xf); 8507 jccb(Assembler::zero, L_exit); 8508 8509 // Fold the rest of bytes 8510 align(4); 8511 BIND(L_tail_loop); 8512 movsbl(rax, Address(buf, 0)); // load byte with sign extension 8513 update_byte_crc32(crc, rax, table); 8514 increment(buf); 8515 decrementl(len); 8516 jccb(Assembler::greater, L_tail_loop); 8517 8518 BIND(L_exit); 8519 notl(crc); // ~c 8520 } 8521 8522 #ifdef _LP64 8523 // S. Gueron / Information Processing Letters 112 (2012) 184 8524 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table. 8525 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0]. 8526 // Output: the 64-bit carry-less product of B * CONST 8527 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n, 8528 Register tmp1, Register tmp2, Register tmp3) { 8529 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 8530 if (n > 0) { 8531 addq(tmp3, n * 256 * 8); 8532 } 8533 // Q1 = TABLEExt[n][B & 0xFF]; 8534 movl(tmp1, in); 8535 andl(tmp1, 0x000000FF); 8536 shll(tmp1, 3); 8537 addq(tmp1, tmp3); 8538 movq(tmp1, Address(tmp1, 0)); 8539 8540 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 8541 movl(tmp2, in); 8542 shrl(tmp2, 8); 8543 andl(tmp2, 0x000000FF); 8544 shll(tmp2, 3); 8545 addq(tmp2, tmp3); 8546 movq(tmp2, Address(tmp2, 0)); 8547 8548 shlq(tmp2, 8); 8549 xorq(tmp1, tmp2); 8550 8551 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 8552 movl(tmp2, in); 8553 shrl(tmp2, 16); 8554 andl(tmp2, 0x000000FF); 8555 shll(tmp2, 3); 8556 addq(tmp2, tmp3); 8557 movq(tmp2, Address(tmp2, 0)); 8558 8559 shlq(tmp2, 16); 8560 xorq(tmp1, tmp2); 8561 8562 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 8563 shrl(in, 24); 8564 andl(in, 0x000000FF); 8565 shll(in, 3); 8566 addq(in, tmp3); 8567 movq(in, Address(in, 0)); 8568 8569 shlq(in, 24); 8570 xorq(in, tmp1); 8571 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 8572 } 8573 8574 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 8575 Register in_out, 8576 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 8577 XMMRegister w_xtmp2, 8578 Register tmp1, 8579 Register n_tmp2, Register n_tmp3) { 8580 if (is_pclmulqdq_supported) { 8581 movdl(w_xtmp1, in_out); // modified blindly 8582 8583 movl(tmp1, const_or_pre_comp_const_index); 8584 movdl(w_xtmp2, tmp1); 8585 pclmulqdq(w_xtmp1, w_xtmp2, 0); 8586 8587 movdq(in_out, w_xtmp1); 8588 } else { 8589 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3); 8590 } 8591 } 8592 8593 // Recombination Alternative 2: No bit-reflections 8594 // T1 = (CRC_A * U1) << 1 8595 // T2 = (CRC_B * U2) << 1 8596 // C1 = T1 >> 32 8597 // C2 = T2 >> 32 8598 // T1 = T1 & 0xFFFFFFFF 8599 // T2 = T2 & 0xFFFFFFFF 8600 // T1 = CRC32(0, T1) 8601 // T2 = CRC32(0, T2) 8602 // C1 = C1 ^ T1 8603 // C2 = C2 ^ T2 8604 // CRC = C1 ^ C2 ^ CRC_C 8605 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 8606 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 8607 Register tmp1, Register tmp2, 8608 Register n_tmp3) { 8609 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 8610 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 8611 shlq(in_out, 1); 8612 movl(tmp1, in_out); 8613 shrq(in_out, 32); 8614 xorl(tmp2, tmp2); 8615 crc32(tmp2, tmp1, 4); 8616 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here 8617 shlq(in1, 1); 8618 movl(tmp1, in1); 8619 shrq(in1, 32); 8620 xorl(tmp2, tmp2); 8621 crc32(tmp2, tmp1, 4); 8622 xorl(in1, tmp2); 8623 xorl(in_out, in1); 8624 xorl(in_out, in2); 8625 } 8626 8627 // Set N to predefined value 8628 // Subtract from a lenght of a buffer 8629 // execute in a loop: 8630 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0 8631 // for i = 1 to N do 8632 // CRC_A = CRC32(CRC_A, A[i]) 8633 // CRC_B = CRC32(CRC_B, B[i]) 8634 // CRC_C = CRC32(CRC_C, C[i]) 8635 // end for 8636 // Recombine 8637 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 8638 Register in_out1, Register in_out2, Register in_out3, 8639 Register tmp1, Register tmp2, Register tmp3, 8640 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 8641 Register tmp4, Register tmp5, 8642 Register n_tmp6) { 8643 Label L_processPartitions; 8644 Label L_processPartition; 8645 Label L_exit; 8646 8647 bind(L_processPartitions); 8648 cmpl(in_out1, 3 * size); 8649 jcc(Assembler::less, L_exit); 8650 xorl(tmp1, tmp1); 8651 xorl(tmp2, tmp2); 8652 movq(tmp3, in_out2); 8653 addq(tmp3, size); 8654 8655 bind(L_processPartition); 8656 crc32(in_out3, Address(in_out2, 0), 8); 8657 crc32(tmp1, Address(in_out2, size), 8); 8658 crc32(tmp2, Address(in_out2, size * 2), 8); 8659 addq(in_out2, 8); 8660 cmpq(in_out2, tmp3); 8661 jcc(Assembler::less, L_processPartition); 8662 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 8663 w_xtmp1, w_xtmp2, w_xtmp3, 8664 tmp4, tmp5, 8665 n_tmp6); 8666 addq(in_out2, 2 * size); 8667 subl(in_out1, 3 * size); 8668 jmp(L_processPartitions); 8669 8670 bind(L_exit); 8671 } 8672 #else 8673 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n, 8674 Register tmp1, Register tmp2, Register tmp3, 8675 XMMRegister xtmp1, XMMRegister xtmp2) { 8676 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 8677 if (n > 0) { 8678 addl(tmp3, n * 256 * 8); 8679 } 8680 // Q1 = TABLEExt[n][B & 0xFF]; 8681 movl(tmp1, in_out); 8682 andl(tmp1, 0x000000FF); 8683 shll(tmp1, 3); 8684 addl(tmp1, tmp3); 8685 movq(xtmp1, Address(tmp1, 0)); 8686 8687 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 8688 movl(tmp2, in_out); 8689 shrl(tmp2, 8); 8690 andl(tmp2, 0x000000FF); 8691 shll(tmp2, 3); 8692 addl(tmp2, tmp3); 8693 movq(xtmp2, Address(tmp2, 0)); 8694 8695 psllq(xtmp2, 8); 8696 pxor(xtmp1, xtmp2); 8697 8698 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 8699 movl(tmp2, in_out); 8700 shrl(tmp2, 16); 8701 andl(tmp2, 0x000000FF); 8702 shll(tmp2, 3); 8703 addl(tmp2, tmp3); 8704 movq(xtmp2, Address(tmp2, 0)); 8705 8706 psllq(xtmp2, 16); 8707 pxor(xtmp1, xtmp2); 8708 8709 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 8710 shrl(in_out, 24); 8711 andl(in_out, 0x000000FF); 8712 shll(in_out, 3); 8713 addl(in_out, tmp3); 8714 movq(xtmp2, Address(in_out, 0)); 8715 8716 psllq(xtmp2, 24); 8717 pxor(xtmp1, xtmp2); // Result in CXMM 8718 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 8719 } 8720 8721 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 8722 Register in_out, 8723 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 8724 XMMRegister w_xtmp2, 8725 Register tmp1, 8726 Register n_tmp2, Register n_tmp3) { 8727 if (is_pclmulqdq_supported) { 8728 movdl(w_xtmp1, in_out); 8729 8730 movl(tmp1, const_or_pre_comp_const_index); 8731 movdl(w_xtmp2, tmp1); 8732 pclmulqdq(w_xtmp1, w_xtmp2, 0); 8733 // Keep result in XMM since GPR is 32 bit in length 8734 } else { 8735 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2); 8736 } 8737 } 8738 8739 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 8740 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 8741 Register tmp1, Register tmp2, 8742 Register n_tmp3) { 8743 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 8744 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 8745 8746 psllq(w_xtmp1, 1); 8747 movdl(tmp1, w_xtmp1); 8748 psrlq(w_xtmp1, 32); 8749 movdl(in_out, w_xtmp1); 8750 8751 xorl(tmp2, tmp2); 8752 crc32(tmp2, tmp1, 4); 8753 xorl(in_out, tmp2); 8754 8755 psllq(w_xtmp2, 1); 8756 movdl(tmp1, w_xtmp2); 8757 psrlq(w_xtmp2, 32); 8758 movdl(in1, w_xtmp2); 8759 8760 xorl(tmp2, tmp2); 8761 crc32(tmp2, tmp1, 4); 8762 xorl(in1, tmp2); 8763 xorl(in_out, in1); 8764 xorl(in_out, in2); 8765 } 8766 8767 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 8768 Register in_out1, Register in_out2, Register in_out3, 8769 Register tmp1, Register tmp2, Register tmp3, 8770 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 8771 Register tmp4, Register tmp5, 8772 Register n_tmp6) { 8773 Label L_processPartitions; 8774 Label L_processPartition; 8775 Label L_exit; 8776 8777 bind(L_processPartitions); 8778 cmpl(in_out1, 3 * size); 8779 jcc(Assembler::less, L_exit); 8780 xorl(tmp1, tmp1); 8781 xorl(tmp2, tmp2); 8782 movl(tmp3, in_out2); 8783 addl(tmp3, size); 8784 8785 bind(L_processPartition); 8786 crc32(in_out3, Address(in_out2, 0), 4); 8787 crc32(tmp1, Address(in_out2, size), 4); 8788 crc32(tmp2, Address(in_out2, size*2), 4); 8789 crc32(in_out3, Address(in_out2, 0+4), 4); 8790 crc32(tmp1, Address(in_out2, size+4), 4); 8791 crc32(tmp2, Address(in_out2, size*2+4), 4); 8792 addl(in_out2, 8); 8793 cmpl(in_out2, tmp3); 8794 jcc(Assembler::less, L_processPartition); 8795 8796 push(tmp3); 8797 push(in_out1); 8798 push(in_out2); 8799 tmp4 = tmp3; 8800 tmp5 = in_out1; 8801 n_tmp6 = in_out2; 8802 8803 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 8804 w_xtmp1, w_xtmp2, w_xtmp3, 8805 tmp4, tmp5, 8806 n_tmp6); 8807 8808 pop(in_out2); 8809 pop(in_out1); 8810 pop(tmp3); 8811 8812 addl(in_out2, 2 * size); 8813 subl(in_out1, 3 * size); 8814 jmp(L_processPartitions); 8815 8816 bind(L_exit); 8817 } 8818 #endif //LP64 8819 8820 #ifdef _LP64 8821 // Algorithm 2: Pipelined usage of the CRC32 instruction. 8822 // Input: A buffer I of L bytes. 8823 // Output: the CRC32C value of the buffer. 8824 // Notations: 8825 // Write L = 24N + r, with N = floor (L/24). 8826 // r = L mod 24 (0 <= r < 24). 8827 // Consider I as the concatenation of A|B|C|R, where A, B, C, each, 8828 // N quadwords, and R consists of r bytes. 8829 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1 8830 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1 8831 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1 8832 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1 8833 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 8834 Register tmp1, Register tmp2, Register tmp3, 8835 Register tmp4, Register tmp5, Register tmp6, 8836 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 8837 bool is_pclmulqdq_supported) { 8838 uint32_t const_or_pre_comp_const_index[CRC32C::NUM_PRECOMPUTED_CONSTANTS]; 8839 Label L_wordByWord; 8840 Label L_byteByByteProlog; 8841 Label L_byteByByte; 8842 Label L_exit; 8843 8844 if (is_pclmulqdq_supported ) { 8845 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 8846 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1); 8847 8848 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 8849 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 8850 8851 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 8852 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 8853 assert((CRC32C::NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\""); 8854 } else { 8855 const_or_pre_comp_const_index[0] = 1; 8856 const_or_pre_comp_const_index[1] = 0; 8857 8858 const_or_pre_comp_const_index[2] = 3; 8859 const_or_pre_comp_const_index[3] = 2; 8860 8861 const_or_pre_comp_const_index[4] = 5; 8862 const_or_pre_comp_const_index[5] = 4; 8863 } 8864 crc32c_proc_chunk(CRC32C::HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 8865 in2, in1, in_out, 8866 tmp1, tmp2, tmp3, 8867 w_xtmp1, w_xtmp2, w_xtmp3, 8868 tmp4, tmp5, 8869 tmp6); 8870 crc32c_proc_chunk(CRC32C::MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 8871 in2, in1, in_out, 8872 tmp1, tmp2, tmp3, 8873 w_xtmp1, w_xtmp2, w_xtmp3, 8874 tmp4, tmp5, 8875 tmp6); 8876 crc32c_proc_chunk(CRC32C::LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 8877 in2, in1, in_out, 8878 tmp1, tmp2, tmp3, 8879 w_xtmp1, w_xtmp2, w_xtmp3, 8880 tmp4, tmp5, 8881 tmp6); 8882 movl(tmp1, in2); 8883 andl(tmp1, 0x00000007); 8884 negl(tmp1); 8885 addl(tmp1, in2); 8886 addq(tmp1, in1); 8887 8888 BIND(L_wordByWord); 8889 cmpq(in1, tmp1); 8890 jcc(Assembler::greaterEqual, L_byteByByteProlog); 8891 crc32(in_out, Address(in1, 0), 4); 8892 addq(in1, 4); 8893 jmp(L_wordByWord); 8894 8895 BIND(L_byteByByteProlog); 8896 andl(in2, 0x00000007); 8897 movl(tmp2, 1); 8898 8899 BIND(L_byteByByte); 8900 cmpl(tmp2, in2); 8901 jccb(Assembler::greater, L_exit); 8902 crc32(in_out, Address(in1, 0), 1); 8903 incq(in1); 8904 incl(tmp2); 8905 jmp(L_byteByByte); 8906 8907 BIND(L_exit); 8908 } 8909 #else 8910 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 8911 Register tmp1, Register tmp2, Register tmp3, 8912 Register tmp4, Register tmp5, Register tmp6, 8913 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 8914 bool is_pclmulqdq_supported) { 8915 uint32_t const_or_pre_comp_const_index[CRC32C::NUM_PRECOMPUTED_CONSTANTS]; 8916 Label L_wordByWord; 8917 Label L_byteByByteProlog; 8918 Label L_byteByByte; 8919 Label L_exit; 8920 8921 if (is_pclmulqdq_supported) { 8922 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 8923 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1); 8924 8925 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 8926 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 8927 8928 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 8929 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 8930 } else { 8931 const_or_pre_comp_const_index[0] = 1; 8932 const_or_pre_comp_const_index[1] = 0; 8933 8934 const_or_pre_comp_const_index[2] = 3; 8935 const_or_pre_comp_const_index[3] = 2; 8936 8937 const_or_pre_comp_const_index[4] = 5; 8938 const_or_pre_comp_const_index[5] = 4; 8939 } 8940 crc32c_proc_chunk(CRC32C::HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 8941 in2, in1, in_out, 8942 tmp1, tmp2, tmp3, 8943 w_xtmp1, w_xtmp2, w_xtmp3, 8944 tmp4, tmp5, 8945 tmp6); 8946 crc32c_proc_chunk(CRC32C::MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 8947 in2, in1, in_out, 8948 tmp1, tmp2, tmp3, 8949 w_xtmp1, w_xtmp2, w_xtmp3, 8950 tmp4, tmp5, 8951 tmp6); 8952 crc32c_proc_chunk(CRC32C::LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 8953 in2, in1, in_out, 8954 tmp1, tmp2, tmp3, 8955 w_xtmp1, w_xtmp2, w_xtmp3, 8956 tmp4, tmp5, 8957 tmp6); 8958 movl(tmp1, in2); 8959 andl(tmp1, 0x00000007); 8960 negl(tmp1); 8961 addl(tmp1, in2); 8962 addl(tmp1, in1); 8963 8964 BIND(L_wordByWord); 8965 cmpl(in1, tmp1); 8966 jcc(Assembler::greaterEqual, L_byteByByteProlog); 8967 crc32(in_out, Address(in1,0), 4); 8968 addl(in1, 4); 8969 jmp(L_wordByWord); 8970 8971 BIND(L_byteByByteProlog); 8972 andl(in2, 0x00000007); 8973 movl(tmp2, 1); 8974 8975 BIND(L_byteByByte); 8976 cmpl(tmp2, in2); 8977 jccb(Assembler::greater, L_exit); 8978 movb(tmp1, Address(in1, 0)); 8979 crc32(in_out, tmp1, 1); 8980 incl(in1); 8981 incl(tmp2); 8982 jmp(L_byteByByte); 8983 8984 BIND(L_exit); 8985 } 8986 #endif // LP64 8987 #undef BIND 8988 #undef BLOCK_COMMENT 8989 8990 8991 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { 8992 switch (cond) { 8993 // Note some conditions are synonyms for others 8994 case Assembler::zero: return Assembler::notZero; 8995 case Assembler::notZero: return Assembler::zero; 8996 case Assembler::less: return Assembler::greaterEqual; 8997 case Assembler::lessEqual: return Assembler::greater; 8998 case Assembler::greater: return Assembler::lessEqual; 8999 case Assembler::greaterEqual: return Assembler::less; 9000 case Assembler::below: return Assembler::aboveEqual; 9001 case Assembler::belowEqual: return Assembler::above; 9002 case Assembler::above: return Assembler::belowEqual; 9003 case Assembler::aboveEqual: return Assembler::below; 9004 case Assembler::overflow: return Assembler::noOverflow; 9005 case Assembler::noOverflow: return Assembler::overflow; 9006 case Assembler::negative: return Assembler::positive; 9007 case Assembler::positive: return Assembler::negative; 9008 case Assembler::parity: return Assembler::noParity; 9009 case Assembler::noParity: return Assembler::parity; 9010 } 9011 ShouldNotReachHere(); return Assembler::overflow; 9012 } 9013 9014 SkipIfEqual::SkipIfEqual( 9015 MacroAssembler* masm, const bool* flag_addr, bool value) { 9016 _masm = masm; 9017 _masm->cmp8(ExternalAddress((address)flag_addr), value); 9018 _masm->jcc(Assembler::equal, _label); 9019 } 9020 9021 SkipIfEqual::~SkipIfEqual() { 9022 _masm->bind(_label); 9023 }