1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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23 */
24
25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30 #include "runtime/rtmLocking.hpp"
31
32
33 // MacroAssembler extends Assembler by frequently used macros.
34 //
35 // Instructions for which a 'better' code sequence exists depending
36 // on arguments should also go in here.
37
38 class MacroAssembler: public Assembler {
39 friend class LIR_Assembler;
40 friend class Runtime1; // as_Address()
41
42 protected:
43
44 Address as_Address(AddressLiteral adr);
45 Address as_Address(ArrayAddress adr);
46
47 // Support for VM calls
48 //
49 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
50 // may customize this version by overriding it for its purposes (e.g., to save/restore
51 // additional registers when doing a VM call).
52 #ifdef CC_INTERP
53 // c++ interpreter never wants to use interp_masm version of call_VM
54 #define VIRTUAL
55 #else
56 #define VIRTUAL virtual
57 #endif
58
59 VIRTUAL void call_VM_leaf_base(
60 address entry_point, // the entry point
61 int number_of_arguments // the number of arguments to pop after the call
62 );
63
64 // This is the base routine called by the different versions of call_VM. The interpreter
65 // may customize this version by overriding it for its purposes (e.g., to save/restore
66 // additional registers when doing a VM call).
67 //
68 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
69 // returns the register which contains the thread upon return. If a thread register has been
70 // specified, the return value will correspond to that register. If no last_java_sp is specified
71 // (noreg) than rsp will be used instead.
72 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
73 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
74 Register java_thread, // the thread if computed before ; use noreg otherwise
75 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
76 address entry_point, // the entry point
77 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
78 bool check_exceptions // whether to check for pending exceptions after return
79 );
80
81 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
82 // The implementation is only non-empty for the InterpreterMacroAssembler,
83 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
84 virtual void check_and_handle_popframe(Register java_thread);
85 virtual void check_and_handle_earlyret(Register java_thread);
86
87 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
88
89 // helpers for FPU flag access
90 // tmp is a temporary register, if none is available use noreg
91 void save_rax (Register tmp);
92 void restore_rax(Register tmp);
93
94 public:
95 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
96
97 // Support for NULL-checks
98 //
99 // Generates code that causes a NULL OS exception if the content of reg is NULL.
100 // If the accessed location is M[reg + offset] and the offset is known, provide the
101 // offset. No explicit code generation is needed if the offset is within a certain
102 // range (0 <= offset <= page_size).
103
104 void null_check(Register reg, int offset = -1);
105 static bool needs_explicit_null_check(intptr_t offset);
106
107 // Required platform-specific helpers for Label::patch_instructions.
108 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
109 void pd_patch_instruction(address branch, address target) {
110 unsigned char op = branch[0];
111 assert(op == 0xE8 /* call */ ||
112 op == 0xE9 /* jmp */ ||
113 op == 0xEB /* short jmp */ ||
114 (op & 0xF0) == 0x70 /* short jcc */ ||
115 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
116 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
117 "Invalid opcode at patch point");
118
119 if (op == 0xEB || (op & 0xF0) == 0x70) {
120 // short offset operators (jmp and jcc)
121 char* disp = (char*) &branch[1];
122 int imm8 = target - (address) &disp[1];
123 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
124 *disp = imm8;
125 } else {
126 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
127 int imm32 = target - (address) &disp[1];
128 *disp = imm32;
129 }
130 }
131
132 // The following 4 methods return the offset of the appropriate move instruction
133
134 // Support for fast byte/short loading with zero extension (depending on particular CPU)
135 int load_unsigned_byte(Register dst, Address src);
136 int load_unsigned_short(Register dst, Address src);
137
138 // Support for fast byte/short loading with sign extension (depending on particular CPU)
139 int load_signed_byte(Register dst, Address src);
140 int load_signed_short(Register dst, Address src);
141
142 // Support for sign-extension (hi:lo = extend_sign(lo))
143 void extend_sign(Register hi, Register lo);
144
145 // Load and store values by size and signed-ness
146 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
147 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
148
149 // Support for inc/dec with optimal instruction selection depending on value
150
151 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
152 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
153
154 void decrementl(Address dst, int value = 1);
155 void decrementl(Register reg, int value = 1);
156
157 void decrementq(Register reg, int value = 1);
158 void decrementq(Address dst, int value = 1);
159
160 void incrementl(Address dst, int value = 1);
161 void incrementl(Register reg, int value = 1);
162
163 void incrementq(Register reg, int value = 1);
164 void incrementq(Address dst, int value = 1);
165
166 // Support optimal SSE move instructions.
167 void movflt(XMMRegister dst, XMMRegister src) {
168 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
169 else { movss (dst, src); return; }
170 }
171 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
172 void movflt(XMMRegister dst, AddressLiteral src);
173 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
174
175 void movdbl(XMMRegister dst, XMMRegister src) {
176 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
177 else { movsd (dst, src); return; }
178 }
179
180 void movdbl(XMMRegister dst, AddressLiteral src);
181
182 void movdbl(XMMRegister dst, Address src) {
183 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
184 else { movlpd(dst, src); return; }
185 }
186 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
187
188 void incrementl(AddressLiteral dst);
189 void incrementl(ArrayAddress dst);
190
191 void incrementq(AddressLiteral dst);
192
193 // Alignment
194 void align(int modulus);
195 void align(int modulus, int target);
196
197 // A 5 byte nop that is safe for patching (see patch_verified_entry)
198 void fat_nop();
199
200 // Stack frame creation/removal
201 void enter();
202 void leave();
203
204 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
205 // The pointer will be loaded into the thread register.
206 void get_thread(Register thread);
207
208
209 // Support for VM calls
210 //
211 // It is imperative that all calls into the VM are handled via the call_VM macros.
212 // They make sure that the stack linkage is setup correctly. call_VM's correspond
213 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
214
215
216 void call_VM(Register oop_result,
217 address entry_point,
218 bool check_exceptions = true);
219 void call_VM(Register oop_result,
220 address entry_point,
221 Register arg_1,
222 bool check_exceptions = true);
223 void call_VM(Register oop_result,
224 address entry_point,
225 Register arg_1, Register arg_2,
226 bool check_exceptions = true);
227 void call_VM(Register oop_result,
228 address entry_point,
229 Register arg_1, Register arg_2, Register arg_3,
230 bool check_exceptions = true);
231
232 // Overloadings with last_Java_sp
233 void call_VM(Register oop_result,
234 Register last_java_sp,
235 address entry_point,
236 int number_of_arguments = 0,
237 bool check_exceptions = true);
238 void call_VM(Register oop_result,
239 Register last_java_sp,
240 address entry_point,
241 Register arg_1, bool
242 check_exceptions = true);
243 void call_VM(Register oop_result,
244 Register last_java_sp,
245 address entry_point,
246 Register arg_1, Register arg_2,
247 bool check_exceptions = true);
248 void call_VM(Register oop_result,
249 Register last_java_sp,
250 address entry_point,
251 Register arg_1, Register arg_2, Register arg_3,
252 bool check_exceptions = true);
253
254 void get_vm_result (Register oop_result, Register thread);
255 void get_vm_result_2(Register metadata_result, Register thread);
256
257 // These always tightly bind to MacroAssembler::call_VM_base
258 // bypassing the virtual implementation
259 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
260 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
261 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
262 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
263 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
264
265 void call_VM_leaf(address entry_point,
266 int number_of_arguments = 0);
267 void call_VM_leaf(address entry_point,
268 Register arg_1);
269 void call_VM_leaf(address entry_point,
270 Register arg_1, Register arg_2);
271 void call_VM_leaf(address entry_point,
272 Register arg_1, Register arg_2, Register arg_3);
273
274 // These always tightly bind to MacroAssembler::call_VM_leaf_base
275 // bypassing the virtual implementation
276 void super_call_VM_leaf(address entry_point);
277 void super_call_VM_leaf(address entry_point, Register arg_1);
278 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
279 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
280 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
281
282 // last Java Frame (fills frame anchor)
283 void set_last_Java_frame(Register thread,
284 Register last_java_sp,
285 Register last_java_fp,
286 address last_java_pc);
287
288 // thread in the default location (r15_thread on 64bit)
289 void set_last_Java_frame(Register last_java_sp,
290 Register last_java_fp,
291 address last_java_pc);
292
293 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
294
295 // thread in the default location (r15_thread on 64bit)
296 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
297
298 // Stores
299 void store_check(Register obj); // store check for obj - register is destroyed afterwards
300 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
301
302 #if INCLUDE_ALL_GCS
303
304 void g1_write_barrier_pre(Register obj,
305 Register pre_val,
306 Register thread,
307 Register tmp,
308 bool tosca_live,
309 bool expand_call);
310
311 void g1_write_barrier_post(Register store_addr,
312 Register new_val,
313 Register thread,
314 Register tmp,
315 Register tmp2);
316
317 #endif // INCLUDE_ALL_GCS
318
319 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
320 void c2bool(Register x);
321
322 // C++ bool manipulation
323
324 void movbool(Register dst, Address src);
325 void movbool(Address dst, bool boolconst);
326 void movbool(Address dst, Register src);
327 void testbool(Register dst);
328
329 // oop manipulations
330 void load_klass(Register dst, Register src);
331 void store_klass(Register dst, Register src);
332
333 void load_heap_oop(Register dst, Address src);
334 void load_heap_oop_not_null(Register dst, Address src);
335 void store_heap_oop(Address dst, Register src);
336 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
337
338 // Used for storing NULL. All other oop constants should be
339 // stored using routines that take a jobject.
340 void store_heap_oop_null(Address dst);
341
342 void load_prototype_header(Register dst, Register src);
343
344 #ifdef _LP64
345 void store_klass_gap(Register dst, Register src);
346
347 // This dummy is to prevent a call to store_heap_oop from
348 // converting a zero (like NULL) into a Register by giving
349 // the compiler two choices it can't resolve
350
351 void store_heap_oop(Address dst, void* dummy);
352
353 void encode_heap_oop(Register r);
354 void decode_heap_oop(Register r);
355 void encode_heap_oop_not_null(Register r);
356 void decode_heap_oop_not_null(Register r);
357 void encode_heap_oop_not_null(Register dst, Register src);
358 void decode_heap_oop_not_null(Register dst, Register src);
359
360 void set_narrow_oop(Register dst, jobject obj);
361 void set_narrow_oop(Address dst, jobject obj);
362 void cmp_narrow_oop(Register dst, jobject obj);
363 void cmp_narrow_oop(Address dst, jobject obj);
364
365 void encode_klass_not_null(Register r);
366 void decode_klass_not_null(Register r);
367 void encode_klass_not_null(Register dst, Register src);
368 void decode_klass_not_null(Register dst, Register src);
369 void set_narrow_klass(Register dst, Klass* k);
370 void set_narrow_klass(Address dst, Klass* k);
371 void cmp_narrow_klass(Register dst, Klass* k);
372 void cmp_narrow_klass(Address dst, Klass* k);
373
374 // Returns the byte size of the instructions generated by decode_klass_not_null()
375 // when compressed klass pointers are being used.
376 static int instr_size_for_decode_klass_not_null();
377
378 // if heap base register is used - reinit it with the correct value
379 void reinit_heapbase();
380
381 DEBUG_ONLY(void verify_heapbase(const char* msg);)
382
383 #endif // _LP64
384
385 // Int division/remainder for Java
386 // (as idivl, but checks for special case as described in JVM spec.)
387 // returns idivl instruction offset for implicit exception handling
388 int corrected_idivl(Register reg);
389
390 // Long division/remainder for Java
391 // (as idivq, but checks for special case as described in JVM spec.)
392 // returns idivq instruction offset for implicit exception handling
393 int corrected_idivq(Register reg);
394
395 void int3();
396
397 // Long operation macros for a 32bit cpu
398 // Long negation for Java
399 void lneg(Register hi, Register lo);
400
401 // Long multiplication for Java
402 // (destroys contents of eax, ebx, ecx and edx)
403 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
404
405 // Long shifts for Java
406 // (semantics as described in JVM spec.)
407 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
408 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
409
410 // Long compare for Java
411 // (semantics as described in JVM spec.)
412 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
413
414
415 // misc
416
417 // Sign extension
418 void sign_extend_short(Register reg);
419 void sign_extend_byte(Register reg);
420
421 // Division by power of 2, rounding towards 0
422 void division_with_shift(Register reg, int shift_value);
423
424 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
425 //
426 // CF (corresponds to C0) if x < y
427 // PF (corresponds to C2) if unordered
428 // ZF (corresponds to C3) if x = y
429 //
430 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
431 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
432 void fcmp(Register tmp);
433 // Variant of the above which allows y to be further down the stack
434 // and which only pops x and y if specified. If pop_right is
435 // specified then pop_left must also be specified.
436 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
437
438 // Floating-point comparison for Java
439 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
440 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
441 // (semantics as described in JVM spec.)
442 void fcmp2int(Register dst, bool unordered_is_less);
443 // Variant of the above which allows y to be further down the stack
444 // and which only pops x and y if specified. If pop_right is
445 // specified then pop_left must also be specified.
446 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
447
448 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
449 // tmp is a temporary register, if none is available use noreg
450 void fremr(Register tmp);
451
452
453 // same as fcmp2int, but using SSE2
454 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
455 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
456
457 // Inlined sin/cos generator for Java; must not use CPU instruction
458 // directly on Intel as it does not have high enough precision
459 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
460 // number of FPU stack slots in use; all but the topmost will
461 // require saving if a slow case is necessary. Assumes argument is
462 // on FP TOS; result is on FP TOS. No cpu registers are changed by
463 // this code.
464 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
465
466 // branch to L if FPU flag C2 is set/not set
467 // tmp is a temporary register, if none is available use noreg
468 void jC2 (Register tmp, Label& L);
469 void jnC2(Register tmp, Label& L);
470
471 // Pop ST (ffree & fincstp combined)
472 void fpop();
473
474 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
475 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
476 void load_float(Address src);
477
478 // Store float value to 'address'. If UseSSE >= 1, the value is stored
479 // from register xmm0. Otherwise, the value is stored from the FPU stack.
480 void store_float(Address dst);
481
482 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
483 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
484 void load_double(Address src);
485
486 // Store double value to 'address'. If UseSSE >= 2, the value is stored
487 // from register xmm0. Otherwise, the value is stored from the FPU stack.
488 void store_double(Address dst);
489
490 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
491 void push_fTOS();
492
493 // pops double TOS element from CPU stack and pushes on FPU stack
494 void pop_fTOS();
495
496 void empty_FPU_stack();
497
498 void push_IU_state();
499 void pop_IU_state();
500
501 void push_FPU_state();
502 void pop_FPU_state();
503
504 void push_CPU_state();
505 void pop_CPU_state();
506
507 // Round up to a power of two
508 void round_to(Register reg, int modulus);
509
510 // Callee saved registers handling
511 void push_callee_saved_registers();
512 void pop_callee_saved_registers();
513
514 // allocation
515 void eden_allocate(
516 Register obj, // result: pointer to object after successful allocation
517 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
518 int con_size_in_bytes, // object size in bytes if known at compile time
519 Register t1, // temp register
520 Label& slow_case // continuation point if fast allocation fails
521 );
522 void tlab_allocate(
523 Register obj, // result: pointer to object after successful allocation
524 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
525 int con_size_in_bytes, // object size in bytes if known at compile time
526 Register t1, // temp register
527 Register t2, // temp register
528 Label& slow_case // continuation point if fast allocation fails
529 );
530 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
531 void incr_allocated_bytes(Register thread,
532 Register var_size_in_bytes, int con_size_in_bytes,
533 Register t1 = noreg);
534
535 // interface method calling
536 void lookup_interface_method(Register recv_klass,
537 Register intf_klass,
538 RegisterOrConstant itable_index,
539 Register method_result,
540 Register scan_temp,
541 Label& no_such_interface);
542
543 // virtual method calling
544 void lookup_virtual_method(Register recv_klass,
545 RegisterOrConstant vtable_index,
546 Register method_result);
547
548 // Test sub_klass against super_klass, with fast and slow paths.
549
550 // The fast path produces a tri-state answer: yes / no / maybe-slow.
551 // One of the three labels can be NULL, meaning take the fall-through.
552 // If super_check_offset is -1, the value is loaded up from super_klass.
553 // No registers are killed, except temp_reg.
554 void check_klass_subtype_fast_path(Register sub_klass,
555 Register super_klass,
556 Register temp_reg,
557 Label* L_success,
558 Label* L_failure,
559 Label* L_slow_path,
560 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
561
562 // The rest of the type check; must be wired to a corresponding fast path.
563 // It does not repeat the fast path logic, so don't use it standalone.
564 // The temp_reg and temp2_reg can be noreg, if no temps are available.
565 // Updates the sub's secondary super cache as necessary.
566 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
567 void check_klass_subtype_slow_path(Register sub_klass,
568 Register super_klass,
569 Register temp_reg,
570 Register temp2_reg,
571 Label* L_success,
572 Label* L_failure,
573 bool set_cond_codes = false);
574
575 // Simplified, combined version, good for typical uses.
576 // Falls through on failure.
577 void check_klass_subtype(Register sub_klass,
578 Register super_klass,
579 Register temp_reg,
580 Label& L_success);
581
582 // method handles (JSR 292)
583 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
584
585 //----
586 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
587
588 // Debugging
589
590 // only if +VerifyOops
591 // TODO: Make these macros with file and line like sparc version!
592 void verify_oop(Register reg, const char* s = "broken oop");
593 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
594
595 // TODO: verify method and klass metadata (compare against vptr?)
596 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
597 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
598
599 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
600 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
601
602 // only if +VerifyFPU
603 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
604
605 // Verify or restore cpu control state after JNI call
606 void restore_cpu_control_state_after_jni();
607
608 // prints msg, dumps registers and stops execution
609 void stop(const char* msg);
610
611 // prints msg and continues
612 void warn(const char* msg);
613
614 // dumps registers and other state
615 void print_state();
616
617 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
618 static void debug64(char* msg, int64_t pc, int64_t regs[]);
619 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
620 static void print_state64(int64_t pc, int64_t regs[]);
621
622 void os_breakpoint();
623
624 void untested() { stop("untested"); }
625
626 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
627
628 void should_not_reach_here() { stop("should not reach here"); }
629
630 void print_CPU_state();
631
632 // Stack overflow checking
633 void bang_stack_with_offset(int offset) {
634 // stack grows down, caller passes positive offset
635 assert(offset > 0, "must bang with negative offset");
636 movl(Address(rsp, (-offset)), rax);
637 }
638
639 // Writes to stack successive pages until offset reached to check for
640 // stack overflow + shadow pages. Also, clobbers tmp
641 void bang_stack_size(Register size, Register tmp);
642
643 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
644 Register tmp,
645 int offset);
646
647 // Support for serializing memory accesses between threads
648 void serialize_memory(Register thread, Register tmp);
649
650 void verify_tlab();
651
652 // Biased locking support
653 // lock_reg and obj_reg must be loaded up with the appropriate values.
654 // swap_reg must be rax, and is killed.
655 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
656 // be killed; if not supplied, push/pop will be used internally to
657 // allocate a temporary (inefficient, avoid if possible).
658 // Optional slow case is for implementations (interpreter and C1) which branch to
659 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
660 // Returns offset of first potentially-faulting instruction for null
661 // check info (currently consumed only by C1). If
662 // swap_reg_contains_mark is true then returns -1 as it is assumed
663 // the calling code has already passed any potential faults.
664 int biased_locking_enter(Register lock_reg, Register obj_reg,
665 Register swap_reg, Register tmp_reg,
666 bool swap_reg_contains_mark,
667 Label& done, Label* slow_case = NULL,
668 BiasedLockingCounters* counters = NULL);
669 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
670 #ifdef COMPILER2
671 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
672 // See full desription in macroAssembler_x86.cpp.
673 void fast_lock(Register obj, Register box, Register tmp,
674 Register scr, Register cx1, Register cx2,
675 BiasedLockingCounters* counters,
676 RTMLockingCounters* rtm_counters,
677 RTMLockingCounters* stack_rtm_counters,
678 Metadata* method_data,
679 bool use_rtm, bool profile_rtm);
680 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
681 #if INCLUDE_RTM_OPT
682 void rtm_counters_update(Register abort_status, Register rtm_counters);
683 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
684 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
685 RTMLockingCounters* rtm_counters,
686 Metadata* method_data);
687 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
688 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
689 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
690 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
691 void rtm_stack_locking(Register obj, Register tmp, Register scr,
692 Register retry_on_abort_count,
693 RTMLockingCounters* stack_rtm_counters,
694 Metadata* method_data, bool profile_rtm,
695 Label& DONE_LABEL, Label& IsInflated);
696 void rtm_inflated_locking(Register obj, Register box, Register tmp,
697 Register scr, Register retry_on_busy_count,
698 Register retry_on_abort_count,
699 RTMLockingCounters* rtm_counters,
700 Metadata* method_data, bool profile_rtm,
701 Label& DONE_LABEL);
702 #endif
703 #endif
704
705 Condition negate_condition(Condition cond);
706
707 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
708 // operands. In general the names are modified to avoid hiding the instruction in Assembler
709 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
710 // here in MacroAssembler. The major exception to this rule is call
711
712 // Arithmetics
713
714
715 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
716 void addptr(Address dst, Register src);
717
718 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
719 void addptr(Register dst, int32_t src);
720 void addptr(Register dst, Register src);
721 void addptr(Register dst, RegisterOrConstant src) {
722 if (src.is_constant()) addptr(dst, (int) src.as_constant());
723 else addptr(dst, src.as_register());
724 }
725
726 void andptr(Register dst, int32_t src);
727 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
728
729 void cmp8(AddressLiteral src1, int imm);
730
731 // renamed to drag out the casting of address to int32_t/intptr_t
732 void cmp32(Register src1, int32_t imm);
733
734 void cmp32(AddressLiteral src1, int32_t imm);
735 // compare reg - mem, or reg - &mem
736 void cmp32(Register src1, AddressLiteral src2);
737
738 void cmp32(Register src1, Address src2);
739
740 #ifndef _LP64
741 void cmpklass(Address dst, Metadata* obj);
742 void cmpklass(Register dst, Metadata* obj);
743 void cmpoop(Address dst, jobject obj);
744 void cmpoop(Register dst, jobject obj);
745 #endif // _LP64
746
747 // NOTE src2 must be the lval. This is NOT an mem-mem compare
748 void cmpptr(Address src1, AddressLiteral src2);
749
750 void cmpptr(Register src1, AddressLiteral src2);
751
752 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
753 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
754 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
755
756 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
757 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
758
759 // cmp64 to avoild hiding cmpq
760 void cmp64(Register src1, AddressLiteral src);
761
762 void cmpxchgptr(Register reg, Address adr);
763
764 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
765
766
767 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
768 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
769
770
771 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
772
773 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
774
775 void shlptr(Register dst, int32_t shift);
776 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
777
778 void shrptr(Register dst, int32_t shift);
779 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
780
781 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
782 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
783
784 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
785
786 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
787 void subptr(Register dst, int32_t src);
788 // Force generation of a 4 byte immediate value even if it fits into 8bit
789 void subptr_imm32(Register dst, int32_t src);
790 void subptr(Register dst, Register src);
791 void subptr(Register dst, RegisterOrConstant src) {
792 if (src.is_constant()) subptr(dst, (int) src.as_constant());
793 else subptr(dst, src.as_register());
794 }
795
796 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
797 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
798
799 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
800 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
801
802 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
803
804
805
806 // Helper functions for statistics gathering.
807 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
808 void cond_inc32(Condition cond, AddressLiteral counter_addr);
809 // Unconditional atomic increment.
810 void atomic_incl(Address counter_addr);
811 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
812 #ifdef _LP64
813 void atomic_incq(Address counter_addr);
814 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
815 #endif
816 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
817 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
818
819 void lea(Register dst, AddressLiteral adr);
820 void lea(Address dst, AddressLiteral adr);
821 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
822
823 void leal32(Register dst, Address src) { leal(dst, src); }
824
825 // Import other testl() methods from the parent class or else
826 // they will be hidden by the following overriding declaration.
827 using Assembler::testl;
828 void testl(Register dst, AddressLiteral src);
829
830 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
831 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
832 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
833 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
834
835 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
836 void testptr(Register src1, Register src2);
837
838 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
839 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
840
841 // Calls
842
843 void call(Label& L, relocInfo::relocType rtype);
844 void call(Register entry);
845
846 // NOTE: this call tranfers to the effective address of entry NOT
847 // the address contained by entry. This is because this is more natural
848 // for jumps/calls.
849 void call(AddressLiteral entry);
850
851 // Emit the CompiledIC call idiom
852 void ic_call(address entry);
853
854 // Jumps
855
856 // NOTE: these jumps tranfer to the effective address of dst NOT
857 // the address contained by dst. This is because this is more natural
858 // for jumps/calls.
859 void jump(AddressLiteral dst);
860 void jump_cc(Condition cc, AddressLiteral dst);
861
862 // 32bit can do a case table jump in one instruction but we no longer allow the base
863 // to be installed in the Address class. This jump will tranfers to the address
864 // contained in the location described by entry (not the address of entry)
865 void jump(ArrayAddress entry);
866
867 // Floating
868
869 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
870 void andpd(XMMRegister dst, AddressLiteral src);
871
872 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
873 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
874 void andps(XMMRegister dst, AddressLiteral src);
875
876 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
877 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
878 void comiss(XMMRegister dst, AddressLiteral src);
879
880 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
881 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
882 void comisd(XMMRegister dst, AddressLiteral src);
883
884 void fadd_s(Address src) { Assembler::fadd_s(src); }
885 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
886
887 void fldcw(Address src) { Assembler::fldcw(src); }
888 void fldcw(AddressLiteral src);
889
890 void fld_s(int index) { Assembler::fld_s(index); }
891 void fld_s(Address src) { Assembler::fld_s(src); }
892 void fld_s(AddressLiteral src);
893
894 void fld_d(Address src) { Assembler::fld_d(src); }
895 void fld_d(AddressLiteral src);
896
897 void fld_x(Address src) { Assembler::fld_x(src); }
898 void fld_x(AddressLiteral src);
899
900 void fmul_s(Address src) { Assembler::fmul_s(src); }
901 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
902
903 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
904 void ldmxcsr(AddressLiteral src);
905
906 // compute pow(x,y) and exp(x) with x86 instructions. Don't cover
907 // all corner cases and may result in NaN and require fallback to a
908 // runtime call.
909 void fast_pow();
910 void fast_exp();
911 void increase_precision();
912 void restore_precision();
913
914 // computes exp(x). Fallback to runtime call included.
915 void exp_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(true, num_fpu_regs_in_use); }
916 // computes pow(x,y). Fallback to runtime call included.
917 void pow_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(false, num_fpu_regs_in_use); }
918
919 private:
920
921 // call runtime as a fallback for trig functions and pow/exp.
922 void fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use);
923
924 // computes 2^(Ylog2X); Ylog2X in ST(0)
925 void pow_exp_core_encoding();
926
927 // computes pow(x,y) or exp(x). Fallback to runtime call included.
928 void pow_or_exp(bool is_exp, int num_fpu_regs_in_use);
929
930 // these are private because users should be doing movflt/movdbl
931
932 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
933 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
934 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
935 void movss(XMMRegister dst, AddressLiteral src);
936
937 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
938 void movlpd(XMMRegister dst, AddressLiteral src);
939
940 public:
941
942 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
943 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
944 void addsd(XMMRegister dst, AddressLiteral src);
945
946 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
947 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
948 void addss(XMMRegister dst, AddressLiteral src);
949
950 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
951 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
952 void divsd(XMMRegister dst, AddressLiteral src);
953
954 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
955 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
956 void divss(XMMRegister dst, AddressLiteral src);
957
958 // Move Unaligned Double Quadword
959 void movdqu(Address dst, XMMRegister src) { Assembler::movdqu(dst, src); }
960 void movdqu(XMMRegister dst, Address src) { Assembler::movdqu(dst, src); }
961 void movdqu(XMMRegister dst, XMMRegister src) { Assembler::movdqu(dst, src); }
962 void movdqu(XMMRegister dst, AddressLiteral src);
963
964 // Move Aligned Double Quadword
965 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
966 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
967 void movdqa(XMMRegister dst, AddressLiteral src);
968
969 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
970 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
971 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
972 void movsd(XMMRegister dst, AddressLiteral src);
973
974 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
975 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
976 void mulsd(XMMRegister dst, AddressLiteral src);
977
978 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
979 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
980 void mulss(XMMRegister dst, AddressLiteral src);
981
982 // Carry-Less Multiplication Quadword
983 void pclmulldq(XMMRegister dst, XMMRegister src) {
984 // 0x00 - multiply lower 64 bits [0:63]
985 Assembler::pclmulqdq(dst, src, 0x00);
986 }
987 void pclmulhdq(XMMRegister dst, XMMRegister src) {
988 // 0x11 - multiply upper 64 bits [64:127]
989 Assembler::pclmulqdq(dst, src, 0x11);
990 }
991
992 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
993 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
994 void sqrtsd(XMMRegister dst, AddressLiteral src);
995
996 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
997 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
998 void sqrtss(XMMRegister dst, AddressLiteral src);
999
1000 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1001 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1002 void subsd(XMMRegister dst, AddressLiteral src);
1003
1004 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1005 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1006 void subss(XMMRegister dst, AddressLiteral src);
1007
1008 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1009 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1010 void ucomiss(XMMRegister dst, AddressLiteral src);
1011
1012 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1013 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1014 void ucomisd(XMMRegister dst, AddressLiteral src);
1015
1016 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1017 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
1018 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1019 void xorpd(XMMRegister dst, AddressLiteral src);
1020
1021 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1022 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
1023 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1024 void xorps(XMMRegister dst, AddressLiteral src);
1025
1026 // Shuffle Bytes
1027 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1028 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1029 void pshufb(XMMRegister dst, AddressLiteral src);
1030 // AVX 3-operands instructions
1031
1032 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1033 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1034 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1035
1036 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1037 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1038 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1039
1040 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1041 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1042 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1043
1044 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1045 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1046 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1047
1048 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1049 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1050 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1051
1052 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1053 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1054 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1055
1056 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1057 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1058 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1059
1060 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1061 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1062 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1063
1064 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1065 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1066 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1067
1068 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1069 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1070 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1071
1072 // AVX Vector instructions
1073
1074 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1075 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1076 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1077
1078 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1079 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1080 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1081
1082 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1083 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1084 Assembler::vpxor(dst, nds, src, vector_len);
1085 else
1086 Assembler::vxorpd(dst, nds, src, vector_len);
1087 }
1088 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1089 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1090 Assembler::vpxor(dst, nds, src, vector_len);
1091 else
1092 Assembler::vxorpd(dst, nds, src, vector_len);
1093 }
1094
1095 // Simple version for AVX2 256bit vectors
1096 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1097 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1098
1099 // Move packed integer values from low 128 bit to hign 128 bit in 256 bit vector.
1100 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1101 if (UseAVX > 1) // vinserti128h is available only in AVX2
1102 Assembler::vinserti128h(dst, nds, src);
1103 else
1104 Assembler::vinsertf128h(dst, nds, src);
1105 }
1106
1107 // Carry-Less Multiplication Quadword
1108 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1109 // 0x00 - multiply lower 64 bits [0:63]
1110 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1111 }
1112 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1113 // 0x11 - multiply upper 64 bits [64:127]
1114 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1115 }
1116
1117 // Data
1118
1119 void cmov32( Condition cc, Register dst, Address src);
1120 void cmov32( Condition cc, Register dst, Register src);
1121
1122 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1123
1124 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1125 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1126
1127 void movoop(Register dst, jobject obj);
1128 void movoop(Address dst, jobject obj);
1129
1130 void mov_metadata(Register dst, Metadata* obj);
1131 void mov_metadata(Address dst, Metadata* obj);
1132
1133 void movptr(ArrayAddress dst, Register src);
1134 // can this do an lea?
1135 void movptr(Register dst, ArrayAddress src);
1136
1137 void movptr(Register dst, Address src);
1138
1139 #ifdef _LP64
1140 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1141 #else
1142 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1143 #endif
1144
1145 void movptr(Register dst, intptr_t src);
1146 void movptr(Register dst, Register src);
1147 void movptr(Address dst, intptr_t src);
1148
1149 void movptr(Address dst, Register src);
1150
1151 void movptr(Register dst, RegisterOrConstant src) {
1152 if (src.is_constant()) movptr(dst, src.as_constant());
1153 else movptr(dst, src.as_register());
1154 }
1155
1156 #ifdef _LP64
1157 // Generally the next two are only used for moving NULL
1158 // Although there are situations in initializing the mark word where
1159 // they could be used. They are dangerous.
1160
1161 // They only exist on LP64 so that int32_t and intptr_t are not the same
1162 // and we have ambiguous declarations.
1163
1164 void movptr(Address dst, int32_t imm32);
1165 void movptr(Register dst, int32_t imm32);
1166 #endif // _LP64
1167
1168 // to avoid hiding movl
1169 void mov32(AddressLiteral dst, Register src);
1170 void mov32(Register dst, AddressLiteral src);
1171
1172 // to avoid hiding movb
1173 void movbyte(ArrayAddress dst, int src);
1174
1175 // Import other mov() methods from the parent class or else
1176 // they will be hidden by the following overriding declaration.
1177 using Assembler::movdl;
1178 using Assembler::movq;
1179 void movdl(XMMRegister dst, AddressLiteral src);
1180 void movq(XMMRegister dst, AddressLiteral src);
1181
1182 // Can push value or effective address
1183 void pushptr(AddressLiteral src);
1184
1185 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1186 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1187
1188 void pushoop(jobject obj);
1189 void pushklass(Metadata* obj);
1190
1191 // sign extend as need a l to ptr sized element
1192 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1193 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1194
1195 // C2 compiled method's prolog code.
1196 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
1197
1198 // clear memory of size 'cnt' qwords, starting at 'base'.
1199 void clear_mem(Register base, Register cnt, Register rtmp);
1200
1201 // IndexOf strings.
1202 // Small strings are loaded through stack if they cross page boundary.
1203 void string_indexof(Register str1, Register str2,
1204 Register cnt1, Register cnt2,
1205 int int_cnt2, Register result,
1206 XMMRegister vec, Register tmp);
1207
1208 // IndexOf for constant substrings with size >= 8 elements
1209 // which don't need to be loaded through stack.
1210 void string_indexofC8(Register str1, Register str2,
1211 Register cnt1, Register cnt2,
1212 int int_cnt2, Register result,
1213 XMMRegister vec, Register tmp);
1214
1215 // Smallest code: we don't need to load through stack,
1216 // check string tail.
1217
1218 // Compare strings.
1219 void string_compare(Register str1, Register str2,
1220 Register cnt1, Register cnt2, Register result,
1221 XMMRegister vec1);
1222
1223 // Compare char[] arrays.
1224 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1225 Register limit, Register result, Register chr,
1226 XMMRegister vec1, XMMRegister vec2);
1227
1228 // Fill primitive arrays
1229 void generate_fill(BasicType t, bool aligned,
1230 Register to, Register value, Register count,
1231 Register rtmp, XMMRegister xtmp);
1232
1233 void encode_iso_array(Register src, Register dst, Register len,
1234 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1235 XMMRegister tmp4, Register tmp5, Register result);
1236
1237 #ifdef _LP64
1238 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1239 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1240 Register y, Register y_idx, Register z,
1241 Register carry, Register product,
1242 Register idx, Register kdx);
1243 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1244 Register yz_idx, Register idx,
1245 Register carry, Register product, int offset);
1246 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1247 Register carry, Register carry2,
1248 Register idx, Register jdx,
1249 Register yz_idx1, Register yz_idx2,
1250 Register tmp, Register tmp3, Register tmp4);
1251 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1252 Register yz_idx, Register idx, Register jdx,
1253 Register carry, Register product,
1254 Register carry2);
1255 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1256 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1257
1258 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1259 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1260 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1261 Register tmp2);
1262 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1263 Register rdxReg, Register raxReg);
1264 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1265 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1266 Register tmp3, Register tmp4);
1267 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1268 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1269
1270 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1271 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1272 Register raxReg);
1273 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1274 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1275 Register raxReg);
1276 #endif
1277
1278 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1279 void update_byte_crc32(Register crc, Register val, Register table);
1280 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1281 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1282 // Note on a naming convention:
1283 // Prefix w = register only used on a Westmere+ architecture
1284 // Prefix n = register only used on a Nehalem architecture
1285 #ifdef _LP64
1286 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1287 Register tmp1, Register tmp2, Register tmp3);
1288 #else
1289 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1290 Register tmp1, Register tmp2, Register tmp3,
1291 XMMRegister xtmp1, XMMRegister xtmp2);
1292 #endif
1293 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1294 Register in_out,
1295 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1296 XMMRegister w_xtmp2,
1297 Register tmp1,
1298 Register n_tmp2, Register n_tmp3);
1299 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1300 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1301 Register tmp1, Register tmp2,
1302 Register n_tmp3);
1303 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1304 Register in_out1, Register in_out2, Register in_out3,
1305 Register tmp1, Register tmp2, Register tmp3,
1306 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1307 Register tmp4, Register tmp5,
1308 Register n_tmp6);
1309 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1310 Register tmp1, Register tmp2, Register tmp3,
1311 Register tmp4, Register tmp5, Register tmp6,
1312 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1313 bool is_pclmulqdq_supported);
1314 // Fold 128-bit data chunk
1315 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1316 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1317 // Fold 8-bit data
1318 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1319 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1320
1321 #undef VIRTUAL
1322
1323 };
1324
1325 /**
1326 * class SkipIfEqual:
1327 *
1328 * Instantiating this class will result in assembly code being output that will
1329 * jump around any code emitted between the creation of the instance and it's
1330 * automatic destruction at the end of a scope block, depending on the value of
1331 * the flag passed to the constructor, which will be checked at run-time.
1332 */
1333 class SkipIfEqual {
1334 private:
1335 MacroAssembler* _masm;
1336 Label _label;
1337
1338 public:
1339 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1340 ~SkipIfEqual();
1341 };
1342
1343 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP