648 if (supports_clmul()) {
649 if (FLAG_IS_DEFAULT(UseCLMUL)) {
650 UseCLMUL = true;
651 }
652 } else if (UseCLMUL) {
653 if (!FLAG_IS_DEFAULT(UseCLMUL))
654 warning("CLMUL instructions not available on this CPU (AVX may also be required)");
655 FLAG_SET_DEFAULT(UseCLMUL, false);
656 }
657
658 if (UseCLMUL && (UseSSE > 2)) {
659 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
660 UseCRC32Intrinsics = true;
661 }
662 } else if (UseCRC32Intrinsics) {
663 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
664 warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
665 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
666 }
667
668 // The AES intrinsic stubs require AES instruction support (of course)
669 // but also require sse3 mode for instructions it use.
670 if (UseAES && (UseSSE > 2)) {
671 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
672 UseAESIntrinsics = true;
673 }
674 } else if (UseAESIntrinsics) {
675 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
676 warning("AES intrinsics are not available on this CPU");
677 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
678 }
679
680 // GHASH/GCM intrinsics
681 if (UseCLMUL && (UseSSE > 2)) {
682 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
683 UseGHASHIntrinsics = true;
684 }
685 } else if (UseGHASHIntrinsics) {
686 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
687 warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
689 }
690
691 if (UseSHA) {
692 warning("SHA instructions are not available on this CPU");
693 FLAG_SET_DEFAULT(UseSHA, false);
694 }
695
696 if (UseSHA1Intrinsics) {
697 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
698 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
699 }
700
701 if (UseSHA256Intrinsics) {
702 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
703 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
704 }
705
706 if (UseSHA512Intrinsics) {
707 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
708 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
709 }
710
711 if (UseCRC32CIntrinsics) {
712 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics))
713 warning("CRC32C intrinsics are not available on this CPU");
714 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
715 }
716
717 if (UseAdler32Intrinsics) {
718 warning("Adler32Intrinsics not available on this CPU.");
719 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
720 }
721
722 // Adjust RTM (Restricted Transactional Memory) flags
723 if (!supports_rtm() && UseRTMLocking) {
724 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
725 // setting during arguments processing. See use_biased_locking().
726 // VM_Version_init() is executed after UseBiasedLocking is used
727 // in Thread::allocate().
728 vm_exit_during_initialization("RTM instructions are not available on this CPU");
729 }
730
731 #if INCLUDE_RTM_OPT
732 if (UseRTMLocking) {
733 if (is_intel_family_core()) {
734 if ((_model == CPU_MODEL_HASWELL_E3) ||
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648 if (supports_clmul()) {
649 if (FLAG_IS_DEFAULT(UseCLMUL)) {
650 UseCLMUL = true;
651 }
652 } else if (UseCLMUL) {
653 if (!FLAG_IS_DEFAULT(UseCLMUL))
654 warning("CLMUL instructions not available on this CPU (AVX may also be required)");
655 FLAG_SET_DEFAULT(UseCLMUL, false);
656 }
657
658 if (UseCLMUL && (UseSSE > 2)) {
659 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
660 UseCRC32Intrinsics = true;
661 }
662 } else if (UseCRC32Intrinsics) {
663 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
664 warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
665 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
666 }
667
668 if (supports_sse4_2()) {
669 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
670 UseCRC32CIntrinsics = true;
671 }
672 }
673 else if (UseCRC32CIntrinsics) {
674 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
675 warning("CRC32C intrinsics are not available on this CPU");
676 }
677 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
678 }
679
680 // The AES intrinsic stubs require AES instruction support (of course)
681 // but also require sse3 mode for instructions it use.
682 if (UseAES && (UseSSE > 2)) {
683 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
684 UseAESIntrinsics = true;
685 }
686 } else if (UseAESIntrinsics) {
687 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
688 warning("AES intrinsics are not available on this CPU");
689 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
690 }
691
692 // GHASH/GCM intrinsics
693 if (UseCLMUL && (UseSSE > 2)) {
694 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
695 UseGHASHIntrinsics = true;
696 }
697 } else if (UseGHASHIntrinsics) {
698 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
699 warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
701 }
702
703 if (UseSHA) {
704 warning("SHA instructions are not available on this CPU");
705 FLAG_SET_DEFAULT(UseSHA, false);
706 }
707
708 if (UseSHA1Intrinsics) {
709 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
710 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
711 }
712
713 if (UseSHA256Intrinsics) {
714 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
715 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
716 }
717
718 if (UseSHA512Intrinsics) {
719 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
720 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
721 }
722
723 if (UseAdler32Intrinsics) {
724 warning("Adler32Intrinsics not available on this CPU.");
725 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
726 }
727
728 // Adjust RTM (Restricted Transactional Memory) flags
729 if (!supports_rtm() && UseRTMLocking) {
730 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
731 // setting during arguments processing. See use_biased_locking().
732 // VM_Version_init() is executed after UseBiasedLocking is used
733 // in Thread::allocate().
734 vm_exit_during_initialization("RTM instructions are not available on this CPU");
735 }
736
737 #if INCLUDE_RTM_OPT
738 if (UseRTMLocking) {
739 if (is_intel_family_core()) {
740 if ((_model == CPU_MODEL_HASWELL_E3) ||
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