1 /* 2 * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "compiler/compileLog.hpp" 27 #include "compiler/oopMap.hpp" 28 #include "memory/allocation.inline.hpp" 29 #include "opto/addnode.hpp" 30 #include "opto/block.hpp" 31 #include "opto/callnode.hpp" 32 #include "opto/cfgnode.hpp" 33 #include "opto/chaitin.hpp" 34 #include "opto/coalesce.hpp" 35 #include "opto/connode.hpp" 36 #include "opto/idealGraphPrinter.hpp" 37 #include "opto/indexSet.hpp" 38 #include "opto/machnode.hpp" 39 #include "opto/memnode.hpp" 40 #include "opto/movenode.hpp" 41 #include "opto/opcodes.hpp" 42 #include "opto/rootnode.hpp" 43 44 #ifndef PRODUCT 45 void LRG::dump() const { 46 ttyLocker ttyl; 47 tty->print("%d ",num_regs()); 48 _mask.dump(); 49 if( _msize_valid ) { 50 if( mask_size() == compute_mask_size() ) tty->print(", #%d ",_mask_size); 51 else tty->print(", #!!!_%d_vs_%d ",_mask_size,_mask.Size()); 52 } else { 53 tty->print(", #?(%d) ",_mask.Size()); 54 } 55 56 tty->print("EffDeg: "); 57 if( _degree_valid ) tty->print( "%d ", _eff_degree ); 58 else tty->print("? "); 59 60 if( is_multidef() ) { 61 tty->print("MultiDef "); 62 if (_defs != NULL) { 63 tty->print("("); 64 for (int i = 0; i < _defs->length(); i++) { 65 tty->print("N%d ", _defs->at(i)->_idx); 66 } 67 tty->print(") "); 68 } 69 } 70 else if( _def == 0 ) tty->print("Dead "); 71 else tty->print("Def: N%d ",_def->_idx); 72 73 tty->print("Cost:%4.2g Area:%4.2g Score:%4.2g ",_cost,_area, score()); 74 // Flags 75 if( _is_oop ) tty->print("Oop "); 76 if( _is_float ) tty->print("Float "); 77 if( _is_vector ) tty->print("Vector "); 78 if( _was_spilled1 ) tty->print("Spilled "); 79 if( _was_spilled2 ) tty->print("Spilled2 "); 80 if( _direct_conflict ) tty->print("Direct_conflict "); 81 if( _fat_proj ) tty->print("Fat "); 82 if( _was_lo ) tty->print("Lo "); 83 if( _has_copy ) tty->print("Copy "); 84 if( _at_risk ) tty->print("Risk "); 85 86 if( _must_spill ) tty->print("Must_spill "); 87 if( _is_bound ) tty->print("Bound "); 88 if( _msize_valid ) { 89 if( _degree_valid && lo_degree() ) tty->print("Trivial "); 90 } 91 92 tty->cr(); 93 } 94 #endif 95 96 // Compute score from cost and area. Low score is best to spill. 97 static double raw_score( double cost, double area ) { 98 return cost - (area*RegisterCostAreaRatio) * 1.52588e-5; 99 } 100 101 double LRG::score() const { 102 // Scale _area by RegisterCostAreaRatio/64K then subtract from cost. 103 // Bigger area lowers score, encourages spilling this live range. 104 // Bigger cost raise score, prevents spilling this live range. 105 // (Note: 1/65536 is the magic constant below; I dont trust the C optimizer 106 // to turn a divide by a constant into a multiply by the reciprical). 107 double score = raw_score( _cost, _area); 108 109 // Account for area. Basically, LRGs covering large areas are better 110 // to spill because more other LRGs get freed up. 111 if( _area == 0.0 ) // No area? Then no progress to spill 112 return 1e35; 113 114 if( _was_spilled2 ) // If spilled once before, we are unlikely 115 return score + 1e30; // to make progress again. 116 117 if( _cost >= _area*3.0 ) // Tiny area relative to cost 118 return score + 1e17; // Probably no progress to spill 119 120 if( (_cost+_cost) >= _area*3.0 ) // Small area relative to cost 121 return score + 1e10; // Likely no progress to spill 122 123 return score; 124 } 125 126 #define NUMBUCKS 3 127 128 // Straight out of Tarjan's union-find algorithm 129 uint LiveRangeMap::find_compress(uint lrg) { 130 uint cur = lrg; 131 uint next = _uf_map.at(cur); 132 while (next != cur) { // Scan chain of equivalences 133 assert( next < cur, "always union smaller"); 134 cur = next; // until find a fixed-point 135 next = _uf_map.at(cur); 136 } 137 138 // Core of union-find algorithm: update chain of 139 // equivalences to be equal to the root. 140 while (lrg != next) { 141 uint tmp = _uf_map.at(lrg); 142 _uf_map.at_put(lrg, next); 143 lrg = tmp; 144 } 145 return lrg; 146 } 147 148 // Reset the Union-Find map to identity 149 void LiveRangeMap::reset_uf_map(uint max_lrg_id) { 150 _max_lrg_id= max_lrg_id; 151 // Force the Union-Find mapping to be at least this large 152 _uf_map.at_put_grow(_max_lrg_id, 0); 153 // Initialize it to be the ID mapping. 154 for (uint i = 0; i < _max_lrg_id; ++i) { 155 _uf_map.at_put(i, i); 156 } 157 } 158 159 // Make all Nodes map directly to their final live range; no need for 160 // the Union-Find mapping after this call. 161 void LiveRangeMap::compress_uf_map_for_nodes() { 162 // For all Nodes, compress mapping 163 uint unique = _names.length(); 164 for (uint i = 0; i < unique; ++i) { 165 uint lrg = _names.at(i); 166 uint compressed_lrg = find(lrg); 167 if (lrg != compressed_lrg) { 168 _names.at_put(i, compressed_lrg); 169 } 170 } 171 } 172 173 // Like Find above, but no path compress, so bad asymptotic behavior 174 uint LiveRangeMap::find_const(uint lrg) const { 175 if (!lrg) { 176 return lrg; // Ignore the zero LRG 177 } 178 179 // Off the end? This happens during debugging dumps when you got 180 // brand new live ranges but have not told the allocator yet. 181 if (lrg >= _max_lrg_id) { 182 return lrg; 183 } 184 185 uint next = _uf_map.at(lrg); 186 while (next != lrg) { // Scan chain of equivalences 187 assert(next < lrg, "always union smaller"); 188 lrg = next; // until find a fixed-point 189 next = _uf_map.at(lrg); 190 } 191 return next; 192 } 193 194 PhaseChaitin::PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher) 195 : PhaseRegAlloc(unique, cfg, matcher, 196 #ifndef PRODUCT 197 print_chaitin_statistics 198 #else 199 NULL 200 #endif 201 ) 202 , _lrg_map(Thread::current()->resource_area(), unique) 203 , _live(0) 204 , _spilled_once(Thread::current()->resource_area()) 205 , _spilled_twice(Thread::current()->resource_area()) 206 , _lo_degree(0), _lo_stk_degree(0), _hi_degree(0), _simplified(0) 207 , _oldphi(unique) 208 #ifndef PRODUCT 209 , _trace_spilling(TraceSpilling || C->method_has_option("TraceSpilling")) 210 #endif 211 { 212 Compile::TracePhase tp("ctorChaitin", &timers[_t_ctorChaitin]); 213 214 _high_frequency_lrg = MIN2(double(OPTO_LRG_HIGH_FREQ), _cfg.get_outer_loop_frequency()); 215 216 // Build a list of basic blocks, sorted by frequency 217 _blks = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks()); 218 // Experiment with sorting strategies to speed compilation 219 double cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket 220 Block **buckets[NUMBUCKS]; // Array of buckets 221 uint buckcnt[NUMBUCKS]; // Array of bucket counters 222 double buckval[NUMBUCKS]; // Array of bucket value cutoffs 223 for (uint i = 0; i < NUMBUCKS; i++) { 224 buckets[i] = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks()); 225 buckcnt[i] = 0; 226 // Bump by three orders of magnitude each time 227 cutoff *= 0.001; 228 buckval[i] = cutoff; 229 for (uint j = 0; j < _cfg.number_of_blocks(); j++) { 230 buckets[i][j] = NULL; 231 } 232 } 233 // Sort blocks into buckets 234 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { 235 for (uint j = 0; j < NUMBUCKS; j++) { 236 if ((j == NUMBUCKS - 1) || (_cfg.get_block(i)->_freq > buckval[j])) { 237 // Assign block to end of list for appropriate bucket 238 buckets[j][buckcnt[j]++] = _cfg.get_block(i); 239 break; // kick out of inner loop 240 } 241 } 242 } 243 // Dump buckets into final block array 244 uint blkcnt = 0; 245 for (uint i = 0; i < NUMBUCKS; i++) { 246 for (uint j = 0; j < buckcnt[i]; j++) { 247 _blks[blkcnt++] = buckets[i][j]; 248 } 249 } 250 251 assert(blkcnt == _cfg.number_of_blocks(), "Block array not totally filled"); 252 } 253 254 // union 2 sets together. 255 void PhaseChaitin::Union( const Node *src_n, const Node *dst_n ) { 256 uint src = _lrg_map.find(src_n); 257 uint dst = _lrg_map.find(dst_n); 258 assert(src, ""); 259 assert(dst, ""); 260 assert(src < _lrg_map.max_lrg_id(), "oob"); 261 assert(dst < _lrg_map.max_lrg_id(), "oob"); 262 assert(src < dst, "always union smaller"); 263 _lrg_map.uf_map(dst, src); 264 } 265 266 void PhaseChaitin::new_lrg(const Node *x, uint lrg) { 267 // Make the Node->LRG mapping 268 _lrg_map.extend(x->_idx,lrg); 269 // Make the Union-Find mapping an identity function 270 _lrg_map.uf_extend(lrg, lrg); 271 } 272 273 274 int PhaseChaitin::clone_projs(Block* b, uint idx, Node* orig, Node* copy, uint& max_lrg_id) { 275 assert(b->find_node(copy) == (idx - 1), "incorrect insert index for copy kill projections"); 276 DEBUG_ONLY( Block* borig = _cfg.get_block_for_node(orig); ) 277 int found_projs = 0; 278 uint cnt = orig->outcnt(); 279 for (uint i = 0; i < cnt; i++) { 280 Node* proj = orig->raw_out(i); 281 if (proj->is_MachProj()) { 282 assert(proj->outcnt() == 0, "only kill projections are expected here"); 283 assert(_cfg.get_block_for_node(proj) == borig, "incorrect block for kill projections"); 284 found_projs++; 285 // Copy kill projections after the cloned node 286 Node* kills = proj->clone(); 287 kills->set_req(0, copy); 288 b->insert_node(kills, idx++); 289 _cfg.map_node_to_block(kills, b); 290 new_lrg(kills, max_lrg_id++); 291 } 292 } 293 return found_projs; 294 } 295 296 // Renumber the live ranges to compact them. Makes the IFG smaller. 297 void PhaseChaitin::compact() { 298 Compile::TracePhase tp("chaitinCompact", &timers[_t_chaitinCompact]); 299 300 // Current the _uf_map contains a series of short chains which are headed 301 // by a self-cycle. All the chains run from big numbers to little numbers. 302 // The Find() call chases the chains & shortens them for the next Find call. 303 // We are going to change this structure slightly. Numbers above a moving 304 // wave 'i' are unchanged. Numbers below 'j' point directly to their 305 // compacted live range with no further chaining. There are no chains or 306 // cycles below 'i', so the Find call no longer works. 307 uint j=1; 308 uint i; 309 for (i = 1; i < _lrg_map.max_lrg_id(); i++) { 310 uint lr = _lrg_map.uf_live_range_id(i); 311 // Ignore unallocated live ranges 312 if (!lr) { 313 continue; 314 } 315 assert(lr <= i, ""); 316 _lrg_map.uf_map(i, ( lr == i ) ? j++ : _lrg_map.uf_live_range_id(lr)); 317 } 318 // Now change the Node->LR mapping to reflect the compacted names 319 uint unique = _lrg_map.size(); 320 for (i = 0; i < unique; i++) { 321 uint lrg_id = _lrg_map.live_range_id(i); 322 _lrg_map.map(i, _lrg_map.uf_live_range_id(lrg_id)); 323 } 324 325 // Reset the Union-Find mapping 326 _lrg_map.reset_uf_map(j); 327 } 328 329 void PhaseChaitin::Register_Allocate() { 330 331 // Above the OLD FP (and in registers) are the incoming arguments. Stack 332 // slots in this area are called "arg_slots". Above the NEW FP (and in 333 // registers) is the outgoing argument area; above that is the spill/temp 334 // area. These are all "frame_slots". Arg_slots start at the zero 335 // stack_slots and count up to the known arg_size. Frame_slots start at 336 // the stack_slot #arg_size and go up. After allocation I map stack 337 // slots to actual offsets. Stack-slots in the arg_slot area are biased 338 // by the frame_size; stack-slots in the frame_slot area are biased by 0. 339 340 _trip_cnt = 0; 341 _alternate = 0; 342 _matcher._allocation_started = true; 343 344 ResourceArea split_arena; // Arena for Split local resources 345 ResourceArea live_arena; // Arena for liveness & IFG info 346 ResourceMark rm(&live_arena); 347 348 // Need live-ness for the IFG; need the IFG for coalescing. If the 349 // liveness is JUST for coalescing, then I can get some mileage by renaming 350 // all copy-related live ranges low and then using the max copy-related 351 // live range as a cut-off for LIVE and the IFG. In other words, I can 352 // build a subset of LIVE and IFG just for copies. 353 PhaseLive live(_cfg, _lrg_map.names(), &live_arena); 354 355 // Need IFG for coalescing and coloring 356 PhaseIFG ifg(&live_arena); 357 _ifg = &ifg; 358 359 // Come out of SSA world to the Named world. Assign (virtual) registers to 360 // Nodes. Use the same register for all inputs and the output of PhiNodes 361 // - effectively ending SSA form. This requires either coalescing live 362 // ranges or inserting copies. For the moment, we insert "virtual copies" 363 // - we pretend there is a copy prior to each Phi in predecessor blocks. 364 // We will attempt to coalesce such "virtual copies" before we manifest 365 // them for real. 366 de_ssa(); 367 368 #ifdef ASSERT 369 // Veify the graph before RA. 370 verify(&live_arena); 371 #endif 372 373 { 374 Compile::TracePhase tp("computeLive", &timers[_t_computeLive]); 375 _live = NULL; // Mark live as being not available 376 rm.reset_to_mark(); // Reclaim working storage 377 IndexSet::reset_memory(C, &live_arena); 378 ifg.init(_lrg_map.max_lrg_id()); // Empty IFG 379 gather_lrg_masks( false ); // Collect LRG masks 380 live.compute(_lrg_map.max_lrg_id()); // Compute liveness 381 _live = &live; // Mark LIVE as being available 382 } 383 384 // Base pointers are currently "used" by instructions which define new 385 // derived pointers. This makes base pointers live up to the where the 386 // derived pointer is made, but not beyond. Really, they need to be live 387 // across any GC point where the derived value is live. So this code looks 388 // at all the GC points, and "stretches" the live range of any base pointer 389 // to the GC point. 390 if (stretch_base_pointer_live_ranges(&live_arena)) { 391 Compile::TracePhase tp("computeLive (sbplr)", &timers[_t_computeLive]); 392 // Since some live range stretched, I need to recompute live 393 _live = NULL; 394 rm.reset_to_mark(); // Reclaim working storage 395 IndexSet::reset_memory(C, &live_arena); 396 ifg.init(_lrg_map.max_lrg_id()); 397 gather_lrg_masks(false); 398 live.compute(_lrg_map.max_lrg_id()); 399 _live = &live; 400 } 401 // Create the interference graph using virtual copies 402 build_ifg_virtual(); // Include stack slots this time 403 404 // The IFG is/was triangular. I am 'squaring it up' so Union can run 405 // faster. Union requires a 'for all' operation which is slow on the 406 // triangular adjacency matrix (quick reminder: the IFG is 'sparse' - 407 // meaning I can visit all the Nodes neighbors less than a Node in time 408 // O(# of neighbors), but I have to visit all the Nodes greater than a 409 // given Node and search them for an instance, i.e., time O(#MaxLRG)). 410 _ifg->SquareUp(); 411 412 // Aggressive (but pessimistic) copy coalescing. 413 // This pass works on virtual copies. Any virtual copies which are not 414 // coalesced get manifested as actual copies 415 { 416 Compile::TracePhase tp("chaitinCoalesce1", &timers[_t_chaitinCoalesce1]); 417 418 PhaseAggressiveCoalesce coalesce(*this); 419 coalesce.coalesce_driver(); 420 // Insert un-coalesced copies. Visit all Phis. Where inputs to a Phi do 421 // not match the Phi itself, insert a copy. 422 coalesce.insert_copies(_matcher); 423 if (C->failing()) { 424 return; 425 } 426 } 427 428 // After aggressive coalesce, attempt a first cut at coloring. 429 // To color, we need the IFG and for that we need LIVE. 430 { 431 Compile::TracePhase tp("computeLive", &timers[_t_computeLive]); 432 _live = NULL; 433 rm.reset_to_mark(); // Reclaim working storage 434 IndexSet::reset_memory(C, &live_arena); 435 ifg.init(_lrg_map.max_lrg_id()); 436 gather_lrg_masks( true ); 437 live.compute(_lrg_map.max_lrg_id()); 438 _live = &live; 439 } 440 441 // Build physical interference graph 442 uint must_spill = 0; 443 must_spill = build_ifg_physical(&live_arena); 444 // If we have a guaranteed spill, might as well spill now 445 if (must_spill) { 446 if(!_lrg_map.max_lrg_id()) { 447 return; 448 } 449 // Bail out if unique gets too large (ie - unique > MaxNodeLimit) 450 C->check_node_count(10*must_spill, "out of nodes before split"); 451 if (C->failing()) { 452 return; 453 } 454 455 uint new_max_lrg_id = Split(_lrg_map.max_lrg_id(), &split_arena); // Split spilling LRG everywhere 456 _lrg_map.set_max_lrg_id(new_max_lrg_id); 457 // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor) 458 // or we failed to split 459 C->check_node_count(2*NodeLimitFudgeFactor, "out of nodes after physical split"); 460 if (C->failing()) { 461 return; 462 } 463 464 NOT_PRODUCT(C->verify_graph_edges();) 465 466 compact(); // Compact LRGs; return new lower max lrg 467 468 { 469 Compile::TracePhase tp("computeLive", &timers[_t_computeLive]); 470 _live = NULL; 471 rm.reset_to_mark(); // Reclaim working storage 472 IndexSet::reset_memory(C, &live_arena); 473 ifg.init(_lrg_map.max_lrg_id()); // Build a new interference graph 474 gather_lrg_masks( true ); // Collect intersect mask 475 live.compute(_lrg_map.max_lrg_id()); // Compute LIVE 476 _live = &live; 477 } 478 build_ifg_physical(&live_arena); 479 _ifg->SquareUp(); 480 _ifg->Compute_Effective_Degree(); 481 // Only do conservative coalescing if requested 482 if (OptoCoalesce) { 483 Compile::TracePhase tp("chaitinCoalesce2", &timers[_t_chaitinCoalesce2]); 484 // Conservative (and pessimistic) copy coalescing of those spills 485 PhaseConservativeCoalesce coalesce(*this); 486 // If max live ranges greater than cutoff, don't color the stack. 487 // This cutoff can be larger than below since it is only done once. 488 coalesce.coalesce_driver(); 489 } 490 _lrg_map.compress_uf_map_for_nodes(); 491 492 #ifdef ASSERT 493 verify(&live_arena, true); 494 #endif 495 } else { 496 ifg.SquareUp(); 497 ifg.Compute_Effective_Degree(); 498 #ifdef ASSERT 499 set_was_low(); 500 #endif 501 } 502 503 // Prepare for Simplify & Select 504 cache_lrg_info(); // Count degree of LRGs 505 506 // Simplify the InterFerence Graph by removing LRGs of low degree. 507 // LRGs of low degree are trivially colorable. 508 Simplify(); 509 510 // Select colors by re-inserting LRGs back into the IFG in reverse order. 511 // Return whether or not something spills. 512 uint spills = Select( ); 513 514 // If we spill, split and recycle the entire thing 515 while( spills ) { 516 if( _trip_cnt++ > 24 ) { 517 DEBUG_ONLY( dump_for_spill_split_recycle(); ) 518 if( _trip_cnt > 27 ) { 519 C->record_method_not_compilable("failed spill-split-recycle sanity check"); 520 return; 521 } 522 } 523 524 if (!_lrg_map.max_lrg_id()) { 525 return; 526 } 527 uint new_max_lrg_id = Split(_lrg_map.max_lrg_id(), &split_arena); // Split spilling LRG everywhere 528 _lrg_map.set_max_lrg_id(new_max_lrg_id); 529 // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor) 530 C->check_node_count(2 * NodeLimitFudgeFactor, "out of nodes after split"); 531 if (C->failing()) { 532 return; 533 } 534 535 compact(); // Compact LRGs; return new lower max lrg 536 537 // Nuke the live-ness and interference graph and LiveRanGe info 538 { 539 Compile::TracePhase tp("computeLive", &timers[_t_computeLive]); 540 _live = NULL; 541 rm.reset_to_mark(); // Reclaim working storage 542 IndexSet::reset_memory(C, &live_arena); 543 ifg.init(_lrg_map.max_lrg_id()); 544 545 // Create LiveRanGe array. 546 // Intersect register masks for all USEs and DEFs 547 gather_lrg_masks(true); 548 live.compute(_lrg_map.max_lrg_id()); 549 _live = &live; 550 } 551 must_spill = build_ifg_physical(&live_arena); 552 _ifg->SquareUp(); 553 _ifg->Compute_Effective_Degree(); 554 555 // Only do conservative coalescing if requested 556 if (OptoCoalesce) { 557 Compile::TracePhase tp("chaitinCoalesce3", &timers[_t_chaitinCoalesce3]); 558 // Conservative (and pessimistic) copy coalescing 559 PhaseConservativeCoalesce coalesce(*this); 560 // Check for few live ranges determines how aggressive coalesce is. 561 coalesce.coalesce_driver(); 562 } 563 _lrg_map.compress_uf_map_for_nodes(); 564 #ifdef ASSERT 565 verify(&live_arena, true); 566 #endif 567 cache_lrg_info(); // Count degree of LRGs 568 569 // Simplify the InterFerence Graph by removing LRGs of low degree. 570 // LRGs of low degree are trivially colorable. 571 Simplify(); 572 573 // Select colors by re-inserting LRGs back into the IFG in reverse order. 574 // Return whether or not something spills. 575 spills = Select(); 576 } 577 578 // Count number of Simplify-Select trips per coloring success. 579 _allocator_attempts += _trip_cnt + 1; 580 _allocator_successes += 1; 581 582 // Peephole remove copies 583 post_allocate_copy_removal(); 584 585 // Merge multidefs if multiple defs representing the same value are used in a single block. 586 merge_multidefs(); 587 588 #ifdef ASSERT 589 // Veify the graph after RA. 590 verify(&live_arena); 591 #endif 592 593 // max_reg is past the largest *register* used. 594 // Convert that to a frame_slot number. 595 if (_max_reg <= _matcher._new_SP) { 596 _framesize = C->out_preserve_stack_slots(); 597 } 598 else { 599 _framesize = _max_reg -_matcher._new_SP; 600 } 601 assert((int)(_matcher._new_SP+_framesize) >= (int)_matcher._out_arg_limit, "framesize must be large enough"); 602 603 // This frame must preserve the required fp alignment 604 _framesize = round_to(_framesize, Matcher::stack_alignment_in_slots()); 605 assert(_framesize <= 1000000, "sanity check"); 606 #ifndef PRODUCT 607 _total_framesize += _framesize; 608 if ((int)_framesize > _max_framesize) { 609 _max_framesize = _framesize; 610 } 611 #endif 612 613 // Convert CISC spills 614 fixup_spills(); 615 616 // Log regalloc results 617 CompileLog* log = Compile::current()->log(); 618 if (log != NULL) { 619 log->elem("regalloc attempts='%d' success='%d'", _trip_cnt, !C->failing()); 620 } 621 622 if (C->failing()) { 623 return; 624 } 625 626 NOT_PRODUCT(C->verify_graph_edges();) 627 628 // Move important info out of the live_arena to longer lasting storage. 629 alloc_node_regs(_lrg_map.size()); 630 for (uint i=0; i < _lrg_map.size(); i++) { 631 if (_lrg_map.live_range_id(i)) { // Live range associated with Node? 632 LRG &lrg = lrgs(_lrg_map.live_range_id(i)); 633 if (!lrg.alive()) { 634 set_bad(i); 635 } else if (lrg.num_regs() == 1) { 636 set1(i, lrg.reg()); 637 } else { // Must be a register-set 638 if (!lrg._fat_proj) { // Must be aligned adjacent register set 639 // Live ranges record the highest register in their mask. 640 // We want the low register for the AD file writer's convenience. 641 OptoReg::Name hi = lrg.reg(); // Get hi register 642 OptoReg::Name lo = OptoReg::add(hi, (1-lrg.num_regs())); // Find lo 643 // We have to use pair [lo,lo+1] even for wide vectors because 644 // the rest of code generation works only with pairs. It is safe 645 // since for registers encoding only 'lo' is used. 646 // Second reg from pair is used in ScheduleAndBundle on SPARC where 647 // vector max size is 8 which corresponds to registers pair. 648 // It is also used in BuildOopMaps but oop operations are not 649 // vectorized. 650 set2(i, lo); 651 } else { // Misaligned; extract 2 bits 652 OptoReg::Name hi = lrg.reg(); // Get hi register 653 lrg.Remove(hi); // Yank from mask 654 int lo = lrg.mask().find_first_elem(); // Find lo 655 set_pair(i, hi, lo); 656 } 657 } 658 if( lrg._is_oop ) _node_oops.set(i); 659 } else { 660 set_bad(i); 661 } 662 } 663 664 // Done! 665 _live = NULL; 666 _ifg = NULL; 667 C->set_indexSet_arena(NULL); // ResourceArea is at end of scope 668 } 669 670 void PhaseChaitin::de_ssa() { 671 // Set initial Names for all Nodes. Most Nodes get the virtual register 672 // number. A few get the ZERO live range number. These do not 673 // get allocated, but instead rely on correct scheduling to ensure that 674 // only one instance is simultaneously live at a time. 675 uint lr_counter = 1; 676 for( uint i = 0; i < _cfg.number_of_blocks(); i++ ) { 677 Block* block = _cfg.get_block(i); 678 uint cnt = block->number_of_nodes(); 679 680 // Handle all the normal Nodes in the block 681 for( uint j = 0; j < cnt; j++ ) { 682 Node *n = block->get_node(j); 683 // Pre-color to the zero live range, or pick virtual register 684 const RegMask &rm = n->out_RegMask(); 685 _lrg_map.map(n->_idx, rm.is_NotEmpty() ? lr_counter++ : 0); 686 } 687 } 688 689 // Reset the Union-Find mapping to be identity 690 _lrg_map.reset_uf_map(lr_counter); 691 } 692 693 694 // Gather LiveRanGe information, including register masks. Modification of 695 // cisc spillable in_RegMasks should not be done before AggressiveCoalesce. 696 void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) { 697 698 // Nail down the frame pointer live range 699 uint fp_lrg = _lrg_map.live_range_id(_cfg.get_root_node()->in(1)->in(TypeFunc::FramePtr)); 700 lrgs(fp_lrg)._cost += 1e12; // Cost is infinite 701 702 // For all blocks 703 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { 704 Block* block = _cfg.get_block(i); 705 706 // For all instructions 707 for (uint j = 1; j < block->number_of_nodes(); j++) { 708 Node* n = block->get_node(j); 709 uint input_edge_start =1; // Skip control most nodes 710 if (n->is_Mach()) { 711 input_edge_start = n->as_Mach()->oper_input_base(); 712 } 713 uint idx = n->is_Copy(); 714 715 // Get virtual register number, same as LiveRanGe index 716 uint vreg = _lrg_map.live_range_id(n); 717 LRG& lrg = lrgs(vreg); 718 if (vreg) { // No vreg means un-allocable (e.g. memory) 719 720 // Collect has-copy bit 721 if (idx) { 722 lrg._has_copy = 1; 723 uint clidx = _lrg_map.live_range_id(n->in(idx)); 724 LRG& copy_src = lrgs(clidx); 725 copy_src._has_copy = 1; 726 } 727 728 // Check for float-vs-int live range (used in register-pressure 729 // calculations) 730 const Type *n_type = n->bottom_type(); 731 if (n_type->is_floatingpoint()) { 732 lrg._is_float = 1; 733 } 734 735 // Check for twice prior spilling. Once prior spilling might have 736 // spilled 'soft', 2nd prior spill should have spilled 'hard' and 737 // further spilling is unlikely to make progress. 738 if (_spilled_once.test(n->_idx)) { 739 lrg._was_spilled1 = 1; 740 if (_spilled_twice.test(n->_idx)) { 741 lrg._was_spilled2 = 1; 742 } 743 } 744 745 #ifndef PRODUCT 746 if (trace_spilling() && lrg._def != NULL) { 747 // collect defs for MultiDef printing 748 if (lrg._defs == NULL) { 749 lrg._defs = new (_ifg->_arena) GrowableArray<Node*>(_ifg->_arena, 2, 0, NULL); 750 lrg._defs->append(lrg._def); 751 } 752 lrg._defs->append(n); 753 } 754 #endif 755 756 // Check for a single def LRG; these can spill nicely 757 // via rematerialization. Flag as NULL for no def found 758 // yet, or 'n' for single def or -1 for many defs. 759 lrg._def = lrg._def ? NodeSentinel : n; 760 761 // Limit result register mask to acceptable registers 762 const RegMask &rm = n->out_RegMask(); 763 lrg.AND( rm ); 764 765 int ireg = n->ideal_reg(); 766 assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP, 767 "oops must be in Op_RegP's" ); 768 769 // Check for vector live range (only if vector register is used). 770 // On SPARC vector uses RegD which could be misaligned so it is not 771 // processes as vector in RA. 772 if (RegMask::is_vector(ireg)) 773 lrg._is_vector = 1; 774 assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD || ireg == Op_RegL, 775 "vector must be in vector registers"); 776 777 // Check for bound register masks 778 const RegMask &lrgmask = lrg.mask(); 779 if (lrgmask.is_bound(ireg)) { 780 lrg._is_bound = 1; 781 } 782 783 // Check for maximum frequency value 784 if (lrg._maxfreq < block->_freq) { 785 lrg._maxfreq = block->_freq; 786 } 787 788 // Check for oop-iness, or long/double 789 // Check for multi-kill projection 790 switch (ireg) { 791 case MachProjNode::fat_proj: 792 // Fat projections have size equal to number of registers killed 793 lrg.set_num_regs(rm.Size()); 794 lrg.set_reg_pressure(lrg.num_regs()); 795 lrg._fat_proj = 1; 796 lrg._is_bound = 1; 797 break; 798 case Op_RegP: 799 #ifdef _LP64 800 lrg.set_num_regs(2); // Size is 2 stack words 801 #else 802 lrg.set_num_regs(1); // Size is 1 stack word 803 #endif 804 // Register pressure is tracked relative to the maximum values 805 // suggested for that platform, INTPRESSURE and FLOATPRESSURE, 806 // and relative to other types which compete for the same regs. 807 // 808 // The following table contains suggested values based on the 809 // architectures as defined in each .ad file. 810 // INTPRESSURE and FLOATPRESSURE may be tuned differently for 811 // compile-speed or performance. 812 // Note1: 813 // SPARC and SPARCV9 reg_pressures are at 2 instead of 1 814 // since .ad registers are defined as high and low halves. 815 // These reg_pressure values remain compatible with the code 816 // in is_high_pressure() which relates get_invalid_mask_size(), 817 // Block::_reg_pressure and INTPRESSURE, FLOATPRESSURE. 818 // Note2: 819 // SPARC -d32 has 24 registers available for integral values, 820 // but only 10 of these are safe for 64-bit longs. 821 // Using set_reg_pressure(2) for both int and long means 822 // the allocator will believe it can fit 26 longs into 823 // registers. Using 2 for longs and 1 for ints means the 824 // allocator will attempt to put 52 integers into registers. 825 // The settings below limit this problem to methods with 826 // many long values which are being run on 32-bit SPARC. 827 // 828 // ------------------- reg_pressure -------------------- 829 // Each entry is reg_pressure_per_value,number_of_regs 830 // RegL RegI RegFlags RegF RegD INTPRESSURE FLOATPRESSURE 831 // IA32 2 1 1 1 1 6 6 832 // IA64 1 1 1 1 1 50 41 833 // SPARC 2 2 2 2 2 48 (24) 52 (26) 834 // SPARCV9 2 2 2 2 2 48 (24) 52 (26) 835 // AMD64 1 1 1 1 1 14 15 836 // ----------------------------------------------------- 837 #if defined(SPARC) 838 lrg.set_reg_pressure(2); // use for v9 as well 839 #else 840 lrg.set_reg_pressure(1); // normally one value per register 841 #endif 842 if( n_type->isa_oop_ptr() ) { 843 lrg._is_oop = 1; 844 } 845 break; 846 case Op_RegL: // Check for long or double 847 case Op_RegD: 848 lrg.set_num_regs(2); 849 // Define platform specific register pressure 850 #if defined(SPARC) || defined(ARM32) 851 lrg.set_reg_pressure(2); 852 #elif defined(IA32) 853 if( ireg == Op_RegL ) { 854 lrg.set_reg_pressure(2); 855 } else { 856 lrg.set_reg_pressure(1); 857 } 858 #else 859 lrg.set_reg_pressure(1); // normally one value per register 860 #endif 861 // If this def of a double forces a mis-aligned double, 862 // flag as '_fat_proj' - really flag as allowing misalignment 863 // AND changes how we count interferences. A mis-aligned 864 // double can interfere with TWO aligned pairs, or effectively 865 // FOUR registers! 866 if (rm.is_misaligned_pair()) { 867 lrg._fat_proj = 1; 868 lrg._is_bound = 1; 869 } 870 break; 871 case Op_RegF: 872 case Op_RegI: 873 case Op_RegN: 874 case Op_RegFlags: 875 case 0: // not an ideal register 876 lrg.set_num_regs(1); 877 #ifdef SPARC 878 lrg.set_reg_pressure(2); 879 #else 880 lrg.set_reg_pressure(1); 881 #endif 882 break; 883 case Op_VecS: 884 assert(Matcher::vector_size_supported(T_BYTE,4), "sanity"); 885 assert(RegMask::num_registers(Op_VecS) == RegMask::SlotsPerVecS, "sanity"); 886 lrg.set_num_regs(RegMask::SlotsPerVecS); 887 lrg.set_reg_pressure(1); 888 break; 889 case Op_VecD: 890 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecD), "sanity"); 891 assert(RegMask::num_registers(Op_VecD) == RegMask::SlotsPerVecD, "sanity"); 892 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecD), "vector should be aligned"); 893 lrg.set_num_regs(RegMask::SlotsPerVecD); 894 lrg.set_reg_pressure(1); 895 break; 896 case Op_VecX: 897 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecX), "sanity"); 898 assert(RegMask::num_registers(Op_VecX) == RegMask::SlotsPerVecX, "sanity"); 899 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecX), "vector should be aligned"); 900 lrg.set_num_regs(RegMask::SlotsPerVecX); 901 lrg.set_reg_pressure(1); 902 break; 903 case Op_VecY: 904 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecY), "sanity"); 905 assert(RegMask::num_registers(Op_VecY) == RegMask::SlotsPerVecY, "sanity"); 906 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecY), "vector should be aligned"); 907 lrg.set_num_regs(RegMask::SlotsPerVecY); 908 lrg.set_reg_pressure(1); 909 break; 910 case Op_VecZ: 911 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecZ), "sanity"); 912 assert(RegMask::num_registers(Op_VecZ) == RegMask::SlotsPerVecZ, "sanity"); 913 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecZ), "vector should be aligned"); 914 lrg.set_num_regs(RegMask::SlotsPerVecZ); 915 lrg.set_reg_pressure(1); 916 break; 917 default: 918 ShouldNotReachHere(); 919 } 920 } 921 922 // Now do the same for inputs 923 uint cnt = n->req(); 924 // Setup for CISC SPILLING 925 uint inp = (uint)AdlcVMDeps::Not_cisc_spillable; 926 if( UseCISCSpill && after_aggressive ) { 927 inp = n->cisc_operand(); 928 if( inp != (uint)AdlcVMDeps::Not_cisc_spillable ) 929 // Convert operand number to edge index number 930 inp = n->as_Mach()->operand_index(inp); 931 } 932 // Prepare register mask for each input 933 for( uint k = input_edge_start; k < cnt; k++ ) { 934 uint vreg = _lrg_map.live_range_id(n->in(k)); 935 if (!vreg) { 936 continue; 937 } 938 939 // If this instruction is CISC Spillable, add the flags 940 // bit to its appropriate input 941 if( UseCISCSpill && after_aggressive && inp == k ) { 942 #ifndef PRODUCT 943 if( TraceCISCSpill ) { 944 tty->print(" use_cisc_RegMask: "); 945 n->dump(); 946 } 947 #endif 948 n->as_Mach()->use_cisc_RegMask(); 949 } 950 951 LRG &lrg = lrgs(vreg); 952 // // Testing for floating point code shape 953 // Node *test = n->in(k); 954 // if( test->is_Mach() ) { 955 // MachNode *m = test->as_Mach(); 956 // int op = m->ideal_Opcode(); 957 // if (n->is_Call() && (op == Op_AddF || op == Op_MulF) ) { 958 // int zzz = 1; 959 // } 960 // } 961 962 // Limit result register mask to acceptable registers. 963 // Do not limit registers from uncommon uses before 964 // AggressiveCoalesce. This effectively pre-virtual-splits 965 // around uncommon uses of common defs. 966 const RegMask &rm = n->in_RegMask(k); 967 if (!after_aggressive && _cfg.get_block_for_node(n->in(k))->_freq > 1000 * block->_freq) { 968 // Since we are BEFORE aggressive coalesce, leave the register 969 // mask untrimmed by the call. This encourages more coalescing. 970 // Later, AFTER aggressive, this live range will have to spill 971 // but the spiller handles slow-path calls very nicely. 972 } else { 973 lrg.AND( rm ); 974 } 975 976 // Check for bound register masks 977 const RegMask &lrgmask = lrg.mask(); 978 int kreg = n->in(k)->ideal_reg(); 979 bool is_vect = RegMask::is_vector(kreg); 980 assert(n->in(k)->bottom_type()->isa_vect() == NULL || 981 is_vect || kreg == Op_RegD || kreg == Op_RegL, 982 "vector must be in vector registers"); 983 if (lrgmask.is_bound(kreg)) 984 lrg._is_bound = 1; 985 986 // If this use of a double forces a mis-aligned double, 987 // flag as '_fat_proj' - really flag as allowing misalignment 988 // AND changes how we count interferences. A mis-aligned 989 // double can interfere with TWO aligned pairs, or effectively 990 // FOUR registers! 991 #ifdef ASSERT 992 if (is_vect) { 993 assert(lrgmask.is_aligned_sets(lrg.num_regs()), "vector should be aligned"); 994 assert(!lrg._fat_proj, "sanity"); 995 assert(RegMask::num_registers(kreg) == lrg.num_regs(), "sanity"); 996 } 997 #endif 998 if (!is_vect && lrg.num_regs() == 2 && !lrg._fat_proj && rm.is_misaligned_pair()) { 999 lrg._fat_proj = 1; 1000 lrg._is_bound = 1; 1001 } 1002 // if the LRG is an unaligned pair, we will have to spill 1003 // so clear the LRG's register mask if it is not already spilled 1004 if (!is_vect && !n->is_SpillCopy() && 1005 (lrg._def == NULL || lrg.is_multidef() || !lrg._def->is_SpillCopy()) && 1006 lrgmask.is_misaligned_pair()) { 1007 lrg.Clear(); 1008 } 1009 1010 // Check for maximum frequency value 1011 if (lrg._maxfreq < block->_freq) { 1012 lrg._maxfreq = block->_freq; 1013 } 1014 1015 } // End for all allocated inputs 1016 } // end for all instructions 1017 } // end for all blocks 1018 1019 // Final per-liverange setup 1020 for (uint i2 = 0; i2 < _lrg_map.max_lrg_id(); i2++) { 1021 LRG &lrg = lrgs(i2); 1022 assert(!lrg._is_vector || !lrg._fat_proj, "sanity"); 1023 if (lrg.num_regs() > 1 && !lrg._fat_proj) { 1024 lrg.clear_to_sets(); 1025 } 1026 lrg.compute_set_mask_size(); 1027 if (lrg.not_free()) { // Handle case where we lose from the start 1028 lrg.set_reg(OptoReg::Name(LRG::SPILL_REG)); 1029 lrg._direct_conflict = 1; 1030 } 1031 lrg.set_degree(0); // no neighbors in IFG yet 1032 } 1033 } 1034 1035 // Set the was-lo-degree bit. Conservative coalescing should not change the 1036 // colorability of the graph. If any live range was of low-degree before 1037 // coalescing, it should Simplify. This call sets the was-lo-degree bit. 1038 // The bit is checked in Simplify. 1039 void PhaseChaitin::set_was_low() { 1040 #ifdef ASSERT 1041 for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) { 1042 int size = lrgs(i).num_regs(); 1043 uint old_was_lo = lrgs(i)._was_lo; 1044 lrgs(i)._was_lo = 0; 1045 if( lrgs(i).lo_degree() ) { 1046 lrgs(i)._was_lo = 1; // Trivially of low degree 1047 } else { // Else check the Brigg's assertion 1048 // Brigg's observation is that the lo-degree neighbors of a 1049 // hi-degree live range will not interfere with the color choices 1050 // of said hi-degree live range. The Simplify reverse-stack-coloring 1051 // order takes care of the details. Hence you do not have to count 1052 // low-degree neighbors when determining if this guy colors. 1053 int briggs_degree = 0; 1054 IndexSet *s = _ifg->neighbors(i); 1055 IndexSetIterator elements(s); 1056 uint lidx; 1057 while((lidx = elements.next()) != 0) { 1058 if( !lrgs(lidx).lo_degree() ) 1059 briggs_degree += MAX2(size,lrgs(lidx).num_regs()); 1060 } 1061 if( briggs_degree < lrgs(i).degrees_of_freedom() ) 1062 lrgs(i)._was_lo = 1; // Low degree via the briggs assertion 1063 } 1064 assert(old_was_lo <= lrgs(i)._was_lo, "_was_lo may not decrease"); 1065 } 1066 #endif 1067 } 1068 1069 #define REGISTER_CONSTRAINED 16 1070 1071 // Compute cost/area ratio, in case we spill. Build the lo-degree list. 1072 void PhaseChaitin::cache_lrg_info( ) { 1073 Compile::TracePhase tp("chaitinCacheLRG", &timers[_t_chaitinCacheLRG]); 1074 1075 for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) { 1076 LRG &lrg = lrgs(i); 1077 1078 // Check for being of low degree: means we can be trivially colored. 1079 // Low degree, dead or must-spill guys just get to simplify right away 1080 if( lrg.lo_degree() || 1081 !lrg.alive() || 1082 lrg._must_spill ) { 1083 // Split low degree list into those guys that must get a 1084 // register and those that can go to register or stack. 1085 // The idea is LRGs that can go register or stack color first when 1086 // they have a good chance of getting a register. The register-only 1087 // lo-degree live ranges always get a register. 1088 OptoReg::Name hi_reg = lrg.mask().find_last_elem(); 1089 if( OptoReg::is_stack(hi_reg)) { // Can go to stack? 1090 lrg._next = _lo_stk_degree; 1091 _lo_stk_degree = i; 1092 } else { 1093 lrg._next = _lo_degree; 1094 _lo_degree = i; 1095 } 1096 } else { // Else high degree 1097 lrgs(_hi_degree)._prev = i; 1098 lrg._next = _hi_degree; 1099 lrg._prev = 0; 1100 _hi_degree = i; 1101 } 1102 } 1103 } 1104 1105 // Simplify the IFG by removing LRGs of low degree that have NO copies 1106 void PhaseChaitin::Pre_Simplify( ) { 1107 1108 // Warm up the lo-degree no-copy list 1109 int lo_no_copy = 0; 1110 for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) { 1111 if ((lrgs(i).lo_degree() && !lrgs(i)._has_copy) || 1112 !lrgs(i).alive() || 1113 lrgs(i)._must_spill) { 1114 lrgs(i)._next = lo_no_copy; 1115 lo_no_copy = i; 1116 } 1117 } 1118 1119 while( lo_no_copy ) { 1120 uint lo = lo_no_copy; 1121 lo_no_copy = lrgs(lo)._next; 1122 int size = lrgs(lo).num_regs(); 1123 1124 // Put the simplified guy on the simplified list. 1125 lrgs(lo)._next = _simplified; 1126 _simplified = lo; 1127 1128 // Yank this guy from the IFG. 1129 IndexSet *adj = _ifg->remove_node( lo ); 1130 1131 // If any neighbors' degrees fall below their number of 1132 // allowed registers, then put that neighbor on the low degree 1133 // list. Note that 'degree' can only fall and 'numregs' is 1134 // unchanged by this action. Thus the two are equal at most once, 1135 // so LRGs hit the lo-degree worklists at most once. 1136 IndexSetIterator elements(adj); 1137 uint neighbor; 1138 while ((neighbor = elements.next()) != 0) { 1139 LRG *n = &lrgs(neighbor); 1140 assert( _ifg->effective_degree(neighbor) == n->degree(), "" ); 1141 1142 // Check for just becoming of-low-degree 1143 if( n->just_lo_degree() && !n->_has_copy ) { 1144 assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice"); 1145 // Put on lo-degree list 1146 n->_next = lo_no_copy; 1147 lo_no_copy = neighbor; 1148 } 1149 } 1150 } // End of while lo-degree no_copy worklist not empty 1151 1152 // No more lo-degree no-copy live ranges to simplify 1153 } 1154 1155 // Simplify the IFG by removing LRGs of low degree. 1156 void PhaseChaitin::Simplify( ) { 1157 Compile::TracePhase tp("chaitinSimplify", &timers[_t_chaitinSimplify]); 1158 1159 while( 1 ) { // Repeat till simplified it all 1160 // May want to explore simplifying lo_degree before _lo_stk_degree. 1161 // This might result in more spills coloring into registers during 1162 // Select(). 1163 while( _lo_degree || _lo_stk_degree ) { 1164 // If possible, pull from lo_stk first 1165 uint lo; 1166 if( _lo_degree ) { 1167 lo = _lo_degree; 1168 _lo_degree = lrgs(lo)._next; 1169 } else { 1170 lo = _lo_stk_degree; 1171 _lo_stk_degree = lrgs(lo)._next; 1172 } 1173 1174 // Put the simplified guy on the simplified list. 1175 lrgs(lo)._next = _simplified; 1176 _simplified = lo; 1177 // If this guy is "at risk" then mark his current neighbors 1178 if( lrgs(lo)._at_risk ) { 1179 IndexSetIterator elements(_ifg->neighbors(lo)); 1180 uint datum; 1181 while ((datum = elements.next()) != 0) { 1182 lrgs(datum)._risk_bias = lo; 1183 } 1184 } 1185 1186 // Yank this guy from the IFG. 1187 IndexSet *adj = _ifg->remove_node( lo ); 1188 1189 // If any neighbors' degrees fall below their number of 1190 // allowed registers, then put that neighbor on the low degree 1191 // list. Note that 'degree' can only fall and 'numregs' is 1192 // unchanged by this action. Thus the two are equal at most once, 1193 // so LRGs hit the lo-degree worklist at most once. 1194 IndexSetIterator elements(adj); 1195 uint neighbor; 1196 while ((neighbor = elements.next()) != 0) { 1197 LRG *n = &lrgs(neighbor); 1198 #ifdef ASSERT 1199 if( VerifyOpto || VerifyRegisterAllocator ) { 1200 assert( _ifg->effective_degree(neighbor) == n->degree(), "" ); 1201 } 1202 #endif 1203 1204 // Check for just becoming of-low-degree just counting registers. 1205 // _must_spill live ranges are already on the low degree list. 1206 if( n->just_lo_degree() && !n->_must_spill ) { 1207 assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice"); 1208 // Pull from hi-degree list 1209 uint prev = n->_prev; 1210 uint next = n->_next; 1211 if( prev ) lrgs(prev)._next = next; 1212 else _hi_degree = next; 1213 lrgs(next)._prev = prev; 1214 n->_next = _lo_degree; 1215 _lo_degree = neighbor; 1216 } 1217 } 1218 } // End of while lo-degree/lo_stk_degree worklist not empty 1219 1220 // Check for got everything: is hi-degree list empty? 1221 if( !_hi_degree ) break; 1222 1223 // Time to pick a potential spill guy 1224 uint lo_score = _hi_degree; 1225 double score = lrgs(lo_score).score(); 1226 double area = lrgs(lo_score)._area; 1227 double cost = lrgs(lo_score)._cost; 1228 bool bound = lrgs(lo_score)._is_bound; 1229 1230 // Find cheapest guy 1231 debug_only( int lo_no_simplify=0; ); 1232 for( uint i = _hi_degree; i; i = lrgs(i)._next ) { 1233 assert( !(*_ifg->_yanked)[i], "" ); 1234 // It's just vaguely possible to move hi-degree to lo-degree without 1235 // going through a just-lo-degree stage: If you remove a double from 1236 // a float live range it's degree will drop by 2 and you can skip the 1237 // just-lo-degree stage. It's very rare (shows up after 5000+ methods 1238 // in -Xcomp of Java2Demo). So just choose this guy to simplify next. 1239 if( lrgs(i).lo_degree() ) { 1240 lo_score = i; 1241 break; 1242 } 1243 debug_only( if( lrgs(i)._was_lo ) lo_no_simplify=i; ); 1244 double iscore = lrgs(i).score(); 1245 double iarea = lrgs(i)._area; 1246 double icost = lrgs(i)._cost; 1247 bool ibound = lrgs(i)._is_bound; 1248 1249 // Compare cost/area of i vs cost/area of lo_score. Smaller cost/area 1250 // wins. Ties happen because all live ranges in question have spilled 1251 // a few times before and the spill-score adds a huge number which 1252 // washes out the low order bits. We are choosing the lesser of 2 1253 // evils; in this case pick largest area to spill. 1254 // Ties also happen when live ranges are defined and used only inside 1255 // one block. In which case their area is 0 and score set to max. 1256 // In such case choose bound live range over unbound to free registers 1257 // or with smaller cost to spill. 1258 if( iscore < score || 1259 (iscore == score && iarea > area && lrgs(lo_score)._was_spilled2) || 1260 (iscore == score && iarea == area && 1261 ( (ibound && !bound) || ibound == bound && (icost < cost) )) ) { 1262 lo_score = i; 1263 score = iscore; 1264 area = iarea; 1265 cost = icost; 1266 bound = ibound; 1267 } 1268 } 1269 LRG *lo_lrg = &lrgs(lo_score); 1270 // The live range we choose for spilling is either hi-degree, or very 1271 // rarely it can be low-degree. If we choose a hi-degree live range 1272 // there better not be any lo-degree choices. 1273 assert( lo_lrg->lo_degree() || !lo_no_simplify, "Live range was lo-degree before coalesce; should simplify" ); 1274 1275 // Pull from hi-degree list 1276 uint prev = lo_lrg->_prev; 1277 uint next = lo_lrg->_next; 1278 if( prev ) lrgs(prev)._next = next; 1279 else _hi_degree = next; 1280 lrgs(next)._prev = prev; 1281 // Jam him on the lo-degree list, despite his high degree. 1282 // Maybe he'll get a color, and maybe he'll spill. 1283 // Only Select() will know. 1284 lrgs(lo_score)._at_risk = true; 1285 _lo_degree = lo_score; 1286 lo_lrg->_next = 0; 1287 1288 } // End of while not simplified everything 1289 1290 } 1291 1292 // Is 'reg' register legal for 'lrg'? 1293 static bool is_legal_reg(LRG &lrg, OptoReg::Name reg, int chunk) { 1294 if (reg >= chunk && reg < (chunk + RegMask::CHUNK_SIZE) && 1295 lrg.mask().Member(OptoReg::add(reg,-chunk))) { 1296 // RA uses OptoReg which represent the highest element of a registers set. 1297 // For example, vectorX (128bit) on x86 uses [XMM,XMMb,XMMc,XMMd] set 1298 // in which XMMd is used by RA to represent such vectors. A double value 1299 // uses [XMM,XMMb] pairs and XMMb is used by RA for it. 1300 // The register mask uses largest bits set of overlapping register sets. 1301 // On x86 with AVX it uses 8 bits for each XMM registers set. 1302 // 1303 // The 'lrg' already has cleared-to-set register mask (done in Select() 1304 // before calling choose_color()). Passing mask.Member(reg) check above 1305 // indicates that the size (num_regs) of 'reg' set is less or equal to 1306 // 'lrg' set size. 1307 // For set size 1 any register which is member of 'lrg' mask is legal. 1308 if (lrg.num_regs()==1) 1309 return true; 1310 // For larger sets only an aligned register with the same set size is legal. 1311 int mask = lrg.num_regs()-1; 1312 if ((reg&mask) == mask) 1313 return true; 1314 } 1315 return false; 1316 } 1317 1318 // Choose a color using the biasing heuristic 1319 OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) { 1320 1321 // Check for "at_risk" LRG's 1322 uint risk_lrg = _lrg_map.find(lrg._risk_bias); 1323 if( risk_lrg != 0 ) { 1324 // Walk the colored neighbors of the "at_risk" candidate 1325 // Choose a color which is both legal and already taken by a neighbor 1326 // of the "at_risk" candidate in order to improve the chances of the 1327 // "at_risk" candidate of coloring 1328 IndexSetIterator elements(_ifg->neighbors(risk_lrg)); 1329 uint datum; 1330 while ((datum = elements.next()) != 0) { 1331 OptoReg::Name reg = lrgs(datum).reg(); 1332 // If this LRG's register is legal for us, choose it 1333 if (is_legal_reg(lrg, reg, chunk)) 1334 return reg; 1335 } 1336 } 1337 1338 uint copy_lrg = _lrg_map.find(lrg._copy_bias); 1339 if( copy_lrg != 0 ) { 1340 // If he has a color, 1341 if( !(*(_ifg->_yanked))[copy_lrg] ) { 1342 OptoReg::Name reg = lrgs(copy_lrg).reg(); 1343 // And it is legal for you, 1344 if (is_legal_reg(lrg, reg, chunk)) 1345 return reg; 1346 } else if( chunk == 0 ) { 1347 // Choose a color which is legal for him 1348 RegMask tempmask = lrg.mask(); 1349 tempmask.AND(lrgs(copy_lrg).mask()); 1350 tempmask.clear_to_sets(lrg.num_regs()); 1351 OptoReg::Name reg = tempmask.find_first_set(lrg.num_regs()); 1352 if (OptoReg::is_valid(reg)) 1353 return reg; 1354 } 1355 } 1356 1357 // If no bias info exists, just go with the register selection ordering 1358 if (lrg._is_vector || lrg.num_regs() == 2) { 1359 // Find an aligned set 1360 return OptoReg::add(lrg.mask().find_first_set(lrg.num_regs()),chunk); 1361 } 1362 1363 // CNC - Fun hack. Alternate 1st and 2nd selection. Enables post-allocate 1364 // copy removal to remove many more copies, by preventing a just-assigned 1365 // register from being repeatedly assigned. 1366 OptoReg::Name reg = lrg.mask().find_first_elem(); 1367 if( (++_alternate & 1) && OptoReg::is_valid(reg) ) { 1368 // This 'Remove; find; Insert' idiom is an expensive way to find the 1369 // SECOND element in the mask. 1370 lrg.Remove(reg); 1371 OptoReg::Name reg2 = lrg.mask().find_first_elem(); 1372 lrg.Insert(reg); 1373 if( OptoReg::is_reg(reg2)) 1374 reg = reg2; 1375 } 1376 return OptoReg::add( reg, chunk ); 1377 } 1378 1379 // Choose a color in the current chunk 1380 OptoReg::Name PhaseChaitin::choose_color( LRG &lrg, int chunk ) { 1381 assert( C->in_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP-1)), "must not allocate stack0 (inside preserve area)"); 1382 assert(C->out_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP+0)), "must not allocate stack0 (inside preserve area)"); 1383 1384 if( lrg.num_regs() == 1 || // Common Case 1385 !lrg._fat_proj ) // Aligned+adjacent pairs ok 1386 // Use a heuristic to "bias" the color choice 1387 return bias_color(lrg, chunk); 1388 1389 assert(!lrg._is_vector, "should be not vector here" ); 1390 assert( lrg.num_regs() >= 2, "dead live ranges do not color" ); 1391 1392 // Fat-proj case or misaligned double argument. 1393 assert(lrg.compute_mask_size() == lrg.num_regs() || 1394 lrg.num_regs() == 2,"fat projs exactly color" ); 1395 assert( !chunk, "always color in 1st chunk" ); 1396 // Return the highest element in the set. 1397 return lrg.mask().find_last_elem(); 1398 } 1399 1400 // Select colors by re-inserting LRGs back into the IFG. LRGs are re-inserted 1401 // in reverse order of removal. As long as nothing of hi-degree was yanked, 1402 // everything going back is guaranteed a color. Select that color. If some 1403 // hi-degree LRG cannot get a color then we record that we must spill. 1404 uint PhaseChaitin::Select( ) { 1405 Compile::TracePhase tp("chaitinSelect", &timers[_t_chaitinSelect]); 1406 1407 uint spill_reg = LRG::SPILL_REG; 1408 _max_reg = OptoReg::Name(0); // Past max register used 1409 while( _simplified ) { 1410 // Pull next LRG from the simplified list - in reverse order of removal 1411 uint lidx = _simplified; 1412 LRG *lrg = &lrgs(lidx); 1413 _simplified = lrg->_next; 1414 1415 1416 #ifndef PRODUCT 1417 if (trace_spilling()) { 1418 ttyLocker ttyl; 1419 tty->print_cr("L%d selecting degree %d degrees_of_freedom %d", lidx, lrg->degree(), 1420 lrg->degrees_of_freedom()); 1421 lrg->dump(); 1422 } 1423 #endif 1424 1425 // Re-insert into the IFG 1426 _ifg->re_insert(lidx); 1427 if( !lrg->alive() ) continue; 1428 // capture allstackedness flag before mask is hacked 1429 const int is_allstack = lrg->mask().is_AllStack(); 1430 1431 // Yeah, yeah, yeah, I know, I know. I can refactor this 1432 // to avoid the GOTO, although the refactored code will not 1433 // be much clearer. We arrive here IFF we have a stack-based 1434 // live range that cannot color in the current chunk, and it 1435 // has to move into the next free stack chunk. 1436 int chunk = 0; // Current chunk is first chunk 1437 retry_next_chunk: 1438 1439 // Remove neighbor colors 1440 IndexSet *s = _ifg->neighbors(lidx); 1441 1442 debug_only(RegMask orig_mask = lrg->mask();) 1443 IndexSetIterator elements(s); 1444 uint neighbor; 1445 while ((neighbor = elements.next()) != 0) { 1446 // Note that neighbor might be a spill_reg. In this case, exclusion 1447 // of its color will be a no-op, since the spill_reg chunk is in outer 1448 // space. Also, if neighbor is in a different chunk, this exclusion 1449 // will be a no-op. (Later on, if lrg runs out of possible colors in 1450 // its chunk, a new chunk of color may be tried, in which case 1451 // examination of neighbors is started again, at retry_next_chunk.) 1452 LRG &nlrg = lrgs(neighbor); 1453 OptoReg::Name nreg = nlrg.reg(); 1454 // Only subtract masks in the same chunk 1455 if( nreg >= chunk && nreg < chunk + RegMask::CHUNK_SIZE ) { 1456 #ifndef PRODUCT 1457 uint size = lrg->mask().Size(); 1458 RegMask rm = lrg->mask(); 1459 #endif 1460 lrg->SUBTRACT(nlrg.mask()); 1461 #ifndef PRODUCT 1462 if (trace_spilling() && lrg->mask().Size() != size) { 1463 ttyLocker ttyl; 1464 tty->print("L%d ", lidx); 1465 rm.dump(); 1466 tty->print(" intersected L%d ", neighbor); 1467 nlrg.mask().dump(); 1468 tty->print(" removed "); 1469 rm.SUBTRACT(lrg->mask()); 1470 rm.dump(); 1471 tty->print(" leaving "); 1472 lrg->mask().dump(); 1473 tty->cr(); 1474 } 1475 #endif 1476 } 1477 } 1478 //assert(is_allstack == lrg->mask().is_AllStack(), "nbrs must not change AllStackedness"); 1479 // Aligned pairs need aligned masks 1480 assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity"); 1481 if (lrg->num_regs() > 1 && !lrg->_fat_proj) { 1482 lrg->clear_to_sets(); 1483 } 1484 1485 // Check if a color is available and if so pick the color 1486 OptoReg::Name reg = choose_color( *lrg, chunk ); 1487 #ifdef SPARC 1488 debug_only(lrg->compute_set_mask_size()); 1489 assert(lrg->num_regs() < 2 || lrg->is_bound() || is_even(reg-1), "allocate all doubles aligned"); 1490 #endif 1491 1492 //--------------- 1493 // If we fail to color and the AllStack flag is set, trigger 1494 // a chunk-rollover event 1495 if(!OptoReg::is_valid(OptoReg::add(reg,-chunk)) && is_allstack) { 1496 // Bump register mask up to next stack chunk 1497 chunk += RegMask::CHUNK_SIZE; 1498 lrg->Set_All(); 1499 1500 goto retry_next_chunk; 1501 } 1502 1503 //--------------- 1504 // Did we get a color? 1505 else if( OptoReg::is_valid(reg)) { 1506 #ifndef PRODUCT 1507 RegMask avail_rm = lrg->mask(); 1508 #endif 1509 1510 // Record selected register 1511 lrg->set_reg(reg); 1512 1513 if( reg >= _max_reg ) // Compute max register limit 1514 _max_reg = OptoReg::add(reg,1); 1515 // Fold reg back into normal space 1516 reg = OptoReg::add(reg,-chunk); 1517 1518 // If the live range is not bound, then we actually had some choices 1519 // to make. In this case, the mask has more bits in it than the colors 1520 // chosen. Restrict the mask to just what was picked. 1521 int n_regs = lrg->num_regs(); 1522 assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity"); 1523 if (n_regs == 1 || !lrg->_fat_proj) { 1524 assert(!lrg->_is_vector || n_regs <= RegMask::SlotsPerVecZ, "sanity"); 1525 lrg->Clear(); // Clear the mask 1526 lrg->Insert(reg); // Set regmask to match selected reg 1527 // For vectors and pairs, also insert the low bit of the pair 1528 for (int i = 1; i < n_regs; i++) 1529 lrg->Insert(OptoReg::add(reg,-i)); 1530 lrg->set_mask_size(n_regs); 1531 } else { // Else fatproj 1532 // mask must be equal to fatproj bits, by definition 1533 } 1534 #ifndef PRODUCT 1535 if (trace_spilling()) { 1536 ttyLocker ttyl; 1537 tty->print("L%d selected ", lidx); 1538 lrg->mask().dump(); 1539 tty->print(" from "); 1540 avail_rm.dump(); 1541 tty->cr(); 1542 } 1543 #endif 1544 // Note that reg is the highest-numbered register in the newly-bound mask. 1545 } // end color available case 1546 1547 //--------------- 1548 // Live range is live and no colors available 1549 else { 1550 assert( lrg->alive(), "" ); 1551 assert( !lrg->_fat_proj || lrg->is_multidef() || 1552 lrg->_def->outcnt() > 0, "fat_proj cannot spill"); 1553 assert( !orig_mask.is_AllStack(), "All Stack does not spill" ); 1554 1555 // Assign the special spillreg register 1556 lrg->set_reg(OptoReg::Name(spill_reg++)); 1557 // Do not empty the regmask; leave mask_size lying around 1558 // for use during Spilling 1559 #ifndef PRODUCT 1560 if( trace_spilling() ) { 1561 ttyLocker ttyl; 1562 tty->print("L%d spilling with neighbors: ", lidx); 1563 s->dump(); 1564 debug_only(tty->print(" original mask: ")); 1565 debug_only(orig_mask.dump()); 1566 dump_lrg(lidx); 1567 } 1568 #endif 1569 } // end spill case 1570 1571 } 1572 1573 return spill_reg-LRG::SPILL_REG; // Return number of spills 1574 } 1575 1576 // Copy 'was_spilled'-edness from the source Node to the dst Node. 1577 void PhaseChaitin::copy_was_spilled( Node *src, Node *dst ) { 1578 if( _spilled_once.test(src->_idx) ) { 1579 _spilled_once.set(dst->_idx); 1580 lrgs(_lrg_map.find(dst))._was_spilled1 = 1; 1581 if( _spilled_twice.test(src->_idx) ) { 1582 _spilled_twice.set(dst->_idx); 1583 lrgs(_lrg_map.find(dst))._was_spilled2 = 1; 1584 } 1585 } 1586 } 1587 1588 // Set the 'spilled_once' or 'spilled_twice' flag on a node. 1589 void PhaseChaitin::set_was_spilled( Node *n ) { 1590 if( _spilled_once.test_set(n->_idx) ) 1591 _spilled_twice.set(n->_idx); 1592 } 1593 1594 // Convert Ideal spill instructions into proper FramePtr + offset Loads and 1595 // Stores. Use-def chains are NOT preserved, but Node->LRG->reg maps are. 1596 void PhaseChaitin::fixup_spills() { 1597 // This function does only cisc spill work. 1598 if( !UseCISCSpill ) return; 1599 1600 Compile::TracePhase tp("fixupSpills", &timers[_t_fixupSpills]); 1601 1602 // Grab the Frame Pointer 1603 Node *fp = _cfg.get_root_block()->head()->in(1)->in(TypeFunc::FramePtr); 1604 1605 // For all blocks 1606 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { 1607 Block* block = _cfg.get_block(i); 1608 1609 // For all instructions in block 1610 uint last_inst = block->end_idx(); 1611 for (uint j = 1; j <= last_inst; j++) { 1612 Node* n = block->get_node(j); 1613 1614 // Dead instruction??? 1615 assert( n->outcnt() != 0 ||// Nothing dead after post alloc 1616 C->top() == n || // Or the random TOP node 1617 n->is_Proj(), // Or a fat-proj kill node 1618 "No dead instructions after post-alloc" ); 1619 1620 int inp = n->cisc_operand(); 1621 if( inp != AdlcVMDeps::Not_cisc_spillable ) { 1622 // Convert operand number to edge index number 1623 MachNode *mach = n->as_Mach(); 1624 inp = mach->operand_index(inp); 1625 Node *src = n->in(inp); // Value to load or store 1626 LRG &lrg_cisc = lrgs(_lrg_map.find_const(src)); 1627 OptoReg::Name src_reg = lrg_cisc.reg(); 1628 // Doubles record the HIGH register of an adjacent pair. 1629 src_reg = OptoReg::add(src_reg,1-lrg_cisc.num_regs()); 1630 if( OptoReg::is_stack(src_reg) ) { // If input is on stack 1631 // This is a CISC Spill, get stack offset and construct new node 1632 #ifndef PRODUCT 1633 if( TraceCISCSpill ) { 1634 tty->print(" reg-instr: "); 1635 n->dump(); 1636 } 1637 #endif 1638 int stk_offset = reg2offset(src_reg); 1639 // Bailout if we might exceed node limit when spilling this instruction 1640 C->check_node_count(0, "out of nodes fixing spills"); 1641 if (C->failing()) return; 1642 // Transform node 1643 MachNode *cisc = mach->cisc_version(stk_offset)->as_Mach(); 1644 cisc->set_req(inp,fp); // Base register is frame pointer 1645 if( cisc->oper_input_base() > 1 && mach->oper_input_base() <= 1 ) { 1646 assert( cisc->oper_input_base() == 2, "Only adding one edge"); 1647 cisc->ins_req(1,src); // Requires a memory edge 1648 } 1649 block->map_node(cisc, j); // Insert into basic block 1650 n->subsume_by(cisc, C); // Correct graph 1651 // 1652 ++_used_cisc_instructions; 1653 #ifndef PRODUCT 1654 if( TraceCISCSpill ) { 1655 tty->print(" cisc-instr: "); 1656 cisc->dump(); 1657 } 1658 #endif 1659 } else { 1660 #ifndef PRODUCT 1661 if( TraceCISCSpill ) { 1662 tty->print(" using reg-instr: "); 1663 n->dump(); 1664 } 1665 #endif 1666 ++_unused_cisc_instructions; // input can be on stack 1667 } 1668 } 1669 1670 } // End of for all instructions 1671 1672 } // End of for all blocks 1673 } 1674 1675 // Helper to stretch above; recursively discover the base Node for a 1676 // given derived Node. Easy for AddP-related machine nodes, but needs 1677 // to be recursive for derived Phis. 1678 Node *PhaseChaitin::find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg ) { 1679 // See if already computed; if so return it 1680 if( derived_base_map[derived->_idx] ) 1681 return derived_base_map[derived->_idx]; 1682 1683 // See if this happens to be a base. 1684 // NOTE: we use TypePtr instead of TypeOopPtr because we can have 1685 // pointers derived from NULL! These are always along paths that 1686 // can't happen at run-time but the optimizer cannot deduce it so 1687 // we have to handle it gracefully. 1688 assert(!derived->bottom_type()->isa_narrowoop() || 1689 derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity"); 1690 const TypePtr *tj = derived->bottom_type()->isa_ptr(); 1691 // If its an OOP with a non-zero offset, then it is derived. 1692 if( tj == NULL || tj->_offset == 0 ) { 1693 derived_base_map[derived->_idx] = derived; 1694 return derived; 1695 } 1696 // Derived is NULL+offset? Base is NULL! 1697 if( derived->is_Con() ) { 1698 Node *base = _matcher.mach_null(); 1699 assert(base != NULL, "sanity"); 1700 if (base->in(0) == NULL) { 1701 // Initialize it once and make it shared: 1702 // set control to _root and place it into Start block 1703 // (where top() node is placed). 1704 base->init_req(0, _cfg.get_root_node()); 1705 Block *startb = _cfg.get_block_for_node(C->top()); 1706 uint node_pos = startb->find_node(C->top()); 1707 startb->insert_node(base, node_pos); 1708 _cfg.map_node_to_block(base, startb); 1709 assert(_lrg_map.live_range_id(base) == 0, "should not have LRG yet"); 1710 1711 // The loadConP0 might have projection nodes depending on architecture 1712 // Add the projection nodes to the CFG 1713 for (DUIterator_Fast imax, i = base->fast_outs(imax); i < imax; i++) { 1714 Node* use = base->fast_out(i); 1715 if (use->is_MachProj()) { 1716 startb->insert_node(use, ++node_pos); 1717 _cfg.map_node_to_block(use, startb); 1718 new_lrg(use, maxlrg++); 1719 } 1720 } 1721 } 1722 if (_lrg_map.live_range_id(base) == 0) { 1723 new_lrg(base, maxlrg++); 1724 } 1725 assert(base->in(0) == _cfg.get_root_node() && _cfg.get_block_for_node(base) == _cfg.get_block_for_node(C->top()), "base NULL should be shared"); 1726 derived_base_map[derived->_idx] = base; 1727 return base; 1728 } 1729 1730 // Check for AddP-related opcodes 1731 if (!derived->is_Phi()) { 1732 assert(derived->as_Mach()->ideal_Opcode() == Op_AddP, err_msg_res("but is: %s", derived->Name())); 1733 Node *base = derived->in(AddPNode::Base); 1734 derived_base_map[derived->_idx] = base; 1735 return base; 1736 } 1737 1738 // Recursively find bases for Phis. 1739 // First check to see if we can avoid a base Phi here. 1740 Node *base = find_base_for_derived( derived_base_map, derived->in(1),maxlrg); 1741 uint i; 1742 for( i = 2; i < derived->req(); i++ ) 1743 if( base != find_base_for_derived( derived_base_map,derived->in(i),maxlrg)) 1744 break; 1745 // Went to the end without finding any different bases? 1746 if( i == derived->req() ) { // No need for a base Phi here 1747 derived_base_map[derived->_idx] = base; 1748 return base; 1749 } 1750 1751 // Now we see we need a base-Phi here to merge the bases 1752 const Type *t = base->bottom_type(); 1753 base = new PhiNode( derived->in(0), t ); 1754 for( i = 1; i < derived->req(); i++ ) { 1755 base->init_req(i, find_base_for_derived(derived_base_map, derived->in(i), maxlrg)); 1756 t = t->meet(base->in(i)->bottom_type()); 1757 } 1758 base->as_Phi()->set_type(t); 1759 1760 // Search the current block for an existing base-Phi 1761 Block *b = _cfg.get_block_for_node(derived); 1762 for( i = 1; i <= b->end_idx(); i++ ) {// Search for matching Phi 1763 Node *phi = b->get_node(i); 1764 if( !phi->is_Phi() ) { // Found end of Phis with no match? 1765 b->insert_node(base, i); // Must insert created Phi here as base 1766 _cfg.map_node_to_block(base, b); 1767 new_lrg(base,maxlrg++); 1768 break; 1769 } 1770 // See if Phi matches. 1771 uint j; 1772 for( j = 1; j < base->req(); j++ ) 1773 if( phi->in(j) != base->in(j) && 1774 !(phi->in(j)->is_Con() && base->in(j)->is_Con()) ) // allow different NULLs 1775 break; 1776 if( j == base->req() ) { // All inputs match? 1777 base = phi; // Then use existing 'phi' and drop 'base' 1778 break; 1779 } 1780 } 1781 1782 1783 // Cache info for later passes 1784 derived_base_map[derived->_idx] = base; 1785 return base; 1786 } 1787 1788 // At each Safepoint, insert extra debug edges for each pair of derived value/ 1789 // base pointer that is live across the Safepoint for oopmap building. The 1790 // edge pairs get added in after sfpt->jvmtail()->oopoff(), but are in the 1791 // required edge set. 1792 bool PhaseChaitin::stretch_base_pointer_live_ranges(ResourceArea *a) { 1793 int must_recompute_live = false; 1794 uint maxlrg = _lrg_map.max_lrg_id(); 1795 Node **derived_base_map = (Node**)a->Amalloc(sizeof(Node*)*C->unique()); 1796 memset( derived_base_map, 0, sizeof(Node*)*C->unique() ); 1797 1798 // For all blocks in RPO do... 1799 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { 1800 Block* block = _cfg.get_block(i); 1801 // Note use of deep-copy constructor. I cannot hammer the original 1802 // liveout bits, because they are needed by the following coalesce pass. 1803 IndexSet liveout(_live->live(block)); 1804 1805 for (uint j = block->end_idx() + 1; j > 1; j--) { 1806 Node* n = block->get_node(j - 1); 1807 1808 // Pre-split compares of loop-phis. Loop-phis form a cycle we would 1809 // like to see in the same register. Compare uses the loop-phi and so 1810 // extends its live range BUT cannot be part of the cycle. If this 1811 // extended live range overlaps with the update of the loop-phi value 1812 // we need both alive at the same time -- which requires at least 1 1813 // copy. But because Intel has only 2-address registers we end up with 1814 // at least 2 copies, one before the loop-phi update instruction and 1815 // one after. Instead we split the input to the compare just after the 1816 // phi. 1817 if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) { 1818 Node *phi = n->in(1); 1819 if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) { 1820 Block *phi_block = _cfg.get_block_for_node(phi); 1821 if (_cfg.get_block_for_node(phi_block->pred(2)) == block) { 1822 const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI]; 1823 Node *spill = new MachSpillCopyNode(MachSpillCopyNode::LoopPhiInput, phi, *mask, *mask); 1824 insert_proj( phi_block, 1, spill, maxlrg++ ); 1825 n->set_req(1,spill); 1826 must_recompute_live = true; 1827 } 1828 } 1829 } 1830 1831 // Get value being defined 1832 uint lidx = _lrg_map.live_range_id(n); 1833 // Ignore the occasional brand-new live range 1834 if (lidx && lidx < _lrg_map.max_lrg_id()) { 1835 // Remove from live-out set 1836 liveout.remove(lidx); 1837 1838 // Copies do not define a new value and so do not interfere. 1839 // Remove the copies source from the liveout set before interfering. 1840 uint idx = n->is_Copy(); 1841 if (idx) { 1842 liveout.remove(_lrg_map.live_range_id(n->in(idx))); 1843 } 1844 } 1845 1846 // Found a safepoint? 1847 JVMState *jvms = n->jvms(); 1848 if( jvms ) { 1849 // Now scan for a live derived pointer 1850 IndexSetIterator elements(&liveout); 1851 uint neighbor; 1852 while ((neighbor = elements.next()) != 0) { 1853 // Find reaching DEF for base and derived values 1854 // This works because we are still in SSA during this call. 1855 Node *derived = lrgs(neighbor)._def; 1856 const TypePtr *tj = derived->bottom_type()->isa_ptr(); 1857 assert(!derived->bottom_type()->isa_narrowoop() || 1858 derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity"); 1859 // If its an OOP with a non-zero offset, then it is derived. 1860 if( tj && tj->_offset != 0 && tj->isa_oop_ptr() ) { 1861 Node *base = find_base_for_derived(derived_base_map, derived, maxlrg); 1862 assert(base->_idx < _lrg_map.size(), ""); 1863 // Add reaching DEFs of derived pointer and base pointer as a 1864 // pair of inputs 1865 n->add_req(derived); 1866 n->add_req(base); 1867 1868 // See if the base pointer is already live to this point. 1869 // Since I'm working on the SSA form, live-ness amounts to 1870 // reaching def's. So if I find the base's live range then 1871 // I know the base's def reaches here. 1872 if ((_lrg_map.live_range_id(base) >= _lrg_map.max_lrg_id() || // (Brand new base (hence not live) or 1873 !liveout.member(_lrg_map.live_range_id(base))) && // not live) AND 1874 (_lrg_map.live_range_id(base) > 0) && // not a constant 1875 _cfg.get_block_for_node(base) != block) { // base not def'd in blk) 1876 // Base pointer is not currently live. Since I stretched 1877 // the base pointer to here and it crosses basic-block 1878 // boundaries, the global live info is now incorrect. 1879 // Recompute live. 1880 must_recompute_live = true; 1881 } // End of if base pointer is not live to debug info 1882 } 1883 } // End of scan all live data for derived ptrs crossing GC point 1884 } // End of if found a GC point 1885 1886 // Make all inputs live 1887 if (!n->is_Phi()) { // Phi function uses come from prior block 1888 for (uint k = 1; k < n->req(); k++) { 1889 uint lidx = _lrg_map.live_range_id(n->in(k)); 1890 if (lidx < _lrg_map.max_lrg_id()) { 1891 liveout.insert(lidx); 1892 } 1893 } 1894 } 1895 1896 } // End of forall instructions in block 1897 liveout.clear(); // Free the memory used by liveout. 1898 1899 } // End of forall blocks 1900 _lrg_map.set_max_lrg_id(maxlrg); 1901 1902 // If I created a new live range I need to recompute live 1903 if (maxlrg != _ifg->_maxlrg) { 1904 must_recompute_live = true; 1905 } 1906 1907 return must_recompute_live != 0; 1908 } 1909 1910 // Extend the node to LRG mapping 1911 1912 void PhaseChaitin::add_reference(const Node *node, const Node *old_node) { 1913 _lrg_map.extend(node->_idx, _lrg_map.live_range_id(old_node)); 1914 } 1915 1916 #ifndef PRODUCT 1917 void PhaseChaitin::dump(const Node *n) const { 1918 uint r = (n->_idx < _lrg_map.size()) ? _lrg_map.find_const(n) : 0; 1919 tty->print("L%d",r); 1920 if (r && n->Opcode() != Op_Phi) { 1921 if( _node_regs ) { // Got a post-allocation copy of allocation? 1922 tty->print("["); 1923 OptoReg::Name second = get_reg_second(n); 1924 if( OptoReg::is_valid(second) ) { 1925 if( OptoReg::is_reg(second) ) 1926 tty->print("%s:",Matcher::regName[second]); 1927 else 1928 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(second)); 1929 } 1930 OptoReg::Name first = get_reg_first(n); 1931 if( OptoReg::is_reg(first) ) 1932 tty->print("%s]",Matcher::regName[first]); 1933 else 1934 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(first)); 1935 } else 1936 n->out_RegMask().dump(); 1937 } 1938 tty->print("/N%d\t",n->_idx); 1939 tty->print("%s === ", n->Name()); 1940 uint k; 1941 for (k = 0; k < n->req(); k++) { 1942 Node *m = n->in(k); 1943 if (!m) { 1944 tty->print("_ "); 1945 } 1946 else { 1947 uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0; 1948 tty->print("L%d",r); 1949 // Data MultiNode's can have projections with no real registers. 1950 // Don't die while dumping them. 1951 int op = n->Opcode(); 1952 if( r && op != Op_Phi && op != Op_Proj && op != Op_SCMemProj) { 1953 if( _node_regs ) { 1954 tty->print("["); 1955 OptoReg::Name second = get_reg_second(n->in(k)); 1956 if( OptoReg::is_valid(second) ) { 1957 if( OptoReg::is_reg(second) ) 1958 tty->print("%s:",Matcher::regName[second]); 1959 else 1960 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), 1961 reg2offset_unchecked(second)); 1962 } 1963 OptoReg::Name first = get_reg_first(n->in(k)); 1964 if( OptoReg::is_reg(first) ) 1965 tty->print("%s]",Matcher::regName[first]); 1966 else 1967 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), 1968 reg2offset_unchecked(first)); 1969 } else 1970 n->in_RegMask(k).dump(); 1971 } 1972 tty->print("/N%d ",m->_idx); 1973 } 1974 } 1975 if( k < n->len() && n->in(k) ) tty->print("| "); 1976 for( ; k < n->len(); k++ ) { 1977 Node *m = n->in(k); 1978 if(!m) { 1979 break; 1980 } 1981 uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0; 1982 tty->print("L%d",r); 1983 tty->print("/N%d ",m->_idx); 1984 } 1985 if( n->is_Mach() ) n->as_Mach()->dump_spec(tty); 1986 else n->dump_spec(tty); 1987 if( _spilled_once.test(n->_idx ) ) { 1988 tty->print(" Spill_1"); 1989 if( _spilled_twice.test(n->_idx ) ) 1990 tty->print(" Spill_2"); 1991 } 1992 tty->print("\n"); 1993 } 1994 1995 void PhaseChaitin::dump(const Block *b) const { 1996 b->dump_head(&_cfg); 1997 1998 // For all instructions 1999 for( uint j = 0; j < b->number_of_nodes(); j++ ) 2000 dump(b->get_node(j)); 2001 // Print live-out info at end of block 2002 if( _live ) { 2003 tty->print("Liveout: "); 2004 IndexSet *live = _live->live(b); 2005 IndexSetIterator elements(live); 2006 tty->print("{"); 2007 uint i; 2008 while ((i = elements.next()) != 0) { 2009 tty->print("L%d ", _lrg_map.find_const(i)); 2010 } 2011 tty->print_cr("}"); 2012 } 2013 tty->print("\n"); 2014 } 2015 2016 void PhaseChaitin::dump() const { 2017 tty->print( "--- Chaitin -- argsize: %d framesize: %d ---\n", 2018 _matcher._new_SP, _framesize ); 2019 2020 // For all blocks 2021 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { 2022 dump(_cfg.get_block(i)); 2023 } 2024 // End of per-block dump 2025 tty->print("\n"); 2026 2027 if (!_ifg) { 2028 tty->print("(No IFG.)\n"); 2029 return; 2030 } 2031 2032 // Dump LRG array 2033 tty->print("--- Live RanGe Array ---\n"); 2034 for (uint i2 = 1; i2 < _lrg_map.max_lrg_id(); i2++) { 2035 tty->print("L%d: ",i2); 2036 if (i2 < _ifg->_maxlrg) { 2037 lrgs(i2).dump(); 2038 } 2039 else { 2040 tty->print_cr("new LRG"); 2041 } 2042 } 2043 tty->cr(); 2044 2045 // Dump lo-degree list 2046 tty->print("Lo degree: "); 2047 for(uint i3 = _lo_degree; i3; i3 = lrgs(i3)._next ) 2048 tty->print("L%d ",i3); 2049 tty->cr(); 2050 2051 // Dump lo-stk-degree list 2052 tty->print("Lo stk degree: "); 2053 for(uint i4 = _lo_stk_degree; i4; i4 = lrgs(i4)._next ) 2054 tty->print("L%d ",i4); 2055 tty->cr(); 2056 2057 // Dump lo-degree list 2058 tty->print("Hi degree: "); 2059 for(uint i5 = _hi_degree; i5; i5 = lrgs(i5)._next ) 2060 tty->print("L%d ",i5); 2061 tty->cr(); 2062 } 2063 2064 void PhaseChaitin::dump_degree_lists() const { 2065 // Dump lo-degree list 2066 tty->print("Lo degree: "); 2067 for( uint i = _lo_degree; i; i = lrgs(i)._next ) 2068 tty->print("L%d ",i); 2069 tty->cr(); 2070 2071 // Dump lo-stk-degree list 2072 tty->print("Lo stk degree: "); 2073 for(uint i2 = _lo_stk_degree; i2; i2 = lrgs(i2)._next ) 2074 tty->print("L%d ",i2); 2075 tty->cr(); 2076 2077 // Dump lo-degree list 2078 tty->print("Hi degree: "); 2079 for(uint i3 = _hi_degree; i3; i3 = lrgs(i3)._next ) 2080 tty->print("L%d ",i3); 2081 tty->cr(); 2082 } 2083 2084 void PhaseChaitin::dump_simplified() const { 2085 tty->print("Simplified: "); 2086 for( uint i = _simplified; i; i = lrgs(i)._next ) 2087 tty->print("L%d ",i); 2088 tty->cr(); 2089 } 2090 2091 static char *print_reg( OptoReg::Name reg, const PhaseChaitin *pc, char *buf ) { 2092 if ((int)reg < 0) 2093 sprintf(buf, "<OptoReg::%d>", (int)reg); 2094 else if (OptoReg::is_reg(reg)) 2095 strcpy(buf, Matcher::regName[reg]); 2096 else 2097 sprintf(buf,"%s + #%d",OptoReg::regname(OptoReg::c_frame_pointer), 2098 pc->reg2offset(reg)); 2099 return buf+strlen(buf); 2100 } 2101 2102 // Dump a register name into a buffer. Be intelligent if we get called 2103 // before allocation is complete. 2104 char *PhaseChaitin::dump_register( const Node *n, char *buf ) const { 2105 if( this == NULL ) { // Not got anything? 2106 sprintf(buf,"N%d",n->_idx); // Then use Node index 2107 } else if( _node_regs ) { 2108 // Post allocation, use direct mappings, no LRG info available 2109 print_reg( get_reg_first(n), this, buf ); 2110 } else { 2111 uint lidx = _lrg_map.find_const(n); // Grab LRG number 2112 if( !_ifg ) { 2113 sprintf(buf,"L%d",lidx); // No register binding yet 2114 } else if( !lidx ) { // Special, not allocated value 2115 strcpy(buf,"Special"); 2116 } else { 2117 if (lrgs(lidx)._is_vector) { 2118 if (lrgs(lidx).mask().is_bound_set(lrgs(lidx).num_regs())) 2119 print_reg( lrgs(lidx).reg(), this, buf ); // a bound machine register 2120 else 2121 sprintf(buf,"L%d",lidx); // No register binding yet 2122 } else if( (lrgs(lidx).num_regs() == 1) 2123 ? lrgs(lidx).mask().is_bound1() 2124 : lrgs(lidx).mask().is_bound_pair() ) { 2125 // Hah! We have a bound machine register 2126 print_reg( lrgs(lidx).reg(), this, buf ); 2127 } else { 2128 sprintf(buf,"L%d",lidx); // No register binding yet 2129 } 2130 } 2131 } 2132 return buf+strlen(buf); 2133 } 2134 2135 void PhaseChaitin::dump_for_spill_split_recycle() const { 2136 if( WizardMode && (PrintCompilation || PrintOpto) ) { 2137 // Display which live ranges need to be split and the allocator's state 2138 tty->print_cr("Graph-Coloring Iteration %d will split the following live ranges", _trip_cnt); 2139 for (uint bidx = 1; bidx < _lrg_map.max_lrg_id(); bidx++) { 2140 if( lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG ) { 2141 tty->print("L%d: ", bidx); 2142 lrgs(bidx).dump(); 2143 } 2144 } 2145 tty->cr(); 2146 dump(); 2147 } 2148 } 2149 2150 void PhaseChaitin::dump_frame() const { 2151 const char *fp = OptoReg::regname(OptoReg::c_frame_pointer); 2152 const TypeTuple *domain = C->tf()->domain(); 2153 const int argcnt = domain->cnt() - TypeFunc::Parms; 2154 2155 // Incoming arguments in registers dump 2156 for( int k = 0; k < argcnt; k++ ) { 2157 OptoReg::Name parmreg = _matcher._parm_regs[k].first(); 2158 if( OptoReg::is_reg(parmreg)) { 2159 const char *reg_name = OptoReg::regname(parmreg); 2160 tty->print("#r%3.3d %s", parmreg, reg_name); 2161 parmreg = _matcher._parm_regs[k].second(); 2162 if( OptoReg::is_reg(parmreg)) { 2163 tty->print(":%s", OptoReg::regname(parmreg)); 2164 } 2165 tty->print(" : parm %d: ", k); 2166 domain->field_at(k + TypeFunc::Parms)->dump(); 2167 tty->cr(); 2168 } 2169 } 2170 2171 // Check for un-owned padding above incoming args 2172 OptoReg::Name reg = _matcher._new_SP; 2173 if( reg > _matcher._in_arg_limit ) { 2174 reg = OptoReg::add(reg, -1); 2175 tty->print_cr("#r%3.3d %s+%2d: pad0, owned by CALLER", reg, fp, reg2offset_unchecked(reg)); 2176 } 2177 2178 // Incoming argument area dump 2179 OptoReg::Name begin_in_arg = OptoReg::add(_matcher._old_SP,C->out_preserve_stack_slots()); 2180 while( reg > begin_in_arg ) { 2181 reg = OptoReg::add(reg, -1); 2182 tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg)); 2183 int j; 2184 for( j = 0; j < argcnt; j++) { 2185 if( _matcher._parm_regs[j].first() == reg || 2186 _matcher._parm_regs[j].second() == reg ) { 2187 tty->print("parm %d: ",j); 2188 domain->field_at(j + TypeFunc::Parms)->dump(); 2189 tty->cr(); 2190 break; 2191 } 2192 } 2193 if( j >= argcnt ) 2194 tty->print_cr("HOLE, owned by SELF"); 2195 } 2196 2197 // Old outgoing preserve area 2198 while( reg > _matcher._old_SP ) { 2199 reg = OptoReg::add(reg, -1); 2200 tty->print_cr("#r%3.3d %s+%2d: old out preserve",reg,fp,reg2offset_unchecked(reg)); 2201 } 2202 2203 // Old SP 2204 tty->print_cr("# -- Old %s -- Framesize: %d --",fp, 2205 reg2offset_unchecked(OptoReg::add(_matcher._old_SP,-1)) - reg2offset_unchecked(_matcher._new_SP)+jintSize); 2206 2207 // Preserve area dump 2208 int fixed_slots = C->fixed_slots(); 2209 OptoReg::Name begin_in_preserve = OptoReg::add(_matcher._old_SP, -(int)C->in_preserve_stack_slots()); 2210 OptoReg::Name return_addr = _matcher.return_addr(); 2211 2212 reg = OptoReg::add(reg, -1); 2213 while (OptoReg::is_stack(reg)) { 2214 tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg)); 2215 if (return_addr == reg) { 2216 tty->print_cr("return address"); 2217 } else if (reg >= begin_in_preserve) { 2218 // Preserved slots are present on x86 2219 if (return_addr == OptoReg::add(reg, VMRegImpl::slots_per_word)) 2220 tty->print_cr("saved fp register"); 2221 else if (return_addr == OptoReg::add(reg, 2*VMRegImpl::slots_per_word) && 2222 VerifyStackAtCalls) 2223 tty->print_cr("0xBADB100D +VerifyStackAtCalls"); 2224 else 2225 tty->print_cr("in_preserve"); 2226 } else if ((int)OptoReg::reg2stack(reg) < fixed_slots) { 2227 tty->print_cr("Fixed slot %d", OptoReg::reg2stack(reg)); 2228 } else { 2229 tty->print_cr("pad2, stack alignment"); 2230 } 2231 reg = OptoReg::add(reg, -1); 2232 } 2233 2234 // Spill area dump 2235 reg = OptoReg::add(_matcher._new_SP, _framesize ); 2236 while( reg > _matcher._out_arg_limit ) { 2237 reg = OptoReg::add(reg, -1); 2238 tty->print_cr("#r%3.3d %s+%2d: spill",reg,fp,reg2offset_unchecked(reg)); 2239 } 2240 2241 // Outgoing argument area dump 2242 while( reg > OptoReg::add(_matcher._new_SP, C->out_preserve_stack_slots()) ) { 2243 reg = OptoReg::add(reg, -1); 2244 tty->print_cr("#r%3.3d %s+%2d: outgoing argument",reg,fp,reg2offset_unchecked(reg)); 2245 } 2246 2247 // Outgoing new preserve area 2248 while( reg > _matcher._new_SP ) { 2249 reg = OptoReg::add(reg, -1); 2250 tty->print_cr("#r%3.3d %s+%2d: new out preserve",reg,fp,reg2offset_unchecked(reg)); 2251 } 2252 tty->print_cr("#"); 2253 } 2254 2255 void PhaseChaitin::dump_bb( uint pre_order ) const { 2256 tty->print_cr("---dump of B%d---",pre_order); 2257 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { 2258 Block* block = _cfg.get_block(i); 2259 if (block->_pre_order == pre_order) { 2260 dump(block); 2261 } 2262 } 2263 } 2264 2265 void PhaseChaitin::dump_lrg( uint lidx, bool defs_only ) const { 2266 tty->print_cr("---dump of L%d---",lidx); 2267 2268 if (_ifg) { 2269 if (lidx >= _lrg_map.max_lrg_id()) { 2270 tty->print("Attempt to print live range index beyond max live range.\n"); 2271 return; 2272 } 2273 tty->print("L%d: ",lidx); 2274 if (lidx < _ifg->_maxlrg) { 2275 lrgs(lidx).dump(); 2276 } else { 2277 tty->print_cr("new LRG"); 2278 } 2279 } 2280 if( _ifg && lidx < _ifg->_maxlrg) { 2281 tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx)); 2282 _ifg->neighbors(lidx)->dump(); 2283 tty->cr(); 2284 } 2285 // For all blocks 2286 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { 2287 Block* block = _cfg.get_block(i); 2288 int dump_once = 0; 2289 2290 // For all instructions 2291 for( uint j = 0; j < block->number_of_nodes(); j++ ) { 2292 Node *n = block->get_node(j); 2293 if (_lrg_map.find_const(n) == lidx) { 2294 if (!dump_once++) { 2295 tty->cr(); 2296 block->dump_head(&_cfg); 2297 } 2298 dump(n); 2299 continue; 2300 } 2301 if (!defs_only) { 2302 uint cnt = n->req(); 2303 for( uint k = 1; k < cnt; k++ ) { 2304 Node *m = n->in(k); 2305 if (!m) { 2306 continue; // be robust in the dumper 2307 } 2308 if (_lrg_map.find_const(m) == lidx) { 2309 if (!dump_once++) { 2310 tty->cr(); 2311 block->dump_head(&_cfg); 2312 } 2313 dump(n); 2314 } 2315 } 2316 } 2317 } 2318 } // End of per-block dump 2319 tty->cr(); 2320 } 2321 #endif // not PRODUCT 2322 2323 int PhaseChaitin::_final_loads = 0; 2324 int PhaseChaitin::_final_stores = 0; 2325 int PhaseChaitin::_final_memoves= 0; 2326 int PhaseChaitin::_final_copies = 0; 2327 double PhaseChaitin::_final_load_cost = 0; 2328 double PhaseChaitin::_final_store_cost = 0; 2329 double PhaseChaitin::_final_memove_cost= 0; 2330 double PhaseChaitin::_final_copy_cost = 0; 2331 int PhaseChaitin::_conserv_coalesce = 0; 2332 int PhaseChaitin::_conserv_coalesce_pair = 0; 2333 int PhaseChaitin::_conserv_coalesce_trie = 0; 2334 int PhaseChaitin::_conserv_coalesce_quad = 0; 2335 int PhaseChaitin::_post_alloc = 0; 2336 int PhaseChaitin::_lost_opp_pp_coalesce = 0; 2337 int PhaseChaitin::_lost_opp_cflow_coalesce = 0; 2338 int PhaseChaitin::_used_cisc_instructions = 0; 2339 int PhaseChaitin::_unused_cisc_instructions = 0; 2340 int PhaseChaitin::_allocator_attempts = 0; 2341 int PhaseChaitin::_allocator_successes = 0; 2342 2343 #ifndef PRODUCT 2344 uint PhaseChaitin::_high_pressure = 0; 2345 uint PhaseChaitin::_low_pressure = 0; 2346 2347 void PhaseChaitin::print_chaitin_statistics() { 2348 tty->print_cr("Inserted %d spill loads, %d spill stores, %d mem-mem moves and %d copies.", _final_loads, _final_stores, _final_memoves, _final_copies); 2349 tty->print_cr("Total load cost= %6.0f, store cost = %6.0f, mem-mem cost = %5.2f, copy cost = %5.0f.", _final_load_cost, _final_store_cost, _final_memove_cost, _final_copy_cost); 2350 tty->print_cr("Adjusted spill cost = %7.0f.", 2351 _final_load_cost*4.0 + _final_store_cost * 2.0 + 2352 _final_copy_cost*1.0 + _final_memove_cost*12.0); 2353 tty->print("Conservatively coalesced %d copies, %d pairs", 2354 _conserv_coalesce, _conserv_coalesce_pair); 2355 if( _conserv_coalesce_trie || _conserv_coalesce_quad ) 2356 tty->print(", %d tries, %d quads", _conserv_coalesce_trie, _conserv_coalesce_quad); 2357 tty->print_cr(", %d post alloc.", _post_alloc); 2358 if( _lost_opp_pp_coalesce || _lost_opp_cflow_coalesce ) 2359 tty->print_cr("Lost coalesce opportunity, %d private-private, and %d cflow interfered.", 2360 _lost_opp_pp_coalesce, _lost_opp_cflow_coalesce ); 2361 if( _used_cisc_instructions || _unused_cisc_instructions ) 2362 tty->print_cr("Used cisc instruction %d, remained in register %d", 2363 _used_cisc_instructions, _unused_cisc_instructions); 2364 if( _allocator_successes != 0 ) 2365 tty->print_cr("Average allocation trips %f", (float)_allocator_attempts/(float)_allocator_successes); 2366 tty->print_cr("High Pressure Blocks = %d, Low Pressure Blocks = %d", _high_pressure, _low_pressure); 2367 } 2368 #endif // not PRODUCT