1 /*
2 * Copyright (c) 1998, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "memory/allocation.inline.hpp"
27 #include "opto/ad.hpp"
28 #include "opto/block.hpp"
29 #include "opto/c2compiler.hpp"
30 #include "opto/callnode.hpp"
31 #include "opto/cfgnode.hpp"
32 #include "opto/machnode.hpp"
33 #include "opto/runtime.hpp"
34 #include "opto/chaitin.hpp"
35 #include "runtime/sharedRuntime.hpp"
36
37 // Optimization - Graph Style
38
39 // Check whether val is not-null-decoded compressed oop,
40 // i.e. will grab into the base of the heap if it represents NULL.
41 static bool accesses_heap_base_zone(Node *val) {
42 if (Universe::narrow_oop_base() > 0) { // Implies UseCompressedOops.
43 if (val && val->is_Mach()) {
44 if (val->as_Mach()->ideal_Opcode() == Op_DecodeN) {
45 // This assumes all Decodes with TypePtr::NotNull are matched to nodes that
46 // decode NULL to point to the heap base (Decode_NN).
47 if (val->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull) {
48 return true;
49 }
50 }
51 // Must recognize load operation with Decode matched in memory operand.
52 // We should not reach here exept for PPC/AIX, as os::zero_page_read_protected()
53 // returns true everywhere else. On PPC, no such memory operands
54 // exist, therefore we did not yet implement a check for such operands.
55 NOT_AIX(Unimplemented());
56 }
57 }
58 return false;
59 }
60
61 static bool needs_explicit_null_check_for_read(Node *val) {
62 // On some OSes (AIX) the page at address 0 is only write protected.
63 // If so, only Store operations will trap.
64 if (os::zero_page_read_protected()) {
65 return false; // Implicit null check will work.
66 }
67 // Also a read accessing the base of a heap-based compressed heap will trap.
68 if (accesses_heap_base_zone(val) && // Hits the base zone page.
69 Universe::narrow_oop_use_implicit_null_checks()) { // Base zone page is protected.
70 return false;
71 }
72
73 return true;
74 }
75
76 //------------------------------implicit_null_check----------------------------
77 // Detect implicit-null-check opportunities. Basically, find NULL checks
78 // with suitable memory ops nearby. Use the memory op to do the NULL check.
79 // I can generate a memory op if there is not one nearby.
80 // The proj is the control projection for the not-null case.
81 // The val is the pointer being checked for nullness or
82 // decodeHeapOop_not_null node if it did not fold into address.
83 void PhaseCFG::implicit_null_check(Block* block, Node *proj, Node *val, int allowed_reasons) {
84 // Assume if null check need for 0 offset then always needed
85 // Intel solaris doesn't support any null checks yet and no
86 // mechanism exists (yet) to set the switches at an os_cpu level
87 if( !ImplicitNullChecks || MacroAssembler::needs_explicit_null_check(0)) return;
88
89 // Make sure the ptr-is-null path appears to be uncommon!
90 float f = block->end()->as_MachIf()->_prob;
91 if( proj->Opcode() == Op_IfTrue ) f = 1.0f - f;
92 if( f > PROB_UNLIKELY_MAG(4) ) return;
93
94 uint bidx = 0; // Capture index of value into memop
95 bool was_store; // Memory op is a store op
96
97 // Get the successor block for if the test ptr is non-null
98 Block* not_null_block; // this one goes with the proj
99 Block* null_block;
100 if (block->get_node(block->number_of_nodes()-1) == proj) {
101 null_block = block->_succs[0];
102 not_null_block = block->_succs[1];
103 } else {
104 assert(block->get_node(block->number_of_nodes()-2) == proj, "proj is one or the other");
105 not_null_block = block->_succs[0];
106 null_block = block->_succs[1];
107 }
108 while (null_block->is_Empty() == Block::empty_with_goto) {
109 null_block = null_block->_succs[0];
110 }
111
112 // Search the exception block for an uncommon trap.
113 // (See Parse::do_if and Parse::do_ifnull for the reason
114 // we need an uncommon trap. Briefly, we need a way to
115 // detect failure of this optimization, as in 6366351.)
116 {
117 bool found_trap = false;
118 for (uint i1 = 0; i1 < null_block->number_of_nodes(); i1++) {
119 Node* nn = null_block->get_node(i1);
120 if (nn->is_MachCall() &&
121 nn->as_MachCall()->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {
122 const Type* trtype = nn->in(TypeFunc::Parms)->bottom_type();
123 if (trtype->isa_int() && trtype->is_int()->is_con()) {
124 jint tr_con = trtype->is_int()->get_con();
125 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
126 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
127 assert((int)reason < (int)BitsPerInt, "recode bit map");
128 if (is_set_nth_bit(allowed_reasons, (int) reason)
129 && action != Deoptimization::Action_none) {
130 // This uncommon trap is sure to recompile, eventually.
131 // When that happens, C->too_many_traps will prevent
132 // this transformation from happening again.
133 found_trap = true;
134 }
135 }
136 break;
137 }
138 }
139 if (!found_trap) {
140 // We did not find an uncommon trap.
141 return;
142 }
143 }
144
145 // Check for decodeHeapOop_not_null node which did not fold into address
146 bool is_decoden = ((intptr_t)val) & 1;
147 val = (Node*)(((intptr_t)val) & ~1);
148
149 assert(!is_decoden || (val->in(0) == NULL) && val->is_Mach() &&
150 (val->as_Mach()->ideal_Opcode() == Op_DecodeN), "sanity");
151
152 // Search the successor block for a load or store who's base value is also
153 // the tested value. There may be several.
154 Node_List *out = new Node_List(Thread::current()->resource_area());
155 MachNode *best = NULL; // Best found so far
156 for (DUIterator i = val->outs(); val->has_out(i); i++) {
157 Node *m = val->out(i);
158 if( !m->is_Mach() ) continue;
159 MachNode *mach = m->as_Mach();
160 was_store = false;
161 int iop = mach->ideal_Opcode();
162 switch( iop ) {
163 case Op_LoadB:
164 case Op_LoadUB:
165 case Op_LoadUS:
166 case Op_LoadD:
167 case Op_LoadF:
168 case Op_LoadI:
169 case Op_LoadL:
170 case Op_LoadP:
171 case Op_LoadN:
172 case Op_LoadS:
173 case Op_LoadKlass:
174 case Op_LoadNKlass:
175 case Op_LoadRange:
176 case Op_LoadD_unaligned:
177 case Op_LoadL_unaligned:
178 assert(mach->in(2) == val, "should be address");
179 break;
180 case Op_StoreB:
181 case Op_StoreC:
182 case Op_StoreCM:
183 case Op_StoreD:
184 case Op_StoreF:
185 case Op_StoreI:
186 case Op_StoreL:
187 case Op_StoreP:
188 case Op_StoreN:
189 case Op_StoreNKlass:
190 was_store = true; // Memory op is a store op
191 // Stores will have their address in slot 2 (memory in slot 1).
192 // If the value being nul-checked is in another slot, it means we
193 // are storing the checked value, which does NOT check the value!
194 if( mach->in(2) != val ) continue;
195 break; // Found a memory op?
196 case Op_StrComp:
197 case Op_StrEquals:
198 case Op_StrIndexOf:
199 case Op_AryEq:
200 case Op_EncodeISOArray:
201 // Not a legit memory op for implicit null check regardless of
202 // embedded loads
203 continue;
204 default: // Also check for embedded loads
205 if( !mach->needs_anti_dependence_check() )
206 continue; // Not an memory op; skip it
207 if( must_clone[iop] ) {
208 // Do not move nodes which produce flags because
209 // RA will try to clone it to place near branch and
210 // it will cause recompilation, see clone_node().
211 continue;
212 }
213 {
214 // Check that value is used in memory address in
215 // instructions with embedded load (CmpP val1,(val2+off)).
216 Node* base;
217 Node* index;
218 const MachOper* oper = mach->memory_inputs(base, index);
219 if (oper == NULL || oper == (MachOper*)-1) {
220 continue; // Not an memory op; skip it
221 }
222 if (val == base ||
223 val == index && val->bottom_type()->isa_narrowoop()) {
224 break; // Found it
225 } else {
226 continue; // Skip it
227 }
228 }
229 break;
230 }
231
232 // On some OSes (AIX) the page at address 0 is only write protected.
233 // If so, only Store operations will trap.
234 // But a read accessing the base of a heap-based compressed heap will trap.
235 if (!was_store && needs_explicit_null_check_for_read(val)) {
236 continue;
237 }
238
239 // check if the offset is not too high for implicit exception
240 {
241 intptr_t offset = 0;
242 const TypePtr *adr_type = NULL; // Do not need this return value here
243 const Node* base = mach->get_base_and_disp(offset, adr_type);
244 if (base == NULL || base == NodeSentinel) {
245 // Narrow oop address doesn't have base, only index
246 if( val->bottom_type()->isa_narrowoop() &&
247 MacroAssembler::needs_explicit_null_check(offset) )
248 continue; // Give up if offset is beyond page size
249 // cannot reason about it; is probably not implicit null exception
250 } else {
251 const TypePtr* tptr;
252 if (UseCompressedOops && (Universe::narrow_oop_shift() == 0 ||
253 Universe::narrow_klass_shift() == 0)) {
254 // 32-bits narrow oop can be the base of address expressions
255 tptr = base->get_ptr_type();
256 } else {
257 // only regular oops are expected here
258 tptr = base->bottom_type()->is_ptr();
259 }
260 // Give up if offset is not a compile-time constant
261 if( offset == Type::OffsetBot || tptr->_offset == Type::OffsetBot )
262 continue;
263 offset += tptr->_offset; // correct if base is offseted
264 if( MacroAssembler::needs_explicit_null_check(offset) )
265 continue; // Give up is reference is beyond 4K page size
266 }
267 }
268
269 // Check ctrl input to see if the null-check dominates the memory op
270 Block *cb = get_block_for_node(mach);
271 cb = cb->_idom; // Always hoist at least 1 block
272 if( !was_store ) { // Stores can be hoisted only one block
273 while( cb->_dom_depth > (block->_dom_depth + 1))
274 cb = cb->_idom; // Hoist loads as far as we want
275 // The non-null-block should dominate the memory op, too. Live
276 // range spilling will insert a spill in the non-null-block if it is
277 // needs to spill the memory op for an implicit null check.
278 if (cb->_dom_depth == (block->_dom_depth + 1)) {
279 if (cb != not_null_block) continue;
280 cb = cb->_idom;
281 }
282 }
283 if( cb != block ) continue;
284
285 // Found a memory user; see if it can be hoisted to check-block
286 uint vidx = 0; // Capture index of value into memop
287 uint j;
288 for( j = mach->req()-1; j > 0; j-- ) {
289 if( mach->in(j) == val ) {
290 vidx = j;
291 // Ignore DecodeN val which could be hoisted to where needed.
292 if( is_decoden ) continue;
293 }
294 // Block of memory-op input
295 Block *inb = get_block_for_node(mach->in(j));
296 Block *b = block; // Start from nul check
297 while( b != inb && b->_dom_depth > inb->_dom_depth )
298 b = b->_idom; // search upwards for input
299 // See if input dominates null check
300 if( b != inb )
301 break;
302 }
303 if( j > 0 )
304 continue;
305 Block *mb = get_block_for_node(mach);
306 // Hoisting stores requires more checks for the anti-dependence case.
307 // Give up hoisting if we have to move the store past any load.
308 if( was_store ) {
309 Block *b = mb; // Start searching here for a local load
310 // mach use (faulting) trying to hoist
311 // n might be blocker to hoisting
312 while( b != block ) {
313 uint k;
314 for( k = 1; k < b->number_of_nodes(); k++ ) {
315 Node *n = b->get_node(k);
316 if( n->needs_anti_dependence_check() &&
317 n->in(LoadNode::Memory) == mach->in(StoreNode::Memory) )
318 break; // Found anti-dependent load
319 }
320 if( k < b->number_of_nodes() )
321 break; // Found anti-dependent load
322 // Make sure control does not do a merge (would have to check allpaths)
323 if( b->num_preds() != 2 ) break;
324 b = get_block_for_node(b->pred(1)); // Move up to predecessor block
325 }
326 if( b != block ) continue;
327 }
328
329 // Make sure this memory op is not already being used for a NullCheck
330 Node *e = mb->end();
331 if( e->is_MachNullCheck() && e->in(1) == mach )
332 continue; // Already being used as a NULL check
333
334 // Found a candidate! Pick one with least dom depth - the highest
335 // in the dom tree should be closest to the null check.
336 if (best == NULL || get_block_for_node(mach)->_dom_depth < get_block_for_node(best)->_dom_depth) {
337 best = mach;
338 bidx = vidx;
339 }
340 }
341 // No candidate!
342 if (best == NULL) {
343 return;
344 }
345
346 // ---- Found an implicit null check
347 extern int implicit_null_checks;
348 implicit_null_checks++;
349
350 if( is_decoden ) {
351 // Check if we need to hoist decodeHeapOop_not_null first.
352 Block *valb = get_block_for_node(val);
353 if( block != valb && block->_dom_depth < valb->_dom_depth ) {
354 // Hoist it up to the end of the test block.
355 valb->find_remove(val);
356 block->add_inst(val);
357 map_node_to_block(val, block);
358 // DecodeN on x86 may kill flags. Check for flag-killing projections
359 // that also need to be hoisted.
360 for (DUIterator_Fast jmax, j = val->fast_outs(jmax); j < jmax; j++) {
361 Node* n = val->fast_out(j);
362 if( n->is_MachProj() ) {
363 get_block_for_node(n)->find_remove(n);
364 block->add_inst(n);
365 map_node_to_block(n, block);
366 }
367 }
368 }
369 }
370 // Hoist the memory candidate up to the end of the test block.
371 Block *old_block = get_block_for_node(best);
372 old_block->find_remove(best);
373 block->add_inst(best);
374 map_node_to_block(best, block);
375
376 // Move the control dependence
377 if (best->in(0) && best->in(0) == old_block->head())
378 best->set_req(0, block->head());
379
380 // Check for flag-killing projections that also need to be hoisted
381 // Should be DU safe because no edge updates.
382 for (DUIterator_Fast jmax, j = best->fast_outs(jmax); j < jmax; j++) {
383 Node* n = best->fast_out(j);
384 if( n->is_MachProj() ) {
385 get_block_for_node(n)->find_remove(n);
386 block->add_inst(n);
387 map_node_to_block(n, block);
388 }
389 }
390
391 // proj==Op_True --> ne test; proj==Op_False --> eq test.
392 // One of two graph shapes got matched:
393 // (IfTrue (If (Bool NE (CmpP ptr NULL))))
394 // (IfFalse (If (Bool EQ (CmpP ptr NULL))))
395 // NULL checks are always branch-if-eq. If we see a IfTrue projection
396 // then we are replacing a 'ne' test with a 'eq' NULL check test.
397 // We need to flip the projections to keep the same semantics.
398 if( proj->Opcode() == Op_IfTrue ) {
399 // Swap order of projections in basic block to swap branch targets
400 Node *tmp1 = block->get_node(block->end_idx()+1);
401 Node *tmp2 = block->get_node(block->end_idx()+2);
402 block->map_node(tmp2, block->end_idx()+1);
403 block->map_node(tmp1, block->end_idx()+2);
404 Node *tmp = new Node(C->top()); // Use not NULL input
405 tmp1->replace_by(tmp);
406 tmp2->replace_by(tmp1);
407 tmp->replace_by(tmp2);
408 tmp->destruct();
409 }
410
411 // Remove the existing null check; use a new implicit null check instead.
412 // Since schedule-local needs precise def-use info, we need to correct
413 // it as well.
414 Node *old_tst = proj->in(0);
415 MachNode *nul_chk = new MachNullCheckNode(old_tst->in(0),best,bidx);
416 block->map_node(nul_chk, block->end_idx());
417 map_node_to_block(nul_chk, block);
418 // Redirect users of old_test to nul_chk
419 for (DUIterator_Last i2min, i2 = old_tst->last_outs(i2min); i2 >= i2min; --i2)
420 old_tst->last_out(i2)->set_req(0, nul_chk);
421 // Clean-up any dead code
422 for (uint i3 = 0; i3 < old_tst->req(); i3++) {
423 Node* in = old_tst->in(i3);
424 old_tst->set_req(i3, NULL);
425 if (in->outcnt() == 0) {
426 // Remove dead input node
427 in->disconnect_inputs(NULL, C);
428 block->find_remove(in);
429 }
430 }
431
432 latency_from_uses(nul_chk);
433 latency_from_uses(best);
434 }
435
436
437 //------------------------------select-----------------------------------------
438 // Select a nice fellow from the worklist to schedule next. If there is only
439 // one choice, then use it. Projections take top priority for correctness
440 // reasons - if I see a projection, then it is next. There are a number of
441 // other special cases, for instructions that consume condition codes, et al.
442 // These are chosen immediately. Some instructions are required to immediately
443 // precede the last instruction in the block, and these are taken last. Of the
444 // remaining cases (most), choose the instruction with the greatest latency
445 // (that is, the most number of pseudo-cycles required to the end of the
446 // routine). If there is a tie, choose the instruction with the most inputs.
447 Node* PhaseCFG::select(
448 Block* block,
449 Node_List &worklist,
450 GrowableArray<int> &ready_cnt,
451 VectorSet &next_call,
452 uint sched_slot,
453 intptr_t* recalc_pressure_nodes) {
454
455 // If only a single entry on the stack, use it
456 uint cnt = worklist.size();
457 if (cnt == 1) {
458 Node *n = worklist[0];
459 worklist.map(0,worklist.pop());
460 return n;
461 }
462
463 uint choice = 0; // Bigger is most important
464 uint latency = 0; // Bigger is scheduled first
465 uint score = 0; // Bigger is better
466 int idx = -1; // Index in worklist
467 int cand_cnt = 0; // Candidate count
468 bool block_size_threshold_ok = (block->number_of_nodes() > 10) ? true : false;
469
470 for( uint i=0; i<cnt; i++ ) { // Inspect entire worklist
471 // Order in worklist is used to break ties.
472 // See caller for how this is used to delay scheduling
473 // of induction variable increments to after the other
474 // uses of the phi are scheduled.
475 Node *n = worklist[i]; // Get Node on worklist
476
477 int iop = n->is_Mach() ? n->as_Mach()->ideal_Opcode() : 0;
478 if( n->is_Proj() || // Projections always win
479 n->Opcode()== Op_Con || // So does constant 'Top'
480 iop == Op_CreateEx || // Create-exception must start block
481 iop == Op_CheckCastPP
482 ) {
483 worklist.map(i,worklist.pop());
484 return n;
485 }
486
487 // Final call in a block must be adjacent to 'catch'
488 Node *e = block->end();
489 if( e->is_Catch() && e->in(0)->in(0) == n )
490 continue;
491
492 // Memory op for an implicit null check has to be at the end of the block
493 if( e->is_MachNullCheck() && e->in(1) == n )
494 continue;
495
496 // Schedule IV increment last.
497 if (e->is_Mach() && e->as_Mach()->ideal_Opcode() == Op_CountedLoopEnd &&
498 e->in(1)->in(1) == n && n->is_iteratively_computed())
499 continue;
500
501 uint n_choice = 2;
502
503 // See if this instruction is consumed by a branch. If so, then (as the
504 // branch is the last instruction in the basic block) force it to the
505 // end of the basic block
506 if ( must_clone[iop] ) {
507 // See if any use is a branch
508 bool found_machif = false;
509
510 for (DUIterator_Fast jmax, j = n->fast_outs(jmax); j < jmax; j++) {
511 Node* use = n->fast_out(j);
512
513 // The use is a conditional branch, make them adjacent
514 if (use->is_MachIf() && get_block_for_node(use) == block) {
515 found_machif = true;
516 break;
517 }
518
519 // More than this instruction pending for successor to be ready,
520 // don't choose this if other opportunities are ready
521 if (ready_cnt.at(use->_idx) > 1)
522 n_choice = 1;
523 }
524
525 // loop terminated, prefer not to use this instruction
526 if (found_machif)
527 continue;
528 }
529
530 // See if this has a predecessor that is "must_clone", i.e. sets the
531 // condition code. If so, choose this first
532 for (uint j = 0; j < n->req() ; j++) {
533 Node *inn = n->in(j);
534 if (inn) {
535 if (inn->is_Mach() && must_clone[inn->as_Mach()->ideal_Opcode()] ) {
536 n_choice = 3;
537 break;
538 }
539 }
540 }
541
542 // MachTemps should be scheduled last so they are near their uses
543 if (n->is_MachTemp()) {
544 n_choice = 1;
545 }
546
547 uint n_latency = get_latency_for_node(n);
548 uint n_score = n->req(); // Many inputs get high score to break ties
549
550 if (OptoRegScheduling && block_size_threshold_ok) {
551 if (recalc_pressure_nodes[n->_idx] == 0x7fff7fff) {
552 _regalloc->_scratch_int_pressure.init(_regalloc->_sched_int_pressure.high_pressure_limit());
553 _regalloc->_scratch_float_pressure.init(_regalloc->_sched_float_pressure.high_pressure_limit());
554 // simulate the notion that we just picked this node to schedule
555 n->add_flag(Node::Flag_is_scheduled);
556 // now caculate its effect upon the graph if we did
557 adjust_register_pressure(n, block, recalc_pressure_nodes, false);
558 // return its state for finalize in case somebody else wins
559 n->remove_flag(Node::Flag_is_scheduled);
560 // now save the two final pressure components of register pressure, limiting pressure calcs to short size
561 short int_pressure = (short)_regalloc->_scratch_int_pressure.current_pressure();
562 short float_pressure = (short)_regalloc->_scratch_float_pressure.current_pressure();
563 recalc_pressure_nodes[n->_idx] = int_pressure;
564 recalc_pressure_nodes[n->_idx] |= (float_pressure << 16);
565 }
566
567 if (_scheduling_for_pressure) {
568 latency = n_latency;
569 if (n_choice != 3) {
570 // Now evaluate each register pressure component based on threshold in the score.
571 // In general the defining register type will dominate the score, ergo we will not see register pressure grow on both banks
572 // on a single instruction, but we might see it shrink on both banks.
573 if (_regalloc->_sched_int_pressure.current_pressure() > _regalloc->_sched_int_pressure.high_pressure_limit()) {
574 short int_pressure = (short)recalc_pressure_nodes[n->_idx];
575 n_score = (int_pressure < 0) ? ((score + n_score) - int_pressure) : (int_pressure > 0) ? 1 : n_score;
576 }
577 if (_regalloc->_sched_float_pressure.current_pressure() > _regalloc->_sched_float_pressure.high_pressure_limit()) {
578 short float_pressure = (short)(recalc_pressure_nodes[n->_idx] >> 16);
579 n_score = (float_pressure < 0) ? ((score + n_score) - float_pressure) : (float_pressure > 0) ? 1 : n_score;
580 }
581 } else {
582 // make sure we choose these candidates
583 score = 0;
584 }
585 }
586 }
587
588 // Keep best latency found
589 cand_cnt++;
590 if (choice < n_choice ||
591 (choice == n_choice &&
592 ((StressLCM && Compile::randomized_select(cand_cnt)) ||
593 (!StressLCM &&
594 (latency < n_latency ||
595 (latency == n_latency &&
596 (score < n_score))))))) {
597 choice = n_choice;
598 latency = n_latency;
599 score = n_score;
600 idx = i; // Also keep index in worklist
601 }
602 } // End of for all ready nodes in worklist
603
604 assert(idx >= 0, "index should be set");
605 Node *n = worklist[(uint)idx]; // Get the winner
606
607 worklist.map((uint)idx, worklist.pop()); // Compress worklist
608 return n;
609 }
610
611 //-------------------------adjust_register_pressure----------------------------
612 void PhaseCFG::adjust_register_pressure(Node* n, Block* block, intptr_t* recalc_pressure_nodes, bool finalize_mode) {
613 PhaseLive* liveinfo = _regalloc->get_live();
614 IndexSet* liveout = liveinfo->live(block);
615 // first adjust the register pressure for the sources
616 for (uint i = 1; i < n->req(); i++) {
617 bool lrg_ends = false;
618 Node *src_n = n->in(i);
619 if (src_n == NULL) continue;
620 if (!src_n->is_Mach()) continue;
621 uint src = _regalloc->_lrg_map.find(src_n);
622 if (src == 0) continue;
623 LRG& lrg_src = _regalloc->lrgs(src);
624 // detect if the live range ends or not
625 if (liveout->member(src) == false) {
626 lrg_ends = true;
627 for (DUIterator_Fast jmax, j = src_n->fast_outs(jmax); j < jmax; j++) {
628 Node* m = src_n->fast_out(j); // Get user
629 if (m == n) continue;
630 if (!m->is_Mach()) continue;
631 MachNode *mach = m->as_Mach();
632 bool src_matches = false;
633 int iop = mach->ideal_Opcode();
634
635 switch (iop) {
636 case Op_StoreB:
637 case Op_StoreC:
638 case Op_StoreCM:
639 case Op_StoreD:
640 case Op_StoreF:
641 case Op_StoreI:
642 case Op_StoreL:
643 case Op_StoreP:
644 case Op_StoreN:
645 case Op_StoreVector:
646 case Op_StoreNKlass:
647 for (uint k = 1; k < m->req(); k++) {
648 Node *in = m->in(k);
649 if (in == src_n) {
650 src_matches = true;
651 break;
652 }
653 }
654 break;
655
656 default:
657 src_matches = true;
658 break;
659 }
660
661 // If we have a store as our use, ignore the non source operands
662 if (src_matches == false) continue;
663
664 // Mark every unscheduled use which is not n with a recalculation
665 if ((get_block_for_node(m) == block) && (!m->is_scheduled())) {
666 if (finalize_mode && !m->is_Phi()) {
667 recalc_pressure_nodes[m->_idx] = 0x7fff7fff;
668 }
669 lrg_ends = false;
670 }
671 }
672 }
673 // if none, this live range ends and we can adjust register pressure
674 if (lrg_ends) {
675 if (finalize_mode) {
676 _regalloc->lower_pressure(block, 0, lrg_src, NULL, _regalloc->_sched_int_pressure, _regalloc->_sched_float_pressure);
677 } else {
678 _regalloc->lower_pressure(block, 0, lrg_src, NULL, _regalloc->_scratch_int_pressure, _regalloc->_scratch_float_pressure);
679 }
680 }
681 }
682
683 // now add the register pressure from the dest and evaluate which heuristic we should use:
684 // 1.) The default, latency scheduling
685 // 2.) Register pressure scheduling based on the high pressure limit threshold for int or float register stacks
686 uint dst = _regalloc->_lrg_map.find(n);
687 if (dst != 0) {
688 LRG& lrg_dst = _regalloc->lrgs(dst);
689 if (finalize_mode) {
690 _regalloc->raise_pressure(block, lrg_dst, _regalloc->_sched_int_pressure, _regalloc->_sched_float_pressure);
691 // check to see if we fall over the register pressure cliff here
692 if (_regalloc->_sched_int_pressure.current_pressure() > _regalloc->_sched_int_pressure.high_pressure_limit()) {
693 _scheduling_for_pressure = true;
694 } else if (_regalloc->_sched_float_pressure.current_pressure() > _regalloc->_sched_float_pressure.high_pressure_limit()) {
695 _scheduling_for_pressure = true;
696 } else {
697 // restore latency scheduling mode
698 _scheduling_for_pressure = false;
699 }
700 } else {
701 _regalloc->raise_pressure(block, lrg_dst, _regalloc->_scratch_int_pressure, _regalloc->_scratch_float_pressure);
702 }
703 }
704 }
705
706 //------------------------------set_next_call----------------------------------
707 void PhaseCFG::set_next_call(Block* block, Node* n, VectorSet& next_call) {
708 if( next_call.test_set(n->_idx) ) return;
709 for( uint i=0; i<n->len(); i++ ) {
710 Node *m = n->in(i);
711 if( !m ) continue; // must see all nodes in block that precede call
712 if (get_block_for_node(m) == block) {
713 set_next_call(block, m, next_call);
714 }
715 }
716 }
717
718 //------------------------------needed_for_next_call---------------------------
719 // Set the flag 'next_call' for each Node that is needed for the next call to
720 // be scheduled. This flag lets me bias scheduling so Nodes needed for the
721 // next subroutine call get priority - basically it moves things NOT needed
722 // for the next call till after the call. This prevents me from trying to
723 // carry lots of stuff live across a call.
724 void PhaseCFG::needed_for_next_call(Block* block, Node* this_call, VectorSet& next_call) {
725 // Find the next control-defining Node in this block
726 Node* call = NULL;
727 for (DUIterator_Fast imax, i = this_call->fast_outs(imax); i < imax; i++) {
728 Node* m = this_call->fast_out(i);
729 if (get_block_for_node(m) == block && // Local-block user
730 m != this_call && // Not self-start node
731 m->is_MachCall()) {
732 call = m;
733 break;
734 }
735 }
736 if (call == NULL) return; // No next call (e.g., block end is near)
737 // Set next-call for all inputs to this call
738 set_next_call(block, call, next_call);
739 }
740
741 //------------------------------add_call_kills-------------------------------------
742 // helper function that adds caller save registers to MachProjNode
743 static void add_call_kills(MachProjNode *proj, RegMask& regs, const char* save_policy, bool exclude_soe) {
744 // Fill in the kill mask for the call
745 for( OptoReg::Name r = OptoReg::Name(0); r < _last_Mach_Reg; r=OptoReg::add(r,1) ) {
746 if( !regs.Member(r) ) { // Not already defined by the call
747 // Save-on-call register?
748 if ((save_policy[r] == 'C') ||
749 (save_policy[r] == 'A') ||
750 ((save_policy[r] == 'E') && exclude_soe)) {
751 proj->_rout.Insert(r);
752 }
753 }
754 }
755 }
756
757
758 //------------------------------sched_call-------------------------------------
759 uint PhaseCFG::sched_call(Block* block, uint node_cnt, Node_List& worklist, GrowableArray<int>& ready_cnt, MachCallNode* mcall, VectorSet& next_call) {
760 RegMask regs;
761
762 // Schedule all the users of the call right now. All the users are
763 // projection Nodes, so they must be scheduled next to the call.
764 // Collect all the defined registers.
765 for (DUIterator_Fast imax, i = mcall->fast_outs(imax); i < imax; i++) {
766 Node* n = mcall->fast_out(i);
767 assert( n->is_MachProj(), "" );
768 int n_cnt = ready_cnt.at(n->_idx)-1;
769 ready_cnt.at_put(n->_idx, n_cnt);
770 assert( n_cnt == 0, "" );
771 // Schedule next to call
772 block->map_node(n, node_cnt++);
773 // Collect defined registers
774 regs.OR(n->out_RegMask());
775 // Check for scheduling the next control-definer
776 if( n->bottom_type() == Type::CONTROL )
777 // Warm up next pile of heuristic bits
778 needed_for_next_call(block, n, next_call);
779
780 // Children of projections are now all ready
781 for (DUIterator_Fast jmax, j = n->fast_outs(jmax); j < jmax; j++) {
782 Node* m = n->fast_out(j); // Get user
783 if(get_block_for_node(m) != block) {
784 continue;
785 }
786 if( m->is_Phi() ) continue;
787 int m_cnt = ready_cnt.at(m->_idx) - 1;
788 ready_cnt.at_put(m->_idx, m_cnt);
789 if( m_cnt == 0 )
790 worklist.push(m);
791 }
792
793 }
794
795 // Act as if the call defines the Frame Pointer.
796 // Certainly the FP is alive and well after the call.
797 regs.Insert(_matcher.c_frame_pointer());
798
799 // Set all registers killed and not already defined by the call.
800 uint r_cnt = mcall->tf()->range()->cnt();
801 int op = mcall->ideal_Opcode();
802 MachProjNode *proj = new MachProjNode( mcall, r_cnt+1, RegMask::Empty, MachProjNode::fat_proj );
803 map_node_to_block(proj, block);
804 block->insert_node(proj, node_cnt++);
805
806 // Select the right register save policy.
807 const char * save_policy;
808 switch (op) {
809 case Op_CallRuntime:
810 case Op_CallLeaf:
811 case Op_CallLeafNoFP:
812 // Calling C code so use C calling convention
813 save_policy = _matcher._c_reg_save_policy;
814 break;
815
816 case Op_CallStaticJava:
817 case Op_CallDynamicJava:
818 // Calling Java code so use Java calling convention
819 save_policy = _matcher._register_save_policy;
820 break;
821
822 default:
823 ShouldNotReachHere();
824 }
825
826 // When using CallRuntime mark SOE registers as killed by the call
827 // so values that could show up in the RegisterMap aren't live in a
828 // callee saved register since the register wouldn't know where to
829 // find them. CallLeaf and CallLeafNoFP are ok because they can't
830 // have debug info on them. Strictly speaking this only needs to be
831 // done for oops since idealreg2debugmask takes care of debug info
832 // references but there no way to handle oops differently than other
833 // pointers as far as the kill mask goes.
834 bool exclude_soe = op == Op_CallRuntime;
835
836 // If the call is a MethodHandle invoke, we need to exclude the
837 // register which is used to save the SP value over MH invokes from
838 // the mask. Otherwise this register could be used for
839 // deoptimization information.
840 if (op == Op_CallStaticJava) {
841 MachCallStaticJavaNode* mcallstaticjava = (MachCallStaticJavaNode*) mcall;
842 if (mcallstaticjava->_method_handle_invoke)
843 proj->_rout.OR(Matcher::method_handle_invoke_SP_save_mask());
844 }
845
846 add_call_kills(proj, regs, save_policy, exclude_soe);
847
848 return node_cnt;
849 }
850
851
852 //------------------------------schedule_local---------------------------------
853 // Topological sort within a block. Someday become a real scheduler.
854 bool PhaseCFG::schedule_local(Block* block, GrowableArray<int>& ready_cnt, VectorSet& next_call, intptr_t *recalc_pressure_nodes) {
855 // Already "sorted" are the block start Node (as the first entry), and
856 // the block-ending Node and any trailing control projections. We leave
857 // these alone. PhiNodes and ParmNodes are made to follow the block start
858 // Node. Everything else gets topo-sorted.
859
860 #ifndef PRODUCT
861 if (trace_opto_pipelining()) {
862 tty->print_cr("# --- schedule_local B%d, before: ---", block->_pre_order);
863 for (uint i = 0;i < block->number_of_nodes(); i++) {
864 tty->print("# ");
865 block->get_node(i)->fast_dump();
866 }
867 tty->print_cr("#");
868 }
869 #endif
870
871 // RootNode is already sorted
872 if (block->number_of_nodes() == 1) {
873 return true;
874 }
875
876 bool block_size_threshold_ok = (block->number_of_nodes() > 10) ? true : false;
877
878 // We track the uses of local definitions as input dependences so that
879 // we know when a given instruction is avialable to be scheduled.
880 uint i;
881 if (OptoRegScheduling && block_size_threshold_ok) {
882 for (i = 1; i < block->number_of_nodes(); i++) { // setup nodes for pressure calc
883 Node *n = block->get_node(i);
884 n->remove_flag(Node::Flag_is_scheduled);
885 if (!n->is_Phi()) {
886 recalc_pressure_nodes[n->_idx] = 0x7fff7fff;
887 }
888 }
889 }
890
891 // Move PhiNodes and ParmNodes from 1 to cnt up to the start
892 uint node_cnt = block->end_idx();
893 uint phi_cnt = 1;
894 for( i = 1; i<node_cnt; i++ ) { // Scan for Phi
895 Node *n = block->get_node(i);
896 if( n->is_Phi() || // Found a PhiNode or ParmNode
897 (n->is_Proj() && n->in(0) == block->head()) ) {
898 // Move guy at 'phi_cnt' to the end; makes a hole at phi_cnt
899 block->map_node(block->get_node(phi_cnt), i);
900 block->map_node(n, phi_cnt++); // swap Phi/Parm up front
901 if (OptoRegScheduling && block_size_threshold_ok) {
902 // mark n as scheduled
903 n->add_flag(Node::Flag_is_scheduled);
904 }
905 } else { // All others
906 // Count block-local inputs to 'n'
907 uint cnt = n->len(); // Input count
908 uint local = 0;
909 for( uint j=0; j<cnt; j++ ) {
910 Node *m = n->in(j);
911 if( m && get_block_for_node(m) == block && !m->is_top() )
912 local++; // One more block-local input
913 }
914 ready_cnt.at_put(n->_idx, local); // Count em up
915
916 #ifdef ASSERT
917 if( UseConcMarkSweepGC || UseG1GC ) {
918 if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_StoreCM ) {
919 // Check the precedence edges
920 for (uint prec = n->req(); prec < n->len(); prec++) {
921 Node* oop_store = n->in(prec);
922 if (oop_store != NULL) {
923 assert(get_block_for_node(oop_store)->_dom_depth <= block->_dom_depth, "oop_store must dominate card-mark");
924 }
925 }
926 }
927 }
928 #endif
929
930 // A few node types require changing a required edge to a precedence edge
931 // before allocation.
932 if( n->is_Mach() && n->req() > TypeFunc::Parms &&
933 (n->as_Mach()->ideal_Opcode() == Op_MemBarAcquire ||
934 n->as_Mach()->ideal_Opcode() == Op_MemBarVolatile) ) {
935 // MemBarAcquire could be created without Precedent edge.
936 // del_req() replaces the specified edge with the last input edge
937 // and then removes the last edge. If the specified edge > number of
938 // edges the last edge will be moved outside of the input edges array
939 // and the edge will be lost. This is why this code should be
940 // executed only when Precedent (== TypeFunc::Parms) edge is present.
941 Node *x = n->in(TypeFunc::Parms);
942 n->del_req(TypeFunc::Parms);
943 n->add_prec(x);
944 }
945 }
946 }
947 for(uint i2=i; i2< block->number_of_nodes(); i2++ ) // Trailing guys get zapped count
948 ready_cnt.at_put(block->get_node(i2)->_idx, 0);
949
950 // All the prescheduled guys do not hold back internal nodes
951 uint i3;
952 for (i3 = 0; i3 < phi_cnt; i3++) { // For all pre-scheduled
953 Node *n = block->get_node(i3); // Get pre-scheduled
954 for (DUIterator_Fast jmax, j = n->fast_outs(jmax); j < jmax; j++) {
955 Node* m = n->fast_out(j);
956 if (get_block_for_node(m) == block) { // Local-block user
957 int m_cnt = ready_cnt.at(m->_idx)-1;
958 if (OptoRegScheduling && block_size_threshold_ok) {
959 // mark m as scheduled
960 if (m_cnt < 0) {
961 m->add_flag(Node::Flag_is_scheduled);
962 }
963 }
964 ready_cnt.at_put(m->_idx, m_cnt); // Fix ready count
965 }
966 }
967 }
968
969 Node_List delay;
970 // Make a worklist
971 Node_List worklist;
972 for(uint i4=i3; i4<node_cnt; i4++ ) { // Put ready guys on worklist
973 Node *m = block->get_node(i4);
974 if( !ready_cnt.at(m->_idx) ) { // Zero ready count?
975 if (m->is_iteratively_computed()) {
976 // Push induction variable increments last to allow other uses
977 // of the phi to be scheduled first. The select() method breaks
978 // ties in scheduling by worklist order.
979 delay.push(m);
980 } else if (m->is_Mach() && m->as_Mach()->ideal_Opcode() == Op_CreateEx) {
981 // Force the CreateEx to the top of the list so it's processed
982 // first and ends up at the start of the block.
983 worklist.insert(0, m);
984 } else {
985 worklist.push(m); // Then on to worklist!
986 }
987 }
988 }
989 while (delay.size()) {
990 Node* d = delay.pop();
991 worklist.push(d);
992 }
993
994 if (OptoRegScheduling && block_size_threshold_ok) {
995 // To stage register pressure calculations we need to examine the live set variables
996 // breaking them up by register class to compartmentalize the calculations.
997 uint float_pressure = FLOATPRESSURE;
998 #ifdef _LP64
999 if (UseAVX > 2) {
1000 float_pressure *= 2;
1001 }
1002 #endif
1003 _regalloc->_sched_int_pressure.init(INTPRESSURE);
1004 _regalloc->_sched_float_pressure.init(float_pressure);
1005 _regalloc->_scratch_int_pressure.init(INTPRESSURE);
1006 _regalloc->_scratch_float_pressure.init(float_pressure);
1007
1008 _regalloc->compute_entry_block_pressure(block);
1009 }
1010
1011 // Warm up the 'next_call' heuristic bits
1012 needed_for_next_call(block, block->head(), next_call);
1013
1014 #ifndef PRODUCT
1015 if (trace_opto_pipelining()) {
1016 for (uint j=0; j< block->number_of_nodes(); j++) {
1017 Node *n = block->get_node(j);
1018 int idx = n->_idx;
1019 tty->print("# ready cnt:%3d ", ready_cnt.at(idx));
1020 tty->print("latency:%3d ", get_latency_for_node(n));
1021 tty->print("%4d: %s\n", idx, n->Name());
1022 }
1023 }
1024 #endif
1025
1026 uint max_idx = (uint)ready_cnt.length();
1027 // Pull from worklist and schedule
1028 while( worklist.size() ) { // Worklist is not ready
1029
1030 #ifndef PRODUCT
1031 if (trace_opto_pipelining()) {
1032 tty->print("# ready list:");
1033 for( uint i=0; i<worklist.size(); i++ ) { // Inspect entire worklist
1034 Node *n = worklist[i]; // Get Node on worklist
1035 tty->print(" %d", n->_idx);
1036 }
1037 tty->cr();
1038 }
1039 #endif
1040
1041 // Select and pop a ready guy from worklist
1042 Node* n = select(block, worklist, ready_cnt, next_call, phi_cnt, recalc_pressure_nodes);
1043 block->map_node(n, phi_cnt++); // Schedule him next
1044
1045 if (OptoRegScheduling && block_size_threshold_ok) {
1046 n->add_flag(Node::Flag_is_scheduled);
1047
1048 // Now adjust the resister pressure with the node we selected
1049 if (!n->is_Phi()) {
1050 adjust_register_pressure(n, block, recalc_pressure_nodes, true);
1051 }
1052 }
1053
1054 #ifndef PRODUCT
1055 if (trace_opto_pipelining()) {
1056 tty->print("# select %d: %s", n->_idx, n->Name());
1057 tty->print(", latency:%d", get_latency_for_node(n));
1058 n->dump();
1059 if (Verbose) {
1060 tty->print("# ready list:");
1061 for( uint i=0; i<worklist.size(); i++ ) { // Inspect entire worklist
1062 Node *n = worklist[i]; // Get Node on worklist
1063 tty->print(" %d", n->_idx);
1064 }
1065 tty->cr();
1066 }
1067 }
1068
1069 #endif
1070 if( n->is_MachCall() ) {
1071 MachCallNode *mcall = n->as_MachCall();
1072 phi_cnt = sched_call(block, phi_cnt, worklist, ready_cnt, mcall, next_call);
1073 continue;
1074 }
1075
1076 if (n->is_Mach() && n->as_Mach()->has_call()) {
1077 RegMask regs;
1078 regs.Insert(_matcher.c_frame_pointer());
1079 regs.OR(n->out_RegMask());
1080
1081 MachProjNode *proj = new MachProjNode( n, 1, RegMask::Empty, MachProjNode::fat_proj );
1082 map_node_to_block(proj, block);
1083 block->insert_node(proj, phi_cnt++);
1084
1085 add_call_kills(proj, regs, _matcher._c_reg_save_policy, false);
1086 }
1087
1088 // Children are now all ready
1089 for (DUIterator_Fast i5max, i5 = n->fast_outs(i5max); i5 < i5max; i5++) {
1090 Node* m = n->fast_out(i5); // Get user
1091 if (get_block_for_node(m) != block) {
1092 continue;
1093 }
1094 if( m->is_Phi() ) continue;
1095 if (m->_idx >= max_idx) { // new node, skip it
1096 assert(m->is_MachProj() && n->is_Mach() && n->as_Mach()->has_call(), "unexpected node types");
1097 continue;
1098 }
1099 int m_cnt = ready_cnt.at(m->_idx) - 1;
1100 ready_cnt.at_put(m->_idx, m_cnt);
1101 if( m_cnt == 0 )
1102 worklist.push(m);
1103 }
1104 }
1105
1106 if( phi_cnt != block->end_idx() ) {
1107 // did not schedule all. Retry, Bailout, or Die
1108 if (C->subsume_loads() == true && !C->failing()) {
1109 // Retry with subsume_loads == false
1110 // If this is the first failure, the sentinel string will "stick"
1111 // to the Compile object, and the C2Compiler will see it and retry.
1112 C->record_failure(C2Compiler::retry_no_subsuming_loads());
1113 }
1114 // assert( phi_cnt == end_idx(), "did not schedule all" );
1115 return false;
1116 }
1117
1118 if (OptoRegScheduling && block_size_threshold_ok) {
1119 _regalloc->compute_exit_block_pressure(block);
1120 block->_reg_pressure = _regalloc->_sched_int_pressure.final_pressure();
1121 block->_freg_pressure = _regalloc->_sched_float_pressure.final_pressure();
1122 }
1123
1124 #ifndef PRODUCT
1125 if (trace_opto_pipelining()) {
1126 tty->print_cr("#");
1127 tty->print_cr("# after schedule_local");
1128 for (uint i = 0;i < block->number_of_nodes();i++) {
1129 tty->print("# ");
1130 block->get_node(i)->fast_dump();
1131 }
1132 tty->print_cr("# ");
1133
1134 if (OptoRegScheduling && block_size_threshold_ok) {
1135 tty->print_cr("# pressure info : %d", block->_pre_order);
1136 _regalloc->print_pressure_info(_regalloc->_sched_int_pressure, "int register info");
1137 _regalloc->print_pressure_info(_regalloc->_sched_float_pressure, "float register info");
1138 }
1139 tty->cr();
1140 }
1141 #endif
1142
1143 return true;
1144 }
1145
1146 //--------------------------catch_cleanup_fix_all_inputs-----------------------
1147 static void catch_cleanup_fix_all_inputs(Node *use, Node *old_def, Node *new_def) {
1148 for (uint l = 0; l < use->len(); l++) {
1149 if (use->in(l) == old_def) {
1150 if (l < use->req()) {
1151 use->set_req(l, new_def);
1152 } else {
1153 use->rm_prec(l);
1154 use->add_prec(new_def);
1155 l--;
1156 }
1157 }
1158 }
1159 }
1160
1161 //------------------------------catch_cleanup_find_cloned_def------------------
1162 Node* PhaseCFG::catch_cleanup_find_cloned_def(Block *use_blk, Node *def, Block *def_blk, int n_clone_idx) {
1163 assert( use_blk != def_blk, "Inter-block cleanup only");
1164
1165 // The use is some block below the Catch. Find and return the clone of the def
1166 // that dominates the use. If there is no clone in a dominating block, then
1167 // create a phi for the def in a dominating block.
1168
1169 // Find which successor block dominates this use. The successor
1170 // blocks must all be single-entry (from the Catch only; I will have
1171 // split blocks to make this so), hence they all dominate.
1172 while( use_blk->_dom_depth > def_blk->_dom_depth+1 )
1173 use_blk = use_blk->_idom;
1174
1175 // Find the successor
1176 Node *fixup = NULL;
1177
1178 uint j;
1179 for( j = 0; j < def_blk->_num_succs; j++ )
1180 if( use_blk == def_blk->_succs[j] )
1181 break;
1182
1183 if( j == def_blk->_num_succs ) {
1184 // Block at same level in dom-tree is not a successor. It needs a
1185 // PhiNode, the PhiNode uses from the def and IT's uses need fixup.
1186 Node_Array inputs = new Node_List(Thread::current()->resource_area());
1187 for(uint k = 1; k < use_blk->num_preds(); k++) {
1188 Block* block = get_block_for_node(use_blk->pred(k));
1189 inputs.map(k, catch_cleanup_find_cloned_def(block, def, def_blk, n_clone_idx));
1190 }
1191
1192 // Check to see if the use_blk already has an identical phi inserted.
1193 // If it exists, it will be at the first position since all uses of a
1194 // def are processed together.
1195 Node *phi = use_blk->get_node(1);
1196 if( phi->is_Phi() ) {
1197 fixup = phi;
1198 for (uint k = 1; k < use_blk->num_preds(); k++) {
1199 if (phi->in(k) != inputs[k]) {
1200 // Not a match
1201 fixup = NULL;
1202 break;
1203 }
1204 }
1205 }
1206
1207 // If an existing PhiNode was not found, make a new one.
1208 if (fixup == NULL) {
1209 Node *new_phi = PhiNode::make(use_blk->head(), def);
1210 use_blk->insert_node(new_phi, 1);
1211 map_node_to_block(new_phi, use_blk);
1212 for (uint k = 1; k < use_blk->num_preds(); k++) {
1213 new_phi->set_req(k, inputs[k]);
1214 }
1215 fixup = new_phi;
1216 }
1217
1218 } else {
1219 // Found the use just below the Catch. Make it use the clone.
1220 fixup = use_blk->get_node(n_clone_idx);
1221 }
1222
1223 return fixup;
1224 }
1225
1226 //--------------------------catch_cleanup_intra_block--------------------------
1227 // Fix all input edges in use that reference "def". The use is in the same
1228 // block as the def and both have been cloned in each successor block.
1229 static void catch_cleanup_intra_block(Node *use, Node *def, Block *blk, int beg, int n_clone_idx) {
1230
1231 // Both the use and def have been cloned. For each successor block,
1232 // get the clone of the use, and make its input the clone of the def
1233 // found in that block.
1234
1235 uint use_idx = blk->find_node(use);
1236 uint offset_idx = use_idx - beg;
1237 for( uint k = 0; k < blk->_num_succs; k++ ) {
1238 // Get clone in each successor block
1239 Block *sb = blk->_succs[k];
1240 Node *clone = sb->get_node(offset_idx+1);
1241 assert( clone->Opcode() == use->Opcode(), "" );
1242
1243 // Make use-clone reference the def-clone
1244 catch_cleanup_fix_all_inputs(clone, def, sb->get_node(n_clone_idx));
1245 }
1246 }
1247
1248 //------------------------------catch_cleanup_inter_block---------------------
1249 // Fix all input edges in use that reference "def". The use is in a different
1250 // block than the def.
1251 void PhaseCFG::catch_cleanup_inter_block(Node *use, Block *use_blk, Node *def, Block *def_blk, int n_clone_idx) {
1252 if( !use_blk ) return; // Can happen if the use is a precedence edge
1253
1254 Node *new_def = catch_cleanup_find_cloned_def(use_blk, def, def_blk, n_clone_idx);
1255 catch_cleanup_fix_all_inputs(use, def, new_def);
1256 }
1257
1258 //------------------------------call_catch_cleanup-----------------------------
1259 // If we inserted any instructions between a Call and his CatchNode,
1260 // clone the instructions on all paths below the Catch.
1261 void PhaseCFG::call_catch_cleanup(Block* block) {
1262
1263 // End of region to clone
1264 uint end = block->end_idx();
1265 if( !block->get_node(end)->is_Catch() ) return;
1266 // Start of region to clone
1267 uint beg = end;
1268 while(!block->get_node(beg-1)->is_MachProj() ||
1269 !block->get_node(beg-1)->in(0)->is_MachCall() ) {
1270 beg--;
1271 assert(beg > 0,"Catch cleanup walking beyond block boundary");
1272 }
1273 // Range of inserted instructions is [beg, end)
1274 if( beg == end ) return;
1275
1276 // Clone along all Catch output paths. Clone area between the 'beg' and
1277 // 'end' indices.
1278 for( uint i = 0; i < block->_num_succs; i++ ) {
1279 Block *sb = block->_succs[i];
1280 // Clone the entire area; ignoring the edge fixup for now.
1281 for( uint j = end; j > beg; j-- ) {
1282 // It is safe here to clone a node with anti_dependence
1283 // since clones dominate on each path.
1284 Node *clone = block->get_node(j-1)->clone();
1285 sb->insert_node(clone, 1);
1286 map_node_to_block(clone, sb);
1287 }
1288 }
1289
1290
1291 // Fixup edges. Check the def-use info per cloned Node
1292 for(uint i2 = beg; i2 < end; i2++ ) {
1293 uint n_clone_idx = i2-beg+1; // Index of clone of n in each successor block
1294 Node *n = block->get_node(i2); // Node that got cloned
1295 // Need DU safe iterator because of edge manipulation in calls.
1296 Unique_Node_List *out = new Unique_Node_List(Thread::current()->resource_area());
1297 for (DUIterator_Fast j1max, j1 = n->fast_outs(j1max); j1 < j1max; j1++) {
1298 out->push(n->fast_out(j1));
1299 }
1300 uint max = out->size();
1301 for (uint j = 0; j < max; j++) {// For all users
1302 Node *use = out->pop();
1303 Block *buse = get_block_for_node(use);
1304 if( use->is_Phi() ) {
1305 for( uint k = 1; k < use->req(); k++ )
1306 if( use->in(k) == n ) {
1307 Block* b = get_block_for_node(buse->pred(k));
1308 Node *fixup = catch_cleanup_find_cloned_def(b, n, block, n_clone_idx);
1309 use->set_req(k, fixup);
1310 }
1311 } else {
1312 if (block == buse) {
1313 catch_cleanup_intra_block(use, n, block, beg, n_clone_idx);
1314 } else {
1315 catch_cleanup_inter_block(use, buse, n, block, n_clone_idx);
1316 }
1317 }
1318 } // End for all users
1319
1320 } // End of for all Nodes in cloned area
1321
1322 // Remove the now-dead cloned ops
1323 for(uint i3 = beg; i3 < end; i3++ ) {
1324 block->get_node(beg)->disconnect_inputs(NULL, C);
1325 block->remove_node(beg);
1326 }
1327
1328 // If the successor blocks have a CreateEx node, move it back to the top
1329 for(uint i4 = 0; i4 < block->_num_succs; i4++ ) {
1330 Block *sb = block->_succs[i4];
1331 uint new_cnt = end - beg;
1332 // Remove any newly created, but dead, nodes.
1333 for( uint j = new_cnt; j > 0; j-- ) {
1334 Node *n = sb->get_node(j);
1335 if (n->outcnt() == 0 &&
1336 (!n->is_Proj() || n->as_Proj()->in(0)->outcnt() == 1) ){
1337 n->disconnect_inputs(NULL, C);
1338 sb->remove_node(j);
1339 new_cnt--;
1340 }
1341 }
1342 // If any newly created nodes remain, move the CreateEx node to the top
1343 if (new_cnt > 0) {
1344 Node *cex = sb->get_node(1+new_cnt);
1345 if( cex->is_Mach() && cex->as_Mach()->ideal_Opcode() == Op_CreateEx ) {
1346 sb->remove_node(1+new_cnt);
1347 sb->insert_node(cex, 1);
1348 }
1349 }
1350 }
1351 }