1843 case Op_CountLeadingZerosI:
1844 case Op_CountLeadingZerosL:
1845 case Op_CountTrailingZerosI:
1846 case Op_CountTrailingZerosL:
1847 case Op_PopCountI:
1848 case Op_PopCountL:
1849 if (!UsePopCountInstruction)
1850 return false;
1851 case Op_CompareAndSwapL:
1852 #ifdef _LP64
1853 case Op_CompareAndSwapP:
1854 #endif
1855 if (!VM_Version::supports_cx8())
1856 return false;
1857 break;
1858 }
1859
1860 return true; // Per default match rules are supported.
1861 }
1862
1863 int Matcher::regnum_to_fpu_offset(int regnum) {
1864 return regnum - 32; // The FP registers are in the second chunk
1865 }
1866
1867 #ifdef ASSERT
1868 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1869 #endif
1870
1871 // Vector width in bytes
1872 const int Matcher::vector_width_in_bytes(BasicType bt) {
1873 assert(MaxVectorSize == 8, "");
1874 return 8;
1875 }
1876
1877 // Vector ideal reg
1878 const int Matcher::vector_ideal_reg(int size) {
1879 assert(MaxVectorSize == 8, "");
1880 return Op_RegD;
1881 }
1882
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1843 case Op_CountLeadingZerosI:
1844 case Op_CountLeadingZerosL:
1845 case Op_CountTrailingZerosI:
1846 case Op_CountTrailingZerosL:
1847 case Op_PopCountI:
1848 case Op_PopCountL:
1849 if (!UsePopCountInstruction)
1850 return false;
1851 case Op_CompareAndSwapL:
1852 #ifdef _LP64
1853 case Op_CompareAndSwapP:
1854 #endif
1855 if (!VM_Version::supports_cx8())
1856 return false;
1857 break;
1858 }
1859
1860 return true; // Per default match rules are supported.
1861 }
1862
1863 const int Matcher::float_pressure_scale(void) {
1864 return 1;
1865 }
1866
1867 int Matcher::regnum_to_fpu_offset(int regnum) {
1868 return regnum - 32; // The FP registers are in the second chunk
1869 }
1870
1871 #ifdef ASSERT
1872 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1873 #endif
1874
1875 // Vector width in bytes
1876 const int Matcher::vector_width_in_bytes(BasicType bt) {
1877 assert(MaxVectorSize == 8, "");
1878 return 8;
1879 }
1880
1881 // Vector ideal reg
1882 const int Matcher::vector_ideal_reg(int size) {
1883 assert(MaxVectorSize == 8, "");
1884 return Op_RegD;
1885 }
1886
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