2319   check_node_count(0, "out of nodes matching instructions");
2320   if (failing()) {
2321     return;
2322   }
2323 
2324   // Build a proper-looking CFG
2325   PhaseCFG cfg(node_arena(), root(), matcher);
2326   _cfg = &cfg;
2327   {
2328     TracePhase tp("scheduler", &timers[_t_scheduler]);
2329     bool success = cfg.do_global_code_motion();
2330     if (!success) {
2331       return;
2332     }
2333 
2334     print_method(PHASE_GLOBAL_CODE_MOTION, 2);
2335     NOT_PRODUCT( verify_graph_edges(); )
2336     debug_only( cfg.verify(); )
2337   }
2338 
2339   PhaseChaitin regalloc(unique(), cfg, matcher);
2340   _regalloc = &regalloc;
2341   {
2342     TracePhase tp("regalloc", &timers[_t_registerAllocation]);
2343     // Perform register allocation.  After Chaitin, use-def chains are
2344     // no longer accurate (at spill code) and so must be ignored.
2345     // Node->LRG->reg mappings are still accurate.
2346     _regalloc->Register_Allocate();
2347 
2348     // Bail out if the allocator builds too many nodes
2349     if (failing()) {
2350       return;
2351     }
2352   }
2353 
2354   // Prior to register allocation we kept empty basic blocks in case the
2355   // the allocator needed a place to spill.  After register allocation we
2356   // are not adding any new instructions.  If any basic block is empty, we
2357   // can now safely remove it.
2358   {
2359     TracePhase tp("blockOrdering", &timers[_t_blockOrdering]);

2319   check_node_count(0, "out of nodes matching instructions");
2320   if (failing()) {
2321     return;
2322   }
2323 
2324   // Build a proper-looking CFG
2325   PhaseCFG cfg(node_arena(), root(), matcher);
2326   _cfg = &cfg;
2327   {
2328     TracePhase tp("scheduler", &timers[_t_scheduler]);
2329     bool success = cfg.do_global_code_motion();
2330     if (!success) {
2331       return;
2332     }
2333 
2334     print_method(PHASE_GLOBAL_CODE_MOTION, 2);
2335     NOT_PRODUCT( verify_graph_edges(); )
2336     debug_only( cfg.verify(); )
2337   }
2338 
2339   PhaseChaitin regalloc(unique(), cfg, matcher, false);
2340   _regalloc = &regalloc;
2341   {
2342     TracePhase tp("regalloc", &timers[_t_registerAllocation]);
2343     // Perform register allocation.  After Chaitin, use-def chains are
2344     // no longer accurate (at spill code) and so must be ignored.
2345     // Node->LRG->reg mappings are still accurate.
2346     _regalloc->Register_Allocate();
2347 
2348     // Bail out if the allocator builds too many nodes
2349     if (failing()) {
2350       return;
2351     }
2352   }
2353 
2354   // Prior to register allocation we kept empty basic blocks in case the
2355   // the allocator needed a place to spill.  After register allocation we
2356   // are not adding any new instructions.  If any basic block is empty, we
2357   // can now safely remove it.
2358   {
2359     TracePhase tp("blockOrdering", &timers[_t_blockOrdering]);