252   OptoReg::Name _new_SP;
 253 
 254   // Register number of the stack slot corresponding to the highest outgoing
 255   // argument on the stack.  Per the Big Picture in the AD file, it is:
 256   //   _new_SP + max outgoing arguments of all calls
 257   OptoReg::Name _out_arg_limit;
 258 
 259   OptoRegPair *_parm_regs;        // Array of machine registers per argument
 260   RegMask *_calling_convention_mask; // Array of RegMasks per argument
 261 
 262   // Does matcher have a match rule for this ideal node?
 263   static const bool has_match_rule(int opcode);
 264   static const bool _hasMatchRule[_last_opcode];
 265 
 266   // Does matcher have a match rule for this ideal node and is the
 267   // predicate (if there is one) true?
 268   // NOTE: If this function is used more commonly in the future, ADLC
 269   // should generate this one.
 270   static const bool match_rule_supported(int opcode);
 271 



 272   // Used to determine if we have fast l2f conversion
 273   // USII has it, USIII doesn't
 274   static const bool convL2FSupported(void);
 275 
 276   // Vector width in bytes
 277   static const int vector_width_in_bytes(BasicType bt);
 278 
 279   // Limits on vector size (number of elements).
 280   static const int max_vector_size(const BasicType bt);
 281   static const int min_vector_size(const BasicType bt);
 282   static const bool vector_size_supported(const BasicType bt, int size) {
 283     return (Matcher::max_vector_size(bt) >= size &&
 284             Matcher::min_vector_size(bt) <= size);
 285   }
 286 
 287   // Vector ideal reg
 288   static const int vector_ideal_reg(int len);
 289   static const int vector_shift_count_ideal_reg(int len);
 290 
 291   // CPU supports misaligned vectors store/load.

 252   OptoReg::Name _new_SP;
 253 
 254   // Register number of the stack slot corresponding to the highest outgoing
 255   // argument on the stack.  Per the Big Picture in the AD file, it is:
 256   //   _new_SP + max outgoing arguments of all calls
 257   OptoReg::Name _out_arg_limit;
 258 
 259   OptoRegPair *_parm_regs;        // Array of machine registers per argument
 260   RegMask *_calling_convention_mask; // Array of RegMasks per argument
 261 
 262   // Does matcher have a match rule for this ideal node?
 263   static const bool has_match_rule(int opcode);
 264   static const bool _hasMatchRule[_last_opcode];
 265 
 266   // Does matcher have a match rule for this ideal node and is the
 267   // predicate (if there is one) true?
 268   // NOTE: If this function is used more commonly in the future, ADLC
 269   // should generate this one.
 270   static const bool match_rule_supported(int opcode);
 271 
 272   // Some uarchs have different sized float register resources
 273   static const int float_pressure_scale(void);
 274 
 275   // Used to determine if we have fast l2f conversion
 276   // USII has it, USIII doesn't
 277   static const bool convL2FSupported(void);
 278 
 279   // Vector width in bytes
 280   static const int vector_width_in_bytes(BasicType bt);
 281 
 282   // Limits on vector size (number of elements).
 283   static const int max_vector_size(const BasicType bt);
 284   static const int min_vector_size(const BasicType bt);
 285   static const bool vector_size_supported(const BasicType bt, int size) {
 286     return (Matcher::max_vector_size(bt) >= size &&
 287             Matcher::min_vector_size(bt) <= size);
 288   }
 289 
 290   // Vector ideal reg
 291   static const int vector_ideal_reg(int len);
 292   static const int vector_shift_count_ideal_reg(int len);
 293 
 294   // CPU supports misaligned vectors store/load.