1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableModRefBS.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc/g1/g1CollectedHeap.inline.hpp"
42 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
59 // -----------------Table 4.5 -------------------- //
60 16, 32, 64, // EVEX_FV(0)
61 4, 4, 4, // EVEX_FV(1) - with Evex.b
62 16, 32, 64, // EVEX_FV(2) - with Evex.w
63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
64 8, 16, 32, // EVEX_HV(0)
65 4, 4, 4, // EVEX_HV(1) - with Evex.b
66 // -----------------Table 4.6 -------------------- //
67 16, 32, 64, // EVEX_FVM(0)
68 1, 1, 1, // EVEX_T1S(0)
69 2, 2, 2, // EVEX_T1S(1)
70 4, 4, 4, // EVEX_T1S(2)
71 8, 8, 8, // EVEX_T1S(3)
72 4, 4, 4, // EVEX_T1F(0)
73 8, 8, 8, // EVEX_T1F(1)
74 8, 8, 8, // EVEX_T2(0)
75 0, 16, 16, // EVEX_T2(1)
76 0, 16, 16, // EVEX_T4(0)
77 0, 0, 32, // EVEX_T4(1)
78 0, 0, 32, // EVEX_T8(0)
79 8, 16, 32, // EVEX_HVM(0)
80 4, 8, 16, // EVEX_QVM(0)
81 2, 4, 8, // EVEX_OVM(0)
82 16, 16, 16, // EVEX_M128(0)
83 8, 32, 64, // EVEX_DUP(0)
84 0, 0, 0 // EVEX_NTUP
85 };
86
87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
88 _is_lval = false;
89 _target = target;
90 switch (rtype) {
91 case relocInfo::oop_type:
92 case relocInfo::metadata_type:
93 // Oops are a special case. Normally they would be their own section
94 // but in cases like icBuffer they are literals in the code stream that
95 // we don't have a section for. We use none so that we get a literal address
96 // which is always patchable.
97 break;
98 case relocInfo::external_word_type:
99 _rspec = external_word_Relocation::spec(target);
100 break;
101 case relocInfo::internal_word_type:
102 _rspec = internal_word_Relocation::spec(target);
103 break;
104 case relocInfo::opt_virtual_call_type:
105 _rspec = opt_virtual_call_Relocation::spec();
106 break;
107 case relocInfo::static_call_type:
108 _rspec = static_call_Relocation::spec();
109 break;
110 case relocInfo::runtime_call_type:
111 _rspec = runtime_call_Relocation::spec();
112 break;
113 case relocInfo::poll_type:
114 case relocInfo::poll_return_type:
115 _rspec = Relocation::spec_simple(rtype);
116 break;
117 case relocInfo::none:
118 break;
119 default:
120 ShouldNotReachHere();
121 break;
122 }
123 }
124
125 // Implementation of Address
126
127 #ifdef _LP64
128
129 Address Address::make_array(ArrayAddress adr) {
130 // Not implementable on 64bit machines
131 // Should have been handled higher up the call chain.
132 ShouldNotReachHere();
133 return Address();
134 }
135
136 // exceedingly dangerous constructor
137 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
138 _base = noreg;
139 _index = noreg;
140 _scale = no_scale;
141 _disp = disp;
142 switch (rtype) {
143 case relocInfo::external_word_type:
144 _rspec = external_word_Relocation::spec(loc);
145 break;
146 case relocInfo::internal_word_type:
147 _rspec = internal_word_Relocation::spec(loc);
148 break;
149 case relocInfo::runtime_call_type:
150 // HMM
151 _rspec = runtime_call_Relocation::spec();
152 break;
153 case relocInfo::poll_type:
154 case relocInfo::poll_return_type:
155 _rspec = Relocation::spec_simple(rtype);
156 break;
157 case relocInfo::none:
158 break;
159 default:
160 ShouldNotReachHere();
161 }
162 }
163 #else // LP64
164
165 Address Address::make_array(ArrayAddress adr) {
166 AddressLiteral base = adr.base();
167 Address index = adr.index();
168 assert(index._disp == 0, "must not have disp"); // maybe it can?
169 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
170 array._rspec = base._rspec;
171 return array;
172 }
173
174 // exceedingly dangerous constructor
175 Address::Address(address loc, RelocationHolder spec) {
176 _base = noreg;
177 _index = noreg;
178 _scale = no_scale;
179 _disp = (intptr_t) loc;
180 _rspec = spec;
181 }
182
183 #endif // _LP64
184
185
186
187 // Convert the raw encoding form into the form expected by the constructor for
188 // Address. An index of 4 (rsp) corresponds to having no index, so convert
189 // that to noreg for the Address constructor.
190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
191 RelocationHolder rspec;
192 if (disp_reloc != relocInfo::none) {
193 rspec = Relocation::spec_simple(disp_reloc);
194 }
195 bool valid_index = index != rsp->encoding();
196 if (valid_index) {
197 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
198 madr._rspec = rspec;
199 return madr;
200 } else {
201 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
202 madr._rspec = rspec;
203 return madr;
204 }
205 }
206
207 // Implementation of Assembler
208
209 int AbstractAssembler::code_fill_byte() {
210 return (u_char)'\xF4'; // hlt
211 }
212
213 // make this go away someday
214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
215 if (rtype == relocInfo::none)
216 emit_int32(data);
217 else
218 emit_data(data, Relocation::spec_simple(rtype), format);
219 }
220
221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
222 assert(imm_operand == 0, "default format must be immediate in this file");
223 assert(inst_mark() != NULL, "must be inside InstructionMark");
224 if (rspec.type() != relocInfo::none) {
225 #ifdef ASSERT
226 check_relocation(rspec, format);
227 #endif
228 // Do not use AbstractAssembler::relocate, which is not intended for
229 // embedded words. Instead, relocate to the enclosing instruction.
230
231 // hack. call32 is too wide for mask so use disp32
232 if (format == call32_operand)
233 code_section()->relocate(inst_mark(), rspec, disp32_operand);
234 else
235 code_section()->relocate(inst_mark(), rspec, format);
236 }
237 emit_int32(data);
238 }
239
240 static int encode(Register r) {
241 int enc = r->encoding();
242 if (enc >= 8) {
243 enc -= 8;
244 }
245 return enc;
246 }
247
248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
249 assert(dst->has_byte_register(), "must have byte register");
250 assert(isByte(op1) && isByte(op2), "wrong opcode");
251 assert(isByte(imm8), "not a byte");
252 assert((op1 & 0x01) == 0, "should be 8bit operation");
253 emit_int8(op1);
254 emit_int8(op2 | encode(dst));
255 emit_int8(imm8);
256 }
257
258
259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
260 assert(isByte(op1) && isByte(op2), "wrong opcode");
261 assert((op1 & 0x01) == 1, "should be 32bit operation");
262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
263 if (is8bit(imm32)) {
264 emit_int8(op1 | 0x02); // set sign bit
265 emit_int8(op2 | encode(dst));
266 emit_int8(imm32 & 0xFF);
267 } else {
268 emit_int8(op1);
269 emit_int8(op2 | encode(dst));
270 emit_int32(imm32);
271 }
272 }
273
274 // Force generation of a 4 byte immediate value even if it fits into 8bit
275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
276 assert(isByte(op1) && isByte(op2), "wrong opcode");
277 assert((op1 & 0x01) == 1, "should be 32bit operation");
278 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
279 emit_int8(op1);
280 emit_int8(op2 | encode(dst));
281 emit_int32(imm32);
282 }
283
284 // immediate-to-memory forms
285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
286 assert((op1 & 0x01) == 1, "should be 32bit operation");
287 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
288 if (is8bit(imm32)) {
289 emit_int8(op1 | 0x02); // set sign bit
290 emit_operand(rm, adr, 1);
291 emit_int8(imm32 & 0xFF);
292 } else {
293 emit_int8(op1);
294 emit_operand(rm, adr, 4);
295 emit_int32(imm32);
296 }
297 }
298
299
300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
301 assert(isByte(op1) && isByte(op2), "wrong opcode");
302 emit_int8(op1);
303 emit_int8(op2 | encode(dst) << 3 | encode(src));
304 }
305
306
307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
309 int mod_idx = 0;
310 // We will test if the displacement fits the compressed format and if so
311 // apply the compression to the displacment iff the result is8bit.
312 if (VM_Version::supports_evex() && is_evex_inst) {
313 switch (cur_tuple_type) {
314 case EVEX_FV:
315 if ((cur_encoding & VEX_W) == VEX_W) {
316 mod_idx += 2 + ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
317 } else {
318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
319 }
320 break;
321
322 case EVEX_HV:
323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
324 break;
325
326 case EVEX_FVM:
327 break;
328
329 case EVEX_T1S:
330 switch (in_size_in_bits) {
331 case EVEX_8bit:
332 break;
333
334 case EVEX_16bit:
335 mod_idx = 1;
336 break;
337
338 case EVEX_32bit:
339 mod_idx = 2;
340 break;
341
342 case EVEX_64bit:
343 mod_idx = 3;
344 break;
345 }
346 break;
347
348 case EVEX_T1F:
349 case EVEX_T2:
350 case EVEX_T4:
351 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
352 break;
353
354 case EVEX_T8:
355 break;
356
357 case EVEX_HVM:
358 break;
359
360 case EVEX_QVM:
361 break;
362
363 case EVEX_OVM:
364 break;
365
366 case EVEX_M128:
367 break;
368
369 case EVEX_DUP:
370 break;
371
372 default:
373 assert(0, "no valid evex tuple_table entry");
374 break;
375 }
376
377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
379 if ((disp % disp_factor) == 0) {
380 int new_disp = disp / disp_factor;
381 if ((-0x80 <= new_disp && new_disp < 0x80)) {
382 disp = new_disp;
383 }
384 } else {
385 return false;
386 }
387 }
388 }
389 return (-0x80 <= disp && disp < 0x80);
390 }
391
392
393 bool Assembler::emit_compressed_disp_byte(int &disp) {
394 int mod_idx = 0;
395 // We will test if the displacement fits the compressed format and if so
396 // apply the compression to the displacment iff the result is8bit.
397 if (VM_Version::supports_evex() && _is_evex_instruction) {
398 switch (_tuple_type) {
399 case EVEX_FV:
400 if ((_evex_encoding & VEX_W) == VEX_W) {
401 mod_idx += 2 + ((_evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
402 } else {
403 mod_idx = ((_evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
404 }
405 break;
406
407 case EVEX_HV:
408 mod_idx = ((_evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
409 break;
410
411 case EVEX_FVM:
412 break;
413
414 case EVEX_T1S:
415 switch (_input_size_in_bits) {
416 case EVEX_8bit:
417 break;
418
419 case EVEX_16bit:
420 mod_idx = 1;
421 break;
422
423 case EVEX_32bit:
424 mod_idx = 2;
425 break;
426
427 case EVEX_64bit:
428 mod_idx = 3;
429 break;
430 }
431 break;
432
433 case EVEX_T1F:
434 case EVEX_T2:
435 case EVEX_T4:
436 mod_idx = (_input_size_in_bits == EVEX_64bit) ? 1 : 0;
437 break;
438
439 case EVEX_T8:
440 break;
441
442 case EVEX_HVM:
443 break;
444
445 case EVEX_QVM:
446 break;
447
448 case EVEX_OVM:
449 break;
450
451 case EVEX_M128:
452 break;
453
454 case EVEX_DUP:
455 break;
456
457 default:
458 assert(0, "no valid evex tuple_table entry");
459 break;
460 }
461
462 if (_avx_vector_len >= AVX_128bit && _avx_vector_len <= AVX_512bit) {
463 int disp_factor = tuple_table[_tuple_type + mod_idx][_avx_vector_len];
464 if ((disp % disp_factor) == 0) {
465 int new_disp = disp / disp_factor;
466 if (is8bit(new_disp)) {
467 disp = new_disp;
468 }
469 } else {
470 return false;
471 }
472 }
473 }
474 return is8bit(disp);
475 }
476
477
478 void Assembler::emit_operand(Register reg, Register base, Register index,
479 Address::ScaleFactor scale, int disp,
480 RelocationHolder const& rspec,
481 int rip_relative_correction) {
482 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
483
484 // Encode the registers as needed in the fields they are used in
485
486 int regenc = encode(reg) << 3;
487 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
488 int baseenc = base->is_valid() ? encode(base) : 0;
489
490 if (base->is_valid()) {
491 if (index->is_valid()) {
492 assert(scale != Address::no_scale, "inconsistent address");
493 // [base + index*scale + disp]
494 if (disp == 0 && rtype == relocInfo::none &&
495 base != rbp LP64_ONLY(&& base != r13)) {
496 // [base + index*scale]
497 // [00 reg 100][ss index base]
498 assert(index != rsp, "illegal addressing mode");
499 emit_int8(0x04 | regenc);
500 emit_int8(scale << 6 | indexenc | baseenc);
501 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
502 // [base + index*scale + imm8]
503 // [01 reg 100][ss index base] imm8
504 assert(index != rsp, "illegal addressing mode");
505 emit_int8(0x44 | regenc);
506 emit_int8(scale << 6 | indexenc | baseenc);
507 emit_int8(disp & 0xFF);
508 } else {
509 // [base + index*scale + disp32]
510 // [10 reg 100][ss index base] disp32
511 assert(index != rsp, "illegal addressing mode");
512 emit_int8(0x84 | regenc);
513 emit_int8(scale << 6 | indexenc | baseenc);
514 emit_data(disp, rspec, disp32_operand);
515 }
516 } else if (base == rsp LP64_ONLY(|| base == r12)) {
517 // [rsp + disp]
518 if (disp == 0 && rtype == relocInfo::none) {
519 // [rsp]
520 // [00 reg 100][00 100 100]
521 emit_int8(0x04 | regenc);
522 emit_int8(0x24);
523 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
524 // [rsp + imm8]
525 // [01 reg 100][00 100 100] disp8
526 emit_int8(0x44 | regenc);
527 emit_int8(0x24);
528 emit_int8(disp & 0xFF);
529 } else {
530 // [rsp + imm32]
531 // [10 reg 100][00 100 100] disp32
532 emit_int8(0x84 | regenc);
533 emit_int8(0x24);
534 emit_data(disp, rspec, disp32_operand);
535 }
536 } else {
537 // [base + disp]
538 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
539 if (disp == 0 && rtype == relocInfo::none &&
540 base != rbp LP64_ONLY(&& base != r13)) {
541 // [base]
542 // [00 reg base]
543 emit_int8(0x00 | regenc | baseenc);
544 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
545 // [base + disp8]
546 // [01 reg base] disp8
547 emit_int8(0x40 | regenc | baseenc);
548 emit_int8(disp & 0xFF);
549 } else {
550 // [base + disp32]
551 // [10 reg base] disp32
552 emit_int8(0x80 | regenc | baseenc);
553 emit_data(disp, rspec, disp32_operand);
554 }
555 }
556 } else {
557 if (index->is_valid()) {
558 assert(scale != Address::no_scale, "inconsistent address");
559 // [index*scale + disp]
560 // [00 reg 100][ss index 101] disp32
561 assert(index != rsp, "illegal addressing mode");
562 emit_int8(0x04 | regenc);
563 emit_int8(scale << 6 | indexenc | 0x05);
564 emit_data(disp, rspec, disp32_operand);
565 } else if (rtype != relocInfo::none ) {
566 // [disp] (64bit) RIP-RELATIVE (32bit) abs
567 // [00 000 101] disp32
568
569 emit_int8(0x05 | regenc);
570 // Note that the RIP-rel. correction applies to the generated
571 // disp field, but _not_ to the target address in the rspec.
572
573 // disp was created by converting the target address minus the pc
574 // at the start of the instruction. That needs more correction here.
575 // intptr_t disp = target - next_ip;
576 assert(inst_mark() != NULL, "must be inside InstructionMark");
577 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
578 int64_t adjusted = disp;
579 // Do rip-rel adjustment for 64bit
580 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
581 assert(is_simm32(adjusted),
582 "must be 32bit offset (RIP relative address)");
583 emit_data((int32_t) adjusted, rspec, disp32_operand);
584
585 } else {
586 // 32bit never did this, did everything as the rip-rel/disp code above
587 // [disp] ABSOLUTE
588 // [00 reg 100][00 100 101] disp32
589 emit_int8(0x04 | regenc);
590 emit_int8(0x25);
591 emit_data(disp, rspec, disp32_operand);
592 }
593 }
594 _is_evex_instruction = false;
595 }
596
597 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
598 Address::ScaleFactor scale, int disp,
599 RelocationHolder const& rspec) {
600 if (UseAVX > 2) {
601 int xreg_enc = reg->encoding();
602 if (xreg_enc > 15) {
603 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
604 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
605 return;
606 }
607 }
608 emit_operand((Register)reg, base, index, scale, disp, rspec);
609 }
610
611 // Secret local extension to Assembler::WhichOperand:
612 #define end_pc_operand (_WhichOperand_limit)
613
614 address Assembler::locate_operand(address inst, WhichOperand which) {
615 // Decode the given instruction, and return the address of
616 // an embedded 32-bit operand word.
617
618 // If "which" is disp32_operand, selects the displacement portion
619 // of an effective address specifier.
620 // If "which" is imm64_operand, selects the trailing immediate constant.
621 // If "which" is call32_operand, selects the displacement of a call or jump.
622 // Caller is responsible for ensuring that there is such an operand,
623 // and that it is 32/64 bits wide.
624
625 // If "which" is end_pc_operand, find the end of the instruction.
626
627 address ip = inst;
628 bool is_64bit = false;
629
630 debug_only(bool has_disp32 = false);
631 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
632
633 again_after_prefix:
634 switch (0xFF & *ip++) {
635
636 // These convenience macros generate groups of "case" labels for the switch.
637 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
638 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
639 case (x)+4: case (x)+5: case (x)+6: case (x)+7
640 #define REP16(x) REP8((x)+0): \
641 case REP8((x)+8)
642
643 case CS_segment:
644 case SS_segment:
645 case DS_segment:
646 case ES_segment:
647 case FS_segment:
648 case GS_segment:
649 // Seems dubious
650 LP64_ONLY(assert(false, "shouldn't have that prefix"));
651 assert(ip == inst+1, "only one prefix allowed");
652 goto again_after_prefix;
653
654 case 0x67:
655 case REX:
656 case REX_B:
657 case REX_X:
658 case REX_XB:
659 case REX_R:
660 case REX_RB:
661 case REX_RX:
662 case REX_RXB:
663 NOT_LP64(assert(false, "64bit prefixes"));
664 goto again_after_prefix;
665
666 case REX_W:
667 case REX_WB:
668 case REX_WX:
669 case REX_WXB:
670 case REX_WR:
671 case REX_WRB:
672 case REX_WRX:
673 case REX_WRXB:
674 NOT_LP64(assert(false, "64bit prefixes"));
675 is_64bit = true;
676 goto again_after_prefix;
677
678 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
679 case 0x88: // movb a, r
680 case 0x89: // movl a, r
681 case 0x8A: // movb r, a
682 case 0x8B: // movl r, a
683 case 0x8F: // popl a
684 debug_only(has_disp32 = true);
685 break;
686
687 case 0x68: // pushq #32
688 if (which == end_pc_operand) {
689 return ip + 4;
690 }
691 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
692 return ip; // not produced by emit_operand
693
694 case 0x66: // movw ... (size prefix)
695 again_after_size_prefix2:
696 switch (0xFF & *ip++) {
697 case REX:
698 case REX_B:
699 case REX_X:
700 case REX_XB:
701 case REX_R:
702 case REX_RB:
703 case REX_RX:
704 case REX_RXB:
705 case REX_W:
706 case REX_WB:
707 case REX_WX:
708 case REX_WXB:
709 case REX_WR:
710 case REX_WRB:
711 case REX_WRX:
712 case REX_WRXB:
713 NOT_LP64(assert(false, "64bit prefix found"));
714 goto again_after_size_prefix2;
715 case 0x8B: // movw r, a
716 case 0x89: // movw a, r
717 debug_only(has_disp32 = true);
718 break;
719 case 0xC7: // movw a, #16
720 debug_only(has_disp32 = true);
721 tail_size = 2; // the imm16
722 break;
723 case 0x0F: // several SSE/SSE2 variants
724 ip--; // reparse the 0x0F
725 goto again_after_prefix;
726 default:
727 ShouldNotReachHere();
728 }
729 break;
730
731 case REP8(0xB8): // movl/q r, #32/#64(oop?)
732 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
733 // these asserts are somewhat nonsensical
734 #ifndef _LP64
735 assert(which == imm_operand || which == disp32_operand,
736 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)));
737 #else
738 assert((which == call32_operand || which == imm_operand) && is_64bit ||
739 which == narrow_oop_operand && !is_64bit,
740 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)));
741 #endif // _LP64
742 return ip;
743
744 case 0x69: // imul r, a, #32
745 case 0xC7: // movl a, #32(oop?)
746 tail_size = 4;
747 debug_only(has_disp32 = true); // has both kinds of operands!
748 break;
749
750 case 0x0F: // movx..., etc.
751 switch (0xFF & *ip++) {
752 case 0x3A: // pcmpestri
753 tail_size = 1;
754 case 0x38: // ptest, pmovzxbw
755 ip++; // skip opcode
756 debug_only(has_disp32 = true); // has both kinds of operands!
757 break;
758
759 case 0x70: // pshufd r, r/a, #8
760 debug_only(has_disp32 = true); // has both kinds of operands!
761 case 0x73: // psrldq r, #8
762 tail_size = 1;
763 break;
764
765 case 0x12: // movlps
766 case 0x28: // movaps
767 case 0x2E: // ucomiss
768 case 0x2F: // comiss
769 case 0x54: // andps
770 case 0x55: // andnps
771 case 0x56: // orps
772 case 0x57: // xorps
773 case 0x59: //mulpd
774 case 0x6E: // movd
775 case 0x7E: // movd
776 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
777 debug_only(has_disp32 = true);
778 break;
779
780 case 0xAD: // shrd r, a, %cl
781 case 0xAF: // imul r, a
782 case 0xBE: // movsbl r, a (movsxb)
783 case 0xBF: // movswl r, a (movsxw)
784 case 0xB6: // movzbl r, a (movzxb)
785 case 0xB7: // movzwl r, a (movzxw)
786 case REP16(0x40): // cmovl cc, r, a
787 case 0xB0: // cmpxchgb
788 case 0xB1: // cmpxchg
789 case 0xC1: // xaddl
790 case 0xC7: // cmpxchg8
791 case REP16(0x90): // setcc a
792 debug_only(has_disp32 = true);
793 // fall out of the switch to decode the address
794 break;
795
796 case 0xC4: // pinsrw r, a, #8
797 debug_only(has_disp32 = true);
798 case 0xC5: // pextrw r, r, #8
799 tail_size = 1; // the imm8
800 break;
801
802 case 0xAC: // shrd r, a, #8
803 debug_only(has_disp32 = true);
804 tail_size = 1; // the imm8
805 break;
806
807 case REP16(0x80): // jcc rdisp32
808 if (which == end_pc_operand) return ip + 4;
809 assert(which == call32_operand, "jcc has no disp32 or imm");
810 return ip;
811 default:
812 ShouldNotReachHere();
813 }
814 break;
815
816 case 0x81: // addl a, #32; addl r, #32
817 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
818 // on 32bit in the case of cmpl, the imm might be an oop
819 tail_size = 4;
820 debug_only(has_disp32 = true); // has both kinds of operands!
821 break;
822
823 case 0x83: // addl a, #8; addl r, #8
824 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
825 debug_only(has_disp32 = true); // has both kinds of operands!
826 tail_size = 1;
827 break;
828
829 case 0x9B:
830 switch (0xFF & *ip++) {
831 case 0xD9: // fnstcw a
832 debug_only(has_disp32 = true);
833 break;
834 default:
835 ShouldNotReachHere();
836 }
837 break;
838
839 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
840 case REP4(0x10): // adc...
841 case REP4(0x20): // and...
842 case REP4(0x30): // xor...
843 case REP4(0x08): // or...
844 case REP4(0x18): // sbb...
845 case REP4(0x28): // sub...
846 case 0xF7: // mull a
847 case 0x8D: // lea r, a
848 case 0x87: // xchg r, a
849 case REP4(0x38): // cmp...
850 case 0x85: // test r, a
851 debug_only(has_disp32 = true); // has both kinds of operands!
852 break;
853
854 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
855 case 0xC6: // movb a, #8
856 case 0x80: // cmpb a, #8
857 case 0x6B: // imul r, a, #8
858 debug_only(has_disp32 = true); // has both kinds of operands!
859 tail_size = 1; // the imm8
860 break;
861
862 case 0xC4: // VEX_3bytes
863 case 0xC5: // VEX_2bytes
864 assert((UseAVX > 0), "shouldn't have VEX prefix");
865 assert(ip == inst+1, "no prefixes allowed");
866 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
867 // but they have prefix 0x0F and processed when 0x0F processed above.
868 //
869 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
870 // instructions (these instructions are not supported in 64-bit mode).
871 // To distinguish them bits [7:6] are set in the VEX second byte since
872 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
873 // those VEX bits REX and vvvv bits are inverted.
874 //
875 // Fortunately C2 doesn't generate these instructions so we don't need
876 // to check for them in product version.
877
878 // Check second byte
879 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
880
881 int vex_opcode;
882 // First byte
883 if ((0xFF & *inst) == VEX_3bytes) {
884 vex_opcode = VEX_OPCODE_MASK & *ip;
885 ip++; // third byte
886 is_64bit = ((VEX_W & *ip) == VEX_W);
887 } else {
888 vex_opcode = VEX_OPCODE_0F;
889 }
890 ip++; // opcode
891 // To find the end of instruction (which == end_pc_operand).
892 switch (vex_opcode) {
893 case VEX_OPCODE_0F:
894 switch (0xFF & *ip) {
895 case 0x70: // pshufd r, r/a, #8
896 case 0x71: // ps[rl|ra|ll]w r, #8
897 case 0x72: // ps[rl|ra|ll]d r, #8
898 case 0x73: // ps[rl|ra|ll]q r, #8
899 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
900 case 0xC4: // pinsrw r, r, r/a, #8
901 case 0xC5: // pextrw r/a, r, #8
902 case 0xC6: // shufp[s|d] r, r, r/a, #8
903 tail_size = 1; // the imm8
904 break;
905 }
906 break;
907 case VEX_OPCODE_0F_3A:
908 tail_size = 1;
909 break;
910 }
911 ip++; // skip opcode
912 debug_only(has_disp32 = true); // has both kinds of operands!
913 break;
914
915 case 0x62: // EVEX_4bytes
916 assert((UseAVX > 0), "shouldn't have EVEX prefix");
917 assert(ip == inst+1, "no prefixes allowed");
918 // no EVEX collisions, all instructions that have 0x62 opcodes
919 // have EVEX versions and are subopcodes of 0x66
920 ip++; // skip P0 and exmaine W in P1
921 is_64bit = ((VEX_W & *ip) == VEX_W);
922 ip++; // move to P2
923 ip++; // skip P2, move to opcode
924 // To find the end of instruction (which == end_pc_operand).
925 switch (0xFF & *ip) {
926 case 0x61: // pcmpestri r, r/a, #8
927 case 0x70: // pshufd r, r/a, #8
928 case 0x73: // psrldq r, #8
929 tail_size = 1; // the imm8
930 break;
931 default:
932 break;
933 }
934 ip++; // skip opcode
935 debug_only(has_disp32 = true); // has both kinds of operands!
936 break;
937
938 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
939 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
940 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
941 case 0xDD: // fld_d a; fst_d a; fstp_d a
942 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
943 case 0xDF: // fild_d a; fistp_d a
944 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
945 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
946 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
947 debug_only(has_disp32 = true);
948 break;
949
950 case 0xE8: // call rdisp32
951 case 0xE9: // jmp rdisp32
952 if (which == end_pc_operand) return ip + 4;
953 assert(which == call32_operand, "call has no disp32 or imm");
954 return ip;
955
956 case 0xF0: // Lock
957 assert(os::is_MP(), "only on MP");
958 goto again_after_prefix;
959
960 case 0xF3: // For SSE
961 case 0xF2: // For SSE2
962 switch (0xFF & *ip++) {
963 case REX:
964 case REX_B:
965 case REX_X:
966 case REX_XB:
967 case REX_R:
968 case REX_RB:
969 case REX_RX:
970 case REX_RXB:
971 case REX_W:
972 case REX_WB:
973 case REX_WX:
974 case REX_WXB:
975 case REX_WR:
976 case REX_WRB:
977 case REX_WRX:
978 case REX_WRXB:
979 NOT_LP64(assert(false, "found 64bit prefix"));
980 ip++;
981 default:
982 ip++;
983 }
984 debug_only(has_disp32 = true); // has both kinds of operands!
985 break;
986
987 default:
988 ShouldNotReachHere();
989
990 #undef REP8
991 #undef REP16
992 }
993
994 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
995 #ifdef _LP64
996 assert(which != imm_operand, "instruction is not a movq reg, imm64");
997 #else
998 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
999 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1000 #endif // LP64
1001 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1002
1003 // parse the output of emit_operand
1004 int op2 = 0xFF & *ip++;
1005 int base = op2 & 0x07;
1006 int op3 = -1;
1007 const int b100 = 4;
1008 const int b101 = 5;
1009 if (base == b100 && (op2 >> 6) != 3) {
1010 op3 = 0xFF & *ip++;
1011 base = op3 & 0x07; // refetch the base
1012 }
1013 // now ip points at the disp (if any)
1014
1015 switch (op2 >> 6) {
1016 case 0:
1017 // [00 reg 100][ss index base]
1018 // [00 reg 100][00 100 esp]
1019 // [00 reg base]
1020 // [00 reg 100][ss index 101][disp32]
1021 // [00 reg 101] [disp32]
1022
1023 if (base == b101) {
1024 if (which == disp32_operand)
1025 return ip; // caller wants the disp32
1026 ip += 4; // skip the disp32
1027 }
1028 break;
1029
1030 case 1:
1031 // [01 reg 100][ss index base][disp8]
1032 // [01 reg 100][00 100 esp][disp8]
1033 // [01 reg base] [disp8]
1034 ip += 1; // skip the disp8
1035 break;
1036
1037 case 2:
1038 // [10 reg 100][ss index base][disp32]
1039 // [10 reg 100][00 100 esp][disp32]
1040 // [10 reg base] [disp32]
1041 if (which == disp32_operand)
1042 return ip; // caller wants the disp32
1043 ip += 4; // skip the disp32
1044 break;
1045
1046 case 3:
1047 // [11 reg base] (not a memory addressing mode)
1048 break;
1049 }
1050
1051 if (which == end_pc_operand) {
1052 return ip + tail_size;
1053 }
1054
1055 #ifdef _LP64
1056 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1057 #else
1058 assert(which == imm_operand, "instruction has only an imm field");
1059 #endif // LP64
1060 return ip;
1061 }
1062
1063 address Assembler::locate_next_instruction(address inst) {
1064 // Secretly share code with locate_operand:
1065 return locate_operand(inst, end_pc_operand);
1066 }
1067
1068
1069 #ifdef ASSERT
1070 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1071 address inst = inst_mark();
1072 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1073 address opnd;
1074
1075 Relocation* r = rspec.reloc();
1076 if (r->type() == relocInfo::none) {
1077 return;
1078 } else if (r->is_call() || format == call32_operand) {
1079 // assert(format == imm32_operand, "cannot specify a nonzero format");
1080 opnd = locate_operand(inst, call32_operand);
1081 } else if (r->is_data()) {
1082 assert(format == imm_operand || format == disp32_operand
1083 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1084 opnd = locate_operand(inst, (WhichOperand)format);
1085 } else {
1086 assert(format == imm_operand, "cannot specify a format");
1087 return;
1088 }
1089 assert(opnd == pc(), "must put operand where relocs can find it");
1090 }
1091 #endif // ASSERT
1092
1093 void Assembler::emit_operand32(Register reg, Address adr) {
1094 assert(reg->encoding() < 8, "no extended registers");
1095 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1096 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1097 adr._rspec);
1098 }
1099
1100 void Assembler::emit_operand(Register reg, Address adr,
1101 int rip_relative_correction) {
1102 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1103 adr._rspec,
1104 rip_relative_correction);
1105 }
1106
1107 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1108 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1109 adr._rspec);
1110 }
1111
1112 // MMX operations
1113 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1114 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1115 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1116 }
1117
1118 // work around gcc (3.2.1-7a) bug
1119 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1120 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1121 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1122 }
1123
1124
1125 void Assembler::emit_farith(int b1, int b2, int i) {
1126 assert(isByte(b1) && isByte(b2), "wrong opcode");
1127 assert(0 <= i && i < 8, "illegal stack offset");
1128 emit_int8(b1);
1129 emit_int8(b2 + i);
1130 }
1131
1132
1133 // Now the Assembler instructions (identical for 32/64 bits)
1134
1135 void Assembler::adcl(Address dst, int32_t imm32) {
1136 InstructionMark im(this);
1137 prefix(dst);
1138 emit_arith_operand(0x81, rdx, dst, imm32);
1139 }
1140
1141 void Assembler::adcl(Address dst, Register src) {
1142 InstructionMark im(this);
1143 prefix(dst, src);
1144 emit_int8(0x11);
1145 emit_operand(src, dst);
1146 }
1147
1148 void Assembler::adcl(Register dst, int32_t imm32) {
1149 prefix(dst);
1150 emit_arith(0x81, 0xD0, dst, imm32);
1151 }
1152
1153 void Assembler::adcl(Register dst, Address src) {
1154 InstructionMark im(this);
1155 prefix(src, dst);
1156 emit_int8(0x13);
1157 emit_operand(dst, src);
1158 }
1159
1160 void Assembler::adcl(Register dst, Register src) {
1161 (void) prefix_and_encode(dst->encoding(), src->encoding());
1162 emit_arith(0x13, 0xC0, dst, src);
1163 }
1164
1165 void Assembler::addl(Address dst, int32_t imm32) {
1166 InstructionMark im(this);
1167 prefix(dst);
1168 emit_arith_operand(0x81, rax, dst, imm32);
1169 }
1170
1171 void Assembler::addl(Address dst, Register src) {
1172 InstructionMark im(this);
1173 prefix(dst, src);
1174 emit_int8(0x01);
1175 emit_operand(src, dst);
1176 }
1177
1178 void Assembler::addl(Register dst, int32_t imm32) {
1179 prefix(dst);
1180 emit_arith(0x81, 0xC0, dst, imm32);
1181 }
1182
1183 void Assembler::addl(Register dst, Address src) {
1184 InstructionMark im(this);
1185 prefix(src, dst);
1186 emit_int8(0x03);
1187 emit_operand(dst, src);
1188 }
1189
1190 void Assembler::addl(Register dst, Register src) {
1191 (void) prefix_and_encode(dst->encoding(), src->encoding());
1192 emit_arith(0x03, 0xC0, dst, src);
1193 }
1194
1195 void Assembler::addr_nop_4() {
1196 assert(UseAddressNop, "no CPU support");
1197 // 4 bytes: NOP DWORD PTR [EAX+0]
1198 emit_int8(0x0F);
1199 emit_int8(0x1F);
1200 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1201 emit_int8(0); // 8-bits offset (1 byte)
1202 }
1203
1204 void Assembler::addr_nop_5() {
1205 assert(UseAddressNop, "no CPU support");
1206 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1207 emit_int8(0x0F);
1208 emit_int8(0x1F);
1209 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1210 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1211 emit_int8(0); // 8-bits offset (1 byte)
1212 }
1213
1214 void Assembler::addr_nop_7() {
1215 assert(UseAddressNop, "no CPU support");
1216 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1217 emit_int8(0x0F);
1218 emit_int8(0x1F);
1219 emit_int8((unsigned char)0x80);
1220 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1221 emit_int32(0); // 32-bits offset (4 bytes)
1222 }
1223
1224 void Assembler::addr_nop_8() {
1225 assert(UseAddressNop, "no CPU support");
1226 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1227 emit_int8(0x0F);
1228 emit_int8(0x1F);
1229 emit_int8((unsigned char)0x84);
1230 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1231 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1232 emit_int32(0); // 32-bits offset (4 bytes)
1233 }
1234
1235 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1236 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1237 if (VM_Version::supports_evex()) {
1238 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_F2);
1239 } else {
1240 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
1241 }
1242 }
1243
1244 void Assembler::addsd(XMMRegister dst, Address src) {
1245 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1246 if (VM_Version::supports_evex()) {
1247 _tuple_type = EVEX_T1S;
1248 _input_size_in_bits = EVEX_64bit;
1249 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_F2);
1250 } else {
1251 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
1252 }
1253 }
1254
1255 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1256 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1257 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1258 }
1259
1260 void Assembler::addss(XMMRegister dst, Address src) {
1261 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1262 if (VM_Version::supports_evex()) {
1263 _tuple_type = EVEX_T1S;
1264 _input_size_in_bits = EVEX_32bit;
1265 }
1266 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1267 }
1268
1269 void Assembler::aesdec(XMMRegister dst, Address src) {
1270 assert(VM_Version::supports_aes(), "");
1271 InstructionMark im(this);
1272 simd_prefix(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
1273 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
1274 emit_int8((unsigned char)0xDE);
1275 emit_operand(dst, src);
1276 }
1277
1278 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1279 assert(VM_Version::supports_aes(), "");
1280 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
1281 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
1282 emit_int8((unsigned char)0xDE);
1283 emit_int8(0xC0 | encode);
1284 }
1285
1286 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1287 assert(VM_Version::supports_aes(), "");
1288 InstructionMark im(this);
1289 simd_prefix(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
1290 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
1291 emit_int8((unsigned char)0xDF);
1292 emit_operand(dst, src);
1293 }
1294
1295 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1296 assert(VM_Version::supports_aes(), "");
1297 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
1298 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
1299 emit_int8((unsigned char)0xDF);
1300 emit_int8((unsigned char)(0xC0 | encode));
1301 }
1302
1303 void Assembler::aesenc(XMMRegister dst, Address src) {
1304 assert(VM_Version::supports_aes(), "");
1305 InstructionMark im(this);
1306 simd_prefix(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
1307 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
1308 emit_int8((unsigned char)0xDC);
1309 emit_operand(dst, src);
1310 }
1311
1312 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1313 assert(VM_Version::supports_aes(), "");
1314 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
1315 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
1316 emit_int8((unsigned char)0xDC);
1317 emit_int8(0xC0 | encode);
1318 }
1319
1320 void Assembler::aesenclast(XMMRegister dst, Address src) {
1321 assert(VM_Version::supports_aes(), "");
1322 InstructionMark im(this);
1323 simd_prefix(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
1324 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
1325 emit_int8((unsigned char)0xDD);
1326 emit_operand(dst, src);
1327 }
1328
1329 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1330 assert(VM_Version::supports_aes(), "");
1331 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
1332 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
1333 emit_int8((unsigned char)0xDD);
1334 emit_int8((unsigned char)(0xC0 | encode));
1335 }
1336
1337 void Assembler::andl(Address dst, int32_t imm32) {
1338 InstructionMark im(this);
1339 prefix(dst);
1340 emit_int8((unsigned char)0x81);
1341 emit_operand(rsp, dst, 4);
1342 emit_int32(imm32);
1343 }
1344
1345 void Assembler::andl(Register dst, int32_t imm32) {
1346 prefix(dst);
1347 emit_arith(0x81, 0xE0, dst, imm32);
1348 }
1349
1350 void Assembler::andl(Register dst, Address src) {
1351 InstructionMark im(this);
1352 prefix(src, dst);
1353 emit_int8(0x23);
1354 emit_operand(dst, src);
1355 }
1356
1357 void Assembler::andl(Register dst, Register src) {
1358 (void) prefix_and_encode(dst->encoding(), src->encoding());
1359 emit_arith(0x23, 0xC0, dst, src);
1360 }
1361
1362 void Assembler::andnl(Register dst, Register src1, Register src2) {
1363 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1364 int encode = vex_prefix_0F38_and_encode_legacy(dst, src1, src2);
1365 emit_int8((unsigned char)0xF2);
1366 emit_int8((unsigned char)(0xC0 | encode));
1367 }
1368
1369 void Assembler::andnl(Register dst, Register src1, Address src2) {
1370 InstructionMark im(this);
1371 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1372 vex_prefix_0F38_legacy(dst, src1, src2);
1373 emit_int8((unsigned char)0xF2);
1374 emit_operand(dst, src2);
1375 }
1376
1377 void Assembler::bsfl(Register dst, Register src) {
1378 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1379 emit_int8(0x0F);
1380 emit_int8((unsigned char)0xBC);
1381 emit_int8((unsigned char)(0xC0 | encode));
1382 }
1383
1384 void Assembler::bsrl(Register dst, Register src) {
1385 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1386 emit_int8(0x0F);
1387 emit_int8((unsigned char)0xBD);
1388 emit_int8((unsigned char)(0xC0 | encode));
1389 }
1390
1391 void Assembler::bswapl(Register reg) { // bswap
1392 int encode = prefix_and_encode(reg->encoding());
1393 emit_int8(0x0F);
1394 emit_int8((unsigned char)(0xC8 | encode));
1395 }
1396
1397 void Assembler::blsil(Register dst, Register src) {
1398 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1399 int encode = vex_prefix_0F38_and_encode_legacy(rbx, dst, src);
1400 emit_int8((unsigned char)0xF3);
1401 emit_int8((unsigned char)(0xC0 | encode));
1402 }
1403
1404 void Assembler::blsil(Register dst, Address src) {
1405 InstructionMark im(this);
1406 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1407 vex_prefix_0F38_legacy(rbx, dst, src);
1408 emit_int8((unsigned char)0xF3);
1409 emit_operand(rbx, src);
1410 }
1411
1412 void Assembler::blsmskl(Register dst, Register src) {
1413 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1414 int encode = vex_prefix_0F38_and_encode_legacy(rdx, dst, src);
1415 emit_int8((unsigned char)0xF3);
1416 emit_int8((unsigned char)(0xC0 | encode));
1417 }
1418
1419 void Assembler::blsmskl(Register dst, Address src) {
1420 InstructionMark im(this);
1421 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1422 vex_prefix_0F38_legacy(rdx, dst, src);
1423 emit_int8((unsigned char)0xF3);
1424 emit_operand(rdx, src);
1425 }
1426
1427 void Assembler::blsrl(Register dst, Register src) {
1428 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1429 int encode = vex_prefix_0F38_and_encode_legacy(rcx, dst, src);
1430 emit_int8((unsigned char)0xF3);
1431 emit_int8((unsigned char)(0xC0 | encode));
1432 }
1433
1434 void Assembler::blsrl(Register dst, Address src) {
1435 InstructionMark im(this);
1436 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1437 vex_prefix_0F38_legacy(rcx, dst, src);
1438 emit_int8((unsigned char)0xF3);
1439 emit_operand(rcx, src);
1440 }
1441
1442 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1443 // suspect disp32 is always good
1444 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1445
1446 if (L.is_bound()) {
1447 const int long_size = 5;
1448 int offs = (int)( target(L) - pc() );
1449 assert(offs <= 0, "assembler error");
1450 InstructionMark im(this);
1451 // 1110 1000 #32-bit disp
1452 emit_int8((unsigned char)0xE8);
1453 emit_data(offs - long_size, rtype, operand);
1454 } else {
1455 InstructionMark im(this);
1456 // 1110 1000 #32-bit disp
1457 L.add_patch_at(code(), locator());
1458
1459 emit_int8((unsigned char)0xE8);
1460 emit_data(int(0), rtype, operand);
1461 }
1462 }
1463
1464 void Assembler::call(Register dst) {
1465 int encode = prefix_and_encode(dst->encoding());
1466 emit_int8((unsigned char)0xFF);
1467 emit_int8((unsigned char)(0xD0 | encode));
1468 }
1469
1470
1471 void Assembler::call(Address adr) {
1472 InstructionMark im(this);
1473 prefix(adr);
1474 emit_int8((unsigned char)0xFF);
1475 emit_operand(rdx, adr);
1476 }
1477
1478 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1479 assert(entry != NULL, "call most probably wrong");
1480 InstructionMark im(this);
1481 emit_int8((unsigned char)0xE8);
1482 intptr_t disp = entry - (pc() + sizeof(int32_t));
1483 assert(is_simm32(disp), "must be 32bit offset (call2)");
1484 // Technically, should use call32_operand, but this format is
1485 // implied by the fact that we're emitting a call instruction.
1486
1487 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1488 emit_data((int) disp, rspec, operand);
1489 }
1490
1491 void Assembler::cdql() {
1492 emit_int8((unsigned char)0x99);
1493 }
1494
1495 void Assembler::cld() {
1496 emit_int8((unsigned char)0xFC);
1497 }
1498
1499 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1500 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1501 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1502 emit_int8(0x0F);
1503 emit_int8(0x40 | cc);
1504 emit_int8((unsigned char)(0xC0 | encode));
1505 }
1506
1507
1508 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1509 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1510 prefix(src, dst);
1511 emit_int8(0x0F);
1512 emit_int8(0x40 | cc);
1513 emit_operand(dst, src);
1514 }
1515
1516 void Assembler::cmpb(Address dst, int imm8) {
1517 InstructionMark im(this);
1518 prefix(dst);
1519 emit_int8((unsigned char)0x80);
1520 emit_operand(rdi, dst, 1);
1521 emit_int8(imm8);
1522 }
1523
1524 void Assembler::cmpl(Address dst, int32_t imm32) {
1525 InstructionMark im(this);
1526 prefix(dst);
1527 emit_int8((unsigned char)0x81);
1528 emit_operand(rdi, dst, 4);
1529 emit_int32(imm32);
1530 }
1531
1532 void Assembler::cmpl(Register dst, int32_t imm32) {
1533 prefix(dst);
1534 emit_arith(0x81, 0xF8, dst, imm32);
1535 }
1536
1537 void Assembler::cmpl(Register dst, Register src) {
1538 (void) prefix_and_encode(dst->encoding(), src->encoding());
1539 emit_arith(0x3B, 0xC0, dst, src);
1540 }
1541
1542 void Assembler::cmpl(Register dst, Address src) {
1543 InstructionMark im(this);
1544 prefix(src, dst);
1545 emit_int8((unsigned char)0x3B);
1546 emit_operand(dst, src);
1547 }
1548
1549 void Assembler::cmpw(Address dst, int imm16) {
1550 InstructionMark im(this);
1551 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1552 emit_int8(0x66);
1553 emit_int8((unsigned char)0x81);
1554 emit_operand(rdi, dst, 2);
1555 emit_int16(imm16);
1556 }
1557
1558 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1559 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1560 // The ZF is set if the compared values were equal, and cleared otherwise.
1561 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1562 InstructionMark im(this);
1563 prefix(adr, reg);
1564 emit_int8(0x0F);
1565 emit_int8((unsigned char)0xB1);
1566 emit_operand(reg, adr);
1567 }
1568
1569 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1570 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1571 // The ZF is set if the compared values were equal, and cleared otherwise.
1572 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1573 InstructionMark im(this);
1574 prefix(adr, reg, true);
1575 emit_int8(0x0F);
1576 emit_int8((unsigned char)0xB0);
1577 emit_operand(reg, adr);
1578 }
1579
1580 void Assembler::comisd(XMMRegister dst, Address src) {
1581 // NOTE: dbx seems to decode this as comiss even though the
1582 // 0x66 is there. Strangly ucomisd comes out correct
1583 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1584 if (VM_Version::supports_evex()) {
1585 _tuple_type = EVEX_T1S;
1586 _input_size_in_bits = EVEX_64bit;
1587 emit_simd_arith_nonds_q(0x2F, dst, src, VEX_SIMD_66, /* no_mask_reg */ true);
1588 } else {
1589 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1590 }
1591 }
1592
1593 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1594 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1595 if (VM_Version::supports_evex()) {
1596 emit_simd_arith_nonds_q(0x2F, dst, src, VEX_SIMD_66, /* no_mask_reg */ true);
1597 } else {
1598 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1599 }
1600 }
1601
1602 void Assembler::comiss(XMMRegister dst, Address src) {
1603 if (VM_Version::supports_evex()) {
1604 _tuple_type = EVEX_T1S;
1605 _input_size_in_bits = EVEX_32bit;
1606 }
1607 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1608 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE, /* no_mask_reg */ true);
1609 }
1610
1611 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1612 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1613 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE, /* no_mask_reg */ true);
1614 }
1615
1616 void Assembler::cpuid() {
1617 emit_int8(0x0F);
1618 emit_int8((unsigned char)0xA2);
1619 }
1620
1621 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1622 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1623 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1624 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1625 //
1626 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1627 //
1628 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1629 //
1630 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1631 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1632 assert(VM_Version::supports_sse4_2(), "");
1633 int8_t w = 0x01;
1634 Prefix p = Prefix_EMPTY;
1635
1636 emit_int8((int8_t)0xF2);
1637 switch (sizeInBytes) {
1638 case 1:
1639 w = 0;
1640 break;
1641 case 2:
1642 case 4:
1643 break;
1644 LP64_ONLY(case 8:)
1645 // This instruction is not valid in 32 bits
1646 // Note:
1647 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1648 //
1649 // Page B - 72 Vol. 2C says
1650 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1651 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1652 // F0!!!
1653 // while 3 - 208 Vol. 2A
1654 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1655 //
1656 // the 0 on a last bit is reserved for a different flavor of this instruction :
1657 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1658 p = REX_W;
1659 break;
1660 default:
1661 assert(0, "Unsupported value for a sizeInBytes argument");
1662 break;
1663 }
1664 LP64_ONLY(prefix(crc, v, p);)
1665 emit_int8((int8_t)0x0F);
1666 emit_int8(0x38);
1667 emit_int8((int8_t)(0xF0 | w));
1668 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1669 }
1670
1671 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1672 assert(VM_Version::supports_sse4_2(), "");
1673 InstructionMark im(this);
1674 int8_t w = 0x01;
1675 Prefix p = Prefix_EMPTY;
1676
1677 emit_int8((int8_t)0xF2);
1678 switch (sizeInBytes) {
1679 case 1:
1680 w = 0;
1681 break;
1682 case 2:
1683 case 4:
1684 break;
1685 LP64_ONLY(case 8:)
1686 // This instruction is not valid in 32 bits
1687 p = REX_W;
1688 break;
1689 default:
1690 assert(0, "Unsupported value for a sizeInBytes argument");
1691 break;
1692 }
1693 LP64_ONLY(prefix(crc, adr, p);)
1694 emit_int8((int8_t)0x0F);
1695 emit_int8(0x38);
1696 emit_int8((int8_t)(0xF0 | w));
1697 emit_operand(crc, adr);
1698 }
1699
1700 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1701 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1702 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3, /* no_mask_reg */ false, /* legacy_mode */ true);
1703 }
1704
1705 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1706 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1707 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE, /* no_mask_reg */ false, /* legacy_mode */ true);
1708 }
1709
1710 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1711 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1712 if (VM_Version::supports_evex()) {
1713 emit_simd_arith_q(0x5A, dst, src, VEX_SIMD_F2);
1714 } else {
1715 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1716 }
1717 }
1718
1719 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1720 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1721 if (VM_Version::supports_evex()) {
1722 _tuple_type = EVEX_T1F;
1723 _input_size_in_bits = EVEX_64bit;
1724 emit_simd_arith_q(0x5A, dst, src, VEX_SIMD_F2);
1725 } else {
1726 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1727 }
1728 }
1729
1730 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1731 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1732 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VM_Version::supports_evex());
1733 emit_int8(0x2A);
1734 emit_int8((unsigned char)(0xC0 | encode));
1735 }
1736
1737 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1738 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1739 if (VM_Version::supports_evex()) {
1740 _tuple_type = EVEX_T1S;
1741 _input_size_in_bits = EVEX_32bit;
1742 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2, /* no_mask_reg */ true);
1743 } else {
1744 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2);
1745 }
1746 }
1747
1748 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1749 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1750 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, /* no_mask_reg */ true);
1751 emit_int8(0x2A);
1752 emit_int8((unsigned char)(0xC0 | encode));
1753 }
1754
1755 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1756 if (VM_Version::supports_evex()) {
1757 _tuple_type = EVEX_T1S;
1758 _input_size_in_bits = EVEX_32bit;
1759 }
1760 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1761 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3, /* no_mask_reg */ true);
1762 }
1763
1764 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1765 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1766 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3, /* no_mask_reg */ true);
1767 emit_int8(0x2A);
1768 emit_int8((unsigned char)(0xC0 | encode));
1769 }
1770
1771 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1772 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1773 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1774 }
1775
1776 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1777 if (VM_Version::supports_evex()) {
1778 _tuple_type = EVEX_T1S;
1779 _input_size_in_bits = EVEX_32bit;
1780 }
1781 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1782 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1783 }
1784
1785
1786 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1787 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1788 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, /* no_mask_reg */ true);
1789 emit_int8(0x2C);
1790 emit_int8((unsigned char)(0xC0 | encode));
1791 }
1792
1793 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1794 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1795 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, /* no_mask_reg */ true);
1796 emit_int8(0x2C);
1797 emit_int8((unsigned char)(0xC0 | encode));
1798 }
1799
1800 void Assembler::decl(Address dst) {
1801 // Don't use it directly. Use MacroAssembler::decrement() instead.
1802 InstructionMark im(this);
1803 prefix(dst);
1804 emit_int8((unsigned char)0xFF);
1805 emit_operand(rcx, dst);
1806 }
1807
1808 void Assembler::divsd(XMMRegister dst, Address src) {
1809 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1810 if (VM_Version::supports_evex()) {
1811 _tuple_type = EVEX_T1S;
1812 _input_size_in_bits = EVEX_64bit;
1813 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_F2);
1814 } else {
1815 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1816 }
1817 }
1818
1819 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1820 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1821 if (VM_Version::supports_evex()) {
1822 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_F2);
1823 } else {
1824 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1825 }
1826 }
1827
1828 void Assembler::divss(XMMRegister dst, Address src) {
1829 if (VM_Version::supports_evex()) {
1830 _tuple_type = EVEX_T1S;
1831 _input_size_in_bits = EVEX_32bit;
1832 }
1833 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1834 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1835 }
1836
1837 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1838 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1839 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1840 }
1841
1842 void Assembler::emms() {
1843 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1844 emit_int8(0x0F);
1845 emit_int8(0x77);
1846 }
1847
1848 void Assembler::hlt() {
1849 emit_int8((unsigned char)0xF4);
1850 }
1851
1852 void Assembler::idivl(Register src) {
1853 int encode = prefix_and_encode(src->encoding());
1854 emit_int8((unsigned char)0xF7);
1855 emit_int8((unsigned char)(0xF8 | encode));
1856 }
1857
1858 void Assembler::divl(Register src) { // Unsigned
1859 int encode = prefix_and_encode(src->encoding());
1860 emit_int8((unsigned char)0xF7);
1861 emit_int8((unsigned char)(0xF0 | encode));
1862 }
1863
1864 void Assembler::imull(Register dst, Register src) {
1865 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1866 emit_int8(0x0F);
1867 emit_int8((unsigned char)0xAF);
1868 emit_int8((unsigned char)(0xC0 | encode));
1869 }
1870
1871
1872 void Assembler::imull(Register dst, Register src, int value) {
1873 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1874 if (is8bit(value)) {
1875 emit_int8(0x6B);
1876 emit_int8((unsigned char)(0xC0 | encode));
1877 emit_int8(value & 0xFF);
1878 } else {
1879 emit_int8(0x69);
1880 emit_int8((unsigned char)(0xC0 | encode));
1881 emit_int32(value);
1882 }
1883 }
1884
1885 void Assembler::imull(Register dst, Address src) {
1886 InstructionMark im(this);
1887 prefix(src, dst);
1888 emit_int8(0x0F);
1889 emit_int8((unsigned char) 0xAF);
1890 emit_operand(dst, src);
1891 }
1892
1893
1894 void Assembler::incl(Address dst) {
1895 // Don't use it directly. Use MacroAssembler::increment() instead.
1896 InstructionMark im(this);
1897 prefix(dst);
1898 emit_int8((unsigned char)0xFF);
1899 emit_operand(rax, dst);
1900 }
1901
1902 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1903 InstructionMark im(this);
1904 assert((0 <= cc) && (cc < 16), "illegal cc");
1905 if (L.is_bound()) {
1906 address dst = target(L);
1907 assert(dst != NULL, "jcc most probably wrong");
1908
1909 const int short_size = 2;
1910 const int long_size = 6;
1911 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1912 if (maybe_short && is8bit(offs - short_size)) {
1913 // 0111 tttn #8-bit disp
1914 emit_int8(0x70 | cc);
1915 emit_int8((offs - short_size) & 0xFF);
1916 } else {
1917 // 0000 1111 1000 tttn #32-bit disp
1918 assert(is_simm32(offs - long_size),
1919 "must be 32bit offset (call4)");
1920 emit_int8(0x0F);
1921 emit_int8((unsigned char)(0x80 | cc));
1922 emit_int32(offs - long_size);
1923 }
1924 } else {
1925 // Note: could eliminate cond. jumps to this jump if condition
1926 // is the same however, seems to be rather unlikely case.
1927 // Note: use jccb() if label to be bound is very close to get
1928 // an 8-bit displacement
1929 L.add_patch_at(code(), locator());
1930 emit_int8(0x0F);
1931 emit_int8((unsigned char)(0x80 | cc));
1932 emit_int32(0);
1933 }
1934 }
1935
1936 void Assembler::jccb(Condition cc, Label& L) {
1937 if (L.is_bound()) {
1938 const int short_size = 2;
1939 address entry = target(L);
1940 #ifdef ASSERT
1941 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1942 intptr_t delta = short_branch_delta();
1943 if (delta != 0) {
1944 dist += (dist < 0 ? (-delta) :delta);
1945 }
1946 assert(is8bit(dist), "Dispacement too large for a short jmp");
1947 #endif
1948 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1949 // 0111 tttn #8-bit disp
1950 emit_int8(0x70 | cc);
1951 emit_int8((offs - short_size) & 0xFF);
1952 } else {
1953 InstructionMark im(this);
1954 L.add_patch_at(code(), locator());
1955 emit_int8(0x70 | cc);
1956 emit_int8(0);
1957 }
1958 }
1959
1960 void Assembler::jmp(Address adr) {
1961 InstructionMark im(this);
1962 prefix(adr);
1963 emit_int8((unsigned char)0xFF);
1964 emit_operand(rsp, adr);
1965 }
1966
1967 void Assembler::jmp(Label& L, bool maybe_short) {
1968 if (L.is_bound()) {
1969 address entry = target(L);
1970 assert(entry != NULL, "jmp most probably wrong");
1971 InstructionMark im(this);
1972 const int short_size = 2;
1973 const int long_size = 5;
1974 intptr_t offs = entry - pc();
1975 if (maybe_short && is8bit(offs - short_size)) {
1976 emit_int8((unsigned char)0xEB);
1977 emit_int8((offs - short_size) & 0xFF);
1978 } else {
1979 emit_int8((unsigned char)0xE9);
1980 emit_int32(offs - long_size);
1981 }
1982 } else {
1983 // By default, forward jumps are always 32-bit displacements, since
1984 // we can't yet know where the label will be bound. If you're sure that
1985 // the forward jump will not run beyond 256 bytes, use jmpb to
1986 // force an 8-bit displacement.
1987 InstructionMark im(this);
1988 L.add_patch_at(code(), locator());
1989 emit_int8((unsigned char)0xE9);
1990 emit_int32(0);
1991 }
1992 }
1993
1994 void Assembler::jmp(Register entry) {
1995 int encode = prefix_and_encode(entry->encoding());
1996 emit_int8((unsigned char)0xFF);
1997 emit_int8((unsigned char)(0xE0 | encode));
1998 }
1999
2000 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2001 InstructionMark im(this);
2002 emit_int8((unsigned char)0xE9);
2003 assert(dest != NULL, "must have a target");
2004 intptr_t disp = dest - (pc() + sizeof(int32_t));
2005 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2006 emit_data(disp, rspec.reloc(), call32_operand);
2007 }
2008
2009 void Assembler::jmpb(Label& L) {
2010 if (L.is_bound()) {
2011 const int short_size = 2;
2012 address entry = target(L);
2013 assert(entry != NULL, "jmp most probably wrong");
2014 #ifdef ASSERT
2015 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2016 intptr_t delta = short_branch_delta();
2017 if (delta != 0) {
2018 dist += (dist < 0 ? (-delta) :delta);
2019 }
2020 assert(is8bit(dist), "Dispacement too large for a short jmp");
2021 #endif
2022 intptr_t offs = entry - pc();
2023 emit_int8((unsigned char)0xEB);
2024 emit_int8((offs - short_size) & 0xFF);
2025 } else {
2026 InstructionMark im(this);
2027 L.add_patch_at(code(), locator());
2028 emit_int8((unsigned char)0xEB);
2029 emit_int8(0);
2030 }
2031 }
2032
2033 void Assembler::ldmxcsr( Address src) {
2034 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2035 InstructionMark im(this);
2036 prefix(src);
2037 emit_int8(0x0F);
2038 emit_int8((unsigned char)0xAE);
2039 emit_operand(as_Register(2), src);
2040 }
2041
2042 void Assembler::leal(Register dst, Address src) {
2043 InstructionMark im(this);
2044 #ifdef _LP64
2045 emit_int8(0x67); // addr32
2046 prefix(src, dst);
2047 #endif // LP64
2048 emit_int8((unsigned char)0x8D);
2049 emit_operand(dst, src);
2050 }
2051
2052 void Assembler::lfence() {
2053 emit_int8(0x0F);
2054 emit_int8((unsigned char)0xAE);
2055 emit_int8((unsigned char)0xE8);
2056 }
2057
2058 void Assembler::lock() {
2059 emit_int8((unsigned char)0xF0);
2060 }
2061
2062 void Assembler::lzcntl(Register dst, Register src) {
2063 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2064 emit_int8((unsigned char)0xF3);
2065 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2066 emit_int8(0x0F);
2067 emit_int8((unsigned char)0xBD);
2068 emit_int8((unsigned char)(0xC0 | encode));
2069 }
2070
2071 // Emit mfence instruction
2072 void Assembler::mfence() {
2073 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2074 emit_int8(0x0F);
2075 emit_int8((unsigned char)0xAE);
2076 emit_int8((unsigned char)0xF0);
2077 }
2078
2079 void Assembler::mov(Register dst, Register src) {
2080 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2081 }
2082
2083 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2084 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2085 if (VM_Version::supports_avx512novl()) {
2086 int vector_len = AVX_512bit;
2087 int dst_enc = dst->encoding();
2088 int src_enc = src->encoding();
2089 int encode = vex_prefix_and_encode(dst_enc, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F,
2090 /* vex_w */ true, vector_len, /* legacy_mode */ false, /* no_mask_reg */ false);
2091 emit_int8(0x28);
2092 emit_int8((unsigned char)(0xC0 | encode));
2093 } else if (VM_Version::supports_evex()) {
2094 emit_simd_arith_nonds_q(0x28, dst, src, VEX_SIMD_66);
2095 } else {
2096 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66);
2097 }
2098 }
2099
2100 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2101 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2102 if (VM_Version::supports_avx512novl()) {
2103 int vector_len = AVX_512bit;
2104 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, vector_len);
2105 emit_int8(0x28);
2106 emit_int8((unsigned char)(0xC0 | encode));
2107 } else {
2108 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE);
2109 }
2110 }
2111
2112 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2113 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2114 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, /* no_mask_reg */ true);
2115 emit_int8(0x16);
2116 emit_int8((unsigned char)(0xC0 | encode));
2117 }
2118
2119 void Assembler::movb(Register dst, Address src) {
2120 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2121 InstructionMark im(this);
2122 prefix(src, dst, true);
2123 emit_int8((unsigned char)0x8A);
2124 emit_operand(dst, src);
2125 }
2126
2127 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2128 _instruction_uses_vl = true;
2129 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2130 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, /* no_mask_reg */ false, VEX_OPCODE_0F,
2131 /* rex_w */ VM_Version::supports_evex(), AVX_128bit, /* legacy_mode */ false);
2132 emit_int8(0x12);
2133 emit_int8(0xC0 | encode);
2134
2135 }
2136
2137 void Assembler::kmovql(KRegister dst, KRegister src) {
2138 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2139 int encode = kreg_prefix_and_encode(dst, knoreg, src, VEX_SIMD_NONE,
2140 /* no_mask_reg */ true, VEX_OPCODE_0F, /* rex_w */ true);
2141 emit_int8((unsigned char)0x90);
2142 emit_int8((unsigned char)(0xC0 | encode));
2143 }
2144
2145 void Assembler::kmovql(KRegister dst, Address src) {
2146 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2147 int dst_enc = dst->encoding();
2148 int nds_enc = 0;
2149 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_NONE,
2150 VEX_OPCODE_0F, /* vex_w */ true, AVX_128bit, /* legacy_mode */ true, /* no_reg_mask */ true);
2151 emit_int8((unsigned char)0x90);
2152 emit_operand((Register)dst, src);
2153 }
2154
2155 void Assembler::kmovql(Address dst, KRegister src) {
2156 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2157 int src_enc = src->encoding();
2158 int nds_enc = 0;
2159 vex_prefix(dst, nds_enc, src_enc, VEX_SIMD_NONE,
2160 VEX_OPCODE_0F, /* vex_w */ true, AVX_128bit, /* legacy_mode */ true, /* no_reg_mask */ true);
2161 emit_int8((unsigned char)0x90);
2162 emit_operand((Register)src, dst);
2163 }
2164
2165 void Assembler::kmovql(KRegister dst, Register src) {
2166 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2167 VexSimdPrefix pre = !_legacy_mode_bw ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2168 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, /* no_mask_reg */ true,
2169 VEX_OPCODE_0F, /* legacy_mode */ !_legacy_mode_bw);
2170 emit_int8((unsigned char)0x92);
2171 emit_int8((unsigned char)(0xC0 | encode));
2172 }
2173
2174 void Assembler::kmovdl(KRegister dst, Register src) {
2175 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2176 VexSimdPrefix pre = !_legacy_mode_bw ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2177 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, /* no_mask_reg */ true);
2178 emit_int8((unsigned char)0x92);
2179 emit_int8((unsigned char)(0xC0 | encode));
2180 }
2181
2182 void Assembler::kmovwl(KRegister dst, Register src) {
2183 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2184 int encode = kreg_prefix_and_encode(dst, knoreg, src, VEX_SIMD_NONE, /* no_mask_reg */ true);
2185 emit_int8((unsigned char)0x92);
2186 emit_int8((unsigned char)(0xC0 | encode));
2187 }
2188
2189 void Assembler::movb(Address dst, int imm8) {
2190 InstructionMark im(this);
2191 prefix(dst);
2192 emit_int8((unsigned char)0xC6);
2193 emit_operand(rax, dst, 1);
2194 emit_int8(imm8);
2195 }
2196
2197
2198 void Assembler::movb(Address dst, Register src) {
2199 assert(src->has_byte_register(), "must have byte register");
2200 InstructionMark im(this);
2201 prefix(dst, src, true);
2202 emit_int8((unsigned char)0x88);
2203 emit_operand(src, dst);
2204 }
2205
2206 void Assembler::movdl(XMMRegister dst, Register src) {
2207 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2208 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, /* no_mask_reg */ true);
2209 emit_int8(0x6E);
2210 emit_int8((unsigned char)(0xC0 | encode));
2211 }
2212
2213 void Assembler::movdl(Register dst, XMMRegister src) {
2214 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2215 // swap src/dst to get correct prefix
2216 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66, /* no_mask_reg */ true);
2217 emit_int8(0x7E);
2218 emit_int8((unsigned char)(0xC0 | encode));
2219 }
2220
2221 void Assembler::movdl(XMMRegister dst, Address src) {
2222 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2223 if (VM_Version::supports_evex()) {
2224 _tuple_type = EVEX_T1S;
2225 _input_size_in_bits = EVEX_32bit;
2226 }
2227 InstructionMark im(this);
2228 simd_prefix(dst, src, VEX_SIMD_66, /* no_reg_mask */ true);
2229 emit_int8(0x6E);
2230 emit_operand(dst, src);
2231 }
2232
2233 void Assembler::movdl(Address dst, XMMRegister src) {
2234 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2235 if (VM_Version::supports_evex()) {
2236 _tuple_type = EVEX_T1S;
2237 _input_size_in_bits = EVEX_32bit;
2238 }
2239 InstructionMark im(this);
2240 simd_prefix(dst, src, VEX_SIMD_66, /* no_reg_mask */ true);
2241 emit_int8(0x7E);
2242 emit_operand(src, dst);
2243 }
2244
2245 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2246 _instruction_uses_vl = true;
2247 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2248 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
2249 }
2250
2251 void Assembler::movdqa(XMMRegister dst, Address src) {
2252 _instruction_uses_vl = true;
2253 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2254 if (VM_Version::supports_evex()) {
2255 _tuple_type = EVEX_FVM;
2256 }
2257 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
2258 }
2259
2260 void Assembler::movdqu(XMMRegister dst, Address src) {
2261 _instruction_uses_vl = true;
2262 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2263 if (VM_Version::supports_evex()) {
2264 _tuple_type = EVEX_FVM;
2265 }
2266 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
2267 }
2268
2269 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2270 _instruction_uses_vl = true;
2271 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2272 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
2273 }
2274
2275 void Assembler::movdqu(Address dst, XMMRegister src) {
2276 _instruction_uses_vl = true;
2277 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2278 if (VM_Version::supports_evex()) {
2279 _tuple_type = EVEX_FVM;
2280 }
2281 InstructionMark im(this);
2282 simd_prefix(dst, src, VEX_SIMD_F3, /* no_mask_reg */ false);
2283 emit_int8(0x7F);
2284 emit_operand(src, dst);
2285 }
2286
2287 // Move Unaligned 256bit Vector
2288 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2289 _instruction_uses_vl = true;
2290 assert(UseAVX > 0, "");
2291 int vector_len = AVX_256bit;
2292 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector_len);
2293 emit_int8(0x6F);
2294 emit_int8((unsigned char)(0xC0 | encode));
2295 }
2296
2297 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2298 _instruction_uses_vl = true;
2299 assert(UseAVX > 0, "");
2300 if (VM_Version::supports_evex()) {
2301 _tuple_type = EVEX_FVM;
2302 }
2303 InstructionMark im(this);
2304 int vector_len = AVX_256bit;
2305 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector_len);
2306 emit_int8(0x6F);
2307 emit_operand(dst, src);
2308 }
2309
2310 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2311 _instruction_uses_vl = true;
2312 assert(UseAVX > 0, "");
2313 if (VM_Version::supports_evex()) {
2314 _tuple_type = EVEX_FVM;
2315 }
2316 InstructionMark im(this);
2317 int vector_len = AVX_256bit;
2318 // swap src<->dst for encoding
2319 assert(src != xnoreg, "sanity");
2320 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector_len);
2321 emit_int8(0x7F);
2322 emit_operand(src, dst);
2323 }
2324
2325 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2326 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2327 _instruction_uses_vl = true;
2328 assert(UseAVX > 0, "");
2329 int src_enc = src->encoding();
2330 int dst_enc = dst->encoding();
2331 int encode = vex_prefix_and_encode(dst_enc, 0, src_enc, VEX_SIMD_F3, VEX_OPCODE_0F,
2332 /* vex_w */ false, vector_len, /* legacy_mode */ false, /* no_mask_reg */ false);
2333 emit_int8(0x6F);
2334 emit_int8((unsigned char)(0xC0 | encode));
2335 }
2336
2337 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2338 _instruction_uses_vl = true;
2339 assert(UseAVX > 0, "");
2340 InstructionMark im(this);
2341 if (VM_Version::supports_evex()) {
2342 _tuple_type = EVEX_FVM;
2343 }
2344 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector_len);
2345 emit_int8(0x6F);
2346 emit_operand(dst, src);
2347 }
2348
2349 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2350 _instruction_uses_vl = true;
2351 assert(UseAVX > 0, "");
2352 InstructionMark im(this);
2353 assert(src != xnoreg, "sanity");
2354 if (VM_Version::supports_evex()) {
2355 _tuple_type = EVEX_FVM;
2356 }
2357 // swap src<->dst for encoding
2358 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector_len);
2359 emit_int8(0x7F);
2360 emit_operand(src, dst);
2361 }
2362
2363 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2364 _instruction_uses_vl = true;
2365 assert(UseAVX > 0, "");
2366 int src_enc = src->encoding();
2367 int dst_enc = dst->encoding();
2368 int encode = vex_prefix_and_encode(dst_enc, 0, src_enc, VEX_SIMD_F3, VEX_OPCODE_0F,
2369 /* vex_w */ true, vector_len, /* legacy_mode */ false, /* no_mask_reg */ false);
2370 emit_int8(0x6F);
2371 emit_int8((unsigned char)(0xC0 | encode));
2372 }
2373
2374 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2375 _instruction_uses_vl = true;
2376 assert(UseAVX > 2, "");
2377 InstructionMark im(this);
2378 _tuple_type = EVEX_FVM;
2379 vex_prefix_q(dst, xnoreg, src, VEX_SIMD_F3, vector_len);
2380 emit_int8(0x6F);
2381 emit_operand(dst, src);
2382 }
2383
2384 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2385 _instruction_uses_vl = true;
2386 assert(UseAVX > 2, "");
2387 InstructionMark im(this);
2388 assert(src != xnoreg, "sanity");
2389 _tuple_type = EVEX_FVM;
2390 // swap src<->dst for encoding
2391 vex_prefix_q(src, xnoreg, dst, VEX_SIMD_F3, vector_len);
2392 emit_int8(0x7F);
2393 emit_operand(src, dst);
2394 }
2395
2396 // Uses zero extension on 64bit
2397
2398 void Assembler::movl(Register dst, int32_t imm32) {
2399 int encode = prefix_and_encode(dst->encoding());
2400 emit_int8((unsigned char)(0xB8 | encode));
2401 emit_int32(imm32);
2402 }
2403
2404 void Assembler::movl(Register dst, Register src) {
2405 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2406 emit_int8((unsigned char)0x8B);
2407 emit_int8((unsigned char)(0xC0 | encode));
2408 }
2409
2410 void Assembler::movl(Register dst, Address src) {
2411 InstructionMark im(this);
2412 prefix(src, dst);
2413 emit_int8((unsigned char)0x8B);
2414 emit_operand(dst, src);
2415 }
2416
2417 void Assembler::movl(Address dst, int32_t imm32) {
2418 InstructionMark im(this);
2419 prefix(dst);
2420 emit_int8((unsigned char)0xC7);
2421 emit_operand(rax, dst, 4);
2422 emit_int32(imm32);
2423 }
2424
2425 void Assembler::movl(Address dst, Register src) {
2426 InstructionMark im(this);
2427 prefix(dst, src);
2428 emit_int8((unsigned char)0x89);
2429 emit_operand(src, dst);
2430 }
2431
2432 // New cpus require to use movsd and movss to avoid partial register stall
2433 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2434 // The selection is done in MacroAssembler::movdbl() and movflt().
2435 void Assembler::movlpd(XMMRegister dst, Address src) {
2436 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2437 if (VM_Version::supports_evex()) {
2438 _tuple_type = EVEX_T1S;
2439 _input_size_in_bits = EVEX_32bit;
2440 emit_simd_arith_q(0x12, dst, src, VEX_SIMD_66, /* no_mask_reg */ true);
2441 } else {
2442 emit_simd_arith(0x12, dst, src, VEX_SIMD_66, /* no_mask_reg */ true);
2443 }
2444 }
2445
2446 void Assembler::movq( MMXRegister dst, Address src ) {
2447 assert( VM_Version::supports_mmx(), "" );
2448 emit_int8(0x0F);
2449 emit_int8(0x6F);
2450 emit_operand(dst, src);
2451 }
2452
2453 void Assembler::movq( Address dst, MMXRegister src ) {
2454 assert( VM_Version::supports_mmx(), "" );
2455 emit_int8(0x0F);
2456 emit_int8(0x7F);
2457 // workaround gcc (3.2.1-7a) bug
2458 // In that version of gcc with only an emit_operand(MMX, Address)
2459 // gcc will tail jump and try and reverse the parameters completely
2460 // obliterating dst in the process. By having a version available
2461 // that doesn't need to swap the args at the tail jump the bug is
2462 // avoided.
2463 emit_operand(dst, src);
2464 }
2465
2466 void Assembler::movq(XMMRegister dst, Address src) {
2467 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2468 InstructionMark im(this);
2469 if (VM_Version::supports_evex()) {
2470 _tuple_type = EVEX_T1S;
2471 _input_size_in_bits = EVEX_64bit;
2472 simd_prefix_q(dst, xnoreg, src, VEX_SIMD_F3, /* no_mask_reg */ true);
2473 } else {
2474 simd_prefix(dst, src, VEX_SIMD_F3, /* no_mask_reg */ true);
2475 }
2476 emit_int8(0x7E);
2477 emit_operand(dst, src);
2478 }
2479
2480 void Assembler::movq(Address dst, XMMRegister src) {
2481 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2482 InstructionMark im(this);
2483 if (VM_Version::supports_evex()) {
2484 _tuple_type = EVEX_T1S;
2485 _input_size_in_bits = EVEX_64bit;
2486 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, /* no_mask_reg */ true,
2487 VEX_OPCODE_0F, /* rex_w */ true);
2488 } else {
2489 simd_prefix(dst, src, VEX_SIMD_66, /* no_mask_reg */ true);
2490 }
2491 emit_int8((unsigned char)0xD6);
2492 emit_operand(src, dst);
2493 }
2494
2495 void Assembler::movsbl(Register dst, Address src) { // movsxb
2496 InstructionMark im(this);
2497 prefix(src, dst);
2498 emit_int8(0x0F);
2499 emit_int8((unsigned char)0xBE);
2500 emit_operand(dst, src);
2501 }
2502
2503 void Assembler::movsbl(Register dst, Register src) { // movsxb
2504 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2505 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2506 emit_int8(0x0F);
2507 emit_int8((unsigned char)0xBE);
2508 emit_int8((unsigned char)(0xC0 | encode));
2509 }
2510
2511 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2512 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2513 if (VM_Version::supports_evex()) {
2514 emit_simd_arith_q(0x10, dst, src, VEX_SIMD_F2, /* no_mask_reg */ true);
2515 } else {
2516 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2);
2517 }
2518 }
2519
2520 void Assembler::movsd(XMMRegister dst, Address src) {
2521 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2522 if (VM_Version::supports_evex()) {
2523 _tuple_type = EVEX_T1S;
2524 _input_size_in_bits = EVEX_64bit;
2525 emit_simd_arith_nonds_q(0x10, dst, src, VEX_SIMD_F2, /* no_mask_reg */ true);
2526 } else {
2527 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2);
2528 }
2529 }
2530
2531 void Assembler::movsd(Address dst, XMMRegister src) {
2532 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2533 InstructionMark im(this);
2534 if (VM_Version::supports_evex()) {
2535 _tuple_type = EVEX_T1S;
2536 _input_size_in_bits = EVEX_64bit;
2537 simd_prefix_q(src, xnoreg, dst, VEX_SIMD_F2);
2538 } else {
2539 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, /* no_mask_reg */ false);
2540 }
2541 emit_int8(0x11);
2542 emit_operand(src, dst);
2543 }
2544
2545 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2546 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2547 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3, /* no_mask_reg */ true);
2548 }
2549
2550 void Assembler::movss(XMMRegister dst, Address src) {
2551 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2552 if (VM_Version::supports_evex()) {
2553 _tuple_type = EVEX_T1S;
2554 _input_size_in_bits = EVEX_32bit;
2555 }
2556 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3, /* no_mask_reg */ true);
2557 }
2558
2559 void Assembler::movss(Address dst, XMMRegister src) {
2560 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2561 if (VM_Version::supports_evex()) {
2562 _tuple_type = EVEX_T1S;
2563 _input_size_in_bits = EVEX_32bit;
2564 }
2565 InstructionMark im(this);
2566 simd_prefix(dst, src, VEX_SIMD_F3, /* no_mask_reg */ false);
2567 emit_int8(0x11);
2568 emit_operand(src, dst);
2569 }
2570
2571 void Assembler::movswl(Register dst, Address src) { // movsxw
2572 InstructionMark im(this);
2573 prefix(src, dst);
2574 emit_int8(0x0F);
2575 emit_int8((unsigned char)0xBF);
2576 emit_operand(dst, src);
2577 }
2578
2579 void Assembler::movswl(Register dst, Register src) { // movsxw
2580 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2581 emit_int8(0x0F);
2582 emit_int8((unsigned char)0xBF);
2583 emit_int8((unsigned char)(0xC0 | encode));
2584 }
2585
2586 void Assembler::movw(Address dst, int imm16) {
2587 InstructionMark im(this);
2588
2589 emit_int8(0x66); // switch to 16-bit mode
2590 prefix(dst);
2591 emit_int8((unsigned char)0xC7);
2592 emit_operand(rax, dst, 2);
2593 emit_int16(imm16);
2594 }
2595
2596 void Assembler::movw(Register dst, Address src) {
2597 InstructionMark im(this);
2598 emit_int8(0x66);
2599 prefix(src, dst);
2600 emit_int8((unsigned char)0x8B);
2601 emit_operand(dst, src);
2602 }
2603
2604 void Assembler::movw(Address dst, Register src) {
2605 InstructionMark im(this);
2606 emit_int8(0x66);
2607 prefix(dst, src);
2608 emit_int8((unsigned char)0x89);
2609 emit_operand(src, dst);
2610 }
2611
2612 void Assembler::movzbl(Register dst, Address src) { // movzxb
2613 InstructionMark im(this);
2614 prefix(src, dst);
2615 emit_int8(0x0F);
2616 emit_int8((unsigned char)0xB6);
2617 emit_operand(dst, src);
2618 }
2619
2620 void Assembler::movzbl(Register dst, Register src) { // movzxb
2621 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2622 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2623 emit_int8(0x0F);
2624 emit_int8((unsigned char)0xB6);
2625 emit_int8(0xC0 | encode);
2626 }
2627
2628 void Assembler::movzwl(Register dst, Address src) { // movzxw
2629 InstructionMark im(this);
2630 prefix(src, dst);
2631 emit_int8(0x0F);
2632 emit_int8((unsigned char)0xB7);
2633 emit_operand(dst, src);
2634 }
2635
2636 void Assembler::movzwl(Register dst, Register src) { // movzxw
2637 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2638 emit_int8(0x0F);
2639 emit_int8((unsigned char)0xB7);
2640 emit_int8(0xC0 | encode);
2641 }
2642
2643 void Assembler::mull(Address src) {
2644 InstructionMark im(this);
2645 prefix(src);
2646 emit_int8((unsigned char)0xF7);
2647 emit_operand(rsp, src);
2648 }
2649
2650 void Assembler::mull(Register src) {
2651 int encode = prefix_and_encode(src->encoding());
2652 emit_int8((unsigned char)0xF7);
2653 emit_int8((unsigned char)(0xE0 | encode));
2654 }
2655
2656 void Assembler::mulsd(XMMRegister dst, Address src) {
2657 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2658 if (VM_Version::supports_evex()) {
2659 _tuple_type = EVEX_T1S;
2660 _input_size_in_bits = EVEX_64bit;
2661 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_F2);
2662 } else {
2663 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2664 }
2665 }
2666
2667 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2668 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2669 if (VM_Version::supports_evex()) {
2670 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_F2);
2671 } else {
2672 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2673 }
2674 }
2675
2676 void Assembler::mulss(XMMRegister dst, Address src) {
2677 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2678 if (VM_Version::supports_evex()) {
2679 _tuple_type = EVEX_T1S;
2680 _input_size_in_bits = EVEX_32bit;
2681 }
2682 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2683 }
2684
2685 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2686 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2687 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2688 }
2689
2690 void Assembler::negl(Register dst) {
2691 int encode = prefix_and_encode(dst->encoding());
2692 emit_int8((unsigned char)0xF7);
2693 emit_int8((unsigned char)(0xD8 | encode));
2694 }
2695
2696 void Assembler::nop(int i) {
2697 #ifdef ASSERT
2698 assert(i > 0, " ");
2699 // The fancy nops aren't currently recognized by debuggers making it a
2700 // pain to disassemble code while debugging. If asserts are on clearly
2701 // speed is not an issue so simply use the single byte traditional nop
2702 // to do alignment.
2703
2704 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2705 return;
2706
2707 #endif // ASSERT
2708
2709 if (UseAddressNop && VM_Version::is_intel()) {
2710 //
2711 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2712 // 1: 0x90
2713 // 2: 0x66 0x90
2714 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2715 // 4: 0x0F 0x1F 0x40 0x00
2716 // 5: 0x0F 0x1F 0x44 0x00 0x00
2717 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2718 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2719 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2720 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2721 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2722 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2723
2724 // The rest coding is Intel specific - don't use consecutive address nops
2725
2726 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2727 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2728 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2729 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2730
2731 while(i >= 15) {
2732 // For Intel don't generate consecutive addess nops (mix with regular nops)
2733 i -= 15;
2734 emit_int8(0x66); // size prefix
2735 emit_int8(0x66); // size prefix
2736 emit_int8(0x66); // size prefix
2737 addr_nop_8();
2738 emit_int8(0x66); // size prefix
2739 emit_int8(0x66); // size prefix
2740 emit_int8(0x66); // size prefix
2741 emit_int8((unsigned char)0x90);
2742 // nop
2743 }
2744 switch (i) {
2745 case 14:
2746 emit_int8(0x66); // size prefix
2747 case 13:
2748 emit_int8(0x66); // size prefix
2749 case 12:
2750 addr_nop_8();
2751 emit_int8(0x66); // size prefix
2752 emit_int8(0x66); // size prefix
2753 emit_int8(0x66); // size prefix
2754 emit_int8((unsigned char)0x90);
2755 // nop
2756 break;
2757 case 11:
2758 emit_int8(0x66); // size prefix
2759 case 10:
2760 emit_int8(0x66); // size prefix
2761 case 9:
2762 emit_int8(0x66); // size prefix
2763 case 8:
2764 addr_nop_8();
2765 break;
2766 case 7:
2767 addr_nop_7();
2768 break;
2769 case 6:
2770 emit_int8(0x66); // size prefix
2771 case 5:
2772 addr_nop_5();
2773 break;
2774 case 4:
2775 addr_nop_4();
2776 break;
2777 case 3:
2778 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2779 emit_int8(0x66); // size prefix
2780 case 2:
2781 emit_int8(0x66); // size prefix
2782 case 1:
2783 emit_int8((unsigned char)0x90);
2784 // nop
2785 break;
2786 default:
2787 assert(i == 0, " ");
2788 }
2789 return;
2790 }
2791 if (UseAddressNop && VM_Version::is_amd()) {
2792 //
2793 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2794 // 1: 0x90
2795 // 2: 0x66 0x90
2796 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2797 // 4: 0x0F 0x1F 0x40 0x00
2798 // 5: 0x0F 0x1F 0x44 0x00 0x00
2799 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2800 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2801 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2802 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2803 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2804 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2805
2806 // The rest coding is AMD specific - use consecutive address nops
2807
2808 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2809 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2810 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2811 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2812 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2813 // Size prefixes (0x66) are added for larger sizes
2814
2815 while(i >= 22) {
2816 i -= 11;
2817 emit_int8(0x66); // size prefix
2818 emit_int8(0x66); // size prefix
2819 emit_int8(0x66); // size prefix
2820 addr_nop_8();
2821 }
2822 // Generate first nop for size between 21-12
2823 switch (i) {
2824 case 21:
2825 i -= 1;
2826 emit_int8(0x66); // size prefix
2827 case 20:
2828 case 19:
2829 i -= 1;
2830 emit_int8(0x66); // size prefix
2831 case 18:
2832 case 17:
2833 i -= 1;
2834 emit_int8(0x66); // size prefix
2835 case 16:
2836 case 15:
2837 i -= 8;
2838 addr_nop_8();
2839 break;
2840 case 14:
2841 case 13:
2842 i -= 7;
2843 addr_nop_7();
2844 break;
2845 case 12:
2846 i -= 6;
2847 emit_int8(0x66); // size prefix
2848 addr_nop_5();
2849 break;
2850 default:
2851 assert(i < 12, " ");
2852 }
2853
2854 // Generate second nop for size between 11-1
2855 switch (i) {
2856 case 11:
2857 emit_int8(0x66); // size prefix
2858 case 10:
2859 emit_int8(0x66); // size prefix
2860 case 9:
2861 emit_int8(0x66); // size prefix
2862 case 8:
2863 addr_nop_8();
2864 break;
2865 case 7:
2866 addr_nop_7();
2867 break;
2868 case 6:
2869 emit_int8(0x66); // size prefix
2870 case 5:
2871 addr_nop_5();
2872 break;
2873 case 4:
2874 addr_nop_4();
2875 break;
2876 case 3:
2877 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2878 emit_int8(0x66); // size prefix
2879 case 2:
2880 emit_int8(0x66); // size prefix
2881 case 1:
2882 emit_int8((unsigned char)0x90);
2883 // nop
2884 break;
2885 default:
2886 assert(i == 0, " ");
2887 }
2888 return;
2889 }
2890
2891 // Using nops with size prefixes "0x66 0x90".
2892 // From AMD Optimization Guide:
2893 // 1: 0x90
2894 // 2: 0x66 0x90
2895 // 3: 0x66 0x66 0x90
2896 // 4: 0x66 0x66 0x66 0x90
2897 // 5: 0x66 0x66 0x90 0x66 0x90
2898 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2899 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2900 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2901 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2902 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2903 //
2904 while(i > 12) {
2905 i -= 4;
2906 emit_int8(0x66); // size prefix
2907 emit_int8(0x66);
2908 emit_int8(0x66);
2909 emit_int8((unsigned char)0x90);
2910 // nop
2911 }
2912 // 1 - 12 nops
2913 if(i > 8) {
2914 if(i > 9) {
2915 i -= 1;
2916 emit_int8(0x66);
2917 }
2918 i -= 3;
2919 emit_int8(0x66);
2920 emit_int8(0x66);
2921 emit_int8((unsigned char)0x90);
2922 }
2923 // 1 - 8 nops
2924 if(i > 4) {
2925 if(i > 6) {
2926 i -= 1;
2927 emit_int8(0x66);
2928 }
2929 i -= 3;
2930 emit_int8(0x66);
2931 emit_int8(0x66);
2932 emit_int8((unsigned char)0x90);
2933 }
2934 switch (i) {
2935 case 4:
2936 emit_int8(0x66);
2937 case 3:
2938 emit_int8(0x66);
2939 case 2:
2940 emit_int8(0x66);
2941 case 1:
2942 emit_int8((unsigned char)0x90);
2943 break;
2944 default:
2945 assert(i == 0, " ");
2946 }
2947 }
2948
2949 void Assembler::notl(Register dst) {
2950 int encode = prefix_and_encode(dst->encoding());
2951 emit_int8((unsigned char)0xF7);
2952 emit_int8((unsigned char)(0xD0 | encode));
2953 }
2954
2955 void Assembler::orl(Address dst, int32_t imm32) {
2956 InstructionMark im(this);
2957 prefix(dst);
2958 emit_arith_operand(0x81, rcx, dst, imm32);
2959 }
2960
2961 void Assembler::orl(Register dst, int32_t imm32) {
2962 prefix(dst);
2963 emit_arith(0x81, 0xC8, dst, imm32);
2964 }
2965
2966 void Assembler::orl(Register dst, Address src) {
2967 InstructionMark im(this);
2968 prefix(src, dst);
2969 emit_int8(0x0B);
2970 emit_operand(dst, src);
2971 }
2972
2973 void Assembler::orl(Register dst, Register src) {
2974 (void) prefix_and_encode(dst->encoding(), src->encoding());
2975 emit_arith(0x0B, 0xC0, dst, src);
2976 }
2977
2978 void Assembler::orl(Address dst, Register src) {
2979 InstructionMark im(this);
2980 prefix(dst, src);
2981 emit_int8(0x09);
2982 emit_operand(src, dst);
2983 }
2984
2985 void Assembler::packuswb(XMMRegister dst, Address src) {
2986 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2987 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2988 if (VM_Version::supports_evex()) {
2989 _tuple_type = EVEX_FV;
2990 _input_size_in_bits = EVEX_32bit;
2991 }
2992 emit_simd_arith(0x67, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
2993 }
2994
2995 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2996 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2997 emit_simd_arith(0x67, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
2998 }
2999
3000 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3001 assert(UseAVX > 0, "some form of AVX must be enabled");
3002 emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
3003 }
3004
3005 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3006 _instruction_uses_vl = true;
3007 assert(VM_Version::supports_avx2(), "");
3008 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, /* no_mask_reg */ false,
3009 VEX_OPCODE_0F_3A, /* rex_w */ true, vector_len);
3010 emit_int8(0x00);
3011 emit_int8(0xC0 | encode);
3012 emit_int8(imm8);
3013 }
3014
3015 void Assembler::pause() {
3016 emit_int8((unsigned char)0xF3);
3017 emit_int8((unsigned char)0x90);
3018 }
3019
3020 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3021 assert(VM_Version::supports_sse4_2(), "");
3022 InstructionMark im(this);
3023 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, /* no_mask_reg */ false, VEX_OPCODE_0F_3A,
3024 /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
3025 emit_int8(0x61);
3026 emit_operand(dst, src);
3027 emit_int8(imm8);
3028 }
3029
3030 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3031 assert(VM_Version::supports_sse4_2(), "");
3032 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, /* no_mask_reg */ false,
3033 VEX_OPCODE_0F_3A, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
3034 emit_int8(0x61);
3035 emit_int8((unsigned char)(0xC0 | encode));
3036 emit_int8(imm8);
3037 }
3038
3039 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3040 assert(VM_Version::supports_sse4_1(), "");
3041 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, /* no_mask_reg */ true,
3042 VEX_OPCODE_0F_3A, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_dq);
3043 emit_int8(0x16);
3044 emit_int8((unsigned char)(0xC0 | encode));
3045 emit_int8(imm8);
3046 }
3047
3048 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3049 assert(VM_Version::supports_sse4_1(), "");
3050 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, /* no_mask_reg */ true,
3051 VEX_OPCODE_0F_3A, /* rex_w */ true, AVX_128bit, /* legacy_mode */ _legacy_mode_dq);
3052 emit_int8(0x16);
3053 emit_int8((unsigned char)(0xC0 | encode));
3054 emit_int8(imm8);
3055 }
3056
3057 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3058 assert(VM_Version::supports_sse2(), "");
3059 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, /* no_mask_reg */ true,
3060 VEX_OPCODE_0F, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
3061 emit_int8((unsigned char)0xC5);
3062 emit_int8((unsigned char)(0xC0 | encode));
3063 emit_int8(imm8);
3064 }
3065
3066 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3067 assert(VM_Version::supports_sse4_1(), "");
3068 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, /* no_mask_reg */ true,
3069 VEX_OPCODE_0F_3A, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_dq);
3070 emit_int8(0x22);
3071 emit_int8((unsigned char)(0xC0 | encode));
3072 emit_int8(imm8);
3073 }
3074
3075 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3076 assert(VM_Version::supports_sse4_1(), "");
3077 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, /* no_mask_reg */ true,
3078 VEX_OPCODE_0F_3A, /* rex_w */ true, AVX_128bit, /* legacy_mode */ _legacy_mode_dq);
3079 emit_int8(0x22);
3080 emit_int8((unsigned char)(0xC0 | encode));
3081 emit_int8(imm8);
3082 }
3083
3084 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3085 assert(VM_Version::supports_sse2(), "");
3086 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, /* no_mask_reg */ true,
3087 VEX_OPCODE_0F, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
3088 emit_int8((unsigned char)0xC4);
3089 emit_int8((unsigned char)(0xC0 | encode));
3090 emit_int8(imm8);
3091 }
3092
3093 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3094 assert(VM_Version::supports_sse4_1(), "");
3095 if (VM_Version::supports_evex()) {
3096 _tuple_type = EVEX_HVM;
3097 }
3098 InstructionMark im(this);
3099 simd_prefix(dst, src, VEX_SIMD_66, /* no_mask_reg */ false, VEX_OPCODE_0F_38);
3100 emit_int8(0x30);
3101 emit_operand(dst, src);
3102 }
3103
3104 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3105 assert(VM_Version::supports_sse4_1(), "");
3106 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, /* no_mask_reg */ false, VEX_OPCODE_0F_38);
3107 emit_int8(0x30);
3108 emit_int8((unsigned char)(0xC0 | encode));
3109 }
3110
3111 // generic
3112 void Assembler::pop(Register dst) {
3113 int encode = prefix_and_encode(dst->encoding());
3114 emit_int8(0x58 | encode);
3115 }
3116
3117 void Assembler::popcntl(Register dst, Address src) {
3118 assert(VM_Version::supports_popcnt(), "must support");
3119 InstructionMark im(this);
3120 emit_int8((unsigned char)0xF3);
3121 prefix(src, dst);
3122 emit_int8(0x0F);
3123 emit_int8((unsigned char)0xB8);
3124 emit_operand(dst, src);
3125 }
3126
3127 void Assembler::popcntl(Register dst, Register src) {
3128 assert(VM_Version::supports_popcnt(), "must support");
3129 emit_int8((unsigned char)0xF3);
3130 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3131 emit_int8(0x0F);
3132 emit_int8((unsigned char)0xB8);
3133 emit_int8((unsigned char)(0xC0 | encode));
3134 }
3135
3136 void Assembler::popf() {
3137 emit_int8((unsigned char)0x9D);
3138 }
3139
3140 #ifndef _LP64 // no 32bit push/pop on amd64
3141 void Assembler::popl(Address dst) {
3142 // NOTE: this will adjust stack by 8byte on 64bits
3143 InstructionMark im(this);
3144 prefix(dst);
3145 emit_int8((unsigned char)0x8F);
3146 emit_operand(rax, dst);
3147 }
3148 #endif
3149
3150 void Assembler::prefetch_prefix(Address src) {
3151 prefix(src);
3152 emit_int8(0x0F);
3153 }
3154
3155 void Assembler::prefetchnta(Address src) {
3156 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3157 InstructionMark im(this);
3158 prefetch_prefix(src);
3159 emit_int8(0x18);
3160 emit_operand(rax, src); // 0, src
3161 }
3162
3163 void Assembler::prefetchr(Address src) {
3164 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3165 InstructionMark im(this);
3166 prefetch_prefix(src);
3167 emit_int8(0x0D);
3168 emit_operand(rax, src); // 0, src
3169 }
3170
3171 void Assembler::prefetcht0(Address src) {
3172 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3173 InstructionMark im(this);
3174 prefetch_prefix(src);
3175 emit_int8(0x18);
3176 emit_operand(rcx, src); // 1, src
3177 }
3178
3179 void Assembler::prefetcht1(Address src) {
3180 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3181 InstructionMark im(this);
3182 prefetch_prefix(src);
3183 emit_int8(0x18);
3184 emit_operand(rdx, src); // 2, src
3185 }
3186
3187 void Assembler::prefetcht2(Address src) {
3188 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3189 InstructionMark im(this);
3190 prefetch_prefix(src);
3191 emit_int8(0x18);
3192 emit_operand(rbx, src); // 3, src
3193 }
3194
3195 void Assembler::prefetchw(Address src) {
3196 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3197 InstructionMark im(this);
3198 prefetch_prefix(src);
3199 emit_int8(0x0D);
3200 emit_operand(rcx, src); // 1, src
3201 }
3202
3203 void Assembler::prefix(Prefix p) {
3204 emit_int8(p);
3205 }
3206
3207 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3208 assert(VM_Version::supports_ssse3(), "");
3209 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
3210 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
3211 emit_int8(0x00);
3212 emit_int8((unsigned char)(0xC0 | encode));
3213 }
3214
3215 void Assembler::pshufb(XMMRegister dst, Address src) {
3216 assert(VM_Version::supports_ssse3(), "");
3217 if (VM_Version::supports_evex()) {
3218 _tuple_type = EVEX_FVM;
3219 }
3220 InstructionMark im(this);
3221 simd_prefix(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
3222 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
3223 emit_int8(0x00);
3224 emit_operand(dst, src);
3225 }
3226
3227 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
3228 _instruction_uses_vl = true;
3229 assert(isByte(mode), "invalid value");
3230 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3231 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
3232 emit_int8(mode & 0xFF);
3233 }
3234
3235 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
3236 _instruction_uses_vl = true;
3237 assert(isByte(mode), "invalid value");
3238 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3239 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3240 if (VM_Version::supports_evex()) {
3241 _tuple_type = EVEX_FV;
3242 _input_size_in_bits = EVEX_32bit;
3243 }
3244 InstructionMark im(this);
3245 simd_prefix(dst, src, VEX_SIMD_66, /* no_mask_reg */ false);
3246 emit_int8(0x70);
3247 emit_operand(dst, src);
3248 emit_int8(mode & 0xFF);
3249 }
3250
3251 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3252 assert(isByte(mode), "invalid value");
3253 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3254 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
3255 emit_int8(mode & 0xFF);
3256 }
3257
3258 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3259 assert(isByte(mode), "invalid value");
3260 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3261 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3262 if (VM_Version::supports_evex()) {
3263 _tuple_type = EVEX_FVM;
3264 }
3265 InstructionMark im(this);
3266 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, /* no_mask_reg */ false,
3267 VEX_OPCODE_0F, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
3268 emit_int8(0x70);
3269 emit_operand(dst, src);
3270 emit_int8(mode & 0xFF);
3271 }
3272
3273 void Assembler::psrldq(XMMRegister dst, int shift) {
3274 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3275 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3276 // XMM3 is for /3 encoding: 66 0F 73 /3 ib
3277 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, /* no_mask_reg */ true,
3278 VEX_OPCODE_0F, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
3279 emit_int8(0x73);
3280 emit_int8((unsigned char)(0xC0 | encode));
3281 emit_int8(shift);
3282 }
3283
3284 void Assembler::pslldq(XMMRegister dst, int shift) {
3285 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3286 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3287 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
3288 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, /* no_mask_reg */ true,
3289 VEX_OPCODE_0F, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
3290 emit_int8(0x73);
3291 emit_int8((unsigned char)(0xC0 | encode));
3292 emit_int8(shift);
3293 }
3294
3295 void Assembler::ptest(XMMRegister dst, Address src) {
3296 assert(VM_Version::supports_sse4_1(), "");
3297 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3298 InstructionMark im(this);
3299 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, /* no_mask_reg */ false,
3300 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
3301 emit_int8(0x17);
3302 emit_operand(dst, src);
3303 }
3304
3305 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3306 assert(VM_Version::supports_sse4_1(), "");
3307 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, /* no_mask_reg */ false,
3308 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
3309 emit_int8(0x17);
3310 emit_int8((unsigned char)(0xC0 | encode));
3311 }
3312
3313 void Assembler::vptest(XMMRegister dst, Address src) {
3314 assert(VM_Version::supports_avx(), "");
3315 InstructionMark im(this);
3316 int vector_len = AVX_256bit;
3317 assert(dst != xnoreg, "sanity");
3318 int dst_enc = dst->encoding();
3319 // swap src<->dst for encoding
3320 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, /* rex_w */ false,
3321 vector_len, /* legacy_mode */ true, /* no_mask_reg */ false);
3322 emit_int8(0x17);
3323 emit_operand(dst, src);
3324 }
3325
3326 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
3327 assert(VM_Version::supports_avx(), "");
3328 int vector_len = AVX_256bit;
3329 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_38, /* legacy_mode */ true);
3330 emit_int8(0x17);
3331 emit_int8((unsigned char)(0xC0 | encode));
3332 }
3333
3334 void Assembler::punpcklbw(XMMRegister dst, Address src) {
3335 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3336 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3337 if (VM_Version::supports_evex()) {
3338 _tuple_type = EVEX_FVM;
3339 }
3340 emit_simd_arith(0x60, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_vlbw);
3341 }
3342
3343 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3344 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3345 emit_simd_arith(0x60, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_vlbw);
3346 }
3347
3348 void Assembler::punpckldq(XMMRegister dst, Address src) {
3349 _instruction_uses_vl = true;
3350 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3351 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3352 if (VM_Version::supports_evex()) {
3353 _tuple_type = EVEX_FV;
3354 _input_size_in_bits = EVEX_32bit;
3355 }
3356 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
3357 }
3358
3359 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
3360 _instruction_uses_vl = true;
3361 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3362 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
3363 }
3364
3365 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
3366 _instruction_uses_vl = true;
3367 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3368 if (VM_Version::supports_evex()) {
3369 emit_simd_arith_q(0x6C, dst, src, VEX_SIMD_66);
3370 } else {
3371 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66);
3372 }
3373 }
3374
3375 void Assembler::push(int32_t imm32) {
3376 // in 64bits we push 64bits onto the stack but only
3377 // take a 32bit immediate
3378 emit_int8(0x68);
3379 emit_int32(imm32);
3380 }
3381
3382 void Assembler::push(Register src) {
3383 int encode = prefix_and_encode(src->encoding());
3384
3385 emit_int8(0x50 | encode);
3386 }
3387
3388 void Assembler::pushf() {
3389 emit_int8((unsigned char)0x9C);
3390 }
3391
3392 #ifndef _LP64 // no 32bit push/pop on amd64
3393 void Assembler::pushl(Address src) {
3394 // Note this will push 64bit on 64bit
3395 InstructionMark im(this);
3396 prefix(src);
3397 emit_int8((unsigned char)0xFF);
3398 emit_operand(rsi, src);
3399 }
3400 #endif
3401
3402 void Assembler::rcll(Register dst, int imm8) {
3403 assert(isShiftCount(imm8), "illegal shift count");
3404 int encode = prefix_and_encode(dst->encoding());
3405 if (imm8 == 1) {
3406 emit_int8((unsigned char)0xD1);
3407 emit_int8((unsigned char)(0xD0 | encode));
3408 } else {
3409 emit_int8((unsigned char)0xC1);
3410 emit_int8((unsigned char)0xD0 | encode);
3411 emit_int8(imm8);
3412 }
3413 }
3414
3415 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
3416 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3417 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, /* no_mask_reg */ false, VEX_OPCODE_0F, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
3418 emit_int8(0x53);
3419 emit_int8(0xC0 | encode);
3420 }
3421
3422 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
3423 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3424 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, /* no_mask_reg */ false, VEX_OPCODE_0F, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
3425 emit_int8(0x53);
3426 emit_int8(0xC0 | encode);
3427 }
3428
3429 void Assembler::rdtsc() {
3430 emit_int8((unsigned char)0x0F);
3431 emit_int8((unsigned char)0x31);
3432 }
3433
3434 // copies data from [esi] to [edi] using rcx pointer sized words
3435 // generic
3436 void Assembler::rep_mov() {
3437 emit_int8((unsigned char)0xF3);
3438 // MOVSQ
3439 LP64_ONLY(prefix(REX_W));
3440 emit_int8((unsigned char)0xA5);
3441 }
3442
3443 // sets rcx bytes with rax, value at [edi]
3444 void Assembler::rep_stosb() {
3445 emit_int8((unsigned char)0xF3); // REP
3446 LP64_ONLY(prefix(REX_W));
3447 emit_int8((unsigned char)0xAA); // STOSB
3448 }
3449
3450 // sets rcx pointer sized words with rax, value at [edi]
3451 // generic
3452 void Assembler::rep_stos() {
3453 emit_int8((unsigned char)0xF3); // REP
3454 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
3455 emit_int8((unsigned char)0xAB);
3456 }
3457
3458 // scans rcx pointer sized words at [edi] for occurance of rax,
3459 // generic
3460 void Assembler::repne_scan() { // repne_scan
3461 emit_int8((unsigned char)0xF2);
3462 // SCASQ
3463 LP64_ONLY(prefix(REX_W));
3464 emit_int8((unsigned char)0xAF);
3465 }
3466
3467 #ifdef _LP64
3468 // scans rcx 4 byte words at [edi] for occurance of rax,
3469 // generic
3470 void Assembler::repne_scanl() { // repne_scan
3471 emit_int8((unsigned char)0xF2);
3472 // SCASL
3473 emit_int8((unsigned char)0xAF);
3474 }
3475 #endif
3476
3477 void Assembler::ret(int imm16) {
3478 if (imm16 == 0) {
3479 emit_int8((unsigned char)0xC3);
3480 } else {
3481 emit_int8((unsigned char)0xC2);
3482 emit_int16(imm16);
3483 }
3484 }
3485
3486 void Assembler::sahf() {
3487 #ifdef _LP64
3488 // Not supported in 64bit mode
3489 ShouldNotReachHere();
3490 #endif
3491 emit_int8((unsigned char)0x9E);
3492 }
3493
3494 void Assembler::sarl(Register dst, int imm8) {
3495 int encode = prefix_and_encode(dst->encoding());
3496 assert(isShiftCount(imm8), "illegal shift count");
3497 if (imm8 == 1) {
3498 emit_int8((unsigned char)0xD1);
3499 emit_int8((unsigned char)(0xF8 | encode));
3500 } else {
3501 emit_int8((unsigned char)0xC1);
3502 emit_int8((unsigned char)(0xF8 | encode));
3503 emit_int8(imm8);
3504 }
3505 }
3506
3507 void Assembler::sarl(Register dst) {
3508 int encode = prefix_and_encode(dst->encoding());
3509 emit_int8((unsigned char)0xD3);
3510 emit_int8((unsigned char)(0xF8 | encode));
3511 }
3512
3513 void Assembler::sbbl(Address dst, int32_t imm32) {
3514 InstructionMark im(this);
3515 prefix(dst);
3516 emit_arith_operand(0x81, rbx, dst, imm32);
3517 }
3518
3519 void Assembler::sbbl(Register dst, int32_t imm32) {
3520 prefix(dst);
3521 emit_arith(0x81, 0xD8, dst, imm32);
3522 }
3523
3524
3525 void Assembler::sbbl(Register dst, Address src) {
3526 InstructionMark im(this);
3527 prefix(src, dst);
3528 emit_int8(0x1B);
3529 emit_operand(dst, src);
3530 }
3531
3532 void Assembler::sbbl(Register dst, Register src) {
3533 (void) prefix_and_encode(dst->encoding(), src->encoding());
3534 emit_arith(0x1B, 0xC0, dst, src);
3535 }
3536
3537 void Assembler::setb(Condition cc, Register dst) {
3538 assert(0 <= cc && cc < 16, "illegal cc");
3539 int encode = prefix_and_encode(dst->encoding(), true);
3540 emit_int8(0x0F);
3541 emit_int8((unsigned char)0x90 | cc);
3542 emit_int8((unsigned char)(0xC0 | encode));
3543 }
3544
3545 void Assembler::shll(Register dst, int imm8) {
3546 assert(isShiftCount(imm8), "illegal shift count");
3547 int encode = prefix_and_encode(dst->encoding());
3548 if (imm8 == 1 ) {
3549 emit_int8((unsigned char)0xD1);
3550 emit_int8((unsigned char)(0xE0 | encode));
3551 } else {
3552 emit_int8((unsigned char)0xC1);
3553 emit_int8((unsigned char)(0xE0 | encode));
3554 emit_int8(imm8);
3555 }
3556 }
3557
3558 void Assembler::shll(Register dst) {
3559 int encode = prefix_and_encode(dst->encoding());
3560 emit_int8((unsigned char)0xD3);
3561 emit_int8((unsigned char)(0xE0 | encode));
3562 }
3563
3564 void Assembler::shrl(Register dst, int imm8) {
3565 assert(isShiftCount(imm8), "illegal shift count");
3566 int encode = prefix_and_encode(dst->encoding());
3567 emit_int8((unsigned char)0xC1);
3568 emit_int8((unsigned char)(0xE8 | encode));
3569 emit_int8(imm8);
3570 }
3571
3572 void Assembler::shrl(Register dst) {
3573 int encode = prefix_and_encode(dst->encoding());
3574 emit_int8((unsigned char)0xD3);
3575 emit_int8((unsigned char)(0xE8 | encode));
3576 }
3577
3578 // copies a single word from [esi] to [edi]
3579 void Assembler::smovl() {
3580 emit_int8((unsigned char)0xA5);
3581 }
3582
3583 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
3584 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3585 if (VM_Version::supports_evex()) {
3586 emit_simd_arith_q(0x51, dst, src, VEX_SIMD_F2);
3587 } else {
3588 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
3589 }
3590 }
3591
3592 void Assembler::sqrtsd(XMMRegister dst, Address src) {
3593 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3594 if (VM_Version::supports_evex()) {
3595 _tuple_type = EVEX_T1S;
3596 _input_size_in_bits = EVEX_64bit;
3597 emit_simd_arith_q(0x51, dst, src, VEX_SIMD_F2);
3598 } else {
3599 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
3600 }
3601 }
3602
3603 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
3604 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3605 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
3606 }
3607
3608 void Assembler::std() {
3609 emit_int8((unsigned char)0xFD);
3610 }
3611
3612 void Assembler::sqrtss(XMMRegister dst, Address src) {
3613 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3614 if (VM_Version::supports_evex()) {
3615 _tuple_type = EVEX_T1S;
3616 _input_size_in_bits = EVEX_32bit;
3617 }
3618 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
3619 }
3620
3621 void Assembler::stmxcsr( Address dst) {
3622 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3623 InstructionMark im(this);
3624 prefix(dst);
3625 emit_int8(0x0F);
3626 emit_int8((unsigned char)0xAE);
3627 emit_operand(as_Register(3), dst);
3628 }
3629
3630 void Assembler::subl(Address dst, int32_t imm32) {
3631 InstructionMark im(this);
3632 prefix(dst);
3633 emit_arith_operand(0x81, rbp, dst, imm32);
3634 }
3635
3636 void Assembler::subl(Address dst, Register src) {
3637 InstructionMark im(this);
3638 prefix(dst, src);
3639 emit_int8(0x29);
3640 emit_operand(src, dst);
3641 }
3642
3643 void Assembler::subl(Register dst, int32_t imm32) {
3644 prefix(dst);
3645 emit_arith(0x81, 0xE8, dst, imm32);
3646 }
3647
3648 // Force generation of a 4 byte immediate value even if it fits into 8bit
3649 void Assembler::subl_imm32(Register dst, int32_t imm32) {
3650 prefix(dst);
3651 emit_arith_imm32(0x81, 0xE8, dst, imm32);
3652 }
3653
3654 void Assembler::subl(Register dst, Address src) {
3655 InstructionMark im(this);
3656 prefix(src, dst);
3657 emit_int8(0x2B);
3658 emit_operand(dst, src);
3659 }
3660
3661 void Assembler::subl(Register dst, Register src) {
3662 (void) prefix_and_encode(dst->encoding(), src->encoding());
3663 emit_arith(0x2B, 0xC0, dst, src);
3664 }
3665
3666 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
3667 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3668 if (VM_Version::supports_evex()) {
3669 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_F2);
3670 } else {
3671 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
3672 }
3673 }
3674
3675 void Assembler::subsd(XMMRegister dst, Address src) {
3676 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3677 if (VM_Version::supports_evex()) {
3678 _tuple_type = EVEX_T1S;
3679 _input_size_in_bits = EVEX_64bit;
3680 }
3681 if (VM_Version::supports_evex()) {
3682 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_F2);
3683 } else {
3684 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
3685 }
3686 }
3687
3688 void Assembler::subss(XMMRegister dst, XMMRegister src) {
3689 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3690 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
3691 }
3692
3693 void Assembler::subss(XMMRegister dst, Address src) {
3694 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3695 if (VM_Version::supports_evex()) {
3696 _tuple_type = EVEX_T1S;
3697 _input_size_in_bits = EVEX_32bit;
3698 }
3699 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
3700 }
3701
3702 void Assembler::testb(Register dst, int imm8) {
3703 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
3704 (void) prefix_and_encode(dst->encoding(), true);
3705 emit_arith_b(0xF6, 0xC0, dst, imm8);
3706 }
3707
3708 void Assembler::testl(Register dst, int32_t imm32) {
3709 // not using emit_arith because test
3710 // doesn't support sign-extension of
3711 // 8bit operands
3712 int encode = dst->encoding();
3713 if (encode == 0) {
3714 emit_int8((unsigned char)0xA9);
3715 } else {
3716 encode = prefix_and_encode(encode);
3717 emit_int8((unsigned char)0xF7);
3718 emit_int8((unsigned char)(0xC0 | encode));
3719 }
3720 emit_int32(imm32);
3721 }
3722
3723 void Assembler::testl(Register dst, Register src) {
3724 (void) prefix_and_encode(dst->encoding(), src->encoding());
3725 emit_arith(0x85, 0xC0, dst, src);
3726 }
3727
3728 void Assembler::testl(Register dst, Address src) {
3729 InstructionMark im(this);
3730 prefix(src, dst);
3731 emit_int8((unsigned char)0x85);
3732 emit_operand(dst, src);
3733 }
3734
3735 void Assembler::tzcntl(Register dst, Register src) {
3736 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
3737 emit_int8((unsigned char)0xF3);
3738 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3739 emit_int8(0x0F);
3740 emit_int8((unsigned char)0xBC);
3741 emit_int8((unsigned char)0xC0 | encode);
3742 }
3743
3744 void Assembler::tzcntq(Register dst, Register src) {
3745 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
3746 emit_int8((unsigned char)0xF3);
3747 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3748 emit_int8(0x0F);
3749 emit_int8((unsigned char)0xBC);
3750 emit_int8((unsigned char)(0xC0 | encode));
3751 }
3752
3753 void Assembler::ucomisd(XMMRegister dst, Address src) {
3754 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3755 if (VM_Version::supports_evex()) {
3756 _tuple_type = EVEX_T1S;
3757 _input_size_in_bits = EVEX_64bit;
3758 emit_simd_arith_nonds_q(0x2E, dst, src, VEX_SIMD_66, /* no_mask_reg */ true);
3759 } else {
3760 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
3761 }
3762 }
3763
3764 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
3765 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3766 if (VM_Version::supports_evex()) {
3767 emit_simd_arith_nonds_q(0x2E, dst, src, VEX_SIMD_66, /* no_mask_reg */ true);
3768 } else {
3769 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
3770 }
3771 }
3772
3773 void Assembler::ucomiss(XMMRegister dst, Address src) {
3774 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3775 if (VM_Version::supports_evex()) {
3776 _tuple_type = EVEX_T1S;
3777 _input_size_in_bits = EVEX_32bit;
3778 }
3779 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE, /* no_mask_reg */ true);
3780 }
3781
3782 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
3783 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3784 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE, /* no_mask_reg */ true);
3785 }
3786
3787 void Assembler::xabort(int8_t imm8) {
3788 emit_int8((unsigned char)0xC6);
3789 emit_int8((unsigned char)0xF8);
3790 emit_int8((unsigned char)(imm8 & 0xFF));
3791 }
3792
3793 void Assembler::xaddl(Address dst, Register src) {
3794 InstructionMark im(this);
3795 prefix(dst, src);
3796 emit_int8(0x0F);
3797 emit_int8((unsigned char)0xC1);
3798 emit_operand(src, dst);
3799 }
3800
3801 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
3802 InstructionMark im(this);
3803 relocate(rtype);
3804 if (abort.is_bound()) {
3805 address entry = target(abort);
3806 assert(entry != NULL, "abort entry NULL");
3807 intptr_t offset = entry - pc();
3808 emit_int8((unsigned char)0xC7);
3809 emit_int8((unsigned char)0xF8);
3810 emit_int32(offset - 6); // 2 opcode + 4 address
3811 } else {
3812 abort.add_patch_at(code(), locator());
3813 emit_int8((unsigned char)0xC7);
3814 emit_int8((unsigned char)0xF8);
3815 emit_int32(0);
3816 }
3817 }
3818
3819 void Assembler::xchgl(Register dst, Address src) { // xchg
3820 InstructionMark im(this);
3821 prefix(src, dst);
3822 emit_int8((unsigned char)0x87);
3823 emit_operand(dst, src);
3824 }
3825
3826 void Assembler::xchgl(Register dst, Register src) {
3827 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3828 emit_int8((unsigned char)0x87);
3829 emit_int8((unsigned char)(0xC0 | encode));
3830 }
3831
3832 void Assembler::xend() {
3833 emit_int8((unsigned char)0x0F);
3834 emit_int8((unsigned char)0x01);
3835 emit_int8((unsigned char)0xD5);
3836 }
3837
3838 void Assembler::xgetbv() {
3839 emit_int8(0x0F);
3840 emit_int8(0x01);
3841 emit_int8((unsigned char)0xD0);
3842 }
3843
3844 void Assembler::xorl(Register dst, int32_t imm32) {
3845 prefix(dst);
3846 emit_arith(0x81, 0xF0, dst, imm32);
3847 }
3848
3849 void Assembler::xorl(Register dst, Address src) {
3850 InstructionMark im(this);
3851 prefix(src, dst);
3852 emit_int8(0x33);
3853 emit_operand(dst, src);
3854 }
3855
3856 void Assembler::xorl(Register dst, Register src) {
3857 (void) prefix_and_encode(dst->encoding(), src->encoding());
3858 emit_arith(0x33, 0xC0, dst, src);
3859 }
3860
3861
3862 // AVX 3-operands scalar float-point arithmetic instructions
3863
3864 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
3865 assert(VM_Version::supports_avx(), "");
3866 if (VM_Version::supports_evex()) {
3867 _tuple_type = EVEX_T1S;
3868 _input_size_in_bits = EVEX_64bit;
3869 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3870 } else {
3871 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3872 }
3873 }
3874
3875 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3876 assert(VM_Version::supports_avx(), "");
3877 if (VM_Version::supports_evex()) {
3878 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3879 } else {
3880 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3881 }
3882 }
3883
3884 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
3885 assert(VM_Version::supports_avx(), "");
3886 if (VM_Version::supports_evex()) {
3887 _tuple_type = EVEX_T1S;
3888 _input_size_in_bits = EVEX_32bit;
3889 }
3890 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3891 }
3892
3893 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3894 assert(VM_Version::supports_avx(), "");
3895 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3896 }
3897
3898 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
3899 assert(VM_Version::supports_avx(), "");
3900 if (VM_Version::supports_evex()) {
3901 _tuple_type = EVEX_T1S;
3902 _input_size_in_bits = EVEX_64bit;
3903 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3904 } else {
3905 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3906 }
3907 }
3908
3909 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3910 assert(VM_Version::supports_avx(), "");
3911 if (VM_Version::supports_evex()) {
3912 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3913 } else {
3914 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3915 }
3916 }
3917
3918 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
3919 assert(VM_Version::supports_avx(), "");
3920 if (VM_Version::supports_evex()) {
3921 _tuple_type = EVEX_T1S;
3922 _input_size_in_bits = EVEX_32bit;
3923 }
3924 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3925 }
3926
3927 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3928 assert(VM_Version::supports_avx(), "");
3929 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3930 }
3931
3932 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
3933 assert(VM_Version::supports_avx(), "");
3934 if (VM_Version::supports_evex()) {
3935 _tuple_type = EVEX_T1S;
3936 _input_size_in_bits = EVEX_64bit;
3937 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3938 } else {
3939 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3940 }
3941 }
3942
3943 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3944 assert(VM_Version::supports_avx(), "");
3945 if (VM_Version::supports_evex()) {
3946 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3947 } else {
3948 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3949 }
3950 }
3951
3952 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
3953 assert(VM_Version::supports_avx(), "");
3954 if (VM_Version::supports_evex()) {
3955 _tuple_type = EVEX_T1S;
3956 _input_size_in_bits = EVEX_32bit;
3957 }
3958 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3959 }
3960
3961 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3962 assert(VM_Version::supports_avx(), "");
3963 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3964 }
3965
3966 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
3967 assert(VM_Version::supports_avx(), "");
3968 if (VM_Version::supports_evex()) {
3969 _tuple_type = EVEX_T1S;
3970 _input_size_in_bits = EVEX_64bit;
3971 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3972 } else {
3973 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3974 }
3975 }
3976
3977 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3978 assert(VM_Version::supports_avx(), "");
3979 if (VM_Version::supports_evex()) {
3980 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3981 } else {
3982 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3983 }
3984 }
3985
3986 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
3987 assert(VM_Version::supports_avx(), "");
3988 if (VM_Version::supports_evex()) {
3989 _tuple_type = EVEX_T1S;
3990 _input_size_in_bits = EVEX_32bit;
3991 }
3992 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3993 }
3994
3995 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3996 assert(VM_Version::supports_avx(), "");
3997 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3998 }
3999
4000 //====================VECTOR ARITHMETIC=====================================
4001
4002 // Float-point vector arithmetic
4003
4004 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4005 _instruction_uses_vl = true;
4006 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4007 if (VM_Version::supports_evex()) {
4008 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_66);
4009 } else {
4010 emit_simd_arith(0x58, dst, src, VEX_SIMD_66);
4011 }
4012 }
4013
4014 void Assembler::addps(XMMRegister dst, XMMRegister src) {
4015 _instruction_uses_vl = true;
4016 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4017 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE);
4018 }
4019
4020 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4021 _instruction_uses_vl = true;
4022 assert(VM_Version::supports_avx(), "");
4023 if (VM_Version::supports_evex()) {
4024 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
4025 } else {
4026 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
4027 }
4028 }
4029
4030 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4031 _instruction_uses_vl = true;
4032 assert(VM_Version::supports_avx(), "");
4033 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector_len);
4034 }
4035
4036 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4037 _instruction_uses_vl = true;
4038 assert(VM_Version::supports_avx(), "");
4039 if (VM_Version::supports_evex()) {
4040 _tuple_type = EVEX_FV;
4041 _input_size_in_bits = EVEX_64bit;
4042 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
4043 } else {
4044 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
4045 }
4046 }
4047
4048 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4049 _instruction_uses_vl = true;
4050 assert(VM_Version::supports_avx(), "");
4051 if (VM_Version::supports_evex()) {
4052 _tuple_type = EVEX_FV;
4053 _input_size_in_bits = EVEX_32bit;
4054 }
4055 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector_len);
4056 }
4057
4058 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
4059 _instruction_uses_vl = true;
4060 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4061 if (VM_Version::supports_evex()) {
4062 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_66);
4063 } else {
4064 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66);
4065 }
4066 }
4067
4068 void Assembler::subps(XMMRegister dst, XMMRegister src) {
4069 _instruction_uses_vl = true;
4070 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4071 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE);
4072 }
4073
4074 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4075 _instruction_uses_vl = true;
4076 assert(VM_Version::supports_avx(), "");
4077 if (VM_Version::supports_evex()) {
4078 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
4079 } else {
4080 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
4081 }
4082 }
4083
4084 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4085 _instruction_uses_vl = true;
4086 assert(VM_Version::supports_avx(), "");
4087 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector_len);
4088 }
4089
4090 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4091 _instruction_uses_vl = true;
4092 assert(VM_Version::supports_avx(), "");
4093 if (VM_Version::supports_evex()) {
4094 _tuple_type = EVEX_FV;
4095 _input_size_in_bits = EVEX_64bit;
4096 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
4097 } else {
4098 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
4099 }
4100 }
4101
4102 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4103 _instruction_uses_vl = true;
4104 assert(VM_Version::supports_avx(), "");
4105 if (VM_Version::supports_evex()) {
4106 _tuple_type = EVEX_FV;
4107 _input_size_in_bits = EVEX_32bit;
4108 }
4109 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector_len);
4110 }
4111
4112 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
4113 _instruction_uses_vl = true;
4114 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4115 if (VM_Version::supports_evex()) {
4116 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_66);
4117 } else {
4118 emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
4119 }
4120 }
4121
4122 void Assembler::mulpd(XMMRegister dst, Address src) {
4123 _instruction_uses_vl = true;
4124 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4125 if (VM_Version::supports_evex()) {
4126 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_66);
4127 } else {
4128 emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
4129 }
4130 }
4131
4132 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
4133 _instruction_uses_vl = true;
4134 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4135 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE);
4136 }
4137
4138 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4139 _instruction_uses_vl = true;
4140 assert(VM_Version::supports_avx(), "");
4141 if (VM_Version::supports_evex()) {
4142 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
4143 } else {
4144 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
4145 }
4146 }
4147
4148 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4149 _instruction_uses_vl = true;
4150 assert(VM_Version::supports_avx(), "");
4151 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector_len);
4152 }
4153
4154 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4155 _instruction_uses_vl = true;
4156 assert(VM_Version::supports_avx(), "");
4157 if (VM_Version::supports_evex()) {
4158 _tuple_type = EVEX_FV;
4159 _input_size_in_bits = EVEX_64bit;
4160 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
4161 } else {
4162 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
4163 }
4164 }
4165
4166 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4167 _instruction_uses_vl = true;
4168 assert(VM_Version::supports_avx(), "");
4169 if (VM_Version::supports_evex()) {
4170 _tuple_type = EVEX_FV;
4171 _input_size_in_bits = EVEX_32bit;
4172 }
4173 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector_len);
4174 }
4175
4176 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
4177 _instruction_uses_vl = true;
4178 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4179 if (VM_Version::supports_evex()) {
4180 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_66);
4181 } else {
4182 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66);
4183 }
4184 }
4185
4186 void Assembler::divps(XMMRegister dst, XMMRegister src) {
4187 _instruction_uses_vl = true;
4188 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4189 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE);
4190 }
4191
4192 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4193 _instruction_uses_vl = true;
4194 assert(VM_Version::supports_avx(), "");
4195 if (VM_Version::supports_evex()) {
4196 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
4197 } else {
4198 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
4199 }
4200 }
4201
4202 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4203 _instruction_uses_vl = true;
4204 assert(VM_Version::supports_avx(), "");
4205 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector_len);
4206 }
4207
4208 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4209 _instruction_uses_vl = true;
4210 assert(VM_Version::supports_avx(), "");
4211 if (VM_Version::supports_evex()) {
4212 _tuple_type = EVEX_FV;
4213 _input_size_in_bits = EVEX_64bit;
4214 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
4215 } else {
4216 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
4217 }
4218 }
4219
4220 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4221 _instruction_uses_vl = true;
4222 assert(VM_Version::supports_avx(), "");
4223 if (VM_Version::supports_evex()) {
4224 _tuple_type = EVEX_FV;
4225 _input_size_in_bits = EVEX_32bit;
4226 }
4227 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector_len);
4228 }
4229
4230 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
4231 _instruction_uses_vl = true;
4232 assert(VM_Version::supports_avx(), "");
4233 if (VM_Version::supports_evex()) {
4234 emit_vex_arith_q(0x51, dst, xnoreg, src, VEX_SIMD_66, vector_len);
4235 } else {
4236 emit_vex_arith(0x51, dst, xnoreg, src, VEX_SIMD_66, vector_len);
4237 }
4238 }
4239
4240 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
4241 _instruction_uses_vl = true;
4242 assert(VM_Version::supports_avx(), "");
4243 if (VM_Version::supports_evex()) {
4244 _tuple_type = EVEX_FV;
4245 _input_size_in_bits = EVEX_64bit;
4246 emit_vex_arith_q(0x51, dst, xnoreg, src, VEX_SIMD_66, vector_len);
4247 } else {
4248 emit_vex_arith(0x51, dst, xnoreg, src, VEX_SIMD_66, vector_len);
4249 }
4250 }
4251
4252 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
4253 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4254 if (VM_Version::supports_avx512dq()) {
4255 emit_simd_arith_q(0x54, dst, src, VEX_SIMD_66);
4256 } else {
4257 emit_simd_arith(0x54, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ true);
4258 }
4259 }
4260
4261 void Assembler::andps(XMMRegister dst, XMMRegister src) {
4262 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4263 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_dq);
4264 }
4265
4266 void Assembler::andps(XMMRegister dst, Address src) {
4267 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4268 if (VM_Version::supports_evex()) {
4269 _tuple_type = EVEX_FV;
4270 _input_size_in_bits = EVEX_32bit;
4271 }
4272 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_dq);
4273 }
4274
4275 void Assembler::andpd(XMMRegister dst, Address src) {
4276 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4277 if (VM_Version::supports_avx512dq()) {
4278 _tuple_type = EVEX_FV;
4279 _input_size_in_bits = EVEX_64bit;
4280 emit_simd_arith_q(0x54, dst, src, VEX_SIMD_66);
4281 } else {
4282 emit_simd_arith(0x54, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ true);
4283 }
4284 }
4285
4286 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4287 assert(VM_Version::supports_avx(), "");
4288 if (VM_Version::supports_avx512dq()) {
4289 emit_vex_arith_q(0x54, dst, nds, src, VEX_SIMD_66, vector_len);
4290 } else {
4291 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ true);
4292 }
4293 }
4294
4295 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4296 assert(VM_Version::supports_avx(), "");
4297 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_dq);
4298 }
4299
4300 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4301 assert(VM_Version::supports_avx(), "");
4302 if (VM_Version::supports_avx512dq()) {
4303 _tuple_type = EVEX_FV;
4304 _input_size_in_bits = EVEX_64bit;
4305 emit_vex_arith_q(0x54, dst, nds, src, VEX_SIMD_66, vector_len);
4306 } else {
4307 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ true);
4308 }
4309 }
4310
4311 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4312 assert(VM_Version::supports_avx(), "");
4313 if (VM_Version::supports_evex()) {
4314 _tuple_type = EVEX_FV;
4315 _input_size_in_bits = EVEX_32bit;
4316 }
4317 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_dq);
4318 }
4319
4320 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
4321 _instruction_uses_vl = true;
4322 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4323 if (VM_Version::supports_evex()) {
4324 emit_simd_arith_q(0x15, dst, src, VEX_SIMD_66);
4325 } else {
4326 emit_simd_arith(0x15, dst, src, VEX_SIMD_66);
4327 }
4328 }
4329
4330 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
4331 _instruction_uses_vl = true;
4332 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4333 if (VM_Version::supports_evex()) {
4334 emit_simd_arith_q(0x14, dst, src, VEX_SIMD_66);
4335 } else {
4336 emit_simd_arith(0x14, dst, src, VEX_SIMD_66);
4337 }
4338 }
4339
4340 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
4341 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4342 if (VM_Version::supports_avx512dq()) {
4343 emit_simd_arith_q(0x57, dst, src, VEX_SIMD_66);
4344 } else {
4345 emit_simd_arith(0x57, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ true);
4346 }
4347 }
4348
4349 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
4350 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4351 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_dq);
4352 }
4353
4354 void Assembler::xorpd(XMMRegister dst, Address src) {
4355 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4356 if (VM_Version::supports_avx512dq()) {
4357 _tuple_type = EVEX_FV;
4358 _input_size_in_bits = EVEX_64bit;
4359 emit_simd_arith_q(0x57, dst, src, VEX_SIMD_66);
4360 } else {
4361 emit_simd_arith(0x57, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ true);
4362 }
4363 }
4364
4365 void Assembler::xorps(XMMRegister dst, Address src) {
4366 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4367 if (VM_Version::supports_evex()) {
4368 _tuple_type = EVEX_FV;
4369 _input_size_in_bits = EVEX_32bit;
4370 }
4371 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_dq);
4372 }
4373
4374 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4375 assert(VM_Version::supports_avx(), "");
4376 if (VM_Version::supports_avx512dq()) {
4377 emit_vex_arith_q(0x57, dst, nds, src, VEX_SIMD_66, vector_len);
4378 } else {
4379 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ true);
4380 }
4381 }
4382
4383 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4384 assert(VM_Version::supports_avx(), "");
4385 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_dq);
4386 }
4387
4388 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4389 assert(VM_Version::supports_avx(), "");
4390 if (VM_Version::supports_avx512dq()) {
4391 _tuple_type = EVEX_FV;
4392 _input_size_in_bits = EVEX_64bit;
4393 emit_vex_arith_q(0x57, dst, nds, src, VEX_SIMD_66, vector_len);
4394 } else {
4395 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ true);
4396 }
4397 }
4398
4399 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4400 assert(VM_Version::supports_avx(), "");
4401 if (VM_Version::supports_evex()) {
4402 _tuple_type = EVEX_FV;
4403 _input_size_in_bits = EVEX_32bit;
4404 }
4405 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_dq);
4406 }
4407
4408 // Integer vector arithmetic
4409 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4410 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4411 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4412 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_38, /* legacy_mode */ true);
4413 emit_int8(0x01);
4414 emit_int8((unsigned char)(0xC0 | encode));
4415 }
4416
4417 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4418 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4419 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4420 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_38, /* legacy_mode */ true);
4421 emit_int8(0x02);
4422 emit_int8((unsigned char)(0xC0 | encode));
4423 }
4424
4425 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
4426 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4427 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4428 }
4429
4430 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
4431 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4432 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4433 }
4434
4435 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
4436 _instruction_uses_vl = true;
4437 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4438 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66);
4439 }
4440
4441 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
4442 _instruction_uses_vl = true;
4443 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4444 if (VM_Version::supports_evex()) {
4445 emit_simd_arith_q(0xD4, dst, src, VEX_SIMD_66);
4446 } else {
4447 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66);
4448 }
4449 }
4450
4451 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
4452 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4453 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
4454 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
4455 emit_int8(0x01);
4456 emit_int8((unsigned char)(0xC0 | encode));
4457 }
4458
4459 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
4460 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4461 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
4462 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
4463 emit_int8(0x02);
4464 emit_int8((unsigned char)(0xC0 | encode));
4465 }
4466
4467 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4468 assert(UseAVX > 0, "requires some form of AVX");
4469 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4470 }
4471
4472 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4473 assert(UseAVX > 0, "requires some form of AVX");
4474 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4475 }
4476
4477 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4478 _instruction_uses_vl = true;
4479 assert(UseAVX > 0, "requires some form of AVX");
4480 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector_len);
4481 }
4482
4483 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4484 _instruction_uses_vl = true;
4485 assert(UseAVX > 0, "requires some form of AVX");
4486 if (VM_Version::supports_evex()) {
4487 emit_vex_arith_q(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4488 } else {
4489 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4490 }
4491 }
4492
4493 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4494 assert(UseAVX > 0, "requires some form of AVX");
4495 if (VM_Version::supports_evex()) {
4496 _tuple_type = EVEX_FVM;
4497 }
4498 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4499 }
4500
4501 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4502 assert(UseAVX > 0, "requires some form of AVX");
4503 if (VM_Version::supports_evex()) {
4504 _tuple_type = EVEX_FVM;
4505 }
4506 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4507 }
4508
4509 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4510 _instruction_uses_vl = true;
4511 assert(UseAVX > 0, "requires some form of AVX");
4512 if (VM_Version::supports_evex()) {
4513 _tuple_type = EVEX_FV;
4514 _input_size_in_bits = EVEX_32bit;
4515 }
4516 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector_len);
4517 }
4518
4519 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4520 _instruction_uses_vl = true;
4521 assert(UseAVX > 0, "requires some form of AVX");
4522 if (VM_Version::supports_evex()) {
4523 _tuple_type = EVEX_FV;
4524 _input_size_in_bits = EVEX_64bit;
4525 emit_vex_arith_q(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4526 } else {
4527 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4528 }
4529 }
4530
4531 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
4532 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4533 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4534 }
4535
4536 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
4537 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4538 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4539 }
4540
4541 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
4542 _instruction_uses_vl = true;
4543 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4544 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66);
4545 }
4546
4547 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
4548 _instruction_uses_vl = true;
4549 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4550 if (VM_Version::supports_evex()) {
4551 emit_simd_arith_q(0xFB, dst, src, VEX_SIMD_66);
4552 } else {
4553 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66);
4554 }
4555 }
4556
4557 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4558 assert(UseAVX > 0, "requires some form of AVX");
4559 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4560 }
4561
4562 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4563 assert(UseAVX > 0, "requires some form of AVX");
4564 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4565 }
4566
4567 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4568 _instruction_uses_vl = true;
4569 assert(UseAVX > 0, "requires some form of AVX");
4570 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector_len);
4571 }
4572
4573 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4574 _instruction_uses_vl = true;
4575 assert(UseAVX > 0, "requires some form of AVX");
4576 if (VM_Version::supports_evex()) {
4577 emit_vex_arith_q(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4578 } else {
4579 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4580 }
4581 }
4582
4583 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4584 assert(UseAVX > 0, "requires some form of AVX");
4585 if (VM_Version::supports_evex()) {
4586 _tuple_type = EVEX_FVM;
4587 }
4588 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4589 }
4590
4591 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4592 assert(UseAVX > 0, "requires some form of AVX");
4593 if (VM_Version::supports_evex()) {
4594 _tuple_type = EVEX_FVM;
4595 }
4596 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4597 }
4598
4599 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4600 _instruction_uses_vl = true;
4601 assert(UseAVX > 0, "requires some form of AVX");
4602 if (VM_Version::supports_evex()) {
4603 _tuple_type = EVEX_FV;
4604 _input_size_in_bits = EVEX_32bit;
4605 }
4606 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector_len);
4607 }
4608
4609 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4610 _instruction_uses_vl = true;
4611 assert(UseAVX > 0, "requires some form of AVX");
4612 if (VM_Version::supports_evex()) {
4613 _tuple_type = EVEX_FV;
4614 _input_size_in_bits = EVEX_64bit;
4615 emit_vex_arith_q(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4616 } else {
4617 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4618 }
4619 }
4620
4621 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
4622 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4623 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4624 }
4625
4626 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
4627 _instruction_uses_vl = true;
4628 assert(VM_Version::supports_sse4_1(), "");
4629 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66,
4630 /* no_mask_reg */ false, VEX_OPCODE_0F_38);
4631 emit_int8(0x40);
4632 emit_int8((unsigned char)(0xC0 | encode));
4633 }
4634
4635 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4636 assert(UseAVX > 0, "requires some form of AVX");
4637 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4638 }
4639
4640 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4641 _instruction_uses_vl = true;
4642 assert(UseAVX > 0, "requires some form of AVX");
4643 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_38);
4644 emit_int8(0x40);
4645 emit_int8((unsigned char)(0xC0 | encode));
4646 }
4647
4648 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4649 assert(UseAVX > 2, "requires some form of AVX");
4650 int src_enc = src->encoding();
4651 int dst_enc = dst->encoding();
4652 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4653 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_38,
4654 /* vex_w */ true, vector_len, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false);
4655 emit_int8(0x40);
4656 emit_int8((unsigned char)(0xC0 | encode));
4657 }
4658
4659 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4660 assert(UseAVX > 0, "requires some form of AVX");
4661 if (VM_Version::supports_evex()) {
4662 _tuple_type = EVEX_FVM;
4663 }
4664 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4665 }
4666
4667 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4668 _instruction_uses_vl = true;
4669 assert(UseAVX > 0, "requires some form of AVX");
4670 if (VM_Version::supports_evex()) {
4671 _tuple_type = EVEX_FV;
4672 _input_size_in_bits = EVEX_32bit;
4673 }
4674 InstructionMark im(this);
4675 int dst_enc = dst->encoding();
4676 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4677 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66,
4678 VEX_OPCODE_0F_38, /* vex_w */ false, vector_len);
4679 emit_int8(0x40);
4680 emit_operand(dst, src);
4681 }
4682
4683 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4684 assert(UseAVX > 0, "requires some form of AVX");
4685 if (VM_Version::supports_evex()) {
4686 _tuple_type = EVEX_FV;
4687 _input_size_in_bits = EVEX_64bit;
4688 }
4689 InstructionMark im(this);
4690 int dst_enc = dst->encoding();
4691 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4692 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66,
4693 VEX_OPCODE_0F_38, /* vex_w */ true, vector_len, /* legacy_mode */ _legacy_mode_dq);
4694 emit_int8(0x40);
4695 emit_operand(dst, src);
4696 }
4697
4698 // Shift packed integers left by specified number of bits.
4699 void Assembler::psllw(XMMRegister dst, int shift) {
4700 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4701 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
4702 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, /* no_mask_reg */ false, VEX_OPCODE_0F,
4703 /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
4704 emit_int8(0x71);
4705 emit_int8((unsigned char)(0xC0 | encode));
4706 emit_int8(shift & 0xFF);
4707 }
4708
4709 void Assembler::pslld(XMMRegister dst, int shift) {
4710 _instruction_uses_vl = true;
4711 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4712 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
4713 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, /* no_mask_reg */ false);
4714 emit_int8(0x72);
4715 emit_int8((unsigned char)(0xC0 | encode));
4716 emit_int8(shift & 0xFF);
4717 }
4718
4719 void Assembler::psllq(XMMRegister dst, int shift) {
4720 _instruction_uses_vl = true;
4721 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4722 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
4723 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, /* no_mask_reg */ false, VEX_OPCODE_0F, /* rex_w */ true);
4724 emit_int8(0x73);
4725 emit_int8((unsigned char)(0xC0 | encode));
4726 emit_int8(shift & 0xFF);
4727 }
4728
4729 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
4730 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4731 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4732 }
4733
4734 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
4735 _instruction_uses_vl = true;
4736 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4737 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66);
4738 }
4739
4740 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
4741 _instruction_uses_vl = true;
4742 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4743 if (VM_Version::supports_evex()) {
4744 emit_simd_arith_q(0xF3, dst, shift, VEX_SIMD_66);
4745 } else {
4746 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66);
4747 }
4748 }
4749
4750 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4751 assert(UseAVX > 0, "requires some form of AVX");
4752 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
4753 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4754 emit_int8(shift & 0xFF);
4755 }
4756
4757 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4758 _instruction_uses_vl = true;
4759 assert(UseAVX > 0, "requires some form of AVX");
4760 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
4761 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector_len);
4762 emit_int8(shift & 0xFF);
4763 }
4764
4765 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4766 _instruction_uses_vl = true;
4767 assert(UseAVX > 0, "requires some form of AVX");
4768 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
4769 if (VM_Version::supports_evex()) {
4770 emit_vex_arith_q(0x73, xmm6, dst, src, VEX_SIMD_66, vector_len);
4771 } else {
4772 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector_len);
4773 }
4774 emit_int8(shift & 0xFF);
4775 }
4776
4777 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4778 assert(UseAVX > 0, "requires some form of AVX");
4779 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4780 }
4781
4782 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4783 _instruction_uses_vl = true;
4784 assert(UseAVX > 0, "requires some form of AVX");
4785 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector_len);
4786 }
4787
4788 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4789 _instruction_uses_vl = true;
4790 assert(UseAVX > 0, "requires some form of AVX");
4791 if (VM_Version::supports_evex()) {
4792 emit_vex_arith_q(0xF3, dst, src, shift, VEX_SIMD_66, vector_len);
4793 } else {
4794 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector_len);
4795 }
4796 }
4797
4798 // Shift packed integers logically right by specified number of bits.
4799 void Assembler::psrlw(XMMRegister dst, int shift) {
4800 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4801 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
4802 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, /* no_mask_reg */ false,
4803 VEX_OPCODE_0F, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
4804 emit_int8(0x71);
4805 emit_int8((unsigned char)(0xC0 | encode));
4806 emit_int8(shift & 0xFF);
4807 }
4808
4809 void Assembler::psrld(XMMRegister dst, int shift) {
4810 _instruction_uses_vl = true;
4811 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4812 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
4813 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, /* no_mask_reg */ false);
4814 emit_int8(0x72);
4815 emit_int8((unsigned char)(0xC0 | encode));
4816 emit_int8(shift & 0xFF);
4817 }
4818
4819 void Assembler::psrlq(XMMRegister dst, int shift) {
4820 _instruction_uses_vl = true;
4821 // Do not confuse it with psrldq SSE2 instruction which
4822 // shifts 128 bit value in xmm register by number of bytes.
4823 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4824 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4825 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, /* no_mask_reg */ false,
4826 VEX_OPCODE_0F, /* rex_w */ VM_Version::supports_evex());
4827 emit_int8(0x73);
4828 emit_int8((unsigned char)(0xC0 | encode));
4829 emit_int8(shift & 0xFF);
4830 }
4831
4832 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
4833 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4834 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4835 }
4836
4837 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
4838 _instruction_uses_vl = true;
4839 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4840 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66);
4841 }
4842
4843 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
4844 _instruction_uses_vl = true;
4845 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4846 if (VM_Version::supports_evex()) {
4847 emit_simd_arith_q(0xD3, dst, shift, VEX_SIMD_66);
4848 } else {
4849 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66);
4850 }
4851 }
4852
4853 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4854 assert(UseAVX > 0, "requires some form of AVX");
4855 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
4856 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4857 emit_int8(shift & 0xFF);
4858 }
4859
4860 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4861 _instruction_uses_vl = true;
4862 assert(UseAVX > 0, "requires some form of AVX");
4863 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
4864 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector_len);
4865 emit_int8(shift & 0xFF);
4866 }
4867
4868 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4869 _instruction_uses_vl = true;
4870 assert(UseAVX > 0, "requires some form of AVX");
4871 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4872 if (VM_Version::supports_evex()) {
4873 emit_vex_arith_q(0x73, xmm2, dst, src, VEX_SIMD_66, vector_len);
4874 } else {
4875 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector_len);
4876 }
4877 emit_int8(shift & 0xFF);
4878 }
4879
4880 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4881 assert(UseAVX > 0, "requires some form of AVX");
4882 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4883 }
4884
4885 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4886 _instruction_uses_vl = true;
4887 assert(UseAVX > 0, "requires some form of AVX");
4888 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector_len);
4889 }
4890
4891 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4892 _instruction_uses_vl = true;
4893 assert(UseAVX > 0, "requires some form of AVX");
4894 if (VM_Version::supports_evex()) {
4895 emit_vex_arith_q(0xD3, dst, src, shift, VEX_SIMD_66, vector_len);
4896 } else {
4897 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector_len);
4898 }
4899 }
4900
4901 // Shift packed integers arithmetically right by specified number of bits.
4902 void Assembler::psraw(XMMRegister dst, int shift) {
4903 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4904 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4905 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, /* no_mask_reg */ false,
4906 VEX_OPCODE_0F, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
4907 emit_int8(0x71);
4908 emit_int8((unsigned char)(0xC0 | encode));
4909 emit_int8(shift & 0xFF);
4910 }
4911
4912 void Assembler::psrad(XMMRegister dst, int shift) {
4913 _instruction_uses_vl = true;
4914 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4915 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
4916 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, /* no_mask_reg */ false);
4917 emit_int8(0x72);
4918 emit_int8((unsigned char)(0xC0 | encode));
4919 emit_int8(shift & 0xFF);
4920 }
4921
4922 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
4923 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4924 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4925 }
4926
4927 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
4928 _instruction_uses_vl = true;
4929 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4930 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66);
4931 }
4932
4933 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4934 assert(UseAVX > 0, "requires some form of AVX");
4935 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4936 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4937 emit_int8(shift & 0xFF);
4938 }
4939
4940 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4941 _instruction_uses_vl = true;
4942 assert(UseAVX > 0, "requires some form of AVX");
4943 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4944 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector_len);
4945 emit_int8(shift & 0xFF);
4946 }
4947
4948 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4949 assert(UseAVX > 0, "requires some form of AVX");
4950 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4951 }
4952
4953 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4954 _instruction_uses_vl = true;
4955 assert(UseAVX > 0, "requires some form of AVX");
4956 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector_len);
4957 }
4958
4959
4960 // logical operations packed integers
4961 void Assembler::pand(XMMRegister dst, XMMRegister src) {
4962 _instruction_uses_vl = true;
4963 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4964 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66);
4965 }
4966
4967 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4968 _instruction_uses_vl = true;
4969 assert(UseAVX > 0, "requires some form of AVX");
4970 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector_len);
4971 }
4972
4973 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4974 _instruction_uses_vl = true;
4975 assert(UseAVX > 0, "requires some form of AVX");
4976 if (VM_Version::supports_evex()) {
4977 _tuple_type = EVEX_FV;
4978 _input_size_in_bits = EVEX_32bit;
4979 }
4980 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector_len);
4981 }
4982
4983 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
4984 _instruction_uses_vl = true;
4985 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4986 if (VM_Version::supports_evex()) {
4987 emit_simd_arith_q(0xDF, dst, src, VEX_SIMD_66);
4988 }
4989 else {
4990 emit_simd_arith(0xDF, dst, src, VEX_SIMD_66);
4991 }
4992 }
4993
4994 void Assembler::por(XMMRegister dst, XMMRegister src) {
4995 _instruction_uses_vl = true;
4996 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4997 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66);
4998 }
4999
5000 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5001 _instruction_uses_vl = true;
5002 assert(UseAVX > 0, "requires some form of AVX");
5003 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector_len);
5004 }
5005
5006 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5007 _instruction_uses_vl = true;
5008 assert(UseAVX > 0, "requires some form of AVX");
5009 if (VM_Version::supports_evex()) {
5010 _tuple_type = EVEX_FV;
5011 _input_size_in_bits = EVEX_32bit;
5012 }
5013 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector_len);
5014 }
5015
5016 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
5017 _instruction_uses_vl = true;
5018 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5019 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66);
5020 }
5021
5022 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5023 _instruction_uses_vl = true;
5024 assert(UseAVX > 0, "requires some form of AVX");
5025 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector_len);
5026 }
5027
5028 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5029 _instruction_uses_vl = true;
5030 assert(UseAVX > 0, "requires some form of AVX");
5031 if (VM_Version::supports_evex()) {
5032 _tuple_type = EVEX_FV;
5033 _input_size_in_bits = EVEX_32bit;
5034 }
5035 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector_len);
5036 }
5037
5038
5039 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5040 assert(VM_Version::supports_avx(), "");
5041 int vector_len = AVX_256bit;
5042 if (VM_Version::supports_evex()) {
5043 vector_len = AVX_512bit;
5044 }
5045 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
5046 emit_int8(0x18);
5047 emit_int8((unsigned char)(0xC0 | encode));
5048 // 0x00 - insert into lower 128 bits
5049 // 0x01 - insert into upper 128 bits
5050 emit_int8(0x01);
5051 }
5052
5053 void Assembler::vinsertf64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5054 assert(VM_Version::supports_evex(), "");
5055 int vector_len = AVX_512bit;
5056 int src_enc = src->encoding();
5057 int dst_enc = dst->encoding();
5058 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5059 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
5060 /* vex_w */ true, vector_len, /* legacy_mode */ false, /* no_mask_reg */ false);
5061 emit_int8(0x1A);
5062 emit_int8((unsigned char)(0xC0 | encode));
5063 // 0x00 - insert into lower 256 bits
5064 // 0x01 - insert into upper 256 bits
5065 emit_int8(0x01);
5066 }
5067
5068 void Assembler::vinsertf64x4h(XMMRegister dst, Address src) {
5069 assert(VM_Version::supports_evex(), "");
5070 _tuple_type = EVEX_T4;
5071 _input_size_in_bits = EVEX_64bit;
5072 InstructionMark im(this);
5073 int vector_len = AVX_512bit;
5074 assert(dst != xnoreg, "sanity");
5075 int dst_enc = dst->encoding();
5076 // swap src<->dst for encoding
5077 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, /* vex_w */ true, vector_len);
5078 emit_int8(0x1A);
5079 emit_operand(dst, src);
5080 // 0x01 - insert into upper 128 bits
5081 emit_int8(0x01);
5082 }
5083
5084 void Assembler::vinsertf32x4h(XMMRegister dst, XMMRegister nds, XMMRegister src, int value) {
5085 assert(VM_Version::supports_evex(), "");
5086 int vector_len = AVX_512bit;
5087 int src_enc = src->encoding();
5088 int dst_enc = dst->encoding();
5089 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5090 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
5091 /* vex_w */ false, vector_len, /* legacy_mode */ false, /* no_mask_reg */ false);
5092 emit_int8(0x18);
5093 emit_int8((unsigned char)(0xC0 | encode));
5094 // 0x00 - insert into q0 128 bits (0..127)
5095 // 0x01 - insert into q1 128 bits (128..255)
5096 // 0x02 - insert into q2 128 bits (256..383)
5097 // 0x03 - insert into q3 128 bits (384..511)
5098 emit_int8(value & 0x3);
5099 }
5100
5101 void Assembler::vinsertf32x4h(XMMRegister dst, Address src, int value) {
5102 assert(VM_Version::supports_evex(), "");
5103 _tuple_type = EVEX_T4;
5104 _input_size_in_bits = EVEX_32bit;
5105 InstructionMark im(this);
5106 int vector_len = AVX_512bit;
5107 assert(dst != xnoreg, "sanity");
5108 int dst_enc = dst->encoding();
5109 // swap src<->dst for encoding
5110 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, /* vex_w */ false, vector_len);
5111 emit_int8(0x18);
5112 emit_operand(dst, src);
5113 // 0x00 - insert into q0 128 bits (0..127)
5114 // 0x01 - insert into q1 128 bits (128..255)
5115 // 0x02 - insert into q2 128 bits (256..383)
5116 // 0x03 - insert into q3 128 bits (384..511)
5117 emit_int8(value & 0x3);
5118 }
5119
5120 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
5121 assert(VM_Version::supports_avx(), "");
5122 int vector_len = AVX_256bit;
5123 if (VM_Version::supports_evex()) {
5124 _tuple_type = EVEX_T4;
5125 _input_size_in_bits = EVEX_32bit;
5126 vector_len = AVX_512bit;
5127 }
5128 InstructionMark im(this);
5129 assert(dst != xnoreg, "sanity");
5130 int dst_enc = dst->encoding();
5131 // swap src<->dst for encoding
5132 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, /* vex_w */ false, vector_len);
5133 emit_int8(0x18);
5134 emit_operand(dst, src);
5135 // 0x01 - insert into upper 128 bits
5136 emit_int8(0x01);
5137 }
5138
5139 void Assembler::vextractf128h(XMMRegister dst, XMMRegister src) {
5140 assert(VM_Version::supports_avx(), "");
5141 int vector_len = AVX_256bit;
5142 if (VM_Version::supports_evex()) {
5143 vector_len = AVX_512bit;
5144 }
5145 int encode = vex_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
5146 emit_int8(0x19);
5147 emit_int8((unsigned char)(0xC0 | encode));
5148 // 0x00 - insert into lower 128 bits
5149 // 0x01 - insert into upper 128 bits
5150 emit_int8(0x01);
5151 }
5152
5153 void Assembler::vextractf128h(Address dst, XMMRegister src) {
5154 assert(VM_Version::supports_avx(), "");
5155 int vector_len = AVX_256bit;
5156 if (VM_Version::supports_evex()) {
5157 _tuple_type = EVEX_T4;
5158 _input_size_in_bits = EVEX_32bit;
5159 vector_len = AVX_512bit;
5160 }
5161 InstructionMark im(this);
5162 assert(src != xnoreg, "sanity");
5163 int src_enc = src->encoding();
5164 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, /* vex_w */ false, vector_len);
5165 emit_int8(0x19);
5166 emit_operand(src, dst);
5167 // 0x01 - extract from upper 128 bits
5168 emit_int8(0x01);
5169 }
5170
5171 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5172 assert(VM_Version::supports_avx2(), "");
5173 int vector_len = AVX_256bit;
5174 if (VM_Version::supports_evex()) {
5175 vector_len = AVX_512bit;
5176 }
5177 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
5178 emit_int8(0x38);
5179 emit_int8((unsigned char)(0xC0 | encode));
5180 // 0x00 - insert into lower 128 bits
5181 // 0x01 - insert into upper 128 bits
5182 emit_int8(0x01);
5183 }
5184
5185 void Assembler::vinserti64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5186 assert(VM_Version::supports_evex(), "");
5187 int vector_len = AVX_512bit;
5188 int src_enc = src->encoding();
5189 int dst_enc = dst->encoding();
5190 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5191 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
5192 /* vex_w */ true, vector_len, /* legacy_mode */ false, /* no_reg_mask */ false);
5193 emit_int8(0x38);
5194 emit_int8((unsigned char)(0xC0 | encode));
5195 // 0x00 - insert into lower 256 bits
5196 // 0x01 - insert into upper 256 bits
5197 emit_int8(0x01);
5198 }
5199
5200 void Assembler::vinserti128h(XMMRegister dst, Address src) {
5201 assert(VM_Version::supports_avx2(), "");
5202 int vector_len = AVX_256bit;
5203 if (VM_Version::supports_evex()) {
5204 _tuple_type = EVEX_T4;
5205 _input_size_in_bits = EVEX_32bit;
5206 vector_len = AVX_512bit;
5207 }
5208 InstructionMark im(this);
5209 assert(dst != xnoreg, "sanity");
5210 int dst_enc = dst->encoding();
5211 // swap src<->dst for encoding
5212 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, /* vex_w */ false, vector_len);
5213 emit_int8(0x38);
5214 emit_operand(dst, src);
5215 // 0x01 - insert into upper 128 bits
5216 emit_int8(0x01);
5217 }
5218
5219 void Assembler::vextracti128h(XMMRegister dst, XMMRegister src) {
5220 assert(VM_Version::supports_avx(), "");
5221 int vector_len = AVX_256bit;
5222 if (VM_Version::supports_evex()) {
5223 vector_len = AVX_512bit;
5224 }
5225 int encode = vex_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
5226 emit_int8(0x39);
5227 emit_int8((unsigned char)(0xC0 | encode));
5228 // 0x00 - insert into lower 128 bits
5229 // 0x01 - insert into upper 128 bits
5230 emit_int8(0x01);
5231 }
5232
5233 void Assembler::vextracti128h(Address dst, XMMRegister src) {
5234 assert(VM_Version::supports_avx2(), "");
5235 int vector_len = AVX_256bit;
5236 if (VM_Version::supports_evex()) {
5237 _tuple_type = EVEX_T4;
5238 _input_size_in_bits = EVEX_32bit;
5239 vector_len = AVX_512bit;
5240 }
5241 InstructionMark im(this);
5242 assert(src != xnoreg, "sanity");
5243 int src_enc = src->encoding();
5244 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, /* vex_w */ false, vector_len);
5245 emit_int8(0x39);
5246 emit_operand(src, dst);
5247 // 0x01 - extract from upper 128 bits
5248 emit_int8(0x01);
5249 }
5250
5251 void Assembler::vextracti64x4h(XMMRegister dst, XMMRegister src) {
5252 assert(VM_Version::supports_evex(), "");
5253 int vector_len = AVX_512bit;
5254 int src_enc = src->encoding();
5255 int dst_enc = dst->encoding();
5256 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
5257 /* vex_w */ true, vector_len, /* legacy_mode */ false, /* no_mask_reg */ false);
5258 emit_int8(0x3B);
5259 emit_int8((unsigned char)(0xC0 | encode));
5260 // 0x01 - extract from upper 256 bits
5261 emit_int8(0x01);
5262 }
5263
5264 void Assembler::vextracti64x2h(XMMRegister dst, XMMRegister src, int value) {
5265 assert(VM_Version::supports_evex(), "");
5266 int vector_len = AVX_512bit;
5267 int src_enc = src->encoding();
5268 int dst_enc = dst->encoding();
5269 int encode;
5270 if (VM_Version::supports_avx512dq()) {
5271 encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
5272 /* vex_w */ true, vector_len, /* legacy_mode */ false, /* no_mask_reg */ false);
5273 } else {
5274 encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
5275 /* vex_w */ false, vector_len, /* legacy_mode */ true, /* no_mask_reg */ false);
5276 }
5277 emit_int8(0x39);
5278 emit_int8((unsigned char)(0xC0 | encode));
5279 // 0x01 - extract from bits 255:128
5280 // 0x02 - extract from bits 383:256
5281 // 0x03 - extract from bits 511:384
5282 emit_int8(value & 0x3);
5283 }
5284
5285 void Assembler::vextractf64x4h(XMMRegister dst, XMMRegister src) {
5286 assert(VM_Version::supports_evex(), "");
5287 int vector_len = AVX_512bit;
5288 int src_enc = src->encoding();
5289 int dst_enc = dst->encoding();
5290 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
5291 /* vex_w */ true, vector_len, /* legacy_mode */ false, /* no_mask_reg */ false);
5292 emit_int8(0x1B);
5293 emit_int8((unsigned char)(0xC0 | encode));
5294 // 0x01 - extract from upper 256 bits
5295 emit_int8(0x01);
5296 }
5297
5298 void Assembler::vextractf64x4h(Address dst, XMMRegister src) {
5299 assert(VM_Version::supports_evex(), "");
5300 _tuple_type = EVEX_T4;
5301 _input_size_in_bits = EVEX_64bit;
5302 InstructionMark im(this);
5303 int vector_len = AVX_512bit;
5304 assert(src != xnoreg, "sanity");
5305 int src_enc = src->encoding();
5306 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
5307 /* vex_w */ true, vector_len);
5308 emit_int8(0x1B);
5309 emit_operand(src, dst);
5310 // 0x01 - extract from upper 256 bits
5311 emit_int8(0x01);
5312 }
5313
5314 void Assembler::vextractf32x4h(XMMRegister dst, XMMRegister src, int value) {
5315 assert(VM_Version::supports_evex(), "");
5316 int vector_len = AVX_512bit;
5317 int src_enc = src->encoding();
5318 int dst_enc = dst->encoding();
5319 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
5320 /* vex_w */ false, vector_len, /* legacy_mode */ false, /* no_mask_reg */ false);
5321 emit_int8(0x19);
5322 emit_int8((unsigned char)(0xC0 | encode));
5323 // 0x00 - extract from bits 127:0
5324 // 0x01 - extract from bits 255:128
5325 // 0x02 - extract from bits 383:256
5326 // 0x03 - extract from bits 511:384
5327 emit_int8(value & 0x3);
5328 }
5329
5330 void Assembler::vextractf32x4h(Address dst, XMMRegister src, int value) {
5331 assert(VM_Version::supports_evex(), "");
5332 _tuple_type = EVEX_T4;
5333 _input_size_in_bits = EVEX_32bit;
5334 InstructionMark im(this);
5335 int vector_len = AVX_512bit;
5336 assert(src != xnoreg, "sanity");
5337 int src_enc = src->encoding();
5338 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, /* vex_w */ false, vector_len);
5339 emit_int8(0x19);
5340 emit_operand(src, dst);
5341 // 0x00 - extract from bits 127:0
5342 // 0x01 - extract from bits 255:128
5343 // 0x02 - extract from bits 383:256
5344 // 0x03 - extract from bits 511:384
5345 emit_int8(value & 0x3);
5346 }
5347
5348 void Assembler::vextractf64x2h(XMMRegister dst, XMMRegister src, int value) {
5349 assert(VM_Version::supports_evex(), "");
5350 int vector_len = AVX_512bit;
5351 int src_enc = src->encoding();
5352 int dst_enc = dst->encoding();
5353 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
5354 /* vex_w */ !_legacy_mode_dq, vector_len, /* legacy_mode */ false, /* no_mask_reg */ false);
5355 emit_int8(0x19);
5356 emit_int8((unsigned char)(0xC0 | encode));
5357 // 0x01 - extract from bits 255:128
5358 // 0x02 - extract from bits 383:256
5359 // 0x03 - extract from bits 511:384
5360 emit_int8(value & 0x3);
5361 }
5362
5363 // duplicate 4-bytes integer data from src into 8 locations in dest
5364 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
5365 _instruction_uses_vl = true;
5366 assert(UseAVX > 1, "");
5367 int vector_len = AVX_256bit;
5368 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_38);
5369 emit_int8(0x58);
5370 emit_int8((unsigned char)(0xC0 | encode));
5371 }
5372
5373 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
5374 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
5375 _instruction_uses_vl = true;
5376 assert(UseAVX > 1, "");
5377 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_38);
5378 emit_int8(0x78);
5379 emit_int8((unsigned char)(0xC0 | encode));
5380 }
5381
5382 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
5383 _instruction_uses_vl = true;
5384 assert(UseAVX > 1, "");
5385 _tuple_type = EVEX_T1S;
5386 _input_size_in_bits = EVEX_8bit;
5387 InstructionMark im(this);
5388 assert(dst != xnoreg, "sanity");
5389 int dst_enc = dst->encoding();
5390 // swap src<->dst for encoding
5391 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, /* vex_w */ false, vector_len);
5392 emit_int8(0x78);
5393 emit_operand(dst, src);
5394 }
5395
5396 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
5397 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
5398 _instruction_uses_vl = true;
5399 assert(UseAVX > 1, "");
5400 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_38);
5401 emit_int8(0x79);
5402 emit_int8((unsigned char)(0xC0 | encode));
5403 }
5404
5405 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
5406 _instruction_uses_vl = true;
5407 assert(UseAVX > 1, "");
5408 _tuple_type = EVEX_T1S;
5409 _input_size_in_bits = EVEX_16bit;
5410 InstructionMark im(this);
5411 assert(dst != xnoreg, "sanity");
5412 int dst_enc = dst->encoding();
5413 // swap src<->dst for encoding
5414 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, /* vex_w */ false, vector_len);
5415 emit_int8(0x79);
5416 emit_operand(dst, src);
5417 }
5418
5419 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5420 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
5421 _instruction_uses_vl = true;
5422 assert(UseAVX > 1, "");
5423 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_38);
5424 emit_int8(0x58);
5425 emit_int8((unsigned char)(0xC0 | encode));
5426 }
5427
5428 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
5429 _instruction_uses_vl = true;
5430 assert(UseAVX > 1, "");
5431 _tuple_type = EVEX_T1S;
5432 _input_size_in_bits = EVEX_32bit;
5433 InstructionMark im(this);
5434 assert(dst != xnoreg, "sanity");
5435 int dst_enc = dst->encoding();
5436 // swap src<->dst for encoding
5437 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, /* vex_w */ false, vector_len);
5438 emit_int8(0x58);
5439 emit_operand(dst, src);
5440 }
5441
5442 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5443 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
5444 _instruction_uses_vl = true;
5445 assert(UseAVX > 1, "");
5446 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38,
5447 /* vex_w */ true, vector_len, /* legacy_mode */ false, /* no_mask_reg */ false);
5448 emit_int8(0x59);
5449 emit_int8((unsigned char)(0xC0 | encode));
5450 }
5451
5452 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
5453 _instruction_uses_vl = true;
5454 assert(UseAVX > 1, "");
5455 _tuple_type = EVEX_T1S;
5456 _input_size_in_bits = EVEX_64bit;
5457 InstructionMark im(this);
5458 assert(dst != xnoreg, "sanity");
5459 int dst_enc = dst->encoding();
5460 // swap src<->dst for encoding
5461 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, /* vex_w */ true, vector_len);
5462 emit_int8(0x59);
5463 emit_operand(dst, src);
5464 }
5465
5466 // duplicate single precision fp from src into 4|8|16 locations in dest : requires AVX512VL
5467 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
5468 _instruction_uses_vl = true;
5469 assert(UseAVX > 1, "");
5470 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38,
5471 /* vex_w */ false, vector_len, /* legacy_mode */ false, /*no_mask_reg */ false);
5472 emit_int8(0x18);
5473 emit_int8((unsigned char)(0xC0 | encode));
5474 }
5475
5476 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
5477 assert(UseAVX > 1, "");
5478 _tuple_type = EVEX_T1S;
5479 _input_size_in_bits = EVEX_32bit;
5480 InstructionMark im(this);
5481 assert(dst != xnoreg, "sanity");
5482 int dst_enc = dst->encoding();
5483 // swap src<->dst for encoding
5484 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, /* vex_w */ false, vector_len);
5485 emit_int8(0x18);
5486 emit_operand(dst, src);
5487 }
5488
5489 // duplicate double precision fp from src into 2|4|8 locations in dest : requires AVX512VL
5490 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
5491 _instruction_uses_vl = true;
5492 assert(UseAVX > 1, "");
5493 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38,
5494 /*vex_w */ true, vector_len, /* legacy_mode */ false, /*no_mask_reg */ false);
5495 emit_int8(0x19);
5496 emit_int8((unsigned char)(0xC0 | encode));
5497 }
5498
5499 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
5500 _instruction_uses_vl = true;
5501 assert(UseAVX > 1, "");
5502 _tuple_type = EVEX_T1S;
5503 _input_size_in_bits = EVEX_64bit;
5504 InstructionMark im(this);
5505 assert(dst != xnoreg, "sanity");
5506 int dst_enc = dst->encoding();
5507 // swap src<->dst for encoding
5508 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, /* vex_w */ true, vector_len);
5509 emit_int8(0x19);
5510 emit_operand(dst, src);
5511 }
5512
5513 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
5514 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
5515 _instruction_uses_vl = true;
5516 assert(VM_Version::supports_evex(), "");
5517 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38,
5518 /*vex_w */ false, vector_len, /* legacy_mode */ false, /*no_mask_reg */ false);
5519 emit_int8(0x7A);
5520 emit_int8((unsigned char)(0xC0 | encode));
5521 }
5522
5523 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
5524 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
5525 _instruction_uses_vl = true;
5526 assert(VM_Version::supports_evex(), "");
5527 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38,
5528 /* vex_w */ false, vector_len, /* legacy_mode */ false, /*no_mask_reg */ false);
5529 emit_int8(0x7B);
5530 emit_int8((unsigned char)(0xC0 | encode));
5531 }
5532
5533 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5534 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
5535 _instruction_uses_vl = true;
5536 assert(VM_Version::supports_evex(), "");
5537 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38,
5538 /* vex_w */ false, vector_len, /* legacy_mode */ false, /*no_mask_reg */ false);
5539 emit_int8(0x7C);
5540 emit_int8((unsigned char)(0xC0 | encode));
5541 }
5542
5543 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5544 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
5545 _instruction_uses_vl = true;
5546 assert(VM_Version::supports_evex(), "");
5547 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38,
5548 /* vex_w */ true, vector_len, /* legacy_mode */ false, /*no_mask_reg */ false);
5549 emit_int8(0x7C);
5550 emit_int8((unsigned char)(0xC0 | encode));
5551 }
5552
5553 // Carry-Less Multiplication Quadword
5554 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
5555 assert(VM_Version::supports_clmul(), "");
5556 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
5557 VEX_OPCODE_0F_3A, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
5558 emit_int8(0x44);
5559 emit_int8((unsigned char)(0xC0 | encode));
5560 emit_int8((unsigned char)mask);
5561 }
5562
5563 // Carry-Less Multiplication Quadword
5564 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
5565 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
5566 int vector_len = AVX_128bit;
5567 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A, /* legacy_mode */ true);
5568 emit_int8(0x44);
5569 emit_int8((unsigned char)(0xC0 | encode));
5570 emit_int8((unsigned char)mask);
5571 }
5572
5573 void Assembler::vzeroupper() {
5574 assert(VM_Version::supports_avx(), "");
5575 if (UseAVX < 3)
5576 {
5577 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
5578 emit_int8(0x77);
5579 }
5580 }
5581
5582
5583 #ifndef _LP64
5584 // 32bit only pieces of the assembler
5585
5586 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
5587 // NO PREFIX AS NEVER 64BIT
5588 InstructionMark im(this);
5589 emit_int8((unsigned char)0x81);
5590 emit_int8((unsigned char)(0xF8 | src1->encoding()));
5591 emit_data(imm32, rspec, 0);
5592 }
5593
5594 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
5595 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
5596 InstructionMark im(this);
5597 emit_int8((unsigned char)0x81);
5598 emit_operand(rdi, src1);
5599 emit_data(imm32, rspec, 0);
5600 }
5601
5602 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
5603 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
5604 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
5605 void Assembler::cmpxchg8(Address adr) {
5606 InstructionMark im(this);
5607 emit_int8(0x0F);
5608 emit_int8((unsigned char)0xC7);
5609 emit_operand(rcx, adr);
5610 }
5611
5612 void Assembler::decl(Register dst) {
5613 // Don't use it directly. Use MacroAssembler::decrementl() instead.
5614 emit_int8(0x48 | dst->encoding());
5615 }
5616
5617 #endif // _LP64
5618
5619 // 64bit typically doesn't use the x87 but needs to for the trig funcs
5620
5621 void Assembler::fabs() {
5622 emit_int8((unsigned char)0xD9);
5623 emit_int8((unsigned char)0xE1);
5624 }
5625
5626 void Assembler::fadd(int i) {
5627 emit_farith(0xD8, 0xC0, i);
5628 }
5629
5630 void Assembler::fadd_d(Address src) {
5631 InstructionMark im(this);
5632 emit_int8((unsigned char)0xDC);
5633 emit_operand32(rax, src);
5634 }
5635
5636 void Assembler::fadd_s(Address src) {
5637 InstructionMark im(this);
5638 emit_int8((unsigned char)0xD8);
5639 emit_operand32(rax, src);
5640 }
5641
5642 void Assembler::fadda(int i) {
5643 emit_farith(0xDC, 0xC0, i);
5644 }
5645
5646 void Assembler::faddp(int i) {
5647 emit_farith(0xDE, 0xC0, i);
5648 }
5649
5650 void Assembler::fchs() {
5651 emit_int8((unsigned char)0xD9);
5652 emit_int8((unsigned char)0xE0);
5653 }
5654
5655 void Assembler::fcom(int i) {
5656 emit_farith(0xD8, 0xD0, i);
5657 }
5658
5659 void Assembler::fcomp(int i) {
5660 emit_farith(0xD8, 0xD8, i);
5661 }
5662
5663 void Assembler::fcomp_d(Address src) {
5664 InstructionMark im(this);
5665 emit_int8((unsigned char)0xDC);
5666 emit_operand32(rbx, src);
5667 }
5668
5669 void Assembler::fcomp_s(Address src) {
5670 InstructionMark im(this);
5671 emit_int8((unsigned char)0xD8);
5672 emit_operand32(rbx, src);
5673 }
5674
5675 void Assembler::fcompp() {
5676 emit_int8((unsigned char)0xDE);
5677 emit_int8((unsigned char)0xD9);
5678 }
5679
5680 void Assembler::fcos() {
5681 emit_int8((unsigned char)0xD9);
5682 emit_int8((unsigned char)0xFF);
5683 }
5684
5685 void Assembler::fdecstp() {
5686 emit_int8((unsigned char)0xD9);
5687 emit_int8((unsigned char)0xF6);
5688 }
5689
5690 void Assembler::fdiv(int i) {
5691 emit_farith(0xD8, 0xF0, i);
5692 }
5693
5694 void Assembler::fdiv_d(Address src) {
5695 InstructionMark im(this);
5696 emit_int8((unsigned char)0xDC);
5697 emit_operand32(rsi, src);
5698 }
5699
5700 void Assembler::fdiv_s(Address src) {
5701 InstructionMark im(this);
5702 emit_int8((unsigned char)0xD8);
5703 emit_operand32(rsi, src);
5704 }
5705
5706 void Assembler::fdiva(int i) {
5707 emit_farith(0xDC, 0xF8, i);
5708 }
5709
5710 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
5711 // is erroneous for some of the floating-point instructions below.
5712
5713 void Assembler::fdivp(int i) {
5714 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
5715 }
5716
5717 void Assembler::fdivr(int i) {
5718 emit_farith(0xD8, 0xF8, i);
5719 }
5720
5721 void Assembler::fdivr_d(Address src) {
5722 InstructionMark im(this);
5723 emit_int8((unsigned char)0xDC);
5724 emit_operand32(rdi, src);
5725 }
5726
5727 void Assembler::fdivr_s(Address src) {
5728 InstructionMark im(this);
5729 emit_int8((unsigned char)0xD8);
5730 emit_operand32(rdi, src);
5731 }
5732
5733 void Assembler::fdivra(int i) {
5734 emit_farith(0xDC, 0xF0, i);
5735 }
5736
5737 void Assembler::fdivrp(int i) {
5738 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
5739 }
5740
5741 void Assembler::ffree(int i) {
5742 emit_farith(0xDD, 0xC0, i);
5743 }
5744
5745 void Assembler::fild_d(Address adr) {
5746 InstructionMark im(this);
5747 emit_int8((unsigned char)0xDF);
5748 emit_operand32(rbp, adr);
5749 }
5750
5751 void Assembler::fild_s(Address adr) {
5752 InstructionMark im(this);
5753 emit_int8((unsigned char)0xDB);
5754 emit_operand32(rax, adr);
5755 }
5756
5757 void Assembler::fincstp() {
5758 emit_int8((unsigned char)0xD9);
5759 emit_int8((unsigned char)0xF7);
5760 }
5761
5762 void Assembler::finit() {
5763 emit_int8((unsigned char)0x9B);
5764 emit_int8((unsigned char)0xDB);
5765 emit_int8((unsigned char)0xE3);
5766 }
5767
5768 void Assembler::fist_s(Address adr) {
5769 InstructionMark im(this);
5770 emit_int8((unsigned char)0xDB);
5771 emit_operand32(rdx, adr);
5772 }
5773
5774 void Assembler::fistp_d(Address adr) {
5775 InstructionMark im(this);
5776 emit_int8((unsigned char)0xDF);
5777 emit_operand32(rdi, adr);
5778 }
5779
5780 void Assembler::fistp_s(Address adr) {
5781 InstructionMark im(this);
5782 emit_int8((unsigned char)0xDB);
5783 emit_operand32(rbx, adr);
5784 }
5785
5786 void Assembler::fld1() {
5787 emit_int8((unsigned char)0xD9);
5788 emit_int8((unsigned char)0xE8);
5789 }
5790
5791 void Assembler::fld_d(Address adr) {
5792 InstructionMark im(this);
5793 emit_int8((unsigned char)0xDD);
5794 emit_operand32(rax, adr);
5795 }
5796
5797 void Assembler::fld_s(Address adr) {
5798 InstructionMark im(this);
5799 emit_int8((unsigned char)0xD9);
5800 emit_operand32(rax, adr);
5801 }
5802
5803
5804 void Assembler::fld_s(int index) {
5805 emit_farith(0xD9, 0xC0, index);
5806 }
5807
5808 void Assembler::fld_x(Address adr) {
5809 InstructionMark im(this);
5810 emit_int8((unsigned char)0xDB);
5811 emit_operand32(rbp, adr);
5812 }
5813
5814 void Assembler::fldcw(Address src) {
5815 InstructionMark im(this);
5816 emit_int8((unsigned char)0xD9);
5817 emit_operand32(rbp, src);
5818 }
5819
5820 void Assembler::fldenv(Address src) {
5821 InstructionMark im(this);
5822 emit_int8((unsigned char)0xD9);
5823 emit_operand32(rsp, src);
5824 }
5825
5826 void Assembler::fldlg2() {
5827 emit_int8((unsigned char)0xD9);
5828 emit_int8((unsigned char)0xEC);
5829 }
5830
5831 void Assembler::fldln2() {
5832 emit_int8((unsigned char)0xD9);
5833 emit_int8((unsigned char)0xED);
5834 }
5835
5836 void Assembler::fldz() {
5837 emit_int8((unsigned char)0xD9);
5838 emit_int8((unsigned char)0xEE);
5839 }
5840
5841 void Assembler::flog() {
5842 fldln2();
5843 fxch();
5844 fyl2x();
5845 }
5846
5847 void Assembler::flog10() {
5848 fldlg2();
5849 fxch();
5850 fyl2x();
5851 }
5852
5853 void Assembler::fmul(int i) {
5854 emit_farith(0xD8, 0xC8, i);
5855 }
5856
5857 void Assembler::fmul_d(Address src) {
5858 InstructionMark im(this);
5859 emit_int8((unsigned char)0xDC);
5860 emit_operand32(rcx, src);
5861 }
5862
5863 void Assembler::fmul_s(Address src) {
5864 InstructionMark im(this);
5865 emit_int8((unsigned char)0xD8);
5866 emit_operand32(rcx, src);
5867 }
5868
5869 void Assembler::fmula(int i) {
5870 emit_farith(0xDC, 0xC8, i);
5871 }
5872
5873 void Assembler::fmulp(int i) {
5874 emit_farith(0xDE, 0xC8, i);
5875 }
5876
5877 void Assembler::fnsave(Address dst) {
5878 InstructionMark im(this);
5879 emit_int8((unsigned char)0xDD);
5880 emit_operand32(rsi, dst);
5881 }
5882
5883 void Assembler::fnstcw(Address src) {
5884 InstructionMark im(this);
5885 emit_int8((unsigned char)0x9B);
5886 emit_int8((unsigned char)0xD9);
5887 emit_operand32(rdi, src);
5888 }
5889
5890 void Assembler::fnstsw_ax() {
5891 emit_int8((unsigned char)0xDF);
5892 emit_int8((unsigned char)0xE0);
5893 }
5894
5895 void Assembler::fprem() {
5896 emit_int8((unsigned char)0xD9);
5897 emit_int8((unsigned char)0xF8);
5898 }
5899
5900 void Assembler::fprem1() {
5901 emit_int8((unsigned char)0xD9);
5902 emit_int8((unsigned char)0xF5);
5903 }
5904
5905 void Assembler::frstor(Address src) {
5906 InstructionMark im(this);
5907 emit_int8((unsigned char)0xDD);
5908 emit_operand32(rsp, src);
5909 }
5910
5911 void Assembler::fsin() {
5912 emit_int8((unsigned char)0xD9);
5913 emit_int8((unsigned char)0xFE);
5914 }
5915
5916 void Assembler::fsqrt() {
5917 emit_int8((unsigned char)0xD9);
5918 emit_int8((unsigned char)0xFA);
5919 }
5920
5921 void Assembler::fst_d(Address adr) {
5922 InstructionMark im(this);
5923 emit_int8((unsigned char)0xDD);
5924 emit_operand32(rdx, adr);
5925 }
5926
5927 void Assembler::fst_s(Address adr) {
5928 InstructionMark im(this);
5929 emit_int8((unsigned char)0xD9);
5930 emit_operand32(rdx, adr);
5931 }
5932
5933 void Assembler::fstp_d(Address adr) {
5934 InstructionMark im(this);
5935 emit_int8((unsigned char)0xDD);
5936 emit_operand32(rbx, adr);
5937 }
5938
5939 void Assembler::fstp_d(int index) {
5940 emit_farith(0xDD, 0xD8, index);
5941 }
5942
5943 void Assembler::fstp_s(Address adr) {
5944 InstructionMark im(this);
5945 emit_int8((unsigned char)0xD9);
5946 emit_operand32(rbx, adr);
5947 }
5948
5949 void Assembler::fstp_x(Address adr) {
5950 InstructionMark im(this);
5951 emit_int8((unsigned char)0xDB);
5952 emit_operand32(rdi, adr);
5953 }
5954
5955 void Assembler::fsub(int i) {
5956 emit_farith(0xD8, 0xE0, i);
5957 }
5958
5959 void Assembler::fsub_d(Address src) {
5960 InstructionMark im(this);
5961 emit_int8((unsigned char)0xDC);
5962 emit_operand32(rsp, src);
5963 }
5964
5965 void Assembler::fsub_s(Address src) {
5966 InstructionMark im(this);
5967 emit_int8((unsigned char)0xD8);
5968 emit_operand32(rsp, src);
5969 }
5970
5971 void Assembler::fsuba(int i) {
5972 emit_farith(0xDC, 0xE8, i);
5973 }
5974
5975 void Assembler::fsubp(int i) {
5976 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
5977 }
5978
5979 void Assembler::fsubr(int i) {
5980 emit_farith(0xD8, 0xE8, i);
5981 }
5982
5983 void Assembler::fsubr_d(Address src) {
5984 InstructionMark im(this);
5985 emit_int8((unsigned char)0xDC);
5986 emit_operand32(rbp, src);
5987 }
5988
5989 void Assembler::fsubr_s(Address src) {
5990 InstructionMark im(this);
5991 emit_int8((unsigned char)0xD8);
5992 emit_operand32(rbp, src);
5993 }
5994
5995 void Assembler::fsubra(int i) {
5996 emit_farith(0xDC, 0xE0, i);
5997 }
5998
5999 void Assembler::fsubrp(int i) {
6000 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
6001 }
6002
6003 void Assembler::ftan() {
6004 emit_int8((unsigned char)0xD9);
6005 emit_int8((unsigned char)0xF2);
6006 emit_int8((unsigned char)0xDD);
6007 emit_int8((unsigned char)0xD8);
6008 }
6009
6010 void Assembler::ftst() {
6011 emit_int8((unsigned char)0xD9);
6012 emit_int8((unsigned char)0xE4);
6013 }
6014
6015 void Assembler::fucomi(int i) {
6016 // make sure the instruction is supported (introduced for P6, together with cmov)
6017 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6018 emit_farith(0xDB, 0xE8, i);
6019 }
6020
6021 void Assembler::fucomip(int i) {
6022 // make sure the instruction is supported (introduced for P6, together with cmov)
6023 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6024 emit_farith(0xDF, 0xE8, i);
6025 }
6026
6027 void Assembler::fwait() {
6028 emit_int8((unsigned char)0x9B);
6029 }
6030
6031 void Assembler::fxch(int i) {
6032 emit_farith(0xD9, 0xC8, i);
6033 }
6034
6035 void Assembler::fyl2x() {
6036 emit_int8((unsigned char)0xD9);
6037 emit_int8((unsigned char)0xF1);
6038 }
6039
6040 void Assembler::frndint() {
6041 emit_int8((unsigned char)0xD9);
6042 emit_int8((unsigned char)0xFC);
6043 }
6044
6045 void Assembler::f2xm1() {
6046 emit_int8((unsigned char)0xD9);
6047 emit_int8((unsigned char)0xF0);
6048 }
6049
6050 void Assembler::fldl2e() {
6051 emit_int8((unsigned char)0xD9);
6052 emit_int8((unsigned char)0xEA);
6053 }
6054
6055 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
6056 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
6057 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
6058 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
6059
6060 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
6061 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6062 if (pre > 0) {
6063 emit_int8(simd_pre[pre]);
6064 }
6065 if (rex_w) {
6066 prefixq(adr, xreg);
6067 } else {
6068 prefix(adr, xreg);
6069 }
6070 if (opc > 0) {
6071 emit_int8(0x0F);
6072 int opc2 = simd_opc[opc];
6073 if (opc2 > 0) {
6074 emit_int8(opc2);
6075 }
6076 }
6077 }
6078
6079 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6080 if (pre > 0) {
6081 emit_int8(simd_pre[pre]);
6082 }
6083 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) :
6084 prefix_and_encode(dst_enc, src_enc);
6085 if (opc > 0) {
6086 emit_int8(0x0F);
6087 int opc2 = simd_opc[opc];
6088 if (opc2 > 0) {
6089 emit_int8(opc2);
6090 }
6091 }
6092 return encode;
6093 }
6094
6095
6096 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, int vector_len) {
6097 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
6098 prefix(VEX_3bytes);
6099
6100 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
6101 byte1 = (~byte1) & 0xE0;
6102 byte1 |= opc;
6103 emit_int8(byte1);
6104
6105 int byte2 = ((~nds_enc) & 0xf) << 3;
6106 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
6107 emit_int8(byte2);
6108 } else {
6109 prefix(VEX_2bytes);
6110
6111 int byte1 = vex_r ? VEX_R : 0;
6112 byte1 = (~byte1) & 0x80;
6113 byte1 |= ((~nds_enc) & 0xf) << 3;
6114 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
6115 emit_int8(byte1);
6116 }
6117 }
6118
6119 // This is a 4 byte encoding
6120 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, bool evex_r, bool evex_v,
6121 int nds_enc, VexSimdPrefix pre, VexOpcode opc,
6122 bool is_extended_context, bool is_merge_context,
6123 int vector_len, bool no_mask_reg ){
6124 // EVEX 0x62 prefix
6125 prefix(EVEX_4bytes);
6126 _evex_encoding = (vex_w ? VEX_W : 0) | (evex_r ? EVEX_Rb : 0);
6127
6128 // P0: byte 2, initialized to RXBR`00mm
6129 // instead of not'd
6130 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
6131 byte2 = (~byte2) & 0xF0;
6132 // confine opc opcode extensions in mm bits to lower two bits
6133 // of form {0F, 0F_38, 0F_3A}
6134 byte2 |= opc;
6135 emit_int8(byte2);
6136
6137 // P1: byte 3 as Wvvvv1pp
6138 int byte3 = ((~nds_enc) & 0xf) << 3;
6139 // p[10] is always 1
6140 byte3 |= EVEX_F;
6141 byte3 |= (vex_w & 1) << 7;
6142 // confine pre opcode extensions in pp bits to lower two bits
6143 // of form {66, F3, F2}
6144 byte3 |= pre;
6145 emit_int8(byte3);
6146
6147 // P2: byte 4 as zL'Lbv'aaa
6148 int byte4 = (no_mask_reg) ? 0 : 1; // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
6149 // EVEX.v` for extending EVEX.vvvv or VIDX
6150 byte4 |= (evex_v ? 0: EVEX_V);
6151 // third EXEC.b for broadcast actions
6152 byte4 |= (is_extended_context ? EVEX_Rb : 0);
6153 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
6154 byte4 |= ((vector_len) & 0x3) << 5;
6155 // last is EVEX.z for zero/merge actions
6156 byte4 |= (is_merge_context ? EVEX_Z : 0);
6157 emit_int8(byte4);
6158 }
6159
6160 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre,
6161 VexOpcode opc, bool vex_w, int vector_len, bool legacy_mode, bool no_mask_reg) {
6162 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
6163 bool vex_b = adr.base_needs_rex();
6164 bool vex_x = adr.index_needs_rex();
6165 _avx_vector_len = vector_len;
6166
6167 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6168 if (_legacy_mode_vl && _instruction_uses_vl) {
6169 switch (vector_len) {
6170 case AVX_128bit:
6171 case AVX_256bit:
6172 legacy_mode = true;
6173 break;
6174 }
6175 }
6176
6177 if ((UseAVX > 2) && (legacy_mode == false))
6178 {
6179 bool evex_r = (xreg_enc >= 16);
6180 bool evex_v = (nds_enc >= 16);
6181 _is_evex_instruction = true;
6182 evex_prefix(vex_r, vex_b, vex_x, vex_w, evex_r, evex_v, nds_enc, pre, opc, false, false, vector_len, no_mask_reg);
6183 } else {
6184 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector_len);
6185 }
6186 _instruction_uses_vl = false;
6187 }
6188
6189 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,
6190 bool vex_w, int vector_len, bool legacy_mode, bool no_mask_reg ) {
6191 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
6192 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
6193 bool vex_x = false;
6194 _avx_vector_len = vector_len;
6195
6196 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6197 if (_legacy_mode_vl && _instruction_uses_vl) {
6198 switch (vector_len) {
6199 case AVX_128bit:
6200 case AVX_256bit:
6201 legacy_mode = true;
6202 break;
6203 }
6204 }
6205
6206 if ((UseAVX > 2) && (legacy_mode == false))
6207 {
6208 bool evex_r = (dst_enc >= 16);
6209 bool evex_v = (nds_enc >= 16);
6210 // can use vex_x as bank extender on rm encoding
6211 vex_x = (src_enc >= 16);
6212 evex_prefix(vex_r, vex_b, vex_x, vex_w, evex_r, evex_v, nds_enc, pre, opc, false, false, vector_len, no_mask_reg);
6213 } else {
6214 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector_len);
6215 }
6216
6217 _instruction_uses_vl = false;
6218
6219 // return modrm byte components for operands
6220 return (((dst_enc & 7) << 3) | (src_enc & 7));
6221 }
6222
6223
6224 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
6225 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len, bool legacy_mode) {
6226 if (UseAVX > 0) {
6227 int xreg_enc = xreg->encoding();
6228 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6229 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector_len, legacy_mode, no_mask_reg);
6230 } else {
6231 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
6232 rex_prefix(adr, xreg, pre, opc, rex_w);
6233 }
6234 }
6235
6236 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
6237 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len, bool legacy_mode) {
6238 int dst_enc = dst->encoding();
6239 int src_enc = src->encoding();
6240 if (UseAVX > 0) {
6241 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6242 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, legacy_mode, no_mask_reg);
6243 } else {
6244 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
6245 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w);
6246 }
6247 }
6248
6249 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, KRegister src, VexSimdPrefix pre,
6250 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len) {
6251 int dst_enc = dst->encoding();
6252 int src_enc = src->encoding();
6253 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6254 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, true, no_mask_reg);
6255 }
6256
6257 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, Register src, VexSimdPrefix pre,
6258 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len) {
6259 int dst_enc = dst->encoding();
6260 int src_enc = src->encoding();
6261 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6262 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, true, no_mask_reg);
6263 }
6264
6265 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
6266 InstructionMark im(this);
6267 simd_prefix(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, false, AVX_128bit, legacy_mode);
6268 emit_int8(opcode);
6269 emit_operand(dst, src);
6270 }
6271
6272 void Assembler::emit_simd_arith_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg) {
6273 InstructionMark im(this);
6274 simd_prefix_q(dst, dst, src, pre, no_mask_reg);
6275 emit_int8(opcode);
6276 emit_operand(dst, src);
6277 }
6278
6279 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
6280 int encode = simd_prefix_and_encode(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, false, AVX_128bit, legacy_mode);
6281 emit_int8(opcode);
6282 emit_int8((unsigned char)(0xC0 | encode));
6283 }
6284
6285 void Assembler::emit_simd_arith_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg) {
6286 int encode = simd_prefix_and_encode(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, true, AVX_128bit);
6287 emit_int8(opcode);
6288 emit_int8((unsigned char)(0xC0 | encode));
6289 }
6290
6291 // Versions with no second source register (non-destructive source).
6292 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool opNoRegMask) {
6293 InstructionMark im(this);
6294 simd_prefix(dst, xnoreg, src, pre, opNoRegMask);
6295 emit_int8(opcode);
6296 emit_operand(dst, src);
6297 }
6298
6299 void Assembler::emit_simd_arith_nonds_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool opNoRegMask) {
6300 InstructionMark im(this);
6301 simd_prefix_q(dst, xnoreg, src, pre, opNoRegMask);
6302 emit_int8(opcode);
6303 emit_operand(dst, src);
6304 }
6305
6306 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
6307 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre, no_mask_reg, VEX_OPCODE_0F, false, AVX_128bit, legacy_mode);
6308 emit_int8(opcode);
6309 emit_int8((unsigned char)(0xC0 | encode));
6310 }
6311
6312 void Assembler::emit_simd_arith_nonds_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg) {
6313 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre, no_mask_reg, VEX_OPCODE_0F, true);
6314 emit_int8(opcode);
6315 emit_int8((unsigned char)(0xC0 | encode));
6316 }
6317
6318 // 3-operands AVX instructions
6319 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, Address src,
6320 VexSimdPrefix pre, int vector_len, bool no_mask_reg, bool legacy_mode) {
6321 InstructionMark im(this);
6322 vex_prefix(dst, nds, src, pre, vector_len, no_mask_reg, legacy_mode);
6323 emit_int8(opcode);
6324 emit_operand(dst, src);
6325 }
6326
6327 void Assembler::emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds,
6328 Address src, VexSimdPrefix pre, int vector_len, bool no_mask_reg) {
6329 InstructionMark im(this);
6330 vex_prefix_q(dst, nds, src, pre, vector_len, no_mask_reg);
6331 emit_int8(opcode);
6332 emit_operand(dst, src);
6333 }
6334
6335 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
6336 VexSimdPrefix pre, int vector_len, bool no_mask_reg, bool legacy_mode) {
6337 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector_len, VEX_OPCODE_0F, legacy_mode, no_mask_reg);
6338 emit_int8(opcode);
6339 emit_int8((unsigned char)(0xC0 | encode));
6340 }
6341
6342 void Assembler::emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
6343 VexSimdPrefix pre, int vector_len, bool no_mask_reg) {
6344 int src_enc = src->encoding();
6345 int dst_enc = dst->encoding();
6346 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6347 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, VEX_OPCODE_0F, true, vector_len, false, no_mask_reg);
6348 emit_int8(opcode);
6349 emit_int8((unsigned char)(0xC0 | encode));
6350 }
6351
6352 #ifndef _LP64
6353
6354 void Assembler::incl(Register dst) {
6355 // Don't use it directly. Use MacroAssembler::incrementl() instead.
6356 emit_int8(0x40 | dst->encoding());
6357 }
6358
6359 void Assembler::lea(Register dst, Address src) {
6360 leal(dst, src);
6361 }
6362
6363 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
6364 InstructionMark im(this);
6365 emit_int8((unsigned char)0xC7);
6366 emit_operand(rax, dst);
6367 emit_data((int)imm32, rspec, 0);
6368 }
6369
6370 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
6371 InstructionMark im(this);
6372 int encode = prefix_and_encode(dst->encoding());
6373 emit_int8((unsigned char)(0xB8 | encode));
6374 emit_data((int)imm32, rspec, 0);
6375 }
6376
6377 void Assembler::popa() { // 32bit
6378 emit_int8(0x61);
6379 }
6380
6381 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
6382 InstructionMark im(this);
6383 emit_int8(0x68);
6384 emit_data(imm32, rspec, 0);
6385 }
6386
6387 void Assembler::pusha() { // 32bit
6388 emit_int8(0x60);
6389 }
6390
6391 void Assembler::set_byte_if_not_zero(Register dst) {
6392 emit_int8(0x0F);
6393 emit_int8((unsigned char)0x95);
6394 emit_int8((unsigned char)(0xE0 | dst->encoding()));
6395 }
6396
6397 void Assembler::shldl(Register dst, Register src) {
6398 emit_int8(0x0F);
6399 emit_int8((unsigned char)0xA5);
6400 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6401 }
6402
6403 // 0F A4 / r ib
6404 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
6405 emit_int8(0x0F);
6406 emit_int8((unsigned char)0xA4);
6407 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6408 emit_int8(imm8);
6409 }
6410
6411 void Assembler::shrdl(Register dst, Register src) {
6412 emit_int8(0x0F);
6413 emit_int8((unsigned char)0xAD);
6414 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6415 }
6416
6417 #else // LP64
6418
6419 void Assembler::set_byte_if_not_zero(Register dst) {
6420 int enc = prefix_and_encode(dst->encoding(), true);
6421 emit_int8(0x0F);
6422 emit_int8((unsigned char)0x95);
6423 emit_int8((unsigned char)(0xE0 | enc));
6424 }
6425
6426 // 64bit only pieces of the assembler
6427 // This should only be used by 64bit instructions that can use rip-relative
6428 // it cannot be used by instructions that want an immediate value.
6429
6430 bool Assembler::reachable(AddressLiteral adr) {
6431 int64_t disp;
6432 // None will force a 64bit literal to the code stream. Likely a placeholder
6433 // for something that will be patched later and we need to certain it will
6434 // always be reachable.
6435 if (adr.reloc() == relocInfo::none) {
6436 return false;
6437 }
6438 if (adr.reloc() == relocInfo::internal_word_type) {
6439 // This should be rip relative and easily reachable.
6440 return true;
6441 }
6442 if (adr.reloc() == relocInfo::virtual_call_type ||
6443 adr.reloc() == relocInfo::opt_virtual_call_type ||
6444 adr.reloc() == relocInfo::static_call_type ||
6445 adr.reloc() == relocInfo::static_stub_type ) {
6446 // This should be rip relative within the code cache and easily
6447 // reachable until we get huge code caches. (At which point
6448 // ic code is going to have issues).
6449 return true;
6450 }
6451 if (adr.reloc() != relocInfo::external_word_type &&
6452 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
6453 adr.reloc() != relocInfo::poll_type && // relocs to identify them
6454 adr.reloc() != relocInfo::runtime_call_type ) {
6455 return false;
6456 }
6457
6458 // Stress the correction code
6459 if (ForceUnreachable) {
6460 // Must be runtimecall reloc, see if it is in the codecache
6461 // Flipping stuff in the codecache to be unreachable causes issues
6462 // with things like inline caches where the additional instructions
6463 // are not handled.
6464 if (CodeCache::find_blob(adr._target) == NULL) {
6465 return false;
6466 }
6467 }
6468 // For external_word_type/runtime_call_type if it is reachable from where we
6469 // are now (possibly a temp buffer) and where we might end up
6470 // anywhere in the codeCache then we are always reachable.
6471 // This would have to change if we ever save/restore shared code
6472 // to be more pessimistic.
6473 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
6474 if (!is_simm32(disp)) return false;
6475 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
6476 if (!is_simm32(disp)) return false;
6477
6478 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
6479
6480 // Because rip relative is a disp + address_of_next_instruction and we
6481 // don't know the value of address_of_next_instruction we apply a fudge factor
6482 // to make sure we will be ok no matter the size of the instruction we get placed into.
6483 // We don't have to fudge the checks above here because they are already worst case.
6484
6485 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
6486 // + 4 because better safe than sorry.
6487 const int fudge = 12 + 4;
6488 if (disp < 0) {
6489 disp -= fudge;
6490 } else {
6491 disp += fudge;
6492 }
6493 return is_simm32(disp);
6494 }
6495
6496 // Check if the polling page is not reachable from the code cache using rip-relative
6497 // addressing.
6498 bool Assembler::is_polling_page_far() {
6499 intptr_t addr = (intptr_t)os::get_polling_page();
6500 return ForceUnreachable ||
6501 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
6502 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
6503 }
6504
6505 void Assembler::emit_data64(jlong data,
6506 relocInfo::relocType rtype,
6507 int format) {
6508 if (rtype == relocInfo::none) {
6509 emit_int64(data);
6510 } else {
6511 emit_data64(data, Relocation::spec_simple(rtype), format);
6512 }
6513 }
6514
6515 void Assembler::emit_data64(jlong data,
6516 RelocationHolder const& rspec,
6517 int format) {
6518 assert(imm_operand == 0, "default format must be immediate in this file");
6519 assert(imm_operand == format, "must be immediate");
6520 assert(inst_mark() != NULL, "must be inside InstructionMark");
6521 // Do not use AbstractAssembler::relocate, which is not intended for
6522 // embedded words. Instead, relocate to the enclosing instruction.
6523 code_section()->relocate(inst_mark(), rspec, format);
6524 #ifdef ASSERT
6525 check_relocation(rspec, format);
6526 #endif
6527 emit_int64(data);
6528 }
6529
6530 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
6531 if (reg_enc >= 8) {
6532 prefix(REX_B);
6533 reg_enc -= 8;
6534 } else if (byteinst && reg_enc >= 4) {
6535 prefix(REX);
6536 }
6537 return reg_enc;
6538 }
6539
6540 int Assembler::prefixq_and_encode(int reg_enc) {
6541 if (reg_enc < 8) {
6542 prefix(REX_W);
6543 } else {
6544 prefix(REX_WB);
6545 reg_enc -= 8;
6546 }
6547 return reg_enc;
6548 }
6549
6550 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
6551 if (dst_enc < 8) {
6552 if (src_enc >= 8) {
6553 prefix(REX_B);
6554 src_enc -= 8;
6555 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
6556 prefix(REX);
6557 }
6558 } else {
6559 if (src_enc < 8) {
6560 prefix(REX_R);
6561 } else {
6562 prefix(REX_RB);
6563 src_enc -= 8;
6564 }
6565 dst_enc -= 8;
6566 }
6567 return dst_enc << 3 | src_enc;
6568 }
6569
6570 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
6571 if (dst_enc < 8) {
6572 if (src_enc < 8) {
6573 prefix(REX_W);
6574 } else {
6575 prefix(REX_WB);
6576 src_enc -= 8;
6577 }
6578 } else {
6579 if (src_enc < 8) {
6580 prefix(REX_WR);
6581 } else {
6582 prefix(REX_WRB);
6583 src_enc -= 8;
6584 }
6585 dst_enc -= 8;
6586 }
6587 return dst_enc << 3 | src_enc;
6588 }
6589
6590 void Assembler::prefix(Register reg) {
6591 if (reg->encoding() >= 8) {
6592 prefix(REX_B);
6593 }
6594 }
6595
6596 void Assembler::prefix(Register dst, Register src, Prefix p) {
6597 if (src->encoding() >= 8) {
6598 p = (Prefix)(p | REX_B);
6599 }
6600 if (dst->encoding() >= 8) {
6601 p = (Prefix)( p | REX_R);
6602 }
6603 if (p != Prefix_EMPTY) {
6604 // do not generate an empty prefix
6605 prefix(p);
6606 }
6607 }
6608
6609 void Assembler::prefix(Register dst, Address adr, Prefix p) {
6610 if (adr.base_needs_rex()) {
6611 if (adr.index_needs_rex()) {
6612 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
6613 } else {
6614 prefix(REX_B);
6615 }
6616 } else {
6617 if (adr.index_needs_rex()) {
6618 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
6619 }
6620 }
6621 if (dst->encoding() >= 8) {
6622 p = (Prefix)(p | REX_R);
6623 }
6624 if (p != Prefix_EMPTY) {
6625 // do not generate an empty prefix
6626 prefix(p);
6627 }
6628 }
6629
6630 void Assembler::prefix(Address adr) {
6631 if (adr.base_needs_rex()) {
6632 if (adr.index_needs_rex()) {
6633 prefix(REX_XB);
6634 } else {
6635 prefix(REX_B);
6636 }
6637 } else {
6638 if (adr.index_needs_rex()) {
6639 prefix(REX_X);
6640 }
6641 }
6642 }
6643
6644 void Assembler::prefixq(Address adr) {
6645 if (adr.base_needs_rex()) {
6646 if (adr.index_needs_rex()) {
6647 prefix(REX_WXB);
6648 } else {
6649 prefix(REX_WB);
6650 }
6651 } else {
6652 if (adr.index_needs_rex()) {
6653 prefix(REX_WX);
6654 } else {
6655 prefix(REX_W);
6656 }
6657 }
6658 }
6659
6660
6661 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
6662 if (reg->encoding() < 8) {
6663 if (adr.base_needs_rex()) {
6664 if (adr.index_needs_rex()) {
6665 prefix(REX_XB);
6666 } else {
6667 prefix(REX_B);
6668 }
6669 } else {
6670 if (adr.index_needs_rex()) {
6671 prefix(REX_X);
6672 } else if (byteinst && reg->encoding() >= 4 ) {
6673 prefix(REX);
6674 }
6675 }
6676 } else {
6677 if (adr.base_needs_rex()) {
6678 if (adr.index_needs_rex()) {
6679 prefix(REX_RXB);
6680 } else {
6681 prefix(REX_RB);
6682 }
6683 } else {
6684 if (adr.index_needs_rex()) {
6685 prefix(REX_RX);
6686 } else {
6687 prefix(REX_R);
6688 }
6689 }
6690 }
6691 }
6692
6693 void Assembler::prefixq(Address adr, Register src) {
6694 if (src->encoding() < 8) {
6695 if (adr.base_needs_rex()) {
6696 if (adr.index_needs_rex()) {
6697 prefix(REX_WXB);
6698 } else {
6699 prefix(REX_WB);
6700 }
6701 } else {
6702 if (adr.index_needs_rex()) {
6703 prefix(REX_WX);
6704 } else {
6705 prefix(REX_W);
6706 }
6707 }
6708 } else {
6709 if (adr.base_needs_rex()) {
6710 if (adr.index_needs_rex()) {
6711 prefix(REX_WRXB);
6712 } else {
6713 prefix(REX_WRB);
6714 }
6715 } else {
6716 if (adr.index_needs_rex()) {
6717 prefix(REX_WRX);
6718 } else {
6719 prefix(REX_WR);
6720 }
6721 }
6722 }
6723 }
6724
6725 void Assembler::prefix(Address adr, XMMRegister reg) {
6726 if (reg->encoding() < 8) {
6727 if (adr.base_needs_rex()) {
6728 if (adr.index_needs_rex()) {
6729 prefix(REX_XB);
6730 } else {
6731 prefix(REX_B);
6732 }
6733 } else {
6734 if (adr.index_needs_rex()) {
6735 prefix(REX_X);
6736 }
6737 }
6738 } else {
6739 if (adr.base_needs_rex()) {
6740 if (adr.index_needs_rex()) {
6741 prefix(REX_RXB);
6742 } else {
6743 prefix(REX_RB);
6744 }
6745 } else {
6746 if (adr.index_needs_rex()) {
6747 prefix(REX_RX);
6748 } else {
6749 prefix(REX_R);
6750 }
6751 }
6752 }
6753 }
6754
6755 void Assembler::prefixq(Address adr, XMMRegister src) {
6756 if (src->encoding() < 8) {
6757 if (adr.base_needs_rex()) {
6758 if (adr.index_needs_rex()) {
6759 prefix(REX_WXB);
6760 } else {
6761 prefix(REX_WB);
6762 }
6763 } else {
6764 if (adr.index_needs_rex()) {
6765 prefix(REX_WX);
6766 } else {
6767 prefix(REX_W);
6768 }
6769 }
6770 } else {
6771 if (adr.base_needs_rex()) {
6772 if (adr.index_needs_rex()) {
6773 prefix(REX_WRXB);
6774 } else {
6775 prefix(REX_WRB);
6776 }
6777 } else {
6778 if (adr.index_needs_rex()) {
6779 prefix(REX_WRX);
6780 } else {
6781 prefix(REX_WR);
6782 }
6783 }
6784 }
6785 }
6786
6787 void Assembler::adcq(Register dst, int32_t imm32) {
6788 (void) prefixq_and_encode(dst->encoding());
6789 emit_arith(0x81, 0xD0, dst, imm32);
6790 }
6791
6792 void Assembler::adcq(Register dst, Address src) {
6793 InstructionMark im(this);
6794 prefixq(src, dst);
6795 emit_int8(0x13);
6796 emit_operand(dst, src);
6797 }
6798
6799 void Assembler::adcq(Register dst, Register src) {
6800 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6801 emit_arith(0x13, 0xC0, dst, src);
6802 }
6803
6804 void Assembler::addq(Address dst, int32_t imm32) {
6805 InstructionMark im(this);
6806 prefixq(dst);
6807 emit_arith_operand(0x81, rax, dst,imm32);
6808 }
6809
6810 void Assembler::addq(Address dst, Register src) {
6811 InstructionMark im(this);
6812 prefixq(dst, src);
6813 emit_int8(0x01);
6814 emit_operand(src, dst);
6815 }
6816
6817 void Assembler::addq(Register dst, int32_t imm32) {
6818 (void) prefixq_and_encode(dst->encoding());
6819 emit_arith(0x81, 0xC0, dst, imm32);
6820 }
6821
6822 void Assembler::addq(Register dst, Address src) {
6823 InstructionMark im(this);
6824 prefixq(src, dst);
6825 emit_int8(0x03);
6826 emit_operand(dst, src);
6827 }
6828
6829 void Assembler::addq(Register dst, Register src) {
6830 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6831 emit_arith(0x03, 0xC0, dst, src);
6832 }
6833
6834 void Assembler::adcxq(Register dst, Register src) {
6835 //assert(VM_Version::supports_adx(), "adx instructions not supported");
6836 emit_int8((unsigned char)0x66);
6837 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6838 emit_int8(0x0F);
6839 emit_int8(0x38);
6840 emit_int8((unsigned char)0xF6);
6841 emit_int8((unsigned char)(0xC0 | encode));
6842 }
6843
6844 void Assembler::adoxq(Register dst, Register src) {
6845 //assert(VM_Version::supports_adx(), "adx instructions not supported");
6846 emit_int8((unsigned char)0xF3);
6847 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6848 emit_int8(0x0F);
6849 emit_int8(0x38);
6850 emit_int8((unsigned char)0xF6);
6851 emit_int8((unsigned char)(0xC0 | encode));
6852 }
6853
6854 void Assembler::andq(Address dst, int32_t imm32) {
6855 InstructionMark im(this);
6856 prefixq(dst);
6857 emit_int8((unsigned char)0x81);
6858 emit_operand(rsp, dst, 4);
6859 emit_int32(imm32);
6860 }
6861
6862 void Assembler::andq(Register dst, int32_t imm32) {
6863 (void) prefixq_and_encode(dst->encoding());
6864 emit_arith(0x81, 0xE0, dst, imm32);
6865 }
6866
6867 void Assembler::andq(Register dst, Address src) {
6868 InstructionMark im(this);
6869 prefixq(src, dst);
6870 emit_int8(0x23);
6871 emit_operand(dst, src);
6872 }
6873
6874 void Assembler::andq(Register dst, Register src) {
6875 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6876 emit_arith(0x23, 0xC0, dst, src);
6877 }
6878
6879 void Assembler::andnq(Register dst, Register src1, Register src2) {
6880 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6881 int encode = vex_prefix_0F38_and_encode_q_legacy(dst, src1, src2);
6882 emit_int8((unsigned char)0xF2);
6883 emit_int8((unsigned char)(0xC0 | encode));
6884 }
6885
6886 void Assembler::andnq(Register dst, Register src1, Address src2) {
6887 InstructionMark im(this);
6888 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6889 vex_prefix_0F38_q_legacy(dst, src1, src2);
6890 emit_int8((unsigned char)0xF2);
6891 emit_operand(dst, src2);
6892 }
6893
6894 void Assembler::bsfq(Register dst, Register src) {
6895 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6896 emit_int8(0x0F);
6897 emit_int8((unsigned char)0xBC);
6898 emit_int8((unsigned char)(0xC0 | encode));
6899 }
6900
6901 void Assembler::bsrq(Register dst, Register src) {
6902 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6903 emit_int8(0x0F);
6904 emit_int8((unsigned char)0xBD);
6905 emit_int8((unsigned char)(0xC0 | encode));
6906 }
6907
6908 void Assembler::bswapq(Register reg) {
6909 int encode = prefixq_and_encode(reg->encoding());
6910 emit_int8(0x0F);
6911 emit_int8((unsigned char)(0xC8 | encode));
6912 }
6913
6914 void Assembler::blsiq(Register dst, Register src) {
6915 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6916 int encode = vex_prefix_0F38_and_encode_q_legacy(rbx, dst, src);
6917 emit_int8((unsigned char)0xF3);
6918 emit_int8((unsigned char)(0xC0 | encode));
6919 }
6920
6921 void Assembler::blsiq(Register dst, Address src) {
6922 InstructionMark im(this);
6923 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6924 vex_prefix_0F38_q_legacy(rbx, dst, src);
6925 emit_int8((unsigned char)0xF3);
6926 emit_operand(rbx, src);
6927 }
6928
6929 void Assembler::blsmskq(Register dst, Register src) {
6930 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6931 int encode = vex_prefix_0F38_and_encode_q_legacy(rdx, dst, src);
6932 emit_int8((unsigned char)0xF3);
6933 emit_int8((unsigned char)(0xC0 | encode));
6934 }
6935
6936 void Assembler::blsmskq(Register dst, Address src) {
6937 InstructionMark im(this);
6938 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6939 vex_prefix_0F38_q_legacy(rdx, dst, src);
6940 emit_int8((unsigned char)0xF3);
6941 emit_operand(rdx, src);
6942 }
6943
6944 void Assembler::blsrq(Register dst, Register src) {
6945 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6946 int encode = vex_prefix_0F38_and_encode_q_legacy(rcx, dst, src);
6947 emit_int8((unsigned char)0xF3);
6948 emit_int8((unsigned char)(0xC0 | encode));
6949 }
6950
6951 void Assembler::blsrq(Register dst, Address src) {
6952 InstructionMark im(this);
6953 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6954 vex_prefix_0F38_q_legacy(rcx, dst, src);
6955 emit_int8((unsigned char)0xF3);
6956 emit_operand(rcx, src);
6957 }
6958
6959 void Assembler::cdqq() {
6960 prefix(REX_W);
6961 emit_int8((unsigned char)0x99);
6962 }
6963
6964 void Assembler::clflush(Address adr) {
6965 prefix(adr);
6966 emit_int8(0x0F);
6967 emit_int8((unsigned char)0xAE);
6968 emit_operand(rdi, adr);
6969 }
6970
6971 void Assembler::cmovq(Condition cc, Register dst, Register src) {
6972 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6973 emit_int8(0x0F);
6974 emit_int8(0x40 | cc);
6975 emit_int8((unsigned char)(0xC0 | encode));
6976 }
6977
6978 void Assembler::cmovq(Condition cc, Register dst, Address src) {
6979 InstructionMark im(this);
6980 prefixq(src, dst);
6981 emit_int8(0x0F);
6982 emit_int8(0x40 | cc);
6983 emit_operand(dst, src);
6984 }
6985
6986 void Assembler::cmpq(Address dst, int32_t imm32) {
6987 InstructionMark im(this);
6988 prefixq(dst);
6989 emit_int8((unsigned char)0x81);
6990 emit_operand(rdi, dst, 4);
6991 emit_int32(imm32);
6992 }
6993
6994 void Assembler::cmpq(Register dst, int32_t imm32) {
6995 (void) prefixq_and_encode(dst->encoding());
6996 emit_arith(0x81, 0xF8, dst, imm32);
6997 }
6998
6999 void Assembler::cmpq(Address dst, Register src) {
7000 InstructionMark im(this);
7001 prefixq(dst, src);
7002 emit_int8(0x3B);
7003 emit_operand(src, dst);
7004 }
7005
7006 void Assembler::cmpq(Register dst, Register src) {
7007 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7008 emit_arith(0x3B, 0xC0, dst, src);
7009 }
7010
7011 void Assembler::cmpq(Register dst, Address src) {
7012 InstructionMark im(this);
7013 prefixq(src, dst);
7014 emit_int8(0x3B);
7015 emit_operand(dst, src);
7016 }
7017
7018 void Assembler::cmpxchgq(Register reg, Address adr) {
7019 InstructionMark im(this);
7020 prefixq(adr, reg);
7021 emit_int8(0x0F);
7022 emit_int8((unsigned char)0xB1);
7023 emit_operand(reg, adr);
7024 }
7025
7026 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
7027 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7028 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2, /* no_mask_reg */ true);
7029 emit_int8(0x2A);
7030 emit_int8((unsigned char)(0xC0 | encode));
7031 }
7032
7033 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
7034 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7035 if (VM_Version::supports_evex()) {
7036 _tuple_type = EVEX_T1S;
7037 _input_size_in_bits = EVEX_32bit;
7038 }
7039 InstructionMark im(this);
7040 simd_prefix_q(dst, dst, src, VEX_SIMD_F2, /* no_mask_reg */ true);
7041 emit_int8(0x2A);
7042 emit_operand(dst, src);
7043 }
7044
7045 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
7046 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7047 if (VM_Version::supports_evex()) {
7048 _tuple_type = EVEX_T1S;
7049 _input_size_in_bits = EVEX_32bit;
7050 }
7051 InstructionMark im(this);
7052 simd_prefix_q(dst, dst, src, VEX_SIMD_F3, /* no_mask_reg */ true);
7053 emit_int8(0x2A);
7054 emit_operand(dst, src);
7055 }
7056
7057 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
7058 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7059 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, /* no_mask_reg */ true);
7060 emit_int8(0x2C);
7061 emit_int8((unsigned char)(0xC0 | encode));
7062 }
7063
7064 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
7065 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7066 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, /* no_mask_reg */ true);
7067 emit_int8(0x2C);
7068 emit_int8((unsigned char)(0xC0 | encode));
7069 }
7070
7071 void Assembler::decl(Register dst) {
7072 // Don't use it directly. Use MacroAssembler::decrementl() instead.
7073 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
7074 int encode = prefix_and_encode(dst->encoding());
7075 emit_int8((unsigned char)0xFF);
7076 emit_int8((unsigned char)(0xC8 | encode));
7077 }
7078
7079 void Assembler::decq(Register dst) {
7080 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7081 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7082 int encode = prefixq_and_encode(dst->encoding());
7083 emit_int8((unsigned char)0xFF);
7084 emit_int8(0xC8 | encode);
7085 }
7086
7087 void Assembler::decq(Address dst) {
7088 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7089 InstructionMark im(this);
7090 prefixq(dst);
7091 emit_int8((unsigned char)0xFF);
7092 emit_operand(rcx, dst);
7093 }
7094
7095 void Assembler::fxrstor(Address src) {
7096 prefixq(src);
7097 emit_int8(0x0F);
7098 emit_int8((unsigned char)0xAE);
7099 emit_operand(as_Register(1), src);
7100 }
7101
7102 void Assembler::xrstor(Address src) {
7103 prefixq(src);
7104 emit_int8(0x0F);
7105 emit_int8((unsigned char)0xAE);
7106 emit_operand(as_Register(5), src);
7107 }
7108
7109 void Assembler::fxsave(Address dst) {
7110 prefixq(dst);
7111 emit_int8(0x0F);
7112 emit_int8((unsigned char)0xAE);
7113 emit_operand(as_Register(0), dst);
7114 }
7115
7116 void Assembler::xsave(Address dst) {
7117 prefixq(dst);
7118 emit_int8(0x0F);
7119 emit_int8((unsigned char)0xAE);
7120 emit_operand(as_Register(4), dst);
7121 }
7122
7123 void Assembler::idivq(Register src) {
7124 int encode = prefixq_and_encode(src->encoding());
7125 emit_int8((unsigned char)0xF7);
7126 emit_int8((unsigned char)(0xF8 | encode));
7127 }
7128
7129 void Assembler::imulq(Register dst, Register src) {
7130 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7131 emit_int8(0x0F);
7132 emit_int8((unsigned char)0xAF);
7133 emit_int8((unsigned char)(0xC0 | encode));
7134 }
7135
7136 void Assembler::imulq(Register dst, Register src, int value) {
7137 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7138 if (is8bit(value)) {
7139 emit_int8(0x6B);
7140 emit_int8((unsigned char)(0xC0 | encode));
7141 emit_int8(value & 0xFF);
7142 } else {
7143 emit_int8(0x69);
7144 emit_int8((unsigned char)(0xC0 | encode));
7145 emit_int32(value);
7146 }
7147 }
7148
7149 void Assembler::imulq(Register dst, Address src) {
7150 InstructionMark im(this);
7151 prefixq(src, dst);
7152 emit_int8(0x0F);
7153 emit_int8((unsigned char) 0xAF);
7154 emit_operand(dst, src);
7155 }
7156
7157 void Assembler::incl(Register dst) {
7158 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7159 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7160 int encode = prefix_and_encode(dst->encoding());
7161 emit_int8((unsigned char)0xFF);
7162 emit_int8((unsigned char)(0xC0 | encode));
7163 }
7164
7165 void Assembler::incq(Register dst) {
7166 // Don't use it directly. Use MacroAssembler::incrementq() instead.
7167 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7168 int encode = prefixq_and_encode(dst->encoding());
7169 emit_int8((unsigned char)0xFF);
7170 emit_int8((unsigned char)(0xC0 | encode));
7171 }
7172
7173 void Assembler::incq(Address dst) {
7174 // Don't use it directly. Use MacroAssembler::incrementq() instead.
7175 InstructionMark im(this);
7176 prefixq(dst);
7177 emit_int8((unsigned char)0xFF);
7178 emit_operand(rax, dst);
7179 }
7180
7181 void Assembler::lea(Register dst, Address src) {
7182 leaq(dst, src);
7183 }
7184
7185 void Assembler::leaq(Register dst, Address src) {
7186 InstructionMark im(this);
7187 prefixq(src, dst);
7188 emit_int8((unsigned char)0x8D);
7189 emit_operand(dst, src);
7190 }
7191
7192 void Assembler::mov64(Register dst, int64_t imm64) {
7193 InstructionMark im(this);
7194 int encode = prefixq_and_encode(dst->encoding());
7195 emit_int8((unsigned char)(0xB8 | encode));
7196 emit_int64(imm64);
7197 }
7198
7199 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
7200 InstructionMark im(this);
7201 int encode = prefixq_and_encode(dst->encoding());
7202 emit_int8(0xB8 | encode);
7203 emit_data64(imm64, rspec);
7204 }
7205
7206 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7207 InstructionMark im(this);
7208 int encode = prefix_and_encode(dst->encoding());
7209 emit_int8((unsigned char)(0xB8 | encode));
7210 emit_data((int)imm32, rspec, narrow_oop_operand);
7211 }
7212
7213 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7214 InstructionMark im(this);
7215 prefix(dst);
7216 emit_int8((unsigned char)0xC7);
7217 emit_operand(rax, dst, 4);
7218 emit_data((int)imm32, rspec, narrow_oop_operand);
7219 }
7220
7221 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
7222 InstructionMark im(this);
7223 int encode = prefix_and_encode(src1->encoding());
7224 emit_int8((unsigned char)0x81);
7225 emit_int8((unsigned char)(0xF8 | encode));
7226 emit_data((int)imm32, rspec, narrow_oop_operand);
7227 }
7228
7229 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
7230 InstructionMark im(this);
7231 prefix(src1);
7232 emit_int8((unsigned char)0x81);
7233 emit_operand(rax, src1, 4);
7234 emit_data((int)imm32, rspec, narrow_oop_operand);
7235 }
7236
7237 void Assembler::lzcntq(Register dst, Register src) {
7238 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
7239 emit_int8((unsigned char)0xF3);
7240 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7241 emit_int8(0x0F);
7242 emit_int8((unsigned char)0xBD);
7243 emit_int8((unsigned char)(0xC0 | encode));
7244 }
7245
7246 void Assembler::movdq(XMMRegister dst, Register src) {
7247 // table D-1 says MMX/SSE2
7248 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7249 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66, /* no_mask_reg */ true);
7250 emit_int8(0x6E);
7251 emit_int8((unsigned char)(0xC0 | encode));
7252 }
7253
7254 void Assembler::movdq(Register dst, XMMRegister src) {
7255 // table D-1 says MMX/SSE2
7256 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7257 // swap src/dst to get correct prefix
7258 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66, /* no_mask_reg */ true);
7259 emit_int8(0x7E);
7260 emit_int8((unsigned char)(0xC0 | encode));
7261 }
7262
7263 void Assembler::movq(Register dst, Register src) {
7264 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7265 emit_int8((unsigned char)0x8B);
7266 emit_int8((unsigned char)(0xC0 | encode));
7267 }
7268
7269 void Assembler::movq(Register dst, Address src) {
7270 InstructionMark im(this);
7271 prefixq(src, dst);
7272 emit_int8((unsigned char)0x8B);
7273 emit_operand(dst, src);
7274 }
7275
7276 void Assembler::movq(Address dst, Register src) {
7277 InstructionMark im(this);
7278 prefixq(dst, src);
7279 emit_int8((unsigned char)0x89);
7280 emit_operand(src, dst);
7281 }
7282
7283 void Assembler::movsbq(Register dst, Address src) {
7284 InstructionMark im(this);
7285 prefixq(src, dst);
7286 emit_int8(0x0F);
7287 emit_int8((unsigned char)0xBE);
7288 emit_operand(dst, src);
7289 }
7290
7291 void Assembler::movsbq(Register dst, Register src) {
7292 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7293 emit_int8(0x0F);
7294 emit_int8((unsigned char)0xBE);
7295 emit_int8((unsigned char)(0xC0 | encode));
7296 }
7297
7298 void Assembler::movslq(Register dst, int32_t imm32) {
7299 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
7300 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
7301 // as a result we shouldn't use until tested at runtime...
7302 ShouldNotReachHere();
7303 InstructionMark im(this);
7304 int encode = prefixq_and_encode(dst->encoding());
7305 emit_int8((unsigned char)(0xC7 | encode));
7306 emit_int32(imm32);
7307 }
7308
7309 void Assembler::movslq(Address dst, int32_t imm32) {
7310 assert(is_simm32(imm32), "lost bits");
7311 InstructionMark im(this);
7312 prefixq(dst);
7313 emit_int8((unsigned char)0xC7);
7314 emit_operand(rax, dst, 4);
7315 emit_int32(imm32);
7316 }
7317
7318 void Assembler::movslq(Register dst, Address src) {
7319 InstructionMark im(this);
7320 prefixq(src, dst);
7321 emit_int8(0x63);
7322 emit_operand(dst, src);
7323 }
7324
7325 void Assembler::movslq(Register dst, Register src) {
7326 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7327 emit_int8(0x63);
7328 emit_int8((unsigned char)(0xC0 | encode));
7329 }
7330
7331 void Assembler::movswq(Register dst, Address src) {
7332 InstructionMark im(this);
7333 prefixq(src, dst);
7334 emit_int8(0x0F);
7335 emit_int8((unsigned char)0xBF);
7336 emit_operand(dst, src);
7337 }
7338
7339 void Assembler::movswq(Register dst, Register src) {
7340 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7341 emit_int8((unsigned char)0x0F);
7342 emit_int8((unsigned char)0xBF);
7343 emit_int8((unsigned char)(0xC0 | encode));
7344 }
7345
7346 void Assembler::movzbq(Register dst, Address src) {
7347 InstructionMark im(this);
7348 prefixq(src, dst);
7349 emit_int8((unsigned char)0x0F);
7350 emit_int8((unsigned char)0xB6);
7351 emit_operand(dst, src);
7352 }
7353
7354 void Assembler::movzbq(Register dst, Register src) {
7355 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7356 emit_int8(0x0F);
7357 emit_int8((unsigned char)0xB6);
7358 emit_int8(0xC0 | encode);
7359 }
7360
7361 void Assembler::movzwq(Register dst, Address src) {
7362 InstructionMark im(this);
7363 prefixq(src, dst);
7364 emit_int8((unsigned char)0x0F);
7365 emit_int8((unsigned char)0xB7);
7366 emit_operand(dst, src);
7367 }
7368
7369 void Assembler::movzwq(Register dst, Register src) {
7370 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7371 emit_int8((unsigned char)0x0F);
7372 emit_int8((unsigned char)0xB7);
7373 emit_int8((unsigned char)(0xC0 | encode));
7374 }
7375
7376 void Assembler::mulq(Address src) {
7377 InstructionMark im(this);
7378 prefixq(src);
7379 emit_int8((unsigned char)0xF7);
7380 emit_operand(rsp, src);
7381 }
7382
7383 void Assembler::mulq(Register src) {
7384 int encode = prefixq_and_encode(src->encoding());
7385 emit_int8((unsigned char)0xF7);
7386 emit_int8((unsigned char)(0xE0 | encode));
7387 }
7388
7389 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
7390 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
7391 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38,
7392 /* vex_w */ true, AVX_128bit, /* legacy_mode */ true, /* no_mask_reg */ false);
7393 emit_int8((unsigned char)0xF6);
7394 emit_int8((unsigned char)(0xC0 | encode));
7395 }
7396
7397 void Assembler::negq(Register dst) {
7398 int encode = prefixq_and_encode(dst->encoding());
7399 emit_int8((unsigned char)0xF7);
7400 emit_int8((unsigned char)(0xD8 | encode));
7401 }
7402
7403 void Assembler::notq(Register dst) {
7404 int encode = prefixq_and_encode(dst->encoding());
7405 emit_int8((unsigned char)0xF7);
7406 emit_int8((unsigned char)(0xD0 | encode));
7407 }
7408
7409 void Assembler::orq(Address dst, int32_t imm32) {
7410 InstructionMark im(this);
7411 prefixq(dst);
7412 emit_int8((unsigned char)0x81);
7413 emit_operand(rcx, dst, 4);
7414 emit_int32(imm32);
7415 }
7416
7417 void Assembler::orq(Register dst, int32_t imm32) {
7418 (void) prefixq_and_encode(dst->encoding());
7419 emit_arith(0x81, 0xC8, dst, imm32);
7420 }
7421
7422 void Assembler::orq(Register dst, Address src) {
7423 InstructionMark im(this);
7424 prefixq(src, dst);
7425 emit_int8(0x0B);
7426 emit_operand(dst, src);
7427 }
7428
7429 void Assembler::orq(Register dst, Register src) {
7430 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7431 emit_arith(0x0B, 0xC0, dst, src);
7432 }
7433
7434 void Assembler::popa() { // 64bit
7435 movq(r15, Address(rsp, 0));
7436 movq(r14, Address(rsp, wordSize));
7437 movq(r13, Address(rsp, 2 * wordSize));
7438 movq(r12, Address(rsp, 3 * wordSize));
7439 movq(r11, Address(rsp, 4 * wordSize));
7440 movq(r10, Address(rsp, 5 * wordSize));
7441 movq(r9, Address(rsp, 6 * wordSize));
7442 movq(r8, Address(rsp, 7 * wordSize));
7443 movq(rdi, Address(rsp, 8 * wordSize));
7444 movq(rsi, Address(rsp, 9 * wordSize));
7445 movq(rbp, Address(rsp, 10 * wordSize));
7446 // skip rsp
7447 movq(rbx, Address(rsp, 12 * wordSize));
7448 movq(rdx, Address(rsp, 13 * wordSize));
7449 movq(rcx, Address(rsp, 14 * wordSize));
7450 movq(rax, Address(rsp, 15 * wordSize));
7451
7452 addq(rsp, 16 * wordSize);
7453 }
7454
7455 void Assembler::popcntq(Register dst, Address src) {
7456 assert(VM_Version::supports_popcnt(), "must support");
7457 InstructionMark im(this);
7458 emit_int8((unsigned char)0xF3);
7459 prefixq(src, dst);
7460 emit_int8((unsigned char)0x0F);
7461 emit_int8((unsigned char)0xB8);
7462 emit_operand(dst, src);
7463 }
7464
7465 void Assembler::popcntq(Register dst, Register src) {
7466 assert(VM_Version::supports_popcnt(), "must support");
7467 emit_int8((unsigned char)0xF3);
7468 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7469 emit_int8((unsigned char)0x0F);
7470 emit_int8((unsigned char)0xB8);
7471 emit_int8((unsigned char)(0xC0 | encode));
7472 }
7473
7474 void Assembler::popq(Address dst) {
7475 InstructionMark im(this);
7476 prefixq(dst);
7477 emit_int8((unsigned char)0x8F);
7478 emit_operand(rax, dst);
7479 }
7480
7481 void Assembler::pusha() { // 64bit
7482 // we have to store original rsp. ABI says that 128 bytes
7483 // below rsp are local scratch.
7484 movq(Address(rsp, -5 * wordSize), rsp);
7485
7486 subq(rsp, 16 * wordSize);
7487
7488 movq(Address(rsp, 15 * wordSize), rax);
7489 movq(Address(rsp, 14 * wordSize), rcx);
7490 movq(Address(rsp, 13 * wordSize), rdx);
7491 movq(Address(rsp, 12 * wordSize), rbx);
7492 // skip rsp
7493 movq(Address(rsp, 10 * wordSize), rbp);
7494 movq(Address(rsp, 9 * wordSize), rsi);
7495 movq(Address(rsp, 8 * wordSize), rdi);
7496 movq(Address(rsp, 7 * wordSize), r8);
7497 movq(Address(rsp, 6 * wordSize), r9);
7498 movq(Address(rsp, 5 * wordSize), r10);
7499 movq(Address(rsp, 4 * wordSize), r11);
7500 movq(Address(rsp, 3 * wordSize), r12);
7501 movq(Address(rsp, 2 * wordSize), r13);
7502 movq(Address(rsp, wordSize), r14);
7503 movq(Address(rsp, 0), r15);
7504 }
7505
7506 void Assembler::pushq(Address src) {
7507 InstructionMark im(this);
7508 prefixq(src);
7509 emit_int8((unsigned char)0xFF);
7510 emit_operand(rsi, src);
7511 }
7512
7513 void Assembler::rclq(Register dst, int imm8) {
7514 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7515 int encode = prefixq_and_encode(dst->encoding());
7516 if (imm8 == 1) {
7517 emit_int8((unsigned char)0xD1);
7518 emit_int8((unsigned char)(0xD0 | encode));
7519 } else {
7520 emit_int8((unsigned char)0xC1);
7521 emit_int8((unsigned char)(0xD0 | encode));
7522 emit_int8(imm8);
7523 }
7524 }
7525
7526 void Assembler::rcrq(Register dst, int imm8) {
7527 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7528 int encode = prefixq_and_encode(dst->encoding());
7529 if (imm8 == 1) {
7530 emit_int8((unsigned char)0xD1);
7531 emit_int8((unsigned char)(0xD8 | encode));
7532 } else {
7533 emit_int8((unsigned char)0xC1);
7534 emit_int8((unsigned char)(0xD8 | encode));
7535 emit_int8(imm8);
7536 }
7537 }
7538
7539 void Assembler::rorq(Register dst, int imm8) {
7540 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7541 int encode = prefixq_and_encode(dst->encoding());
7542 if (imm8 == 1) {
7543 emit_int8((unsigned char)0xD1);
7544 emit_int8((unsigned char)(0xC8 | encode));
7545 } else {
7546 emit_int8((unsigned char)0xC1);
7547 emit_int8((unsigned char)(0xc8 | encode));
7548 emit_int8(imm8);
7549 }
7550 }
7551
7552 void Assembler::rorxq(Register dst, Register src, int imm8) {
7553 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
7554 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A,
7555 /* vex_w */ true, AVX_128bit, /* legacy_mode */ true, /* no_mask_reg */ false);
7556 emit_int8((unsigned char)0xF0);
7557 emit_int8((unsigned char)(0xC0 | encode));
7558 emit_int8(imm8);
7559 }
7560
7561 void Assembler::sarq(Register dst, int imm8) {
7562 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7563 int encode = prefixq_and_encode(dst->encoding());
7564 if (imm8 == 1) {
7565 emit_int8((unsigned char)0xD1);
7566 emit_int8((unsigned char)(0xF8 | encode));
7567 } else {
7568 emit_int8((unsigned char)0xC1);
7569 emit_int8((unsigned char)(0xF8 | encode));
7570 emit_int8(imm8);
7571 }
7572 }
7573
7574 void Assembler::sarq(Register dst) {
7575 int encode = prefixq_and_encode(dst->encoding());
7576 emit_int8((unsigned char)0xD3);
7577 emit_int8((unsigned char)(0xF8 | encode));
7578 }
7579
7580 void Assembler::sbbq(Address dst, int32_t imm32) {
7581 InstructionMark im(this);
7582 prefixq(dst);
7583 emit_arith_operand(0x81, rbx, dst, imm32);
7584 }
7585
7586 void Assembler::sbbq(Register dst, int32_t imm32) {
7587 (void) prefixq_and_encode(dst->encoding());
7588 emit_arith(0x81, 0xD8, dst, imm32);
7589 }
7590
7591 void Assembler::sbbq(Register dst, Address src) {
7592 InstructionMark im(this);
7593 prefixq(src, dst);
7594 emit_int8(0x1B);
7595 emit_operand(dst, src);
7596 }
7597
7598 void Assembler::sbbq(Register dst, Register src) {
7599 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7600 emit_arith(0x1B, 0xC0, dst, src);
7601 }
7602
7603 void Assembler::shlq(Register dst, int imm8) {
7604 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7605 int encode = prefixq_and_encode(dst->encoding());
7606 if (imm8 == 1) {
7607 emit_int8((unsigned char)0xD1);
7608 emit_int8((unsigned char)(0xE0 | encode));
7609 } else {
7610 emit_int8((unsigned char)0xC1);
7611 emit_int8((unsigned char)(0xE0 | encode));
7612 emit_int8(imm8);
7613 }
7614 }
7615
7616 void Assembler::shlq(Register dst) {
7617 int encode = prefixq_and_encode(dst->encoding());
7618 emit_int8((unsigned char)0xD3);
7619 emit_int8((unsigned char)(0xE0 | encode));
7620 }
7621
7622 void Assembler::shrq(Register dst, int imm8) {
7623 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7624 int encode = prefixq_and_encode(dst->encoding());
7625 emit_int8((unsigned char)0xC1);
7626 emit_int8((unsigned char)(0xE8 | encode));
7627 emit_int8(imm8);
7628 }
7629
7630 void Assembler::shrq(Register dst) {
7631 int encode = prefixq_and_encode(dst->encoding());
7632 emit_int8((unsigned char)0xD3);
7633 emit_int8(0xE8 | encode);
7634 }
7635
7636 void Assembler::subq(Address dst, int32_t imm32) {
7637 InstructionMark im(this);
7638 prefixq(dst);
7639 emit_arith_operand(0x81, rbp, dst, imm32);
7640 }
7641
7642 void Assembler::subq(Address dst, Register src) {
7643 InstructionMark im(this);
7644 prefixq(dst, src);
7645 emit_int8(0x29);
7646 emit_operand(src, dst);
7647 }
7648
7649 void Assembler::subq(Register dst, int32_t imm32) {
7650 (void) prefixq_and_encode(dst->encoding());
7651 emit_arith(0x81, 0xE8, dst, imm32);
7652 }
7653
7654 // Force generation of a 4 byte immediate value even if it fits into 8bit
7655 void Assembler::subq_imm32(Register dst, int32_t imm32) {
7656 (void) prefixq_and_encode(dst->encoding());
7657 emit_arith_imm32(0x81, 0xE8, dst, imm32);
7658 }
7659
7660 void Assembler::subq(Register dst, Address src) {
7661 InstructionMark im(this);
7662 prefixq(src, dst);
7663 emit_int8(0x2B);
7664 emit_operand(dst, src);
7665 }
7666
7667 void Assembler::subq(Register dst, Register src) {
7668 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7669 emit_arith(0x2B, 0xC0, dst, src);
7670 }
7671
7672 void Assembler::testq(Register dst, int32_t imm32) {
7673 // not using emit_arith because test
7674 // doesn't support sign-extension of
7675 // 8bit operands
7676 int encode = dst->encoding();
7677 if (encode == 0) {
7678 prefix(REX_W);
7679 emit_int8((unsigned char)0xA9);
7680 } else {
7681 encode = prefixq_and_encode(encode);
7682 emit_int8((unsigned char)0xF7);
7683 emit_int8((unsigned char)(0xC0 | encode));
7684 }
7685 emit_int32(imm32);
7686 }
7687
7688 void Assembler::testq(Register dst, Register src) {
7689 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7690 emit_arith(0x85, 0xC0, dst, src);
7691 }
7692
7693 void Assembler::xaddq(Address dst, Register src) {
7694 InstructionMark im(this);
7695 prefixq(dst, src);
7696 emit_int8(0x0F);
7697 emit_int8((unsigned char)0xC1);
7698 emit_operand(src, dst);
7699 }
7700
7701 void Assembler::xchgq(Register dst, Address src) {
7702 InstructionMark im(this);
7703 prefixq(src, dst);
7704 emit_int8((unsigned char)0x87);
7705 emit_operand(dst, src);
7706 }
7707
7708 void Assembler::xchgq(Register dst, Register src) {
7709 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7710 emit_int8((unsigned char)0x87);
7711 emit_int8((unsigned char)(0xc0 | encode));
7712 }
7713
7714 void Assembler::xorq(Register dst, Register src) {
7715 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7716 emit_arith(0x33, 0xC0, dst, src);
7717 }
7718
7719 void Assembler::xorq(Register dst, Address src) {
7720 InstructionMark im(this);
7721 prefixq(src, dst);
7722 emit_int8(0x33);
7723 emit_operand(dst, src);
7724 }
7725
7726 #endif // !LP64