1522 }
1523
1524 void Assembler::cmpl(Address dst, int32_t imm32) {
1525 InstructionMark im(this);
1526 prefix(dst);
1527 emit_int8((unsigned char)0x81);
1528 emit_operand(rdi, dst, 4);
1529 emit_int32(imm32);
1530 }
1531
1532 void Assembler::cmpl(Register dst, int32_t imm32) {
1533 prefix(dst);
1534 emit_arith(0x81, 0xF8, dst, imm32);
1535 }
1536
1537 void Assembler::cmpl(Register dst, Register src) {
1538 (void) prefix_and_encode(dst->encoding(), src->encoding());
1539 emit_arith(0x3B, 0xC0, dst, src);
1540 }
1541
1542
1543 void Assembler::cmpl(Register dst, Address src) {
1544 InstructionMark im(this);
1545 prefix(src, dst);
1546 emit_int8((unsigned char)0x3B);
1547 emit_operand(dst, src);
1548 }
1549
1550 void Assembler::cmpw(Address dst, int imm16) {
1551 InstructionMark im(this);
1552 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1553 emit_int8(0x66);
1554 emit_int8((unsigned char)0x81);
1555 emit_operand(rdi, dst, 2);
1556 emit_int16(imm16);
1557 }
1558
1559 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1560 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1561 // The ZF is set if the compared values were equal, and cleared otherwise.
1562 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
2108 } else {
2109 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE);
2110 }
2111 }
2112
2113 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2114 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2115 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, /* no_mask_reg */ true);
2116 emit_int8(0x16);
2117 emit_int8((unsigned char)(0xC0 | encode));
2118 }
2119
2120 void Assembler::movb(Register dst, Address src) {
2121 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2122 InstructionMark im(this);
2123 prefix(src, dst, true);
2124 emit_int8((unsigned char)0x8A);
2125 emit_operand(dst, src);
2126 }
2127
2128 void Assembler::kmovql(KRegister dst, KRegister src) {
2129 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2130 int encode = kreg_prefix_and_encode(dst, knoreg, src, VEX_SIMD_NONE,
2131 /* no_mask_reg */ true, VEX_OPCODE_0F, /* rex_w */ true);
2132 emit_int8((unsigned char)0x90);
2133 emit_int8((unsigned char)(0xC0 | encode));
2134 }
2135
2136 void Assembler::kmovql(KRegister dst, Address src) {
2137 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2138 int dst_enc = dst->encoding();
2139 int nds_enc = 0;
2140 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_NONE,
2141 VEX_OPCODE_0F, /* vex_w */ true, AVX_128bit, /* legacy_mode */ true, /* no_reg_mask */ true);
2142 emit_int8((unsigned char)0x90);
2143 emit_operand((Register)dst, src);
2144 }
2145
2146 void Assembler::kmovql(Address dst, KRegister src) {
2147 NOT_LP64(assert(VM_Version::supports_evex(), ""));
3384 void Assembler::pushl(Address src) {
3385 // Note this will push 64bit on 64bit
3386 InstructionMark im(this);
3387 prefix(src);
3388 emit_int8((unsigned char)0xFF);
3389 emit_operand(rsi, src);
3390 }
3391 #endif
3392
3393 void Assembler::rcll(Register dst, int imm8) {
3394 assert(isShiftCount(imm8), "illegal shift count");
3395 int encode = prefix_and_encode(dst->encoding());
3396 if (imm8 == 1) {
3397 emit_int8((unsigned char)0xD1);
3398 emit_int8((unsigned char)(0xD0 | encode));
3399 } else {
3400 emit_int8((unsigned char)0xC1);
3401 emit_int8((unsigned char)0xD0 | encode);
3402 emit_int8(imm8);
3403 }
3404 }
3405
3406 void Assembler::rdtsc() {
3407 emit_int8((unsigned char)0x0F);
3408 emit_int8((unsigned char)0x31);
3409 }
3410
3411 // copies data from [esi] to [edi] using rcx pointer sized words
3412 // generic
3413 void Assembler::rep_mov() {
3414 emit_int8((unsigned char)0xF3);
3415 // MOVSQ
3416 LP64_ONLY(prefix(REX_W));
3417 emit_int8((unsigned char)0xA5);
3418 }
3419
3420 // sets rcx bytes with rax, value at [edi]
3421 void Assembler::rep_stosb() {
3422 emit_int8((unsigned char)0xF3); // REP
3423 LP64_ONLY(prefix(REX_W));
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1522 }
1523
1524 void Assembler::cmpl(Address dst, int32_t imm32) {
1525 InstructionMark im(this);
1526 prefix(dst);
1527 emit_int8((unsigned char)0x81);
1528 emit_operand(rdi, dst, 4);
1529 emit_int32(imm32);
1530 }
1531
1532 void Assembler::cmpl(Register dst, int32_t imm32) {
1533 prefix(dst);
1534 emit_arith(0x81, 0xF8, dst, imm32);
1535 }
1536
1537 void Assembler::cmpl(Register dst, Register src) {
1538 (void) prefix_and_encode(dst->encoding(), src->encoding());
1539 emit_arith(0x3B, 0xC0, dst, src);
1540 }
1541
1542 void Assembler::cmpl(Register dst, Address src) {
1543 InstructionMark im(this);
1544 prefix(src, dst);
1545 emit_int8((unsigned char)0x3B);
1546 emit_operand(dst, src);
1547 }
1548
1549 void Assembler::cmpw(Address dst, int imm16) {
1550 InstructionMark im(this);
1551 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1552 emit_int8(0x66);
1553 emit_int8((unsigned char)0x81);
1554 emit_operand(rdi, dst, 2);
1555 emit_int16(imm16);
1556 }
1557
1558 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1559 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1560 // The ZF is set if the compared values were equal, and cleared otherwise.
1561 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
2107 } else {
2108 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE);
2109 }
2110 }
2111
2112 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2113 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2114 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, /* no_mask_reg */ true);
2115 emit_int8(0x16);
2116 emit_int8((unsigned char)(0xC0 | encode));
2117 }
2118
2119 void Assembler::movb(Register dst, Address src) {
2120 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2121 InstructionMark im(this);
2122 prefix(src, dst, true);
2123 emit_int8((unsigned char)0x8A);
2124 emit_operand(dst, src);
2125 }
2126
2127 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2128 _instruction_uses_vl = true;
2129 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2130 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, /* no_mask_reg */ false, VEX_OPCODE_0F,
2131 /* rex_w */ VM_Version::supports_evex(), AVX_128bit, /* legacy_mode */ false);
2132 emit_int8(0x12);
2133 emit_int8(0xC0 | encode);
2134
2135 }
2136
2137 void Assembler::kmovql(KRegister dst, KRegister src) {
2138 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2139 int encode = kreg_prefix_and_encode(dst, knoreg, src, VEX_SIMD_NONE,
2140 /* no_mask_reg */ true, VEX_OPCODE_0F, /* rex_w */ true);
2141 emit_int8((unsigned char)0x90);
2142 emit_int8((unsigned char)(0xC0 | encode));
2143 }
2144
2145 void Assembler::kmovql(KRegister dst, Address src) {
2146 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2147 int dst_enc = dst->encoding();
2148 int nds_enc = 0;
2149 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_NONE,
2150 VEX_OPCODE_0F, /* vex_w */ true, AVX_128bit, /* legacy_mode */ true, /* no_reg_mask */ true);
2151 emit_int8((unsigned char)0x90);
2152 emit_operand((Register)dst, src);
2153 }
2154
2155 void Assembler::kmovql(Address dst, KRegister src) {
2156 NOT_LP64(assert(VM_Version::supports_evex(), ""));
3393 void Assembler::pushl(Address src) {
3394 // Note this will push 64bit on 64bit
3395 InstructionMark im(this);
3396 prefix(src);
3397 emit_int8((unsigned char)0xFF);
3398 emit_operand(rsi, src);
3399 }
3400 #endif
3401
3402 void Assembler::rcll(Register dst, int imm8) {
3403 assert(isShiftCount(imm8), "illegal shift count");
3404 int encode = prefix_and_encode(dst->encoding());
3405 if (imm8 == 1) {
3406 emit_int8((unsigned char)0xD1);
3407 emit_int8((unsigned char)(0xD0 | encode));
3408 } else {
3409 emit_int8((unsigned char)0xC1);
3410 emit_int8((unsigned char)0xD0 | encode);
3411 emit_int8(imm8);
3412 }
3413 }
3414
3415 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
3416 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3417 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, /* no_mask_reg */ false, VEX_OPCODE_0F, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
3418 emit_int8(0x53);
3419 emit_int8(0xC0 | encode);
3420 }
3421
3422 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
3423 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3424 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, /* no_mask_reg */ false, VEX_OPCODE_0F, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
3425 emit_int8(0x53);
3426 emit_int8(0xC0 | encode);
3427 }
3428
3429 void Assembler::rdtsc() {
3430 emit_int8((unsigned char)0x0F);
3431 emit_int8((unsigned char)0x31);
3432 }
3433
3434 // copies data from [esi] to [edi] using rcx pointer sized words
3435 // generic
3436 void Assembler::rep_mov() {
3437 emit_int8((unsigned char)0xF3);
3438 // MOVSQ
3439 LP64_ONLY(prefix(REX_W));
3440 emit_int8((unsigned char)0xA5);
3441 }
3442
3443 // sets rcx bytes with rax, value at [edi]
3444 void Assembler::rep_stosb() {
3445 emit_int8((unsigned char)0xF3); // REP
3446 LP64_ONLY(prefix(REX_W));
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