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src/cpu/x86/vm/c1_LIRAssembler_x86.cpp

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2423   if (value->is_double_xmm()) {
2424     switch(code) {
2425       case lir_abs :
2426         {
2427           if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2428             __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2429           }
2430           __ andpd(dest->as_xmm_double_reg(),
2431                     ExternalAddress((address)double_signmask_pool));
2432         }
2433         break;
2434 
2435       case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2436       // all other intrinsics are not available in the SSE instruction set, so FPU is used
2437       default      : ShouldNotReachHere();
2438     }
2439 
2440   } else if (value->is_double_fpu()) {
2441     assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2442     switch(code) {
2443       case lir_log   : __ flog() ; break;
2444       case lir_log10 : __ flog10() ; break;
2445       case lir_abs   : __ fabs() ; break;
2446       case lir_sqrt  : __ fsqrt(); break;
2447       case lir_sin   :
2448         // Should consider not saving rbx, if not necessary
2449         __ trigfunc('s', op->as_Op2()->fpu_stack_size());
2450         break;
2451       case lir_cos :
2452         // Should consider not saving rbx, if not necessary
2453         assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots");
2454         __ trigfunc('c', op->as_Op2()->fpu_stack_size());
2455         break;
2456       case lir_tan :
2457         // Should consider not saving rbx, if not necessary
2458         __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2459         break;
2460       case lir_pow :
2461         __ pow_with_fallback(op->as_Op2()->fpu_stack_size());
2462         break;
2463       default      : ShouldNotReachHere();




2423   if (value->is_double_xmm()) {
2424     switch(code) {
2425       case lir_abs :
2426         {
2427           if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2428             __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2429           }
2430           __ andpd(dest->as_xmm_double_reg(),
2431                     ExternalAddress((address)double_signmask_pool));
2432         }
2433         break;
2434 
2435       case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2436       // all other intrinsics are not available in the SSE instruction set, so FPU is used
2437       default      : ShouldNotReachHere();
2438     }
2439 
2440   } else if (value->is_double_fpu()) {
2441     assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2442     switch(code) {

2443       case lir_log10 : __ flog10() ; break;
2444       case lir_abs   : __ fabs() ; break;
2445       case lir_sqrt  : __ fsqrt(); break;
2446       case lir_sin   :
2447         // Should consider not saving rbx, if not necessary
2448         __ trigfunc('s', op->as_Op2()->fpu_stack_size());
2449         break;
2450       case lir_cos :
2451         // Should consider not saving rbx, if not necessary
2452         assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots");
2453         __ trigfunc('c', op->as_Op2()->fpu_stack_size());
2454         break;
2455       case lir_tan :
2456         // Should consider not saving rbx, if not necessary
2457         __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2458         break;
2459       case lir_pow :
2460         __ pow_with_fallback(op->as_Op2()->fpu_stack_size());
2461         break;
2462       default      : ShouldNotReachHere();


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