296 }
297 }
298
299
300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
301 assert(isByte(op1) && isByte(op2), "wrong opcode");
302 emit_int8(op1);
303 emit_int8(op2 | encode(dst) << 3 | encode(src));
304 }
305
306
307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
309 int mod_idx = 0;
310 // We will test if the displacement fits the compressed format and if so
311 // apply the compression to the displacment iff the result is8bit.
312 if (VM_Version::supports_evex() && is_evex_inst) {
313 switch (cur_tuple_type) {
314 case EVEX_FV:
315 if ((cur_encoding & VEX_W) == VEX_W) {
316 mod_idx += 2 + ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
317 } else {
318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
319 }
320 break;
321
322 case EVEX_HV:
323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
324 break;
325
326 case EVEX_FVM:
327 break;
328
329 case EVEX_T1S:
330 switch (in_size_in_bits) {
331 case EVEX_8bit:
332 break;
333
334 case EVEX_16bit:
335 mod_idx = 1;
336 break;
377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
379 if ((disp % disp_factor) == 0) {
380 int new_disp = disp / disp_factor;
381 if ((-0x80 <= new_disp && new_disp < 0x80)) {
382 disp = new_disp;
383 }
384 } else {
385 return false;
386 }
387 }
388 }
389 return (-0x80 <= disp && disp < 0x80);
390 }
391
392
393 bool Assembler::emit_compressed_disp_byte(int &disp) {
394 int mod_idx = 0;
395 // We will test if the displacement fits the compressed format and if so
396 // apply the compression to the displacment iff the result is8bit.
397 if (VM_Version::supports_evex() && _is_evex_instruction) {
398 switch (_tuple_type) {
399 case EVEX_FV:
400 if ((_evex_encoding & VEX_W) == VEX_W) {
401 mod_idx += 2 + ((_evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
402 } else {
403 mod_idx = ((_evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
404 }
405 break;
406
407 case EVEX_HV:
408 mod_idx = ((_evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
409 break;
410
411 case EVEX_FVM:
412 break;
413
414 case EVEX_T1S:
415 switch (_input_size_in_bits) {
416 case EVEX_8bit:
417 break;
418
419 case EVEX_16bit:
420 mod_idx = 1;
421 break;
422
423 case EVEX_32bit:
424 mod_idx = 2;
425 break;
426
427 case EVEX_64bit:
428 mod_idx = 3;
429 break;
430 }
431 break;
432
433 case EVEX_T1F:
434 case EVEX_T2:
435 case EVEX_T4:
436 mod_idx = (_input_size_in_bits == EVEX_64bit) ? 1 : 0;
437 break;
438
439 case EVEX_T8:
440 break;
441
442 case EVEX_HVM:
443 break;
444
445 case EVEX_QVM:
446 break;
447
448 case EVEX_OVM:
449 break;
450
451 case EVEX_M128:
452 break;
453
454 case EVEX_DUP:
455 break;
456
457 default:
458 assert(0, "no valid evex tuple_table entry");
459 break;
460 }
461
462 if (_avx_vector_len >= AVX_128bit && _avx_vector_len <= AVX_512bit) {
463 int disp_factor = tuple_table[_tuple_type + mod_idx][_avx_vector_len];
464 if ((disp % disp_factor) == 0) {
465 int new_disp = disp / disp_factor;
466 if (is8bit(new_disp)) {
467 disp = new_disp;
468 }
469 } else {
470 return false;
471 }
472 }
473 }
474 return is8bit(disp);
475 }
476
477
478 void Assembler::emit_operand(Register reg, Register base, Register index,
479 Address::ScaleFactor scale, int disp,
480 RelocationHolder const& rspec,
481 int rip_relative_correction) {
482 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
483
574 // at the start of the instruction. That needs more correction here.
575 // intptr_t disp = target - next_ip;
576 assert(inst_mark() != NULL, "must be inside InstructionMark");
577 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
578 int64_t adjusted = disp;
579 // Do rip-rel adjustment for 64bit
580 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
581 assert(is_simm32(adjusted),
582 "must be 32bit offset (RIP relative address)");
583 emit_data((int32_t) adjusted, rspec, disp32_operand);
584
585 } else {
586 // 32bit never did this, did everything as the rip-rel/disp code above
587 // [disp] ABSOLUTE
588 // [00 reg 100][00 100 101] disp32
589 emit_int8(0x04 | regenc);
590 emit_int8(0x25);
591 emit_data(disp, rspec, disp32_operand);
592 }
593 }
594 _is_evex_instruction = false;
595 }
596
597 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
598 Address::ScaleFactor scale, int disp,
599 RelocationHolder const& rspec) {
600 if (UseAVX > 2) {
601 int xreg_enc = reg->encoding();
602 if (xreg_enc > 15) {
603 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
604 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
605 return;
606 }
607 }
608 emit_operand((Register)reg, base, index, scale, disp, rspec);
609 }
610
611 // Secret local extension to Assembler::WhichOperand:
612 #define end_pc_operand (_WhichOperand_limit)
613
614 address Assembler::locate_operand(address inst, WhichOperand which) {
753 tail_size = 1;
754 case 0x38: // ptest, pmovzxbw
755 ip++; // skip opcode
756 debug_only(has_disp32 = true); // has both kinds of operands!
757 break;
758
759 case 0x70: // pshufd r, r/a, #8
760 debug_only(has_disp32 = true); // has both kinds of operands!
761 case 0x73: // psrldq r, #8
762 tail_size = 1;
763 break;
764
765 case 0x12: // movlps
766 case 0x28: // movaps
767 case 0x2E: // ucomiss
768 case 0x2F: // comiss
769 case 0x54: // andps
770 case 0x55: // andnps
771 case 0x56: // orps
772 case 0x57: // xorps
773 case 0x59: //mulpd
774 case 0x6E: // movd
775 case 0x7E: // movd
776 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
777 debug_only(has_disp32 = true);
778 break;
779
780 case 0xAD: // shrd r, a, %cl
781 case 0xAF: // imul r, a
782 case 0xBE: // movsbl r, a (movsxb)
783 case 0xBF: // movswl r, a (movsxw)
784 case 0xB6: // movzbl r, a (movzxb)
785 case 0xB7: // movzwl r, a (movzxw)
786 case REP16(0x40): // cmovl cc, r, a
787 case 0xB0: // cmpxchgb
788 case 0xB1: // cmpxchg
789 case 0xC1: // xaddl
790 case 0xC7: // cmpxchg8
791 case REP16(0x90): // setcc a
792 debug_only(has_disp32 = true);
793 // fall out of the switch to decode the address
1217 emit_int8(0x0F);
1218 emit_int8(0x1F);
1219 emit_int8((unsigned char)0x80);
1220 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1221 emit_int32(0); // 32-bits offset (4 bytes)
1222 }
1223
1224 void Assembler::addr_nop_8() {
1225 assert(UseAddressNop, "no CPU support");
1226 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1227 emit_int8(0x0F);
1228 emit_int8(0x1F);
1229 emit_int8((unsigned char)0x84);
1230 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1231 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1232 emit_int32(0); // 32-bits offset (4 bytes)
1233 }
1234
1235 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1236 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1237 if (VM_Version::supports_evex()) {
1238 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_F2);
1239 } else {
1240 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
1241 }
1242 }
1243
1244 void Assembler::addsd(XMMRegister dst, Address src) {
1245 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1246 if (VM_Version::supports_evex()) {
1247 _tuple_type = EVEX_T1S;
1248 _input_size_in_bits = EVEX_64bit;
1249 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_F2);
1250 } else {
1251 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
1252 }
1253 }
1254
1255 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1256 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1257 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1258 }
1259
1260 void Assembler::addss(XMMRegister dst, Address src) {
1261 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1262 if (VM_Version::supports_evex()) {
1263 _tuple_type = EVEX_T1S;
1264 _input_size_in_bits = EVEX_32bit;
1265 }
1266 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1267 }
1268
1269 void Assembler::aesdec(XMMRegister dst, Address src) {
1270 assert(VM_Version::supports_aes(), "");
1271 InstructionMark im(this);
1272 simd_prefix(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
1273 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
1274 emit_int8((unsigned char)0xDE);
1275 emit_operand(dst, src);
1276 }
1277
1278 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1279 assert(VM_Version::supports_aes(), "");
1280 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
1281 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
1282 emit_int8((unsigned char)0xDE);
1283 emit_int8(0xC0 | encode);
1284 }
1285
1286 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1287 assert(VM_Version::supports_aes(), "");
1288 InstructionMark im(this);
1289 simd_prefix(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
1290 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
1291 emit_int8((unsigned char)0xDF);
1292 emit_operand(dst, src);
1293 }
1294
1295 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1296 assert(VM_Version::supports_aes(), "");
1297 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
1298 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
1299 emit_int8((unsigned char)0xDF);
1300 emit_int8((unsigned char)(0xC0 | encode));
1301 }
1302
1303 void Assembler::aesenc(XMMRegister dst, Address src) {
1304 assert(VM_Version::supports_aes(), "");
1305 InstructionMark im(this);
1306 simd_prefix(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
1307 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
1308 emit_int8((unsigned char)0xDC);
1309 emit_operand(dst, src);
1310 }
1311
1312 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1313 assert(VM_Version::supports_aes(), "");
1314 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
1315 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
1316 emit_int8((unsigned char)0xDC);
1317 emit_int8(0xC0 | encode);
1318 }
1319
1320 void Assembler::aesenclast(XMMRegister dst, Address src) {
1321 assert(VM_Version::supports_aes(), "");
1322 InstructionMark im(this);
1323 simd_prefix(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
1324 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
1325 emit_int8((unsigned char)0xDD);
1326 emit_operand(dst, src);
1327 }
1328
1329 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1330 assert(VM_Version::supports_aes(), "");
1331 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
1332 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
1333 emit_int8((unsigned char)0xDD);
1334 emit_int8((unsigned char)(0xC0 | encode));
1335 }
1336
1337 void Assembler::andl(Address dst, int32_t imm32) {
1338 InstructionMark im(this);
1339 prefix(dst);
1340 emit_int8((unsigned char)0x81);
1341 emit_operand(rsp, dst, 4);
1342 emit_int32(imm32);
1343 }
1344
1345 void Assembler::andl(Register dst, int32_t imm32) {
1346 prefix(dst);
1347 emit_arith(0x81, 0xE0, dst, imm32);
1348 }
1349
1350 void Assembler::andl(Register dst, Address src) {
1351 InstructionMark im(this);
1352 prefix(src, dst);
1353 emit_int8(0x23);
1354 emit_operand(dst, src);
1355 }
1356
1357 void Assembler::andl(Register dst, Register src) {
1358 (void) prefix_and_encode(dst->encoding(), src->encoding());
1359 emit_arith(0x23, 0xC0, dst, src);
1360 }
1361
1362 void Assembler::andnl(Register dst, Register src1, Register src2) {
1363 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1364 int encode = vex_prefix_0F38_and_encode_legacy(dst, src1, src2);
1365 emit_int8((unsigned char)0xF2);
1366 emit_int8((unsigned char)(0xC0 | encode));
1367 }
1368
1369 void Assembler::andnl(Register dst, Register src1, Address src2) {
1370 InstructionMark im(this);
1371 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1372 vex_prefix_0F38_legacy(dst, src1, src2);
1373 emit_int8((unsigned char)0xF2);
1374 emit_operand(dst, src2);
1375 }
1376
1377 void Assembler::bsfl(Register dst, Register src) {
1378 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1379 emit_int8(0x0F);
1380 emit_int8((unsigned char)0xBC);
1381 emit_int8((unsigned char)(0xC0 | encode));
1382 }
1383
1384 void Assembler::bsrl(Register dst, Register src) {
1385 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1386 emit_int8(0x0F);
1387 emit_int8((unsigned char)0xBD);
1388 emit_int8((unsigned char)(0xC0 | encode));
1389 }
1390
1391 void Assembler::bswapl(Register reg) { // bswap
1392 int encode = prefix_and_encode(reg->encoding());
1393 emit_int8(0x0F);
1394 emit_int8((unsigned char)(0xC8 | encode));
1395 }
1396
1397 void Assembler::blsil(Register dst, Register src) {
1398 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1399 int encode = vex_prefix_0F38_and_encode_legacy(rbx, dst, src);
1400 emit_int8((unsigned char)0xF3);
1401 emit_int8((unsigned char)(0xC0 | encode));
1402 }
1403
1404 void Assembler::blsil(Register dst, Address src) {
1405 InstructionMark im(this);
1406 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1407 vex_prefix_0F38_legacy(rbx, dst, src);
1408 emit_int8((unsigned char)0xF3);
1409 emit_operand(rbx, src);
1410 }
1411
1412 void Assembler::blsmskl(Register dst, Register src) {
1413 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1414 int encode = vex_prefix_0F38_and_encode_legacy(rdx, dst, src);
1415 emit_int8((unsigned char)0xF3);
1416 emit_int8((unsigned char)(0xC0 | encode));
1417 }
1418
1419 void Assembler::blsmskl(Register dst, Address src) {
1420 InstructionMark im(this);
1421 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1422 vex_prefix_0F38_legacy(rdx, dst, src);
1423 emit_int8((unsigned char)0xF3);
1424 emit_operand(rdx, src);
1425 }
1426
1427 void Assembler::blsrl(Register dst, Register src) {
1428 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1429 int encode = vex_prefix_0F38_and_encode_legacy(rcx, dst, src);
1430 emit_int8((unsigned char)0xF3);
1431 emit_int8((unsigned char)(0xC0 | encode));
1432 }
1433
1434 void Assembler::blsrl(Register dst, Address src) {
1435 InstructionMark im(this);
1436 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1437 vex_prefix_0F38_legacy(rcx, dst, src);
1438 emit_int8((unsigned char)0xF3);
1439 emit_operand(rcx, src);
1440 }
1441
1442 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1443 // suspect disp32 is always good
1444 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1445
1446 if (L.is_bound()) {
1447 const int long_size = 5;
1448 int offs = (int)( target(L) - pc() );
1449 assert(offs <= 0, "assembler error");
1450 InstructionMark im(this);
1451 // 1110 1000 #32-bit disp
1452 emit_int8((unsigned char)0xE8);
1453 emit_data(offs - long_size, rtype, operand);
1454 } else {
1455 InstructionMark im(this);
1456 // 1110 1000 #32-bit disp
1457 L.add_patch_at(code(), locator());
1564 emit_int8(0x0F);
1565 emit_int8((unsigned char)0xB1);
1566 emit_operand(reg, adr);
1567 }
1568
1569 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1570 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1571 // The ZF is set if the compared values were equal, and cleared otherwise.
1572 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1573 InstructionMark im(this);
1574 prefix(adr, reg, true);
1575 emit_int8(0x0F);
1576 emit_int8((unsigned char)0xB0);
1577 emit_operand(reg, adr);
1578 }
1579
1580 void Assembler::comisd(XMMRegister dst, Address src) {
1581 // NOTE: dbx seems to decode this as comiss even though the
1582 // 0x66 is there. Strangly ucomisd comes out correct
1583 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1584 if (VM_Version::supports_evex()) {
1585 _tuple_type = EVEX_T1S;
1586 _input_size_in_bits = EVEX_64bit;
1587 emit_simd_arith_nonds_q(0x2F, dst, src, VEX_SIMD_66, /* no_mask_reg */ true);
1588 } else {
1589 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1590 }
1591 }
1592
1593 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1594 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1595 if (VM_Version::supports_evex()) {
1596 emit_simd_arith_nonds_q(0x2F, dst, src, VEX_SIMD_66, /* no_mask_reg */ true);
1597 } else {
1598 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1599 }
1600 }
1601
1602 void Assembler::comiss(XMMRegister dst, Address src) {
1603 if (VM_Version::supports_evex()) {
1604 _tuple_type = EVEX_T1S;
1605 _input_size_in_bits = EVEX_32bit;
1606 }
1607 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1608 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE, /* no_mask_reg */ true);
1609 }
1610
1611 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1612 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1613 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE, /* no_mask_reg */ true);
1614 }
1615
1616 void Assembler::cpuid() {
1617 emit_int8(0x0F);
1618 emit_int8((unsigned char)0xA2);
1619 }
1620
1621 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1622 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1623 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1624 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1625 //
1626 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1627 //
1628 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1629 //
1630 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1631 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1632 assert(VM_Version::supports_sse4_2(), "");
1633 int8_t w = 0x01;
1682 case 2:
1683 case 4:
1684 break;
1685 LP64_ONLY(case 8:)
1686 // This instruction is not valid in 32 bits
1687 p = REX_W;
1688 break;
1689 default:
1690 assert(0, "Unsupported value for a sizeInBytes argument");
1691 break;
1692 }
1693 LP64_ONLY(prefix(crc, adr, p);)
1694 emit_int8((int8_t)0x0F);
1695 emit_int8(0x38);
1696 emit_int8((int8_t)(0xF0 | w));
1697 emit_operand(crc, adr);
1698 }
1699
1700 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1701 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1702 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3, /* no_mask_reg */ false, /* legacy_mode */ true);
1703 }
1704
1705 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1706 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1707 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE, /* no_mask_reg */ false, /* legacy_mode */ true);
1708 }
1709
1710 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1711 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1712 if (VM_Version::supports_evex()) {
1713 emit_simd_arith_q(0x5A, dst, src, VEX_SIMD_F2);
1714 } else {
1715 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1716 }
1717 }
1718
1719 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1720 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1721 if (VM_Version::supports_evex()) {
1722 _tuple_type = EVEX_T1F;
1723 _input_size_in_bits = EVEX_64bit;
1724 emit_simd_arith_q(0x5A, dst, src, VEX_SIMD_F2);
1725 } else {
1726 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1727 }
1728 }
1729
1730 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1731 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1732 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VM_Version::supports_evex());
1733 emit_int8(0x2A);
1734 emit_int8((unsigned char)(0xC0 | encode));
1735 }
1736
1737 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1738 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1739 if (VM_Version::supports_evex()) {
1740 _tuple_type = EVEX_T1S;
1741 _input_size_in_bits = EVEX_32bit;
1742 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2, /* no_mask_reg */ true);
1743 } else {
1744 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2);
1745 }
1746 }
1747
1748 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1749 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1750 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, /* no_mask_reg */ true);
1751 emit_int8(0x2A);
1752 emit_int8((unsigned char)(0xC0 | encode));
1753 }
1754
1755 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1756 if (VM_Version::supports_evex()) {
1757 _tuple_type = EVEX_T1S;
1758 _input_size_in_bits = EVEX_32bit;
1759 }
1760 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1761 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3, /* no_mask_reg */ true);
1762 }
1763
1764 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1765 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1766 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3, /* no_mask_reg */ true);
1767 emit_int8(0x2A);
1768 emit_int8((unsigned char)(0xC0 | encode));
1769 }
1770
1771 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1772 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1773 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1774 }
1775
1776 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1777 if (VM_Version::supports_evex()) {
1778 _tuple_type = EVEX_T1S;
1779 _input_size_in_bits = EVEX_32bit;
1780 }
1781 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1782 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1783 }
1784
1785
1786 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1787 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1788 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, /* no_mask_reg */ true);
1789 emit_int8(0x2C);
1790 emit_int8((unsigned char)(0xC0 | encode));
1791 }
1792
1793 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1794 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1795 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, /* no_mask_reg */ true);
1796 emit_int8(0x2C);
1797 emit_int8((unsigned char)(0xC0 | encode));
1798 }
1799
1800 void Assembler::decl(Address dst) {
1801 // Don't use it directly. Use MacroAssembler::decrement() instead.
1802 InstructionMark im(this);
1803 prefix(dst);
1804 emit_int8((unsigned char)0xFF);
1805 emit_operand(rcx, dst);
1806 }
1807
1808 void Assembler::divsd(XMMRegister dst, Address src) {
1809 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1810 if (VM_Version::supports_evex()) {
1811 _tuple_type = EVEX_T1S;
1812 _input_size_in_bits = EVEX_64bit;
1813 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_F2);
1814 } else {
1815 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1816 }
1817 }
1818
1819 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1820 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1821 if (VM_Version::supports_evex()) {
1822 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_F2);
1823 } else {
1824 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1825 }
1826 }
1827
1828 void Assembler::divss(XMMRegister dst, Address src) {
1829 if (VM_Version::supports_evex()) {
1830 _tuple_type = EVEX_T1S;
1831 _input_size_in_bits = EVEX_32bit;
1832 }
1833 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1834 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1835 }
1836
1837 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1838 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1839 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1840 }
1841
1842 void Assembler::emms() {
1843 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1844 emit_int8(0x0F);
1845 emit_int8(0x77);
1846 }
1847
1848 void Assembler::hlt() {
1849 emit_int8((unsigned char)0xF4);
1850 }
1851
1852 void Assembler::idivl(Register src) {
1853 int encode = prefix_and_encode(src->encoding());
1854 emit_int8((unsigned char)0xF7);
1855 emit_int8((unsigned char)(0xF8 | encode));
1856 }
1857
1858 void Assembler::divl(Register src) { // Unsigned
1859 int encode = prefix_and_encode(src->encoding());
2065 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2066 emit_int8(0x0F);
2067 emit_int8((unsigned char)0xBD);
2068 emit_int8((unsigned char)(0xC0 | encode));
2069 }
2070
2071 // Emit mfence instruction
2072 void Assembler::mfence() {
2073 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2074 emit_int8(0x0F);
2075 emit_int8((unsigned char)0xAE);
2076 emit_int8((unsigned char)0xF0);
2077 }
2078
2079 void Assembler::mov(Register dst, Register src) {
2080 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2081 }
2082
2083 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2084 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2085 if (VM_Version::supports_avx512novl()) {
2086 int vector_len = AVX_512bit;
2087 int dst_enc = dst->encoding();
2088 int src_enc = src->encoding();
2089 int encode = vex_prefix_and_encode(dst_enc, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F,
2090 /* vex_w */ true, vector_len, /* legacy_mode */ false, /* no_mask_reg */ false);
2091 emit_int8(0x28);
2092 emit_int8((unsigned char)(0xC0 | encode));
2093 } else if (VM_Version::supports_evex()) {
2094 emit_simd_arith_nonds_q(0x28, dst, src, VEX_SIMD_66);
2095 } else {
2096 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66);
2097 }
2098 }
2099
2100 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2101 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2102 if (VM_Version::supports_avx512novl()) {
2103 int vector_len = AVX_512bit;
2104 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, vector_len);
2105 emit_int8(0x28);
2106 emit_int8((unsigned char)(0xC0 | encode));
2107 } else {
2108 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE);
2109 }
2110 }
2111
2112 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2113 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2114 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, /* no_mask_reg */ true);
2115 emit_int8(0x16);
2116 emit_int8((unsigned char)(0xC0 | encode));
2117 }
2118
2119 void Assembler::movb(Register dst, Address src) {
2120 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2121 InstructionMark im(this);
2122 prefix(src, dst, true);
2123 emit_int8((unsigned char)0x8A);
2124 emit_operand(dst, src);
2125 }
2126
2127 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2128 _instruction_uses_vl = true;
2129 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2130 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, /* no_mask_reg */ false, VEX_OPCODE_0F,
2131 /* rex_w */ VM_Version::supports_evex(), AVX_128bit, /* legacy_mode */ false);
2132 emit_int8(0x12);
2133 emit_int8(0xC0 | encode);
2134
2135 }
2136
2137 void Assembler::kmovql(KRegister dst, KRegister src) {
2138 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2139 int encode = kreg_prefix_and_encode(dst, knoreg, src, VEX_SIMD_NONE,
2140 /* no_mask_reg */ true, VEX_OPCODE_0F, /* rex_w */ true);
2141 emit_int8((unsigned char)0x90);
2142 emit_int8((unsigned char)(0xC0 | encode));
2143 }
2144
2145 void Assembler::kmovql(KRegister dst, Address src) {
2146 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2147 int dst_enc = dst->encoding();
2148 int nds_enc = 0;
2149 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_NONE,
2150 VEX_OPCODE_0F, /* vex_w */ true, AVX_128bit, /* legacy_mode */ true, /* no_reg_mask */ true);
2151 emit_int8((unsigned char)0x90);
2152 emit_operand((Register)dst, src);
2153 }
2154
2155 void Assembler::kmovql(Address dst, KRegister src) {
2156 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2157 int src_enc = src->encoding();
2158 int nds_enc = 0;
2159 vex_prefix(dst, nds_enc, src_enc, VEX_SIMD_NONE,
2160 VEX_OPCODE_0F, /* vex_w */ true, AVX_128bit, /* legacy_mode */ true, /* no_reg_mask */ true);
2161 emit_int8((unsigned char)0x90);
2162 emit_operand((Register)src, dst);
2163 }
2164
2165 void Assembler::kmovql(KRegister dst, Register src) {
2166 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2167 VexSimdPrefix pre = !_legacy_mode_bw ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2168 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, /* no_mask_reg */ true,
2169 VEX_OPCODE_0F, /* legacy_mode */ !_legacy_mode_bw);
2170 emit_int8((unsigned char)0x92);
2171 emit_int8((unsigned char)(0xC0 | encode));
2172 }
2173
2174 void Assembler::kmovdl(KRegister dst, Register src) {
2175 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2176 VexSimdPrefix pre = !_legacy_mode_bw ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2177 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, /* no_mask_reg */ true);
2178 emit_int8((unsigned char)0x92);
2179 emit_int8((unsigned char)(0xC0 | encode));
2180 }
2181
2182 void Assembler::kmovwl(KRegister dst, Register src) {
2183 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2184 int encode = kreg_prefix_and_encode(dst, knoreg, src, VEX_SIMD_NONE, /* no_mask_reg */ true);
2185 emit_int8((unsigned char)0x92);
2186 emit_int8((unsigned char)(0xC0 | encode));
2187 }
2188
2189 void Assembler::movb(Address dst, int imm8) {
2190 InstructionMark im(this);
2191 prefix(dst);
2192 emit_int8((unsigned char)0xC6);
2193 emit_operand(rax, dst, 1);
2194 emit_int8(imm8);
2195 }
2196
2197
2198 void Assembler::movb(Address dst, Register src) {
2199 assert(src->has_byte_register(), "must have byte register");
2200 InstructionMark im(this);
2201 prefix(dst, src, true);
2202 emit_int8((unsigned char)0x88);
2203 emit_operand(src, dst);
2204 }
2205
2206 void Assembler::movdl(XMMRegister dst, Register src) {
2207 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2208 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, /* no_mask_reg */ true);
2209 emit_int8(0x6E);
2210 emit_int8((unsigned char)(0xC0 | encode));
2211 }
2212
2213 void Assembler::movdl(Register dst, XMMRegister src) {
2214 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2215 // swap src/dst to get correct prefix
2216 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66, /* no_mask_reg */ true);
2217 emit_int8(0x7E);
2218 emit_int8((unsigned char)(0xC0 | encode));
2219 }
2220
2221 void Assembler::movdl(XMMRegister dst, Address src) {
2222 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2223 if (VM_Version::supports_evex()) {
2224 _tuple_type = EVEX_T1S;
2225 _input_size_in_bits = EVEX_32bit;
2226 }
2227 InstructionMark im(this);
2228 simd_prefix(dst, src, VEX_SIMD_66, /* no_reg_mask */ true);
2229 emit_int8(0x6E);
2230 emit_operand(dst, src);
2231 }
2232
2233 void Assembler::movdl(Address dst, XMMRegister src) {
2234 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2235 if (VM_Version::supports_evex()) {
2236 _tuple_type = EVEX_T1S;
2237 _input_size_in_bits = EVEX_32bit;
2238 }
2239 InstructionMark im(this);
2240 simd_prefix(dst, src, VEX_SIMD_66, /* no_reg_mask */ true);
2241 emit_int8(0x7E);
2242 emit_operand(src, dst);
2243 }
2244
2245 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2246 _instruction_uses_vl = true;
2247 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2248 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
2249 }
2250
2251 void Assembler::movdqa(XMMRegister dst, Address src) {
2252 _instruction_uses_vl = true;
2253 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2254 if (VM_Version::supports_evex()) {
2255 _tuple_type = EVEX_FVM;
2256 }
2257 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
2258 }
2259
2260 void Assembler::movdqu(XMMRegister dst, Address src) {
2261 _instruction_uses_vl = true;
2262 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2263 if (VM_Version::supports_evex()) {
2264 _tuple_type = EVEX_FVM;
2265 }
2266 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
2267 }
2268
2269 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2270 _instruction_uses_vl = true;
2271 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2272 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
2273 }
2274
2275 void Assembler::movdqu(Address dst, XMMRegister src) {
2276 _instruction_uses_vl = true;
2277 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2278 if (VM_Version::supports_evex()) {
2279 _tuple_type = EVEX_FVM;
2280 }
2281 InstructionMark im(this);
2282 simd_prefix(dst, src, VEX_SIMD_F3, /* no_mask_reg */ false);
2283 emit_int8(0x7F);
2284 emit_operand(src, dst);
2285 }
2286
2287 // Move Unaligned 256bit Vector
2288 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2289 _instruction_uses_vl = true;
2290 assert(UseAVX > 0, "");
2291 int vector_len = AVX_256bit;
2292 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector_len);
2293 emit_int8(0x6F);
2294 emit_int8((unsigned char)(0xC0 | encode));
2295 }
2296
2297 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2298 _instruction_uses_vl = true;
2299 assert(UseAVX > 0, "");
2300 if (VM_Version::supports_evex()) {
2301 _tuple_type = EVEX_FVM;
2302 }
2303 InstructionMark im(this);
2304 int vector_len = AVX_256bit;
2305 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector_len);
2306 emit_int8(0x6F);
2307 emit_operand(dst, src);
2308 }
2309
2310 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2311 _instruction_uses_vl = true;
2312 assert(UseAVX > 0, "");
2313 if (VM_Version::supports_evex()) {
2314 _tuple_type = EVEX_FVM;
2315 }
2316 InstructionMark im(this);
2317 int vector_len = AVX_256bit;
2318 // swap src<->dst for encoding
2319 assert(src != xnoreg, "sanity");
2320 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector_len);
2321 emit_int8(0x7F);
2322 emit_operand(src, dst);
2323 }
2324
2325 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2326 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2327 _instruction_uses_vl = true;
2328 assert(UseAVX > 0, "");
2329 int src_enc = src->encoding();
2330 int dst_enc = dst->encoding();
2331 int encode = vex_prefix_and_encode(dst_enc, 0, src_enc, VEX_SIMD_F3, VEX_OPCODE_0F,
2332 /* vex_w */ false, vector_len, /* legacy_mode */ false, /* no_mask_reg */ false);
2333 emit_int8(0x6F);
2334 emit_int8((unsigned char)(0xC0 | encode));
2335 }
2336
2337 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2338 _instruction_uses_vl = true;
2339 assert(UseAVX > 0, "");
2340 InstructionMark im(this);
2341 if (VM_Version::supports_evex()) {
2342 _tuple_type = EVEX_FVM;
2343 }
2344 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector_len);
2345 emit_int8(0x6F);
2346 emit_operand(dst, src);
2347 }
2348
2349 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2350 _instruction_uses_vl = true;
2351 assert(UseAVX > 0, "");
2352 InstructionMark im(this);
2353 assert(src != xnoreg, "sanity");
2354 if (VM_Version::supports_evex()) {
2355 _tuple_type = EVEX_FVM;
2356 }
2357 // swap src<->dst for encoding
2358 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector_len);
2359 emit_int8(0x7F);
2360 emit_operand(src, dst);
2361 }
2362
2363 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2364 _instruction_uses_vl = true;
2365 assert(UseAVX > 0, "");
2366 int src_enc = src->encoding();
2367 int dst_enc = dst->encoding();
2368 int encode = vex_prefix_and_encode(dst_enc, 0, src_enc, VEX_SIMD_F3, VEX_OPCODE_0F,
2369 /* vex_w */ true, vector_len, /* legacy_mode */ false, /* no_mask_reg */ false);
2370 emit_int8(0x6F);
2371 emit_int8((unsigned char)(0xC0 | encode));
2372 }
2373
2374 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2375 _instruction_uses_vl = true;
2376 assert(UseAVX > 2, "");
2377 InstructionMark im(this);
2378 _tuple_type = EVEX_FVM;
2379 vex_prefix_q(dst, xnoreg, src, VEX_SIMD_F3, vector_len);
2380 emit_int8(0x6F);
2381 emit_operand(dst, src);
2382 }
2383
2384 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2385 _instruction_uses_vl = true;
2386 assert(UseAVX > 2, "");
2387 InstructionMark im(this);
2388 assert(src != xnoreg, "sanity");
2389 _tuple_type = EVEX_FVM;
2390 // swap src<->dst for encoding
2391 vex_prefix_q(src, xnoreg, dst, VEX_SIMD_F3, vector_len);
2392 emit_int8(0x7F);
2393 emit_operand(src, dst);
2394 }
2395
2396 // Uses zero extension on 64bit
2397
2398 void Assembler::movl(Register dst, int32_t imm32) {
2399 int encode = prefix_and_encode(dst->encoding());
2400 emit_int8((unsigned char)(0xB8 | encode));
2401 emit_int32(imm32);
2402 }
2403
2404 void Assembler::movl(Register dst, Register src) {
2405 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2406 emit_int8((unsigned char)0x8B);
2407 emit_int8((unsigned char)(0xC0 | encode));
2408 }
2409
2410 void Assembler::movl(Register dst, Address src) {
2411 InstructionMark im(this);
2417 void Assembler::movl(Address dst, int32_t imm32) {
2418 InstructionMark im(this);
2419 prefix(dst);
2420 emit_int8((unsigned char)0xC7);
2421 emit_operand(rax, dst, 4);
2422 emit_int32(imm32);
2423 }
2424
2425 void Assembler::movl(Address dst, Register src) {
2426 InstructionMark im(this);
2427 prefix(dst, src);
2428 emit_int8((unsigned char)0x89);
2429 emit_operand(src, dst);
2430 }
2431
2432 // New cpus require to use movsd and movss to avoid partial register stall
2433 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2434 // The selection is done in MacroAssembler::movdbl() and movflt().
2435 void Assembler::movlpd(XMMRegister dst, Address src) {
2436 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2437 if (VM_Version::supports_evex()) {
2438 _tuple_type = EVEX_T1S;
2439 _input_size_in_bits = EVEX_32bit;
2440 emit_simd_arith_q(0x12, dst, src, VEX_SIMD_66, /* no_mask_reg */ true);
2441 } else {
2442 emit_simd_arith(0x12, dst, src, VEX_SIMD_66, /* no_mask_reg */ true);
2443 }
2444 }
2445
2446 void Assembler::movq( MMXRegister dst, Address src ) {
2447 assert( VM_Version::supports_mmx(), "" );
2448 emit_int8(0x0F);
2449 emit_int8(0x6F);
2450 emit_operand(dst, src);
2451 }
2452
2453 void Assembler::movq( Address dst, MMXRegister src ) {
2454 assert( VM_Version::supports_mmx(), "" );
2455 emit_int8(0x0F);
2456 emit_int8(0x7F);
2457 // workaround gcc (3.2.1-7a) bug
2458 // In that version of gcc with only an emit_operand(MMX, Address)
2459 // gcc will tail jump and try and reverse the parameters completely
2460 // obliterating dst in the process. By having a version available
2461 // that doesn't need to swap the args at the tail jump the bug is
2462 // avoided.
2463 emit_operand(dst, src);
2464 }
2465
2466 void Assembler::movq(XMMRegister dst, Address src) {
2467 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2468 InstructionMark im(this);
2469 if (VM_Version::supports_evex()) {
2470 _tuple_type = EVEX_T1S;
2471 _input_size_in_bits = EVEX_64bit;
2472 simd_prefix_q(dst, xnoreg, src, VEX_SIMD_F3, /* no_mask_reg */ true);
2473 } else {
2474 simd_prefix(dst, src, VEX_SIMD_F3, /* no_mask_reg */ true);
2475 }
2476 emit_int8(0x7E);
2477 emit_operand(dst, src);
2478 }
2479
2480 void Assembler::movq(Address dst, XMMRegister src) {
2481 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2482 InstructionMark im(this);
2483 if (VM_Version::supports_evex()) {
2484 _tuple_type = EVEX_T1S;
2485 _input_size_in_bits = EVEX_64bit;
2486 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, /* no_mask_reg */ true,
2487 VEX_OPCODE_0F, /* rex_w */ true);
2488 } else {
2489 simd_prefix(dst, src, VEX_SIMD_66, /* no_mask_reg */ true);
2490 }
2491 emit_int8((unsigned char)0xD6);
2492 emit_operand(src, dst);
2493 }
2494
2495 void Assembler::movsbl(Register dst, Address src) { // movsxb
2496 InstructionMark im(this);
2497 prefix(src, dst);
2498 emit_int8(0x0F);
2499 emit_int8((unsigned char)0xBE);
2500 emit_operand(dst, src);
2501 }
2502
2503 void Assembler::movsbl(Register dst, Register src) { // movsxb
2504 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2505 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2506 emit_int8(0x0F);
2507 emit_int8((unsigned char)0xBE);
2508 emit_int8((unsigned char)(0xC0 | encode));
2509 }
2510
2511 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2512 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2513 if (VM_Version::supports_evex()) {
2514 emit_simd_arith_q(0x10, dst, src, VEX_SIMD_F2, /* no_mask_reg */ true);
2515 } else {
2516 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2);
2517 }
2518 }
2519
2520 void Assembler::movsd(XMMRegister dst, Address src) {
2521 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2522 if (VM_Version::supports_evex()) {
2523 _tuple_type = EVEX_T1S;
2524 _input_size_in_bits = EVEX_64bit;
2525 emit_simd_arith_nonds_q(0x10, dst, src, VEX_SIMD_F2, /* no_mask_reg */ true);
2526 } else {
2527 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2);
2528 }
2529 }
2530
2531 void Assembler::movsd(Address dst, XMMRegister src) {
2532 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2533 InstructionMark im(this);
2534 if (VM_Version::supports_evex()) {
2535 _tuple_type = EVEX_T1S;
2536 _input_size_in_bits = EVEX_64bit;
2537 simd_prefix_q(src, xnoreg, dst, VEX_SIMD_F2);
2538 } else {
2539 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, /* no_mask_reg */ false);
2540 }
2541 emit_int8(0x11);
2542 emit_operand(src, dst);
2543 }
2544
2545 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2546 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2547 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3, /* no_mask_reg */ true);
2548 }
2549
2550 void Assembler::movss(XMMRegister dst, Address src) {
2551 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2552 if (VM_Version::supports_evex()) {
2553 _tuple_type = EVEX_T1S;
2554 _input_size_in_bits = EVEX_32bit;
2555 }
2556 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3, /* no_mask_reg */ true);
2557 }
2558
2559 void Assembler::movss(Address dst, XMMRegister src) {
2560 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2561 if (VM_Version::supports_evex()) {
2562 _tuple_type = EVEX_T1S;
2563 _input_size_in_bits = EVEX_32bit;
2564 }
2565 InstructionMark im(this);
2566 simd_prefix(dst, src, VEX_SIMD_F3, /* no_mask_reg */ false);
2567 emit_int8(0x11);
2568 emit_operand(src, dst);
2569 }
2570
2571 void Assembler::movswl(Register dst, Address src) { // movsxw
2572 InstructionMark im(this);
2573 prefix(src, dst);
2574 emit_int8(0x0F);
2575 emit_int8((unsigned char)0xBF);
2576 emit_operand(dst, src);
2577 }
2578
2579 void Assembler::movswl(Register dst, Register src) { // movsxw
2580 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2581 emit_int8(0x0F);
2582 emit_int8((unsigned char)0xBF);
2583 emit_int8((unsigned char)(0xC0 | encode));
2584 }
2585
2586 void Assembler::movw(Address dst, int imm16) {
2638 emit_int8(0x0F);
2639 emit_int8((unsigned char)0xB7);
2640 emit_int8(0xC0 | encode);
2641 }
2642
2643 void Assembler::mull(Address src) {
2644 InstructionMark im(this);
2645 prefix(src);
2646 emit_int8((unsigned char)0xF7);
2647 emit_operand(rsp, src);
2648 }
2649
2650 void Assembler::mull(Register src) {
2651 int encode = prefix_and_encode(src->encoding());
2652 emit_int8((unsigned char)0xF7);
2653 emit_int8((unsigned char)(0xE0 | encode));
2654 }
2655
2656 void Assembler::mulsd(XMMRegister dst, Address src) {
2657 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2658 if (VM_Version::supports_evex()) {
2659 _tuple_type = EVEX_T1S;
2660 _input_size_in_bits = EVEX_64bit;
2661 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_F2);
2662 } else {
2663 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2664 }
2665 }
2666
2667 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2668 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2669 if (VM_Version::supports_evex()) {
2670 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_F2);
2671 } else {
2672 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2673 }
2674 }
2675
2676 void Assembler::mulss(XMMRegister dst, Address src) {
2677 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2678 if (VM_Version::supports_evex()) {
2679 _tuple_type = EVEX_T1S;
2680 _input_size_in_bits = EVEX_32bit;
2681 }
2682 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2683 }
2684
2685 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2686 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2687 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2688 }
2689
2690 void Assembler::negl(Register dst) {
2691 int encode = prefix_and_encode(dst->encoding());
2692 emit_int8((unsigned char)0xF7);
2693 emit_int8((unsigned char)(0xD8 | encode));
2694 }
2695
2696 void Assembler::nop(int i) {
2697 #ifdef ASSERT
2698 assert(i > 0, " ");
2699 // The fancy nops aren't currently recognized by debuggers making it a
2700 // pain to disassemble code while debugging. If asserts are on clearly
2701 // speed is not an issue so simply use the single byte traditional nop
2702 // to do alignment.
2703
2704 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2705 return;
2706
2707 #endif // ASSERT
2968 prefix(src, dst);
2969 emit_int8(0x0B);
2970 emit_operand(dst, src);
2971 }
2972
2973 void Assembler::orl(Register dst, Register src) {
2974 (void) prefix_and_encode(dst->encoding(), src->encoding());
2975 emit_arith(0x0B, 0xC0, dst, src);
2976 }
2977
2978 void Assembler::orl(Address dst, Register src) {
2979 InstructionMark im(this);
2980 prefix(dst, src);
2981 emit_int8(0x09);
2982 emit_operand(src, dst);
2983 }
2984
2985 void Assembler::packuswb(XMMRegister dst, Address src) {
2986 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2987 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2988 if (VM_Version::supports_evex()) {
2989 _tuple_type = EVEX_FV;
2990 _input_size_in_bits = EVEX_32bit;
2991 }
2992 emit_simd_arith(0x67, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
2993 }
2994
2995 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2996 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2997 emit_simd_arith(0x67, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
2998 }
2999
3000 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3001 assert(UseAVX > 0, "some form of AVX must be enabled");
3002 emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
3003 }
3004
3005 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3006 _instruction_uses_vl = true;
3007 assert(VM_Version::supports_avx2(), "");
3008 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, /* no_mask_reg */ false,
3009 VEX_OPCODE_0F_3A, /* rex_w */ true, vector_len);
3010 emit_int8(0x00);
3011 emit_int8(0xC0 | encode);
3012 emit_int8(imm8);
3013 }
3014
3015 void Assembler::pause() {
3016 emit_int8((unsigned char)0xF3);
3017 emit_int8((unsigned char)0x90);
3018 }
3019
3020 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3021 assert(VM_Version::supports_sse4_2(), "");
3022 InstructionMark im(this);
3023 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, /* no_mask_reg */ false, VEX_OPCODE_0F_3A,
3024 /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
3025 emit_int8(0x61);
3026 emit_operand(dst, src);
3027 emit_int8(imm8);
3028 }
3029
3030 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3031 assert(VM_Version::supports_sse4_2(), "");
3032 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, /* no_mask_reg */ false,
3033 VEX_OPCODE_0F_3A, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
3034 emit_int8(0x61);
3035 emit_int8((unsigned char)(0xC0 | encode));
3036 emit_int8(imm8);
3037 }
3038
3039 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3040 assert(VM_Version::supports_sse4_1(), "");
3041 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, /* no_mask_reg */ true,
3042 VEX_OPCODE_0F_3A, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_dq);
3043 emit_int8(0x16);
3044 emit_int8((unsigned char)(0xC0 | encode));
3045 emit_int8(imm8);
3046 }
3047
3048 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3049 assert(VM_Version::supports_sse4_1(), "");
3050 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, /* no_mask_reg */ true,
3051 VEX_OPCODE_0F_3A, /* rex_w */ true, AVX_128bit, /* legacy_mode */ _legacy_mode_dq);
3052 emit_int8(0x16);
3053 emit_int8((unsigned char)(0xC0 | encode));
3054 emit_int8(imm8);
3055 }
3056
3057 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3058 assert(VM_Version::supports_sse2(), "");
3059 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, /* no_mask_reg */ true,
3060 VEX_OPCODE_0F, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
3061 emit_int8((unsigned char)0xC5);
3062 emit_int8((unsigned char)(0xC0 | encode));
3063 emit_int8(imm8);
3064 }
3065
3066 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3067 assert(VM_Version::supports_sse4_1(), "");
3068 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, /* no_mask_reg */ true,
3069 VEX_OPCODE_0F_3A, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_dq);
3070 emit_int8(0x22);
3071 emit_int8((unsigned char)(0xC0 | encode));
3072 emit_int8(imm8);
3073 }
3074
3075 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3076 assert(VM_Version::supports_sse4_1(), "");
3077 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, /* no_mask_reg */ true,
3078 VEX_OPCODE_0F_3A, /* rex_w */ true, AVX_128bit, /* legacy_mode */ _legacy_mode_dq);
3079 emit_int8(0x22);
3080 emit_int8((unsigned char)(0xC0 | encode));
3081 emit_int8(imm8);
3082 }
3083
3084 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3085 assert(VM_Version::supports_sse2(), "");
3086 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, /* no_mask_reg */ true,
3087 VEX_OPCODE_0F, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
3088 emit_int8((unsigned char)0xC4);
3089 emit_int8((unsigned char)(0xC0 | encode));
3090 emit_int8(imm8);
3091 }
3092
3093 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3094 assert(VM_Version::supports_sse4_1(), "");
3095 if (VM_Version::supports_evex()) {
3096 _tuple_type = EVEX_HVM;
3097 }
3098 InstructionMark im(this);
3099 simd_prefix(dst, src, VEX_SIMD_66, /* no_mask_reg */ false, VEX_OPCODE_0F_38);
3100 emit_int8(0x30);
3101 emit_operand(dst, src);
3102 }
3103
3104 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3105 assert(VM_Version::supports_sse4_1(), "");
3106 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, /* no_mask_reg */ false, VEX_OPCODE_0F_38);
3107 emit_int8(0x30);
3108 emit_int8((unsigned char)(0xC0 | encode));
3109 }
3110
3111 // generic
3112 void Assembler::pop(Register dst) {
3113 int encode = prefix_and_encode(dst->encoding());
3114 emit_int8(0x58 | encode);
3115 }
3116
3117 void Assembler::popcntl(Register dst, Address src) {
3118 assert(VM_Version::supports_popcnt(), "must support");
3119 InstructionMark im(this);
3120 emit_int8((unsigned char)0xF3);
3121 prefix(src, dst);
3122 emit_int8(0x0F);
3123 emit_int8((unsigned char)0xB8);
3124 emit_operand(dst, src);
3125 }
3126
3189 InstructionMark im(this);
3190 prefetch_prefix(src);
3191 emit_int8(0x18);
3192 emit_operand(rbx, src); // 3, src
3193 }
3194
3195 void Assembler::prefetchw(Address src) {
3196 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3197 InstructionMark im(this);
3198 prefetch_prefix(src);
3199 emit_int8(0x0D);
3200 emit_operand(rcx, src); // 1, src
3201 }
3202
3203 void Assembler::prefix(Prefix p) {
3204 emit_int8(p);
3205 }
3206
3207 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3208 assert(VM_Version::supports_ssse3(), "");
3209 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
3210 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
3211 emit_int8(0x00);
3212 emit_int8((unsigned char)(0xC0 | encode));
3213 }
3214
3215 void Assembler::pshufb(XMMRegister dst, Address src) {
3216 assert(VM_Version::supports_ssse3(), "");
3217 if (VM_Version::supports_evex()) {
3218 _tuple_type = EVEX_FVM;
3219 }
3220 InstructionMark im(this);
3221 simd_prefix(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
3222 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
3223 emit_int8(0x00);
3224 emit_operand(dst, src);
3225 }
3226
3227 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
3228 _instruction_uses_vl = true;
3229 assert(isByte(mode), "invalid value");
3230 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3231 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
3232 emit_int8(mode & 0xFF);
3233 }
3234
3235 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
3236 _instruction_uses_vl = true;
3237 assert(isByte(mode), "invalid value");
3238 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3239 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3240 if (VM_Version::supports_evex()) {
3241 _tuple_type = EVEX_FV;
3242 _input_size_in_bits = EVEX_32bit;
3243 }
3244 InstructionMark im(this);
3245 simd_prefix(dst, src, VEX_SIMD_66, /* no_mask_reg */ false);
3246 emit_int8(0x70);
3247 emit_operand(dst, src);
3248 emit_int8(mode & 0xFF);
3249 }
3250
3251 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3252 assert(isByte(mode), "invalid value");
3253 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3254 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
3255 emit_int8(mode & 0xFF);
3256 }
3257
3258 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3259 assert(isByte(mode), "invalid value");
3260 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3261 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3262 if (VM_Version::supports_evex()) {
3263 _tuple_type = EVEX_FVM;
3264 }
3265 InstructionMark im(this);
3266 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, /* no_mask_reg */ false,
3267 VEX_OPCODE_0F, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
3268 emit_int8(0x70);
3269 emit_operand(dst, src);
3270 emit_int8(mode & 0xFF);
3271 }
3272
3273 void Assembler::psrldq(XMMRegister dst, int shift) {
3274 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3275 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3276 // XMM3 is for /3 encoding: 66 0F 73 /3 ib
3277 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, /* no_mask_reg */ true,
3278 VEX_OPCODE_0F, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
3279 emit_int8(0x73);
3280 emit_int8((unsigned char)(0xC0 | encode));
3281 emit_int8(shift);
3282 }
3283
3284 void Assembler::pslldq(XMMRegister dst, int shift) {
3285 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3286 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3287 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
3288 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, /* no_mask_reg */ true,
3289 VEX_OPCODE_0F, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
3290 emit_int8(0x73);
3291 emit_int8((unsigned char)(0xC0 | encode));
3292 emit_int8(shift);
3293 }
3294
3295 void Assembler::ptest(XMMRegister dst, Address src) {
3296 assert(VM_Version::supports_sse4_1(), "");
3297 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3298 InstructionMark im(this);
3299 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, /* no_mask_reg */ false,
3300 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
3301 emit_int8(0x17);
3302 emit_operand(dst, src);
3303 }
3304
3305 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3306 assert(VM_Version::supports_sse4_1(), "");
3307 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, /* no_mask_reg */ false,
3308 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
3309 emit_int8(0x17);
3310 emit_int8((unsigned char)(0xC0 | encode));
3311 }
3312
3313 void Assembler::vptest(XMMRegister dst, Address src) {
3314 assert(VM_Version::supports_avx(), "");
3315 InstructionMark im(this);
3316 int vector_len = AVX_256bit;
3317 assert(dst != xnoreg, "sanity");
3318 int dst_enc = dst->encoding();
3319 // swap src<->dst for encoding
3320 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, /* rex_w */ false,
3321 vector_len, /* legacy_mode */ true, /* no_mask_reg */ false);
3322 emit_int8(0x17);
3323 emit_operand(dst, src);
3324 }
3325
3326 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
3327 assert(VM_Version::supports_avx(), "");
3328 int vector_len = AVX_256bit;
3329 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_38, /* legacy_mode */ true);
3330 emit_int8(0x17);
3331 emit_int8((unsigned char)(0xC0 | encode));
3332 }
3333
3334 void Assembler::punpcklbw(XMMRegister dst, Address src) {
3335 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3336 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3337 if (VM_Version::supports_evex()) {
3338 _tuple_type = EVEX_FVM;
3339 }
3340 emit_simd_arith(0x60, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_vlbw);
3341 }
3342
3343 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3344 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3345 emit_simd_arith(0x60, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_vlbw);
3346 }
3347
3348 void Assembler::punpckldq(XMMRegister dst, Address src) {
3349 _instruction_uses_vl = true;
3350 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3351 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3352 if (VM_Version::supports_evex()) {
3353 _tuple_type = EVEX_FV;
3354 _input_size_in_bits = EVEX_32bit;
3355 }
3356 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
3357 }
3358
3359 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
3360 _instruction_uses_vl = true;
3361 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3362 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
3363 }
3364
3365 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
3366 _instruction_uses_vl = true;
3367 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3368 if (VM_Version::supports_evex()) {
3369 emit_simd_arith_q(0x6C, dst, src, VEX_SIMD_66);
3370 } else {
3371 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66);
3372 }
3373 }
3374
3375 void Assembler::push(int32_t imm32) {
3376 // in 64bits we push 64bits onto the stack but only
3377 // take a 32bit immediate
3378 emit_int8(0x68);
3379 emit_int32(imm32);
3380 }
3381
3382 void Assembler::push(Register src) {
3383 int encode = prefix_and_encode(src->encoding());
3384
3385 emit_int8(0x50 | encode);
3386 }
3387
3388 void Assembler::pushf() {
3389 emit_int8((unsigned char)0x9C);
3390 }
3391
3392 #ifndef _LP64 // no 32bit push/pop on amd64
3397 emit_int8((unsigned char)0xFF);
3398 emit_operand(rsi, src);
3399 }
3400 #endif
3401
3402 void Assembler::rcll(Register dst, int imm8) {
3403 assert(isShiftCount(imm8), "illegal shift count");
3404 int encode = prefix_and_encode(dst->encoding());
3405 if (imm8 == 1) {
3406 emit_int8((unsigned char)0xD1);
3407 emit_int8((unsigned char)(0xD0 | encode));
3408 } else {
3409 emit_int8((unsigned char)0xC1);
3410 emit_int8((unsigned char)0xD0 | encode);
3411 emit_int8(imm8);
3412 }
3413 }
3414
3415 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
3416 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3417 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, /* no_mask_reg */ false, VEX_OPCODE_0F, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
3418 emit_int8(0x53);
3419 emit_int8(0xC0 | encode);
3420 }
3421
3422 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
3423 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3424 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, /* no_mask_reg */ false, VEX_OPCODE_0F, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
3425 emit_int8(0x53);
3426 emit_int8(0xC0 | encode);
3427 }
3428
3429 void Assembler::rdtsc() {
3430 emit_int8((unsigned char)0x0F);
3431 emit_int8((unsigned char)0x31);
3432 }
3433
3434 // copies data from [esi] to [edi] using rcx pointer sized words
3435 // generic
3436 void Assembler::rep_mov() {
3437 emit_int8((unsigned char)0xF3);
3438 // MOVSQ
3439 LP64_ONLY(prefix(REX_W));
3440 emit_int8((unsigned char)0xA5);
3441 }
3442
3443 // sets rcx bytes with rax, value at [edi]
3444 void Assembler::rep_stosb() {
3445 emit_int8((unsigned char)0xF3); // REP
3446 LP64_ONLY(prefix(REX_W));
3565 assert(isShiftCount(imm8), "illegal shift count");
3566 int encode = prefix_and_encode(dst->encoding());
3567 emit_int8((unsigned char)0xC1);
3568 emit_int8((unsigned char)(0xE8 | encode));
3569 emit_int8(imm8);
3570 }
3571
3572 void Assembler::shrl(Register dst) {
3573 int encode = prefix_and_encode(dst->encoding());
3574 emit_int8((unsigned char)0xD3);
3575 emit_int8((unsigned char)(0xE8 | encode));
3576 }
3577
3578 // copies a single word from [esi] to [edi]
3579 void Assembler::smovl() {
3580 emit_int8((unsigned char)0xA5);
3581 }
3582
3583 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
3584 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3585 if (VM_Version::supports_evex()) {
3586 emit_simd_arith_q(0x51, dst, src, VEX_SIMD_F2);
3587 } else {
3588 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
3589 }
3590 }
3591
3592 void Assembler::sqrtsd(XMMRegister dst, Address src) {
3593 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3594 if (VM_Version::supports_evex()) {
3595 _tuple_type = EVEX_T1S;
3596 _input_size_in_bits = EVEX_64bit;
3597 emit_simd_arith_q(0x51, dst, src, VEX_SIMD_F2);
3598 } else {
3599 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
3600 }
3601 }
3602
3603 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
3604 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3605 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
3606 }
3607
3608 void Assembler::std() {
3609 emit_int8((unsigned char)0xFD);
3610 }
3611
3612 void Assembler::sqrtss(XMMRegister dst, Address src) {
3613 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3614 if (VM_Version::supports_evex()) {
3615 _tuple_type = EVEX_T1S;
3616 _input_size_in_bits = EVEX_32bit;
3617 }
3618 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
3619 }
3620
3621 void Assembler::stmxcsr( Address dst) {
3622 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3623 InstructionMark im(this);
3624 prefix(dst);
3625 emit_int8(0x0F);
3626 emit_int8((unsigned char)0xAE);
3627 emit_operand(as_Register(3), dst);
3628 }
3629
3630 void Assembler::subl(Address dst, int32_t imm32) {
3631 InstructionMark im(this);
3632 prefix(dst);
3633 emit_arith_operand(0x81, rbp, dst, imm32);
3634 }
3635
3636 void Assembler::subl(Address dst, Register src) {
3637 InstructionMark im(this);
3638 prefix(dst, src);
3648 // Force generation of a 4 byte immediate value even if it fits into 8bit
3649 void Assembler::subl_imm32(Register dst, int32_t imm32) {
3650 prefix(dst);
3651 emit_arith_imm32(0x81, 0xE8, dst, imm32);
3652 }
3653
3654 void Assembler::subl(Register dst, Address src) {
3655 InstructionMark im(this);
3656 prefix(src, dst);
3657 emit_int8(0x2B);
3658 emit_operand(dst, src);
3659 }
3660
3661 void Assembler::subl(Register dst, Register src) {
3662 (void) prefix_and_encode(dst->encoding(), src->encoding());
3663 emit_arith(0x2B, 0xC0, dst, src);
3664 }
3665
3666 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
3667 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3668 if (VM_Version::supports_evex()) {
3669 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_F2);
3670 } else {
3671 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
3672 }
3673 }
3674
3675 void Assembler::subsd(XMMRegister dst, Address src) {
3676 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3677 if (VM_Version::supports_evex()) {
3678 _tuple_type = EVEX_T1S;
3679 _input_size_in_bits = EVEX_64bit;
3680 }
3681 if (VM_Version::supports_evex()) {
3682 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_F2);
3683 } else {
3684 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
3685 }
3686 }
3687
3688 void Assembler::subss(XMMRegister dst, XMMRegister src) {
3689 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3690 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
3691 }
3692
3693 void Assembler::subss(XMMRegister dst, Address src) {
3694 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3695 if (VM_Version::supports_evex()) {
3696 _tuple_type = EVEX_T1S;
3697 _input_size_in_bits = EVEX_32bit;
3698 }
3699 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
3700 }
3701
3702 void Assembler::testb(Register dst, int imm8) {
3703 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
3704 (void) prefix_and_encode(dst->encoding(), true);
3705 emit_arith_b(0xF6, 0xC0, dst, imm8);
3706 }
3707
3708 void Assembler::testl(Register dst, int32_t imm32) {
3709 // not using emit_arith because test
3710 // doesn't support sign-extension of
3711 // 8bit operands
3712 int encode = dst->encoding();
3713 if (encode == 0) {
3714 emit_int8((unsigned char)0xA9);
3715 } else {
3716 encode = prefix_and_encode(encode);
3717 emit_int8((unsigned char)0xF7);
3718 emit_int8((unsigned char)(0xC0 | encode));
3719 }
3735 void Assembler::tzcntl(Register dst, Register src) {
3736 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
3737 emit_int8((unsigned char)0xF3);
3738 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3739 emit_int8(0x0F);
3740 emit_int8((unsigned char)0xBC);
3741 emit_int8((unsigned char)0xC0 | encode);
3742 }
3743
3744 void Assembler::tzcntq(Register dst, Register src) {
3745 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
3746 emit_int8((unsigned char)0xF3);
3747 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3748 emit_int8(0x0F);
3749 emit_int8((unsigned char)0xBC);
3750 emit_int8((unsigned char)(0xC0 | encode));
3751 }
3752
3753 void Assembler::ucomisd(XMMRegister dst, Address src) {
3754 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3755 if (VM_Version::supports_evex()) {
3756 _tuple_type = EVEX_T1S;
3757 _input_size_in_bits = EVEX_64bit;
3758 emit_simd_arith_nonds_q(0x2E, dst, src, VEX_SIMD_66, /* no_mask_reg */ true);
3759 } else {
3760 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
3761 }
3762 }
3763
3764 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
3765 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3766 if (VM_Version::supports_evex()) {
3767 emit_simd_arith_nonds_q(0x2E, dst, src, VEX_SIMD_66, /* no_mask_reg */ true);
3768 } else {
3769 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
3770 }
3771 }
3772
3773 void Assembler::ucomiss(XMMRegister dst, Address src) {
3774 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3775 if (VM_Version::supports_evex()) {
3776 _tuple_type = EVEX_T1S;
3777 _input_size_in_bits = EVEX_32bit;
3778 }
3779 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE, /* no_mask_reg */ true);
3780 }
3781
3782 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
3783 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3784 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE, /* no_mask_reg */ true);
3785 }
3786
3787 void Assembler::xabort(int8_t imm8) {
3788 emit_int8((unsigned char)0xC6);
3789 emit_int8((unsigned char)0xF8);
3790 emit_int8((unsigned char)(imm8 & 0xFF));
3791 }
3792
3793 void Assembler::xaddl(Address dst, Register src) {
3794 InstructionMark im(this);
3795 prefix(dst, src);
3796 emit_int8(0x0F);
3797 emit_int8((unsigned char)0xC1);
3798 emit_operand(src, dst);
3799 }
3800
3801 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
3802 InstructionMark im(this);
3803 relocate(rtype);
3804 if (abort.is_bound()) {
3846 emit_arith(0x81, 0xF0, dst, imm32);
3847 }
3848
3849 void Assembler::xorl(Register dst, Address src) {
3850 InstructionMark im(this);
3851 prefix(src, dst);
3852 emit_int8(0x33);
3853 emit_operand(dst, src);
3854 }
3855
3856 void Assembler::xorl(Register dst, Register src) {
3857 (void) prefix_and_encode(dst->encoding(), src->encoding());
3858 emit_arith(0x33, 0xC0, dst, src);
3859 }
3860
3861
3862 // AVX 3-operands scalar float-point arithmetic instructions
3863
3864 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
3865 assert(VM_Version::supports_avx(), "");
3866 if (VM_Version::supports_evex()) {
3867 _tuple_type = EVEX_T1S;
3868 _input_size_in_bits = EVEX_64bit;
3869 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3870 } else {
3871 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3872 }
3873 }
3874
3875 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3876 assert(VM_Version::supports_avx(), "");
3877 if (VM_Version::supports_evex()) {
3878 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3879 } else {
3880 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3881 }
3882 }
3883
3884 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
3885 assert(VM_Version::supports_avx(), "");
3886 if (VM_Version::supports_evex()) {
3887 _tuple_type = EVEX_T1S;
3888 _input_size_in_bits = EVEX_32bit;
3889 }
3890 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3891 }
3892
3893 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3894 assert(VM_Version::supports_avx(), "");
3895 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3896 }
3897
3898 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
3899 assert(VM_Version::supports_avx(), "");
3900 if (VM_Version::supports_evex()) {
3901 _tuple_type = EVEX_T1S;
3902 _input_size_in_bits = EVEX_64bit;
3903 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3904 } else {
3905 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3906 }
3907 }
3908
3909 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3910 assert(VM_Version::supports_avx(), "");
3911 if (VM_Version::supports_evex()) {
3912 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3913 } else {
3914 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3915 }
3916 }
3917
3918 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
3919 assert(VM_Version::supports_avx(), "");
3920 if (VM_Version::supports_evex()) {
3921 _tuple_type = EVEX_T1S;
3922 _input_size_in_bits = EVEX_32bit;
3923 }
3924 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3925 }
3926
3927 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3928 assert(VM_Version::supports_avx(), "");
3929 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3930 }
3931
3932 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
3933 assert(VM_Version::supports_avx(), "");
3934 if (VM_Version::supports_evex()) {
3935 _tuple_type = EVEX_T1S;
3936 _input_size_in_bits = EVEX_64bit;
3937 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3938 } else {
3939 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3940 }
3941 }
3942
3943 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3944 assert(VM_Version::supports_avx(), "");
3945 if (VM_Version::supports_evex()) {
3946 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3947 } else {
3948 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3949 }
3950 }
3951
3952 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
3953 assert(VM_Version::supports_avx(), "");
3954 if (VM_Version::supports_evex()) {
3955 _tuple_type = EVEX_T1S;
3956 _input_size_in_bits = EVEX_32bit;
3957 }
3958 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3959 }
3960
3961 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3962 assert(VM_Version::supports_avx(), "");
3963 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3964 }
3965
3966 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
3967 assert(VM_Version::supports_avx(), "");
3968 if (VM_Version::supports_evex()) {
3969 _tuple_type = EVEX_T1S;
3970 _input_size_in_bits = EVEX_64bit;
3971 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3972 } else {
3973 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3974 }
3975 }
3976
3977 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3978 assert(VM_Version::supports_avx(), "");
3979 if (VM_Version::supports_evex()) {
3980 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3981 } else {
3982 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3983 }
3984 }
3985
3986 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
3987 assert(VM_Version::supports_avx(), "");
3988 if (VM_Version::supports_evex()) {
3989 _tuple_type = EVEX_T1S;
3990 _input_size_in_bits = EVEX_32bit;
3991 }
3992 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3993 }
3994
3995 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3996 assert(VM_Version::supports_avx(), "");
3997 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3998 }
3999
4000 //====================VECTOR ARITHMETIC=====================================
4001
4002 // Float-point vector arithmetic
4003
4004 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4005 _instruction_uses_vl = true;
4006 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4007 if (VM_Version::supports_evex()) {
4008 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_66);
4009 } else {
4010 emit_simd_arith(0x58, dst, src, VEX_SIMD_66);
4011 }
4012 }
4013
4014 void Assembler::addps(XMMRegister dst, XMMRegister src) {
4015 _instruction_uses_vl = true;
4016 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4017 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE);
4018 }
4019
4020 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4021 _instruction_uses_vl = true;
4022 assert(VM_Version::supports_avx(), "");
4023 if (VM_Version::supports_evex()) {
4024 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
4025 } else {
4026 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
4027 }
4028 }
4029
4030 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4031 _instruction_uses_vl = true;
4032 assert(VM_Version::supports_avx(), "");
4033 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector_len);
4034 }
4035
4036 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4037 _instruction_uses_vl = true;
4038 assert(VM_Version::supports_avx(), "");
4039 if (VM_Version::supports_evex()) {
4040 _tuple_type = EVEX_FV;
4041 _input_size_in_bits = EVEX_64bit;
4042 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
4043 } else {
4044 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
4045 }
4046 }
4047
4048 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4049 _instruction_uses_vl = true;
4050 assert(VM_Version::supports_avx(), "");
4051 if (VM_Version::supports_evex()) {
4052 _tuple_type = EVEX_FV;
4053 _input_size_in_bits = EVEX_32bit;
4054 }
4055 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector_len);
4056 }
4057
4058 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
4059 _instruction_uses_vl = true;
4060 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4061 if (VM_Version::supports_evex()) {
4062 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_66);
4063 } else {
4064 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66);
4065 }
4066 }
4067
4068 void Assembler::subps(XMMRegister dst, XMMRegister src) {
4069 _instruction_uses_vl = true;
4070 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4071 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE);
4072 }
4073
4074 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4075 _instruction_uses_vl = true;
4076 assert(VM_Version::supports_avx(), "");
4077 if (VM_Version::supports_evex()) {
4078 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
4079 } else {
4080 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
4081 }
4082 }
4083
4084 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4085 _instruction_uses_vl = true;
4086 assert(VM_Version::supports_avx(), "");
4087 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector_len);
4088 }
4089
4090 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4091 _instruction_uses_vl = true;
4092 assert(VM_Version::supports_avx(), "");
4093 if (VM_Version::supports_evex()) {
4094 _tuple_type = EVEX_FV;
4095 _input_size_in_bits = EVEX_64bit;
4096 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
4097 } else {
4098 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
4099 }
4100 }
4101
4102 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4103 _instruction_uses_vl = true;
4104 assert(VM_Version::supports_avx(), "");
4105 if (VM_Version::supports_evex()) {
4106 _tuple_type = EVEX_FV;
4107 _input_size_in_bits = EVEX_32bit;
4108 }
4109 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector_len);
4110 }
4111
4112 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
4113 _instruction_uses_vl = true;
4114 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4115 if (VM_Version::supports_evex()) {
4116 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_66);
4117 } else {
4118 emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
4119 }
4120 }
4121
4122 void Assembler::mulpd(XMMRegister dst, Address src) {
4123 _instruction_uses_vl = true;
4124 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4125 if (VM_Version::supports_evex()) {
4126 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_66);
4127 } else {
4128 emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
4129 }
4130 }
4131
4132 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
4133 _instruction_uses_vl = true;
4134 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4135 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE);
4136 }
4137
4138 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4139 _instruction_uses_vl = true;
4140 assert(VM_Version::supports_avx(), "");
4141 if (VM_Version::supports_evex()) {
4142 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
4143 } else {
4144 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
4145 }
4146 }
4147
4148 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4149 _instruction_uses_vl = true;
4150 assert(VM_Version::supports_avx(), "");
4151 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector_len);
4152 }
4153
4154 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4155 _instruction_uses_vl = true;
4156 assert(VM_Version::supports_avx(), "");
4157 if (VM_Version::supports_evex()) {
4158 _tuple_type = EVEX_FV;
4159 _input_size_in_bits = EVEX_64bit;
4160 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
4161 } else {
4162 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
4163 }
4164 }
4165
4166 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4167 _instruction_uses_vl = true;
4168 assert(VM_Version::supports_avx(), "");
4169 if (VM_Version::supports_evex()) {
4170 _tuple_type = EVEX_FV;
4171 _input_size_in_bits = EVEX_32bit;
4172 }
4173 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector_len);
4174 }
4175
4176 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
4177 _instruction_uses_vl = true;
4178 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4179 if (VM_Version::supports_evex()) {
4180 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_66);
4181 } else {
4182 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66);
4183 }
4184 }
4185
4186 void Assembler::divps(XMMRegister dst, XMMRegister src) {
4187 _instruction_uses_vl = true;
4188 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4189 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE);
4190 }
4191
4192 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4193 _instruction_uses_vl = true;
4194 assert(VM_Version::supports_avx(), "");
4195 if (VM_Version::supports_evex()) {
4196 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
4197 } else {
4198 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
4199 }
4200 }
4201
4202 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4203 _instruction_uses_vl = true;
4204 assert(VM_Version::supports_avx(), "");
4205 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector_len);
4206 }
4207
4208 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4209 _instruction_uses_vl = true;
4210 assert(VM_Version::supports_avx(), "");
4211 if (VM_Version::supports_evex()) {
4212 _tuple_type = EVEX_FV;
4213 _input_size_in_bits = EVEX_64bit;
4214 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
4215 } else {
4216 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
4217 }
4218 }
4219
4220 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4221 _instruction_uses_vl = true;
4222 assert(VM_Version::supports_avx(), "");
4223 if (VM_Version::supports_evex()) {
4224 _tuple_type = EVEX_FV;
4225 _input_size_in_bits = EVEX_32bit;
4226 }
4227 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector_len);
4228 }
4229
4230 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
4231 _instruction_uses_vl = true;
4232 assert(VM_Version::supports_avx(), "");
4233 if (VM_Version::supports_evex()) {
4234 emit_vex_arith_q(0x51, dst, xnoreg, src, VEX_SIMD_66, vector_len);
4235 } else {
4236 emit_vex_arith(0x51, dst, xnoreg, src, VEX_SIMD_66, vector_len);
4237 }
4238 }
4239
4240 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
4241 _instruction_uses_vl = true;
4242 assert(VM_Version::supports_avx(), "");
4243 if (VM_Version::supports_evex()) {
4244 _tuple_type = EVEX_FV;
4245 _input_size_in_bits = EVEX_64bit;
4246 emit_vex_arith_q(0x51, dst, xnoreg, src, VEX_SIMD_66, vector_len);
4247 } else {
4248 emit_vex_arith(0x51, dst, xnoreg, src, VEX_SIMD_66, vector_len);
4249 }
4250 }
4251
4252 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
4253 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4254 if (VM_Version::supports_avx512dq()) {
4255 emit_simd_arith_q(0x54, dst, src, VEX_SIMD_66);
4256 } else {
4257 emit_simd_arith(0x54, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ true);
4258 }
4259 }
4260
4261 void Assembler::andps(XMMRegister dst, XMMRegister src) {
4262 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4263 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_dq);
4264 }
4265
4266 void Assembler::andps(XMMRegister dst, Address src) {
4267 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4268 if (VM_Version::supports_evex()) {
4269 _tuple_type = EVEX_FV;
4270 _input_size_in_bits = EVEX_32bit;
4271 }
4272 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_dq);
4273 }
4274
4275 void Assembler::andpd(XMMRegister dst, Address src) {
4276 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4277 if (VM_Version::supports_avx512dq()) {
4278 _tuple_type = EVEX_FV;
4279 _input_size_in_bits = EVEX_64bit;
4280 emit_simd_arith_q(0x54, dst, src, VEX_SIMD_66);
4281 } else {
4282 emit_simd_arith(0x54, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ true);
4283 }
4284 }
4285
4286 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4287 assert(VM_Version::supports_avx(), "");
4288 if (VM_Version::supports_avx512dq()) {
4289 emit_vex_arith_q(0x54, dst, nds, src, VEX_SIMD_66, vector_len);
4290 } else {
4291 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ true);
4292 }
4293 }
4294
4295 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4296 assert(VM_Version::supports_avx(), "");
4297 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_dq);
4298 }
4299
4300 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4301 assert(VM_Version::supports_avx(), "");
4302 if (VM_Version::supports_avx512dq()) {
4303 _tuple_type = EVEX_FV;
4304 _input_size_in_bits = EVEX_64bit;
4305 emit_vex_arith_q(0x54, dst, nds, src, VEX_SIMD_66, vector_len);
4306 } else {
4307 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ true);
4308 }
4309 }
4310
4311 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4312 assert(VM_Version::supports_avx(), "");
4313 if (VM_Version::supports_evex()) {
4314 _tuple_type = EVEX_FV;
4315 _input_size_in_bits = EVEX_32bit;
4316 }
4317 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_dq);
4318 }
4319
4320 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
4321 _instruction_uses_vl = true;
4322 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4323 if (VM_Version::supports_evex()) {
4324 emit_simd_arith_q(0x15, dst, src, VEX_SIMD_66);
4325 } else {
4326 emit_simd_arith(0x15, dst, src, VEX_SIMD_66);
4327 }
4328 }
4329
4330 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
4331 _instruction_uses_vl = true;
4332 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4333 if (VM_Version::supports_evex()) {
4334 emit_simd_arith_q(0x14, dst, src, VEX_SIMD_66);
4335 } else {
4336 emit_simd_arith(0x14, dst, src, VEX_SIMD_66);
4337 }
4338 }
4339
4340 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
4341 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4342 if (VM_Version::supports_avx512dq()) {
4343 emit_simd_arith_q(0x57, dst, src, VEX_SIMD_66);
4344 } else {
4345 emit_simd_arith(0x57, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ true);
4346 }
4347 }
4348
4349 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
4350 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4351 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_dq);
4352 }
4353
4354 void Assembler::xorpd(XMMRegister dst, Address src) {
4355 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4356 if (VM_Version::supports_avx512dq()) {
4357 _tuple_type = EVEX_FV;
4358 _input_size_in_bits = EVEX_64bit;
4359 emit_simd_arith_q(0x57, dst, src, VEX_SIMD_66);
4360 } else {
4361 emit_simd_arith(0x57, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ true);
4362 }
4363 }
4364
4365 void Assembler::xorps(XMMRegister dst, Address src) {
4366 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4367 if (VM_Version::supports_evex()) {
4368 _tuple_type = EVEX_FV;
4369 _input_size_in_bits = EVEX_32bit;
4370 }
4371 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_dq);
4372 }
4373
4374 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4375 assert(VM_Version::supports_avx(), "");
4376 if (VM_Version::supports_avx512dq()) {
4377 emit_vex_arith_q(0x57, dst, nds, src, VEX_SIMD_66, vector_len);
4378 } else {
4379 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ true);
4380 }
4381 }
4382
4383 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4384 assert(VM_Version::supports_avx(), "");
4385 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_dq);
4386 }
4387
4388 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4389 assert(VM_Version::supports_avx(), "");
4390 if (VM_Version::supports_avx512dq()) {
4391 _tuple_type = EVEX_FV;
4392 _input_size_in_bits = EVEX_64bit;
4393 emit_vex_arith_q(0x57, dst, nds, src, VEX_SIMD_66, vector_len);
4394 } else {
4395 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ true);
4396 }
4397 }
4398
4399 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4400 assert(VM_Version::supports_avx(), "");
4401 if (VM_Version::supports_evex()) {
4402 _tuple_type = EVEX_FV;
4403 _input_size_in_bits = EVEX_32bit;
4404 }
4405 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_dq);
4406 }
4407
4408 // Integer vector arithmetic
4409 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4410 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4411 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4412 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_38, /* legacy_mode */ true);
4413 emit_int8(0x01);
4414 emit_int8((unsigned char)(0xC0 | encode));
4415 }
4416
4417 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4418 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4419 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4420 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_38, /* legacy_mode */ true);
4421 emit_int8(0x02);
4422 emit_int8((unsigned char)(0xC0 | encode));
4423 }
4424
4425 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
4426 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4427 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4428 }
4429
4430 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
4431 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4432 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4433 }
4434
4435 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
4436 _instruction_uses_vl = true;
4437 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4438 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66);
4439 }
4440
4441 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
4442 _instruction_uses_vl = true;
4443 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4444 if (VM_Version::supports_evex()) {
4445 emit_simd_arith_q(0xD4, dst, src, VEX_SIMD_66);
4446 } else {
4447 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66);
4448 }
4449 }
4450
4451 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
4452 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4453 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
4454 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
4455 emit_int8(0x01);
4456 emit_int8((unsigned char)(0xC0 | encode));
4457 }
4458
4459 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
4460 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4461 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
4462 VEX_OPCODE_0F_38, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
4463 emit_int8(0x02);
4464 emit_int8((unsigned char)(0xC0 | encode));
4465 }
4466
4467 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4468 assert(UseAVX > 0, "requires some form of AVX");
4469 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4470 }
4471
4472 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4473 assert(UseAVX > 0, "requires some form of AVX");
4474 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4475 }
4476
4477 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4478 _instruction_uses_vl = true;
4479 assert(UseAVX > 0, "requires some form of AVX");
4480 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector_len);
4481 }
4482
4483 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4484 _instruction_uses_vl = true;
4485 assert(UseAVX > 0, "requires some form of AVX");
4486 if (VM_Version::supports_evex()) {
4487 emit_vex_arith_q(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4488 } else {
4489 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4490 }
4491 }
4492
4493 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4494 assert(UseAVX > 0, "requires some form of AVX");
4495 if (VM_Version::supports_evex()) {
4496 _tuple_type = EVEX_FVM;
4497 }
4498 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4499 }
4500
4501 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4502 assert(UseAVX > 0, "requires some form of AVX");
4503 if (VM_Version::supports_evex()) {
4504 _tuple_type = EVEX_FVM;
4505 }
4506 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4507 }
4508
4509 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4510 _instruction_uses_vl = true;
4511 assert(UseAVX > 0, "requires some form of AVX");
4512 if (VM_Version::supports_evex()) {
4513 _tuple_type = EVEX_FV;
4514 _input_size_in_bits = EVEX_32bit;
4515 }
4516 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector_len);
4517 }
4518
4519 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4520 _instruction_uses_vl = true;
4521 assert(UseAVX > 0, "requires some form of AVX");
4522 if (VM_Version::supports_evex()) {
4523 _tuple_type = EVEX_FV;
4524 _input_size_in_bits = EVEX_64bit;
4525 emit_vex_arith_q(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4526 } else {
4527 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4528 }
4529 }
4530
4531 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
4532 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4533 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4534 }
4535
4536 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
4537 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4538 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4539 }
4540
4541 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
4542 _instruction_uses_vl = true;
4543 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4544 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66);
4545 }
4546
4547 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
4548 _instruction_uses_vl = true;
4549 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4550 if (VM_Version::supports_evex()) {
4551 emit_simd_arith_q(0xFB, dst, src, VEX_SIMD_66);
4552 } else {
4553 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66);
4554 }
4555 }
4556
4557 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4558 assert(UseAVX > 0, "requires some form of AVX");
4559 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4560 }
4561
4562 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4563 assert(UseAVX > 0, "requires some form of AVX");
4564 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4565 }
4566
4567 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4568 _instruction_uses_vl = true;
4569 assert(UseAVX > 0, "requires some form of AVX");
4570 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector_len);
4571 }
4572
4573 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4574 _instruction_uses_vl = true;
4575 assert(UseAVX > 0, "requires some form of AVX");
4576 if (VM_Version::supports_evex()) {
4577 emit_vex_arith_q(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4578 } else {
4579 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4580 }
4581 }
4582
4583 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4584 assert(UseAVX > 0, "requires some form of AVX");
4585 if (VM_Version::supports_evex()) {
4586 _tuple_type = EVEX_FVM;
4587 }
4588 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4589 }
4590
4591 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4592 assert(UseAVX > 0, "requires some form of AVX");
4593 if (VM_Version::supports_evex()) {
4594 _tuple_type = EVEX_FVM;
4595 }
4596 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4597 }
4598
4599 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4600 _instruction_uses_vl = true;
4601 assert(UseAVX > 0, "requires some form of AVX");
4602 if (VM_Version::supports_evex()) {
4603 _tuple_type = EVEX_FV;
4604 _input_size_in_bits = EVEX_32bit;
4605 }
4606 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector_len);
4607 }
4608
4609 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4610 _instruction_uses_vl = true;
4611 assert(UseAVX > 0, "requires some form of AVX");
4612 if (VM_Version::supports_evex()) {
4613 _tuple_type = EVEX_FV;
4614 _input_size_in_bits = EVEX_64bit;
4615 emit_vex_arith_q(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4616 } else {
4617 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4618 }
4619 }
4620
4621 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
4622 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4623 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4624 }
4625
4626 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
4627 _instruction_uses_vl = true;
4628 assert(VM_Version::supports_sse4_1(), "");
4629 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66,
4630 /* no_mask_reg */ false, VEX_OPCODE_0F_38);
4631 emit_int8(0x40);
4632 emit_int8((unsigned char)(0xC0 | encode));
4633 }
4634
4635 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4636 assert(UseAVX > 0, "requires some form of AVX");
4637 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4638 }
4639
4640 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4641 _instruction_uses_vl = true;
4642 assert(UseAVX > 0, "requires some form of AVX");
4643 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_38);
4644 emit_int8(0x40);
4645 emit_int8((unsigned char)(0xC0 | encode));
4646 }
4647
4648 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4649 assert(UseAVX > 2, "requires some form of AVX");
4650 int src_enc = src->encoding();
4651 int dst_enc = dst->encoding();
4652 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4653 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_38,
4654 /* vex_w */ true, vector_len, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false);
4655 emit_int8(0x40);
4656 emit_int8((unsigned char)(0xC0 | encode));
4657 }
4658
4659 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4660 assert(UseAVX > 0, "requires some form of AVX");
4661 if (VM_Version::supports_evex()) {
4662 _tuple_type = EVEX_FVM;
4663 }
4664 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4665 }
4666
4667 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4668 _instruction_uses_vl = true;
4669 assert(UseAVX > 0, "requires some form of AVX");
4670 if (VM_Version::supports_evex()) {
4671 _tuple_type = EVEX_FV;
4672 _input_size_in_bits = EVEX_32bit;
4673 }
4674 InstructionMark im(this);
4675 int dst_enc = dst->encoding();
4676 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4677 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66,
4678 VEX_OPCODE_0F_38, /* vex_w */ false, vector_len);
4679 emit_int8(0x40);
4680 emit_operand(dst, src);
4681 }
4682
4683 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4684 assert(UseAVX > 0, "requires some form of AVX");
4685 if (VM_Version::supports_evex()) {
4686 _tuple_type = EVEX_FV;
4687 _input_size_in_bits = EVEX_64bit;
4688 }
4689 InstructionMark im(this);
4690 int dst_enc = dst->encoding();
4691 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4692 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66,
4693 VEX_OPCODE_0F_38, /* vex_w */ true, vector_len, /* legacy_mode */ _legacy_mode_dq);
4694 emit_int8(0x40);
4695 emit_operand(dst, src);
4696 }
4697
4698 // Shift packed integers left by specified number of bits.
4699 void Assembler::psllw(XMMRegister dst, int shift) {
4700 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4701 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
4702 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, /* no_mask_reg */ false, VEX_OPCODE_0F,
4703 /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
4704 emit_int8(0x71);
4705 emit_int8((unsigned char)(0xC0 | encode));
4706 emit_int8(shift & 0xFF);
4707 }
4708
4709 void Assembler::pslld(XMMRegister dst, int shift) {
4710 _instruction_uses_vl = true;
4711 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4712 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
4713 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, /* no_mask_reg */ false);
4714 emit_int8(0x72);
4715 emit_int8((unsigned char)(0xC0 | encode));
4716 emit_int8(shift & 0xFF);
4717 }
4718
4719 void Assembler::psllq(XMMRegister dst, int shift) {
4720 _instruction_uses_vl = true;
4721 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4722 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
4723 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, /* no_mask_reg */ false, VEX_OPCODE_0F, /* rex_w */ true);
4724 emit_int8(0x73);
4725 emit_int8((unsigned char)(0xC0 | encode));
4726 emit_int8(shift & 0xFF);
4727 }
4728
4729 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
4730 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4731 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4732 }
4733
4734 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
4735 _instruction_uses_vl = true;
4736 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4737 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66);
4738 }
4739
4740 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
4741 _instruction_uses_vl = true;
4742 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4743 if (VM_Version::supports_evex()) {
4744 emit_simd_arith_q(0xF3, dst, shift, VEX_SIMD_66);
4745 } else {
4746 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66);
4747 }
4748 }
4749
4750 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4751 assert(UseAVX > 0, "requires some form of AVX");
4752 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
4753 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4754 emit_int8(shift & 0xFF);
4755 }
4756
4757 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4758 _instruction_uses_vl = true;
4759 assert(UseAVX > 0, "requires some form of AVX");
4760 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
4761 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector_len);
4762 emit_int8(shift & 0xFF);
4763 }
4764
4765 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4766 _instruction_uses_vl = true;
4767 assert(UseAVX > 0, "requires some form of AVX");
4768 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
4769 if (VM_Version::supports_evex()) {
4770 emit_vex_arith_q(0x73, xmm6, dst, src, VEX_SIMD_66, vector_len);
4771 } else {
4772 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector_len);
4773 }
4774 emit_int8(shift & 0xFF);
4775 }
4776
4777 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4778 assert(UseAVX > 0, "requires some form of AVX");
4779 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4780 }
4781
4782 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4783 _instruction_uses_vl = true;
4784 assert(UseAVX > 0, "requires some form of AVX");
4785 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector_len);
4786 }
4787
4788 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4789 _instruction_uses_vl = true;
4790 assert(UseAVX > 0, "requires some form of AVX");
4791 if (VM_Version::supports_evex()) {
4792 emit_vex_arith_q(0xF3, dst, src, shift, VEX_SIMD_66, vector_len);
4793 } else {
4794 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector_len);
4795 }
4796 }
4797
4798 // Shift packed integers logically right by specified number of bits.
4799 void Assembler::psrlw(XMMRegister dst, int shift) {
4800 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4801 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
4802 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, /* no_mask_reg */ false,
4803 VEX_OPCODE_0F, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
4804 emit_int8(0x71);
4805 emit_int8((unsigned char)(0xC0 | encode));
4806 emit_int8(shift & 0xFF);
4807 }
4808
4809 void Assembler::psrld(XMMRegister dst, int shift) {
4810 _instruction_uses_vl = true;
4811 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4812 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
4813 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, /* no_mask_reg */ false);
4814 emit_int8(0x72);
4815 emit_int8((unsigned char)(0xC0 | encode));
4816 emit_int8(shift & 0xFF);
4817 }
4818
4819 void Assembler::psrlq(XMMRegister dst, int shift) {
4820 _instruction_uses_vl = true;
4821 // Do not confuse it with psrldq SSE2 instruction which
4822 // shifts 128 bit value in xmm register by number of bytes.
4823 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4824 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4825 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, /* no_mask_reg */ false,
4826 VEX_OPCODE_0F, /* rex_w */ VM_Version::supports_evex());
4827 emit_int8(0x73);
4828 emit_int8((unsigned char)(0xC0 | encode));
4829 emit_int8(shift & 0xFF);
4830 }
4831
4832 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
4833 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4834 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4835 }
4836
4837 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
4838 _instruction_uses_vl = true;
4839 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4840 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66);
4841 }
4842
4843 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
4844 _instruction_uses_vl = true;
4845 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4846 if (VM_Version::supports_evex()) {
4847 emit_simd_arith_q(0xD3, dst, shift, VEX_SIMD_66);
4848 } else {
4849 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66);
4850 }
4851 }
4852
4853 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4854 assert(UseAVX > 0, "requires some form of AVX");
4855 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
4856 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4857 emit_int8(shift & 0xFF);
4858 }
4859
4860 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4861 _instruction_uses_vl = true;
4862 assert(UseAVX > 0, "requires some form of AVX");
4863 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
4864 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector_len);
4865 emit_int8(shift & 0xFF);
4866 }
4867
4868 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4869 _instruction_uses_vl = true;
4870 assert(UseAVX > 0, "requires some form of AVX");
4871 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4872 if (VM_Version::supports_evex()) {
4873 emit_vex_arith_q(0x73, xmm2, dst, src, VEX_SIMD_66, vector_len);
4874 } else {
4875 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector_len);
4876 }
4877 emit_int8(shift & 0xFF);
4878 }
4879
4880 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4881 assert(UseAVX > 0, "requires some form of AVX");
4882 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4883 }
4884
4885 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4886 _instruction_uses_vl = true;
4887 assert(UseAVX > 0, "requires some form of AVX");
4888 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector_len);
4889 }
4890
4891 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4892 _instruction_uses_vl = true;
4893 assert(UseAVX > 0, "requires some form of AVX");
4894 if (VM_Version::supports_evex()) {
4895 emit_vex_arith_q(0xD3, dst, src, shift, VEX_SIMD_66, vector_len);
4896 } else {
4897 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector_len);
4898 }
4899 }
4900
4901 // Shift packed integers arithmetically right by specified number of bits.
4902 void Assembler::psraw(XMMRegister dst, int shift) {
4903 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4904 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4905 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, /* no_mask_reg */ false,
4906 VEX_OPCODE_0F, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
4907 emit_int8(0x71);
4908 emit_int8((unsigned char)(0xC0 | encode));
4909 emit_int8(shift & 0xFF);
4910 }
4911
4912 void Assembler::psrad(XMMRegister dst, int shift) {
4913 _instruction_uses_vl = true;
4914 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4915 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
4916 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, /* no_mask_reg */ false);
4917 emit_int8(0x72);
4918 emit_int8((unsigned char)(0xC0 | encode));
4919 emit_int8(shift & 0xFF);
4920 }
4921
4922 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
4923 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4924 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4925 }
4926
4927 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
4928 _instruction_uses_vl = true;
4929 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4930 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66);
4931 }
4932
4933 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4934 assert(UseAVX > 0, "requires some form of AVX");
4935 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4936 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4937 emit_int8(shift & 0xFF);
4938 }
4939
4940 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4941 _instruction_uses_vl = true;
4942 assert(UseAVX > 0, "requires some form of AVX");
4943 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4944 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector_len);
4945 emit_int8(shift & 0xFF);
4946 }
4947
4948 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4949 assert(UseAVX > 0, "requires some form of AVX");
4950 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector_len, /* no_mask_reg */ false, /* legacy_mode */ _legacy_mode_bw);
4951 }
4952
4953 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4954 _instruction_uses_vl = true;
4955 assert(UseAVX > 0, "requires some form of AVX");
4956 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector_len);
4957 }
4958
4959
4960 // logical operations packed integers
4961 void Assembler::pand(XMMRegister dst, XMMRegister src) {
4962 _instruction_uses_vl = true;
4963 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4964 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66);
4965 }
4966
4967 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4968 _instruction_uses_vl = true;
4969 assert(UseAVX > 0, "requires some form of AVX");
4970 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector_len);
4971 }
4972
4973 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4974 _instruction_uses_vl = true;
4975 assert(UseAVX > 0, "requires some form of AVX");
4976 if (VM_Version::supports_evex()) {
4977 _tuple_type = EVEX_FV;
4978 _input_size_in_bits = EVEX_32bit;
4979 }
4980 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector_len);
4981 }
4982
4983 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
4984 _instruction_uses_vl = true;
4985 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4986 if (VM_Version::supports_evex()) {
4987 emit_simd_arith_q(0xDF, dst, src, VEX_SIMD_66);
4988 }
4989 else {
4990 emit_simd_arith(0xDF, dst, src, VEX_SIMD_66);
4991 }
4992 }
4993
4994 void Assembler::por(XMMRegister dst, XMMRegister src) {
4995 _instruction_uses_vl = true;
4996 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4997 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66);
4998 }
4999
5000 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5001 _instruction_uses_vl = true;
5002 assert(UseAVX > 0, "requires some form of AVX");
5003 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector_len);
5004 }
5005
5006 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5007 _instruction_uses_vl = true;
5008 assert(UseAVX > 0, "requires some form of AVX");
5009 if (VM_Version::supports_evex()) {
5010 _tuple_type = EVEX_FV;
5011 _input_size_in_bits = EVEX_32bit;
5012 }
5013 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector_len);
5014 }
5015
5016 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
5017 _instruction_uses_vl = true;
5018 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5019 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66);
5020 }
5021
5022 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5023 _instruction_uses_vl = true;
5024 assert(UseAVX > 0, "requires some form of AVX");
5025 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector_len);
5026 }
5027
5028 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5029 _instruction_uses_vl = true;
5030 assert(UseAVX > 0, "requires some form of AVX");
5031 if (VM_Version::supports_evex()) {
5032 _tuple_type = EVEX_FV;
5033 _input_size_in_bits = EVEX_32bit;
5034 }
5035 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector_len);
5036 }
5037
5038
5039 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5040 assert(VM_Version::supports_avx(), "");
5041 int vector_len = AVX_256bit;
5042 if (VM_Version::supports_evex()) {
5043 vector_len = AVX_512bit;
5044 }
5045 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
5046 emit_int8(0x18);
5047 emit_int8((unsigned char)(0xC0 | encode));
5048 // 0x00 - insert into lower 128 bits
5049 // 0x01 - insert into upper 128 bits
5050 emit_int8(0x01);
5051 }
5052
5053 void Assembler::vinsertf64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5054 assert(VM_Version::supports_evex(), "");
5055 int vector_len = AVX_512bit;
5056 int src_enc = src->encoding();
5057 int dst_enc = dst->encoding();
5058 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5059 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
5060 /* vex_w */ true, vector_len, /* legacy_mode */ false, /* no_mask_reg */ false);
5061 emit_int8(0x1A);
5062 emit_int8((unsigned char)(0xC0 | encode));
5063 // 0x00 - insert into lower 256 bits
5064 // 0x01 - insert into upper 256 bits
5065 emit_int8(0x01);
5066 }
5067
5068 void Assembler::vinsertf64x4h(XMMRegister dst, Address src) {
5069 assert(VM_Version::supports_evex(), "");
5070 _tuple_type = EVEX_T4;
5071 _input_size_in_bits = EVEX_64bit;
5072 InstructionMark im(this);
5073 int vector_len = AVX_512bit;
5074 assert(dst != xnoreg, "sanity");
5075 int dst_enc = dst->encoding();
5076 // swap src<->dst for encoding
5077 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, /* vex_w */ true, vector_len);
5078 emit_int8(0x1A);
5079 emit_operand(dst, src);
5080 // 0x01 - insert into upper 128 bits
5081 emit_int8(0x01);
5082 }
5083
5084 void Assembler::vinsertf32x4h(XMMRegister dst, XMMRegister nds, XMMRegister src, int value) {
5085 assert(VM_Version::supports_evex(), "");
5086 int vector_len = AVX_512bit;
5087 int src_enc = src->encoding();
5088 int dst_enc = dst->encoding();
5089 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5090 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
5091 /* vex_w */ false, vector_len, /* legacy_mode */ false, /* no_mask_reg */ false);
5092 emit_int8(0x18);
5093 emit_int8((unsigned char)(0xC0 | encode));
5094 // 0x00 - insert into q0 128 bits (0..127)
5095 // 0x01 - insert into q1 128 bits (128..255)
5096 // 0x02 - insert into q2 128 bits (256..383)
5097 // 0x03 - insert into q3 128 bits (384..511)
5098 emit_int8(value & 0x3);
5099 }
5100
5101 void Assembler::vinsertf32x4h(XMMRegister dst, Address src, int value) {
5102 assert(VM_Version::supports_evex(), "");
5103 _tuple_type = EVEX_T4;
5104 _input_size_in_bits = EVEX_32bit;
5105 InstructionMark im(this);
5106 int vector_len = AVX_512bit;
5107 assert(dst != xnoreg, "sanity");
5108 int dst_enc = dst->encoding();
5109 // swap src<->dst for encoding
5110 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, /* vex_w */ false, vector_len);
5111 emit_int8(0x18);
5112 emit_operand(dst, src);
5113 // 0x00 - insert into q0 128 bits (0..127)
5114 // 0x01 - insert into q1 128 bits (128..255)
5115 // 0x02 - insert into q2 128 bits (256..383)
5116 // 0x03 - insert into q3 128 bits (384..511)
5117 emit_int8(value & 0x3);
5118 }
5119
5120 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
5121 assert(VM_Version::supports_avx(), "");
5122 int vector_len = AVX_256bit;
5123 if (VM_Version::supports_evex()) {
5124 _tuple_type = EVEX_T4;
5125 _input_size_in_bits = EVEX_32bit;
5126 vector_len = AVX_512bit;
5127 }
5128 InstructionMark im(this);
5129 assert(dst != xnoreg, "sanity");
5130 int dst_enc = dst->encoding();
5131 // swap src<->dst for encoding
5132 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, /* vex_w */ false, vector_len);
5133 emit_int8(0x18);
5134 emit_operand(dst, src);
5135 // 0x01 - insert into upper 128 bits
5136 emit_int8(0x01);
5137 }
5138
5139 void Assembler::vextractf128h(XMMRegister dst, XMMRegister src) {
5140 assert(VM_Version::supports_avx(), "");
5141 int vector_len = AVX_256bit;
5142 if (VM_Version::supports_evex()) {
5143 vector_len = AVX_512bit;
5144 }
5145 int encode = vex_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
5146 emit_int8(0x19);
5147 emit_int8((unsigned char)(0xC0 | encode));
5148 // 0x00 - insert into lower 128 bits
5149 // 0x01 - insert into upper 128 bits
5150 emit_int8(0x01);
5151 }
5152
5153 void Assembler::vextractf128h(Address dst, XMMRegister src) {
5154 assert(VM_Version::supports_avx(), "");
5155 int vector_len = AVX_256bit;
5156 if (VM_Version::supports_evex()) {
5157 _tuple_type = EVEX_T4;
5158 _input_size_in_bits = EVEX_32bit;
5159 vector_len = AVX_512bit;
5160 }
5161 InstructionMark im(this);
5162 assert(src != xnoreg, "sanity");
5163 int src_enc = src->encoding();
5164 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, /* vex_w */ false, vector_len);
5165 emit_int8(0x19);
5166 emit_operand(src, dst);
5167 // 0x01 - extract from upper 128 bits
5168 emit_int8(0x01);
5169 }
5170
5171 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5172 assert(VM_Version::supports_avx2(), "");
5173 int vector_len = AVX_256bit;
5174 if (VM_Version::supports_evex()) {
5175 vector_len = AVX_512bit;
5176 }
5177 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
5178 emit_int8(0x38);
5179 emit_int8((unsigned char)(0xC0 | encode));
5180 // 0x00 - insert into lower 128 bits
5181 // 0x01 - insert into upper 128 bits
5182 emit_int8(0x01);
5183 }
5184
5185 void Assembler::vinserti64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5186 assert(VM_Version::supports_evex(), "");
5187 int vector_len = AVX_512bit;
5188 int src_enc = src->encoding();
5189 int dst_enc = dst->encoding();
5190 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5191 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
5192 /* vex_w */ true, vector_len, /* legacy_mode */ false, /* no_reg_mask */ false);
5193 emit_int8(0x38);
5194 emit_int8((unsigned char)(0xC0 | encode));
5195 // 0x00 - insert into lower 256 bits
5196 // 0x01 - insert into upper 256 bits
5197 emit_int8(0x01);
5198 }
5199
5200 void Assembler::vinserti128h(XMMRegister dst, Address src) {
5201 assert(VM_Version::supports_avx2(), "");
5202 int vector_len = AVX_256bit;
5203 if (VM_Version::supports_evex()) {
5204 _tuple_type = EVEX_T4;
5205 _input_size_in_bits = EVEX_32bit;
5206 vector_len = AVX_512bit;
5207 }
5208 InstructionMark im(this);
5209 assert(dst != xnoreg, "sanity");
5210 int dst_enc = dst->encoding();
5211 // swap src<->dst for encoding
5212 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, /* vex_w */ false, vector_len);
5213 emit_int8(0x38);
5214 emit_operand(dst, src);
5215 // 0x01 - insert into upper 128 bits
5216 emit_int8(0x01);
5217 }
5218
5219 void Assembler::vextracti128h(XMMRegister dst, XMMRegister src) {
5220 assert(VM_Version::supports_avx(), "");
5221 int vector_len = AVX_256bit;
5222 if (VM_Version::supports_evex()) {
5223 vector_len = AVX_512bit;
5224 }
5225 int encode = vex_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
5226 emit_int8(0x39);
5227 emit_int8((unsigned char)(0xC0 | encode));
5228 // 0x00 - insert into lower 128 bits
5229 // 0x01 - insert into upper 128 bits
5230 emit_int8(0x01);
5231 }
5232
5233 void Assembler::vextracti128h(Address dst, XMMRegister src) {
5234 assert(VM_Version::supports_avx2(), "");
5235 int vector_len = AVX_256bit;
5236 if (VM_Version::supports_evex()) {
5237 _tuple_type = EVEX_T4;
5238 _input_size_in_bits = EVEX_32bit;
5239 vector_len = AVX_512bit;
5240 }
5241 InstructionMark im(this);
5242 assert(src != xnoreg, "sanity");
5243 int src_enc = src->encoding();
5244 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, /* vex_w */ false, vector_len);
5245 emit_int8(0x39);
5246 emit_operand(src, dst);
5247 // 0x01 - extract from upper 128 bits
5248 emit_int8(0x01);
5249 }
5250
5251 void Assembler::vextracti64x4h(XMMRegister dst, XMMRegister src) {
5252 assert(VM_Version::supports_evex(), "");
5253 int vector_len = AVX_512bit;
5254 int src_enc = src->encoding();
5255 int dst_enc = dst->encoding();
5256 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
5257 /* vex_w */ true, vector_len, /* legacy_mode */ false, /* no_mask_reg */ false);
5258 emit_int8(0x3B);
5259 emit_int8((unsigned char)(0xC0 | encode));
5260 // 0x01 - extract from upper 256 bits
5261 emit_int8(0x01);
5262 }
5263
5264 void Assembler::vextracti64x2h(XMMRegister dst, XMMRegister src, int value) {
5265 assert(VM_Version::supports_evex(), "");
5266 int vector_len = AVX_512bit;
5267 int src_enc = src->encoding();
5268 int dst_enc = dst->encoding();
5269 int encode;
5270 if (VM_Version::supports_avx512dq()) {
5271 encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
5272 /* vex_w */ true, vector_len, /* legacy_mode */ false, /* no_mask_reg */ false);
5273 } else {
5274 encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
5275 /* vex_w */ false, vector_len, /* legacy_mode */ true, /* no_mask_reg */ false);
5276 }
5277 emit_int8(0x39);
5278 emit_int8((unsigned char)(0xC0 | encode));
5279 // 0x01 - extract from bits 255:128
5280 // 0x02 - extract from bits 383:256
5281 // 0x03 - extract from bits 511:384
5282 emit_int8(value & 0x3);
5283 }
5284
5285 void Assembler::vextractf64x4h(XMMRegister dst, XMMRegister src) {
5286 assert(VM_Version::supports_evex(), "");
5287 int vector_len = AVX_512bit;
5288 int src_enc = src->encoding();
5289 int dst_enc = dst->encoding();
5290 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
5291 /* vex_w */ true, vector_len, /* legacy_mode */ false, /* no_mask_reg */ false);
5292 emit_int8(0x1B);
5293 emit_int8((unsigned char)(0xC0 | encode));
5294 // 0x01 - extract from upper 256 bits
5295 emit_int8(0x01);
5296 }
5297
5298 void Assembler::vextractf64x4h(Address dst, XMMRegister src) {
5299 assert(VM_Version::supports_evex(), "");
5300 _tuple_type = EVEX_T4;
5301 _input_size_in_bits = EVEX_64bit;
5302 InstructionMark im(this);
5303 int vector_len = AVX_512bit;
5304 assert(src != xnoreg, "sanity");
5305 int src_enc = src->encoding();
5306 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
5307 /* vex_w */ true, vector_len);
5308 emit_int8(0x1B);
5309 emit_operand(src, dst);
5310 // 0x01 - extract from upper 256 bits
5311 emit_int8(0x01);
5312 }
5313
5314 void Assembler::vextractf32x4h(XMMRegister dst, XMMRegister src, int value) {
5315 assert(VM_Version::supports_evex(), "");
5316 int vector_len = AVX_512bit;
5317 int src_enc = src->encoding();
5318 int dst_enc = dst->encoding();
5319 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
5320 /* vex_w */ false, vector_len, /* legacy_mode */ false, /* no_mask_reg */ false);
5321 emit_int8(0x19);
5322 emit_int8((unsigned char)(0xC0 | encode));
5323 // 0x00 - extract from bits 127:0
5324 // 0x01 - extract from bits 255:128
5325 // 0x02 - extract from bits 383:256
5326 // 0x03 - extract from bits 511:384
5327 emit_int8(value & 0x3);
5328 }
5329
5330 void Assembler::vextractf32x4h(Address dst, XMMRegister src, int value) {
5331 assert(VM_Version::supports_evex(), "");
5332 _tuple_type = EVEX_T4;
5333 _input_size_in_bits = EVEX_32bit;
5334 InstructionMark im(this);
5335 int vector_len = AVX_512bit;
5336 assert(src != xnoreg, "sanity");
5337 int src_enc = src->encoding();
5338 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, /* vex_w */ false, vector_len);
5339 emit_int8(0x19);
5340 emit_operand(src, dst);
5341 // 0x00 - extract from bits 127:0
5342 // 0x01 - extract from bits 255:128
5343 // 0x02 - extract from bits 383:256
5344 // 0x03 - extract from bits 511:384
5345 emit_int8(value & 0x3);
5346 }
5347
5348 void Assembler::vextractf64x2h(XMMRegister dst, XMMRegister src, int value) {
5349 assert(VM_Version::supports_evex(), "");
5350 int vector_len = AVX_512bit;
5351 int src_enc = src->encoding();
5352 int dst_enc = dst->encoding();
5353 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
5354 /* vex_w */ !_legacy_mode_dq, vector_len, /* legacy_mode */ false, /* no_mask_reg */ false);
5355 emit_int8(0x19);
5356 emit_int8((unsigned char)(0xC0 | encode));
5357 // 0x01 - extract from bits 255:128
5358 // 0x02 - extract from bits 383:256
5359 // 0x03 - extract from bits 511:384
5360 emit_int8(value & 0x3);
5361 }
5362
5363 // duplicate 4-bytes integer data from src into 8 locations in dest
5364 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
5365 _instruction_uses_vl = true;
5366 assert(UseAVX > 1, "");
5367 int vector_len = AVX_256bit;
5368 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_38);
5369 emit_int8(0x58);
5370 emit_int8((unsigned char)(0xC0 | encode));
5371 }
5372
5373 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
5374 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
5375 _instruction_uses_vl = true;
5376 assert(UseAVX > 1, "");
5377 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_38);
5378 emit_int8(0x78);
5379 emit_int8((unsigned char)(0xC0 | encode));
5380 }
5381
5382 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
5383 _instruction_uses_vl = true;
5384 assert(UseAVX > 1, "");
5385 _tuple_type = EVEX_T1S;
5386 _input_size_in_bits = EVEX_8bit;
5387 InstructionMark im(this);
5388 assert(dst != xnoreg, "sanity");
5389 int dst_enc = dst->encoding();
5390 // swap src<->dst for encoding
5391 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, /* vex_w */ false, vector_len);
5392 emit_int8(0x78);
5393 emit_operand(dst, src);
5394 }
5395
5396 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
5397 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
5398 _instruction_uses_vl = true;
5399 assert(UseAVX > 1, "");
5400 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_38);
5401 emit_int8(0x79);
5402 emit_int8((unsigned char)(0xC0 | encode));
5403 }
5404
5405 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
5406 _instruction_uses_vl = true;
5407 assert(UseAVX > 1, "");
5408 _tuple_type = EVEX_T1S;
5409 _input_size_in_bits = EVEX_16bit;
5410 InstructionMark im(this);
5411 assert(dst != xnoreg, "sanity");
5412 int dst_enc = dst->encoding();
5413 // swap src<->dst for encoding
5414 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, /* vex_w */ false, vector_len);
5415 emit_int8(0x79);
5416 emit_operand(dst, src);
5417 }
5418
5419 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5420 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
5421 _instruction_uses_vl = true;
5422 assert(UseAVX > 1, "");
5423 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_38);
5424 emit_int8(0x58);
5425 emit_int8((unsigned char)(0xC0 | encode));
5426 }
5427
5428 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
5429 _instruction_uses_vl = true;
5430 assert(UseAVX > 1, "");
5431 _tuple_type = EVEX_T1S;
5432 _input_size_in_bits = EVEX_32bit;
5433 InstructionMark im(this);
5434 assert(dst != xnoreg, "sanity");
5435 int dst_enc = dst->encoding();
5436 // swap src<->dst for encoding
5437 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, /* vex_w */ false, vector_len);
5438 emit_int8(0x58);
5439 emit_operand(dst, src);
5440 }
5441
5442 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5443 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
5444 _instruction_uses_vl = true;
5445 assert(UseAVX > 1, "");
5446 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38,
5447 /* vex_w */ true, vector_len, /* legacy_mode */ false, /* no_mask_reg */ false);
5448 emit_int8(0x59);
5449 emit_int8((unsigned char)(0xC0 | encode));
5450 }
5451
5452 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
5453 _instruction_uses_vl = true;
5454 assert(UseAVX > 1, "");
5455 _tuple_type = EVEX_T1S;
5456 _input_size_in_bits = EVEX_64bit;
5457 InstructionMark im(this);
5458 assert(dst != xnoreg, "sanity");
5459 int dst_enc = dst->encoding();
5460 // swap src<->dst for encoding
5461 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, /* vex_w */ true, vector_len);
5462 emit_int8(0x59);
5463 emit_operand(dst, src);
5464 }
5465
5466 // duplicate single precision fp from src into 4|8|16 locations in dest : requires AVX512VL
5467 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
5468 _instruction_uses_vl = true;
5469 assert(UseAVX > 1, "");
5470 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38,
5471 /* vex_w */ false, vector_len, /* legacy_mode */ false, /*no_mask_reg */ false);
5472 emit_int8(0x18);
5473 emit_int8((unsigned char)(0xC0 | encode));
5474 }
5475
5476 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
5477 assert(UseAVX > 1, "");
5478 _tuple_type = EVEX_T1S;
5479 _input_size_in_bits = EVEX_32bit;
5480 InstructionMark im(this);
5481 assert(dst != xnoreg, "sanity");
5482 int dst_enc = dst->encoding();
5483 // swap src<->dst for encoding
5484 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, /* vex_w */ false, vector_len);
5485 emit_int8(0x18);
5486 emit_operand(dst, src);
5487 }
5488
5489 // duplicate double precision fp from src into 2|4|8 locations in dest : requires AVX512VL
5490 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
5491 _instruction_uses_vl = true;
5492 assert(UseAVX > 1, "");
5493 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38,
5494 /*vex_w */ true, vector_len, /* legacy_mode */ false, /*no_mask_reg */ false);
5495 emit_int8(0x19);
5496 emit_int8((unsigned char)(0xC0 | encode));
5497 }
5498
5499 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
5500 _instruction_uses_vl = true;
5501 assert(UseAVX > 1, "");
5502 _tuple_type = EVEX_T1S;
5503 _input_size_in_bits = EVEX_64bit;
5504 InstructionMark im(this);
5505 assert(dst != xnoreg, "sanity");
5506 int dst_enc = dst->encoding();
5507 // swap src<->dst for encoding
5508 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, /* vex_w */ true, vector_len);
5509 emit_int8(0x19);
5510 emit_operand(dst, src);
5511 }
5512
5513 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
5514 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
5515 _instruction_uses_vl = true;
5516 assert(VM_Version::supports_evex(), "");
5517 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38,
5518 /*vex_w */ false, vector_len, /* legacy_mode */ false, /*no_mask_reg */ false);
5519 emit_int8(0x7A);
5520 emit_int8((unsigned char)(0xC0 | encode));
5521 }
5522
5523 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
5524 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
5525 _instruction_uses_vl = true;
5526 assert(VM_Version::supports_evex(), "");
5527 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38,
5528 /* vex_w */ false, vector_len, /* legacy_mode */ false, /*no_mask_reg */ false);
5529 emit_int8(0x7B);
5530 emit_int8((unsigned char)(0xC0 | encode));
5531 }
5532
5533 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5534 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
5535 _instruction_uses_vl = true;
5536 assert(VM_Version::supports_evex(), "");
5537 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38,
5538 /* vex_w */ false, vector_len, /* legacy_mode */ false, /*no_mask_reg */ false);
5539 emit_int8(0x7C);
5540 emit_int8((unsigned char)(0xC0 | encode));
5541 }
5542
5543 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5544 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
5545 _instruction_uses_vl = true;
5546 assert(VM_Version::supports_evex(), "");
5547 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38,
5548 /* vex_w */ true, vector_len, /* legacy_mode */ false, /*no_mask_reg */ false);
5549 emit_int8(0x7C);
5550 emit_int8((unsigned char)(0xC0 | encode));
5551 }
5552
5553 // Carry-Less Multiplication Quadword
5554 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
5555 assert(VM_Version::supports_clmul(), "");
5556 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, /* no_mask_reg */ false,
5557 VEX_OPCODE_0F_3A, /* rex_w */ false, AVX_128bit, /* legacy_mode */ true);
5558 emit_int8(0x44);
5559 emit_int8((unsigned char)(0xC0 | encode));
5560 emit_int8((unsigned char)mask);
5561 }
5562
5563 // Carry-Less Multiplication Quadword
5564 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
5565 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
5566 int vector_len = AVX_128bit;
5567 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A, /* legacy_mode */ true);
5568 emit_int8(0x44);
5569 emit_int8((unsigned char)(0xC0 | encode));
5570 emit_int8((unsigned char)mask);
5571 }
5572
5573 void Assembler::vzeroupper() {
5574 assert(VM_Version::supports_avx(), "");
5575 if (UseAVX < 3)
5576 {
5577 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
5578 emit_int8(0x77);
5579 }
5580 }
5581
5582
5583 #ifndef _LP64
5584 // 32bit only pieces of the assembler
5585
5586 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
5587 // NO PREFIX AS NEVER 64BIT
5588 InstructionMark im(this);
5589 emit_int8((unsigned char)0x81);
5590 emit_int8((unsigned char)(0xF8 | src1->encoding()));
5591 emit_data(imm32, rspec, 0);
5592 }
5593
5594 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
5595 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
5596 InstructionMark im(this);
5597 emit_int8((unsigned char)0x81);
5598 emit_operand(rdi, src1);
5599 emit_data(imm32, rspec, 0);
6063 emit_int8(simd_pre[pre]);
6064 }
6065 if (rex_w) {
6066 prefixq(adr, xreg);
6067 } else {
6068 prefix(adr, xreg);
6069 }
6070 if (opc > 0) {
6071 emit_int8(0x0F);
6072 int opc2 = simd_opc[opc];
6073 if (opc2 > 0) {
6074 emit_int8(opc2);
6075 }
6076 }
6077 }
6078
6079 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6080 if (pre > 0) {
6081 emit_int8(simd_pre[pre]);
6082 }
6083 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) :
6084 prefix_and_encode(dst_enc, src_enc);
6085 if (opc > 0) {
6086 emit_int8(0x0F);
6087 int opc2 = simd_opc[opc];
6088 if (opc2 > 0) {
6089 emit_int8(opc2);
6090 }
6091 }
6092 return encode;
6093 }
6094
6095
6096 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, int vector_len) {
6097 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
6098 prefix(VEX_3bytes);
6099
6100 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
6101 byte1 = (~byte1) & 0xE0;
6102 byte1 |= opc;
6103 emit_int8(byte1);
6104
6105 int byte2 = ((~nds_enc) & 0xf) << 3;
6106 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
6107 emit_int8(byte2);
6108 } else {
6109 prefix(VEX_2bytes);
6110
6111 int byte1 = vex_r ? VEX_R : 0;
6112 byte1 = (~byte1) & 0x80;
6113 byte1 |= ((~nds_enc) & 0xf) << 3;
6114 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
6115 emit_int8(byte1);
6116 }
6117 }
6118
6119 // This is a 4 byte encoding
6120 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, bool evex_r, bool evex_v,
6121 int nds_enc, VexSimdPrefix pre, VexOpcode opc,
6122 bool is_extended_context, bool is_merge_context,
6123 int vector_len, bool no_mask_reg ){
6124 // EVEX 0x62 prefix
6125 prefix(EVEX_4bytes);
6126 _evex_encoding = (vex_w ? VEX_W : 0) | (evex_r ? EVEX_Rb : 0);
6127
6128 // P0: byte 2, initialized to RXBR`00mm
6129 // instead of not'd
6130 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
6131 byte2 = (~byte2) & 0xF0;
6132 // confine opc opcode extensions in mm bits to lower two bits
6133 // of form {0F, 0F_38, 0F_3A}
6134 byte2 |= opc;
6135 emit_int8(byte2);
6136
6137 // P1: byte 3 as Wvvvv1pp
6138 int byte3 = ((~nds_enc) & 0xf) << 3;
6139 // p[10] is always 1
6140 byte3 |= EVEX_F;
6141 byte3 |= (vex_w & 1) << 7;
6142 // confine pre opcode extensions in pp bits to lower two bits
6143 // of form {66, F3, F2}
6144 byte3 |= pre;
6145 emit_int8(byte3);
6146
6147 // P2: byte 4 as zL'Lbv'aaa
6148 int byte4 = (no_mask_reg) ? 0 : 1; // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
6149 // EVEX.v` for extending EVEX.vvvv or VIDX
6150 byte4 |= (evex_v ? 0: EVEX_V);
6151 // third EXEC.b for broadcast actions
6152 byte4 |= (is_extended_context ? EVEX_Rb : 0);
6153 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
6154 byte4 |= ((vector_len) & 0x3) << 5;
6155 // last is EVEX.z for zero/merge actions
6156 byte4 |= (is_merge_context ? EVEX_Z : 0);
6157 emit_int8(byte4);
6158 }
6159
6160 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre,
6161 VexOpcode opc, bool vex_w, int vector_len, bool legacy_mode, bool no_mask_reg) {
6162 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
6163 bool vex_b = adr.base_needs_rex();
6164 bool vex_x = adr.index_needs_rex();
6165 _avx_vector_len = vector_len;
6166
6167 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6168 if (_legacy_mode_vl && _instruction_uses_vl) {
6169 switch (vector_len) {
6170 case AVX_128bit:
6171 case AVX_256bit:
6172 legacy_mode = true;
6173 break;
6174 }
6175 }
6176
6177 if ((UseAVX > 2) && (legacy_mode == false))
6178 {
6179 bool evex_r = (xreg_enc >= 16);
6180 bool evex_v = (nds_enc >= 16);
6181 _is_evex_instruction = true;
6182 evex_prefix(vex_r, vex_b, vex_x, vex_w, evex_r, evex_v, nds_enc, pre, opc, false, false, vector_len, no_mask_reg);
6183 } else {
6184 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector_len);
6185 }
6186 _instruction_uses_vl = false;
6187 }
6188
6189 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,
6190 bool vex_w, int vector_len, bool legacy_mode, bool no_mask_reg ) {
6191 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
6192 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
6193 bool vex_x = false;
6194 _avx_vector_len = vector_len;
6195
6196 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6197 if (_legacy_mode_vl && _instruction_uses_vl) {
6198 switch (vector_len) {
6199 case AVX_128bit:
6200 case AVX_256bit:
6201 legacy_mode = true;
6202 break;
6203 }
6204 }
6205
6206 if ((UseAVX > 2) && (legacy_mode == false))
6207 {
6208 bool evex_r = (dst_enc >= 16);
6209 bool evex_v = (nds_enc >= 16);
6210 // can use vex_x as bank extender on rm encoding
6211 vex_x = (src_enc >= 16);
6212 evex_prefix(vex_r, vex_b, vex_x, vex_w, evex_r, evex_v, nds_enc, pre, opc, false, false, vector_len, no_mask_reg);
6213 } else {
6214 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector_len);
6215 }
6216
6217 _instruction_uses_vl = false;
6218
6219 // return modrm byte components for operands
6220 return (((dst_enc & 7) << 3) | (src_enc & 7));
6221 }
6222
6223
6224 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
6225 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len, bool legacy_mode) {
6226 if (UseAVX > 0) {
6227 int xreg_enc = xreg->encoding();
6228 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6229 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector_len, legacy_mode, no_mask_reg);
6230 } else {
6231 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
6232 rex_prefix(adr, xreg, pre, opc, rex_w);
6233 }
6234 }
6235
6236 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
6237 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len, bool legacy_mode) {
6238 int dst_enc = dst->encoding();
6239 int src_enc = src->encoding();
6240 if (UseAVX > 0) {
6241 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6242 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, legacy_mode, no_mask_reg);
6243 } else {
6244 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
6245 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w);
6246 }
6247 }
6248
6249 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, KRegister src, VexSimdPrefix pre,
6250 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len) {
6251 int dst_enc = dst->encoding();
6252 int src_enc = src->encoding();
6253 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6254 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, true, no_mask_reg);
6255 }
6256
6257 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, Register src, VexSimdPrefix pre,
6258 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len) {
6259 int dst_enc = dst->encoding();
6260 int src_enc = src->encoding();
6261 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6262 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, true, no_mask_reg);
6263 }
6264
6265 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
6266 InstructionMark im(this);
6267 simd_prefix(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, false, AVX_128bit, legacy_mode);
6268 emit_int8(opcode);
6269 emit_operand(dst, src);
6270 }
6271
6272 void Assembler::emit_simd_arith_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg) {
6273 InstructionMark im(this);
6274 simd_prefix_q(dst, dst, src, pre, no_mask_reg);
6275 emit_int8(opcode);
6276 emit_operand(dst, src);
6277 }
6278
6279 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
6280 int encode = simd_prefix_and_encode(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, false, AVX_128bit, legacy_mode);
6281 emit_int8(opcode);
6282 emit_int8((unsigned char)(0xC0 | encode));
6283 }
6284
6285 void Assembler::emit_simd_arith_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg) {
6286 int encode = simd_prefix_and_encode(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, true, AVX_128bit);
6287 emit_int8(opcode);
6288 emit_int8((unsigned char)(0xC0 | encode));
6289 }
6290
6291 // Versions with no second source register (non-destructive source).
6292 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool opNoRegMask) {
6293 InstructionMark im(this);
6294 simd_prefix(dst, xnoreg, src, pre, opNoRegMask);
6295 emit_int8(opcode);
6296 emit_operand(dst, src);
6297 }
6298
6299 void Assembler::emit_simd_arith_nonds_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool opNoRegMask) {
6300 InstructionMark im(this);
6301 simd_prefix_q(dst, xnoreg, src, pre, opNoRegMask);
6302 emit_int8(opcode);
6303 emit_operand(dst, src);
6304 }
6305
6306 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
6307 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre, no_mask_reg, VEX_OPCODE_0F, false, AVX_128bit, legacy_mode);
6308 emit_int8(opcode);
6309 emit_int8((unsigned char)(0xC0 | encode));
6310 }
6311
6312 void Assembler::emit_simd_arith_nonds_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg) {
6313 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre, no_mask_reg, VEX_OPCODE_0F, true);
6314 emit_int8(opcode);
6315 emit_int8((unsigned char)(0xC0 | encode));
6316 }
6317
6318 // 3-operands AVX instructions
6319 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, Address src,
6320 VexSimdPrefix pre, int vector_len, bool no_mask_reg, bool legacy_mode) {
6321 InstructionMark im(this);
6322 vex_prefix(dst, nds, src, pre, vector_len, no_mask_reg, legacy_mode);
6323 emit_int8(opcode);
6324 emit_operand(dst, src);
6325 }
6326
6327 void Assembler::emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds,
6328 Address src, VexSimdPrefix pre, int vector_len, bool no_mask_reg) {
6329 InstructionMark im(this);
6330 vex_prefix_q(dst, nds, src, pre, vector_len, no_mask_reg);
6331 emit_int8(opcode);
6332 emit_operand(dst, src);
6333 }
6334
6335 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
6336 VexSimdPrefix pre, int vector_len, bool no_mask_reg, bool legacy_mode) {
6337 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector_len, VEX_OPCODE_0F, legacy_mode, no_mask_reg);
6338 emit_int8(opcode);
6339 emit_int8((unsigned char)(0xC0 | encode));
6340 }
6341
6342 void Assembler::emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
6343 VexSimdPrefix pre, int vector_len, bool no_mask_reg) {
6344 int src_enc = src->encoding();
6345 int dst_enc = dst->encoding();
6346 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6347 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, VEX_OPCODE_0F, true, vector_len, false, no_mask_reg);
6348 emit_int8(opcode);
6349 emit_int8((unsigned char)(0xC0 | encode));
6350 }
6351
6352 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
6353 assert(VM_Version::supports_avx(), "");
6354 assert(!VM_Version::supports_evex(), "");
6355 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F, /* no_mask_reg */ false);
6356 emit_int8((unsigned char)0xC2);
6357 emit_int8((unsigned char)(0xC0 | encode));
6358 emit_int8((unsigned char)(0xF & cop));
6359 }
6360
6361 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
6362 assert(VM_Version::supports_avx(), "");
6363 assert(!VM_Version::supports_evex(), "");
6364 int encode = vex_prefix_and_encode(dst, nds, src1, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A, /* no_mask_reg */ false);
6365 emit_int8((unsigned char)0x4B);
6366 emit_int8((unsigned char)(0xC0 | encode));
6367 int src2_enc = src2->encoding();
6368 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
6369 }
6370
6371
6372 #ifndef _LP64
6373
6374 void Assembler::incl(Register dst) {
6375 // Don't use it directly. Use MacroAssembler::incrementl() instead.
6376 emit_int8(0x40 | dst->encoding());
6377 }
6378
6379 void Assembler::lea(Register dst, Address src) {
6380 leal(dst, src);
6381 }
6382
6383 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
6384 InstructionMark im(this);
6881
6882 void Assembler::andq(Register dst, int32_t imm32) {
6883 (void) prefixq_and_encode(dst->encoding());
6884 emit_arith(0x81, 0xE0, dst, imm32);
6885 }
6886
6887 void Assembler::andq(Register dst, Address src) {
6888 InstructionMark im(this);
6889 prefixq(src, dst);
6890 emit_int8(0x23);
6891 emit_operand(dst, src);
6892 }
6893
6894 void Assembler::andq(Register dst, Register src) {
6895 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6896 emit_arith(0x23, 0xC0, dst, src);
6897 }
6898
6899 void Assembler::andnq(Register dst, Register src1, Register src2) {
6900 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6901 int encode = vex_prefix_0F38_and_encode_q_legacy(dst, src1, src2);
6902 emit_int8((unsigned char)0xF2);
6903 emit_int8((unsigned char)(0xC0 | encode));
6904 }
6905
6906 void Assembler::andnq(Register dst, Register src1, Address src2) {
6907 InstructionMark im(this);
6908 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6909 vex_prefix_0F38_q_legacy(dst, src1, src2);
6910 emit_int8((unsigned char)0xF2);
6911 emit_operand(dst, src2);
6912 }
6913
6914 void Assembler::bsfq(Register dst, Register src) {
6915 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6916 emit_int8(0x0F);
6917 emit_int8((unsigned char)0xBC);
6918 emit_int8((unsigned char)(0xC0 | encode));
6919 }
6920
6921 void Assembler::bsrq(Register dst, Register src) {
6922 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6923 emit_int8(0x0F);
6924 emit_int8((unsigned char)0xBD);
6925 emit_int8((unsigned char)(0xC0 | encode));
6926 }
6927
6928 void Assembler::bswapq(Register reg) {
6929 int encode = prefixq_and_encode(reg->encoding());
6930 emit_int8(0x0F);
6931 emit_int8((unsigned char)(0xC8 | encode));
6932 }
6933
6934 void Assembler::blsiq(Register dst, Register src) {
6935 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6936 int encode = vex_prefix_0F38_and_encode_q_legacy(rbx, dst, src);
6937 emit_int8((unsigned char)0xF3);
6938 emit_int8((unsigned char)(0xC0 | encode));
6939 }
6940
6941 void Assembler::blsiq(Register dst, Address src) {
6942 InstructionMark im(this);
6943 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6944 vex_prefix_0F38_q_legacy(rbx, dst, src);
6945 emit_int8((unsigned char)0xF3);
6946 emit_operand(rbx, src);
6947 }
6948
6949 void Assembler::blsmskq(Register dst, Register src) {
6950 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6951 int encode = vex_prefix_0F38_and_encode_q_legacy(rdx, dst, src);
6952 emit_int8((unsigned char)0xF3);
6953 emit_int8((unsigned char)(0xC0 | encode));
6954 }
6955
6956 void Assembler::blsmskq(Register dst, Address src) {
6957 InstructionMark im(this);
6958 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6959 vex_prefix_0F38_q_legacy(rdx, dst, src);
6960 emit_int8((unsigned char)0xF3);
6961 emit_operand(rdx, src);
6962 }
6963
6964 void Assembler::blsrq(Register dst, Register src) {
6965 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6966 int encode = vex_prefix_0F38_and_encode_q_legacy(rcx, dst, src);
6967 emit_int8((unsigned char)0xF3);
6968 emit_int8((unsigned char)(0xC0 | encode));
6969 }
6970
6971 void Assembler::blsrq(Register dst, Address src) {
6972 InstructionMark im(this);
6973 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6974 vex_prefix_0F38_q_legacy(rcx, dst, src);
6975 emit_int8((unsigned char)0xF3);
6976 emit_operand(rcx, src);
6977 }
6978
6979 void Assembler::cdqq() {
6980 prefix(REX_W);
6981 emit_int8((unsigned char)0x99);
6982 }
6983
6984 void Assembler::clflush(Address adr) {
6985 prefix(adr);
6986 emit_int8(0x0F);
6987 emit_int8((unsigned char)0xAE);
6988 emit_operand(rdi, adr);
6989 }
6990
6991 void Assembler::cmovq(Condition cc, Register dst, Register src) {
6992 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6993 emit_int8(0x0F);
6994 emit_int8(0x40 | cc);
7028 emit_arith(0x3B, 0xC0, dst, src);
7029 }
7030
7031 void Assembler::cmpq(Register dst, Address src) {
7032 InstructionMark im(this);
7033 prefixq(src, dst);
7034 emit_int8(0x3B);
7035 emit_operand(dst, src);
7036 }
7037
7038 void Assembler::cmpxchgq(Register reg, Address adr) {
7039 InstructionMark im(this);
7040 prefixq(adr, reg);
7041 emit_int8(0x0F);
7042 emit_int8((unsigned char)0xB1);
7043 emit_operand(reg, adr);
7044 }
7045
7046 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
7047 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7048 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2, /* no_mask_reg */ true);
7049 emit_int8(0x2A);
7050 emit_int8((unsigned char)(0xC0 | encode));
7051 }
7052
7053 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
7054 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7055 if (VM_Version::supports_evex()) {
7056 _tuple_type = EVEX_T1S;
7057 _input_size_in_bits = EVEX_32bit;
7058 }
7059 InstructionMark im(this);
7060 simd_prefix_q(dst, dst, src, VEX_SIMD_F2, /* no_mask_reg */ true);
7061 emit_int8(0x2A);
7062 emit_operand(dst, src);
7063 }
7064
7065 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
7066 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7067 if (VM_Version::supports_evex()) {
7068 _tuple_type = EVEX_T1S;
7069 _input_size_in_bits = EVEX_32bit;
7070 }
7071 InstructionMark im(this);
7072 simd_prefix_q(dst, dst, src, VEX_SIMD_F3, /* no_mask_reg */ true);
7073 emit_int8(0x2A);
7074 emit_operand(dst, src);
7075 }
7076
7077 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
7078 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7079 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, /* no_mask_reg */ true);
7080 emit_int8(0x2C);
7081 emit_int8((unsigned char)(0xC0 | encode));
7082 }
7083
7084 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
7085 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7086 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, /* no_mask_reg */ true);
7087 emit_int8(0x2C);
7088 emit_int8((unsigned char)(0xC0 | encode));
7089 }
7090
7091 void Assembler::decl(Register dst) {
7092 // Don't use it directly. Use MacroAssembler::decrementl() instead.
7093 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
7094 int encode = prefix_and_encode(dst->encoding());
7095 emit_int8((unsigned char)0xFF);
7096 emit_int8((unsigned char)(0xC8 | encode));
7097 }
7098
7099 void Assembler::decq(Register dst) {
7100 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7101 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7102 int encode = prefixq_and_encode(dst->encoding());
7103 emit_int8((unsigned char)0xFF);
7104 emit_int8(0xC8 | encode);
7105 }
7106
7249 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
7250 InstructionMark im(this);
7251 prefix(src1);
7252 emit_int8((unsigned char)0x81);
7253 emit_operand(rax, src1, 4);
7254 emit_data((int)imm32, rspec, narrow_oop_operand);
7255 }
7256
7257 void Assembler::lzcntq(Register dst, Register src) {
7258 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
7259 emit_int8((unsigned char)0xF3);
7260 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7261 emit_int8(0x0F);
7262 emit_int8((unsigned char)0xBD);
7263 emit_int8((unsigned char)(0xC0 | encode));
7264 }
7265
7266 void Assembler::movdq(XMMRegister dst, Register src) {
7267 // table D-1 says MMX/SSE2
7268 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7269 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66, /* no_mask_reg */ true);
7270 emit_int8(0x6E);
7271 emit_int8((unsigned char)(0xC0 | encode));
7272 }
7273
7274 void Assembler::movdq(Register dst, XMMRegister src) {
7275 // table D-1 says MMX/SSE2
7276 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7277 // swap src/dst to get correct prefix
7278 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66, /* no_mask_reg */ true);
7279 emit_int8(0x7E);
7280 emit_int8((unsigned char)(0xC0 | encode));
7281 }
7282
7283 void Assembler::movq(Register dst, Register src) {
7284 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7285 emit_int8((unsigned char)0x8B);
7286 emit_int8((unsigned char)(0xC0 | encode));
7287 }
7288
7289 void Assembler::movq(Register dst, Address src) {
7290 InstructionMark im(this);
7291 prefixq(src, dst);
7292 emit_int8((unsigned char)0x8B);
7293 emit_operand(dst, src);
7294 }
7295
7296 void Assembler::movq(Address dst, Register src) {
7297 InstructionMark im(this);
7298 prefixq(dst, src);
7391 emit_int8((unsigned char)0x0F);
7392 emit_int8((unsigned char)0xB7);
7393 emit_int8((unsigned char)(0xC0 | encode));
7394 }
7395
7396 void Assembler::mulq(Address src) {
7397 InstructionMark im(this);
7398 prefixq(src);
7399 emit_int8((unsigned char)0xF7);
7400 emit_operand(rsp, src);
7401 }
7402
7403 void Assembler::mulq(Register src) {
7404 int encode = prefixq_and_encode(src->encoding());
7405 emit_int8((unsigned char)0xF7);
7406 emit_int8((unsigned char)(0xE0 | encode));
7407 }
7408
7409 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
7410 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
7411 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38,
7412 /* vex_w */ true, AVX_128bit, /* legacy_mode */ true, /* no_mask_reg */ false);
7413 emit_int8((unsigned char)0xF6);
7414 emit_int8((unsigned char)(0xC0 | encode));
7415 }
7416
7417 void Assembler::negq(Register dst) {
7418 int encode = prefixq_and_encode(dst->encoding());
7419 emit_int8((unsigned char)0xF7);
7420 emit_int8((unsigned char)(0xD8 | encode));
7421 }
7422
7423 void Assembler::notq(Register dst) {
7424 int encode = prefixq_and_encode(dst->encoding());
7425 emit_int8((unsigned char)0xF7);
7426 emit_int8((unsigned char)(0xD0 | encode));
7427 }
7428
7429 void Assembler::orq(Address dst, int32_t imm32) {
7430 InstructionMark im(this);
7431 prefixq(dst);
7432 emit_int8((unsigned char)0x81);
7554 emit_int8((unsigned char)(0xD8 | encode));
7555 emit_int8(imm8);
7556 }
7557 }
7558
7559 void Assembler::rorq(Register dst, int imm8) {
7560 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7561 int encode = prefixq_and_encode(dst->encoding());
7562 if (imm8 == 1) {
7563 emit_int8((unsigned char)0xD1);
7564 emit_int8((unsigned char)(0xC8 | encode));
7565 } else {
7566 emit_int8((unsigned char)0xC1);
7567 emit_int8((unsigned char)(0xc8 | encode));
7568 emit_int8(imm8);
7569 }
7570 }
7571
7572 void Assembler::rorxq(Register dst, Register src, int imm8) {
7573 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
7574 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A,
7575 /* vex_w */ true, AVX_128bit, /* legacy_mode */ true, /* no_mask_reg */ false);
7576 emit_int8((unsigned char)0xF0);
7577 emit_int8((unsigned char)(0xC0 | encode));
7578 emit_int8(imm8);
7579 }
7580
7581 void Assembler::sarq(Register dst, int imm8) {
7582 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7583 int encode = prefixq_and_encode(dst->encoding());
7584 if (imm8 == 1) {
7585 emit_int8((unsigned char)0xD1);
7586 emit_int8((unsigned char)(0xF8 | encode));
7587 } else {
7588 emit_int8((unsigned char)0xC1);
7589 emit_int8((unsigned char)(0xF8 | encode));
7590 emit_int8(imm8);
7591 }
7592 }
7593
7594 void Assembler::sarq(Register dst) {
7595 int encode = prefixq_and_encode(dst->encoding());
|
296 }
297 }
298
299
300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
301 assert(isByte(op1) && isByte(op2), "wrong opcode");
302 emit_int8(op1);
303 emit_int8(op2 | encode(dst) << 3 | encode(src));
304 }
305
306
307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
309 int mod_idx = 0;
310 // We will test if the displacement fits the compressed format and if so
311 // apply the compression to the displacment iff the result is8bit.
312 if (VM_Version::supports_evex() && is_evex_inst) {
313 switch (cur_tuple_type) {
314 case EVEX_FV:
315 if ((cur_encoding & VEX_W) == VEX_W) {
316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
317 } else {
318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
319 }
320 break;
321
322 case EVEX_HV:
323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
324 break;
325
326 case EVEX_FVM:
327 break;
328
329 case EVEX_T1S:
330 switch (in_size_in_bits) {
331 case EVEX_8bit:
332 break;
333
334 case EVEX_16bit:
335 mod_idx = 1;
336 break;
377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
379 if ((disp % disp_factor) == 0) {
380 int new_disp = disp / disp_factor;
381 if ((-0x80 <= new_disp && new_disp < 0x80)) {
382 disp = new_disp;
383 }
384 } else {
385 return false;
386 }
387 }
388 }
389 return (-0x80 <= disp && disp < 0x80);
390 }
391
392
393 bool Assembler::emit_compressed_disp_byte(int &disp) {
394 int mod_idx = 0;
395 // We will test if the displacement fits the compressed format and if so
396 // apply the compression to the displacment iff the result is8bit.
397 if (VM_Version::supports_evex() && (_attributes != NULL) && _attributes->is_evex_instruction()) {
398 int evex_encoding = _attributes->get_evex_encoding();
399 int tuple_type = _attributes->get_tuple_type();
400 switch (tuple_type) {
401 case EVEX_FV:
402 if ((evex_encoding & VEX_W) == VEX_W) {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
404 } else {
405 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
406 }
407 break;
408
409 case EVEX_HV:
410 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
411 break;
412
413 case EVEX_FVM:
414 break;
415
416 case EVEX_T1S:
417 switch (_attributes->get_input_size()) {
418 case EVEX_8bit:
419 break;
420
421 case EVEX_16bit:
422 mod_idx = 1;
423 break;
424
425 case EVEX_32bit:
426 mod_idx = 2;
427 break;
428
429 case EVEX_64bit:
430 mod_idx = 3;
431 break;
432 }
433 break;
434
435 case EVEX_T1F:
436 case EVEX_T2:
437 case EVEX_T4:
438 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
439 break;
440
441 case EVEX_T8:
442 break;
443
444 case EVEX_HVM:
445 break;
446
447 case EVEX_QVM:
448 break;
449
450 case EVEX_OVM:
451 break;
452
453 case EVEX_M128:
454 break;
455
456 case EVEX_DUP:
457 break;
458
459 default:
460 assert(0, "no valid evex tuple_table entry");
461 break;
462 }
463
464 int vector_len = _attributes->get_vector_len();
465 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
466 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
467 if ((disp % disp_factor) == 0) {
468 int new_disp = disp / disp_factor;
469 if (is8bit(new_disp)) {
470 disp = new_disp;
471 }
472 } else {
473 return false;
474 }
475 }
476 }
477 return is8bit(disp);
478 }
479
480
481 void Assembler::emit_operand(Register reg, Register base, Register index,
482 Address::ScaleFactor scale, int disp,
483 RelocationHolder const& rspec,
484 int rip_relative_correction) {
485 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
486
577 // at the start of the instruction. That needs more correction here.
578 // intptr_t disp = target - next_ip;
579 assert(inst_mark() != NULL, "must be inside InstructionMark");
580 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
581 int64_t adjusted = disp;
582 // Do rip-rel adjustment for 64bit
583 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
584 assert(is_simm32(adjusted),
585 "must be 32bit offset (RIP relative address)");
586 emit_data((int32_t) adjusted, rspec, disp32_operand);
587
588 } else {
589 // 32bit never did this, did everything as the rip-rel/disp code above
590 // [disp] ABSOLUTE
591 // [00 reg 100][00 100 101] disp32
592 emit_int8(0x04 | regenc);
593 emit_int8(0x25);
594 emit_data(disp, rspec, disp32_operand);
595 }
596 }
597 }
598
599 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
600 Address::ScaleFactor scale, int disp,
601 RelocationHolder const& rspec) {
602 if (UseAVX > 2) {
603 int xreg_enc = reg->encoding();
604 if (xreg_enc > 15) {
605 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
606 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
607 return;
608 }
609 }
610 emit_operand((Register)reg, base, index, scale, disp, rspec);
611 }
612
613 // Secret local extension to Assembler::WhichOperand:
614 #define end_pc_operand (_WhichOperand_limit)
615
616 address Assembler::locate_operand(address inst, WhichOperand which) {
755 tail_size = 1;
756 case 0x38: // ptest, pmovzxbw
757 ip++; // skip opcode
758 debug_only(has_disp32 = true); // has both kinds of operands!
759 break;
760
761 case 0x70: // pshufd r, r/a, #8
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 case 0x73: // psrldq r, #8
764 tail_size = 1;
765 break;
766
767 case 0x12: // movlps
768 case 0x28: // movaps
769 case 0x2E: // ucomiss
770 case 0x2F: // comiss
771 case 0x54: // andps
772 case 0x55: // andnps
773 case 0x56: // orps
774 case 0x57: // xorps
775 case 0x59: // mulpd
776 case 0x6E: // movd
777 case 0x7E: // movd
778 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
779 debug_only(has_disp32 = true);
780 break;
781
782 case 0xAD: // shrd r, a, %cl
783 case 0xAF: // imul r, a
784 case 0xBE: // movsbl r, a (movsxb)
785 case 0xBF: // movswl r, a (movsxw)
786 case 0xB6: // movzbl r, a (movzxb)
787 case 0xB7: // movzwl r, a (movzxw)
788 case REP16(0x40): // cmovl cc, r, a
789 case 0xB0: // cmpxchgb
790 case 0xB1: // cmpxchg
791 case 0xC1: // xaddl
792 case 0xC7: // cmpxchg8
793 case REP16(0x90): // setcc a
794 debug_only(has_disp32 = true);
795 // fall out of the switch to decode the address
1219 emit_int8(0x0F);
1220 emit_int8(0x1F);
1221 emit_int8((unsigned char)0x80);
1222 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1223 emit_int32(0); // 32-bits offset (4 bytes)
1224 }
1225
1226 void Assembler::addr_nop_8() {
1227 assert(UseAddressNop, "no CPU support");
1228 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1229 emit_int8(0x0F);
1230 emit_int8(0x1F);
1231 emit_int8((unsigned char)0x84);
1232 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1233 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1234 emit_int32(0); // 32-bits offset (4 bytes)
1235 }
1236
1237 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1238 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1239 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1240 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1241 emit_int8(0x58);
1242 emit_int8((unsigned char)(0xC0 | encode));
1243 }
1244
1245 void Assembler::addsd(XMMRegister dst, Address src) {
1246 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1247 InstructionMark im(this);
1248 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1249 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1250 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1251 emit_int8(0x58);
1252 emit_operand(dst, src);
1253 }
1254
1255 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1256 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1257 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1258 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1259 emit_int8(0x58);
1260 emit_int8((unsigned char)(0xC0 | encode));
1261 }
1262
1263 void Assembler::addss(XMMRegister dst, Address src) {
1264 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1265 InstructionMark im(this);
1266 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1267 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1268 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1269 emit_int8(0x58);
1270 emit_operand(dst, src);
1271 }
1272
1273 void Assembler::aesdec(XMMRegister dst, Address src) {
1274 assert(VM_Version::supports_aes(), "");
1275 InstructionMark im(this);
1276 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1277 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1278 emit_int8((unsigned char)0xDE);
1279 emit_operand(dst, src);
1280 }
1281
1282 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1283 assert(VM_Version::supports_aes(), "");
1284 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1285 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1286 emit_int8((unsigned char)0xDE);
1287 emit_int8(0xC0 | encode);
1288 }
1289
1290 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1291 assert(VM_Version::supports_aes(), "");
1292 InstructionMark im(this);
1293 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1294 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1295 emit_int8((unsigned char)0xDF);
1296 emit_operand(dst, src);
1297 }
1298
1299 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1300 assert(VM_Version::supports_aes(), "");
1301 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1302 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1303 emit_int8((unsigned char)0xDF);
1304 emit_int8((unsigned char)(0xC0 | encode));
1305 }
1306
1307 void Assembler::aesenc(XMMRegister dst, Address src) {
1308 assert(VM_Version::supports_aes(), "");
1309 InstructionMark im(this);
1310 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1311 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1312 emit_int8((unsigned char)0xDC);
1313 emit_operand(dst, src);
1314 }
1315
1316 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1317 assert(VM_Version::supports_aes(), "");
1318 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1319 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1320 emit_int8((unsigned char)0xDC);
1321 emit_int8(0xC0 | encode);
1322 }
1323
1324 void Assembler::aesenclast(XMMRegister dst, Address src) {
1325 assert(VM_Version::supports_aes(), "");
1326 InstructionMark im(this);
1327 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1328 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1329 emit_int8((unsigned char)0xDD);
1330 emit_operand(dst, src);
1331 }
1332
1333 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1334 assert(VM_Version::supports_aes(), "");
1335 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1336 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1337 emit_int8((unsigned char)0xDD);
1338 emit_int8((unsigned char)(0xC0 | encode));
1339 }
1340
1341 void Assembler::andl(Address dst, int32_t imm32) {
1342 InstructionMark im(this);
1343 prefix(dst);
1344 emit_int8((unsigned char)0x81);
1345 emit_operand(rsp, dst, 4);
1346 emit_int32(imm32);
1347 }
1348
1349 void Assembler::andl(Register dst, int32_t imm32) {
1350 prefix(dst);
1351 emit_arith(0x81, 0xE0, dst, imm32);
1352 }
1353
1354 void Assembler::andl(Register dst, Address src) {
1355 InstructionMark im(this);
1356 prefix(src, dst);
1357 emit_int8(0x23);
1358 emit_operand(dst, src);
1359 }
1360
1361 void Assembler::andl(Register dst, Register src) {
1362 (void) prefix_and_encode(dst->encoding(), src->encoding());
1363 emit_arith(0x23, 0xC0, dst, src);
1364 }
1365
1366 void Assembler::andnl(Register dst, Register src1, Register src2) {
1367 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1368 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1369 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1370 emit_int8((unsigned char)0xF2);
1371 emit_int8((unsigned char)(0xC0 | encode));
1372 }
1373
1374 void Assembler::andnl(Register dst, Register src1, Address src2) {
1375 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1376 InstructionMark im(this);
1377 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1378 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1379 emit_int8((unsigned char)0xF2);
1380 emit_operand(dst, src2);
1381 }
1382
1383 void Assembler::bsfl(Register dst, Register src) {
1384 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1385 emit_int8(0x0F);
1386 emit_int8((unsigned char)0xBC);
1387 emit_int8((unsigned char)(0xC0 | encode));
1388 }
1389
1390 void Assembler::bsrl(Register dst, Register src) {
1391 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1392 emit_int8(0x0F);
1393 emit_int8((unsigned char)0xBD);
1394 emit_int8((unsigned char)(0xC0 | encode));
1395 }
1396
1397 void Assembler::bswapl(Register reg) { // bswap
1398 int encode = prefix_and_encode(reg->encoding());
1399 emit_int8(0x0F);
1400 emit_int8((unsigned char)(0xC8 | encode));
1401 }
1402
1403 void Assembler::blsil(Register dst, Register src) {
1404 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1405 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1406 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1407 emit_int8((unsigned char)0xF3);
1408 emit_int8((unsigned char)(0xC0 | encode));
1409 }
1410
1411 void Assembler::blsil(Register dst, Address src) {
1412 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1413 InstructionMark im(this);
1414 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1415 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1416 emit_int8((unsigned char)0xF3);
1417 emit_operand(rbx, src);
1418 }
1419
1420 void Assembler::blsmskl(Register dst, Register src) {
1421 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1422 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1423 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1424 emit_int8((unsigned char)0xF3);
1425 emit_int8((unsigned char)(0xC0 | encode));
1426 }
1427
1428 void Assembler::blsmskl(Register dst, Address src) {
1429 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1430 InstructionMark im(this);
1431 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1432 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1433 emit_int8((unsigned char)0xF3);
1434 emit_operand(rdx, src);
1435 }
1436
1437 void Assembler::blsrl(Register dst, Register src) {
1438 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1439 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1440 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1441 emit_int8((unsigned char)0xF3);
1442 emit_int8((unsigned char)(0xC0 | encode));
1443 }
1444
1445 void Assembler::blsrl(Register dst, Address src) {
1446 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1447 InstructionMark im(this);
1448 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1449 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1450 emit_int8((unsigned char)0xF3);
1451 emit_operand(rcx, src);
1452 }
1453
1454 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1455 // suspect disp32 is always good
1456 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1457
1458 if (L.is_bound()) {
1459 const int long_size = 5;
1460 int offs = (int)( target(L) - pc() );
1461 assert(offs <= 0, "assembler error");
1462 InstructionMark im(this);
1463 // 1110 1000 #32-bit disp
1464 emit_int8((unsigned char)0xE8);
1465 emit_data(offs - long_size, rtype, operand);
1466 } else {
1467 InstructionMark im(this);
1468 // 1110 1000 #32-bit disp
1469 L.add_patch_at(code(), locator());
1576 emit_int8(0x0F);
1577 emit_int8((unsigned char)0xB1);
1578 emit_operand(reg, adr);
1579 }
1580
1581 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1582 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1583 // The ZF is set if the compared values were equal, and cleared otherwise.
1584 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1585 InstructionMark im(this);
1586 prefix(adr, reg, true);
1587 emit_int8(0x0F);
1588 emit_int8((unsigned char)0xB0);
1589 emit_operand(reg, adr);
1590 }
1591
1592 void Assembler::comisd(XMMRegister dst, Address src) {
1593 // NOTE: dbx seems to decode this as comiss even though the
1594 // 0x66 is there. Strangly ucomisd comes out correct
1595 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1596 InstructionMark im(this);
1597 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1598 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1599 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1600 emit_int8(0x2F);
1601 emit_operand(dst, src);
1602 }
1603
1604 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1605 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1606 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1607 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1608 emit_int8(0x2F);
1609 emit_int8((unsigned char)(0xC0 | encode));
1610 }
1611
1612 void Assembler::comiss(XMMRegister dst, Address src) {
1613 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1614 InstructionMark im(this);
1615 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1616 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1617 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1618 emit_int8(0x2F);
1619 emit_operand(dst, src);
1620 }
1621
1622 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1623 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1624 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1625 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1626 emit_int8(0x2F);
1627 emit_int8((unsigned char)(0xC0 | encode));
1628 }
1629
1630 void Assembler::cpuid() {
1631 emit_int8(0x0F);
1632 emit_int8((unsigned char)0xA2);
1633 }
1634
1635 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1636 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1637 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1638 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1639 //
1640 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1641 //
1642 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1643 //
1644 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1645 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1646 assert(VM_Version::supports_sse4_2(), "");
1647 int8_t w = 0x01;
1696 case 2:
1697 case 4:
1698 break;
1699 LP64_ONLY(case 8:)
1700 // This instruction is not valid in 32 bits
1701 p = REX_W;
1702 break;
1703 default:
1704 assert(0, "Unsupported value for a sizeInBytes argument");
1705 break;
1706 }
1707 LP64_ONLY(prefix(crc, adr, p);)
1708 emit_int8((int8_t)0x0F);
1709 emit_int8(0x38);
1710 emit_int8((int8_t)(0xF0 | w));
1711 emit_operand(crc, adr);
1712 }
1713
1714 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1715 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1716 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1717 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1718 emit_int8((unsigned char)0xE6);
1719 emit_int8((unsigned char)(0xC0 | encode));
1720 }
1721
1722 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1723 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1724 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1725 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1726 emit_int8(0x5B);
1727 emit_int8((unsigned char)(0xC0 | encode));
1728 }
1729
1730 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1731 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1732 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1733 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1734 emit_int8(0x5A);
1735 emit_int8((unsigned char)(0xC0 | encode));
1736 }
1737
1738 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1739 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1740 InstructionMark im(this);
1741 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1742 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1743 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1744 emit_int8(0x5A);
1745 emit_operand(dst, src);
1746 }
1747
1748 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1749 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1750 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1751 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1752 emit_int8(0x2A);
1753 emit_int8((unsigned char)(0xC0 | encode));
1754 }
1755
1756 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1757 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1758 InstructionMark im(this);
1759 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1760 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1761 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1762 emit_int8(0x2A);
1763 emit_operand(dst, src);
1764 }
1765
1766 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1767 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1768 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1769 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1770 emit_int8(0x2A);
1771 emit_int8((unsigned char)(0xC0 | encode));
1772 }
1773
1774 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1775 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1776 InstructionMark im(this);
1777 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1778 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1779 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1780 emit_int8(0x2A);
1781 emit_operand(dst, src);
1782 }
1783
1784 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1785 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1786 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1787 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1788 emit_int8(0x2A);
1789 emit_int8((unsigned char)(0xC0 | encode));
1790 }
1791
1792 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1793 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1794 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1795 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1796 emit_int8(0x5A);
1797 emit_int8((unsigned char)(0xC0 | encode));
1798 }
1799
1800 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1801 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1802 InstructionMark im(this);
1803 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1804 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1805 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1806 emit_int8(0x5A);
1807 emit_operand(dst, src);
1808 }
1809
1810
1811 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1812 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1813 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1814 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1815 emit_int8(0x2C);
1816 emit_int8((unsigned char)(0xC0 | encode));
1817 }
1818
1819 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1820 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1821 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1822 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1823 emit_int8(0x2C);
1824 emit_int8((unsigned char)(0xC0 | encode));
1825 }
1826
1827 void Assembler::decl(Address dst) {
1828 // Don't use it directly. Use MacroAssembler::decrement() instead.
1829 InstructionMark im(this);
1830 prefix(dst);
1831 emit_int8((unsigned char)0xFF);
1832 emit_operand(rcx, dst);
1833 }
1834
1835 void Assembler::divsd(XMMRegister dst, Address src) {
1836 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1837 InstructionMark im(this);
1838 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1839 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1840 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1841 emit_int8(0x5E);
1842 emit_operand(dst, src);
1843 }
1844
1845 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1846 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1847 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1848 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1849 emit_int8(0x5E);
1850 emit_int8((unsigned char)(0xC0 | encode));
1851 }
1852
1853 void Assembler::divss(XMMRegister dst, Address src) {
1854 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1855 InstructionMark im(this);
1856 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1857 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1858 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1859 emit_int8(0x5E);
1860 emit_operand(dst, src);
1861 }
1862
1863 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1864 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1865 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1866 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1867 emit_int8(0x5E);
1868 emit_int8((unsigned char)(0xC0 | encode));
1869 }
1870
1871 void Assembler::emms() {
1872 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1873 emit_int8(0x0F);
1874 emit_int8(0x77);
1875 }
1876
1877 void Assembler::hlt() {
1878 emit_int8((unsigned char)0xF4);
1879 }
1880
1881 void Assembler::idivl(Register src) {
1882 int encode = prefix_and_encode(src->encoding());
1883 emit_int8((unsigned char)0xF7);
1884 emit_int8((unsigned char)(0xF8 | encode));
1885 }
1886
1887 void Assembler::divl(Register src) { // Unsigned
1888 int encode = prefix_and_encode(src->encoding());
2094 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2095 emit_int8(0x0F);
2096 emit_int8((unsigned char)0xBD);
2097 emit_int8((unsigned char)(0xC0 | encode));
2098 }
2099
2100 // Emit mfence instruction
2101 void Assembler::mfence() {
2102 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2103 emit_int8(0x0F);
2104 emit_int8((unsigned char)0xAE);
2105 emit_int8((unsigned char)0xF0);
2106 }
2107
2108 void Assembler::mov(Register dst, Register src) {
2109 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2110 }
2111
2112 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2113 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2114 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2115 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2116 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2117 emit_int8(0x28);
2118 emit_int8((unsigned char)(0xC0 | encode));
2119 }
2120
2121 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2122 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2123 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2124 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2125 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2126 emit_int8(0x28);
2127 emit_int8((unsigned char)(0xC0 | encode));
2128 }
2129
2130 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2131 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2132 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2133 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2134 emit_int8(0x16);
2135 emit_int8((unsigned char)(0xC0 | encode));
2136 }
2137
2138 void Assembler::movb(Register dst, Address src) {
2139 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2140 InstructionMark im(this);
2141 prefix(src, dst, true);
2142 emit_int8((unsigned char)0x8A);
2143 emit_operand(dst, src);
2144 }
2145
2146 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2147 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2148 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_128bit;
2149 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2150 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2151 emit_int8(0x12);
2152 emit_int8(0xC0 | encode);
2153 }
2154
2155 void Assembler::kmovql(KRegister dst, KRegister src) {
2156 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2157 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2158 int encode = kreg_prefix_and_encode(dst, knoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2159 emit_int8((unsigned char)0x90);
2160 emit_int8((unsigned char)(0xC0 | encode));
2161 }
2162
2163 void Assembler::kmovql(KRegister dst, Address src) {
2164 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2165 InstructionMark im(this);
2166 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2167 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2168 emit_int8((unsigned char)0x90);
2169 emit_operand((Register)dst, src);
2170 }
2171
2172 void Assembler::kmovql(Address dst, KRegister src) {
2173 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2174 InstructionMark im(this);
2175 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2176 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2177 emit_int8((unsigned char)0x90);
2178 emit_operand((Register)src, dst);
2179 }
2180
2181 void Assembler::kmovql(KRegister dst, Register src) {
2182 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2183 VexSimdPrefix pre = !_legacy_mode_bw ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2184 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_bw, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2185 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, VEX_OPCODE_0F, &attributes);
2186 emit_int8((unsigned char)0x92);
2187 emit_int8((unsigned char)(0xC0 | encode));
2188 }
2189
2190 void Assembler::kmovdl(KRegister dst, Register src) {
2191 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2192 VexSimdPrefix pre = !_legacy_mode_bw ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2193 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2194 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, VEX_OPCODE_0F, &attributes);
2195 emit_int8((unsigned char)0x92);
2196 emit_int8((unsigned char)(0xC0 | encode));
2197 }
2198
2199 void Assembler::kmovwl(KRegister dst, Register src) {
2200 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2201 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2202 int encode = kreg_prefix_and_encode(dst, knoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2203 emit_int8((unsigned char)0x92);
2204 emit_int8((unsigned char)(0xC0 | encode));
2205 }
2206
2207 void Assembler::movb(Address dst, int imm8) {
2208 InstructionMark im(this);
2209 prefix(dst);
2210 emit_int8((unsigned char)0xC6);
2211 emit_operand(rax, dst, 1);
2212 emit_int8(imm8);
2213 }
2214
2215
2216 void Assembler::movb(Address dst, Register src) {
2217 assert(src->has_byte_register(), "must have byte register");
2218 InstructionMark im(this);
2219 prefix(dst, src, true);
2220 emit_int8((unsigned char)0x88);
2221 emit_operand(src, dst);
2222 }
2223
2224 void Assembler::movdl(XMMRegister dst, Register src) {
2225 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2226 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2227 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2228 emit_int8(0x6E);
2229 emit_int8((unsigned char)(0xC0 | encode));
2230 }
2231
2232 void Assembler::movdl(Register dst, XMMRegister src) {
2233 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2234 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2235 // swap src/dst to get correct prefix
2236 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2237 emit_int8(0x7E);
2238 emit_int8((unsigned char)(0xC0 | encode));
2239 }
2240
2241 void Assembler::movdl(XMMRegister dst, Address src) {
2242 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2243 InstructionMark im(this);
2244 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2245 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2246 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2247 emit_int8(0x6E);
2248 emit_operand(dst, src);
2249 }
2250
2251 void Assembler::movdl(Address dst, XMMRegister src) {
2252 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2253 InstructionMark im(this);
2254 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2255 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2256 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2257 emit_int8(0x7E);
2258 emit_operand(src, dst);
2259 }
2260
2261 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2262 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2263 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2264 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2265 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2266 emit_int8(0x6F);
2267 emit_int8((unsigned char)(0xC0 | encode));
2268 }
2269
2270 void Assembler::movdqa(XMMRegister dst, Address src) {
2271 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2272 InstructionMark im(this);
2273 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2274 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2275 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2276 emit_int8(0x6F);
2277 emit_operand(dst, src);
2278 }
2279
2280 void Assembler::movdqu(XMMRegister dst, Address src) {
2281 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2282 InstructionMark im(this);
2283 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2284 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2285 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2286 emit_int8(0x6F);
2287 emit_operand(dst, src);
2288 }
2289
2290 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2291 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2292 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2293 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2294 emit_int8(0x6F);
2295 emit_int8((unsigned char)(0xC0 | encode));
2296 }
2297
2298 void Assembler::movdqu(Address dst, XMMRegister src) {
2299 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2300 InstructionMark im(this);
2301 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2302 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2303 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2304 emit_int8(0x7F);
2305 emit_operand(src, dst);
2306 }
2307
2308 // Move Unaligned 256bit Vector
2309 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2310 assert(UseAVX > 0, "");
2311 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2312 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2313 emit_int8(0x6F);
2314 emit_int8((unsigned char)(0xC0 | encode));
2315 }
2316
2317 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2318 assert(UseAVX > 0, "");
2319 InstructionMark im(this);
2320 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2321 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2322 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2323 emit_int8(0x6F);
2324 emit_operand(dst, src);
2325 }
2326
2327 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2328 assert(UseAVX > 0, "");
2329 InstructionMark im(this);
2330 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2331 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2332 // swap src<->dst for encoding
2333 assert(src != xnoreg, "sanity");
2334 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2335 emit_int8(0x7F);
2336 emit_operand(src, dst);
2337 }
2338
2339 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2340 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2341 assert(VM_Version::supports_evex(), "");
2342 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2343 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2344 emit_int8(0x6F);
2345 emit_int8((unsigned char)(0xC0 | encode));
2346 }
2347
2348 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2349 assert(VM_Version::supports_evex(), "");
2350 InstructionMark im(this);
2351 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2352 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2353 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2354 emit_int8(0x6F);
2355 emit_operand(dst, src);
2356 }
2357
2358 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2359 assert(VM_Version::supports_evex(), "");
2360 assert(src != xnoreg, "sanity");
2361 InstructionMark im(this);
2362 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2363 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2364 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2365 emit_int8(0x7F);
2366 emit_operand(src, dst);
2367 }
2368
2369 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2370 assert(VM_Version::supports_evex(), "");
2371 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2372 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2373 emit_int8(0x6F);
2374 emit_int8((unsigned char)(0xC0 | encode));
2375 }
2376
2377 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2378 assert(VM_Version::supports_evex(), "");
2379 InstructionMark im(this);
2380 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2381 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2382 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2383 emit_int8(0x6F);
2384 emit_operand(dst, src);
2385 }
2386
2387 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2388 assert(VM_Version::supports_evex(), "");
2389 assert(src != xnoreg, "sanity");
2390 InstructionMark im(this);
2391 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2392 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2393 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2394 emit_int8(0x7F);
2395 emit_operand(src, dst);
2396 }
2397
2398 // Uses zero extension on 64bit
2399
2400 void Assembler::movl(Register dst, int32_t imm32) {
2401 int encode = prefix_and_encode(dst->encoding());
2402 emit_int8((unsigned char)(0xB8 | encode));
2403 emit_int32(imm32);
2404 }
2405
2406 void Assembler::movl(Register dst, Register src) {
2407 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2408 emit_int8((unsigned char)0x8B);
2409 emit_int8((unsigned char)(0xC0 | encode));
2410 }
2411
2412 void Assembler::movl(Register dst, Address src) {
2413 InstructionMark im(this);
2419 void Assembler::movl(Address dst, int32_t imm32) {
2420 InstructionMark im(this);
2421 prefix(dst);
2422 emit_int8((unsigned char)0xC7);
2423 emit_operand(rax, dst, 4);
2424 emit_int32(imm32);
2425 }
2426
2427 void Assembler::movl(Address dst, Register src) {
2428 InstructionMark im(this);
2429 prefix(dst, src);
2430 emit_int8((unsigned char)0x89);
2431 emit_operand(src, dst);
2432 }
2433
2434 // New cpus require to use movsd and movss to avoid partial register stall
2435 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2436 // The selection is done in MacroAssembler::movdbl() and movflt().
2437 void Assembler::movlpd(XMMRegister dst, Address src) {
2438 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2439 InstructionMark im(this);
2440 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2441 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2442 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2443 emit_int8(0x12);
2444 emit_operand(dst, src);
2445 }
2446
2447 void Assembler::movq( MMXRegister dst, Address src ) {
2448 assert( VM_Version::supports_mmx(), "" );
2449 emit_int8(0x0F);
2450 emit_int8(0x6F);
2451 emit_operand(dst, src);
2452 }
2453
2454 void Assembler::movq( Address dst, MMXRegister src ) {
2455 assert( VM_Version::supports_mmx(), "" );
2456 emit_int8(0x0F);
2457 emit_int8(0x7F);
2458 // workaround gcc (3.2.1-7a) bug
2459 // In that version of gcc with only an emit_operand(MMX, Address)
2460 // gcc will tail jump and try and reverse the parameters completely
2461 // obliterating dst in the process. By having a version available
2462 // that doesn't need to swap the args at the tail jump the bug is
2463 // avoided.
2464 emit_operand(dst, src);
2465 }
2466
2467 void Assembler::movq(XMMRegister dst, Address src) {
2468 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2469 InstructionMark im(this);
2470 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2471 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2472 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2473 emit_int8(0x7E);
2474 emit_operand(dst, src);
2475 }
2476
2477 void Assembler::movq(Address dst, XMMRegister src) {
2478 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2479 InstructionMark im(this);
2480 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2481 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2482 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2483 emit_int8((unsigned char)0xD6);
2484 emit_operand(src, dst);
2485 }
2486
2487 void Assembler::movsbl(Register dst, Address src) { // movsxb
2488 InstructionMark im(this);
2489 prefix(src, dst);
2490 emit_int8(0x0F);
2491 emit_int8((unsigned char)0xBE);
2492 emit_operand(dst, src);
2493 }
2494
2495 void Assembler::movsbl(Register dst, Register src) { // movsxb
2496 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2497 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2498 emit_int8(0x0F);
2499 emit_int8((unsigned char)0xBE);
2500 emit_int8((unsigned char)(0xC0 | encode));
2501 }
2502
2503 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2504 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2505 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2506 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2507 emit_int8(0x10);
2508 emit_int8((unsigned char)(0xC0 | encode));
2509 }
2510
2511 void Assembler::movsd(XMMRegister dst, Address src) {
2512 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2513 InstructionMark im(this);
2514 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2515 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2516 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2517 emit_int8(0x10);
2518 emit_operand(dst, src);
2519 }
2520
2521 void Assembler::movsd(Address dst, XMMRegister src) {
2522 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2523 InstructionMark im(this);
2524 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2525 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2526 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2527 emit_int8(0x11);
2528 emit_operand(src, dst);
2529 }
2530
2531 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2532 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2533 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2534 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2535 emit_int8(0x10);
2536 emit_int8((unsigned char)(0xC0 | encode));
2537 }
2538
2539 void Assembler::movss(XMMRegister dst, Address src) {
2540 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2541 InstructionMark im(this);
2542 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2543 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2544 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2545 emit_int8(0x10);
2546 emit_operand(dst, src);
2547 }
2548
2549 void Assembler::movss(Address dst, XMMRegister src) {
2550 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2551 InstructionMark im(this);
2552 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2553 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2554 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2555 emit_int8(0x11);
2556 emit_operand(src, dst);
2557 }
2558
2559 void Assembler::movswl(Register dst, Address src) { // movsxw
2560 InstructionMark im(this);
2561 prefix(src, dst);
2562 emit_int8(0x0F);
2563 emit_int8((unsigned char)0xBF);
2564 emit_operand(dst, src);
2565 }
2566
2567 void Assembler::movswl(Register dst, Register src) { // movsxw
2568 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2569 emit_int8(0x0F);
2570 emit_int8((unsigned char)0xBF);
2571 emit_int8((unsigned char)(0xC0 | encode));
2572 }
2573
2574 void Assembler::movw(Address dst, int imm16) {
2626 emit_int8(0x0F);
2627 emit_int8((unsigned char)0xB7);
2628 emit_int8(0xC0 | encode);
2629 }
2630
2631 void Assembler::mull(Address src) {
2632 InstructionMark im(this);
2633 prefix(src);
2634 emit_int8((unsigned char)0xF7);
2635 emit_operand(rsp, src);
2636 }
2637
2638 void Assembler::mull(Register src) {
2639 int encode = prefix_and_encode(src->encoding());
2640 emit_int8((unsigned char)0xF7);
2641 emit_int8((unsigned char)(0xE0 | encode));
2642 }
2643
2644 void Assembler::mulsd(XMMRegister dst, Address src) {
2645 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2646 InstructionMark im(this);
2647 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2648 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2649 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2650 emit_int8(0x59);
2651 emit_operand(dst, src);
2652 }
2653
2654 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2655 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2656 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2657 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2658 emit_int8(0x59);
2659 emit_int8((unsigned char)(0xC0 | encode));
2660 }
2661
2662 void Assembler::mulss(XMMRegister dst, Address src) {
2663 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2664 InstructionMark im(this);
2665 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2666 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2667 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2668 emit_int8(0x59);
2669 emit_operand(dst, src);
2670 }
2671
2672 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2673 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2674 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2675 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2676 emit_int8(0x59);
2677 emit_int8((unsigned char)(0xC0 | encode));
2678 }
2679
2680 void Assembler::negl(Register dst) {
2681 int encode = prefix_and_encode(dst->encoding());
2682 emit_int8((unsigned char)0xF7);
2683 emit_int8((unsigned char)(0xD8 | encode));
2684 }
2685
2686 void Assembler::nop(int i) {
2687 #ifdef ASSERT
2688 assert(i > 0, " ");
2689 // The fancy nops aren't currently recognized by debuggers making it a
2690 // pain to disassemble code while debugging. If asserts are on clearly
2691 // speed is not an issue so simply use the single byte traditional nop
2692 // to do alignment.
2693
2694 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2695 return;
2696
2697 #endif // ASSERT
2958 prefix(src, dst);
2959 emit_int8(0x0B);
2960 emit_operand(dst, src);
2961 }
2962
2963 void Assembler::orl(Register dst, Register src) {
2964 (void) prefix_and_encode(dst->encoding(), src->encoding());
2965 emit_arith(0x0B, 0xC0, dst, src);
2966 }
2967
2968 void Assembler::orl(Address dst, Register src) {
2969 InstructionMark im(this);
2970 prefix(dst, src);
2971 emit_int8(0x09);
2972 emit_operand(src, dst);
2973 }
2974
2975 void Assembler::packuswb(XMMRegister dst, Address src) {
2976 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2977 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2978 InstructionMark im(this);
2979 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2980 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
2981 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2982 emit_int8(0x67);
2983 emit_operand(dst, src);
2984 }
2985
2986 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2987 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2988 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2989 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2990 emit_int8(0x67);
2991 emit_int8((unsigned char)(0xC0 | encode));
2992 }
2993
2994 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2995 assert(UseAVX > 0, "some form of AVX must be enabled");
2996 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2997 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
2998 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2999 emit_int8(0x67);
3000 emit_int8((unsigned char)(0xC0 | encode));
3001 }
3002
3003 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3004 assert(VM_Version::supports_avx2(), "");
3005 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3006 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3007 emit_int8(0x00);
3008 emit_int8(0xC0 | encode);
3009 emit_int8(imm8);
3010 }
3011
3012 void Assembler::pause() {
3013 emit_int8((unsigned char)0xF3);
3014 emit_int8((unsigned char)0x90);
3015 }
3016
3017 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3018 assert(VM_Version::supports_sse4_2(), "");
3019 InstructionMark im(this);
3020 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3021 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3022 emit_int8(0x61);
3023 emit_operand(dst, src);
3024 emit_int8(imm8);
3025 }
3026
3027 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3028 assert(VM_Version::supports_sse4_2(), "");
3029 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3030 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3031 emit_int8(0x61);
3032 emit_int8((unsigned char)(0xC0 | encode));
3033 emit_int8(imm8);
3034 }
3035
3036 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3037 assert(VM_Version::supports_sse4_1(), "");
3038 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3039 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3040 emit_int8(0x16);
3041 emit_int8((unsigned char)(0xC0 | encode));
3042 emit_int8(imm8);
3043 }
3044
3045 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3046 assert(VM_Version::supports_sse4_1(), "");
3047 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3048 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3049 emit_int8(0x16);
3050 emit_int8((unsigned char)(0xC0 | encode));
3051 emit_int8(imm8);
3052 }
3053
3054 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3055 assert(VM_Version::supports_sse2(), "");
3056 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3057 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3058 emit_int8((unsigned char)0xC5);
3059 emit_int8((unsigned char)(0xC0 | encode));
3060 emit_int8(imm8);
3061 }
3062
3063 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3064 assert(VM_Version::supports_sse4_1(), "");
3065 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3066 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3067 emit_int8(0x22);
3068 emit_int8((unsigned char)(0xC0 | encode));
3069 emit_int8(imm8);
3070 }
3071
3072 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3073 assert(VM_Version::supports_sse4_1(), "");
3074 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3075 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3076 emit_int8(0x22);
3077 emit_int8((unsigned char)(0xC0 | encode));
3078 emit_int8(imm8);
3079 }
3080
3081 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3082 assert(VM_Version::supports_sse2(), "");
3083 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3084 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3085 emit_int8((unsigned char)0xC4);
3086 emit_int8((unsigned char)(0xC0 | encode));
3087 emit_int8(imm8);
3088 }
3089
3090 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3091 assert(VM_Version::supports_sse4_1(), "");
3092 InstructionMark im(this);
3093 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3094 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3095 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3096 emit_int8(0x30);
3097 emit_operand(dst, src);
3098 }
3099
3100 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3101 assert(VM_Version::supports_sse4_1(), "");
3102 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3103 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3104 emit_int8(0x30);
3105 emit_int8((unsigned char)(0xC0 | encode));
3106 }
3107
3108 // generic
3109 void Assembler::pop(Register dst) {
3110 int encode = prefix_and_encode(dst->encoding());
3111 emit_int8(0x58 | encode);
3112 }
3113
3114 void Assembler::popcntl(Register dst, Address src) {
3115 assert(VM_Version::supports_popcnt(), "must support");
3116 InstructionMark im(this);
3117 emit_int8((unsigned char)0xF3);
3118 prefix(src, dst);
3119 emit_int8(0x0F);
3120 emit_int8((unsigned char)0xB8);
3121 emit_operand(dst, src);
3122 }
3123
3186 InstructionMark im(this);
3187 prefetch_prefix(src);
3188 emit_int8(0x18);
3189 emit_operand(rbx, src); // 3, src
3190 }
3191
3192 void Assembler::prefetchw(Address src) {
3193 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3194 InstructionMark im(this);
3195 prefetch_prefix(src);
3196 emit_int8(0x0D);
3197 emit_operand(rcx, src); // 1, src
3198 }
3199
3200 void Assembler::prefix(Prefix p) {
3201 emit_int8(p);
3202 }
3203
3204 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3205 assert(VM_Version::supports_ssse3(), "");
3206 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3207 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3208 emit_int8(0x00);
3209 emit_int8((unsigned char)(0xC0 | encode));
3210 }
3211
3212 void Assembler::pshufb(XMMRegister dst, Address src) {
3213 assert(VM_Version::supports_ssse3(), "");
3214 InstructionMark im(this);
3215 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3216 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3217 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3218 emit_int8(0x00);
3219 emit_operand(dst, src);
3220 }
3221
3222 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
3223 assert(isByte(mode), "invalid value");
3224 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3225 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_128bit;
3226 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3227 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3228 emit_int8(0x70);
3229 emit_int8((unsigned char)(0xC0 | encode));
3230 emit_int8(mode & 0xFF);
3231 }
3232
3233 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
3234 assert(isByte(mode), "invalid value");
3235 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3236 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3237 InstructionMark im(this);
3238 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3239 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3240 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3241 emit_int8(0x70);
3242 emit_operand(dst, src);
3243 emit_int8(mode & 0xFF);
3244 }
3245
3246 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3247 assert(isByte(mode), "invalid value");
3248 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3249 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3250 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3251 emit_int8(0x70);
3252 emit_int8((unsigned char)(0xC0 | encode));
3253 emit_int8(mode & 0xFF);
3254 }
3255
3256 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3257 assert(isByte(mode), "invalid value");
3258 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3259 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3260 InstructionMark im(this);
3261 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3262 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3263 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3264 emit_int8(0x70);
3265 emit_operand(dst, src);
3266 emit_int8(mode & 0xFF);
3267 }
3268
3269 void Assembler::psrldq(XMMRegister dst, int shift) {
3270 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3271 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3272 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3273 // XMM3 is for /3 encoding: 66 0F 73 /3 ib
3274 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3275 emit_int8(0x73);
3276 emit_int8((unsigned char)(0xC0 | encode));
3277 emit_int8(shift);
3278 }
3279
3280 void Assembler::pslldq(XMMRegister dst, int shift) {
3281 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3282 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3283 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3284 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
3285 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3286 emit_int8(0x73);
3287 emit_int8((unsigned char)(0xC0 | encode));
3288 emit_int8(shift);
3289 }
3290
3291 void Assembler::ptest(XMMRegister dst, Address src) {
3292 assert(VM_Version::supports_sse4_1(), "");
3293 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3294 InstructionMark im(this);
3295 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3296 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3297 emit_int8(0x17);
3298 emit_operand(dst, src);
3299 }
3300
3301 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3302 assert(VM_Version::supports_sse4_1(), "");
3303 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3304 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3305 emit_int8(0x17);
3306 emit_int8((unsigned char)(0xC0 | encode));
3307 }
3308
3309 void Assembler::vptest(XMMRegister dst, Address src) {
3310 assert(VM_Version::supports_avx(), "");
3311 InstructionMark im(this);
3312 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3313 assert(dst != xnoreg, "sanity");
3314 // swap src<->dst for encoding
3315 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3316 emit_int8(0x17);
3317 emit_operand(dst, src);
3318 }
3319
3320 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
3321 assert(VM_Version::supports_avx(), "");
3322 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3323 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3324 emit_int8(0x17);
3325 emit_int8((unsigned char)(0xC0 | encode));
3326 }
3327
3328 void Assembler::punpcklbw(XMMRegister dst, Address src) {
3329 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3330 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3331 InstructionMark im(this);
3332 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3333 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3334 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3335 emit_int8(0x60);
3336 emit_operand(dst, src);
3337 }
3338
3339 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3340 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3341 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3342 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3343 emit_int8(0x60);
3344 emit_int8((unsigned char)(0xC0 | encode));
3345 }
3346
3347 void Assembler::punpckldq(XMMRegister dst, Address src) {
3348 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3349 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3350 InstructionMark im(this);
3351 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3352 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3353 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3354 emit_int8(0x62);
3355 emit_operand(dst, src);
3356 }
3357
3358 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
3359 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3360 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3361 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3362 emit_int8(0x62);
3363 emit_int8((unsigned char)(0xC0 | encode));
3364 }
3365
3366 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
3367 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3368 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3369 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3370 emit_int8(0x6C);
3371 emit_int8((unsigned char)(0xC0 | encode));
3372 }
3373
3374 void Assembler::push(int32_t imm32) {
3375 // in 64bits we push 64bits onto the stack but only
3376 // take a 32bit immediate
3377 emit_int8(0x68);
3378 emit_int32(imm32);
3379 }
3380
3381 void Assembler::push(Register src) {
3382 int encode = prefix_and_encode(src->encoding());
3383
3384 emit_int8(0x50 | encode);
3385 }
3386
3387 void Assembler::pushf() {
3388 emit_int8((unsigned char)0x9C);
3389 }
3390
3391 #ifndef _LP64 // no 32bit push/pop on amd64
3396 emit_int8((unsigned char)0xFF);
3397 emit_operand(rsi, src);
3398 }
3399 #endif
3400
3401 void Assembler::rcll(Register dst, int imm8) {
3402 assert(isShiftCount(imm8), "illegal shift count");
3403 int encode = prefix_and_encode(dst->encoding());
3404 if (imm8 == 1) {
3405 emit_int8((unsigned char)0xD1);
3406 emit_int8((unsigned char)(0xD0 | encode));
3407 } else {
3408 emit_int8((unsigned char)0xC1);
3409 emit_int8((unsigned char)0xD0 | encode);
3410 emit_int8(imm8);
3411 }
3412 }
3413
3414 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
3415 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3416 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3417 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3418 emit_int8(0x53);
3419 emit_int8((unsigned char)(0xC0 | encode));
3420 }
3421
3422 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
3423 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3424 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3425 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3426 emit_int8(0x53);
3427 emit_int8((unsigned char)(0xC0 | encode));
3428 }
3429
3430 void Assembler::rdtsc() {
3431 emit_int8((unsigned char)0x0F);
3432 emit_int8((unsigned char)0x31);
3433 }
3434
3435 // copies data from [esi] to [edi] using rcx pointer sized words
3436 // generic
3437 void Assembler::rep_mov() {
3438 emit_int8((unsigned char)0xF3);
3439 // MOVSQ
3440 LP64_ONLY(prefix(REX_W));
3441 emit_int8((unsigned char)0xA5);
3442 }
3443
3444 // sets rcx bytes with rax, value at [edi]
3445 void Assembler::rep_stosb() {
3446 emit_int8((unsigned char)0xF3); // REP
3447 LP64_ONLY(prefix(REX_W));
3566 assert(isShiftCount(imm8), "illegal shift count");
3567 int encode = prefix_and_encode(dst->encoding());
3568 emit_int8((unsigned char)0xC1);
3569 emit_int8((unsigned char)(0xE8 | encode));
3570 emit_int8(imm8);
3571 }
3572
3573 void Assembler::shrl(Register dst) {
3574 int encode = prefix_and_encode(dst->encoding());
3575 emit_int8((unsigned char)0xD3);
3576 emit_int8((unsigned char)(0xE8 | encode));
3577 }
3578
3579 // copies a single word from [esi] to [edi]
3580 void Assembler::smovl() {
3581 emit_int8((unsigned char)0xA5);
3582 }
3583
3584 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
3585 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3586 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3587 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3588 emit_int8(0x51);
3589 emit_int8((unsigned char)(0xC0 | encode));
3590 }
3591
3592 void Assembler::sqrtsd(XMMRegister dst, Address src) {
3593 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3594 InstructionMark im(this);
3595 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3596 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3597 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3598 emit_int8(0x51);
3599 emit_operand(dst, src);
3600 }
3601
3602 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
3603 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3604 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3605 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3606 emit_int8(0x51);
3607 emit_int8((unsigned char)(0xC0 | encode));
3608 }
3609
3610 void Assembler::std() {
3611 emit_int8((unsigned char)0xFD);
3612 }
3613
3614 void Assembler::sqrtss(XMMRegister dst, Address src) {
3615 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3616 InstructionMark im(this);
3617 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3618 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3619 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3620 emit_int8(0x51);
3621 emit_operand(dst, src);
3622 }
3623
3624 void Assembler::stmxcsr( Address dst) {
3625 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3626 InstructionMark im(this);
3627 prefix(dst);
3628 emit_int8(0x0F);
3629 emit_int8((unsigned char)0xAE);
3630 emit_operand(as_Register(3), dst);
3631 }
3632
3633 void Assembler::subl(Address dst, int32_t imm32) {
3634 InstructionMark im(this);
3635 prefix(dst);
3636 emit_arith_operand(0x81, rbp, dst, imm32);
3637 }
3638
3639 void Assembler::subl(Address dst, Register src) {
3640 InstructionMark im(this);
3641 prefix(dst, src);
3651 // Force generation of a 4 byte immediate value even if it fits into 8bit
3652 void Assembler::subl_imm32(Register dst, int32_t imm32) {
3653 prefix(dst);
3654 emit_arith_imm32(0x81, 0xE8, dst, imm32);
3655 }
3656
3657 void Assembler::subl(Register dst, Address src) {
3658 InstructionMark im(this);
3659 prefix(src, dst);
3660 emit_int8(0x2B);
3661 emit_operand(dst, src);
3662 }
3663
3664 void Assembler::subl(Register dst, Register src) {
3665 (void) prefix_and_encode(dst->encoding(), src->encoding());
3666 emit_arith(0x2B, 0xC0, dst, src);
3667 }
3668
3669 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
3670 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3671 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3672 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3673 emit_int8(0x5C);
3674 emit_int8((unsigned char)(0xC0 | encode));
3675 }
3676
3677 void Assembler::subsd(XMMRegister dst, Address src) {
3678 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3679 InstructionMark im(this);
3680 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3681 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3682 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3683 emit_int8(0x5C);
3684 emit_operand(dst, src);
3685 }
3686
3687 void Assembler::subss(XMMRegister dst, XMMRegister src) {
3688 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3689 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3690 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3691 emit_int8(0x5C);
3692 emit_int8((unsigned char)(0xC0 | encode));
3693 }
3694
3695 void Assembler::subss(XMMRegister dst, Address src) {
3696 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3697 InstructionMark im(this);
3698 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3699 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3700 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3701 emit_int8(0x5C);
3702 emit_operand(dst, src);
3703 }
3704
3705 void Assembler::testb(Register dst, int imm8) {
3706 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
3707 (void) prefix_and_encode(dst->encoding(), true);
3708 emit_arith_b(0xF6, 0xC0, dst, imm8);
3709 }
3710
3711 void Assembler::testl(Register dst, int32_t imm32) {
3712 // not using emit_arith because test
3713 // doesn't support sign-extension of
3714 // 8bit operands
3715 int encode = dst->encoding();
3716 if (encode == 0) {
3717 emit_int8((unsigned char)0xA9);
3718 } else {
3719 encode = prefix_and_encode(encode);
3720 emit_int8((unsigned char)0xF7);
3721 emit_int8((unsigned char)(0xC0 | encode));
3722 }
3738 void Assembler::tzcntl(Register dst, Register src) {
3739 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
3740 emit_int8((unsigned char)0xF3);
3741 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3742 emit_int8(0x0F);
3743 emit_int8((unsigned char)0xBC);
3744 emit_int8((unsigned char)0xC0 | encode);
3745 }
3746
3747 void Assembler::tzcntq(Register dst, Register src) {
3748 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
3749 emit_int8((unsigned char)0xF3);
3750 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3751 emit_int8(0x0F);
3752 emit_int8((unsigned char)0xBC);
3753 emit_int8((unsigned char)(0xC0 | encode));
3754 }
3755
3756 void Assembler::ucomisd(XMMRegister dst, Address src) {
3757 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3758 InstructionMark im(this);
3759 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3760 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3761 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3762 emit_int8(0x2E);
3763 emit_operand(dst, src);
3764 }
3765
3766 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
3767 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3768 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3769 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3770 emit_int8(0x2E);
3771 emit_int8((unsigned char)(0xC0 | encode));
3772 }
3773
3774 void Assembler::ucomiss(XMMRegister dst, Address src) {
3775 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3776 InstructionMark im(this);
3777 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3778 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3779 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3780 emit_int8(0x2E);
3781 emit_operand(dst, src);
3782 }
3783
3784 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
3785 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3786 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3787 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3788 emit_int8(0x2E);
3789 emit_int8((unsigned char)(0xC0 | encode));
3790 }
3791
3792 void Assembler::xabort(int8_t imm8) {
3793 emit_int8((unsigned char)0xC6);
3794 emit_int8((unsigned char)0xF8);
3795 emit_int8((unsigned char)(imm8 & 0xFF));
3796 }
3797
3798 void Assembler::xaddl(Address dst, Register src) {
3799 InstructionMark im(this);
3800 prefix(dst, src);
3801 emit_int8(0x0F);
3802 emit_int8((unsigned char)0xC1);
3803 emit_operand(src, dst);
3804 }
3805
3806 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
3807 InstructionMark im(this);
3808 relocate(rtype);
3809 if (abort.is_bound()) {
3851 emit_arith(0x81, 0xF0, dst, imm32);
3852 }
3853
3854 void Assembler::xorl(Register dst, Address src) {
3855 InstructionMark im(this);
3856 prefix(src, dst);
3857 emit_int8(0x33);
3858 emit_operand(dst, src);
3859 }
3860
3861 void Assembler::xorl(Register dst, Register src) {
3862 (void) prefix_and_encode(dst->encoding(), src->encoding());
3863 emit_arith(0x33, 0xC0, dst, src);
3864 }
3865
3866
3867 // AVX 3-operands scalar float-point arithmetic instructions
3868
3869 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
3870 assert(VM_Version::supports_avx(), "");
3871 InstructionMark im(this);
3872 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3873 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3874 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3875 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3876 emit_int8(0x58);
3877 emit_operand(dst, src);
3878 }
3879
3880 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3881 assert(VM_Version::supports_avx(), "");
3882 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3883 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3884 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3885 emit_int8(0x58);
3886 emit_int8((unsigned char)(0xC0 | encode));
3887 }
3888
3889 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
3890 assert(VM_Version::supports_avx(), "");
3891 InstructionMark im(this);
3892 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3893 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3894 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3895 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3896 emit_int8(0x58);
3897 emit_operand(dst, src);
3898 }
3899
3900 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3901 assert(VM_Version::supports_avx(), "");
3902 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3903 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3904 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3905 emit_int8(0x58);
3906 emit_int8((unsigned char)(0xC0 | encode));
3907 }
3908
3909 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
3910 assert(VM_Version::supports_avx(), "");
3911 InstructionMark im(this);
3912 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3913 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3914 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3915 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3916 emit_int8(0x5E);
3917 emit_operand(dst, src);
3918 }
3919
3920 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3921 assert(VM_Version::supports_avx(), "");
3922 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3923 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3924 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3925 emit_int8(0x5E);
3926 emit_int8((unsigned char)(0xC0 | encode));
3927 }
3928
3929 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
3930 assert(VM_Version::supports_avx(), "");
3931 InstructionMark im(this);
3932 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3933 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3934 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3935 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3936 emit_int8(0x5E);
3937 emit_operand(dst, src);
3938 }
3939
3940 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3941 assert(VM_Version::supports_avx(), "");
3942 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3943 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3944 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3945 emit_int8(0x5E);
3946 emit_int8((unsigned char)(0xC0 | encode));
3947 }
3948
3949 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
3950 assert(VM_Version::supports_avx(), "");
3951 InstructionMark im(this);
3952 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3953 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3954 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3955 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3956 emit_int8(0x59);
3957 emit_operand(dst, src);
3958 }
3959
3960 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3961 assert(VM_Version::supports_avx(), "");
3962 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3963 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3964 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3965 emit_int8(0x59);
3966 emit_int8((unsigned char)(0xC0 | encode));
3967 }
3968
3969 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
3970 assert(VM_Version::supports_avx(), "");
3971 InstructionMark im(this);
3972 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3973 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3974 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3975 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3976 emit_int8(0x59);
3977 emit_operand(dst, src);
3978 }
3979
3980 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3981 assert(VM_Version::supports_avx(), "");
3982 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3983 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3984 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3985 emit_int8(0x59);
3986 emit_int8((unsigned char)(0xC0 | encode));
3987 }
3988
3989 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
3990 assert(VM_Version::supports_avx(), "");
3991 InstructionMark im(this);
3992 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3993 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3994 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3995 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3996 emit_int8(0x5C);
3997 emit_operand(dst, src);
3998 }
3999
4000 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4001 assert(VM_Version::supports_avx(), "");
4002 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4003 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4004 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4005 emit_int8(0x5C);
4006 emit_int8((unsigned char)(0xC0 | encode));
4007 }
4008
4009 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
4010 assert(VM_Version::supports_avx(), "");
4011 InstructionMark im(this);
4012 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4013 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4014 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4015 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4016 emit_int8(0x5C);
4017 emit_operand(dst, src);
4018 }
4019
4020 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4021 assert(VM_Version::supports_avx(), "");
4022 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4023 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4024 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4025 emit_int8(0x5C);
4026 emit_int8((unsigned char)(0xC0 | encode));
4027 }
4028
4029 //====================VECTOR ARITHMETIC=====================================
4030
4031 // Float-point vector arithmetic
4032
4033 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4034 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4035 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4036 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4037 emit_int8(0x58);
4038 emit_int8((unsigned char)(0xC0 | encode));
4039 }
4040
4041 void Assembler::addps(XMMRegister dst, XMMRegister src) {
4042 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4043 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4044 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4045 emit_int8(0x58);
4046 emit_int8((unsigned char)(0xC0 | encode));
4047 }
4048
4049 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4050 assert(VM_Version::supports_avx(), "");
4051 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4052 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4053 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4054 emit_int8(0x58);
4055 emit_int8((unsigned char)(0xC0 | encode));
4056 }
4057
4058 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4059 assert(VM_Version::supports_avx(), "");
4060 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4061 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4062 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4063 emit_int8(0x58);
4064 emit_int8((unsigned char)(0xC0 | encode));
4065 }
4066
4067 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4068 assert(VM_Version::supports_avx(), "");
4069 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4070 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4071 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4072 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4073 emit_int8(0x58);
4074 emit_operand(dst, src);
4075 }
4076
4077 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4078 assert(VM_Version::supports_avx(), "");
4079 InstructionMark im(this);
4080 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4081 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4082 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4083 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4084 emit_int8(0x58);
4085 emit_operand(dst, src);
4086 }
4087
4088 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
4089 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4090 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4091 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4092 emit_int8(0x5C);
4093 emit_int8((unsigned char)(0xC0 | encode));
4094 }
4095
4096 void Assembler::subps(XMMRegister dst, XMMRegister src) {
4097 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4098 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4099 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4100 emit_int8(0x5C);
4101 emit_int8((unsigned char)(0xC0 | encode));
4102 }
4103
4104 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4105 assert(VM_Version::supports_avx(), "");
4106 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4107 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4108 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4109 emit_int8(0x5C);
4110 emit_int8((unsigned char)(0xC0 | encode));
4111 }
4112
4113 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4114 assert(VM_Version::supports_avx(), "");
4115 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4116 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4117 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4118 emit_int8(0x5C);
4119 emit_int8((unsigned char)(0xC0 | encode));
4120 }
4121
4122 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4123 assert(VM_Version::supports_avx(), "");
4124 InstructionMark im(this);
4125 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4126 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4127 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4128 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4129 emit_int8(0x5C);
4130 emit_operand(dst, src);
4131 }
4132
4133 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4134 assert(VM_Version::supports_avx(), "");
4135 InstructionMark im(this);
4136 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4137 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4138 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4139 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4140 emit_int8(0x5C);
4141 emit_operand(dst, src);
4142 }
4143
4144 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
4145 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4146 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4147 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4148 emit_int8(0x59);
4149 emit_int8((unsigned char)(0xC0 | encode));
4150 }
4151
4152 void Assembler::mulpd(XMMRegister dst, Address src) {
4153 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4154 InstructionMark im(this);
4155 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4156 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4157 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4158 emit_int8(0x59);
4159 emit_operand(dst, src);
4160 }
4161
4162 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
4163 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4164 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4165 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4166 emit_int8(0x59);
4167 emit_int8((unsigned char)(0xC0 | encode));
4168 }
4169
4170 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4171 assert(VM_Version::supports_avx(), "");
4172 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4173 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4174 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4175 emit_int8(0x59);
4176 emit_int8((unsigned char)(0xC0 | encode));
4177 }
4178
4179 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4180 assert(VM_Version::supports_avx(), "");
4181 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4182 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4183 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4184 emit_int8(0x59);
4185 emit_int8((unsigned char)(0xC0 | encode));
4186 }
4187
4188 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4189 assert(VM_Version::supports_avx(), "");
4190 InstructionMark im(this);
4191 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4192 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4193 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4194 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4195 emit_int8(0x59);
4196 emit_operand(dst, src);
4197 }
4198
4199 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4200 assert(VM_Version::supports_avx(), "");
4201 InstructionMark im(this);
4202 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4203 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4204 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4205 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4206 emit_int8(0x59);
4207 emit_operand(dst, src);
4208 }
4209
4210 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
4211 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4212 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4213 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4214 emit_int8(0x5E);
4215 emit_int8((unsigned char)(0xC0 | encode));
4216 }
4217
4218 void Assembler::divps(XMMRegister dst, XMMRegister src) {
4219 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4220 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4221 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4222 emit_int8(0x5E);
4223 emit_int8((unsigned char)(0xC0 | encode));
4224 }
4225
4226 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4227 assert(VM_Version::supports_avx(), "");
4228 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4229 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4230 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4231 emit_int8(0x5E);
4232 emit_int8((unsigned char)(0xC0 | encode));
4233 }
4234
4235 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4236 assert(VM_Version::supports_avx(), "");
4237 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4238 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4239 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4240 emit_int8(0x5E);
4241 emit_int8((unsigned char)(0xC0 | encode));
4242 }
4243
4244 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4245 assert(VM_Version::supports_avx(), "");
4246 InstructionMark im(this);
4247 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4248 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4249 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4250 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4251 emit_int8(0x5E);
4252 emit_operand(dst, src);
4253 }
4254
4255 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4256 assert(VM_Version::supports_avx(), "");
4257 InstructionMark im(this);
4258 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4259 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4260 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4261 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4262 emit_int8(0x5E);
4263 emit_operand(dst, src);
4264 }
4265
4266 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
4267 assert(VM_Version::supports_avx(), "");
4268 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4269 int nds_enc = 0;
4270 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4271 emit_int8(0x51);
4272 emit_int8((unsigned char)(0xC0 | encode));
4273 }
4274
4275 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
4276 assert(VM_Version::supports_avx(), "");
4277 InstructionMark im(this);
4278 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4279 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4280 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4281 emit_int8(0x51);
4282 emit_operand(dst, src);
4283 }
4284
4285 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
4286 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4287 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4288 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4289 emit_int8(0x54);
4290 emit_int8((unsigned char)(0xC0 | encode));
4291 }
4292
4293 void Assembler::andps(XMMRegister dst, XMMRegister src) {
4294 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4295 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4296 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4297 emit_int8(0x54);
4298 emit_int8((unsigned char)(0xC0 | encode));
4299 }
4300
4301 void Assembler::andps(XMMRegister dst, Address src) {
4302 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4303 InstructionMark im(this);
4304 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4305 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4306 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4307 emit_int8(0x54);
4308 emit_operand(dst, src);
4309 }
4310
4311 void Assembler::andpd(XMMRegister dst, Address src) {
4312 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4313 InstructionMark im(this);
4314 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4315 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4316 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4317 emit_int8(0x54);
4318 emit_operand(dst, src);
4319 }
4320
4321 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4322 assert(VM_Version::supports_avx(), "");
4323 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4324 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4325 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4326 emit_int8(0x54);
4327 emit_int8((unsigned char)(0xC0 | encode));
4328 }
4329
4330 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4331 assert(VM_Version::supports_avx(), "");
4332 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4333 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4334 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4335 emit_int8(0x54);
4336 emit_int8((unsigned char)(0xC0 | encode));
4337 }
4338
4339 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4340 assert(VM_Version::supports_avx(), "");
4341 InstructionMark im(this);
4342 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4343 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4344 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4345 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4346 emit_int8(0x54);
4347 emit_operand(dst, src);
4348 }
4349
4350 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4351 assert(VM_Version::supports_avx(), "");
4352 InstructionMark im(this);
4353 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4354 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4355 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4356 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4357 emit_int8(0x54);
4358 emit_operand(dst, src);
4359 }
4360
4361 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
4362 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4363 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4364 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4365 emit_int8(0x15);
4366 emit_int8((unsigned char)(0xC0 | encode));
4367 }
4368
4369 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
4370 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4371 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4372 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4373 emit_int8(0x14);
4374 emit_int8((unsigned char)(0xC0 | encode));
4375 }
4376
4377 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
4378 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4379 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4380 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4381 emit_int8(0x57);
4382 emit_int8((unsigned char)(0xC0 | encode));
4383 }
4384
4385 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
4386 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4387 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4388 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4389 emit_int8(0x57);
4390 emit_int8((unsigned char)(0xC0 | encode));
4391 }
4392
4393 void Assembler::xorpd(XMMRegister dst, Address src) {
4394 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4395 InstructionMark im(this);
4396 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4397 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4398 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4399 emit_int8(0x57);
4400 emit_operand(dst, src);
4401 }
4402
4403 void Assembler::xorps(XMMRegister dst, Address src) {
4404 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4405 InstructionMark im(this);
4406 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4407 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4408 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4409 emit_int8(0x57);
4410 emit_operand(dst, src);
4411 }
4412
4413 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4414 assert(VM_Version::supports_avx(), "");
4415 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4416 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4417 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4418 emit_int8(0x57);
4419 emit_int8((unsigned char)(0xC0 | encode));
4420 }
4421
4422 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4423 assert(VM_Version::supports_avx(), "");
4424 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4425 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4426 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4427 emit_int8(0x57);
4428 emit_int8((unsigned char)(0xC0 | encode));
4429 }
4430
4431 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4432 assert(VM_Version::supports_avx(), "");
4433 InstructionMark im(this);
4434 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4435 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4436 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4437 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4438 emit_int8(0x57);
4439 emit_operand(dst, src);
4440 }
4441
4442 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4443 assert(VM_Version::supports_avx(), "");
4444 InstructionMark im(this);
4445 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4446 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4447 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4448 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4449 emit_int8(0x57);
4450 emit_operand(dst, src);
4451 }
4452
4453 // Integer vector arithmetic
4454 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4455 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4456 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4457 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4458 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4459 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4460 emit_int8(0x01);
4461 emit_int8((unsigned char)(0xC0 | encode));
4462 }
4463
4464 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4465 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4466 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4467 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4468 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4469 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4470 emit_int8(0x02);
4471 emit_int8((unsigned char)(0xC0 | encode));
4472 }
4473
4474 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
4475 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4476 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4477 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4478 emit_int8((unsigned char)0xFC);
4479 emit_int8((unsigned char)(0xC0 | encode));
4480 }
4481
4482 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
4483 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4484 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4485 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4486 emit_int8((unsigned char)0xFD);
4487 emit_int8((unsigned char)(0xC0 | encode));
4488 }
4489
4490 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
4491 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4492 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4493 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4494 emit_int8((unsigned char)0xFE);
4495 emit_int8((unsigned char)(0xC0 | encode));
4496 }
4497
4498 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
4499 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4500 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4501 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4502 emit_int8((unsigned char)0xD4);
4503 emit_int8((unsigned char)(0xC0 | encode));
4504 }
4505
4506 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
4507 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4508 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4509 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4510 emit_int8(0x01);
4511 emit_int8((unsigned char)(0xC0 | encode));
4512 }
4513
4514 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
4515 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4516 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4517 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4518 emit_int8(0x02);
4519 emit_int8((unsigned char)(0xC0 | encode));
4520 }
4521
4522 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4523 assert(UseAVX > 0, "requires some form of AVX");
4524 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4525 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4526 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4527 emit_int8((unsigned char)0xFC);
4528 emit_int8((unsigned char)(0xC0 | encode));
4529 }
4530
4531 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4532 assert(UseAVX > 0, "requires some form of AVX");
4533 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4534 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4535 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4536 emit_int8((unsigned char)0xFD);
4537 emit_int8((unsigned char)(0xC0 | encode));
4538 }
4539
4540 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4541 assert(UseAVX > 0, "requires some form of AVX");
4542 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4543 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4544 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4545 emit_int8((unsigned char)0xFE);
4546 emit_int8((unsigned char)(0xC0 | encode));
4547 }
4548
4549 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4550 assert(UseAVX > 0, "requires some form of AVX");
4551 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4552 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4553 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4554 emit_int8((unsigned char)0xD4);
4555 emit_int8((unsigned char)(0xC0 | encode));
4556 }
4557
4558 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4559 assert(UseAVX > 0, "requires some form of AVX");
4560 InstructionMark im(this);
4561 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4562 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4563 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4564 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4565 emit_int8((unsigned char)0xFC);
4566 emit_operand(dst, src);
4567 }
4568
4569 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4570 assert(UseAVX > 0, "requires some form of AVX");
4571 InstructionMark im(this);
4572 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4573 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4574 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4575 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4576 emit_int8((unsigned char)0xFD);
4577 emit_operand(dst, src);
4578 }
4579
4580 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4581 assert(UseAVX > 0, "requires some form of AVX");
4582 InstructionMark im(this);
4583 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4584 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4585 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4586 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4587 emit_int8((unsigned char)0xFE);
4588 emit_operand(dst, src);
4589 }
4590
4591 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4592 assert(UseAVX > 0, "requires some form of AVX");
4593 InstructionMark im(this);
4594 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4595 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4596 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4597 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4598 emit_int8((unsigned char)0xD4);
4599 emit_operand(dst, src);
4600 }
4601
4602 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
4603 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4604 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4605 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4606 emit_int8((unsigned char)0xF8);
4607 emit_int8((unsigned char)(0xC0 | encode));
4608 }
4609
4610 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
4611 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4612 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4613 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4614 emit_int8((unsigned char)0xF9);
4615 emit_int8((unsigned char)(0xC0 | encode));
4616 }
4617
4618 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
4619 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4620 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4621 emit_int8((unsigned char)0xFA);
4622 emit_int8((unsigned char)(0xC0 | encode));
4623 }
4624
4625 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
4626 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4627 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4628 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4629 emit_int8((unsigned char)0xFB);
4630 emit_int8((unsigned char)(0xC0 | encode));
4631 }
4632
4633 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4634 assert(UseAVX > 0, "requires some form of AVX");
4635 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4636 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4637 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4638 emit_int8((unsigned char)0xF8);
4639 emit_int8((unsigned char)(0xC0 | encode));
4640 }
4641
4642 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4643 assert(UseAVX > 0, "requires some form of AVX");
4644 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4645 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4646 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4647 emit_int8((unsigned char)0xF9);
4648 emit_int8((unsigned char)(0xC0 | encode));
4649 }
4650
4651 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4652 assert(UseAVX > 0, "requires some form of AVX");
4653 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4654 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4655 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4656 emit_int8((unsigned char)0xFA);
4657 emit_int8((unsigned char)(0xC0 | encode));
4658 }
4659
4660 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4661 assert(UseAVX > 0, "requires some form of AVX");
4662 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4663 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4664 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4665 emit_int8((unsigned char)0xFB);
4666 emit_int8((unsigned char)(0xC0 | encode));
4667 }
4668
4669 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4670 assert(UseAVX > 0, "requires some form of AVX");
4671 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4672 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4673 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4674 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4675 emit_int8((unsigned char)0xF8);
4676 emit_operand(dst, src);
4677 }
4678
4679 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4680 assert(UseAVX > 0, "requires some form of AVX");
4681 InstructionMark im(this);
4682 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4683 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4684 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4685 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4686 emit_int8((unsigned char)0xF9);
4687 emit_operand(dst, src);
4688 }
4689
4690 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4691 assert(UseAVX > 0, "requires some form of AVX");
4692 InstructionMark im(this);
4693 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4694 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4695 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4696 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4697 emit_int8((unsigned char)0xFA);
4698 emit_operand(dst, src);
4699 }
4700
4701 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4702 assert(UseAVX > 0, "requires some form of AVX");
4703 InstructionMark im(this);
4704 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4705 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4706 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4707 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4708 emit_int8((unsigned char)0xFB);
4709 emit_operand(dst, src);
4710 }
4711
4712 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
4713 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4714 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4715 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4716 emit_int8((unsigned char)0xD5);
4717 emit_int8((unsigned char)(0xC0 | encode));
4718 }
4719
4720 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
4721 assert(VM_Version::supports_sse4_1(), "");
4722 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4723 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4724 emit_int8(0x40);
4725 emit_int8((unsigned char)(0xC0 | encode));
4726 }
4727
4728 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4729 assert(UseAVX > 0, "requires some form of AVX");
4730 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4731 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4732 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4733 emit_int8((unsigned char)0xD5);
4734 emit_int8((unsigned char)(0xC0 | encode));
4735 }
4736
4737 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4738 assert(UseAVX > 0, "requires some form of AVX");
4739 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4740 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4741 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4742 emit_int8(0x40);
4743 emit_int8((unsigned char)(0xC0 | encode));
4744 }
4745
4746 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4747 assert(UseAVX > 2, "requires some form of AVX");
4748 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4749 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4750 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4751 emit_int8(0x40);
4752 emit_int8((unsigned char)(0xC0 | encode));
4753 }
4754
4755 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4756 assert(UseAVX > 0, "requires some form of AVX");
4757 InstructionMark im(this);
4758 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4759 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4760 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4761 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4762 emit_int8((unsigned char)0xD5);
4763 emit_operand(dst, src);
4764 }
4765
4766 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4767 assert(UseAVX > 0, "requires some form of AVX");
4768 InstructionMark im(this);
4769 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4770 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4771 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4772 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4773 emit_int8(0x40);
4774 emit_operand(dst, src);
4775 }
4776
4777 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4778 assert(UseAVX > 0, "requires some form of AVX");
4779 InstructionMark im(this);
4780 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4781 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4782 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4783 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4784 emit_int8(0x40);
4785 emit_operand(dst, src);
4786 }
4787
4788 // Shift packed integers left by specified number of bits.
4789 void Assembler::psllw(XMMRegister dst, int shift) {
4790 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4791 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4792 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
4793 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4794 emit_int8(0x71);
4795 emit_int8((unsigned char)(0xC0 | encode));
4796 emit_int8(shift & 0xFF);
4797 }
4798
4799 void Assembler::pslld(XMMRegister dst, int shift) {
4800 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4801 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4802 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
4803 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4804 emit_int8(0x72);
4805 emit_int8((unsigned char)(0xC0 | encode));
4806 emit_int8(shift & 0xFF);
4807 }
4808
4809 void Assembler::psllq(XMMRegister dst, int shift) {
4810 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4811 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4812 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
4813 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4814 emit_int8(0x73);
4815 emit_int8((unsigned char)(0xC0 | encode));
4816 emit_int8(shift & 0xFF);
4817 }
4818
4819 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
4820 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4821 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4822 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4823 emit_int8((unsigned char)0xF1);
4824 emit_int8((unsigned char)(0xC0 | encode));
4825 }
4826
4827 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
4828 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4829 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4830 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4831 emit_int8((unsigned char)0xF2);
4832 emit_int8((unsigned char)(0xC0 | encode));
4833 }
4834
4835 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
4836 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4837 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4838 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4839 emit_int8((unsigned char)0xF3);
4840 emit_int8((unsigned char)(0xC0 | encode));
4841 }
4842
4843 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4844 assert(UseAVX > 0, "requires some form of AVX");
4845 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4846 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
4847 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4848 emit_int8(0x71);
4849 emit_int8((unsigned char)(0xC0 | encode));
4850 emit_int8(shift & 0xFF);
4851 }
4852
4853 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4854 assert(UseAVX > 0, "requires some form of AVX");
4855 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4856 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4857 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
4858 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4859 emit_int8(0x72);
4860 emit_int8((unsigned char)(0xC0 | encode));
4861 emit_int8(shift & 0xFF);
4862 }
4863
4864 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4865 assert(UseAVX > 0, "requires some form of AVX");
4866 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4867 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
4868 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4869 emit_int8(0x73);
4870 emit_int8((unsigned char)(0xC0 | encode));
4871 emit_int8(shift & 0xFF);
4872 }
4873
4874 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4875 assert(UseAVX > 0, "requires some form of AVX");
4876 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4877 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4878 emit_int8((unsigned char)0xF1);
4879 emit_int8((unsigned char)(0xC0 | encode));
4880 }
4881
4882 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4883 assert(UseAVX > 0, "requires some form of AVX");
4884 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4885 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4886 emit_int8((unsigned char)0xF2);
4887 emit_int8((unsigned char)(0xC0 | encode));
4888 }
4889
4890 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4891 assert(UseAVX > 0, "requires some form of AVX");
4892 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4893 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4894 emit_int8((unsigned char)0xF3);
4895 emit_int8((unsigned char)(0xC0 | encode));
4896 }
4897
4898 // Shift packed integers logically right by specified number of bits.
4899 void Assembler::psrlw(XMMRegister dst, int shift) {
4900 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4901 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4902 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
4903 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4904 emit_int8(0x71);
4905 emit_int8((unsigned char)(0xC0 | encode));
4906 emit_int8(shift & 0xFF);
4907 }
4908
4909 void Assembler::psrld(XMMRegister dst, int shift) {
4910 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4911 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4912 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
4913 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4914 emit_int8(0x72);
4915 emit_int8((unsigned char)(0xC0 | encode));
4916 emit_int8(shift & 0xFF);
4917 }
4918
4919 void Assembler::psrlq(XMMRegister dst, int shift) {
4920 // Do not confuse it with psrldq SSE2 instruction which
4921 // shifts 128 bit value in xmm register by number of bytes.
4922 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4923 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4924 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4925 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4926 emit_int8(0x73);
4927 emit_int8((unsigned char)(0xC0 | encode));
4928 emit_int8(shift & 0xFF);
4929 }
4930
4931 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
4932 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4933 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4934 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4935 emit_int8((unsigned char)0xD1);
4936 emit_int8((unsigned char)(0xC0 | encode));
4937 }
4938
4939 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
4940 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4941 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4942 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4943 emit_int8((unsigned char)0xD2);
4944 emit_int8((unsigned char)(0xC0 | encode));
4945 }
4946
4947 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
4948 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4949 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4950 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4951 emit_int8((unsigned char)0xD3);
4952 emit_int8((unsigned char)(0xC0 | encode));
4953 }
4954
4955 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4956 assert(UseAVX > 0, "requires some form of AVX");
4957 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4958 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
4959 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4960 emit_int8(0x71);
4961 emit_int8((unsigned char)(0xC0 | encode));
4962 emit_int8(shift & 0xFF);
4963 }
4964
4965 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4966 assert(UseAVX > 0, "requires some form of AVX");
4967 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4968 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
4969 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4970 emit_int8(0x72);
4971 emit_int8((unsigned char)(0xC0 | encode));
4972 emit_int8(shift & 0xFF);
4973 }
4974
4975 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4976 assert(UseAVX > 0, "requires some form of AVX");
4977 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4978 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4979 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4980 emit_int8(0x73);
4981 emit_int8((unsigned char)(0xC0 | encode));
4982 emit_int8(shift & 0xFF);
4983 }
4984
4985 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4986 assert(UseAVX > 0, "requires some form of AVX");
4987 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4988 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4989 emit_int8((unsigned char)0xD1);
4990 emit_int8((unsigned char)(0xC0 | encode));
4991 }
4992
4993 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4994 assert(UseAVX > 0, "requires some form of AVX");
4995 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4996 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4997 emit_int8((unsigned char)0xD2);
4998 emit_int8((unsigned char)(0xC0 | encode));
4999 }
5000
5001 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5002 assert(UseAVX > 0, "requires some form of AVX");
5003 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5004 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5005 emit_int8((unsigned char)0xD3);
5006 emit_int8((unsigned char)(0xC0 | encode));
5007 }
5008
5009 // Shift packed integers arithmetically right by specified number of bits.
5010 void Assembler::psraw(XMMRegister dst, int shift) {
5011 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5012 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5013 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5014 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5015 emit_int8(0x71);
5016 emit_int8((unsigned char)(0xC0 | encode));
5017 emit_int8(shift & 0xFF);
5018 }
5019
5020 void Assembler::psrad(XMMRegister dst, int shift) {
5021 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5022 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5023 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
5024 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5025 emit_int8(0x72);
5026 emit_int8((unsigned char)(0xC0 | encode));
5027 emit_int8(shift & 0xFF);
5028 }
5029
5030 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
5031 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5032 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5033 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5034 emit_int8((unsigned char)0xE1);
5035 emit_int8((unsigned char)(0xC0 | encode));
5036 }
5037
5038 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
5039 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5040 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5041 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5042 emit_int8((unsigned char)0xE2);
5043 emit_int8((unsigned char)(0xC0 | encode));
5044 }
5045
5046 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5047 assert(UseAVX > 0, "requires some form of AVX");
5048 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5049 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5050 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5051 emit_int8(0x71);
5052 emit_int8((unsigned char)(0xC0 | encode));
5053 emit_int8(shift & 0xFF);
5054 }
5055
5056 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5057 assert(UseAVX > 0, "requires some form of AVX");
5058 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5059 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5060 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5061 emit_int8(0x72);
5062 emit_int8((unsigned char)(0xC0 | encode));
5063 emit_int8(shift & 0xFF);
5064 }
5065
5066 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5067 assert(UseAVX > 0, "requires some form of AVX");
5068 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5069 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5070 emit_int8((unsigned char)0xE1);
5071 emit_int8((unsigned char)(0xC0 | encode));
5072 }
5073
5074 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5075 assert(UseAVX > 0, "requires some form of AVX");
5076 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5077 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5078 emit_int8((unsigned char)0xE2);
5079 emit_int8((unsigned char)(0xC0 | encode));
5080 }
5081
5082
5083 // logical operations packed integers
5084 void Assembler::pand(XMMRegister dst, XMMRegister src) {
5085 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5086 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5087 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5088 emit_int8((unsigned char)0xDB);
5089 emit_int8((unsigned char)(0xC0 | encode));
5090 }
5091
5092 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5093 assert(UseAVX > 0, "requires some form of AVX");
5094 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5095 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5096 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5097 emit_int8((unsigned char)0xDB);
5098 emit_int8((unsigned char)(0xC0 | encode));
5099 }
5100
5101 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5102 assert(UseAVX > 0, "requires some form of AVX");
5103 InstructionMark im(this);
5104 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5105 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5106 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5107 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5108 emit_int8((unsigned char)0xDB);
5109 emit_operand(dst, src);
5110 }
5111
5112 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
5113 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5114 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5115 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5116 emit_int8((unsigned char)0xDF);
5117 emit_int8((unsigned char)(0xC0 | encode));
5118 }
5119
5120 void Assembler::por(XMMRegister dst, XMMRegister src) {
5121 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5122 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5123 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5124 emit_int8((unsigned char)0xEB);
5125 emit_int8((unsigned char)(0xC0 | encode));
5126 }
5127
5128 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5129 assert(UseAVX > 0, "requires some form of AVX");
5130 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5131 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5132 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5133 emit_int8((unsigned char)0xEB);
5134 emit_int8((unsigned char)(0xC0 | encode));
5135 }
5136
5137 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5138 assert(UseAVX > 0, "requires some form of AVX");
5139 InstructionMark im(this);
5140 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5141 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5142 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5143 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5144 emit_int8((unsigned char)0xEB);
5145 emit_operand(dst, src);
5146 }
5147
5148 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
5149 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5150 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5151 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5152 emit_int8((unsigned char)0xEF);
5153 emit_int8((unsigned char)(0xC0 | encode));
5154 }
5155
5156 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5157 assert(UseAVX > 0, "requires some form of AVX");
5158 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5159 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5160 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5161 emit_int8((unsigned char)0xEF);
5162 emit_int8((unsigned char)(0xC0 | encode));
5163 }
5164
5165 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5166 assert(UseAVX > 0, "requires some form of AVX");
5167 InstructionMark im(this);
5168 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5169 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5170 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5171 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5172 emit_int8((unsigned char)0xEF);
5173 emit_operand(dst, src);
5174 }
5175
5176
5177 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5178 assert(VM_Version::supports_avx(), "");
5179 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5180 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5181 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5182 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5183 emit_int8(0x18);
5184 emit_int8((unsigned char)(0xC0 | encode));
5185 // 0x00 - insert into lower 128 bits
5186 // 0x01 - insert into upper 128 bits
5187 emit_int8(0x01);
5188 }
5189
5190 void Assembler::vinsertf64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src, int value) {
5191 assert(VM_Version::supports_evex(), "");
5192 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5193 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5194 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5195 emit_int8(0x1A);
5196 emit_int8((unsigned char)(0xC0 | encode));
5197 // 0x00 - insert into lower 256 bits
5198 // 0x01 - insert into upper 256 bits
5199 emit_int8(value & 0x01);
5200 }
5201
5202 void Assembler::vinsertf64x4h(XMMRegister dst, Address src, int value) {
5203 assert(VM_Version::supports_evex(), "");
5204 assert(dst != xnoreg, "sanity");
5205 InstructionMark im(this);
5206 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5207 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
5208 // swap src<->dst for encoding
5209 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5210 emit_int8(0x1A);
5211 emit_operand(dst, src);
5212 // 0x00 - insert into lower 256 bits
5213 // 0x01 - insert into upper 128 bits
5214 emit_int8(value & 0x01);
5215 }
5216
5217 void Assembler::vinsertf32x4h(XMMRegister dst, XMMRegister nds, XMMRegister src, int value) {
5218 assert(VM_Version::supports_evex(), "");
5219 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5220 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5221 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5222 emit_int8(0x18);
5223 emit_int8((unsigned char)(0xC0 | encode));
5224 // 0x00 - insert into q0 128 bits (0..127)
5225 // 0x01 - insert into q1 128 bits (128..255)
5226 // 0x02 - insert into q2 128 bits (256..383)
5227 // 0x03 - insert into q3 128 bits (384..511)
5228 emit_int8(value & 0x3);
5229 }
5230
5231 void Assembler::vinsertf32x4h(XMMRegister dst, Address src, int value) {
5232 assert(VM_Version::supports_avx(), "");
5233 assert(dst != xnoreg, "sanity");
5234 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5235 InstructionMark im(this);
5236 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5237 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5238 // swap src<->dst for encoding
5239 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5240 emit_int8(0x18);
5241 emit_operand(dst, src);
5242 // 0x00 - insert into q0 128 bits (0..127)
5243 // 0x01 - insert into q1 128 bits (128..255)
5244 // 0x02 - insert into q2 128 bits (256..383)
5245 // 0x03 - insert into q3 128 bits (384..511)
5246 emit_int8(value & 0x3);
5247 }
5248
5249 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
5250 assert(VM_Version::supports_avx(), "");
5251 assert(dst != xnoreg, "sanity");
5252 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5253 InstructionMark im(this);
5254 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5255 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5256 // swap src<->dst for encoding
5257 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5258 emit_int8(0x18);
5259 emit_operand(dst, src);
5260 // 0x01 - insert into upper 128 bits
5261 emit_int8(0x01);
5262 }
5263
5264 void Assembler::vextractf128h(XMMRegister dst, XMMRegister src) {
5265 assert(VM_Version::supports_avx(), "");
5266 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5267 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5268 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5269 emit_int8(0x19);
5270 emit_int8((unsigned char)(0xC0 | encode));
5271 // 0x00 - insert into lower 128 bits
5272 // 0x01 - insert into upper 128 bits
5273 emit_int8(0x01);
5274 }
5275
5276 void Assembler::vextractf128h(Address dst, XMMRegister src) {
5277 assert(VM_Version::supports_avx(), "");
5278 assert(src != xnoreg, "sanity");
5279 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5280 InstructionMark im(this);
5281 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5282 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5283 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5284 emit_int8(0x19);
5285 emit_operand(src, dst);
5286 // 0x01 - extract from upper 128 bits
5287 emit_int8(0x01);
5288 }
5289
5290 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5291 assert(VM_Version::supports_avx2(), "");
5292 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5293 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5294 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5295 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5296 emit_int8(0x38);
5297 emit_int8((unsigned char)(0xC0 | encode));
5298 // 0x00 - insert into lower 128 bits
5299 // 0x01 - insert into upper 128 bits
5300 emit_int8(0x01);
5301 }
5302
5303 void Assembler::vinserti64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src, int value) {
5304 assert(VM_Version::supports_evex(), "");
5305 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5306 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5307 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5308 emit_int8(0x38);
5309 emit_int8((unsigned char)(0xC0 | encode));
5310 // 0x00 - insert into lower 256 bits
5311 // 0x01 - insert into upper 256 bits
5312 emit_int8(value & 0x01);
5313 }
5314
5315 void Assembler::vinserti128h(XMMRegister dst, Address src) {
5316 assert(VM_Version::supports_avx2(), "");
5317 assert(dst != xnoreg, "sanity");
5318 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5319 InstructionMark im(this);
5320 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5321 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5322 // swap src<->dst for encoding
5323 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5324 emit_int8(0x38);
5325 emit_operand(dst, src);
5326 // 0x01 - insert into upper 128 bits
5327 emit_int8(0x01);
5328 }
5329
5330 void Assembler::vextracti128h(XMMRegister dst, XMMRegister src) {
5331 assert(VM_Version::supports_avx(), "");
5332 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5333 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5334 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5335 emit_int8(0x39);
5336 emit_int8((unsigned char)(0xC0 | encode));
5337 // 0x00 - insert into lower 128 bits
5338 // 0x01 - insert into upper 128 bits
5339 emit_int8(0x01);
5340 }
5341
5342 void Assembler::vextracti128h(Address dst, XMMRegister src) {
5343 assert(VM_Version::supports_avx2(), "");
5344 assert(src != xnoreg, "sanity");
5345 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5346 InstructionMark im(this);
5347 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5348 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5349 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5350 emit_int8(0x39);
5351 emit_operand(src, dst);
5352 // 0x01 - extract from upper 128 bits
5353 emit_int8(0x01);
5354 }
5355
5356 void Assembler::vextracti64x4h(XMMRegister dst, XMMRegister src, int value) {
5357 assert(VM_Version::supports_evex(), "");
5358 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5359 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5360 emit_int8(0x3B);
5361 emit_int8((unsigned char)(0xC0 | encode));
5362 // 0x00 - extract from lower 256 bits
5363 // 0x01 - extract from upper 256 bits
5364 emit_int8(value & 0x01);
5365 }
5366
5367 void Assembler::vextracti64x2h(XMMRegister dst, XMMRegister src, int value) {
5368 assert(VM_Version::supports_evex(), "");
5369 InstructionAttr attributes(AVX_512bit, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5370 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5371 emit_int8(0x39);
5372 emit_int8((unsigned char)(0xC0 | encode));
5373 // 0x01 - extract from bits 255:128
5374 // 0x02 - extract from bits 383:256
5375 // 0x03 - extract from bits 511:384
5376 emit_int8(value & 0x3);
5377 }
5378
5379 void Assembler::vextractf64x4h(XMMRegister dst, XMMRegister src, int value) {
5380 assert(VM_Version::supports_evex(), "");
5381 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5382 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5383 emit_int8(0x1B);
5384 emit_int8((unsigned char)(0xC0 | encode));
5385 // 0x00 - extract from lower 256 bits
5386 // 0x01 - extract from upper 256 bits
5387 emit_int8(value & 0x1);
5388 }
5389
5390 void Assembler::vextractf64x4h(Address dst, XMMRegister src, int value) {
5391 assert(VM_Version::supports_evex(), "");
5392 assert(src != xnoreg, "sanity");
5393 InstructionMark im(this);
5394 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5395 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
5396 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5397 emit_int8(0x1B);
5398 emit_operand(src, dst);
5399 // 0x00 - extract from lower 256 bits
5400 // 0x01 - extract from upper 256 bits
5401 emit_int8(value & 0x01);
5402 }
5403
5404 void Assembler::vextractf32x4h(XMMRegister dst, XMMRegister src, int value) {
5405 assert(VM_Version::supports_avx(), "");
5406 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5407 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5408 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5409 emit_int8(0x19);
5410 emit_int8((unsigned char)(0xC0 | encode));
5411 // 0x00 - extract from bits 127:0
5412 // 0x01 - extract from bits 255:128
5413 // 0x02 - extract from bits 383:256
5414 // 0x03 - extract from bits 511:384
5415 emit_int8(value & 0x3);
5416 }
5417
5418 void Assembler::vextractf32x4h(Address dst, XMMRegister src, int value) {
5419 assert(VM_Version::supports_evex(), "");
5420 assert(src != xnoreg, "sanity");
5421 InstructionMark im(this);
5422 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5423 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5424 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5425 emit_int8(0x19);
5426 emit_operand(src, dst);
5427 // 0x00 - extract from bits 127:0
5428 // 0x01 - extract from bits 255:128
5429 // 0x02 - extract from bits 383:256
5430 // 0x03 - extract from bits 511:384
5431 emit_int8(value & 0x3);
5432 }
5433
5434 void Assembler::vextractf64x2h(XMMRegister dst, XMMRegister src, int value) {
5435 assert(VM_Version::supports_evex(), "");
5436 InstructionAttr attributes(AVX_512bit, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5437 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5438 emit_int8(0x19);
5439 emit_int8((unsigned char)(0xC0 | encode));
5440 // 0x01 - extract from bits 255:128
5441 // 0x02 - extract from bits 383:256
5442 // 0x03 - extract from bits 511:384
5443 emit_int8(value & 0x3);
5444 }
5445
5446 // duplicate 4-bytes integer data from src into 8 locations in dest
5447 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
5448 assert(UseAVX > 1, "");
5449 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5450 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5451 emit_int8(0x58);
5452 emit_int8((unsigned char)(0xC0 | encode));
5453 }
5454
5455 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
5456 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
5457 assert(UseAVX > 1, "");
5458 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5459 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5460 emit_int8(0x78);
5461 emit_int8((unsigned char)(0xC0 | encode));
5462 }
5463
5464 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
5465 assert(UseAVX > 1, "");
5466 assert(dst != xnoreg, "sanity");
5467 InstructionMark im(this);
5468 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5469 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
5470 // swap src<->dst for encoding
5471 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5472 emit_int8(0x78);
5473 emit_operand(dst, src);
5474 }
5475
5476 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
5477 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
5478 assert(UseAVX > 1, "");
5479 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5480 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5481 emit_int8(0x79);
5482 emit_int8((unsigned char)(0xC0 | encode));
5483 }
5484
5485 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
5486 assert(UseAVX > 1, "");
5487 assert(dst != xnoreg, "sanity");
5488 InstructionMark im(this);
5489 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5490 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
5491 // swap src<->dst for encoding
5492 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5493 emit_int8(0x79);
5494 emit_operand(dst, src);
5495 }
5496
5497 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5498 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
5499 assert(UseAVX > 1, "");
5500 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5501 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5502 emit_int8(0x58);
5503 emit_int8((unsigned char)(0xC0 | encode));
5504 }
5505
5506 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
5507 assert(UseAVX > 1, "");
5508 assert(dst != xnoreg, "sanity");
5509 InstructionMark im(this);
5510 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5511 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5512 // swap src<->dst for encoding
5513 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5514 emit_int8(0x58);
5515 emit_operand(dst, src);
5516 }
5517
5518 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5519 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
5520 assert(UseAVX > 1, "");
5521 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5522 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5523 emit_int8(0x59);
5524 emit_int8((unsigned char)(0xC0 | encode));
5525 }
5526
5527 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
5528 assert(UseAVX > 1, "");
5529 assert(dst != xnoreg, "sanity");
5530 InstructionMark im(this);
5531 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5532 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5533 // swap src<->dst for encoding
5534 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5535 emit_int8(0x59);
5536 emit_operand(dst, src);
5537 }
5538
5539 // duplicate single precision fp from src into 4|8|16 locations in dest : requires AVX512VL
5540 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
5541 assert(UseAVX > 1, "");
5542 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5543 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5544 emit_int8(0x18);
5545 emit_int8((unsigned char)(0xC0 | encode));
5546 }
5547
5548 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
5549 assert(UseAVX > 1, "");
5550 assert(dst != xnoreg, "sanity");
5551 InstructionMark im(this);
5552 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5553 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5554 // swap src<->dst for encoding
5555 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5556 emit_int8(0x18);
5557 emit_operand(dst, src);
5558 }
5559
5560 // duplicate double precision fp from src into 2|4|8 locations in dest : requires AVX512VL
5561 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
5562 assert(UseAVX > 1, "");
5563 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5564 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5565 emit_int8(0x19);
5566 emit_int8((unsigned char)(0xC0 | encode));
5567 }
5568
5569 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
5570 assert(UseAVX > 1, "");
5571 assert(dst != xnoreg, "sanity");
5572 InstructionMark im(this);
5573 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5574 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5575 // swap src<->dst for encoding
5576 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5577 emit_int8(0x19);
5578 emit_operand(dst, src);
5579 }
5580
5581 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
5582 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
5583 assert(VM_Version::supports_evex(), "");
5584 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5585 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5586 emit_int8(0x7A);
5587 emit_int8((unsigned char)(0xC0 | encode));
5588 }
5589
5590 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
5591 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
5592 assert(VM_Version::supports_evex(), "");
5593 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5594 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5595 emit_int8(0x7B);
5596 emit_int8((unsigned char)(0xC0 | encode));
5597 }
5598
5599 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5600 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
5601 assert(VM_Version::supports_evex(), "");
5602 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5603 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5604 emit_int8(0x7C);
5605 emit_int8((unsigned char)(0xC0 | encode));
5606 }
5607
5608 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5609 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
5610 assert(VM_Version::supports_evex(), "");
5611 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5612 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5613 emit_int8(0x7C);
5614 emit_int8((unsigned char)(0xC0 | encode));
5615 }
5616
5617 // Carry-Less Multiplication Quadword
5618 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
5619 assert(VM_Version::supports_clmul(), "");
5620 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5621 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5622 emit_int8(0x44);
5623 emit_int8((unsigned char)(0xC0 | encode));
5624 emit_int8((unsigned char)mask);
5625 }
5626
5627 // Carry-Less Multiplication Quadword
5628 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
5629 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
5630 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5631 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5632 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5633 emit_int8(0x44);
5634 emit_int8((unsigned char)(0xC0 | encode));
5635 emit_int8((unsigned char)mask);
5636 }
5637
5638 void Assembler::vzeroupper() {
5639 assert(VM_Version::supports_avx(), "");
5640 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5641 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5642 emit_int8(0x77);
5643 }
5644
5645
5646 #ifndef _LP64
5647 // 32bit only pieces of the assembler
5648
5649 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
5650 // NO PREFIX AS NEVER 64BIT
5651 InstructionMark im(this);
5652 emit_int8((unsigned char)0x81);
5653 emit_int8((unsigned char)(0xF8 | src1->encoding()));
5654 emit_data(imm32, rspec, 0);
5655 }
5656
5657 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
5658 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
5659 InstructionMark im(this);
5660 emit_int8((unsigned char)0x81);
5661 emit_operand(rdi, src1);
5662 emit_data(imm32, rspec, 0);
6126 emit_int8(simd_pre[pre]);
6127 }
6128 if (rex_w) {
6129 prefixq(adr, xreg);
6130 } else {
6131 prefix(adr, xreg);
6132 }
6133 if (opc > 0) {
6134 emit_int8(0x0F);
6135 int opc2 = simd_opc[opc];
6136 if (opc2 > 0) {
6137 emit_int8(opc2);
6138 }
6139 }
6140 }
6141
6142 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6143 if (pre > 0) {
6144 emit_int8(simd_pre[pre]);
6145 }
6146 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
6147 if (opc > 0) {
6148 emit_int8(0x0F);
6149 int opc2 = simd_opc[opc];
6150 if (opc2 > 0) {
6151 emit_int8(opc2);
6152 }
6153 }
6154 return encode;
6155 }
6156
6157
6158 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
6159 int vector_len = _attributes->get_vector_len();
6160 bool vex_w = _attributes->is_rex_vex_w();
6161 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
6162 prefix(VEX_3bytes);
6163
6164 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
6165 byte1 = (~byte1) & 0xE0;
6166 byte1 |= opc;
6167 emit_int8(byte1);
6168
6169 int byte2 = ((~nds_enc) & 0xf) << 3;
6170 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
6171 emit_int8(byte2);
6172 } else {
6173 prefix(VEX_2bytes);
6174
6175 int byte1 = vex_r ? VEX_R : 0;
6176 byte1 = (~byte1) & 0x80;
6177 byte1 |= ((~nds_enc) & 0xf) << 3;
6178 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
6179 emit_int8(byte1);
6180 }
6181 }
6182
6183 // This is a 4 byte encoding
6184 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
6185 // EVEX 0x62 prefix
6186 prefix(EVEX_4bytes);
6187 bool vex_w = _attributes->is_rex_vex_w();
6188 int evex_encoding = (vex_w ? VEX_W : 0);
6189 // EVEX.b is not currently used for broadcast of single element or data rounding modes
6190 _attributes->set_evex_encoding(evex_encoding);
6191
6192 // P0: byte 2, initialized to RXBR`00mm
6193 // instead of not'd
6194 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
6195 byte2 = (~byte2) & 0xF0;
6196 // confine opc opcode extensions in mm bits to lower two bits
6197 // of form {0F, 0F_38, 0F_3A}
6198 byte2 |= opc;
6199 emit_int8(byte2);
6200
6201 // P1: byte 3 as Wvvvv1pp
6202 int byte3 = ((~nds_enc) & 0xf) << 3;
6203 // p[10] is always 1
6204 byte3 |= EVEX_F;
6205 byte3 |= (vex_w & 1) << 7;
6206 // confine pre opcode extensions in pp bits to lower two bits
6207 // of form {66, F3, F2}
6208 byte3 |= pre;
6209 emit_int8(byte3);
6210
6211 // P2: byte 4 as zL'Lbv'aaa
6212 int byte4 = (_attributes->is_no_reg_mask()) ? 0 : 1; // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
6213 // EVEX.v` for extending EVEX.vvvv or VIDX
6214 byte4 |= (evex_v ? 0: EVEX_V);
6215 // third EXEC.b for broadcast actions
6216 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
6217 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
6218 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
6219 // last is EVEX.z for zero/merge actions
6220 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
6221 emit_int8(byte4);
6222 }
6223
6224 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
6225 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
6226 bool vex_b = adr.base_needs_rex();
6227 bool vex_x = adr.index_needs_rex();
6228 set_attributes(attributes);
6229 attributes->set_current_assembler(this);
6230
6231 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6232 if ((UseAVX > 2) && _legacy_mode_vl && attributes->uses_vl()) {
6233 switch (attributes->get_vector_len()) {
6234 case AVX_128bit:
6235 case AVX_256bit:
6236 attributes->set_is_legacy_mode();
6237 break;
6238 }
6239 }
6240
6241 if ((UseAVX > 2) && !attributes->is_legacy_mode())
6242 {
6243 bool evex_r = (xreg_enc >= 16);
6244 bool evex_v = (nds_enc >= 16);
6245 attributes->set_is_evex_instruction();
6246 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
6247 } else {
6248 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
6249 }
6250 }
6251
6252 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
6253 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
6254 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
6255 bool vex_x = false;
6256 set_attributes(attributes);
6257 attributes->set_current_assembler(this);
6258
6259 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6260 if ((UseAVX > 2) && _legacy_mode_vl && attributes->uses_vl()) {
6261 switch (attributes->get_vector_len()) {
6262 case AVX_128bit:
6263 case AVX_256bit:
6264 if ((dst_enc >= 16) | (nds_enc >= 16) | (src_enc >= 16)) {
6265 // up propagate arithmetic instructions to meet RA requirements
6266 attributes->set_vector_len(AVX_512bit);
6267 } else {
6268 attributes->set_is_legacy_mode();
6269 }
6270 break;
6271 }
6272 }
6273
6274 if ((UseAVX > 2) && !attributes->is_legacy_mode())
6275 {
6276 bool evex_r = (dst_enc >= 16);
6277 bool evex_v = (nds_enc >= 16);
6278 // can use vex_x as bank extender on rm encoding
6279 vex_x = (src_enc >= 16);
6280 attributes->set_is_evex_instruction();
6281 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
6282 } else {
6283 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
6284 }
6285
6286 // return modrm byte components for operands
6287 return (((dst_enc & 7) << 3) | (src_enc & 7));
6288 }
6289
6290
6291 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
6292 VexOpcode opc, InstructionAttr *attributes) {
6293 if (UseAVX > 0) {
6294 int xreg_enc = xreg->encoding();
6295 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6296 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
6297 } else {
6298 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
6299 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
6300 }
6301 }
6302
6303 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
6304 VexOpcode opc, InstructionAttr *attributes) {
6305 int dst_enc = dst->encoding();
6306 int src_enc = src->encoding();
6307 if (UseAVX > 0) {
6308 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6309 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
6310 } else {
6311 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
6312 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
6313 }
6314 }
6315
6316 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, KRegister src, VexSimdPrefix pre,
6317 VexOpcode opc, InstructionAttr *attributes) {
6318 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6319 return vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), pre, opc, attributes);
6320 }
6321
6322 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, Register src, VexSimdPrefix pre,
6323 VexOpcode opc, InstructionAttr *attributes) {
6324 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6325 return vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), pre, opc, attributes);
6326 }
6327
6328 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
6329 assert(VM_Version::supports_avx(), "");
6330 assert(!VM_Version::supports_evex(), "");
6331 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6332 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6333 emit_int8((unsigned char)0xC2);
6334 emit_int8((unsigned char)(0xC0 | encode));
6335 emit_int8((unsigned char)(0xF & cop));
6336 }
6337
6338 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
6339 assert(VM_Version::supports_avx(), "");
6340 assert(!VM_Version::supports_evex(), "");
6341 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6342 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6343 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6344 emit_int8((unsigned char)0x4B);
6345 emit_int8((unsigned char)(0xC0 | encode));
6346 int src2_enc = src2->encoding();
6347 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
6348 }
6349
6350
6351 #ifndef _LP64
6352
6353 void Assembler::incl(Register dst) {
6354 // Don't use it directly. Use MacroAssembler::incrementl() instead.
6355 emit_int8(0x40 | dst->encoding());
6356 }
6357
6358 void Assembler::lea(Register dst, Address src) {
6359 leal(dst, src);
6360 }
6361
6362 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
6363 InstructionMark im(this);
6860
6861 void Assembler::andq(Register dst, int32_t imm32) {
6862 (void) prefixq_and_encode(dst->encoding());
6863 emit_arith(0x81, 0xE0, dst, imm32);
6864 }
6865
6866 void Assembler::andq(Register dst, Address src) {
6867 InstructionMark im(this);
6868 prefixq(src, dst);
6869 emit_int8(0x23);
6870 emit_operand(dst, src);
6871 }
6872
6873 void Assembler::andq(Register dst, Register src) {
6874 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6875 emit_arith(0x23, 0xC0, dst, src);
6876 }
6877
6878 void Assembler::andnq(Register dst, Register src1, Register src2) {
6879 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6880 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6881 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
6882 emit_int8((unsigned char)0xF2);
6883 emit_int8((unsigned char)(0xC0 | encode));
6884 }
6885
6886 void Assembler::andnq(Register dst, Register src1, Address src2) {
6887 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6888 InstructionMark im(this);
6889 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6890 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
6891 emit_int8((unsigned char)0xF2);
6892 emit_operand(dst, src2);
6893 }
6894
6895 void Assembler::bsfq(Register dst, Register src) {
6896 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6897 emit_int8(0x0F);
6898 emit_int8((unsigned char)0xBC);
6899 emit_int8((unsigned char)(0xC0 | encode));
6900 }
6901
6902 void Assembler::bsrq(Register dst, Register src) {
6903 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6904 emit_int8(0x0F);
6905 emit_int8((unsigned char)0xBD);
6906 emit_int8((unsigned char)(0xC0 | encode));
6907 }
6908
6909 void Assembler::bswapq(Register reg) {
6910 int encode = prefixq_and_encode(reg->encoding());
6911 emit_int8(0x0F);
6912 emit_int8((unsigned char)(0xC8 | encode));
6913 }
6914
6915 void Assembler::blsiq(Register dst, Register src) {
6916 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6917 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6918 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
6919 emit_int8((unsigned char)0xF3);
6920 emit_int8((unsigned char)(0xC0 | encode));
6921 }
6922
6923 void Assembler::blsiq(Register dst, Address src) {
6924 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6925 InstructionMark im(this);
6926 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6927 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
6928 emit_int8((unsigned char)0xF3);
6929 emit_operand(rbx, src);
6930 }
6931
6932 void Assembler::blsmskq(Register dst, Register src) {
6933 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6934 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6935 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
6936 emit_int8((unsigned char)0xF3);
6937 emit_int8((unsigned char)(0xC0 | encode));
6938 }
6939
6940 void Assembler::blsmskq(Register dst, Address src) {
6941 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6942 InstructionMark im(this);
6943 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6944 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
6945 emit_int8((unsigned char)0xF3);
6946 emit_operand(rdx, src);
6947 }
6948
6949 void Assembler::blsrq(Register dst, Register src) {
6950 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6951 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6952 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
6953 emit_int8((unsigned char)0xF3);
6954 emit_int8((unsigned char)(0xC0 | encode));
6955 }
6956
6957 void Assembler::blsrq(Register dst, Address src) {
6958 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6959 InstructionMark im(this);
6960 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6961 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
6962 emit_int8((unsigned char)0xF3);
6963 emit_operand(rcx, src);
6964 }
6965
6966 void Assembler::cdqq() {
6967 prefix(REX_W);
6968 emit_int8((unsigned char)0x99);
6969 }
6970
6971 void Assembler::clflush(Address adr) {
6972 prefix(adr);
6973 emit_int8(0x0F);
6974 emit_int8((unsigned char)0xAE);
6975 emit_operand(rdi, adr);
6976 }
6977
6978 void Assembler::cmovq(Condition cc, Register dst, Register src) {
6979 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6980 emit_int8(0x0F);
6981 emit_int8(0x40 | cc);
7015 emit_arith(0x3B, 0xC0, dst, src);
7016 }
7017
7018 void Assembler::cmpq(Register dst, Address src) {
7019 InstructionMark im(this);
7020 prefixq(src, dst);
7021 emit_int8(0x3B);
7022 emit_operand(dst, src);
7023 }
7024
7025 void Assembler::cmpxchgq(Register reg, Address adr) {
7026 InstructionMark im(this);
7027 prefixq(adr, reg);
7028 emit_int8(0x0F);
7029 emit_int8((unsigned char)0xB1);
7030 emit_operand(reg, adr);
7031 }
7032
7033 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
7034 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7035 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7036 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7037 emit_int8(0x2A);
7038 emit_int8((unsigned char)(0xC0 | encode));
7039 }
7040
7041 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
7042 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7043 InstructionMark im(this);
7044 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7045 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7046 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7047 emit_int8(0x2A);
7048 emit_operand(dst, src);
7049 }
7050
7051 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
7052 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7053 InstructionMark im(this);
7054 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7055 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7056 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7057 emit_int8(0x2A);
7058 emit_operand(dst, src);
7059 }
7060
7061 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
7062 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7063 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7064 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7065 emit_int8(0x2C);
7066 emit_int8((unsigned char)(0xC0 | encode));
7067 }
7068
7069 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
7070 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7071 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7072 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7073 emit_int8(0x2C);
7074 emit_int8((unsigned char)(0xC0 | encode));
7075 }
7076
7077 void Assembler::decl(Register dst) {
7078 // Don't use it directly. Use MacroAssembler::decrementl() instead.
7079 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
7080 int encode = prefix_and_encode(dst->encoding());
7081 emit_int8((unsigned char)0xFF);
7082 emit_int8((unsigned char)(0xC8 | encode));
7083 }
7084
7085 void Assembler::decq(Register dst) {
7086 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7087 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7088 int encode = prefixq_and_encode(dst->encoding());
7089 emit_int8((unsigned char)0xFF);
7090 emit_int8(0xC8 | encode);
7091 }
7092
7235 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
7236 InstructionMark im(this);
7237 prefix(src1);
7238 emit_int8((unsigned char)0x81);
7239 emit_operand(rax, src1, 4);
7240 emit_data((int)imm32, rspec, narrow_oop_operand);
7241 }
7242
7243 void Assembler::lzcntq(Register dst, Register src) {
7244 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
7245 emit_int8((unsigned char)0xF3);
7246 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7247 emit_int8(0x0F);
7248 emit_int8((unsigned char)0xBD);
7249 emit_int8((unsigned char)(0xC0 | encode));
7250 }
7251
7252 void Assembler::movdq(XMMRegister dst, Register src) {
7253 // table D-1 says MMX/SSE2
7254 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7255 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7256 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7257 emit_int8(0x6E);
7258 emit_int8((unsigned char)(0xC0 | encode));
7259 }
7260
7261 void Assembler::movdq(Register dst, XMMRegister src) {
7262 // table D-1 says MMX/SSE2
7263 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7264 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7265 // swap src/dst to get correct prefix
7266 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7267 emit_int8(0x7E);
7268 emit_int8((unsigned char)(0xC0 | encode));
7269 }
7270
7271 void Assembler::movq(Register dst, Register src) {
7272 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7273 emit_int8((unsigned char)0x8B);
7274 emit_int8((unsigned char)(0xC0 | encode));
7275 }
7276
7277 void Assembler::movq(Register dst, Address src) {
7278 InstructionMark im(this);
7279 prefixq(src, dst);
7280 emit_int8((unsigned char)0x8B);
7281 emit_operand(dst, src);
7282 }
7283
7284 void Assembler::movq(Address dst, Register src) {
7285 InstructionMark im(this);
7286 prefixq(dst, src);
7379 emit_int8((unsigned char)0x0F);
7380 emit_int8((unsigned char)0xB7);
7381 emit_int8((unsigned char)(0xC0 | encode));
7382 }
7383
7384 void Assembler::mulq(Address src) {
7385 InstructionMark im(this);
7386 prefixq(src);
7387 emit_int8((unsigned char)0xF7);
7388 emit_operand(rsp, src);
7389 }
7390
7391 void Assembler::mulq(Register src) {
7392 int encode = prefixq_and_encode(src->encoding());
7393 emit_int8((unsigned char)0xF7);
7394 emit_int8((unsigned char)(0xE0 | encode));
7395 }
7396
7397 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
7398 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
7399 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7400 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
7401 emit_int8((unsigned char)0xF6);
7402 emit_int8((unsigned char)(0xC0 | encode));
7403 }
7404
7405 void Assembler::negq(Register dst) {
7406 int encode = prefixq_and_encode(dst->encoding());
7407 emit_int8((unsigned char)0xF7);
7408 emit_int8((unsigned char)(0xD8 | encode));
7409 }
7410
7411 void Assembler::notq(Register dst) {
7412 int encode = prefixq_and_encode(dst->encoding());
7413 emit_int8((unsigned char)0xF7);
7414 emit_int8((unsigned char)(0xD0 | encode));
7415 }
7416
7417 void Assembler::orq(Address dst, int32_t imm32) {
7418 InstructionMark im(this);
7419 prefixq(dst);
7420 emit_int8((unsigned char)0x81);
7542 emit_int8((unsigned char)(0xD8 | encode));
7543 emit_int8(imm8);
7544 }
7545 }
7546
7547 void Assembler::rorq(Register dst, int imm8) {
7548 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7549 int encode = prefixq_and_encode(dst->encoding());
7550 if (imm8 == 1) {
7551 emit_int8((unsigned char)0xD1);
7552 emit_int8((unsigned char)(0xC8 | encode));
7553 } else {
7554 emit_int8((unsigned char)0xC1);
7555 emit_int8((unsigned char)(0xc8 | encode));
7556 emit_int8(imm8);
7557 }
7558 }
7559
7560 void Assembler::rorxq(Register dst, Register src, int imm8) {
7561 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
7562 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7563 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
7564 emit_int8((unsigned char)0xF0);
7565 emit_int8((unsigned char)(0xC0 | encode));
7566 emit_int8(imm8);
7567 }
7568
7569 void Assembler::sarq(Register dst, int imm8) {
7570 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7571 int encode = prefixq_and_encode(dst->encoding());
7572 if (imm8 == 1) {
7573 emit_int8((unsigned char)0xD1);
7574 emit_int8((unsigned char)(0xF8 | encode));
7575 } else {
7576 emit_int8((unsigned char)0xC1);
7577 emit_int8((unsigned char)(0xF8 | encode));
7578 emit_int8(imm8);
7579 }
7580 }
7581
7582 void Assembler::sarq(Register dst) {
7583 int encode = prefixq_and_encode(dst->encoding());
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