1 /*
   2  * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP
  26 #define CPU_X86_VM_ASSEMBLER_X86_HPP
  27 
  28 #include "asm/register.hpp"
  29 #include "vm_version_x86.hpp"
  30 
  31 class BiasedLockingCounters;
  32 
  33 // Contains all the definitions needed for x86 assembly code generation.
  34 
  35 // Calling convention
  36 class Argument VALUE_OBJ_CLASS_SPEC {
  37  public:
  38   enum {
  39 #ifdef _LP64
  40 #ifdef _WIN64
  41     n_int_register_parameters_c   = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
  42     n_float_register_parameters_c = 4,  // xmm0 - xmm3 (c_farg0, c_farg1, ... )
  43 #else
  44     n_int_register_parameters_c   = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
  45     n_float_register_parameters_c = 8,  // xmm0 - xmm7 (c_farg0, c_farg1, ... )
  46 #endif // _WIN64
  47     n_int_register_parameters_j   = 6, // j_rarg0, j_rarg1, ...
  48     n_float_register_parameters_j = 8  // j_farg0, j_farg1, ...
  49 #else
  50     n_register_parameters = 0   // 0 registers used to pass arguments
  51 #endif // _LP64
  52   };
  53 };
  54 
  55 
  56 #ifdef _LP64
  57 // Symbolically name the register arguments used by the c calling convention.
  58 // Windows is different from linux/solaris. So much for standards...
  59 
  60 #ifdef _WIN64
  61 
  62 REGISTER_DECLARATION(Register, c_rarg0, rcx);
  63 REGISTER_DECLARATION(Register, c_rarg1, rdx);
  64 REGISTER_DECLARATION(Register, c_rarg2, r8);
  65 REGISTER_DECLARATION(Register, c_rarg3, r9);
  66 
  67 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
  68 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
  69 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
  70 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
  71 
  72 #else
  73 
  74 REGISTER_DECLARATION(Register, c_rarg0, rdi);
  75 REGISTER_DECLARATION(Register, c_rarg1, rsi);
  76 REGISTER_DECLARATION(Register, c_rarg2, rdx);
  77 REGISTER_DECLARATION(Register, c_rarg3, rcx);
  78 REGISTER_DECLARATION(Register, c_rarg4, r8);
  79 REGISTER_DECLARATION(Register, c_rarg5, r9);
  80 
  81 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
  82 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
  83 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
  84 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
  85 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
  86 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
  87 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
  88 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
  89 
  90 #endif // _WIN64
  91 
  92 // Symbolically name the register arguments used by the Java calling convention.
  93 // We have control over the convention for java so we can do what we please.
  94 // What pleases us is to offset the java calling convention so that when
  95 // we call a suitable jni method the arguments are lined up and we don't
  96 // have to do little shuffling. A suitable jni method is non-static and a
  97 // small number of arguments (two fewer args on windows)
  98 //
  99 //        |-------------------------------------------------------|
 100 //        | c_rarg0   c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5    |
 101 //        |-------------------------------------------------------|
 102 //        | rcx       rdx      r8      r9      rdi*    rsi*       | windows (* not a c_rarg)
 103 //        | rdi       rsi      rdx     rcx     r8      r9         | solaris/linux
 104 //        |-------------------------------------------------------|
 105 //        | j_rarg5   j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4    |
 106 //        |-------------------------------------------------------|
 107 
 108 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
 109 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
 110 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
 111 // Windows runs out of register args here
 112 #ifdef _WIN64
 113 REGISTER_DECLARATION(Register, j_rarg3, rdi);
 114 REGISTER_DECLARATION(Register, j_rarg4, rsi);
 115 #else
 116 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
 117 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
 118 #endif /* _WIN64 */
 119 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
 120 
 121 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
 122 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
 123 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
 124 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
 125 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
 126 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
 127 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
 128 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
 129 
 130 REGISTER_DECLARATION(Register, rscratch1, r10);  // volatile
 131 REGISTER_DECLARATION(Register, rscratch2, r11);  // volatile
 132 
 133 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
 134 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
 135 
 136 #else
 137 // rscratch1 will apear in 32bit code that is dead but of course must compile
 138 // Using noreg ensures if the dead code is incorrectly live and executed it
 139 // will cause an assertion failure
 140 #define rscratch1 noreg
 141 #define rscratch2 noreg
 142 
 143 #endif // _LP64
 144 
 145 // JSR 292
 146 // On x86, the SP does not have to be saved when invoking method handle intrinsics
 147 // or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg.
 148 REGISTER_DECLARATION(Register, rbp_mh_SP_save, noreg);
 149 
 150 // Address is an abstraction used to represent a memory location
 151 // using any of the amd64 addressing modes with one object.
 152 //
 153 // Note: A register location is represented via a Register, not
 154 //       via an address for efficiency & simplicity reasons.
 155 
 156 class ArrayAddress;
 157 
 158 class Address VALUE_OBJ_CLASS_SPEC {
 159  public:
 160   enum ScaleFactor {
 161     no_scale = -1,
 162     times_1  =  0,
 163     times_2  =  1,
 164     times_4  =  2,
 165     times_8  =  3,
 166     times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
 167   };
 168   static ScaleFactor times(int size) {
 169     assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
 170     if (size == 8)  return times_8;
 171     if (size == 4)  return times_4;
 172     if (size == 2)  return times_2;
 173     return times_1;
 174   }
 175   static int scale_size(ScaleFactor scale) {
 176     assert(scale != no_scale, "");
 177     assert(((1 << (int)times_1) == 1 &&
 178             (1 << (int)times_2) == 2 &&
 179             (1 << (int)times_4) == 4 &&
 180             (1 << (int)times_8) == 8), "");
 181     return (1 << (int)scale);
 182   }
 183 
 184  private:
 185   Register         _base;
 186   Register         _index;
 187   ScaleFactor      _scale;
 188   int              _disp;
 189   RelocationHolder _rspec;
 190 
 191   // Easily misused constructors make them private
 192   // %%% can we make these go away?
 193   NOT_LP64(Address(address loc, RelocationHolder spec);)
 194   Address(int disp, address loc, relocInfo::relocType rtype);
 195   Address(int disp, address loc, RelocationHolder spec);
 196 
 197  public:
 198 
 199  int disp() { return _disp; }
 200   // creation
 201   Address()
 202     : _base(noreg),
 203       _index(noreg),
 204       _scale(no_scale),
 205       _disp(0) {
 206   }
 207 
 208   // No default displacement otherwise Register can be implicitly
 209   // converted to 0(Register) which is quite a different animal.
 210 
 211   Address(Register base, int disp)
 212     : _base(base),
 213       _index(noreg),
 214       _scale(no_scale),
 215       _disp(disp) {
 216   }
 217 
 218   Address(Register base, Register index, ScaleFactor scale, int disp = 0)
 219     : _base (base),
 220       _index(index),
 221       _scale(scale),
 222       _disp (disp) {
 223     assert(!index->is_valid() == (scale == Address::no_scale),
 224            "inconsistent address");
 225   }
 226 
 227   Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
 228     : _base (base),
 229       _index(index.register_or_noreg()),
 230       _scale(scale),
 231       _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
 232     if (!index.is_register())  scale = Address::no_scale;
 233     assert(!_index->is_valid() == (scale == Address::no_scale),
 234            "inconsistent address");
 235   }
 236 
 237   Address plus_disp(int disp) const {
 238     Address a = (*this);
 239     a._disp += disp;
 240     return a;
 241   }
 242   Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
 243     Address a = (*this);
 244     a._disp += disp.constant_or_zero() * scale_size(scale);
 245     if (disp.is_register()) {
 246       assert(!a.index()->is_valid(), "competing indexes");
 247       a._index = disp.as_register();
 248       a._scale = scale;
 249     }
 250     return a;
 251   }
 252   bool is_same_address(Address a) const {
 253     // disregard _rspec
 254     return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
 255   }
 256 
 257   // The following two overloads are used in connection with the
 258   // ByteSize type (see sizes.hpp).  They simplify the use of
 259   // ByteSize'd arguments in assembly code. Note that their equivalent
 260   // for the optimized build are the member functions with int disp
 261   // argument since ByteSize is mapped to an int type in that case.
 262   //
 263   // Note: DO NOT introduce similar overloaded functions for WordSize
 264   // arguments as in the optimized mode, both ByteSize and WordSize
 265   // are mapped to the same type and thus the compiler cannot make a
 266   // distinction anymore (=> compiler errors).
 267 
 268 #ifdef ASSERT
 269   Address(Register base, ByteSize disp)
 270     : _base(base),
 271       _index(noreg),
 272       _scale(no_scale),
 273       _disp(in_bytes(disp)) {
 274   }
 275 
 276   Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
 277     : _base(base),
 278       _index(index),
 279       _scale(scale),
 280       _disp(in_bytes(disp)) {
 281     assert(!index->is_valid() == (scale == Address::no_scale),
 282            "inconsistent address");
 283   }
 284 
 285   Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
 286     : _base (base),
 287       _index(index.register_or_noreg()),
 288       _scale(scale),
 289       _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
 290     if (!index.is_register())  scale = Address::no_scale;
 291     assert(!_index->is_valid() == (scale == Address::no_scale),
 292            "inconsistent address");
 293   }
 294 
 295 #endif // ASSERT
 296 
 297   // accessors
 298   bool        uses(Register reg) const { return _base == reg || _index == reg; }
 299   Register    base()             const { return _base;  }
 300   Register    index()            const { return _index; }
 301   ScaleFactor scale()            const { return _scale; }
 302   int         disp()             const { return _disp;  }
 303 
 304   // Convert the raw encoding form into the form expected by the constructor for
 305   // Address.  An index of 4 (rsp) corresponds to having no index, so convert
 306   // that to noreg for the Address constructor.
 307   static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
 308 
 309   static Address make_array(ArrayAddress);
 310 
 311  private:
 312   bool base_needs_rex() const {
 313     return _base != noreg && _base->encoding() >= 8;
 314   }
 315 
 316   bool index_needs_rex() const {
 317     return _index != noreg &&_index->encoding() >= 8;
 318   }
 319 
 320   relocInfo::relocType reloc() const { return _rspec.type(); }
 321 
 322   friend class Assembler;
 323   friend class MacroAssembler;
 324   friend class LIR_Assembler; // base/index/scale/disp
 325 };
 326 
 327 //
 328 // AddressLiteral has been split out from Address because operands of this type
 329 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
 330 // the few instructions that need to deal with address literals are unique and the
 331 // MacroAssembler does not have to implement every instruction in the Assembler
 332 // in order to search for address literals that may need special handling depending
 333 // on the instruction and the platform. As small step on the way to merging i486/amd64
 334 // directories.
 335 //
 336 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
 337   friend class ArrayAddress;
 338   RelocationHolder _rspec;
 339   // Typically we use AddressLiterals we want to use their rval
 340   // However in some situations we want the lval (effect address) of the item.
 341   // We provide a special factory for making those lvals.
 342   bool _is_lval;
 343 
 344   // If the target is far we'll need to load the ea of this to
 345   // a register to reach it. Otherwise if near we can do rip
 346   // relative addressing.
 347 
 348   address          _target;
 349 
 350  protected:
 351   // creation
 352   AddressLiteral()
 353     : _is_lval(false),
 354       _target(NULL)
 355   {}
 356 
 357   public:
 358 
 359 
 360   AddressLiteral(address target, relocInfo::relocType rtype);
 361 
 362   AddressLiteral(address target, RelocationHolder const& rspec)
 363     : _rspec(rspec),
 364       _is_lval(false),
 365       _target(target)
 366   {}
 367 
 368   AddressLiteral addr() {
 369     AddressLiteral ret = *this;
 370     ret._is_lval = true;
 371     return ret;
 372   }
 373 
 374 
 375  private:
 376 
 377   address target() { return _target; }
 378   bool is_lval() { return _is_lval; }
 379 
 380   relocInfo::relocType reloc() const { return _rspec.type(); }
 381   const RelocationHolder& rspec() const { return _rspec; }
 382 
 383   friend class Assembler;
 384   friend class MacroAssembler;
 385   friend class Address;
 386   friend class LIR_Assembler;
 387 };
 388 
 389 // Convience classes
 390 class RuntimeAddress: public AddressLiteral {
 391 
 392   public:
 393 
 394   RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
 395 
 396 };
 397 
 398 class ExternalAddress: public AddressLiteral {
 399  private:
 400   static relocInfo::relocType reloc_for_target(address target) {
 401     // Sometimes ExternalAddress is used for values which aren't
 402     // exactly addresses, like the card table base.
 403     // external_word_type can't be used for values in the first page
 404     // so just skip the reloc in that case.
 405     return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
 406   }
 407 
 408  public:
 409 
 410   ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
 411 
 412 };
 413 
 414 class InternalAddress: public AddressLiteral {
 415 
 416   public:
 417 
 418   InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
 419 
 420 };
 421 
 422 // x86 can do array addressing as a single operation since disp can be an absolute
 423 // address amd64 can't. We create a class that expresses the concept but does extra
 424 // magic on amd64 to get the final result
 425 
 426 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
 427   private:
 428 
 429   AddressLiteral _base;
 430   Address        _index;
 431 
 432   public:
 433 
 434   ArrayAddress() {};
 435   ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
 436   AddressLiteral base() { return _base; }
 437   Address index() { return _index; }
 438 
 439 };
 440 
 441 class InstructionAttr;
 442 
 443 // 64-bit refect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes
 444 // See fxsave and xsave(EVEX enabled) documentation for layout
 445 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY(2688 / wordSize);
 446 
 447 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
 448 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
 449 // is what you get. The Assembler is generating code into a CodeBuffer.
 450 
 451 class Assembler : public AbstractAssembler  {
 452   friend class AbstractAssembler; // for the non-virtual hack
 453   friend class LIR_Assembler; // as_Address()
 454   friend class StubGenerator;
 455 
 456  public:
 457   enum Condition {                     // The x86 condition codes used for conditional jumps/moves.
 458     zero          = 0x4,
 459     notZero       = 0x5,
 460     equal         = 0x4,
 461     notEqual      = 0x5,
 462     less          = 0xc,
 463     lessEqual     = 0xe,
 464     greater       = 0xf,
 465     greaterEqual  = 0xd,
 466     below         = 0x2,
 467     belowEqual    = 0x6,
 468     above         = 0x7,
 469     aboveEqual    = 0x3,
 470     overflow      = 0x0,
 471     noOverflow    = 0x1,
 472     carrySet      = 0x2,
 473     carryClear    = 0x3,
 474     negative      = 0x8,
 475     positive      = 0x9,
 476     parity        = 0xa,
 477     noParity      = 0xb
 478   };
 479 
 480   enum Prefix {
 481     // segment overrides
 482     CS_segment = 0x2e,
 483     SS_segment = 0x36,
 484     DS_segment = 0x3e,
 485     ES_segment = 0x26,
 486     FS_segment = 0x64,
 487     GS_segment = 0x65,
 488 
 489     REX        = 0x40,
 490 
 491     REX_B      = 0x41,
 492     REX_X      = 0x42,
 493     REX_XB     = 0x43,
 494     REX_R      = 0x44,
 495     REX_RB     = 0x45,
 496     REX_RX     = 0x46,
 497     REX_RXB    = 0x47,
 498 
 499     REX_W      = 0x48,
 500 
 501     REX_WB     = 0x49,
 502     REX_WX     = 0x4A,
 503     REX_WXB    = 0x4B,
 504     REX_WR     = 0x4C,
 505     REX_WRB    = 0x4D,
 506     REX_WRX    = 0x4E,
 507     REX_WRXB   = 0x4F,
 508 
 509     VEX_3bytes = 0xC4,
 510     VEX_2bytes = 0xC5,
 511     EVEX_4bytes = 0x62,
 512     Prefix_EMPTY = 0x0
 513   };
 514 
 515   enum VexPrefix {
 516     VEX_B = 0x20,
 517     VEX_X = 0x40,
 518     VEX_R = 0x80,
 519     VEX_W = 0x80
 520   };
 521 
 522   enum ExexPrefix {
 523     EVEX_F  = 0x04,
 524     EVEX_V  = 0x08,
 525     EVEX_Rb = 0x10,
 526     EVEX_X  = 0x40,
 527     EVEX_Z  = 0x80
 528   };
 529 
 530   enum VexSimdPrefix {
 531     VEX_SIMD_NONE = 0x0,
 532     VEX_SIMD_66   = 0x1,
 533     VEX_SIMD_F3   = 0x2,
 534     VEX_SIMD_F2   = 0x3
 535   };
 536 
 537   enum VexOpcode {
 538     VEX_OPCODE_NONE  = 0x0,
 539     VEX_OPCODE_0F    = 0x1,
 540     VEX_OPCODE_0F_38 = 0x2,
 541     VEX_OPCODE_0F_3A = 0x3,
 542     VEX_OPCODE_MASK  = 0x1F
 543   };
 544 
 545   enum AvxVectorLen {
 546     AVX_128bit = 0x0,
 547     AVX_256bit = 0x1,
 548     AVX_512bit = 0x2,
 549     AVX_NoVec  = 0x4
 550   };
 551 
 552   enum EvexTupleType {
 553     EVEX_FV   = 0,
 554     EVEX_HV   = 4,
 555     EVEX_FVM  = 6,
 556     EVEX_T1S  = 7,
 557     EVEX_T1F  = 11,
 558     EVEX_T2   = 13,
 559     EVEX_T4   = 15,
 560     EVEX_T8   = 17,
 561     EVEX_HVM  = 18,
 562     EVEX_QVM  = 19,
 563     EVEX_OVM  = 20,
 564     EVEX_M128 = 21,
 565     EVEX_DUP  = 22,
 566     EVEX_ETUP = 23
 567   };
 568 
 569   enum EvexInputSizeInBits {
 570     EVEX_8bit  = 0,
 571     EVEX_16bit = 1,
 572     EVEX_32bit = 2,
 573     EVEX_64bit = 3,
 574     EVEX_NObit = 4
 575   };
 576 
 577   enum WhichOperand {
 578     // input to locate_operand, and format code for relocations
 579     imm_operand  = 0,            // embedded 32-bit|64-bit immediate operand
 580     disp32_operand = 1,          // embedded 32-bit displacement or address
 581     call32_operand = 2,          // embedded 32-bit self-relative displacement
 582 #ifndef _LP64
 583     _WhichOperand_limit = 3
 584 #else
 585      narrow_oop_operand = 3,     // embedded 32-bit immediate narrow oop
 586     _WhichOperand_limit = 4
 587 #endif
 588   };
 589 
 590 
 591 
 592   // NOTE: The general philopsophy of the declarations here is that 64bit versions
 593   // of instructions are freely declared without the need for wrapping them an ifdef.
 594   // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
 595   // In the .cpp file the implementations are wrapped so that they are dropped out
 596   // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL
 597   // to the size it was prior to merging up the 32bit and 64bit assemblers.
 598   //
 599   // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
 600   // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
 601 
 602 private:
 603 
 604   bool _legacy_mode_bw;
 605   bool _legacy_mode_dq;
 606   bool _legacy_mode_vl;
 607   bool _legacy_mode_vlbw;
 608 
 609   class InstructionAttr *_attributes;
 610 
 611   // 64bit prefixes
 612   int prefix_and_encode(int reg_enc, bool byteinst = false);
 613   int prefixq_and_encode(int reg_enc);
 614 
 615   int prefix_and_encode(int dst_enc, int src_enc) {
 616     return prefix_and_encode(dst_enc, false, src_enc, false);
 617   }
 618   int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte);
 619   int prefixq_and_encode(int dst_enc, int src_enc);
 620 
 621   void prefix(Register reg);
 622   void prefix(Register dst, Register src, Prefix p);
 623   void prefix(Register dst, Address adr, Prefix p);
 624   void prefix(Address adr);
 625   void prefixq(Address adr);
 626 
 627   void prefix(Address adr, Register reg,  bool byteinst = false);
 628   void prefix(Address adr, XMMRegister reg);
 629   void prefixq(Address adr, Register reg);
 630   void prefixq(Address adr, XMMRegister reg);
 631 
 632   void prefetch_prefix(Address src);
 633 
 634   void rex_prefix(Address adr, XMMRegister xreg,
 635                   VexSimdPrefix pre, VexOpcode opc, bool rex_w);
 636   int  rex_prefix_and_encode(int dst_enc, int src_enc,
 637                              VexSimdPrefix pre, VexOpcode opc, bool rex_w);
 638 
 639   void vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc);
 640 
 641   void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v,
 642                    int nds_enc, VexSimdPrefix pre, VexOpcode opc);
 643 
 644   void vex_prefix(Address adr, int nds_enc, int xreg_enc,
 645                   VexSimdPrefix pre, VexOpcode opc,
 646                   InstructionAttr *attributes);
 647 
 648   int  vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
 649                              VexSimdPrefix pre, VexOpcode opc,
 650                              InstructionAttr *attributes);
 651 
 652   void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
 653                    VexOpcode opc, InstructionAttr *attributes);
 654 
 655   int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
 656                              VexOpcode opc, InstructionAttr *attributes);
 657 
 658   int kreg_prefix_and_encode(KRegister dst, KRegister nds, KRegister src, VexSimdPrefix pre,
 659                              VexOpcode opc, InstructionAttr *attributes);
 660 
 661   int kreg_prefix_and_encode(KRegister dst, KRegister nds, Register src, VexSimdPrefix pre,
 662                              VexOpcode opc, InstructionAttr *attributes);
 663 
 664   // Helper functions for groups of instructions
 665   void emit_arith_b(int op1, int op2, Register dst, int imm8);
 666 
 667   void emit_arith(int op1, int op2, Register dst, int32_t imm32);
 668   // Force generation of a 4 byte immediate value even if it fits into 8bit
 669   void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
 670   void emit_arith(int op1, int op2, Register dst, Register src);
 671 
 672   bool emit_compressed_disp_byte(int &disp);
 673 
 674   void emit_operand(Register reg,
 675                     Register base, Register index, Address::ScaleFactor scale,
 676                     int disp,
 677                     RelocationHolder const& rspec,
 678                     int rip_relative_correction = 0);
 679 
 680   void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
 681 
 682   // operands that only take the original 32bit registers
 683   void emit_operand32(Register reg, Address adr);
 684 
 685   void emit_operand(XMMRegister reg,
 686                     Register base, Register index, Address::ScaleFactor scale,
 687                     int disp,
 688                     RelocationHolder const& rspec);
 689 
 690   void emit_operand(XMMRegister reg, Address adr);
 691 
 692   void emit_operand(MMXRegister reg, Address adr);
 693 
 694   // workaround gcc (3.2.1-7) bug
 695   void emit_operand(Address adr, MMXRegister reg);
 696 
 697 
 698   // Immediate-to-memory forms
 699   void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
 700 
 701   void emit_farith(int b1, int b2, int i);
 702 
 703 
 704  protected:
 705   #ifdef ASSERT
 706   void check_relocation(RelocationHolder const& rspec, int format);
 707   #endif
 708 
 709   void emit_data(jint data, relocInfo::relocType    rtype, int format);
 710   void emit_data(jint data, RelocationHolder const& rspec, int format);
 711   void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
 712   void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
 713 
 714   bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
 715 
 716   // These are all easily abused and hence protected
 717 
 718   // 32BIT ONLY SECTION
 719 #ifndef _LP64
 720   // Make these disappear in 64bit mode since they would never be correct
 721   void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);   // 32BIT ONLY
 722   void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 723 
 724   void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 725   void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);     // 32BIT ONLY
 726 
 727   void push_literal32(int32_t imm32, RelocationHolder const& rspec);                 // 32BIT ONLY
 728 #else
 729   // 64BIT ONLY SECTION
 730   void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec);   // 64BIT ONLY
 731 
 732   void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
 733   void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
 734 
 735   void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
 736   void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
 737 #endif // _LP64
 738 
 739   // These are unique in that we are ensured by the caller that the 32bit
 740   // relative in these instructions will always be able to reach the potentially
 741   // 64bit address described by entry. Since they can take a 64bit address they
 742   // don't have the 32 suffix like the other instructions in this class.
 743 
 744   void call_literal(address entry, RelocationHolder const& rspec);
 745   void jmp_literal(address entry, RelocationHolder const& rspec);
 746 
 747   // Avoid using directly section
 748   // Instructions in this section are actually usable by anyone without danger
 749   // of failure but have performance issues that are addressed my enhanced
 750   // instructions which will do the proper thing base on the particular cpu.
 751   // We protect them because we don't trust you...
 752 
 753   // Don't use next inc() and dec() methods directly. INC & DEC instructions
 754   // could cause a partial flag stall since they don't set CF flag.
 755   // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
 756   // which call inc() & dec() or add() & sub() in accordance with
 757   // the product flag UseIncDec value.
 758 
 759   void decl(Register dst);
 760   void decl(Address dst);
 761   void decq(Register dst);
 762   void decq(Address dst);
 763 
 764   void incl(Register dst);
 765   void incl(Address dst);
 766   void incq(Register dst);
 767   void incq(Address dst);
 768 
 769   // New cpus require use of movsd and movss to avoid partial register stall
 770   // when loading from memory. But for old Opteron use movlpd instead of movsd.
 771   // The selection is done in MacroAssembler::movdbl() and movflt().
 772 
 773   // Move Scalar Single-Precision Floating-Point Values
 774   void movss(XMMRegister dst, Address src);
 775   void movss(XMMRegister dst, XMMRegister src);
 776   void movss(Address dst, XMMRegister src);
 777 
 778   // Move Scalar Double-Precision Floating-Point Values
 779   void movsd(XMMRegister dst, Address src);
 780   void movsd(XMMRegister dst, XMMRegister src);
 781   void movsd(Address dst, XMMRegister src);
 782   void movlpd(XMMRegister dst, Address src);
 783 
 784   // New cpus require use of movaps and movapd to avoid partial register stall
 785   // when moving between registers.
 786   void movaps(XMMRegister dst, XMMRegister src);
 787   void movapd(XMMRegister dst, XMMRegister src);
 788 
 789   // End avoid using directly
 790 
 791 
 792   // Instruction prefixes
 793   void prefix(Prefix p);
 794 
 795   public:
 796 
 797   // Creation
 798   Assembler(CodeBuffer* code) : AbstractAssembler(code) {
 799     init_attributes();
 800   }
 801 
 802   // Decoding
 803   static address locate_operand(address inst, WhichOperand which);
 804   static address locate_next_instruction(address inst);
 805 
 806   // Utilities
 807   static bool is_polling_page_far() NOT_LP64({ return false;});
 808   static bool query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
 809                                          int cur_tuple_type, int in_size_in_bits, int cur_encoding);
 810 
 811   // Generic instructions
 812   // Does 32bit or 64bit as needed for the platform. In some sense these
 813   // belong in macro assembler but there is no need for both varieties to exist
 814 
 815   void init_attributes(void) {
 816     _legacy_mode_bw = (VM_Version::supports_avx512bw() == false);
 817     _legacy_mode_dq = (VM_Version::supports_avx512dq() == false);
 818     _legacy_mode_vl = (VM_Version::supports_avx512vl() == false);
 819     _legacy_mode_vlbw = (VM_Version::supports_avx512vlbw() == false);
 820     _attributes = NULL;
 821   }
 822 
 823   void set_attributes(InstructionAttr *attributes) { _attributes = attributes; }
 824   void clear_attributes(void) { _attributes = NULL; }
 825 
 826   void lea(Register dst, Address src);
 827 
 828   void mov(Register dst, Register src);
 829 
 830   void pusha();
 831   void popa();
 832 
 833   void pushf();
 834   void popf();
 835 
 836   void push(int32_t imm32);
 837 
 838   void push(Register src);
 839 
 840   void pop(Register dst);
 841 
 842   // These are dummies to prevent surprise implicit conversions to Register
 843   void push(void* v);
 844   void pop(void* v);
 845 
 846   // These do register sized moves/scans
 847   void rep_mov();
 848   void rep_stos();
 849   void rep_stosb();
 850   void repne_scan();
 851 #ifdef _LP64
 852   void repne_scanl();
 853 #endif
 854 
 855   // Vanilla instructions in lexical order
 856 
 857   void adcl(Address dst, int32_t imm32);
 858   void adcl(Address dst, Register src);
 859   void adcl(Register dst, int32_t imm32);
 860   void adcl(Register dst, Address src);
 861   void adcl(Register dst, Register src);
 862 
 863   void adcq(Register dst, int32_t imm32);
 864   void adcq(Register dst, Address src);
 865   void adcq(Register dst, Register src);
 866 
 867   void addl(Address dst, int32_t imm32);
 868   void addl(Address dst, Register src);
 869   void addl(Register dst, int32_t imm32);
 870   void addl(Register dst, Address src);
 871   void addl(Register dst, Register src);
 872 
 873   void addq(Address dst, int32_t imm32);
 874   void addq(Address dst, Register src);
 875   void addq(Register dst, int32_t imm32);
 876   void addq(Register dst, Address src);
 877   void addq(Register dst, Register src);
 878 
 879 #ifdef _LP64
 880  //Add Unsigned Integers with Carry Flag
 881   void adcxq(Register dst, Register src);
 882 
 883  //Add Unsigned Integers with Overflow Flag
 884   void adoxq(Register dst, Register src);
 885 #endif
 886 
 887   void addr_nop_4();
 888   void addr_nop_5();
 889   void addr_nop_7();
 890   void addr_nop_8();
 891 
 892   // Add Scalar Double-Precision Floating-Point Values
 893   void addsd(XMMRegister dst, Address src);
 894   void addsd(XMMRegister dst, XMMRegister src);
 895 
 896   // Add Scalar Single-Precision Floating-Point Values
 897   void addss(XMMRegister dst, Address src);
 898   void addss(XMMRegister dst, XMMRegister src);
 899 
 900   // AES instructions
 901   void aesdec(XMMRegister dst, Address src);
 902   void aesdec(XMMRegister dst, XMMRegister src);
 903   void aesdeclast(XMMRegister dst, Address src);
 904   void aesdeclast(XMMRegister dst, XMMRegister src);
 905   void aesenc(XMMRegister dst, Address src);
 906   void aesenc(XMMRegister dst, XMMRegister src);
 907   void aesenclast(XMMRegister dst, Address src);
 908   void aesenclast(XMMRegister dst, XMMRegister src);
 909 
 910 
 911   void andl(Address  dst, int32_t imm32);
 912   void andl(Register dst, int32_t imm32);
 913   void andl(Register dst, Address src);
 914   void andl(Register dst, Register src);
 915 
 916   void andq(Address  dst, int32_t imm32);
 917   void andq(Register dst, int32_t imm32);
 918   void andq(Register dst, Address src);
 919   void andq(Register dst, Register src);
 920 
 921   // BMI instructions
 922   void andnl(Register dst, Register src1, Register src2);
 923   void andnl(Register dst, Register src1, Address src2);
 924   void andnq(Register dst, Register src1, Register src2);
 925   void andnq(Register dst, Register src1, Address src2);
 926 
 927   void blsil(Register dst, Register src);
 928   void blsil(Register dst, Address src);
 929   void blsiq(Register dst, Register src);
 930   void blsiq(Register dst, Address src);
 931 
 932   void blsmskl(Register dst, Register src);
 933   void blsmskl(Register dst, Address src);
 934   void blsmskq(Register dst, Register src);
 935   void blsmskq(Register dst, Address src);
 936 
 937   void blsrl(Register dst, Register src);
 938   void blsrl(Register dst, Address src);
 939   void blsrq(Register dst, Register src);
 940   void blsrq(Register dst, Address src);
 941 
 942   void bsfl(Register dst, Register src);
 943   void bsrl(Register dst, Register src);
 944 
 945 #ifdef _LP64
 946   void bsfq(Register dst, Register src);
 947   void bsrq(Register dst, Register src);
 948 #endif
 949 
 950   void bswapl(Register reg);
 951 
 952   void bswapq(Register reg);
 953 
 954   void call(Label& L, relocInfo::relocType rtype);
 955   void call(Register reg);  // push pc; pc <- reg
 956   void call(Address adr);   // push pc; pc <- adr
 957 
 958   void cdql();
 959 
 960   void cdqq();
 961 
 962   void cld();
 963 
 964   void clflush(Address adr);
 965 
 966   void cmovl(Condition cc, Register dst, Register src);
 967   void cmovl(Condition cc, Register dst, Address src);
 968 
 969   void cmovq(Condition cc, Register dst, Register src);
 970   void cmovq(Condition cc, Register dst, Address src);
 971 
 972 
 973   void cmpb(Address dst, int imm8);
 974 
 975   void cmpl(Address dst, int32_t imm32);
 976 
 977   void cmpl(Register dst, int32_t imm32);
 978   void cmpl(Register dst, Register src);
 979   void cmpl(Register dst, Address src);
 980 
 981   void cmpq(Address dst, int32_t imm32);
 982   void cmpq(Address dst, Register src);
 983 
 984   void cmpq(Register dst, int32_t imm32);
 985   void cmpq(Register dst, Register src);
 986   void cmpq(Register dst, Address src);
 987 
 988   // these are dummies used to catch attempting to convert NULL to Register
 989   void cmpl(Register dst, void* junk); // dummy
 990   void cmpq(Register dst, void* junk); // dummy
 991 
 992   void cmpw(Address dst, int imm16);
 993 
 994   void cmpxchg8 (Address adr);
 995 
 996   void cmpxchgb(Register reg, Address adr);
 997   void cmpxchgl(Register reg, Address adr);
 998 
 999   void cmpxchgq(Register reg, Address adr);
1000 
1001   // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1002   void comisd(XMMRegister dst, Address src);
1003   void comisd(XMMRegister dst, XMMRegister src);
1004 
1005   // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1006   void comiss(XMMRegister dst, Address src);
1007   void comiss(XMMRegister dst, XMMRegister src);
1008 
1009   // Identify processor type and features
1010   void cpuid();
1011 
1012   // CRC32C
1013   void crc32(Register crc, Register v, int8_t sizeInBytes);
1014   void crc32(Register crc, Address adr, int8_t sizeInBytes);
1015 
1016   // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
1017   void cvtsd2ss(XMMRegister dst, XMMRegister src);
1018   void cvtsd2ss(XMMRegister dst, Address src);
1019 
1020   // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
1021   void cvtsi2sdl(XMMRegister dst, Register src);
1022   void cvtsi2sdl(XMMRegister dst, Address src);
1023   void cvtsi2sdq(XMMRegister dst, Register src);
1024   void cvtsi2sdq(XMMRegister dst, Address src);
1025 
1026   // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
1027   void cvtsi2ssl(XMMRegister dst, Register src);
1028   void cvtsi2ssl(XMMRegister dst, Address src);
1029   void cvtsi2ssq(XMMRegister dst, Register src);
1030   void cvtsi2ssq(XMMRegister dst, Address src);
1031 
1032   // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
1033   void cvtdq2pd(XMMRegister dst, XMMRegister src);
1034 
1035   // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
1036   void cvtdq2ps(XMMRegister dst, XMMRegister src);
1037 
1038   // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
1039   void cvtss2sd(XMMRegister dst, XMMRegister src);
1040   void cvtss2sd(XMMRegister dst, Address src);
1041 
1042   // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
1043   void cvttsd2sil(Register dst, Address src);
1044   void cvttsd2sil(Register dst, XMMRegister src);
1045   void cvttsd2siq(Register dst, XMMRegister src);
1046 
1047   // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
1048   void cvttss2sil(Register dst, XMMRegister src);
1049   void cvttss2siq(Register dst, XMMRegister src);
1050 
1051   // Divide Scalar Double-Precision Floating-Point Values
1052   void divsd(XMMRegister dst, Address src);
1053   void divsd(XMMRegister dst, XMMRegister src);
1054 
1055   // Divide Scalar Single-Precision Floating-Point Values
1056   void divss(XMMRegister dst, Address src);
1057   void divss(XMMRegister dst, XMMRegister src);
1058 
1059   void emms();
1060 
1061   void fabs();
1062 
1063   void fadd(int i);
1064 
1065   void fadd_d(Address src);
1066   void fadd_s(Address src);
1067 
1068   // "Alternate" versions of x87 instructions place result down in FPU
1069   // stack instead of on TOS
1070 
1071   void fadda(int i); // "alternate" fadd
1072   void faddp(int i = 1);
1073 
1074   void fchs();
1075 
1076   void fcom(int i);
1077 
1078   void fcomp(int i = 1);
1079   void fcomp_d(Address src);
1080   void fcomp_s(Address src);
1081 
1082   void fcompp();
1083 
1084   void fcos();
1085 
1086   void fdecstp();
1087 
1088   void fdiv(int i);
1089   void fdiv_d(Address src);
1090   void fdivr_s(Address src);
1091   void fdiva(int i);  // "alternate" fdiv
1092   void fdivp(int i = 1);
1093 
1094   void fdivr(int i);
1095   void fdivr_d(Address src);
1096   void fdiv_s(Address src);
1097 
1098   void fdivra(int i); // "alternate" reversed fdiv
1099 
1100   void fdivrp(int i = 1);
1101 
1102   void ffree(int i = 0);
1103 
1104   void fild_d(Address adr);
1105   void fild_s(Address adr);
1106 
1107   void fincstp();
1108 
1109   void finit();
1110 
1111   void fist_s (Address adr);
1112   void fistp_d(Address adr);
1113   void fistp_s(Address adr);
1114 
1115   void fld1();
1116 
1117   void fld_d(Address adr);
1118   void fld_s(Address adr);
1119   void fld_s(int index);
1120   void fld_x(Address adr);  // extended-precision (80-bit) format
1121 
1122   void fldcw(Address src);
1123 
1124   void fldenv(Address src);
1125 
1126   void fldlg2();
1127 
1128   void fldln2();
1129 
1130   void fldz();
1131 
1132   void flog();
1133   void flog10();
1134 
1135   void fmul(int i);
1136 
1137   void fmul_d(Address src);
1138   void fmul_s(Address src);
1139 
1140   void fmula(int i);  // "alternate" fmul
1141 
1142   void fmulp(int i = 1);
1143 
1144   void fnsave(Address dst);
1145 
1146   void fnstcw(Address src);
1147 
1148   void fnstsw_ax();
1149 
1150   void fprem();
1151   void fprem1();
1152 
1153   void frstor(Address src);
1154 
1155   void fsin();
1156 
1157   void fsqrt();
1158 
1159   void fst_d(Address adr);
1160   void fst_s(Address adr);
1161 
1162   void fstp_d(Address adr);
1163   void fstp_d(int index);
1164   void fstp_s(Address adr);
1165   void fstp_x(Address adr); // extended-precision (80-bit) format
1166 
1167   void fsub(int i);
1168   void fsub_d(Address src);
1169   void fsub_s(Address src);
1170 
1171   void fsuba(int i);  // "alternate" fsub
1172 
1173   void fsubp(int i = 1);
1174 
1175   void fsubr(int i);
1176   void fsubr_d(Address src);
1177   void fsubr_s(Address src);
1178 
1179   void fsubra(int i); // "alternate" reversed fsub
1180 
1181   void fsubrp(int i = 1);
1182 
1183   void ftan();
1184 
1185   void ftst();
1186 
1187   void fucomi(int i = 1);
1188   void fucomip(int i = 1);
1189 
1190   void fwait();
1191 
1192   void fxch(int i = 1);
1193 
1194   void fxrstor(Address src);
1195   void xrstor(Address src);
1196 
1197   void fxsave(Address dst);
1198   void xsave(Address dst);
1199 
1200   void fyl2x();
1201   void frndint();
1202   void f2xm1();
1203   void fldl2e();
1204 
1205   void hlt();
1206 
1207   void idivl(Register src);
1208   void divl(Register src); // Unsigned division
1209 
1210 #ifdef _LP64
1211   void idivq(Register src);
1212 #endif
1213 
1214   void imull(Register dst, Register src);
1215   void imull(Register dst, Register src, int value);
1216   void imull(Register dst, Address src);
1217 
1218 #ifdef _LP64
1219   void imulq(Register dst, Register src);
1220   void imulq(Register dst, Register src, int value);
1221   void imulq(Register dst, Address src);
1222 #endif
1223 
1224   // jcc is the generic conditional branch generator to run-
1225   // time routines, jcc is used for branches to labels. jcc
1226   // takes a branch opcode (cc) and a label (L) and generates
1227   // either a backward branch or a forward branch and links it
1228   // to the label fixup chain. Usage:
1229   //
1230   // Label L;      // unbound label
1231   // jcc(cc, L);   // forward branch to unbound label
1232   // bind(L);      // bind label to the current pc
1233   // jcc(cc, L);   // backward branch to bound label
1234   // bind(L);      // illegal: a label may be bound only once
1235   //
1236   // Note: The same Label can be used for forward and backward branches
1237   // but it may be bound only once.
1238 
1239   void jcc(Condition cc, Label& L, bool maybe_short = true);
1240 
1241   // Conditional jump to a 8-bit offset to L.
1242   // WARNING: be very careful using this for forward jumps.  If the label is
1243   // not bound within an 8-bit offset of this instruction, a run-time error
1244   // will occur.
1245   void jccb(Condition cc, Label& L);
1246 
1247   void jmp(Address entry);    // pc <- entry
1248 
1249   // Label operations & relative jumps (PPUM Appendix D)
1250   void jmp(Label& L, bool maybe_short = true);   // unconditional jump to L
1251 
1252   void jmp(Register entry); // pc <- entry
1253 
1254   // Unconditional 8-bit offset jump to L.
1255   // WARNING: be very careful using this for forward jumps.  If the label is
1256   // not bound within an 8-bit offset of this instruction, a run-time error
1257   // will occur.
1258   void jmpb(Label& L);
1259 
1260   void ldmxcsr( Address src );
1261 
1262   void leal(Register dst, Address src);
1263 
1264   void leaq(Register dst, Address src);
1265 
1266   void lfence();
1267 
1268   void lock();
1269 
1270   void lzcntl(Register dst, Register src);
1271 
1272 #ifdef _LP64
1273   void lzcntq(Register dst, Register src);
1274 #endif
1275 
1276   enum Membar_mask_bits {
1277     StoreStore = 1 << 3,
1278     LoadStore  = 1 << 2,
1279     StoreLoad  = 1 << 1,
1280     LoadLoad   = 1 << 0
1281   };
1282 
1283   // Serializes memory and blows flags
1284   void membar(Membar_mask_bits order_constraint) {
1285     if (os::is_MP()) {
1286       // We only have to handle StoreLoad
1287       if (order_constraint & StoreLoad) {
1288         // All usable chips support "locked" instructions which suffice
1289         // as barriers, and are much faster than the alternative of
1290         // using cpuid instruction. We use here a locked add [esp-C],0.
1291         // This is conveniently otherwise a no-op except for blowing
1292         // flags, and introducing a false dependency on target memory
1293         // location. We can't do anything with flags, but we can avoid
1294         // memory dependencies in the current method by locked-adding
1295         // somewhere else on the stack. Doing [esp+C] will collide with
1296         // something on stack in current method, hence we go for [esp-C].
1297         // It is convenient since it is almost always in data cache, for
1298         // any small C.  We need to step back from SP to avoid data
1299         // dependencies with other things on below SP (callee-saves, for
1300         // example). Without a clear way to figure out the minimal safe
1301         // distance from SP, it makes sense to step back the complete
1302         // cache line, as this will also avoid possible second-order effects
1303         // with locked ops against the cache line. Our choice of offset
1304         // is bounded by x86 operand encoding, which should stay within
1305         // [-128; +127] to have the 8-byte displacement encoding.
1306         //
1307         // Any change to this code may need to revisit other places in
1308         // the code where this idiom is used, in particular the
1309         // orderAccess code.
1310 
1311         int offset = -VM_Version::L1_line_size();
1312         if (offset < -128) {
1313           offset = -128;
1314         }
1315 
1316         lock();
1317         addl(Address(rsp, offset), 0);// Assert the lock# signal here
1318       }
1319     }
1320   }
1321 
1322   void mfence();
1323 
1324   // Moves
1325 
1326   void mov64(Register dst, int64_t imm64);
1327 
1328   void movb(Address dst, Register src);
1329   void movb(Address dst, int imm8);
1330   void movb(Register dst, Address src);
1331 
1332   void movddup(XMMRegister dst, XMMRegister src);
1333 
1334   void kmovql(KRegister dst, KRegister src);
1335   void kmovql(KRegister dst, Register src);
1336   void kmovdl(KRegister dst, Register src);
1337   void kmovwl(KRegister dst, Register src);
1338   void kmovql(Address dst, KRegister src);
1339   void kmovql(KRegister dst, Address src);
1340 
1341   void movdl(XMMRegister dst, Register src);
1342   void movdl(Register dst, XMMRegister src);
1343   void movdl(XMMRegister dst, Address src);
1344   void movdl(Address dst, XMMRegister src);
1345 
1346   // Move Double Quadword
1347   void movdq(XMMRegister dst, Register src);
1348   void movdq(Register dst, XMMRegister src);
1349 
1350   // Move Aligned Double Quadword
1351   void movdqa(XMMRegister dst, XMMRegister src);
1352   void movdqa(XMMRegister dst, Address src);
1353 
1354   // Move Unaligned Double Quadword
1355   void movdqu(Address     dst, XMMRegister src);
1356   void movdqu(XMMRegister dst, Address src);
1357   void movdqu(XMMRegister dst, XMMRegister src);
1358 
1359   // Move Unaligned 256bit Vector
1360   void vmovdqu(Address dst, XMMRegister src);
1361   void vmovdqu(XMMRegister dst, Address src);
1362   void vmovdqu(XMMRegister dst, XMMRegister src);
1363 
1364    // Move Unaligned 512bit Vector
1365   void evmovdqul(Address dst, XMMRegister src, int vector_len);
1366   void evmovdqul(XMMRegister dst, Address src, int vector_len);
1367   void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len);
1368   void evmovdquq(Address dst, XMMRegister src, int vector_len);
1369   void evmovdquq(XMMRegister dst, Address src, int vector_len);
1370   void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len);
1371 
1372   // Move lower 64bit to high 64bit in 128bit register
1373   void movlhps(XMMRegister dst, XMMRegister src);
1374 
1375   void movl(Register dst, int32_t imm32);
1376   void movl(Address dst, int32_t imm32);
1377   void movl(Register dst, Register src);
1378   void movl(Register dst, Address src);
1379   void movl(Address dst, Register src);
1380 
1381   // These dummies prevent using movl from converting a zero (like NULL) into Register
1382   // by giving the compiler two choices it can't resolve
1383 
1384   void movl(Address  dst, void* junk);
1385   void movl(Register dst, void* junk);
1386 
1387 #ifdef _LP64
1388   void movq(Register dst, Register src);
1389   void movq(Register dst, Address src);
1390   void movq(Address  dst, Register src);
1391 #endif
1392 
1393   void movq(Address     dst, MMXRegister src );
1394   void movq(MMXRegister dst, Address src );
1395 
1396 #ifdef _LP64
1397   // These dummies prevent using movq from converting a zero (like NULL) into Register
1398   // by giving the compiler two choices it can't resolve
1399 
1400   void movq(Address  dst, void* dummy);
1401   void movq(Register dst, void* dummy);
1402 #endif
1403 
1404   // Move Quadword
1405   void movq(Address     dst, XMMRegister src);
1406   void movq(XMMRegister dst, Address src);
1407 
1408   void movsbl(Register dst, Address src);
1409   void movsbl(Register dst, Register src);
1410 
1411 #ifdef _LP64
1412   void movsbq(Register dst, Address src);
1413   void movsbq(Register dst, Register src);
1414 
1415   // Move signed 32bit immediate to 64bit extending sign
1416   void movslq(Address  dst, int32_t imm64);
1417   void movslq(Register dst, int32_t imm64);
1418 
1419   void movslq(Register dst, Address src);
1420   void movslq(Register dst, Register src);
1421   void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1422 #endif
1423 
1424   void movswl(Register dst, Address src);
1425   void movswl(Register dst, Register src);
1426 
1427 #ifdef _LP64
1428   void movswq(Register dst, Address src);
1429   void movswq(Register dst, Register src);
1430 #endif
1431 
1432   void movw(Address dst, int imm16);
1433   void movw(Register dst, Address src);
1434   void movw(Address dst, Register src);
1435 
1436   void movzbl(Register dst, Address src);
1437   void movzbl(Register dst, Register src);
1438 
1439 #ifdef _LP64
1440   void movzbq(Register dst, Address src);
1441   void movzbq(Register dst, Register src);
1442 #endif
1443 
1444   void movzwl(Register dst, Address src);
1445   void movzwl(Register dst, Register src);
1446 
1447 #ifdef _LP64
1448   void movzwq(Register dst, Address src);
1449   void movzwq(Register dst, Register src);
1450 #endif
1451 
1452   // Unsigned multiply with RAX destination register
1453   void mull(Address src);
1454   void mull(Register src);
1455 
1456 #ifdef _LP64
1457   void mulq(Address src);
1458   void mulq(Register src);
1459   void mulxq(Register dst1, Register dst2, Register src);
1460 #endif
1461 
1462   // Multiply Scalar Double-Precision Floating-Point Values
1463   void mulsd(XMMRegister dst, Address src);
1464   void mulsd(XMMRegister dst, XMMRegister src);
1465 
1466   // Multiply Scalar Single-Precision Floating-Point Values
1467   void mulss(XMMRegister dst, Address src);
1468   void mulss(XMMRegister dst, XMMRegister src);
1469 
1470   void negl(Register dst);
1471 
1472 #ifdef _LP64
1473   void negq(Register dst);
1474 #endif
1475 
1476   void nop(int i = 1);
1477 
1478   void notl(Register dst);
1479 
1480 #ifdef _LP64
1481   void notq(Register dst);
1482 #endif
1483 
1484   void orl(Address dst, int32_t imm32);
1485   void orl(Register dst, int32_t imm32);
1486   void orl(Register dst, Address src);
1487   void orl(Register dst, Register src);
1488   void orl(Address dst, Register src);
1489 
1490   void orq(Address dst, int32_t imm32);
1491   void orq(Register dst, int32_t imm32);
1492   void orq(Register dst, Address src);
1493   void orq(Register dst, Register src);
1494 
1495   // Pack with unsigned saturation
1496   void packuswb(XMMRegister dst, XMMRegister src);
1497   void packuswb(XMMRegister dst, Address src);
1498   void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1499 
1500   // Pemutation of 64bit words
1501   void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1502   void vpermq(XMMRegister dst, XMMRegister src, int imm8);
1503 
1504   void pause();
1505 
1506   // SSE4.2 string instructions
1507   void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1508   void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1509 
1510   // SSE 4.1 extract
1511   void pextrd(Register dst, XMMRegister src, int imm8);
1512   void pextrq(Register dst, XMMRegister src, int imm8);
1513   // SSE 2 extract
1514   void pextrw(Register dst, XMMRegister src, int imm8);
1515 
1516   // SSE 4.1 insert
1517   void pinsrd(XMMRegister dst, Register src, int imm8);
1518   void pinsrq(XMMRegister dst, Register src, int imm8);
1519   // SSE 2 insert
1520   void pinsrw(XMMRegister dst, Register src, int imm8);
1521 
1522   // SSE4.1 packed move
1523   void pmovzxbw(XMMRegister dst, XMMRegister src);
1524   void pmovzxbw(XMMRegister dst, Address src);
1525 
1526 #ifndef _LP64 // no 32bit push/pop on amd64
1527   void popl(Address dst);
1528 #endif
1529 
1530 #ifdef _LP64
1531   void popq(Address dst);
1532 #endif
1533 
1534   void popcntl(Register dst, Address src);
1535   void popcntl(Register dst, Register src);
1536 
1537 #ifdef _LP64
1538   void popcntq(Register dst, Address src);
1539   void popcntq(Register dst, Register src);
1540 #endif
1541 
1542   // Prefetches (SSE, SSE2, 3DNOW only)
1543 
1544   void prefetchnta(Address src);
1545   void prefetchr(Address src);
1546   void prefetcht0(Address src);
1547   void prefetcht1(Address src);
1548   void prefetcht2(Address src);
1549   void prefetchw(Address src);
1550 
1551   // Shuffle Bytes
1552   void pshufb(XMMRegister dst, XMMRegister src);
1553   void pshufb(XMMRegister dst, Address src);
1554 
1555   // Shuffle Packed Doublewords
1556   void pshufd(XMMRegister dst, XMMRegister src, int mode);
1557   void pshufd(XMMRegister dst, Address src,     int mode);
1558 
1559   // Shuffle Packed Low Words
1560   void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1561   void pshuflw(XMMRegister dst, Address src,     int mode);
1562 
1563   // Shift Right by bytes Logical DoubleQuadword Immediate
1564   void psrldq(XMMRegister dst, int shift);
1565   // Shift Left by bytes Logical DoubleQuadword Immediate
1566   void pslldq(XMMRegister dst, int shift);
1567 
1568   // Logical Compare 128bit
1569   void ptest(XMMRegister dst, XMMRegister src);
1570   void ptest(XMMRegister dst, Address src);
1571   // Logical Compare 256bit
1572   void vptest(XMMRegister dst, XMMRegister src);
1573   void vptest(XMMRegister dst, Address src);
1574 
1575   // Interleave Low Bytes
1576   void punpcklbw(XMMRegister dst, XMMRegister src);
1577   void punpcklbw(XMMRegister dst, Address src);
1578 
1579   // Interleave Low Doublewords
1580   void punpckldq(XMMRegister dst, XMMRegister src);
1581   void punpckldq(XMMRegister dst, Address src);
1582 
1583   // Interleave Low Quadwords
1584   void punpcklqdq(XMMRegister dst, XMMRegister src);
1585 
1586 #ifndef _LP64 // no 32bit push/pop on amd64
1587   void pushl(Address src);
1588 #endif
1589 
1590   void pushq(Address src);
1591 
1592   void rcll(Register dst, int imm8);
1593 
1594   void rclq(Register dst, int imm8);
1595 
1596   void rcrq(Register dst, int imm8);
1597 
1598   void rcpps(XMMRegister dst, XMMRegister src);
1599 
1600   void rcpss(XMMRegister dst, XMMRegister src);
1601 
1602   void rdtsc();
1603 
1604   void ret(int imm16);
1605 
1606 #ifdef _LP64
1607   void rorq(Register dst, int imm8);
1608   void rorxq(Register dst, Register src, int imm8);
1609 #endif
1610 
1611   void sahf();
1612 
1613   void sarl(Register dst, int imm8);
1614   void sarl(Register dst);
1615 
1616   void sarq(Register dst, int imm8);
1617   void sarq(Register dst);
1618 
1619   void sbbl(Address dst, int32_t imm32);
1620   void sbbl(Register dst, int32_t imm32);
1621   void sbbl(Register dst, Address src);
1622   void sbbl(Register dst, Register src);
1623 
1624   void sbbq(Address dst, int32_t imm32);
1625   void sbbq(Register dst, int32_t imm32);
1626   void sbbq(Register dst, Address src);
1627   void sbbq(Register dst, Register src);
1628 
1629   void setb(Condition cc, Register dst);
1630 
1631   void shldl(Register dst, Register src);
1632   void shldl(Register dst, Register src, int8_t imm8);
1633 
1634   void shll(Register dst, int imm8);
1635   void shll(Register dst);
1636 
1637   void shlq(Register dst, int imm8);
1638   void shlq(Register dst);
1639 
1640   void shrdl(Register dst, Register src);
1641 
1642   void shrl(Register dst, int imm8);
1643   void shrl(Register dst);
1644 
1645   void shrq(Register dst, int imm8);
1646   void shrq(Register dst);
1647 
1648   void smovl(); // QQQ generic?
1649 
1650   // Compute Square Root of Scalar Double-Precision Floating-Point Value
1651   void sqrtsd(XMMRegister dst, Address src);
1652   void sqrtsd(XMMRegister dst, XMMRegister src);
1653 
1654   // Compute Square Root of Scalar Single-Precision Floating-Point Value
1655   void sqrtss(XMMRegister dst, Address src);
1656   void sqrtss(XMMRegister dst, XMMRegister src);
1657 
1658   void std();
1659 
1660   void stmxcsr( Address dst );
1661 
1662   void subl(Address dst, int32_t imm32);
1663   void subl(Address dst, Register src);
1664   void subl(Register dst, int32_t imm32);
1665   void subl(Register dst, Address src);
1666   void subl(Register dst, Register src);
1667 
1668   void subq(Address dst, int32_t imm32);
1669   void subq(Address dst, Register src);
1670   void subq(Register dst, int32_t imm32);
1671   void subq(Register dst, Address src);
1672   void subq(Register dst, Register src);
1673 
1674   // Force generation of a 4 byte immediate value even if it fits into 8bit
1675   void subl_imm32(Register dst, int32_t imm32);
1676   void subq_imm32(Register dst, int32_t imm32);
1677 
1678   // Subtract Scalar Double-Precision Floating-Point Values
1679   void subsd(XMMRegister dst, Address src);
1680   void subsd(XMMRegister dst, XMMRegister src);
1681 
1682   // Subtract Scalar Single-Precision Floating-Point Values
1683   void subss(XMMRegister dst, Address src);
1684   void subss(XMMRegister dst, XMMRegister src);
1685 
1686   void testb(Register dst, int imm8);
1687 
1688   void testl(Register dst, int32_t imm32);
1689   void testl(Register dst, Register src);
1690   void testl(Register dst, Address src);
1691 
1692   void testq(Register dst, int32_t imm32);
1693   void testq(Register dst, Register src);
1694 
1695   // BMI - count trailing zeros
1696   void tzcntl(Register dst, Register src);
1697   void tzcntq(Register dst, Register src);
1698 
1699   // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1700   void ucomisd(XMMRegister dst, Address src);
1701   void ucomisd(XMMRegister dst, XMMRegister src);
1702 
1703   // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1704   void ucomiss(XMMRegister dst, Address src);
1705   void ucomiss(XMMRegister dst, XMMRegister src);
1706 
1707   void xabort(int8_t imm8);
1708 
1709   void xaddl(Address dst, Register src);
1710 
1711   void xaddq(Address dst, Register src);
1712 
1713   void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none);
1714 
1715   void xchgl(Register reg, Address adr);
1716   void xchgl(Register dst, Register src);
1717 
1718   void xchgq(Register reg, Address adr);
1719   void xchgq(Register dst, Register src);
1720 
1721   void xend();
1722 
1723   // Get Value of Extended Control Register
1724   void xgetbv();
1725 
1726   void xorl(Register dst, int32_t imm32);
1727   void xorl(Register dst, Address src);
1728   void xorl(Register dst, Register src);
1729 
1730   void xorq(Register dst, Address src);
1731   void xorq(Register dst, Register src);
1732 
1733   void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1734 
1735   // AVX 3-operands scalar instructions (encoded with VEX prefix)
1736 
1737   void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
1738   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1739   void vaddss(XMMRegister dst, XMMRegister nds, Address src);
1740   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1741   void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
1742   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1743   void vdivss(XMMRegister dst, XMMRegister nds, Address src);
1744   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1745   void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
1746   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1747   void vmulss(XMMRegister dst, XMMRegister nds, Address src);
1748   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1749   void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
1750   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1751   void vsubss(XMMRegister dst, XMMRegister nds, Address src);
1752   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1753 
1754 
1755   //====================VECTOR ARITHMETIC=====================================
1756 
1757   // Add Packed Floating-Point Values
1758   void addpd(XMMRegister dst, XMMRegister src);
1759   void addps(XMMRegister dst, XMMRegister src);
1760   void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1761   void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1762   void vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1763   void vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1764 
1765   // Subtract Packed Floating-Point Values
1766   void subpd(XMMRegister dst, XMMRegister src);
1767   void subps(XMMRegister dst, XMMRegister src);
1768   void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1769   void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1770   void vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1771   void vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1772 
1773   // Multiply Packed Floating-Point Values
1774   void mulpd(XMMRegister dst, XMMRegister src);
1775   void mulpd(XMMRegister dst, Address src);
1776   void mulps(XMMRegister dst, XMMRegister src);
1777   void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1778   void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1779   void vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1780   void vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1781 
1782   // Divide Packed Floating-Point Values
1783   void divpd(XMMRegister dst, XMMRegister src);
1784   void divps(XMMRegister dst, XMMRegister src);
1785   void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1786   void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1787   void vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1788   void vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1789 
1790   // Sqrt Packed Floating-Point Values - Double precision only
1791   void vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len);
1792   void vsqrtpd(XMMRegister dst, Address src, int vector_len);
1793 
1794   // Bitwise Logical AND of Packed Floating-Point Values
1795   void andpd(XMMRegister dst, XMMRegister src);
1796   void andps(XMMRegister dst, XMMRegister src);
1797   void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1798   void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1799   void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1800   void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1801 
1802   void unpckhpd(XMMRegister dst, XMMRegister src);
1803   void unpcklpd(XMMRegister dst, XMMRegister src);
1804 
1805   // Bitwise Logical XOR of Packed Floating-Point Values
1806   void xorpd(XMMRegister dst, XMMRegister src);
1807   void xorps(XMMRegister dst, XMMRegister src);
1808   void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1809   void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1810   void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1811   void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1812 
1813   // Add horizontal packed integers
1814   void vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1815   void vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1816   void phaddw(XMMRegister dst, XMMRegister src);
1817   void phaddd(XMMRegister dst, XMMRegister src);
1818 
1819   // Add packed integers
1820   void paddb(XMMRegister dst, XMMRegister src);
1821   void paddw(XMMRegister dst, XMMRegister src);
1822   void paddd(XMMRegister dst, XMMRegister src);
1823   void paddq(XMMRegister dst, XMMRegister src);
1824   void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1825   void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1826   void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1827   void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1828   void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1829   void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1830   void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1831   void vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1832 
1833   // Sub packed integers
1834   void psubb(XMMRegister dst, XMMRegister src);
1835   void psubw(XMMRegister dst, XMMRegister src);
1836   void psubd(XMMRegister dst, XMMRegister src);
1837   void psubq(XMMRegister dst, XMMRegister src);
1838   void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1839   void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1840   void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1841   void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1842   void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1843   void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1844   void vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1845   void vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1846 
1847   // Multiply packed integers (only shorts and ints)
1848   void pmullw(XMMRegister dst, XMMRegister src);
1849   void pmulld(XMMRegister dst, XMMRegister src);
1850   void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1851   void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1852   void vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1853   void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1854   void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1855   void vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1856 
1857   // Shift left packed integers
1858   void psllw(XMMRegister dst, int shift);
1859   void pslld(XMMRegister dst, int shift);
1860   void psllq(XMMRegister dst, int shift);
1861   void psllw(XMMRegister dst, XMMRegister shift);
1862   void pslld(XMMRegister dst, XMMRegister shift);
1863   void psllq(XMMRegister dst, XMMRegister shift);
1864   void vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1865   void vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1866   void vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1867   void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1868   void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1869   void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1870 
1871   // Logical shift right packed integers
1872   void psrlw(XMMRegister dst, int shift);
1873   void psrld(XMMRegister dst, int shift);
1874   void psrlq(XMMRegister dst, int shift);
1875   void psrlw(XMMRegister dst, XMMRegister shift);
1876   void psrld(XMMRegister dst, XMMRegister shift);
1877   void psrlq(XMMRegister dst, XMMRegister shift);
1878   void vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1879   void vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1880   void vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1881   void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1882   void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1883   void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1884 
1885   // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
1886   void psraw(XMMRegister dst, int shift);
1887   void psrad(XMMRegister dst, int shift);
1888   void psraw(XMMRegister dst, XMMRegister shift);
1889   void psrad(XMMRegister dst, XMMRegister shift);
1890   void vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1891   void vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1892   void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1893   void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1894 
1895   // And packed integers
1896   void pand(XMMRegister dst, XMMRegister src);
1897   void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1898   void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1899 
1900   // Andn packed integers
1901   void pandn(XMMRegister dst, XMMRegister src);
1902 
1903   // Or packed integers
1904   void por(XMMRegister dst, XMMRegister src);
1905   void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1906   void vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1907 
1908   // Xor packed integers
1909   void pxor(XMMRegister dst, XMMRegister src);
1910   void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1911   void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1912 
1913   // Copy low 128bit into high 128bit of YMM registers.
1914   void vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src);
1915   void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src);
1916   void vextractf128h(XMMRegister dst, XMMRegister src);
1917   void vextracti128h(XMMRegister dst, XMMRegister src);
1918 
1919   // Load/store high 128bit of YMM registers which does not destroy other half.
1920   void vinsertf128h(XMMRegister dst, Address src);
1921   void vinserti128h(XMMRegister dst, Address src);
1922   void vextractf128h(Address dst, XMMRegister src);
1923   void vextracti128h(Address dst, XMMRegister src);
1924 
1925   // Copy low 256bit into high 256bit of ZMM registers.
1926   void vinserti64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src, int value);
1927   void vinsertf64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src, int value);
1928   void vextracti64x4h(XMMRegister dst, XMMRegister src, int value);
1929   void vextractf64x4h(XMMRegister dst, XMMRegister src, int value);
1930   void vextractf64x4h(Address dst, XMMRegister src, int value);
1931   void vinsertf64x4h(XMMRegister dst, Address src, int value);
1932 
1933   // Copy targeted 128bit segments of the ZMM registers
1934   void vextracti64x2h(XMMRegister dst, XMMRegister src, int value);
1935   void vextractf64x2h(XMMRegister dst, XMMRegister src, int value);
1936   void vextractf32x4h(XMMRegister dst, XMMRegister src, int value);
1937   void vextractf32x4h(Address dst, XMMRegister src, int value);
1938   void vinsertf32x4h(XMMRegister dst, XMMRegister nds, XMMRegister src, int value);
1939   void vinsertf32x4h(XMMRegister dst, Address src, int value);
1940 
1941   // duplicate 4-bytes integer data from src into 8 locations in dest
1942   void vpbroadcastd(XMMRegister dst, XMMRegister src);
1943 
1944   // duplicate n-bytes integer data from src into vector_len locations in dest
1945   void evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len);
1946   void evpbroadcastb(XMMRegister dst, Address src, int vector_len);
1947   void evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
1948   void evpbroadcastw(XMMRegister dst, Address src, int vector_len);
1949   void evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len);
1950   void evpbroadcastd(XMMRegister dst, Address src, int vector_len);
1951   void evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len);
1952   void evpbroadcastq(XMMRegister dst, Address src, int vector_len);
1953 
1954   void evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len);
1955   void evpbroadcastss(XMMRegister dst, Address src, int vector_len);
1956   void evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len);
1957   void evpbroadcastsd(XMMRegister dst, Address src, int vector_len);
1958 
1959   void evpbroadcastb(XMMRegister dst, Register src, int vector_len);
1960   void evpbroadcastw(XMMRegister dst, Register src, int vector_len);
1961   void evpbroadcastd(XMMRegister dst, Register src, int vector_len);
1962   void evpbroadcastq(XMMRegister dst, Register src, int vector_len);
1963 
1964   // Carry-Less Multiplication Quadword
1965   void pclmulqdq(XMMRegister dst, XMMRegister src, int mask);
1966   void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask);
1967 
1968   // AVX instruction which is used to clear upper 128 bits of YMM registers and
1969   // to avoid transaction penalty between AVX and SSE states. There is no
1970   // penalty if legacy SSE instructions are encoded using VEX prefix because
1971   // they always clear upper 128 bits. It should be used before calling
1972   // runtime code and native libraries.
1973   void vzeroupper();
1974 
1975   // AVX support for vectorized conditional move (double). The following two instructions used only coupled.
1976   void cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len);
1977   void vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
1978 
1979 
1980  protected:
1981   // Next instructions require address alignment 16 bytes SSE mode.
1982   // They should be called only from corresponding MacroAssembler instructions.
1983   void andpd(XMMRegister dst, Address src);
1984   void andps(XMMRegister dst, Address src);
1985   void xorpd(XMMRegister dst, Address src);
1986   void xorps(XMMRegister dst, Address src);
1987 
1988 };
1989 
1990 // The Intel x86/Amd64 Assembler attributes: All fields enclosed here are to guide encoding level decisions.
1991 // Specific set functions are for specialized use, else defaults or whatever was supplied to object construction
1992 // are applied.
1993 class InstructionAttr {
1994 public:
1995   InstructionAttr(
1996     int vector_len,
1997     bool rex_vex_w,
1998     bool legacy_mode,
1999     bool no_reg_mask,
2000     bool uses_vl)
2001     :
2002       _avx_vector_len(vector_len),
2003       _rex_vex_w(rex_vex_w),
2004       _legacy_mode(legacy_mode),
2005       _no_reg_mask(no_reg_mask),
2006       _uses_vl(uses_vl),
2007       _tuple_type(Assembler::EVEX_ETUP),
2008       _input_size_in_bits(Assembler::EVEX_NObit),
2009       _is_evex_instruction(false),
2010       _evex_encoding(0),
2011       _is_clear_context(false),
2012       _is_extended_context(false),
2013       _current_assembler(NULL) {
2014     if (UseAVX < 3) _legacy_mode = true;
2015   }
2016 
2017   ~InstructionAttr() {
2018     if (_current_assembler != NULL) {
2019       _current_assembler->clear_attributes();
2020     }
2021     _current_assembler = NULL;
2022   }
2023 
2024 private:
2025   int  _avx_vector_len;
2026   bool _rex_vex_w;
2027   bool _legacy_mode;
2028   bool _no_reg_mask;
2029   bool _uses_vl;
2030   int  _tuple_type;
2031   int  _input_size_in_bits;
2032   bool _is_evex_instruction;
2033   int  _evex_encoding;
2034   bool _is_clear_context;
2035   bool _is_extended_context;
2036 
2037   Assembler *_current_assembler;
2038 
2039 public:
2040   // query functions for field accessors
2041   int  get_vector_len(void) const { return _avx_vector_len; }
2042   bool is_rex_vex_w(void) const { return _rex_vex_w; }
2043   bool is_legacy_mode(void) const { return _legacy_mode; }
2044   bool is_no_reg_mask(void) const { return _no_reg_mask; }
2045   bool uses_vl(void) const { return _uses_vl; }
2046   int  get_tuple_type(void) const { return _tuple_type; }
2047   int  get_input_size(void) const { return _input_size_in_bits; }
2048   int  is_evex_instruction(void) const { return _is_evex_instruction; }
2049   int  get_evex_encoding(void) const { return _evex_encoding; }
2050   bool is_clear_context(void) const { return _is_clear_context; }
2051   bool is_extended_context(void) const { return _is_extended_context; }
2052 
2053   // Set the vector len manually
2054   void set_vector_len(int vector_len) { _avx_vector_len = vector_len; }
2055 
2056   // Set the instruction to be encoded in AVX mode
2057   void set_is_legacy_mode(void) { _legacy_mode = true; }
2058 
2059   // Set the current instuction to be encoded as an EVEX instuction
2060   void set_is_evex_instruction(void) { _is_evex_instruction = true; }
2061 
2062   // Internal encoding data used in compressed immediate offset programming
2063   void set_evex_encoding(int value) { _evex_encoding = value; }
2064 
2065   // Set the Evex.Z field to be used to clear all non directed XMM/YMM/ZMM components
2066   void set_is_clear_context(void) { _is_clear_context = true; }
2067 
2068   // Map back to current asembler so that we can manage object level assocation
2069   void set_current_assembler(Assembler *current_assembler) { _current_assembler = current_assembler; }
2070 
2071   // Address modifiers used for compressed displacement calculation
2072   void set_address_attributes(int tuple_type, int input_size_in_bits) {
2073     if (VM_Version::supports_evex()) {
2074       _tuple_type = tuple_type;
2075       _input_size_in_bits = input_size_in_bits;
2076     }
2077   }
2078 
2079 };
2080 
2081 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP