1 //
   2 // Copyright (c) 2011, 2015, Oracle and/or its affiliates. All rights reserved.
   3 // Copyright 2012, 2015 SAP AG. All rights reserved.
   4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5 //
   6 // This code is free software; you can redistribute it and/or modify it
   7 // under the terms of the GNU General Public License version 2 only, as
   8 // published by the Free Software Foundation.
   9 //
  10 // This code is distributed in the hope that it will be useful, but WITHOUT
  11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13 // version 2 for more details (a copy is included in the LICENSE file that
  14 // accompanied this code).
  15 //
  16 // You should have received a copy of the GNU General Public License version
  17 // 2 along with this work; if not, write to the Free Software Foundation,
  18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19 //
  20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21 // or visit www.oracle.com if you need additional information or have any
  22 // questions.
  23 //
  24 //
  25 
  26 //
  27 // PPC64 Architecture Description File
  28 //
  29 
  30 //----------REGISTER DEFINITION BLOCK------------------------------------------
  31 // This information is used by the matcher and the register allocator to
  32 // describe individual registers and classes of registers within the target
  33 // architecture.
  34 register %{
  35 //----------Architecture Description Register Definitions----------------------
  36 // General Registers
  37 // "reg_def"  name (register save type, C convention save type,
  38 //                  ideal register type, encoding);
  39 //
  40 // Register Save Types:
  41 //
  42 //   NS  = No-Save:     The register allocator assumes that these registers
  43 //                      can be used without saving upon entry to the method, &
  44 //                      that they do not need to be saved at call sites.
  45 //
  46 //   SOC = Save-On-Call: The register allocator assumes that these registers
  47 //                      can be used without saving upon entry to the method,
  48 //                      but that they must be saved at call sites.
  49 //                      These are called "volatiles" on ppc.
  50 //
  51 //   SOE = Save-On-Entry: The register allocator assumes that these registers
  52 //                      must be saved before using them upon entry to the
  53 //                      method, but they do not need to be saved at call
  54 //                      sites.
  55 //                      These are called "nonvolatiles" on ppc.
  56 //
  57 //   AS  = Always-Save:   The register allocator assumes that these registers
  58 //                      must be saved before using them upon entry to the
  59 //                      method, & that they must be saved at call sites.
  60 //
  61 // Ideal Register Type is used to determine how to save & restore a
  62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
  63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
  64 //
  65 // The encoding number is the actual bit-pattern placed into the opcodes.
  66 //
  67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
  68 // Supplement Version 1.7 as of 2003-10-29.
  69 //
  70 // For each 64-bit register we must define two registers: the register
  71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
  72 // e.g. R3_H, which is needed by the allocator, but is not used
  73 // for stores, loads, etc.
  74 
  75 // ----------------------------
  76 // Integer/Long Registers
  77 // ----------------------------
  78 
  79   // PPC64 has 32 64-bit integer registers.
  80 
  81   // types: v = volatile, nv = non-volatile, s = system
  82   reg_def R0   ( SOC, SOC, Op_RegI,  0, R0->as_VMReg()         );  // v   used in prologs
  83   reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
  84   reg_def R1   ( NS,  NS,  Op_RegI,  1, R1->as_VMReg()         );  // s   SP
  85   reg_def R1_H ( NS,  NS,  Op_RegI, 99, R1->as_VMReg()->next() );
  86   reg_def R2   ( SOC, SOC, Op_RegI,  2, R2->as_VMReg()         );  // v   TOC
  87   reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
  88   reg_def R3   ( SOC, SOC, Op_RegI,  3, R3->as_VMReg()         );  // v   iarg1 & iret
  89   reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
  90   reg_def R4   ( SOC, SOC, Op_RegI,  4, R4->as_VMReg()         );  //     iarg2
  91   reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
  92   reg_def R5   ( SOC, SOC, Op_RegI,  5, R5->as_VMReg()         );  // v   iarg3
  93   reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
  94   reg_def R6   ( SOC, SOC, Op_RegI,  6, R6->as_VMReg()         );  // v   iarg4
  95   reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
  96   reg_def R7   ( SOC, SOC, Op_RegI,  7, R7->as_VMReg()         );  // v   iarg5
  97   reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
  98   reg_def R8   ( SOC, SOC, Op_RegI,  8, R8->as_VMReg()         );  // v   iarg6
  99   reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
 100   reg_def R9   ( SOC, SOC, Op_RegI,  9, R9->as_VMReg()         );  // v   iarg7
 101   reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
 102   reg_def R10  ( SOC, SOC, Op_RegI, 10, R10->as_VMReg()        );  // v   iarg8
 103   reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
 104   reg_def R11  ( SOC, SOC, Op_RegI, 11, R11->as_VMReg()        );  // v   ENV / scratch
 105   reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
 106   reg_def R12  ( SOC, SOC, Op_RegI, 12, R12->as_VMReg()        );  // v   scratch
 107   reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
 108   reg_def R13  ( NS,  NS,  Op_RegI, 13, R13->as_VMReg()        );  // s   system thread id
 109   reg_def R13_H( NS,  NS,  Op_RegI, 99, R13->as_VMReg()->next());
 110   reg_def R14  ( SOC, SOE, Op_RegI, 14, R14->as_VMReg()        );  // nv
 111   reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
 112   reg_def R15  ( SOC, SOE, Op_RegI, 15, R15->as_VMReg()        );  // nv
 113   reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
 114   reg_def R16  ( SOC, SOE, Op_RegI, 16, R16->as_VMReg()        );  // nv
 115   reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
 116   reg_def R17  ( SOC, SOE, Op_RegI, 17, R17->as_VMReg()        );  // nv
 117   reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
 118   reg_def R18  ( SOC, SOE, Op_RegI, 18, R18->as_VMReg()        );  // nv
 119   reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
 120   reg_def R19  ( SOC, SOE, Op_RegI, 19, R19->as_VMReg()        );  // nv
 121   reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
 122   reg_def R20  ( SOC, SOE, Op_RegI, 20, R20->as_VMReg()        );  // nv
 123   reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
 124   reg_def R21  ( SOC, SOE, Op_RegI, 21, R21->as_VMReg()        );  // nv
 125   reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
 126   reg_def R22  ( SOC, SOE, Op_RegI, 22, R22->as_VMReg()        );  // nv
 127   reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
 128   reg_def R23  ( SOC, SOE, Op_RegI, 23, R23->as_VMReg()        );  // nv
 129   reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
 130   reg_def R24  ( SOC, SOE, Op_RegI, 24, R24->as_VMReg()        );  // nv
 131   reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
 132   reg_def R25  ( SOC, SOE, Op_RegI, 25, R25->as_VMReg()        );  // nv
 133   reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
 134   reg_def R26  ( SOC, SOE, Op_RegI, 26, R26->as_VMReg()        );  // nv
 135   reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
 136   reg_def R27  ( SOC, SOE, Op_RegI, 27, R27->as_VMReg()        );  // nv
 137   reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
 138   reg_def R28  ( SOC, SOE, Op_RegI, 28, R28->as_VMReg()        );  // nv
 139   reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
 140   reg_def R29  ( SOC, SOE, Op_RegI, 29, R29->as_VMReg()        );  // nv
 141   reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
 142   reg_def R30  ( SOC, SOE, Op_RegI, 30, R30->as_VMReg()        );  // nv
 143   reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
 144   reg_def R31  ( SOC, SOE, Op_RegI, 31, R31->as_VMReg()        );  // nv
 145   reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
 146 
 147 
 148 // ----------------------------
 149 // Float/Double Registers
 150 // ----------------------------
 151 
 152   // Double Registers
 153   // The rules of ADL require that double registers be defined in pairs.
 154   // Each pair must be two 32-bit values, but not necessarily a pair of
 155   // single float registers. In each pair, ADLC-assigned register numbers
 156   // must be adjacent, with the lower number even. Finally, when the
 157   // CPU stores such a register pair to memory, the word associated with
 158   // the lower ADLC-assigned number must be stored to the lower address.
 159 
 160   // PPC64 has 32 64-bit floating-point registers. Each can store a single
 161   // or double precision floating-point value.
 162 
 163   // types: v = volatile, nv = non-volatile, s = system
 164   reg_def F0   ( SOC, SOC, Op_RegF,  0, F0->as_VMReg()         );  // v   scratch
 165   reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
 166   reg_def F1   ( SOC, SOC, Op_RegF,  1, F1->as_VMReg()         );  // v   farg1 & fret
 167   reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
 168   reg_def F2   ( SOC, SOC, Op_RegF,  2, F2->as_VMReg()         );  // v   farg2
 169   reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
 170   reg_def F3   ( SOC, SOC, Op_RegF,  3, F3->as_VMReg()         );  // v   farg3
 171   reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
 172   reg_def F4   ( SOC, SOC, Op_RegF,  4, F4->as_VMReg()         );  // v   farg4
 173   reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
 174   reg_def F5   ( SOC, SOC, Op_RegF,  5, F5->as_VMReg()         );  // v   farg5
 175   reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
 176   reg_def F6   ( SOC, SOC, Op_RegF,  6, F6->as_VMReg()         );  // v   farg6
 177   reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
 178   reg_def F7   ( SOC, SOC, Op_RegF,  7, F7->as_VMReg()         );  // v   farg7
 179   reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
 180   reg_def F8   ( SOC, SOC, Op_RegF,  8, F8->as_VMReg()         );  // v   farg8
 181   reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
 182   reg_def F9   ( SOC, SOC, Op_RegF,  9, F9->as_VMReg()         );  // v   farg9
 183   reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
 184   reg_def F10  ( SOC, SOC, Op_RegF, 10, F10->as_VMReg()        );  // v   farg10
 185   reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
 186   reg_def F11  ( SOC, SOC, Op_RegF, 11, F11->as_VMReg()        );  // v   farg11
 187   reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
 188   reg_def F12  ( SOC, SOC, Op_RegF, 12, F12->as_VMReg()        );  // v   farg12
 189   reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
 190   reg_def F13  ( SOC, SOC, Op_RegF, 13, F13->as_VMReg()        );  // v   farg13
 191   reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
 192   reg_def F14  ( SOC, SOE, Op_RegF, 14, F14->as_VMReg()        );  // nv
 193   reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
 194   reg_def F15  ( SOC, SOE, Op_RegF, 15, F15->as_VMReg()        );  // nv
 195   reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
 196   reg_def F16  ( SOC, SOE, Op_RegF, 16, F16->as_VMReg()        );  // nv
 197   reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
 198   reg_def F17  ( SOC, SOE, Op_RegF, 17, F17->as_VMReg()        );  // nv
 199   reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
 200   reg_def F18  ( SOC, SOE, Op_RegF, 18, F18->as_VMReg()        );  // nv
 201   reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
 202   reg_def F19  ( SOC, SOE, Op_RegF, 19, F19->as_VMReg()        );  // nv
 203   reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
 204   reg_def F20  ( SOC, SOE, Op_RegF, 20, F20->as_VMReg()        );  // nv
 205   reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
 206   reg_def F21  ( SOC, SOE, Op_RegF, 21, F21->as_VMReg()        );  // nv
 207   reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
 208   reg_def F22  ( SOC, SOE, Op_RegF, 22, F22->as_VMReg()        );  // nv
 209   reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
 210   reg_def F23  ( SOC, SOE, Op_RegF, 23, F23->as_VMReg()        );  // nv
 211   reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
 212   reg_def F24  ( SOC, SOE, Op_RegF, 24, F24->as_VMReg()        );  // nv
 213   reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
 214   reg_def F25  ( SOC, SOE, Op_RegF, 25, F25->as_VMReg()        );  // nv
 215   reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
 216   reg_def F26  ( SOC, SOE, Op_RegF, 26, F26->as_VMReg()        );  // nv
 217   reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
 218   reg_def F27  ( SOC, SOE, Op_RegF, 27, F27->as_VMReg()        );  // nv
 219   reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
 220   reg_def F28  ( SOC, SOE, Op_RegF, 28, F28->as_VMReg()        );  // nv
 221   reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
 222   reg_def F29  ( SOC, SOE, Op_RegF, 29, F29->as_VMReg()        );  // nv
 223   reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
 224   reg_def F30  ( SOC, SOE, Op_RegF, 30, F30->as_VMReg()        );  // nv
 225   reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
 226   reg_def F31  ( SOC, SOE, Op_RegF, 31, F31->as_VMReg()        );  // nv
 227   reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
 228 
 229 // ----------------------------
 230 // Special Registers
 231 // ----------------------------
 232 
 233 // Condition Codes Flag Registers
 234 
 235   // PPC64 has 8 condition code "registers" which are all contained
 236   // in the CR register.
 237 
 238   // types: v = volatile, nv = non-volatile, s = system
 239   reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg());  // v
 240   reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg());  // v
 241   reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg());  // nv
 242   reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg());  // nv
 243   reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg());  // nv
 244   reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg());  // v
 245   reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg());  // v
 246   reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg());  // v
 247 
 248   // Special registers of PPC64
 249 
 250   reg_def SR_XER(    SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg());     // v
 251   reg_def SR_LR(     SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg());      // v
 252   reg_def SR_CTR(    SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg());     // v
 253   reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg());  // v
 254   reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
 255   reg_def SR_PPR(    SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg());     // v
 256 
 257 
 258 // ----------------------------
 259 // Specify priority of register selection within phases of register
 260 // allocation. Highest priority is first. A useful heuristic is to
 261 // give registers a low priority when they are required by machine
 262 // instructions, like EAX and EDX on I486, and choose no-save registers
 263 // before save-on-call, & save-on-call before save-on-entry. Registers
 264 // which participate in fixed calling sequences should come last.
 265 // Registers which are used as pairs must fall on an even boundary.
 266 
 267 // It's worth about 1% on SPEC geomean to get this right.
 268 
 269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
 270 // in adGlobals_ppc.hpp which defines the <register>_num values, e.g.
 271 // R3_num. Therefore, R3_num may not be (and in reality is not)
 272 // the same as R3->encoding()! Furthermore, we cannot make any
 273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
 274 // Additionally, the function
 275 //   static enum RC rc_class(OptoReg::Name reg )
 276 // maps a given <register>_num value to its chunk type (except for flags)
 277 // and its current implementation relies on chunk0 and chunk1 having a
 278 // size of 64 each.
 279 
 280 // If you change this allocation class, please have a look at the
 281 // default values for the parameters RoundRobinIntegerRegIntervalStart
 282 // and RoundRobinFloatRegIntervalStart
 283 
 284 alloc_class chunk0 (
 285   // Chunk0 contains *all* 64 integer registers halves.
 286 
 287   // "non-volatile" registers
 288   R14, R14_H,
 289   R15, R15_H,
 290   R17, R17_H,
 291   R18, R18_H,
 292   R19, R19_H,
 293   R20, R20_H,
 294   R21, R21_H,
 295   R22, R22_H,
 296   R23, R23_H,
 297   R24, R24_H,
 298   R25, R25_H,
 299   R26, R26_H,
 300   R27, R27_H,
 301   R28, R28_H,
 302   R29, R29_H,
 303   R30, R30_H,
 304   R31, R31_H,
 305 
 306   // scratch/special registers
 307   R11, R11_H,
 308   R12, R12_H,
 309 
 310   // argument registers
 311   R10, R10_H,
 312   R9,  R9_H,
 313   R8,  R8_H,
 314   R7,  R7_H,
 315   R6,  R6_H,
 316   R5,  R5_H,
 317   R4,  R4_H,
 318   R3,  R3_H,
 319 
 320   // special registers, not available for allocation
 321   R16, R16_H,     // R16_thread
 322   R13, R13_H,     // system thread id
 323   R2,  R2_H,      // may be used for TOC
 324   R1,  R1_H,      // SP
 325   R0,  R0_H       // R0 (scratch)
 326 );
 327 
 328 // If you change this allocation class, please have a look at the
 329 // default values for the parameters RoundRobinIntegerRegIntervalStart
 330 // and RoundRobinFloatRegIntervalStart
 331 
 332 alloc_class chunk1 (
 333   // Chunk1 contains *all* 64 floating-point registers halves.
 334 
 335   // scratch register
 336   F0,  F0_H,
 337 
 338   // argument registers
 339   F13, F13_H,
 340   F12, F12_H,
 341   F11, F11_H,
 342   F10, F10_H,
 343   F9,  F9_H,
 344   F8,  F8_H,
 345   F7,  F7_H,
 346   F6,  F6_H,
 347   F5,  F5_H,
 348   F4,  F4_H,
 349   F3,  F3_H,
 350   F2,  F2_H,
 351   F1,  F1_H,
 352 
 353   // non-volatile registers
 354   F14, F14_H,
 355   F15, F15_H,
 356   F16, F16_H,
 357   F17, F17_H,
 358   F18, F18_H,
 359   F19, F19_H,
 360   F20, F20_H,
 361   F21, F21_H,
 362   F22, F22_H,
 363   F23, F23_H,
 364   F24, F24_H,
 365   F25, F25_H,
 366   F26, F26_H,
 367   F27, F27_H,
 368   F28, F28_H,
 369   F29, F29_H,
 370   F30, F30_H,
 371   F31, F31_H
 372 );
 373 
 374 alloc_class chunk2 (
 375   // Chunk2 contains *all* 8 condition code registers.
 376 
 377   CCR0,
 378   CCR1,
 379   CCR2,
 380   CCR3,
 381   CCR4,
 382   CCR5,
 383   CCR6,
 384   CCR7
 385 );
 386 
 387 alloc_class chunk3 (
 388   // special registers
 389   // These registers are not allocated, but used for nodes generated by postalloc expand.
 390   SR_XER,
 391   SR_LR,
 392   SR_CTR,
 393   SR_VRSAVE,
 394   SR_SPEFSCR,
 395   SR_PPR
 396 );
 397 
 398 //-------Architecture Description Register Classes-----------------------
 399 
 400 // Several register classes are automatically defined based upon
 401 // information in this architecture description.
 402 
 403 // 1) reg_class inline_cache_reg           ( as defined in frame section )
 404 // 2) reg_class compiler_method_oop_reg    ( as defined in frame section )
 405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
 406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
 407 //
 408 
 409 // ----------------------------
 410 // 32 Bit Register Classes
 411 // ----------------------------
 412 
 413 // We specify registers twice, once as read/write, and once read-only.
 414 // We use the read-only registers for source operands. With this, we
 415 // can include preset read only registers in this class, as a hard-coded
 416 // '0'-register. (We used to simulate this on ppc.)
 417 
 418 // 32 bit registers that can be read and written i.e. these registers
 419 // can be dest (or src) of normal instructions.
 420 reg_class bits32_reg_rw(
 421 /*R0*/              // R0
 422 /*R1*/              // SP
 423   R2,               // TOC
 424   R3,
 425   R4,
 426   R5,
 427   R6,
 428   R7,
 429   R8,
 430   R9,
 431   R10,
 432   R11,
 433   R12,
 434 /*R13*/             // system thread id
 435   R14,
 436   R15,
 437 /*R16*/             // R16_thread
 438   R17,
 439   R18,
 440   R19,
 441   R20,
 442   R21,
 443   R22,
 444   R23,
 445   R24,
 446   R25,
 447   R26,
 448   R27,
 449   R28,
 450 /*R29,*/             // global TOC
 451   R30,
 452   R31
 453 );
 454 
 455 // 32 bit registers that can only be read i.e. these registers can
 456 // only be src of all instructions.
 457 reg_class bits32_reg_ro(
 458 /*R0*/              // R0
 459 /*R1*/              // SP
 460   R2                // TOC
 461   R3,
 462   R4,
 463   R5,
 464   R6,
 465   R7,
 466   R8,
 467   R9,
 468   R10,
 469   R11,
 470   R12,
 471 /*R13*/             // system thread id
 472   R14,
 473   R15,
 474 /*R16*/             // R16_thread
 475   R17,
 476   R18,
 477   R19,
 478   R20,
 479   R21,
 480   R22,
 481   R23,
 482   R24,
 483   R25,
 484   R26,
 485   R27,
 486   R28,
 487 /*R29,*/
 488   R30,
 489   R31
 490 );
 491 
 492 reg_class rscratch1_bits32_reg(R11);
 493 reg_class rscratch2_bits32_reg(R12);
 494 reg_class rarg1_bits32_reg(R3);
 495 reg_class rarg2_bits32_reg(R4);
 496 reg_class rarg3_bits32_reg(R5);
 497 reg_class rarg4_bits32_reg(R6);
 498 
 499 // ----------------------------
 500 // 64 Bit Register Classes
 501 // ----------------------------
 502 // 64-bit build means 64-bit pointers means hi/lo pairs
 503 
 504 reg_class rscratch1_bits64_reg(R11_H, R11);
 505 reg_class rscratch2_bits64_reg(R12_H, R12);
 506 reg_class rarg1_bits64_reg(R3_H, R3);
 507 reg_class rarg2_bits64_reg(R4_H, R4);
 508 reg_class rarg3_bits64_reg(R5_H, R5);
 509 reg_class rarg4_bits64_reg(R6_H, R6);
 510 // Thread register, 'written' by tlsLoadP, see there.
 511 reg_class thread_bits64_reg(R16_H, R16);
 512 
 513 reg_class r19_bits64_reg(R19_H, R19);
 514 
 515 // 64 bit registers that can be read and written i.e. these registers
 516 // can be dest (or src) of normal instructions.
 517 reg_class bits64_reg_rw(
 518 /*R0_H,  R0*/     // R0
 519 /*R1_H,  R1*/     // SP
 520   R2_H,  R2,      // TOC
 521   R3_H,  R3,
 522   R4_H,  R4,
 523   R5_H,  R5,
 524   R6_H,  R6,
 525   R7_H,  R7,
 526   R8_H,  R8,
 527   R9_H,  R9,
 528   R10_H, R10,
 529   R11_H, R11,
 530   R12_H, R12,
 531 /*R13_H, R13*/   // system thread id
 532   R14_H, R14,
 533   R15_H, R15,
 534 /*R16_H, R16*/   // R16_thread
 535   R17_H, R17,
 536   R18_H, R18,
 537   R19_H, R19,
 538   R20_H, R20,
 539   R21_H, R21,
 540   R22_H, R22,
 541   R23_H, R23,
 542   R24_H, R24,
 543   R25_H, R25,
 544   R26_H, R26,
 545   R27_H, R27,
 546   R28_H, R28,
 547 /*R29_H, R29,*/
 548   R30_H, R30,
 549   R31_H, R31
 550 );
 551 
 552 // 64 bit registers used excluding r2, r11 and r12
 553 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
 554 // r2, r11 and r12 internally.
 555 reg_class bits64_reg_leaf_call(
 556 /*R0_H,  R0*/     // R0
 557 /*R1_H,  R1*/     // SP
 558 /*R2_H,  R2*/     // TOC
 559   R3_H,  R3,
 560   R4_H,  R4,
 561   R5_H,  R5,
 562   R6_H,  R6,
 563   R7_H,  R7,
 564   R8_H,  R8,
 565   R9_H,  R9,
 566   R10_H, R10,
 567 /*R11_H, R11*/
 568 /*R12_H, R12*/
 569 /*R13_H, R13*/   // system thread id
 570   R14_H, R14,
 571   R15_H, R15,
 572 /*R16_H, R16*/   // R16_thread
 573   R17_H, R17,
 574   R18_H, R18,
 575   R19_H, R19,
 576   R20_H, R20,
 577   R21_H, R21,
 578   R22_H, R22,
 579   R23_H, R23,
 580   R24_H, R24,
 581   R25_H, R25,
 582   R26_H, R26,
 583   R27_H, R27,
 584   R28_H, R28,
 585 /*R29_H, R29,*/
 586   R30_H, R30,
 587   R31_H, R31
 588 );
 589 
 590 // Used to hold the TOC to avoid collisions with expanded DynamicCall
 591 // which uses r19 as inline cache internally and expanded LeafCall which uses
 592 // r2, r11 and r12 internally.
 593 reg_class bits64_constant_table_base(
 594 /*R0_H,  R0*/     // R0
 595 /*R1_H,  R1*/     // SP
 596 /*R2_H,  R2*/     // TOC
 597   R3_H,  R3,
 598   R4_H,  R4,
 599   R5_H,  R5,
 600   R6_H,  R6,
 601   R7_H,  R7,
 602   R8_H,  R8,
 603   R9_H,  R9,
 604   R10_H, R10,
 605 /*R11_H, R11*/
 606 /*R12_H, R12*/
 607 /*R13_H, R13*/   // system thread id
 608   R14_H, R14,
 609   R15_H, R15,
 610 /*R16_H, R16*/   // R16_thread
 611   R17_H, R17,
 612   R18_H, R18,
 613 /*R19_H, R19*/
 614   R20_H, R20,
 615   R21_H, R21,
 616   R22_H, R22,
 617   R23_H, R23,
 618   R24_H, R24,
 619   R25_H, R25,
 620   R26_H, R26,
 621   R27_H, R27,
 622   R28_H, R28,
 623 /*R29_H, R29,*/
 624   R30_H, R30,
 625   R31_H, R31
 626 );
 627 
 628 // 64 bit registers that can only be read i.e. these registers can
 629 // only be src of all instructions.
 630 reg_class bits64_reg_ro(
 631 /*R0_H,  R0*/     // R0
 632   R1_H,  R1,
 633   R2_H,  R2,       // TOC
 634   R3_H,  R3,
 635   R4_H,  R4,
 636   R5_H,  R5,
 637   R6_H,  R6,
 638   R7_H,  R7,
 639   R8_H,  R8,
 640   R9_H,  R9,
 641   R10_H, R10,
 642   R11_H, R11,
 643   R12_H, R12,
 644 /*R13_H, R13*/   // system thread id
 645   R14_H, R14,
 646   R15_H, R15,
 647   R16_H, R16,    // R16_thread
 648   R17_H, R17,
 649   R18_H, R18,
 650   R19_H, R19,
 651   R20_H, R20,
 652   R21_H, R21,
 653   R22_H, R22,
 654   R23_H, R23,
 655   R24_H, R24,
 656   R25_H, R25,
 657   R26_H, R26,
 658   R27_H, R27,
 659   R28_H, R28,
 660 /*R29_H, R29,*/ // TODO: let allocator handle TOC!!
 661   R30_H, R30,
 662   R31_H, R31
 663 );
 664 
 665 
 666 // ----------------------------
 667 // Special Class for Condition Code Flags Register
 668 
 669 reg_class int_flags(
 670 /*CCR0*/             // scratch
 671 /*CCR1*/             // scratch
 672 /*CCR2*/             // nv!
 673 /*CCR3*/             // nv!
 674 /*CCR4*/             // nv!
 675   CCR5,
 676   CCR6,
 677   CCR7
 678 );
 679 
 680 reg_class int_flags_ro(
 681   CCR0,
 682   CCR1,
 683   CCR2,
 684   CCR3,
 685   CCR4,
 686   CCR5,
 687   CCR6,
 688   CCR7
 689 );
 690 
 691 reg_class int_flags_CR0(CCR0);
 692 reg_class int_flags_CR1(CCR1);
 693 reg_class int_flags_CR6(CCR6);
 694 reg_class ctr_reg(SR_CTR);
 695 
 696 // ----------------------------
 697 // Float Register Classes
 698 // ----------------------------
 699 
 700 reg_class flt_reg(
 701 /*F0*/              // scratch
 702   F1,
 703   F2,
 704   F3,
 705   F4,
 706   F5,
 707   F6,
 708   F7,
 709   F8,
 710   F9,
 711   F10,
 712   F11,
 713   F12,
 714   F13,
 715   F14,              // nv!
 716   F15,              // nv!
 717   F16,              // nv!
 718   F17,              // nv!
 719   F18,              // nv!
 720   F19,              // nv!
 721   F20,              // nv!
 722   F21,              // nv!
 723   F22,              // nv!
 724   F23,              // nv!
 725   F24,              // nv!
 726   F25,              // nv!
 727   F26,              // nv!
 728   F27,              // nv!
 729   F28,              // nv!
 730   F29,              // nv!
 731   F30,              // nv!
 732   F31               // nv!
 733 );
 734 
 735 // Double precision float registers have virtual `high halves' that
 736 // are needed by the allocator.
 737 reg_class dbl_reg(
 738 /*F0,  F0_H*/     // scratch
 739   F1,  F1_H,
 740   F2,  F2_H,
 741   F3,  F3_H,
 742   F4,  F4_H,
 743   F5,  F5_H,
 744   F6,  F6_H,
 745   F7,  F7_H,
 746   F8,  F8_H,
 747   F9,  F9_H,
 748   F10, F10_H,
 749   F11, F11_H,
 750   F12, F12_H,
 751   F13, F13_H,
 752   F14, F14_H,    // nv!
 753   F15, F15_H,    // nv!
 754   F16, F16_H,    // nv!
 755   F17, F17_H,    // nv!
 756   F18, F18_H,    // nv!
 757   F19, F19_H,    // nv!
 758   F20, F20_H,    // nv!
 759   F21, F21_H,    // nv!
 760   F22, F22_H,    // nv!
 761   F23, F23_H,    // nv!
 762   F24, F24_H,    // nv!
 763   F25, F25_H,    // nv!
 764   F26, F26_H,    // nv!
 765   F27, F27_H,    // nv!
 766   F28, F28_H,    // nv!
 767   F29, F29_H,    // nv!
 768   F30, F30_H,    // nv!
 769   F31, F31_H     // nv!
 770 );
 771 
 772  %}
 773 
 774 //----------DEFINITION BLOCK---------------------------------------------------
 775 // Define name --> value mappings to inform the ADLC of an integer valued name
 776 // Current support includes integer values in the range [0, 0x7FFFFFFF]
 777 // Format:
 778 //        int_def  <name>         ( <int_value>, <expression>);
 779 // Generated Code in ad_<arch>.hpp
 780 //        #define  <name>   (<expression>)
 781 //        // value == <int_value>
 782 // Generated code in ad_<arch>.cpp adlc_verification()
 783 //        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
 784 //
 785 definitions %{
 786   // The default cost (of an ALU instruction).
 787   int_def DEFAULT_COST_LOW        (     30,      30);
 788   int_def DEFAULT_COST            (    100,     100);
 789   int_def HUGE_COST               (1000000, 1000000);
 790 
 791   // Memory refs
 792   int_def MEMORY_REF_COST_LOW     (    200, DEFAULT_COST * 2);
 793   int_def MEMORY_REF_COST         (    300, DEFAULT_COST * 3);
 794 
 795   // Branches are even more expensive.
 796   int_def BRANCH_COST             (    900, DEFAULT_COST * 9);
 797   int_def CALL_COST               (   1300, DEFAULT_COST * 13);
 798 %}
 799 
 800 
 801 //----------SOURCE BLOCK-------------------------------------------------------
 802 // This is a block of C++ code which provides values, functions, and
 803 // definitions necessary in the rest of the architecture description.
 804 source_hpp %{
 805   // Header information of the source block.
 806   // Method declarations/definitions which are used outside
 807   // the ad-scope can conveniently be defined here.
 808   //
 809   // To keep related declarations/definitions/uses close together,
 810   // we switch between source %{ }% and source_hpp %{ }% freely as needed.
 811 
 812   // Returns true if Node n is followed by a MemBar node that
 813   // will do an acquire. If so, this node must not do the acquire
 814   // operation.
 815   bool followed_by_acquire(const Node *n);
 816 %}
 817 
 818 source %{
 819 
 820 // Optimize load-acquire.
 821 //
 822 // Check if acquire is unnecessary due to following operation that does
 823 // acquire anyways.
 824 // Walk the pattern:
 825 //
 826 //      n: Load.acq
 827 //           |
 828 //      MemBarAcquire
 829 //       |         |
 830 //  Proj(ctrl)  Proj(mem)
 831 //       |         |
 832 //   MemBarRelease/Volatile
 833 //
 834 bool followed_by_acquire(const Node *load) {
 835   assert(load->is_Load(), "So far implemented only for loads.");
 836 
 837   // Find MemBarAcquire.
 838   const Node *mba = NULL;
 839   for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
 840     const Node *out = load->fast_out(i);
 841     if (out->Opcode() == Op_MemBarAcquire) {
 842       if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
 843       mba = out;
 844       break;
 845     }
 846   }
 847   if (!mba) return false;
 848 
 849   // Find following MemBar node.
 850   //
 851   // The following node must be reachable by control AND memory
 852   // edge to assure no other operations are in between the two nodes.
 853   //
 854   // So first get the Proj node, mem_proj, to use it to iterate forward.
 855   Node *mem_proj = NULL;
 856   for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
 857     mem_proj = mba->fast_out(i);      // Throw out-of-bounds if proj not found
 858     assert(mem_proj->is_Proj(), "only projections here");
 859     ProjNode *proj = mem_proj->as_Proj();
 860     if (proj->_con == TypeFunc::Memory &&
 861         !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
 862       break;
 863   }
 864   assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
 865 
 866   // Search MemBar behind Proj. If there are other memory operations
 867   // behind the Proj we lost.
 868   for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
 869     Node *x = mem_proj->fast_out(j);
 870     // Proj might have an edge to a store or load node which precedes the membar.
 871     if (x->is_Mem()) return false;
 872 
 873     // On PPC64 release and volatile are implemented by an instruction
 874     // that also has acquire semantics. I.e. there is no need for an
 875     // acquire before these.
 876     int xop = x->Opcode();
 877     if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
 878       // Make sure we're not missing Call/Phi/MergeMem by checking
 879       // control edges. The control edge must directly lead back
 880       // to the MemBarAcquire
 881       Node *ctrl_proj = x->in(0);
 882       if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
 883         return true;
 884       }
 885     }
 886   }
 887 
 888   return false;
 889 }
 890 
 891 #define __ _masm.
 892 
 893 // Tertiary op of a LoadP or StoreP encoding.
 894 #define REGP_OP true
 895 
 896 // ****************************************************************************
 897 
 898 // REQUIRED FUNCTIONALITY
 899 
 900 // !!!!! Special hack to get all type of calls to specify the byte offset
 901 //       from the start of the call to the point where the return address
 902 //       will point.
 903 
 904 // PPC port: Removed use of lazy constant construct.
 905 
 906 int MachCallStaticJavaNode::ret_addr_offset() {
 907   // It's only a single branch-and-link instruction.
 908   return 4;
 909 }
 910 
 911 int MachCallDynamicJavaNode::ret_addr_offset() {
 912   // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
 913   // postalloc expanded calls if we use inline caches and do not update method data.
 914   if (UseInlineCaches)
 915     return 4;
 916 
 917   int vtable_index = this->_vtable_index;
 918   if (vtable_index < 0) {
 919     // Must be invalid_vtable_index, not nonvirtual_vtable_index.
 920     assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
 921     return 12;
 922   } else {
 923     assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
 924     return 24;
 925   }
 926 }
 927 
 928 int MachCallRuntimeNode::ret_addr_offset() {
 929 #if defined(ABI_ELFv2)
 930   return 28;
 931 #else
 932   return 40;
 933 #endif
 934 }
 935 
 936 //=============================================================================
 937 
 938 // condition code conversions
 939 
 940 static int cc_to_boint(int cc) {
 941   return Assembler::bcondCRbiIs0 | (cc & 8);
 942 }
 943 
 944 static int cc_to_inverse_boint(int cc) {
 945   return Assembler::bcondCRbiIs0 | (8-(cc & 8));
 946 }
 947 
 948 static int cc_to_biint(int cc, int flags_reg) {
 949   return (flags_reg << 2) | (cc & 3);
 950 }
 951 
 952 //=============================================================================
 953 
 954 // Compute padding required for nodes which need alignment. The padding
 955 // is the number of bytes (not instructions) which will be inserted before
 956 // the instruction. The padding must match the size of a NOP instruction.
 957 
 958 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
 959   return (3*4-current_offset)&31;
 960 }
 961 
 962 int string_indexOf_imm1Node::compute_padding(int current_offset) const {
 963   return (2*4-current_offset)&31;
 964 }
 965 
 966 int string_indexOf_immNode::compute_padding(int current_offset) const {
 967   return (3*4-current_offset)&31;
 968 }
 969 
 970 int string_indexOfNode::compute_padding(int current_offset) const {
 971   return (1*4-current_offset)&31;
 972 }
 973 
 974 int string_compareNode::compute_padding(int current_offset) const {
 975   return (4*4-current_offset)&31;
 976 }
 977 
 978 int string_equals_immNode::compute_padding(int current_offset) const {
 979   if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled).
 980   return (2*4-current_offset)&31;
 981 }
 982 
 983 int string_equalsNode::compute_padding(int current_offset) const {
 984   return (7*4-current_offset)&31;
 985 }
 986 
 987 int inlineCallClearArrayNode::compute_padding(int current_offset) const {
 988   return (2*4-current_offset)&31;
 989 }
 990 
 991 //=============================================================================
 992 
 993 // Indicate if the safepoint node needs the polling page as an input.
 994 bool SafePointNode::needs_polling_address_input() {
 995   // The address is loaded from thread by a seperate node.
 996   return true;
 997 }
 998 
 999 //=============================================================================
1000 
1001 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1002 void emit_break(CodeBuffer &cbuf) {
1003   MacroAssembler _masm(&cbuf);
1004   __ illtrap();
1005 }
1006 
1007 #ifndef PRODUCT
1008 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1009   st->print("BREAKPOINT");
1010 }
1011 #endif
1012 
1013 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1014   emit_break(cbuf);
1015 }
1016 
1017 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1018   return MachNode::size(ra_);
1019 }
1020 
1021 //=============================================================================
1022 
1023 void emit_nop(CodeBuffer &cbuf) {
1024   MacroAssembler _masm(&cbuf);
1025   __ nop();
1026 }
1027 
1028 static inline void emit_long(CodeBuffer &cbuf, int value) {
1029   *((int*)(cbuf.insts_end())) = value;
1030   cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1031 }
1032 
1033 //=============================================================================
1034 
1035 %} // interrupt source
1036 
1037 source_hpp %{ // Header information of the source block.
1038 
1039 //--------------------------------------------------------------
1040 //---<  Used for optimization in Compile::Shorten_branches  >---
1041 //--------------------------------------------------------------
1042 
1043 const uint trampoline_stub_size     =  6 * BytesPerInstWord;
1044 
1045 class CallStubImpl {
1046 
1047  public:
1048 
1049   // Emit call stub, compiled java to interpreter.
1050   static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset);
1051 
1052   // Size of call trampoline stub.
1053   // This doesn't need to be accurate to the byte, but it
1054   // must be larger than or equal to the real size of the stub.
1055   static uint size_call_trampoline() {
1056     return trampoline_stub_size;
1057   }
1058 
1059   // number of relocations needed by a call trampoline stub
1060   static uint reloc_call_trampoline() {
1061     return 5;
1062   }
1063 
1064 };
1065 
1066 %} // end source_hpp
1067 
1068 source %{
1069 
1070 // Emit a trampoline stub for a call to a target which is too far away.
1071 //
1072 // code sequences:
1073 //
1074 // call-site:
1075 //   branch-and-link to <destination> or <trampoline stub>
1076 //
1077 // Related trampoline stub for this call-site in the stub section:
1078 //   load the call target from the constant pool
1079 //   branch via CTR (LR/link still points to the call-site above)
1080 
1081 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1082   // Start the stub.
1083   address stub = __ start_a_stub(Compile::MAX_stubs_size/2);
1084   if (stub == NULL) {
1085     ciEnv::current()->record_failure("CodeCache is full");
1086     return;
1087   }
1088 
1089   // For java_to_interp stubs we use R11_scratch1 as scratch register
1090   // and in call trampoline stubs we use R12_scratch2. This way we
1091   // can distinguish them (see is_NativeCallTrampolineStub_at()).
1092   Register reg_scratch = R12_scratch2;
1093 
1094   // Create a trampoline stub relocation which relates this trampoline stub
1095   // with the call instruction at insts_call_instruction_offset in the
1096   // instructions code-section.
1097   __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset));
1098   const int stub_start_offset = __ offset();
1099 
1100   // Now, create the trampoline stub's code:
1101   // - load the TOC
1102   // - load the call target from the constant pool
1103   // - call
1104   __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1105   __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false);
1106   __ mtctr(reg_scratch);
1107   __ bctr();
1108 
1109   const address stub_start_addr = __ addr_at(stub_start_offset);
1110 
1111   // FIXME: Assert that the trampoline stub can be identified and patched.
1112 
1113   // Assert that the encoded destination_toc_offset can be identified and that it is correct.
1114   assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(),
1115          "encoded offset into the constant pool must match");
1116   // Trampoline_stub_size should be good.
1117   assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size");
1118   assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
1119 
1120   // End the stub.
1121   __ end_a_stub();
1122 }
1123 
1124 //=============================================================================
1125 
1126 // Emit an inline branch-and-link call and a related trampoline stub.
1127 //
1128 // code sequences:
1129 //
1130 // call-site:
1131 //   branch-and-link to <destination> or <trampoline stub>
1132 //
1133 // Related trampoline stub for this call-site in the stub section:
1134 //   load the call target from the constant pool
1135 //   branch via CTR (LR/link still points to the call-site above)
1136 //
1137 
1138 typedef struct {
1139   int insts_call_instruction_offset;
1140   int ret_addr_offset;
1141 } EmitCallOffsets;
1142 
1143 // Emit a branch-and-link instruction that branches to a trampoline.
1144 // - Remember the offset of the branch-and-link instruction.
1145 // - Add a relocation at the branch-and-link instruction.
1146 // - Emit a branch-and-link.
1147 // - Remember the return pc offset.
1148 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1149   EmitCallOffsets offsets = { -1, -1 };
1150   const int start_offset = __ offset();
1151   offsets.insts_call_instruction_offset = __ offset();
1152 
1153   // No entry point given, use the current pc.
1154   if (entry_point == NULL) entry_point = __ pc();
1155 
1156   if (!Compile::current()->in_scratch_emit_size()) {
1157     // Put the entry point as a constant into the constant pool.
1158     const address entry_point_toc_addr   = __ address_constant(entry_point, RelocationHolder::none);
1159     const int     entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1160 
1161     // Emit the trampoline stub which will be related to the branch-and-link below.
1162     CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1163     if (ciEnv::current()->failing()) { return offsets; } // Code cache may be full.
1164     __ relocate(rtype);
1165   }
1166 
1167   // Note: At this point we do not have the address of the trampoline
1168   // stub, and the entry point might be too far away for bl, so __ pc()
1169   // serves as dummy and the bl will be patched later.
1170   __ bl((address) __ pc());
1171 
1172   offsets.ret_addr_offset = __ offset() - start_offset;
1173 
1174   return offsets;
1175 }
1176 
1177 //=============================================================================
1178 
1179 // Factory for creating loadConL* nodes for large/small constant pool.
1180 
1181 static inline jlong replicate_immF(float con) {
1182   // Replicate float con 2 times and pack into vector.
1183   int val = *((int*)&con);
1184   jlong lval = val;
1185   lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1186   return lval;
1187 }
1188 
1189 //=============================================================================
1190 
1191 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1192 int Compile::ConstantTable::calculate_table_base_offset() const {
1193   return 0;  // absolute addressing, no offset
1194 }
1195 
1196 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1197 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1198   iRegPdstOper *op_dst = new iRegPdstOper();
1199   MachNode *m1 = new loadToc_hiNode();
1200   MachNode *m2 = new loadToc_loNode();
1201 
1202   m1->add_req(NULL);
1203   m2->add_req(NULL, m1);
1204   m1->_opnds[0] = op_dst;
1205   m2->_opnds[0] = op_dst;
1206   m2->_opnds[1] = op_dst;
1207   ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1208   ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1209   nodes->push(m1);
1210   nodes->push(m2);
1211 }
1212 
1213 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1214   // Is postalloc expanded.
1215   ShouldNotReachHere();
1216 }
1217 
1218 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1219   return 0;
1220 }
1221 
1222 #ifndef PRODUCT
1223 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1224   st->print("-- \t// MachConstantBaseNode (empty encoding)");
1225 }
1226 #endif
1227 
1228 //=============================================================================
1229 
1230 #ifndef PRODUCT
1231 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1232   Compile* C = ra_->C;
1233   const long framesize = C->frame_slots() << LogBytesPerInt;
1234 
1235   st->print("PROLOG\n\t");
1236   if (C->need_stack_bang(framesize)) {
1237     st->print("stack_overflow_check\n\t");
1238   }
1239 
1240   if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1241     st->print("save return pc\n\t");
1242     st->print("push frame %ld\n\t", -framesize);
1243   }
1244 }
1245 #endif
1246 
1247 // Macro used instead of the common __ to emulate the pipes of PPC.
1248 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1249 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1250 // still no scheduling of this code is possible, the micro scheduler is aware of the
1251 // code and can update its internal data. The following mechanism is used to achieve this:
1252 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1253 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1254 #if 0 // TODO: PPC port
1255 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling())                    \
1256                   C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1257                 _masm.
1258 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling())                    \
1259                   C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1260 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling())                 \
1261                   C->hb_scheduling()->_pdScheduling->advance_offset
1262 #else
1263 #define ___(op) if (UsePower6SchedulerPPC64)                                          \
1264                   Unimplemented();                                                    \
1265                 _masm.
1266 #define ___stop if (UsePower6SchedulerPPC64)                                          \
1267                   Unimplemented()
1268 #define ___advance if (UsePower6SchedulerPPC64)                                       \
1269                   Unimplemented()
1270 #endif
1271 
1272 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1273   Compile* C = ra_->C;
1274   MacroAssembler _masm(&cbuf);
1275 
1276   const long framesize = C->frame_size_in_bytes();
1277   assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment");
1278 
1279   const bool method_is_frameless      = false /* TODO: PPC port C->is_frameless_method()*/;
1280 
1281   const Register return_pc            = R20; // Must match return_addr() in frame section.
1282   const Register callers_sp           = R21;
1283   const Register push_frame_temp      = R22;
1284   const Register toc_temp             = R23;
1285   assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1286 
1287   if (method_is_frameless) {
1288     // Add nop at beginning of all frameless methods to prevent any
1289     // oop instructions from getting overwritten by make_not_entrant
1290     // (patching attempt would fail).
1291     ___(nop) nop();
1292   } else {
1293     // Get return pc.
1294     ___(mflr) mflr(return_pc);
1295   }
1296 
1297   // Calls to C2R adapters often do not accept exceptional returns.
1298   // We require that their callers must bang for them. But be
1299   // careful, because some VM calls (such as call site linkage) can
1300   // use several kilobytes of stack. But the stack safety zone should
1301   // account for that. See bugs 4446381, 4468289, 4497237.
1302 
1303   int bangsize = C->bang_size_in_bytes();
1304   assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect");
1305   if (C->need_stack_bang(bangsize) && UseStackBanging) {
1306     // Unfortunately we cannot use the function provided in
1307     // assembler.cpp as we have to emulate the pipes. So I had to
1308     // insert the code of generate_stack_overflow_check(), see
1309     // assembler.cpp for some illuminative comments.
1310     const int page_size = os::vm_page_size();
1311     int bang_end = StackShadowPages * page_size;
1312 
1313     // This is how far the previous frame's stack banging extended.
1314     const int bang_end_safe = bang_end;
1315 
1316     if (bangsize > page_size) {
1317       bang_end += bangsize;
1318     }
1319 
1320     int bang_offset = bang_end_safe;
1321 
1322     while (bang_offset <= bang_end) {
1323       // Need at least one stack bang at end of shadow zone.
1324 
1325       // Again I had to copy code, this time from assembler_ppc.cpp,
1326       // bang_stack_with_offset - see there for comments.
1327 
1328       // Stack grows down, caller passes positive offset.
1329       assert(bang_offset > 0, "must bang with positive offset");
1330 
1331       long stdoffset = -bang_offset;
1332 
1333       if (Assembler::is_simm(stdoffset, 16)) {
1334         // Signed 16 bit offset, a simple std is ok.
1335         if (UseLoadInstructionsForStackBangingPPC64) {
1336           ___(ld) ld(R0,  (int)(signed short)stdoffset, R1_SP);
1337         } else {
1338           ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1339         }
1340       } else if (Assembler::is_simm(stdoffset, 31)) {
1341         // Use largeoffset calculations for addis & ld/std.
1342         const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1343         const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1344 
1345         Register tmp = R11;
1346         ___(addis) addis(tmp, R1_SP, hi);
1347         if (UseLoadInstructionsForStackBangingPPC64) {
1348           ___(ld) ld(R0, lo, tmp);
1349         } else {
1350           ___(std) std(R0, lo, tmp);
1351         }
1352       } else {
1353         ShouldNotReachHere();
1354       }
1355 
1356       bang_offset += page_size;
1357     }
1358     // R11 trashed
1359   } // C->need_stack_bang(framesize) && UseStackBanging
1360 
1361   unsigned int bytes = (unsigned int)framesize;
1362   long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1363   ciMethod *currMethod = C->method();
1364 
1365   // Optimized version for most common case.
1366   if (UsePower6SchedulerPPC64 &&
1367       !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1368       !(false /* ConstantsALot TODO: PPC port*/)) {
1369     ___(or) mr(callers_sp, R1_SP);
1370     ___(std) std(return_pc, _abi(lr), R1_SP);
1371     ___(stdu) stdu(R1_SP, -offset, R1_SP);
1372     return;
1373   }
1374 
1375   if (!method_is_frameless) {
1376     // Get callers sp.
1377     ___(or) mr(callers_sp, R1_SP);
1378 
1379     // Push method's frame, modifies SP.
1380     assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1381     // The ABI is already accounted for in 'framesize' via the
1382     // 'out_preserve' area.
1383     Register tmp = push_frame_temp;
1384     // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1385     if (Assembler::is_simm(-offset, 16)) {
1386       ___(stdu) stdu(R1_SP, -offset, R1_SP);
1387     } else {
1388       long x = -offset;
1389       // Had to insert load_const(tmp, -offset).
1390       ___(addis)  lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1391       ___(ori)    ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1392       ___(rldicr) sldi(tmp, tmp, 32);
1393       ___(oris)   oris(tmp, tmp, (x & 0xffff0000) >> 16);
1394       ___(ori)    ori( tmp, tmp, (x & 0x0000ffff));
1395 
1396       ___(stdux) stdux(R1_SP, R1_SP, tmp);
1397     }
1398   }
1399 #if 0 // TODO: PPC port
1400   // For testing large constant pools, emit a lot of constants to constant pool.
1401   // "Randomize" const_size.
1402   if (ConstantsALot) {
1403     const int num_consts = const_size();
1404     for (int i = 0; i < num_consts; i++) {
1405       __ long_constant(0xB0B5B00BBABE);
1406     }
1407   }
1408 #endif
1409   if (!method_is_frameless) {
1410     // Save return pc.
1411     ___(std) std(return_pc, _abi(lr), callers_sp);
1412   }
1413 }
1414 #undef ___
1415 #undef ___stop
1416 #undef ___advance
1417 
1418 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1419   // Variable size. determine dynamically.
1420   return MachNode::size(ra_);
1421 }
1422 
1423 int MachPrologNode::reloc() const {
1424   // Return number of relocatable values contained in this instruction.
1425   return 1; // 1 reloc entry for load_const(toc).
1426 }
1427 
1428 //=============================================================================
1429 
1430 #ifndef PRODUCT
1431 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1432   Compile* C = ra_->C;
1433 
1434   st->print("EPILOG\n\t");
1435   st->print("restore return pc\n\t");
1436   st->print("pop frame\n\t");
1437 
1438   if (do_polling() && C->is_method_compilation()) {
1439     st->print("touch polling page\n\t");
1440   }
1441 }
1442 #endif
1443 
1444 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1445   Compile* C = ra_->C;
1446   MacroAssembler _masm(&cbuf);
1447 
1448   const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1449   assert(framesize >= 0, "negative frame-size?");
1450 
1451   const bool method_needs_polling = do_polling() && C->is_method_compilation();
1452   const bool method_is_frameless  = false /* TODO: PPC port C->is_frameless_method()*/;
1453   const Register return_pc        = R11;
1454   const Register polling_page     = R12;
1455 
1456   if (!method_is_frameless) {
1457     // Restore return pc relative to callers' sp.
1458     __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1459   }
1460 
1461   if (method_needs_polling) {
1462     if (LoadPollAddressFromThread) {
1463       // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1464       Unimplemented();
1465     } else {
1466       __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1467     }
1468   }
1469 
1470   if (!method_is_frameless) {
1471     // Move return pc to LR.
1472     __ mtlr(return_pc);
1473     // Pop frame (fixed frame-size).
1474     __ addi(R1_SP, R1_SP, (int)framesize);
1475   }
1476 
1477   if (method_needs_polling) {
1478     // We need to mark the code position where the load from the safepoint
1479     // polling page was emitted as relocInfo::poll_return_type here.
1480     __ relocate(relocInfo::poll_return_type);
1481     __ load_from_polling_page(polling_page);
1482   }
1483 }
1484 
1485 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1486   // Variable size. Determine dynamically.
1487   return MachNode::size(ra_);
1488 }
1489 
1490 int MachEpilogNode::reloc() const {
1491   // Return number of relocatable values contained in this instruction.
1492   return 1; // 1 for load_from_polling_page.
1493 }
1494 
1495 const Pipeline * MachEpilogNode::pipeline() const {
1496   return MachNode::pipeline_class();
1497 }
1498 
1499 // This method seems to be obsolete. It is declared in machnode.hpp
1500 // and defined in all *.ad files, but it is never called. Should we
1501 // get rid of it?
1502 int MachEpilogNode::safepoint_offset() const {
1503   assert(do_polling(), "no return for this epilog node");
1504   return 0;
1505 }
1506 
1507 #if 0 // TODO: PPC port
1508 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1509   MacroAssembler _masm(&cbuf);
1510   if (LoadPollAddressFromThread) {
1511     _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1512   } else {
1513     _masm.nop();
1514   }
1515 }
1516 
1517 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1518   if (LoadPollAddressFromThread) {
1519     return 4;
1520   } else {
1521     return 4;
1522   }
1523 }
1524 
1525 #ifndef PRODUCT
1526 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1527   st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1528 }
1529 #endif
1530 
1531 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1532   return RSCRATCH1_BITS64_REG_mask();
1533 }
1534 #endif // PPC port
1535 
1536 // =============================================================================
1537 
1538 // Figure out which register class each belongs in: rc_int, rc_float or
1539 // rc_stack.
1540 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1541 
1542 static enum RC rc_class(OptoReg::Name reg) {
1543   // Return the register class for the given register. The given register
1544   // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1545   // enumeration in adGlobals_ppc.hpp.
1546 
1547   if (reg == OptoReg::Bad) return rc_bad;
1548 
1549   // We have 64 integer register halves, starting at index 0.
1550   if (reg < 64) return rc_int;
1551 
1552   // We have 64 floating-point register halves, starting at index 64.
1553   if (reg < 64+64) return rc_float;
1554 
1555   // Between float regs & stack are the flags regs.
1556   assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1557 
1558   return rc_stack;
1559 }
1560 
1561 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1562                         bool do_print, Compile* C, outputStream *st) {
1563 
1564   assert(opcode == Assembler::LD_OPCODE   ||
1565          opcode == Assembler::STD_OPCODE  ||
1566          opcode == Assembler::LWZ_OPCODE  ||
1567          opcode == Assembler::STW_OPCODE  ||
1568          opcode == Assembler::LFD_OPCODE  ||
1569          opcode == Assembler::STFD_OPCODE ||
1570          opcode == Assembler::LFS_OPCODE  ||
1571          opcode == Assembler::STFS_OPCODE,
1572          "opcode not supported");
1573 
1574   if (cbuf) {
1575     int d =
1576       (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1577         Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1578       : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1579     emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1580   }
1581 #ifndef PRODUCT
1582   else if (do_print) {
1583     st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1584               op_str,
1585               Matcher::regName[reg],
1586               offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1587   }
1588 #endif
1589   return 4; // size
1590 }
1591 
1592 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1593   Compile* C = ra_->C;
1594 
1595   // Get registers to move.
1596   OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1597   OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1598   OptoReg::Name dst_hi = ra_->get_reg_second(this);
1599   OptoReg::Name dst_lo = ra_->get_reg_first(this);
1600 
1601   enum RC src_hi_rc = rc_class(src_hi);
1602   enum RC src_lo_rc = rc_class(src_lo);
1603   enum RC dst_hi_rc = rc_class(dst_hi);
1604   enum RC dst_lo_rc = rc_class(dst_lo);
1605 
1606   assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1607   if (src_hi != OptoReg::Bad)
1608     assert((src_lo&1)==0 && src_lo+1==src_hi &&
1609            (dst_lo&1)==0 && dst_lo+1==dst_hi,
1610            "expected aligned-adjacent pairs");
1611   // Generate spill code!
1612   int size = 0;
1613 
1614   if (src_lo == dst_lo && src_hi == dst_hi)
1615     return size;            // Self copy, no move.
1616 
1617   // --------------------------------------
1618   // Memory->Memory Spill. Use R0 to hold the value.
1619   if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1620     int src_offset = ra_->reg2offset(src_lo);
1621     int dst_offset = ra_->reg2offset(dst_lo);
1622     if (src_hi != OptoReg::Bad) {
1623       assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1624              "expected same type of move for high parts");
1625       size += ld_st_helper(cbuf, "LD  ", Assembler::LD_OPCODE,  R0_num, src_offset, !do_size, C, st);
1626       if (!cbuf && !do_size) st->print("\n\t");
1627       size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1628     } else {
1629       size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1630       if (!cbuf && !do_size) st->print("\n\t");
1631       size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1632     }
1633     return size;
1634   }
1635 
1636   // --------------------------------------
1637   // Check for float->int copy; requires a trip through memory.
1638   if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1639     Unimplemented();
1640   }
1641 
1642   // --------------------------------------
1643   // Check for integer reg-reg copy.
1644   if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1645       Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1646       Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1647       size = (Rsrc != Rdst) ? 4 : 0;
1648 
1649       if (cbuf) {
1650         MacroAssembler _masm(cbuf);
1651         if (size) {
1652           __ mr(Rdst, Rsrc);
1653         }
1654       }
1655 #ifndef PRODUCT
1656       else if (!do_size) {
1657         if (size) {
1658           st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1659         } else {
1660           st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1661         }
1662       }
1663 #endif
1664       return size;
1665   }
1666 
1667   // Check for integer store.
1668   if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1669     int dst_offset = ra_->reg2offset(dst_lo);
1670     if (src_hi != OptoReg::Bad) {
1671       assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1672              "expected same type of move for high parts");
1673       size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1674     } else {
1675       size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1676     }
1677     return size;
1678   }
1679 
1680   // Check for integer load.
1681   if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1682     int src_offset = ra_->reg2offset(src_lo);
1683     if (src_hi != OptoReg::Bad) {
1684       assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1685              "expected same type of move for high parts");
1686       size += ld_st_helper(cbuf, "LD  ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1687     } else {
1688       size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1689     }
1690     return size;
1691   }
1692 
1693   // Check for float reg-reg copy.
1694   if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1695     if (cbuf) {
1696       MacroAssembler _masm(cbuf);
1697       FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1698       FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1699       __ fmr(Rdst, Rsrc);
1700     }
1701 #ifndef PRODUCT
1702     else if (!do_size) {
1703       st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1704     }
1705 #endif
1706     return 4;
1707   }
1708 
1709   // Check for float store.
1710   if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1711     int dst_offset = ra_->reg2offset(dst_lo);
1712     if (src_hi != OptoReg::Bad) {
1713       assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1714              "expected same type of move for high parts");
1715       size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1716     } else {
1717       size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1718     }
1719     return size;
1720   }
1721 
1722   // Check for float load.
1723   if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1724     int src_offset = ra_->reg2offset(src_lo);
1725     if (src_hi != OptoReg::Bad) {
1726       assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1727              "expected same type of move for high parts");
1728       size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1729     } else {
1730       size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1731     }
1732     return size;
1733   }
1734 
1735   // --------------------------------------------------------------------
1736   // Check for hi bits still needing moving. Only happens for misaligned
1737   // arguments to native calls.
1738   if (src_hi == dst_hi)
1739     return size;               // Self copy; no move.
1740 
1741   assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1742   ShouldNotReachHere(); // Unimplemented
1743   return 0;
1744 }
1745 
1746 #ifndef PRODUCT
1747 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1748   if (!ra_)
1749     st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1750   else
1751     implementation(NULL, ra_, false, st);
1752 }
1753 #endif
1754 
1755 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1756   implementation(&cbuf, ra_, false, NULL);
1757 }
1758 
1759 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1760   return implementation(NULL, ra_, true, NULL);
1761 }
1762 
1763 #if 0 // TODO: PPC port
1764 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1765 #ifndef PRODUCT
1766   if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1767 #endif
1768   assert(ra_->node_regs_max_index() != 0, "");
1769 
1770   // Get registers to move.
1771   OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1772   OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1773   OptoReg::Name dst_hi = ra_->get_reg_second(n);
1774   OptoReg::Name dst_lo = ra_->get_reg_first(n);
1775 
1776   enum RC src_lo_rc = rc_class(src_lo);
1777   enum RC dst_lo_rc = rc_class(dst_lo);
1778 
1779   if (src_lo == dst_lo && src_hi == dst_hi)
1780     return ppc64Opcode_none;            // Self copy, no move.
1781 
1782   // --------------------------------------
1783   // Memory->Memory Spill. Use R0 to hold the value.
1784   if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1785     return ppc64Opcode_compound;
1786   }
1787 
1788   // --------------------------------------
1789   // Check for float->int copy; requires a trip through memory.
1790   if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1791     Unimplemented();
1792   }
1793 
1794   // --------------------------------------
1795   // Check for integer reg-reg copy.
1796   if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1797     Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1798     Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1799     if (Rsrc == Rdst) {
1800       return ppc64Opcode_none;
1801     } else {
1802       return ppc64Opcode_or;
1803     }
1804   }
1805 
1806   // Check for integer store.
1807   if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1808     if (src_hi != OptoReg::Bad) {
1809       return ppc64Opcode_std;
1810     } else {
1811       return ppc64Opcode_stw;
1812     }
1813   }
1814 
1815   // Check for integer load.
1816   if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1817     if (src_hi != OptoReg::Bad) {
1818       return ppc64Opcode_ld;
1819     } else {
1820       return ppc64Opcode_lwz;
1821     }
1822   }
1823 
1824   // Check for float reg-reg copy.
1825   if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1826     return ppc64Opcode_fmr;
1827   }
1828 
1829   // Check for float store.
1830   if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1831     if (src_hi != OptoReg::Bad) {
1832       return ppc64Opcode_stfd;
1833     } else {
1834       return ppc64Opcode_stfs;
1835     }
1836   }
1837 
1838   // Check for float load.
1839   if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1840     if (src_hi != OptoReg::Bad) {
1841       return ppc64Opcode_lfd;
1842     } else {
1843       return ppc64Opcode_lfs;
1844     }
1845   }
1846 
1847   // --------------------------------------------------------------------
1848   // Check for hi bits still needing moving. Only happens for misaligned
1849   // arguments to native calls.
1850   if (src_hi == dst_hi) {
1851     return ppc64Opcode_none;               // Self copy; no move.
1852   }
1853 
1854   ShouldNotReachHere();
1855   return ppc64Opcode_undefined;
1856 }
1857 #endif // PPC port
1858 
1859 #ifndef PRODUCT
1860 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1861   st->print("NOP \t// %d nops to pad for loops.", _count);
1862 }
1863 #endif
1864 
1865 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1866   MacroAssembler _masm(&cbuf);
1867   // _count contains the number of nops needed for padding.
1868   for (int i = 0; i < _count; i++) {
1869     __ nop();
1870   }
1871 }
1872 
1873 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1874   return _count * 4;
1875 }
1876 
1877 #ifndef PRODUCT
1878 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1879   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1880   char reg_str[128];
1881   ra_->dump_register(this, reg_str);
1882   st->print("ADDI    %s, SP, %d \t// box node", reg_str, offset);
1883 }
1884 #endif
1885 
1886 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1887   MacroAssembler _masm(&cbuf);
1888 
1889   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1890   int reg    = ra_->get_encode(this);
1891 
1892   if (Assembler::is_simm(offset, 16)) {
1893     __ addi(as_Register(reg), R1, offset);
1894   } else {
1895     ShouldNotReachHere();
1896   }
1897 }
1898 
1899 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1900   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1901   return 4;
1902 }
1903 
1904 #ifndef PRODUCT
1905 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1906   st->print_cr("---- MachUEPNode ----");
1907   st->print_cr("...");
1908 }
1909 #endif
1910 
1911 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1912   // This is the unverified entry point.
1913   MacroAssembler _masm(&cbuf);
1914 
1915   // Inline_cache contains a klass.
1916   Register ic_klass       = as_Register(Matcher::inline_cache_reg_encode());
1917   Register receiver_klass = R12_scratch2;  // tmp
1918 
1919   assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
1920   assert(R11_scratch1 == R11, "need prologue scratch register");
1921 
1922   // Check for NULL argument if we don't have implicit null checks.
1923   if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
1924     if (TrapBasedNullChecks) {
1925       __ trap_null_check(R3_ARG1);
1926     } else {
1927       Label valid;
1928       __ cmpdi(CCR0, R3_ARG1, 0);
1929       __ bne_predict_taken(CCR0, valid);
1930       // We have a null argument, branch to ic_miss_stub.
1931       __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1932                            relocInfo::runtime_call_type);
1933       __ bind(valid);
1934     }
1935   }
1936   // Assume argument is not NULL, load klass from receiver.
1937   __ load_klass(receiver_klass, R3_ARG1);
1938 
1939   if (TrapBasedICMissChecks) {
1940     __ trap_ic_miss_check(receiver_klass, ic_klass);
1941   } else {
1942     Label valid;
1943     __ cmpd(CCR0, receiver_klass, ic_klass);
1944     __ beq_predict_taken(CCR0, valid);
1945     // We have an unexpected klass, branch to ic_miss_stub.
1946     __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1947                          relocInfo::runtime_call_type);
1948     __ bind(valid);
1949   }
1950 
1951   // Argument is valid and klass is as expected, continue.
1952 }
1953 
1954 #if 0 // TODO: PPC port
1955 // Optimize UEP code on z (save a load_const() call in main path).
1956 int MachUEPNode::ep_offset() {
1957   return 0;
1958 }
1959 #endif
1960 
1961 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1962   // Variable size. Determine dynamically.
1963   return MachNode::size(ra_);
1964 }
1965 
1966 //=============================================================================
1967 
1968 %} // interrupt source
1969 
1970 source_hpp %{ // Header information of the source block.
1971 
1972 class HandlerImpl {
1973 
1974  public:
1975 
1976   static int emit_exception_handler(CodeBuffer &cbuf);
1977   static int emit_deopt_handler(CodeBuffer& cbuf);
1978 
1979   static uint size_exception_handler() {
1980     // The exception_handler is a b64_patchable.
1981     return MacroAssembler::b64_patchable_size;
1982   }
1983 
1984   static uint size_deopt_handler() {
1985     // The deopt_handler is a bl64_patchable.
1986     return MacroAssembler::bl64_patchable_size;
1987   }
1988 
1989 };
1990 
1991 %} // end source_hpp
1992 
1993 source %{
1994 
1995 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
1996   MacroAssembler _masm(&cbuf);
1997 
1998   address base = __ start_a_stub(size_exception_handler());
1999   if (base == NULL) return 0; // CodeBuffer::expand failed
2000 
2001   int offset = __ offset();
2002   __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
2003                        relocInfo::runtime_call_type);
2004   assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
2005   __ end_a_stub();
2006 
2007   return offset;
2008 }
2009 
2010 // The deopt_handler is like the exception handler, but it calls to
2011 // the deoptimization blob instead of jumping to the exception blob.
2012 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
2013   MacroAssembler _masm(&cbuf);
2014 
2015   address base = __ start_a_stub(size_deopt_handler());
2016   if (base == NULL) return 0; // CodeBuffer::expand failed
2017 
2018   int offset = __ offset();
2019   __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
2020                         relocInfo::runtime_call_type);
2021   assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
2022   __ end_a_stub();
2023 
2024   return offset;
2025 }
2026 
2027 //=============================================================================
2028 
2029 // Use a frame slots bias for frameless methods if accessing the stack.
2030 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2031   if (as_Register(reg_enc) == R1_SP) {
2032     return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2033   }
2034   return 0;
2035 }
2036 
2037 const bool Matcher::match_rule_supported(int opcode) {
2038   if (!has_match_rule(opcode))
2039     return false;
2040 
2041   switch (opcode) {
2042   case Op_SqrtD:
2043     return VM_Version::has_fsqrt();
2044   case Op_CountLeadingZerosI:
2045   case Op_CountLeadingZerosL:
2046   case Op_CountTrailingZerosI:
2047   case Op_CountTrailingZerosL:
2048     if (!UseCountLeadingZerosInstructionsPPC64)
2049       return false;
2050     break;
2051 
2052   case Op_PopCountI:
2053   case Op_PopCountL:
2054     return (UsePopCountInstruction && VM_Version::has_popcntw());
2055 
2056   case Op_StrComp:
2057     return SpecialStringCompareTo;
2058   case Op_StrEquals:
2059     return SpecialStringEquals;
2060   case Op_StrIndexOf:
2061     return SpecialStringIndexOf;
2062   }
2063 
2064   return true;  // Per default match rules are supported.
2065 }
2066 
2067 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
2068 
2069   // TODO
2070   // identify extra cases that we might want to provide match rules for
2071   // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
2072   if (!has_match_rule(opcode)) {
2073     return false;
2074   }
2075 
2076   bool ret_value = match_rule_supported(opcode);
2077   // Add rules here.
2078 
2079   return ret_value;  // Per default match rules are supported.
2080 }
2081 
2082 const int Matcher::float_pressure(int default_pressure_threshold) {
2083   return default_pressure_threshold;
2084 }
2085 
2086 int Matcher::regnum_to_fpu_offset(int regnum) {
2087   // No user for this method?
2088   Unimplemented();
2089   return 999;
2090 }
2091 
2092 const bool Matcher::convL2FSupported(void) {
2093   // fcfids can do the conversion (>= Power7).
2094   // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2095   return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2096 }
2097 
2098 // Vector width in bytes.
2099 const int Matcher::vector_width_in_bytes(BasicType bt) {
2100   assert(MaxVectorSize == 8, "");
2101   return 8;
2102 }
2103 
2104 // Vector ideal reg.
2105 const int Matcher::vector_ideal_reg(int size) {
2106   assert(MaxVectorSize == 8 && size == 8, "");
2107   return Op_RegL;
2108 }
2109 
2110 const int Matcher::vector_shift_count_ideal_reg(int size) {
2111   fatal("vector shift is not supported");
2112   return Node::NotAMachineReg;
2113 }
2114 
2115 // Limits on vector size (number of elements) loaded into vector.
2116 const int Matcher::max_vector_size(const BasicType bt) {
2117   assert(is_java_primitive(bt), "only primitive type vectors");
2118   return vector_width_in_bytes(bt)/type2aelembytes(bt);
2119 }
2120 
2121 const int Matcher::min_vector_size(const BasicType bt) {
2122   return max_vector_size(bt); // Same as max.
2123 }
2124 
2125 // PPC doesn't support misaligned vectors store/load.
2126 const bool Matcher::misaligned_vectors_ok() {
2127   return false;
2128 }
2129 
2130 // PPC AES support not yet implemented
2131 const bool Matcher::pass_original_key_for_aes() {
2132   return false;
2133 }
2134 
2135 // RETURNS: whether this branch offset is short enough that a short
2136 // branch can be used.
2137 //
2138 // If the platform does not provide any short branch variants, then
2139 // this method should return `false' for offset 0.
2140 //
2141 // `Compile::Fill_buffer' will decide on basis of this information
2142 // whether to do the pass `Compile::Shorten_branches' at all.
2143 //
2144 // And `Compile::Shorten_branches' will decide on basis of this
2145 // information whether to replace particular branch sites by short
2146 // ones.
2147 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2148   // Is the offset within the range of a ppc64 pc relative branch?
2149   bool b;
2150 
2151   const int safety_zone = 3 * BytesPerInstWord;
2152   b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2153                          29 - 16 + 1 + 2);
2154   return b;
2155 }
2156 
2157 const bool Matcher::isSimpleConstant64(jlong value) {
2158   // Probably always true, even if a temp register is required.
2159   return true;
2160 }
2161 /* TODO: PPC port
2162 // Make a new machine dependent decode node (with its operands).
2163 MachTypeNode *Matcher::make_decode_node() {
2164   assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2165          "This method is only implemented for unscaled cOops mode so far");
2166   MachTypeNode *decode = new decodeN_unscaledNode();
2167   decode->set_opnd_array(0, new iRegPdstOper());
2168   decode->set_opnd_array(1, new iRegNsrcOper());
2169   return decode;
2170 }
2171 */
2172 // Threshold size for cleararray.
2173 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2174 
2175 // false => size gets scaled to BytesPerLong, ok.
2176 const bool Matcher::init_array_count_is_in_bytes = false;
2177 
2178 // Use conditional move (CMOVL) on Power7.
2179 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2180 
2181 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2182 // fsel doesn't accept a condition register as input, so this would be slightly different.
2183 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2184 
2185 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2186 const bool Matcher::require_postalloc_expand = true;
2187 
2188 // Should the Matcher clone shifts on addressing modes, expecting them to
2189 // be subsumed into complex addressing expressions or compute them into
2190 // registers? True for Intel but false for most RISCs.
2191 const bool Matcher::clone_shift_expressions = false;
2192 
2193 // Do we need to mask the count passed to shift instructions or does
2194 // the cpu only look at the lower 5/6 bits anyway?
2195 // PowerPC requires masked shift counts.
2196 const bool Matcher::need_masked_shift_count = true;
2197 
2198 // This affects two different things:
2199 //  - how Decode nodes are matched
2200 //  - how ImplicitNullCheck opportunities are recognized
2201 // If true, the matcher will try to remove all Decodes and match them
2202 // (as operands) into nodes. NullChecks are not prepared to deal with
2203 // Decodes by final_graph_reshaping().
2204 // If false, final_graph_reshaping() forces the decode behind the Cmp
2205 // for a NullCheck. The matcher matches the Decode node into a register.
2206 // Implicit_null_check optimization moves the Decode along with the
2207 // memory operation back up before the NullCheck.
2208 bool Matcher::narrow_oop_use_complex_address() {
2209   // TODO: PPC port if (MatchDecodeNodes) return true;
2210   return false;
2211 }
2212 
2213 bool Matcher::narrow_klass_use_complex_address() {
2214   NOT_LP64(ShouldNotCallThis());
2215   assert(UseCompressedClassPointers, "only for compressed klass code");
2216   // TODO: PPC port if (MatchDecodeNodes) return true;
2217   return false;
2218 }
2219 
2220 // Is it better to copy float constants, or load them directly from memory?
2221 // Intel can load a float constant from a direct address, requiring no
2222 // extra registers. Most RISCs will have to materialize an address into a
2223 // register first, so they would do better to copy the constant from stack.
2224 const bool Matcher::rematerialize_float_constants = false;
2225 
2226 // If CPU can load and store mis-aligned doubles directly then no fixup is
2227 // needed. Else we split the double into 2 integer pieces and move it
2228 // piece-by-piece. Only happens when passing doubles into C code as the
2229 // Java calling convention forces doubles to be aligned.
2230 const bool Matcher::misaligned_doubles_ok = true;
2231 
2232 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2233  Unimplemented();
2234 }
2235 
2236 // Advertise here if the CPU requires explicit rounding operations
2237 // to implement the UseStrictFP mode.
2238 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2239 
2240 // Do floats take an entire double register or just half?
2241 //
2242 // A float occupies a ppc64 double register. For the allocator, a
2243 // ppc64 double register appears as a pair of float registers.
2244 bool Matcher::float_in_double() { return true; }
2245 
2246 // Do ints take an entire long register or just half?
2247 // The relevant question is how the int is callee-saved:
2248 // the whole long is written but de-opt'ing will have to extract
2249 // the relevant 32 bits.
2250 const bool Matcher::int_in_long = true;
2251 
2252 // Constants for c2c and c calling conventions.
2253 
2254 const MachRegisterNumbers iarg_reg[8] = {
2255   R3_num, R4_num, R5_num, R6_num,
2256   R7_num, R8_num, R9_num, R10_num
2257 };
2258 
2259 const MachRegisterNumbers farg_reg[13] = {
2260   F1_num, F2_num, F3_num, F4_num,
2261   F5_num, F6_num, F7_num, F8_num,
2262   F9_num, F10_num, F11_num, F12_num,
2263   F13_num
2264 };
2265 
2266 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2267 
2268 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2269 
2270 // Return whether or not this register is ever used as an argument. This
2271 // function is used on startup to build the trampoline stubs in generateOptoStub.
2272 // Registers not mentioned will be killed by the VM call in the trampoline, and
2273 // arguments in those registers not be available to the callee.
2274 bool Matcher::can_be_java_arg(int reg) {
2275   // We return true for all registers contained in iarg_reg[] and
2276   // farg_reg[] and their virtual halves.
2277   // We must include the virtual halves in order to get STDs and LDs
2278   // instead of STWs and LWs in the trampoline stubs.
2279 
2280   if (   reg == R3_num  || reg == R3_H_num
2281       || reg == R4_num  || reg == R4_H_num
2282       || reg == R5_num  || reg == R5_H_num
2283       || reg == R6_num  || reg == R6_H_num
2284       || reg == R7_num  || reg == R7_H_num
2285       || reg == R8_num  || reg == R8_H_num
2286       || reg == R9_num  || reg == R9_H_num
2287       || reg == R10_num || reg == R10_H_num)
2288     return true;
2289 
2290   if (   reg == F1_num  || reg == F1_H_num
2291       || reg == F2_num  || reg == F2_H_num
2292       || reg == F3_num  || reg == F3_H_num
2293       || reg == F4_num  || reg == F4_H_num
2294       || reg == F5_num  || reg == F5_H_num
2295       || reg == F6_num  || reg == F6_H_num
2296       || reg == F7_num  || reg == F7_H_num
2297       || reg == F8_num  || reg == F8_H_num
2298       || reg == F9_num  || reg == F9_H_num
2299       || reg == F10_num || reg == F10_H_num
2300       || reg == F11_num || reg == F11_H_num
2301       || reg == F12_num || reg == F12_H_num
2302       || reg == F13_num || reg == F13_H_num)
2303     return true;
2304 
2305   return false;
2306 }
2307 
2308 bool Matcher::is_spillable_arg(int reg) {
2309   return can_be_java_arg(reg);
2310 }
2311 
2312 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2313   return false;
2314 }
2315 
2316 // Register for DIVI projection of divmodI.
2317 RegMask Matcher::divI_proj_mask() {
2318   ShouldNotReachHere();
2319   return RegMask();
2320 }
2321 
2322 // Register for MODI projection of divmodI.
2323 RegMask Matcher::modI_proj_mask() {
2324   ShouldNotReachHere();
2325   return RegMask();
2326 }
2327 
2328 // Register for DIVL projection of divmodL.
2329 RegMask Matcher::divL_proj_mask() {
2330   ShouldNotReachHere();
2331   return RegMask();
2332 }
2333 
2334 // Register for MODL projection of divmodL.
2335 RegMask Matcher::modL_proj_mask() {
2336   ShouldNotReachHere();
2337   return RegMask();
2338 }
2339 
2340 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2341   return RegMask();
2342 }
2343 
2344 %}
2345 
2346 //----------ENCODING BLOCK-----------------------------------------------------
2347 // This block specifies the encoding classes used by the compiler to output
2348 // byte streams. Encoding classes are parameterized macros used by
2349 // Machine Instruction Nodes in order to generate the bit encoding of the
2350 // instruction. Operands specify their base encoding interface with the
2351 // interface keyword. There are currently supported four interfaces,
2352 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2353 // operand to generate a function which returns its register number when
2354 // queried. CONST_INTER causes an operand to generate a function which
2355 // returns the value of the constant when queried. MEMORY_INTER causes an
2356 // operand to generate four functions which return the Base Register, the
2357 // Index Register, the Scale Value, and the Offset Value of the operand when
2358 // queried. COND_INTER causes an operand to generate six functions which
2359 // return the encoding code (ie - encoding bits for the instruction)
2360 // associated with each basic boolean condition for a conditional instruction.
2361 //
2362 // Instructions specify two basic values for encoding. Again, a function
2363 // is available to check if the constant displacement is an oop. They use the
2364 // ins_encode keyword to specify their encoding classes (which must be
2365 // a sequence of enc_class names, and their parameters, specified in
2366 // the encoding block), and they use the
2367 // opcode keyword to specify, in order, their primary, secondary, and
2368 // tertiary opcode. Only the opcode sections which a particular instruction
2369 // needs for encoding need to be specified.
2370 encode %{
2371   enc_class enc_unimplemented %{
2372     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2373     MacroAssembler _masm(&cbuf);
2374     __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2375   %}
2376 
2377   enc_class enc_untested %{
2378 #ifdef ASSERT
2379     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2380     MacroAssembler _masm(&cbuf);
2381     __ untested("Untested mach node encoding in AD file.");
2382 #else
2383     // TODO: PPC port $archOpcode(ppc64Opcode_none);
2384 #endif
2385   %}
2386 
2387   enc_class enc_lbz(iRegIdst dst, memory mem) %{
2388     // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2389     MacroAssembler _masm(&cbuf);
2390     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2391     __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2392   %}
2393 
2394   // Load acquire.
2395   enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2396     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2397     MacroAssembler _masm(&cbuf);
2398     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2399     __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2400     __ twi_0($dst$$Register);
2401     __ isync();
2402   %}
2403 
2404   enc_class enc_lhz(iRegIdst dst, memory mem) %{
2405     // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2406 
2407     MacroAssembler _masm(&cbuf);
2408     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2409     __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2410   %}
2411 
2412   // Load acquire.
2413   enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2414     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2415 
2416     MacroAssembler _masm(&cbuf);
2417     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2418     __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2419     __ twi_0($dst$$Register);
2420     __ isync();
2421   %}
2422 
2423   enc_class enc_lwz(iRegIdst dst, memory mem) %{
2424     // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2425 
2426     MacroAssembler _masm(&cbuf);
2427     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2428     __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2429   %}
2430 
2431   // Load acquire.
2432   enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2433     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2434 
2435     MacroAssembler _masm(&cbuf);
2436     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2437     __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2438     __ twi_0($dst$$Register);
2439     __ isync();
2440   %}
2441 
2442   enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2443     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2444     MacroAssembler _masm(&cbuf);
2445     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2446     // Operand 'ds' requires 4-alignment.
2447     assert((Idisp & 0x3) == 0, "unaligned offset");
2448     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2449   %}
2450 
2451   // Load acquire.
2452   enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2453     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2454     MacroAssembler _masm(&cbuf);
2455     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2456     // Operand 'ds' requires 4-alignment.
2457     assert((Idisp & 0x3) == 0, "unaligned offset");
2458     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2459     __ twi_0($dst$$Register);
2460     __ isync();
2461   %}
2462 
2463   enc_class enc_lfd(RegF dst, memory mem) %{
2464     // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2465     MacroAssembler _masm(&cbuf);
2466     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2467     __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2468   %}
2469 
2470   enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2471     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2472 
2473     MacroAssembler _masm(&cbuf);
2474     int toc_offset = 0;
2475 
2476     if (!ra_->C->in_scratch_emit_size()) {
2477       address const_toc_addr;
2478       // Create a non-oop constant, no relocation needed.
2479       // If it is an IC, it has a virtual_call_Relocation.
2480       const_toc_addr = __ long_constant((jlong)$src$$constant);
2481 
2482       // Get the constant's TOC offset.
2483       toc_offset = __ offset_to_method_toc(const_toc_addr);
2484 
2485       // Keep the current instruction offset in mind.
2486       ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2487     }
2488 
2489     __ ld($dst$$Register, toc_offset, $toc$$Register);
2490   %}
2491 
2492   enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2493     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2494 
2495     MacroAssembler _masm(&cbuf);
2496 
2497     if (!ra_->C->in_scratch_emit_size()) {
2498       address const_toc_addr;
2499       // Create a non-oop constant, no relocation needed.
2500       // If it is an IC, it has a virtual_call_Relocation.
2501       const_toc_addr = __ long_constant((jlong)$src$$constant);
2502 
2503       // Get the constant's TOC offset.
2504       const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2505       // Store the toc offset of the constant.
2506       ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2507 
2508       // Also keep the current instruction offset in mind.
2509       ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2510     }
2511 
2512     __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2513   %}
2514 
2515 %} // encode
2516 
2517 source %{
2518 
2519 typedef struct {
2520   loadConL_hiNode *_large_hi;
2521   loadConL_loNode *_large_lo;
2522   loadConLNode    *_small;
2523   MachNode        *_last;
2524 } loadConLNodesTuple;
2525 
2526 loadConLNodesTuple loadConLNodesTuple_create(PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2527                                              OptoReg::Name reg_second, OptoReg::Name reg_first) {
2528   loadConLNodesTuple nodes;
2529 
2530   const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2531   if (large_constant_pool) {
2532     // Create new nodes.
2533     loadConL_hiNode *m1 = new loadConL_hiNode();
2534     loadConL_loNode *m2 = new loadConL_loNode();
2535 
2536     // inputs for new nodes
2537     m1->add_req(NULL, toc);
2538     m2->add_req(NULL, m1);
2539 
2540     // operands for new nodes
2541     m1->_opnds[0] = new iRegLdstOper(); // dst
2542     m1->_opnds[1] = immSrc;             // src
2543     m1->_opnds[2] = new iRegPdstOper(); // toc
2544     m2->_opnds[0] = new iRegLdstOper(); // dst
2545     m2->_opnds[1] = immSrc;             // src
2546     m2->_opnds[2] = new iRegLdstOper(); // base
2547 
2548     // Initialize ins_attrib TOC fields.
2549     m1->_const_toc_offset = -1;
2550     m2->_const_toc_offset_hi_node = m1;
2551 
2552     // Initialize ins_attrib instruction offset.
2553     m1->_cbuf_insts_offset = -1;
2554 
2555     // register allocation for new nodes
2556     ra_->set_pair(m1->_idx, reg_second, reg_first);
2557     ra_->set_pair(m2->_idx, reg_second, reg_first);
2558 
2559     // Create result.
2560     nodes._large_hi = m1;
2561     nodes._large_lo = m2;
2562     nodes._small = NULL;
2563     nodes._last = nodes._large_lo;
2564     assert(m2->bottom_type()->isa_long(), "must be long");
2565   } else {
2566     loadConLNode *m2 = new loadConLNode();
2567 
2568     // inputs for new nodes
2569     m2->add_req(NULL, toc);
2570 
2571     // operands for new nodes
2572     m2->_opnds[0] = new iRegLdstOper(); // dst
2573     m2->_opnds[1] = immSrc;             // src
2574     m2->_opnds[2] = new iRegPdstOper(); // toc
2575 
2576     // Initialize ins_attrib instruction offset.
2577     m2->_cbuf_insts_offset = -1;
2578 
2579     // register allocation for new nodes
2580     ra_->set_pair(m2->_idx, reg_second, reg_first);
2581 
2582     // Create result.
2583     nodes._large_hi = NULL;
2584     nodes._large_lo = NULL;
2585     nodes._small = m2;
2586     nodes._last = nodes._small;
2587     assert(m2->bottom_type()->isa_long(), "must be long");
2588   }
2589 
2590   return nodes;
2591 }
2592 
2593 %} // source
2594 
2595 encode %{
2596   // Postalloc expand emitter for loading a long constant from the method's TOC.
2597   // Enc_class needed as consttanttablebase is not supported by postalloc
2598   // expand.
2599   enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2600     // Create new nodes.
2601     loadConLNodesTuple loadConLNodes =
2602       loadConLNodesTuple_create(ra_, n_toc, op_src,
2603                                 ra_->get_reg_second(this), ra_->get_reg_first(this));
2604 
2605     // Push new nodes.
2606     if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2607     if (loadConLNodes._last)     nodes->push(loadConLNodes._last);
2608 
2609     // some asserts
2610     assert(nodes->length() >= 1, "must have created at least 1 node");
2611     assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2612   %}
2613 
2614   enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2615     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2616 
2617     MacroAssembler _masm(&cbuf);
2618     int toc_offset = 0;
2619 
2620     if (!ra_->C->in_scratch_emit_size()) {
2621       intptr_t val = $src$$constant;
2622       relocInfo::relocType constant_reloc = $src->constant_reloc();  // src
2623       address const_toc_addr;
2624       if (constant_reloc == relocInfo::oop_type) {
2625         // Create an oop constant and a corresponding relocation.
2626         AddressLiteral a = __ allocate_oop_address((jobject)val);
2627         const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2628         __ relocate(a.rspec());
2629       } else if (constant_reloc == relocInfo::metadata_type) {
2630         AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2631         const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2632         __ relocate(a.rspec());
2633       } else {
2634         // Create a non-oop constant, no relocation needed.
2635         const_toc_addr = __ long_constant((jlong)$src$$constant);
2636       }
2637 
2638       // Get the constant's TOC offset.
2639       toc_offset = __ offset_to_method_toc(const_toc_addr);
2640     }
2641 
2642     __ ld($dst$$Register, toc_offset, $toc$$Register);
2643   %}
2644 
2645   enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2646     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2647 
2648     MacroAssembler _masm(&cbuf);
2649     if (!ra_->C->in_scratch_emit_size()) {
2650       intptr_t val = $src$$constant;
2651       relocInfo::relocType constant_reloc = $src->constant_reloc();  // src
2652       address const_toc_addr;
2653       if (constant_reloc == relocInfo::oop_type) {
2654         // Create an oop constant and a corresponding relocation.
2655         AddressLiteral a = __ allocate_oop_address((jobject)val);
2656         const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2657         __ relocate(a.rspec());
2658       } else if (constant_reloc == relocInfo::metadata_type) {
2659         AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2660         const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2661         __ relocate(a.rspec());
2662       } else {  // non-oop pointers, e.g. card mark base, heap top
2663         // Create a non-oop constant, no relocation needed.
2664         const_toc_addr = __ long_constant((jlong)$src$$constant);
2665       }
2666 
2667       // Get the constant's TOC offset.
2668       const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2669       // Store the toc offset of the constant.
2670       ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2671     }
2672 
2673     __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2674   %}
2675 
2676   // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2677   // Enc_class needed as consttanttablebase is not supported by postalloc
2678   // expand.
2679   enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2680     const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2681     if (large_constant_pool) {
2682       // Create new nodes.
2683       loadConP_hiNode *m1 = new loadConP_hiNode();
2684       loadConP_loNode *m2 = new loadConP_loNode();
2685 
2686       // inputs for new nodes
2687       m1->add_req(NULL, n_toc);
2688       m2->add_req(NULL, m1);
2689 
2690       // operands for new nodes
2691       m1->_opnds[0] = new iRegPdstOper(); // dst
2692       m1->_opnds[1] = op_src;             // src
2693       m1->_opnds[2] = new iRegPdstOper(); // toc
2694       m2->_opnds[0] = new iRegPdstOper(); // dst
2695       m2->_opnds[1] = op_src;             // src
2696       m2->_opnds[2] = new iRegLdstOper(); // base
2697 
2698       // Initialize ins_attrib TOC fields.
2699       m1->_const_toc_offset = -1;
2700       m2->_const_toc_offset_hi_node = m1;
2701 
2702       // Register allocation for new nodes.
2703       ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2704       ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2705 
2706       nodes->push(m1);
2707       nodes->push(m2);
2708       assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2709     } else {
2710       loadConPNode *m2 = new loadConPNode();
2711 
2712       // inputs for new nodes
2713       m2->add_req(NULL, n_toc);
2714 
2715       // operands for new nodes
2716       m2->_opnds[0] = new iRegPdstOper(); // dst
2717       m2->_opnds[1] = op_src;             // src
2718       m2->_opnds[2] = new iRegPdstOper(); // toc
2719 
2720       // Register allocation for new nodes.
2721       ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2722 
2723       nodes->push(m2);
2724       assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2725     }
2726   %}
2727 
2728   // Enc_class needed as consttanttablebase is not supported by postalloc
2729   // expand.
2730   enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2731     bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2732 
2733     MachNode *m2;
2734     if (large_constant_pool) {
2735       m2 = new loadConFCompNode();
2736     } else {
2737       m2 = new loadConFNode();
2738     }
2739     // inputs for new nodes
2740     m2->add_req(NULL, n_toc);
2741 
2742     // operands for new nodes
2743     m2->_opnds[0] = op_dst;
2744     m2->_opnds[1] = op_src;
2745     m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2746 
2747     // register allocation for new nodes
2748     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2749     nodes->push(m2);
2750   %}
2751 
2752   // Enc_class needed as consttanttablebase is not supported by postalloc
2753   // expand.
2754   enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2755     bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2756 
2757     MachNode *m2;
2758     if (large_constant_pool) {
2759       m2 = new loadConDCompNode();
2760     } else {
2761       m2 = new loadConDNode();
2762     }
2763     // inputs for new nodes
2764     m2->add_req(NULL, n_toc);
2765 
2766     // operands for new nodes
2767     m2->_opnds[0] = op_dst;
2768     m2->_opnds[1] = op_src;
2769     m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2770 
2771     // register allocation for new nodes
2772     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2773     nodes->push(m2);
2774   %}
2775 
2776   enc_class enc_stw(iRegIsrc src, memory mem) %{
2777     // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2778     MacroAssembler _masm(&cbuf);
2779     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2780     __ stw($src$$Register, Idisp, $mem$$base$$Register);
2781   %}
2782 
2783   enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2784     // TODO: PPC port $archOpcode(ppc64Opcode_std);
2785     MacroAssembler _masm(&cbuf);
2786     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2787     // Operand 'ds' requires 4-alignment.
2788     assert((Idisp & 0x3) == 0, "unaligned offset");
2789     __ std($src$$Register, Idisp, $mem$$base$$Register);
2790   %}
2791 
2792   enc_class enc_stfs(RegF src, memory mem) %{
2793     // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2794     MacroAssembler _masm(&cbuf);
2795     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2796     __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2797   %}
2798 
2799   enc_class enc_stfd(RegF src, memory mem) %{
2800     // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2801     MacroAssembler _masm(&cbuf);
2802     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2803     __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2804   %}
2805 
2806   // Use release_store for card-marking to ensure that previous
2807   // oop-stores are visible before the card-mark change.
2808   enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
2809     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2810     // FIXME: Implement this as a cmove and use a fixed condition code
2811     // register which is written on every transition to compiled code,
2812     // e.g. in call-stub and when returning from runtime stubs.
2813     //
2814     // Proposed code sequence for the cmove implementation:
2815     //
2816     // Label skip_release;
2817     // __ beq(CCRfixed, skip_release);
2818     // __ release();
2819     // __ bind(skip_release);
2820     // __ stb(card mark);
2821 
2822     MacroAssembler _masm(&cbuf);
2823     Label skip_storestore;
2824 
2825 #if 0 // TODO: PPC port
2826     // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2827     // StoreStore barrier conditionally.
2828     __ lwz(R0, 0, $releaseFieldAddr$$Register);
2829     __ cmpwi($crx$$CondRegister, R0, 0);
2830     __ beq_predict_taken($crx$$CondRegister, skip_storestore);
2831 #endif
2832     __ li(R0, 0);
2833     __ membar(Assembler::StoreStore);
2834 #if 0 // TODO: PPC port
2835     __ bind(skip_storestore);
2836 #endif
2837 
2838     // Do the store.
2839     if ($mem$$index == 0) {
2840       __ stb(R0, $mem$$disp, $mem$$base$$Register);
2841     } else {
2842       assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2843       __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2844     }
2845   %}
2846 
2847   enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2848 
2849     if (VM_Version::has_isel()) {
2850       // use isel instruction with Power 7
2851       cmpP_reg_imm16Node *n_compare  = new cmpP_reg_imm16Node();
2852       encodeP_subNode    *n_sub_base = new encodeP_subNode();
2853       encodeP_shiftNode  *n_shift    = new encodeP_shiftNode();
2854       cond_set_0_oopNode *n_cond_set = new cond_set_0_oopNode();
2855 
2856       n_compare->add_req(n_region, n_src);
2857       n_compare->_opnds[0] = op_crx;
2858       n_compare->_opnds[1] = op_src;
2859       n_compare->_opnds[2] = new immL16Oper(0);
2860 
2861       n_sub_base->add_req(n_region, n_src);
2862       n_sub_base->_opnds[0] = op_dst;
2863       n_sub_base->_opnds[1] = op_src;
2864       n_sub_base->_bottom_type = _bottom_type;
2865 
2866       n_shift->add_req(n_region, n_sub_base);
2867       n_shift->_opnds[0] = op_dst;
2868       n_shift->_opnds[1] = op_dst;
2869       n_shift->_bottom_type = _bottom_type;
2870 
2871       n_cond_set->add_req(n_region, n_compare, n_shift);
2872       n_cond_set->_opnds[0] = op_dst;
2873       n_cond_set->_opnds[1] = op_crx;
2874       n_cond_set->_opnds[2] = op_dst;
2875       n_cond_set->_bottom_type = _bottom_type;
2876 
2877       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2878       ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2879       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2880       ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2881 
2882       nodes->push(n_compare);
2883       nodes->push(n_sub_base);
2884       nodes->push(n_shift);
2885       nodes->push(n_cond_set);
2886 
2887     } else {
2888       // before Power 7
2889       moveRegNode        *n_move     = new moveRegNode();
2890       cmpP_reg_imm16Node *n_compare  = new cmpP_reg_imm16Node();
2891       encodeP_shiftNode  *n_shift    = new encodeP_shiftNode();
2892       cond_sub_baseNode  *n_sub_base = new cond_sub_baseNode();
2893 
2894       n_move->add_req(n_region, n_src);
2895       n_move->_opnds[0] = op_dst;
2896       n_move->_opnds[1] = op_src;
2897       ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2898 
2899       n_compare->add_req(n_region, n_src);
2900       n_compare->add_prec(n_move);
2901 
2902       n_compare->_opnds[0] = op_crx;
2903       n_compare->_opnds[1] = op_src;
2904       n_compare->_opnds[2] = new immL16Oper(0);
2905 
2906       n_sub_base->add_req(n_region, n_compare, n_src);
2907       n_sub_base->_opnds[0] = op_dst;
2908       n_sub_base->_opnds[1] = op_crx;
2909       n_sub_base->_opnds[2] = op_src;
2910       n_sub_base->_bottom_type = _bottom_type;
2911 
2912       n_shift->add_req(n_region, n_sub_base);
2913       n_shift->_opnds[0] = op_dst;
2914       n_shift->_opnds[1] = op_dst;
2915       n_shift->_bottom_type = _bottom_type;
2916 
2917       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2918       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2919       ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2920       ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2921 
2922       nodes->push(n_move);
2923       nodes->push(n_compare);
2924       nodes->push(n_sub_base);
2925       nodes->push(n_shift);
2926     }
2927 
2928     assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2929   %}
2930 
2931   enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
2932 
2933     encodeP_subNode *n1 = new encodeP_subNode();
2934     n1->add_req(n_region, n_src);
2935     n1->_opnds[0] = op_dst;
2936     n1->_opnds[1] = op_src;
2937     n1->_bottom_type = _bottom_type;
2938 
2939     encodeP_shiftNode *n2 = new encodeP_shiftNode();
2940     n2->add_req(n_region, n1);
2941     n2->_opnds[0] = op_dst;
2942     n2->_opnds[1] = op_dst;
2943     n2->_bottom_type = _bottom_type;
2944     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2945     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2946 
2947     nodes->push(n1);
2948     nodes->push(n2);
2949     assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2950   %}
2951 
2952   enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
2953     decodeN_shiftNode *n_shift    = new decodeN_shiftNode();
2954     cmpN_reg_imm0Node *n_compare  = new cmpN_reg_imm0Node();
2955 
2956     n_compare->add_req(n_region, n_src);
2957     n_compare->_opnds[0] = op_crx;
2958     n_compare->_opnds[1] = op_src;
2959     n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
2960 
2961     n_shift->add_req(n_region, n_src);
2962     n_shift->_opnds[0] = op_dst;
2963     n_shift->_opnds[1] = op_src;
2964     n_shift->_bottom_type = _bottom_type;
2965 
2966     if (VM_Version::has_isel()) {
2967       // use isel instruction with Power 7
2968 
2969       decodeN_addNode *n_add_base = new decodeN_addNode();
2970       n_add_base->add_req(n_region, n_shift);
2971       n_add_base->_opnds[0] = op_dst;
2972       n_add_base->_opnds[1] = op_dst;
2973       n_add_base->_bottom_type = _bottom_type;
2974 
2975       cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
2976       n_cond_set->add_req(n_region, n_compare, n_add_base);
2977       n_cond_set->_opnds[0] = op_dst;
2978       n_cond_set->_opnds[1] = op_crx;
2979       n_cond_set->_opnds[2] = op_dst;
2980       n_cond_set->_bottom_type = _bottom_type;
2981 
2982       assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
2983       ra_->set_oop(n_cond_set, true);
2984 
2985       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2986       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2987       ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2988       ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2989 
2990       nodes->push(n_compare);
2991       nodes->push(n_shift);
2992       nodes->push(n_add_base);
2993       nodes->push(n_cond_set);
2994 
2995     } else {
2996       // before Power 7
2997       cond_add_baseNode *n_add_base = new cond_add_baseNode();
2998 
2999       n_add_base->add_req(n_region, n_compare, n_shift);
3000       n_add_base->_opnds[0] = op_dst;
3001       n_add_base->_opnds[1] = op_crx;
3002       n_add_base->_opnds[2] = op_dst;
3003       n_add_base->_bottom_type = _bottom_type;
3004 
3005       assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3006       ra_->set_oop(n_add_base, true);
3007 
3008       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3009       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3010       ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3011 
3012       nodes->push(n_compare);
3013       nodes->push(n_shift);
3014       nodes->push(n_add_base);
3015     }
3016   %}
3017 
3018   enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3019     decodeN_shiftNode *n1 = new decodeN_shiftNode();
3020     n1->add_req(n_region, n_src);
3021     n1->_opnds[0] = op_dst;
3022     n1->_opnds[1] = op_src;
3023     n1->_bottom_type = _bottom_type;
3024 
3025     decodeN_addNode *n2 = new decodeN_addNode();
3026     n2->add_req(n_region, n1);
3027     n2->_opnds[0] = op_dst;
3028     n2->_opnds[1] = op_dst;
3029     n2->_bottom_type = _bottom_type;
3030     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3031     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3032 
3033     assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3034     ra_->set_oop(n2, true);
3035 
3036     nodes->push(n1);
3037     nodes->push(n2);
3038   %}
3039 
3040   enc_class enc_cmove_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src, cmpOp cmp) %{
3041     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3042 
3043     MacroAssembler _masm(&cbuf);
3044     int cc        = $cmp$$cmpcode;
3045     int flags_reg = $crx$$reg;
3046     Label done;
3047     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3048     // Branch if not (cmp crx).
3049     __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3050     __ mr($dst$$Register, $src$$Register);
3051     // TODO PPC port __ endgroup_if_needed(_size == 12);
3052     __ bind(done);
3053   %}
3054 
3055   enc_class enc_cmove_imm(iRegIdst dst, flagsRegSrc crx, immI16 src, cmpOp cmp) %{
3056     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3057 
3058     MacroAssembler _masm(&cbuf);
3059     Label done;
3060     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3061     // Branch if not (cmp crx).
3062     __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3063     __ li($dst$$Register, $src$$constant);
3064     // TODO PPC port __ endgroup_if_needed(_size == 12);
3065     __ bind(done);
3066   %}
3067 
3068   // New atomics.
3069   enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3070     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3071 
3072     MacroAssembler _masm(&cbuf);
3073     Register Rtmp   = R0;
3074     Register Rres   = $res$$Register;
3075     Register Rsrc   = $src$$Register;
3076     Register Rptr   = $mem_ptr$$Register;
3077     bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3078     Register Rold   = RegCollision ? Rtmp : Rres;
3079 
3080     Label Lretry;
3081     __ bind(Lretry);
3082     __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3083     __ add(Rtmp, Rsrc, Rold);
3084     __ stwcx_(Rtmp, Rptr);
3085     if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3086       __ bne_predict_not_taken(CCR0, Lretry);
3087     } else {
3088       __ bne(                  CCR0, Lretry);
3089     }
3090     if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3091     __ fence();
3092   %}
3093 
3094   enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3095     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3096 
3097     MacroAssembler _masm(&cbuf);
3098     Register Rtmp   = R0;
3099     Register Rres   = $res$$Register;
3100     Register Rsrc   = $src$$Register;
3101     Register Rptr   = $mem_ptr$$Register;
3102     bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3103     Register Rold   = RegCollision ? Rtmp : Rres;
3104 
3105     Label Lretry;
3106     __ bind(Lretry);
3107     __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3108     __ add(Rtmp, Rsrc, Rold);
3109     __ stdcx_(Rtmp, Rptr);
3110     if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3111       __ bne_predict_not_taken(CCR0, Lretry);
3112     } else {
3113       __ bne(                  CCR0, Lretry);
3114     }
3115     if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3116     __ fence();
3117   %}
3118 
3119   enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3120     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3121 
3122     MacroAssembler _masm(&cbuf);
3123     Register Rtmp   = R0;
3124     Register Rres   = $res$$Register;
3125     Register Rsrc   = $src$$Register;
3126     Register Rptr   = $mem_ptr$$Register;
3127     bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3128     Register Rold   = RegCollision ? Rtmp : Rres;
3129 
3130     Label Lretry;
3131     __ bind(Lretry);
3132     __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3133     __ stwcx_(Rsrc, Rptr);
3134     if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3135       __ bne_predict_not_taken(CCR0, Lretry);
3136     } else {
3137       __ bne(                  CCR0, Lretry);
3138     }
3139     if (RegCollision) __ mr(Rres, Rtmp);
3140     __ fence();
3141   %}
3142 
3143   enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3144     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3145 
3146     MacroAssembler _masm(&cbuf);
3147     Register Rtmp   = R0;
3148     Register Rres   = $res$$Register;
3149     Register Rsrc   = $src$$Register;
3150     Register Rptr   = $mem_ptr$$Register;
3151     bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3152     Register Rold   = RegCollision ? Rtmp : Rres;
3153 
3154     Label Lretry;
3155     __ bind(Lretry);
3156     __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3157     __ stdcx_(Rsrc, Rptr);
3158     if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3159       __ bne_predict_not_taken(CCR0, Lretry);
3160     } else {
3161       __ bne(                  CCR0, Lretry);
3162     }
3163     if (RegCollision) __ mr(Rres, Rtmp);
3164     __ fence();
3165   %}
3166 
3167   // This enc_class is needed so that scheduler gets proper
3168   // input mapping for latency computation.
3169   enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3170     // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3171     MacroAssembler _masm(&cbuf);
3172     __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3173   %}
3174 
3175   enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3176     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3177 
3178     MacroAssembler _masm(&cbuf);
3179 
3180     Label done;
3181     __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3182     __ li($dst$$Register, $zero$$constant);
3183     __ beq($crx$$CondRegister, done);
3184     __ li($dst$$Register, $notzero$$constant);
3185     __ bind(done);
3186   %}
3187 
3188   enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3189     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3190 
3191     MacroAssembler _masm(&cbuf);
3192 
3193     Label done;
3194     __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3195     __ li($dst$$Register, $zero$$constant);
3196     __ beq($crx$$CondRegister, done);
3197     __ li($dst$$Register, $notzero$$constant);
3198     __ bind(done);
3199   %}
3200 
3201   enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL mem ) %{
3202     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3203 
3204     MacroAssembler _masm(&cbuf);
3205     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3206     Label done;
3207     __ bso($crx$$CondRegister, done);
3208     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3209     // TODO PPC port __ endgroup_if_needed(_size == 12);
3210     __ bind(done);
3211   %}
3212 
3213   enc_class enc_bc(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3214     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3215 
3216     MacroAssembler _masm(&cbuf);
3217     Label d;   // dummy
3218     __ bind(d);
3219     Label* p = ($lbl$$label);
3220     // `p' is `NULL' when this encoding class is used only to
3221     // determine the size of the encoded instruction.
3222     Label& l = (NULL == p)? d : *(p);
3223     int cc = $cmp$$cmpcode;
3224     int flags_reg = $crx$$reg;
3225     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3226     int bhint = Assembler::bhintNoHint;
3227 
3228     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3229       if (_prob <= PROB_NEVER) {
3230         bhint = Assembler::bhintIsNotTaken;
3231       } else if (_prob >= PROB_ALWAYS) {
3232         bhint = Assembler::bhintIsTaken;
3233       }
3234     }
3235 
3236     __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3237           cc_to_biint(cc, flags_reg),
3238           l);
3239   %}
3240 
3241   enc_class enc_bc_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3242     // The scheduler doesn't know about branch shortening, so we set the opcode
3243     // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3244     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3245 
3246     MacroAssembler _masm(&cbuf);
3247     Label d;    // dummy
3248     __ bind(d);
3249     Label* p = ($lbl$$label);
3250     // `p' is `NULL' when this encoding class is used only to
3251     // determine the size of the encoded instruction.
3252     Label& l = (NULL == p)? d : *(p);
3253     int cc = $cmp$$cmpcode;
3254     int flags_reg = $crx$$reg;
3255     int bhint = Assembler::bhintNoHint;
3256 
3257     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3258       if (_prob <= PROB_NEVER) {
3259         bhint = Assembler::bhintIsNotTaken;
3260       } else if (_prob >= PROB_ALWAYS) {
3261         bhint = Assembler::bhintIsTaken;
3262       }
3263     }
3264 
3265     // Tell the conditional far branch to optimize itself when being relocated.
3266     __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3267                   cc_to_biint(cc, flags_reg),
3268                   l,
3269                   MacroAssembler::bc_far_optimize_on_relocate);
3270   %}
3271 
3272   // Branch used with Power6 scheduling (can be shortened without changing the node).
3273   enc_class enc_bc_short_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3274     // The scheduler doesn't know about branch shortening, so we set the opcode
3275     // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3276     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3277 
3278     MacroAssembler _masm(&cbuf);
3279     Label d;   // dummy
3280     __ bind(d);
3281     Label* p = ($lbl$$label);
3282     // `p' is `NULL' when this encoding class is used only to
3283     // determine the size of the encoded instruction.
3284     Label& l = (NULL == p)? d : *(p);
3285     int cc = $cmp$$cmpcode;
3286     int flags_reg = $crx$$reg;
3287     int bhint = Assembler::bhintNoHint;
3288 
3289     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3290       if (_prob <= PROB_NEVER) {
3291         bhint = Assembler::bhintIsNotTaken;
3292       } else if (_prob >= PROB_ALWAYS) {
3293         bhint = Assembler::bhintIsTaken;
3294       }
3295     }
3296 
3297 #if 0 // TODO: PPC port
3298     if (_size == 8) {
3299       // Tell the conditional far branch to optimize itself when being relocated.
3300       __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3301                     cc_to_biint(cc, flags_reg),
3302                     l,
3303                     MacroAssembler::bc_far_optimize_on_relocate);
3304     } else {
3305       __ bc    (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3306                     cc_to_biint(cc, flags_reg),
3307                     l);
3308     }
3309 #endif
3310     Unimplemented();
3311   %}
3312 
3313   // Postalloc expand emitter for loading a replicatef float constant from
3314   // the method's TOC.
3315   // Enc_class needed as consttanttablebase is not supported by postalloc
3316   // expand.
3317   enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3318     // Create new nodes.
3319 
3320     // Make an operand with the bit pattern to load as float.
3321     immLOper *op_repl = new immLOper((jlong)replicate_immF(op_src->constantF()));
3322 
3323     loadConLNodesTuple loadConLNodes =
3324       loadConLNodesTuple_create(ra_, n_toc, op_repl,
3325                                 ra_->get_reg_second(this), ra_->get_reg_first(this));
3326 
3327     // Push new nodes.
3328     if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3329     if (loadConLNodes._last)     nodes->push(loadConLNodes._last);
3330 
3331     assert(nodes->length() >= 1, "must have created at least 1 node");
3332     assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3333   %}
3334 
3335   // This enc_class is needed so that scheduler gets proper
3336   // input mapping for latency computation.
3337   enc_class enc_poll(immI dst, iRegLdst poll) %{
3338     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3339     // Fake operand dst needed for PPC scheduler.
3340     assert($dst$$constant == 0x0, "dst must be 0x0");
3341 
3342     MacroAssembler _masm(&cbuf);
3343     // Mark the code position where the load from the safepoint
3344     // polling page was emitted as relocInfo::poll_type.
3345     __ relocate(relocInfo::poll_type);
3346     __ load_from_polling_page($poll$$Register);
3347   %}
3348 
3349   // A Java static call or a runtime call.
3350   //
3351   // Branch-and-link relative to a trampoline.
3352   // The trampoline loads the target address and does a long branch to there.
3353   // In case we call java, the trampoline branches to a interpreter_stub
3354   // which loads the inline cache and the real call target from the constant pool.
3355   //
3356   // This basically looks like this:
3357   //
3358   // >>>> consts      -+  -+
3359   //                   |   |- offset1
3360   // [call target1]    | <-+
3361   // [IC cache]        |- offset2
3362   // [call target2] <--+
3363   //
3364   // <<<< consts
3365   // >>>> insts
3366   //
3367   // bl offset16               -+  -+             ??? // How many bits available?
3368   //                            |   |
3369   // <<<< insts                 |   |
3370   // >>>> stubs                 |   |
3371   //                            |   |- trampoline_stub_Reloc
3372   // trampoline stub:           | <-+
3373   //   r2 = toc                 |
3374   //   r2 = [r2 + offset1]      |       // Load call target1 from const section
3375   //   mtctr r2                 |
3376   //   bctr                     |- static_stub_Reloc
3377   // comp_to_interp_stub:   <---+
3378   //   r1 = toc
3379   //   ICreg = [r1 + IC_offset]         // Load IC from const section
3380   //   r1    = [r1 + offset2]           // Load call target2 from const section
3381   //   mtctr r1
3382   //   bctr
3383   //
3384   // <<<< stubs
3385   //
3386   // The call instruction in the code either
3387   // - Branches directly to a compiled method if the offset is encodable in instruction.
3388   // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3389   // - Branches to the compiled_to_interp stub if the target is interpreted.
3390   //
3391   // Further there are three relocations from the loads to the constants in
3392   // the constant section.
3393   //
3394   // Usage of r1 and r2 in the stubs allows to distinguish them.
3395   enc_class enc_java_static_call(method meth) %{
3396     // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3397 
3398     MacroAssembler _masm(&cbuf);
3399     address entry_point = (address)$meth$$method;
3400 
3401     if (!_method) {
3402       // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3403       emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3404     } else {
3405       // Remember the offset not the address.
3406       const int start_offset = __ offset();
3407       // The trampoline stub.
3408       if (!Compile::current()->in_scratch_emit_size()) {
3409         // No entry point given, use the current pc.
3410         // Make sure branch fits into
3411         if (entry_point == 0) entry_point = __ pc();
3412 
3413         // Put the entry point as a constant into the constant pool.
3414         const address entry_point_toc_addr   = __ address_constant(entry_point, RelocationHolder::none);
3415         const int     entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3416 
3417         // Emit the trampoline stub which will be related to the branch-and-link below.
3418         CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3419         if (ciEnv::current()->failing()) { return; } // Code cache may be full.
3420         __ relocate(_optimized_virtual ?
3421                     relocInfo::opt_virtual_call_type : relocInfo::static_call_type);
3422       }
3423 
3424       // The real call.
3425       // Note: At this point we do not have the address of the trampoline
3426       // stub, and the entry point might be too far away for bl, so __ pc()
3427       // serves as dummy and the bl will be patched later.
3428       cbuf.set_insts_mark();
3429       __ bl(__ pc());  // Emits a relocation.
3430 
3431       // The stub for call to interpreter.
3432       address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
3433       if (stub == NULL) {
3434         ciEnv::current()->record_failure("CodeCache is full");
3435         return;
3436       }
3437     }
3438   %}
3439 
3440   // Emit a method handle call.
3441   //
3442   // Method handle calls from compiled to compiled are going thru a
3443   // c2i -> i2c adapter, extending the frame for their arguments. The
3444   // caller however, returns directly to the compiled callee, that has
3445   // to cope with the extended frame. We restore the original frame by
3446   // loading the callers sp and adding the calculated framesize.
3447   enc_class enc_java_handle_call(method meth) %{
3448     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3449 
3450     MacroAssembler _masm(&cbuf);
3451     address entry_point = (address)$meth$$method;
3452 
3453     // Remember the offset not the address.
3454     const int start_offset = __ offset();
3455     // The trampoline stub.
3456     if (!ra_->C->in_scratch_emit_size()) {
3457       // No entry point given, use the current pc.
3458       // Make sure branch fits into
3459       if (entry_point == 0) entry_point = __ pc();
3460 
3461       // Put the entry point as a constant into the constant pool.
3462       const address entry_point_toc_addr   = __ address_constant(entry_point, RelocationHolder::none);
3463       const int     entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3464 
3465       // Emit the trampoline stub which will be related to the branch-and-link below.
3466       CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3467       if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3468       assert(_optimized_virtual, "methodHandle call should be a virtual call");
3469       __ relocate(relocInfo::opt_virtual_call_type);
3470     }
3471 
3472     // The real call.
3473     // Note: At this point we do not have the address of the trampoline
3474     // stub, and the entry point might be too far away for bl, so __ pc()
3475     // serves as dummy and the bl will be patched later.
3476     cbuf.set_insts_mark();
3477     __ bl(__ pc());  // Emits a relocation.
3478 
3479     assert(_method, "execute next statement conditionally");
3480     // The stub for call to interpreter.
3481     address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
3482     if (stub == NULL) {
3483       ciEnv::current()->record_failure("CodeCache is full");
3484       return;
3485     }
3486 
3487     // Restore original sp.
3488     __ ld(R11_scratch1, 0, R1_SP); // Load caller sp.
3489     const long framesize = ra_->C->frame_slots() << LogBytesPerInt;
3490     unsigned int bytes = (unsigned int)framesize;
3491     long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
3492     if (Assembler::is_simm(-offset, 16)) {
3493       __ addi(R1_SP, R11_scratch1, -offset);
3494     } else {
3495       __ load_const_optimized(R12_scratch2, -offset);
3496       __ add(R1_SP, R11_scratch1, R12_scratch2);
3497     }
3498 #ifdef ASSERT
3499   __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp.
3500   __ cmpd(CCR0, R11_scratch1, R12_scratch2);
3501   __ asm_assert_eq("backlink changed", 0x8000);
3502 #endif
3503     // If fails should store backlink before unextending.
3504 
3505     if (ra_->C->env()->failing()) {
3506       return;
3507     }
3508   %}
3509 
3510   // Second node of expanded dynamic call - the call.
3511   enc_class enc_java_dynamic_call_sched(method meth) %{
3512     // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3513 
3514     MacroAssembler _masm(&cbuf);
3515 
3516     if (!ra_->C->in_scratch_emit_size()) {
3517       // Create a call trampoline stub for the given method.
3518       const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3519       const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3520       const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3521       CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3522       if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3523 
3524       // Build relocation at call site with ic position as data.
3525       assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3526              (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3527              "must have one, but can't have both");
3528       assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3529              (_load_ic_node != NULL    && _load_ic_node->_cbuf_insts_offset != -1),
3530              "must contain instruction offset");
3531       const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3532         ? _load_ic_hi_node->_cbuf_insts_offset
3533         : _load_ic_node->_cbuf_insts_offset;
3534       const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3535       assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3536              "should be load from TOC");
3537 
3538       __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
3539     }
3540 
3541     // At this point I do not have the address of the trampoline stub,
3542     // and the entry point might be too far away for bl. Pc() serves
3543     // as dummy and bl will be patched later.
3544     __ bl((address) __ pc());
3545   %}
3546 
3547   // postalloc expand emitter for virtual calls.
3548   enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3549 
3550     // Create the nodes for loading the IC from the TOC.
3551     loadConLNodesTuple loadConLNodes_IC =
3552       loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong)Universe::non_oop_word()),
3553                                 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3554 
3555     // Create the call node.
3556     CallDynamicJavaDirectSchedNode *call = new CallDynamicJavaDirectSchedNode();
3557     call->_method_handle_invoke = _method_handle_invoke;
3558     call->_vtable_index      = _vtable_index;
3559     call->_method            = _method;
3560     call->_bci               = _bci;
3561     call->_optimized_virtual = _optimized_virtual;
3562     call->_tf                = _tf;
3563     call->_entry_point       = _entry_point;
3564     call->_cnt               = _cnt;
3565     call->_argsize           = _argsize;
3566     call->_oop_map           = _oop_map;
3567     call->_jvms              = _jvms;
3568     call->_jvmadj            = _jvmadj;
3569     call->_in_rms            = _in_rms;
3570     call->_nesting           = _nesting;
3571 
3572     // New call needs all inputs of old call.
3573     // Req...
3574     for (uint i = 0; i < req(); ++i) {
3575       // The expanded node does not need toc any more.
3576       // Add the inline cache constant here instead. This expresses the
3577       // register of the inline cache must be live at the call.
3578       // Else we would have to adapt JVMState by -1.
3579       if (i == mach_constant_base_node_input()) {
3580         call->add_req(loadConLNodes_IC._last);
3581       } else {
3582         call->add_req(in(i));
3583       }
3584     }
3585     // ...as well as prec
3586     for (uint i = req(); i < len(); ++i) {
3587       call->add_prec(in(i));
3588     }
3589 
3590     // Remember nodes loading the inline cache into r19.
3591     call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3592     call->_load_ic_node    = loadConLNodes_IC._small;
3593 
3594     // Operands for new nodes.
3595     call->_opnds[0] = _opnds[0];
3596     call->_opnds[1] = _opnds[1];
3597 
3598     // Only the inline cache is associated with a register.
3599     assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3600 
3601     // Push new nodes.
3602     if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3603     if (loadConLNodes_IC._last)     nodes->push(loadConLNodes_IC._last);
3604     nodes->push(call);
3605   %}
3606 
3607   // Compound version of call dynamic
3608   // Toc is only passed so that it can be used in ins_encode statement.
3609   // In the code we have to use $constanttablebase.
3610   enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3611     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3612     MacroAssembler _masm(&cbuf);
3613     int start_offset = __ offset();
3614 
3615     Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3616 #if 0
3617     int vtable_index = this->_vtable_index;
3618     if (_vtable_index < 0) {
3619       // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3620       assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3621       Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3622 
3623       // Virtual call relocation will point to ic load.
3624       address virtual_call_meta_addr = __ pc();
3625       // Load a clear inline cache.
3626       AddressLiteral empty_ic((address) Universe::non_oop_word());
3627       __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc);
3628       // CALL to fixup routine.  Fixup routine uses ScopeDesc info
3629       // to determine who we intended to call.
3630       __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3631       emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3632       assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3633              "Fix constant in ret_addr_offset()");
3634     } else {
3635       assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3636       // Go thru the vtable. Get receiver klass. Receiver already
3637       // checked for non-null. If we'll go thru a C2I adapter, the
3638       // interpreter expects method in R19_method.
3639 
3640       __ load_klass(R11_scratch1, R3);
3641 
3642       int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size();
3643       int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes();
3644       __ li(R19_method, v_off);
3645       __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3646       // NOTE: for vtable dispatches, the vtable entry will never be
3647       // null. However it may very well end up in handle_wrong_method
3648       // if the method is abstract for the particular class.
3649       __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3650       // Call target. Either compiled code or C2I adapter.
3651       __ mtctr(R11_scratch1);
3652       __ bctrl();
3653       if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3654         tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3655       }
3656       assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3657              "Fix constant in ret_addr_offset()");
3658     }
3659 #endif
3660     Unimplemented();  // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3661   %}
3662 
3663   // a runtime call
3664   enc_class enc_java_to_runtime_call (method meth) %{
3665     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3666 
3667     MacroAssembler _masm(&cbuf);
3668     const address start_pc = __ pc();
3669 
3670 #if defined(ABI_ELFv2)
3671     address entry= !($meth$$method) ? NULL : (address)$meth$$method;
3672     __ call_c(entry, relocInfo::runtime_call_type);
3673 #else
3674     // The function we're going to call.
3675     FunctionDescriptor fdtemp;
3676     const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3677 
3678     Register Rtoc = R12_scratch2;
3679     // Calculate the method's TOC.
3680     __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3681     // Put entry, env, toc into the constant pool, this needs up to 3 constant
3682     // pool entries; call_c_using_toc will optimize the call.
3683     __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3684 #endif
3685 
3686     // Check the ret_addr_offset.
3687     assert(((MachCallRuntimeNode*)this)->ret_addr_offset() ==  __ last_calls_return_pc() - start_pc,
3688            "Fix constant in ret_addr_offset()");
3689   %}
3690 
3691   // Move to ctr for leaf call.
3692   // This enc_class is needed so that scheduler gets proper
3693   // input mapping for latency computation.
3694   enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3695     // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3696     MacroAssembler _masm(&cbuf);
3697     __ mtctr($src$$Register);
3698   %}
3699 
3700   // Postalloc expand emitter for runtime leaf calls.
3701   enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3702     loadConLNodesTuple loadConLNodes_Entry;
3703 #if defined(ABI_ELFv2)
3704     jlong entry_address = (jlong) this->entry_point();
3705     assert(entry_address, "need address here");
3706     loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3707                                                     OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3708 #else
3709     // Get the struct that describes the function we are about to call.
3710     FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3711     assert(fd, "need fd here");
3712     jlong entry_address = (jlong) fd->entry();
3713     // new nodes
3714     loadConLNodesTuple loadConLNodes_Env;
3715     loadConLNodesTuple loadConLNodes_Toc;
3716 
3717     // Create nodes and operands for loading the entry point.
3718     loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3719                                                     OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3720 
3721 
3722     // Create nodes and operands for loading the env pointer.
3723     if (fd->env() != NULL) {
3724       loadConLNodes_Env = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->env()),
3725                                                     OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3726     } else {
3727       loadConLNodes_Env._large_hi = NULL;
3728       loadConLNodes_Env._large_lo = NULL;
3729       loadConLNodes_Env._small    = NULL;
3730       loadConLNodes_Env._last = new loadConL16Node();
3731       loadConLNodes_Env._last->_opnds[0] = new iRegLdstOper();
3732       loadConLNodes_Env._last->_opnds[1] = new immL16Oper(0);
3733       ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3734     }
3735 
3736     // Create nodes and operands for loading the Toc point.
3737     loadConLNodes_Toc = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->toc()),
3738                                                   OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3739 #endif // ABI_ELFv2
3740     // mtctr node
3741     MachNode *mtctr = new CallLeafDirect_mtctrNode();
3742 
3743     assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3744     mtctr->add_req(0, loadConLNodes_Entry._last);
3745 
3746     mtctr->_opnds[0] = new iRegLdstOper();
3747     mtctr->_opnds[1] = new iRegLdstOper();
3748 
3749     // call node
3750     MachCallLeafNode *call = new CallLeafDirectNode();
3751 
3752     call->_opnds[0] = _opnds[0];
3753     call->_opnds[1] = new methodOper((intptr_t) entry_address); // May get set later.
3754 
3755     // Make the new call node look like the old one.
3756     call->_name        = _name;
3757     call->_tf          = _tf;
3758     call->_entry_point = _entry_point;
3759     call->_cnt         = _cnt;
3760     call->_argsize     = _argsize;
3761     call->_oop_map     = _oop_map;
3762     guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3763     call->_jvms        = NULL;
3764     call->_jvmadj      = _jvmadj;
3765     call->_in_rms      = _in_rms;
3766     call->_nesting     = _nesting;
3767 
3768 
3769     // New call needs all inputs of old call.
3770     // Req...
3771     for (uint i = 0; i < req(); ++i) {
3772       if (i != mach_constant_base_node_input()) {
3773         call->add_req(in(i));
3774       }
3775     }
3776 
3777     // These must be reqired edges, as the registers are live up to
3778     // the call. Else the constants are handled as kills.
3779     call->add_req(mtctr);
3780 #if !defined(ABI_ELFv2)
3781     call->add_req(loadConLNodes_Env._last);
3782     call->add_req(loadConLNodes_Toc._last);
3783 #endif
3784 
3785     // ...as well as prec
3786     for (uint i = req(); i < len(); ++i) {
3787       call->add_prec(in(i));
3788     }
3789 
3790     // registers
3791     ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3792 
3793     // Insert the new nodes.
3794     if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3795     if (loadConLNodes_Entry._last)     nodes->push(loadConLNodes_Entry._last);
3796 #if !defined(ABI_ELFv2)
3797     if (loadConLNodes_Env._large_hi)   nodes->push(loadConLNodes_Env._large_hi);
3798     if (loadConLNodes_Env._last)       nodes->push(loadConLNodes_Env._last);
3799     if (loadConLNodes_Toc._large_hi)   nodes->push(loadConLNodes_Toc._large_hi);
3800     if (loadConLNodes_Toc._last)       nodes->push(loadConLNodes_Toc._last);
3801 #endif
3802     nodes->push(mtctr);
3803     nodes->push(call);
3804   %}
3805 %}
3806 
3807 //----------FRAME--------------------------------------------------------------
3808 // Definition of frame structure and management information.
3809 
3810 frame %{
3811   // What direction does stack grow in (assumed to be same for native & Java).
3812   stack_direction(TOWARDS_LOW);
3813 
3814   // These two registers define part of the calling convention between
3815   // compiled code and the interpreter.
3816 
3817   // Inline Cache Register or method for I2C.
3818   inline_cache_reg(R19); // R19_method
3819 
3820   // Method Oop Register when calling interpreter.
3821   interpreter_method_oop_reg(R19); // R19_method
3822 
3823   // Optional: name the operand used by cisc-spilling to access
3824   // [stack_pointer + offset].
3825   cisc_spilling_operand_name(indOffset);
3826 
3827   // Number of stack slots consumed by a Monitor enter.
3828   sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3829 
3830   // Compiled code's Frame Pointer.
3831   frame_pointer(R1); // R1_SP
3832 
3833   // Interpreter stores its frame pointer in a register which is
3834   // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3835   // interpreted java to compiled java.
3836   //
3837   // R14_state holds pointer to caller's cInterpreter.
3838   interpreter_frame_pointer(R14); // R14_state
3839 
3840   stack_alignment(frame::alignment_in_bytes);
3841 
3842   in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3843 
3844   // Number of outgoing stack slots killed above the
3845   // out_preserve_stack_slots for calls to C. Supports the var-args
3846   // backing area for register parms.
3847   //
3848   varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3849 
3850   // The after-PROLOG location of the return address. Location of
3851   // return address specifies a type (REG or STACK) and a number
3852   // representing the register number (i.e. - use a register name) or
3853   // stack slot.
3854   //
3855   // A: Link register is stored in stack slot ...
3856   // M:  ... but it's in the caller's frame according to PPC-64 ABI.
3857   // J: Therefore, we make sure that the link register is also in R11_scratch1
3858   //    at the end of the prolog.
3859   // B: We use R20, now.
3860   //return_addr(REG R20);
3861 
3862   // G: After reading the comments made by all the luminaries on their
3863   //    failure to tell the compiler where the return address really is,
3864   //    I hardly dare to try myself.  However, I'm convinced it's in slot
3865   //    4 what apparently works and saves us some spills.
3866   return_addr(STACK 4);
3867 
3868   // This is the body of the function
3869   //
3870   // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3871   //                                  uint length,      // length of array
3872   //                                  bool is_outgoing)
3873   //
3874   // The `sig' array is to be updated. sig[j] represents the location
3875   // of the j-th argument, either a register or a stack slot.
3876 
3877   // Comment taken from i486.ad:
3878   // Body of function which returns an integer array locating
3879   // arguments either in registers or in stack slots. Passed an array
3880   // of ideal registers called "sig" and a "length" count. Stack-slot
3881   // offsets are based on outgoing arguments, i.e. a CALLER setting up
3882   // arguments for a CALLEE. Incoming stack arguments are
3883   // automatically biased by the preserve_stack_slots field above.
3884   calling_convention %{
3885     // No difference between ingoing/outgoing. Just pass false.
3886     SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3887   %}
3888 
3889   // Comment taken from i486.ad:
3890   // Body of function which returns an integer array locating
3891   // arguments either in registers or in stack slots. Passed an array
3892   // of ideal registers called "sig" and a "length" count. Stack-slot
3893   // offsets are based on outgoing arguments, i.e. a CALLER setting up
3894   // arguments for a CALLEE. Incoming stack arguments are
3895   // automatically biased by the preserve_stack_slots field above.
3896   c_calling_convention %{
3897     // This is obviously always outgoing.
3898     // C argument in register AND stack slot.
3899     (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3900   %}
3901 
3902   // Location of native (C/C++) and interpreter return values. This
3903   // is specified to be the same as Java. In the 32-bit VM, long
3904   // values are actually returned from native calls in O0:O1 and
3905   // returned to the interpreter in I0:I1. The copying to and from
3906   // the register pairs is done by the appropriate call and epilog
3907   // opcodes. This simplifies the register allocator.
3908   c_return_value %{
3909     assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3910             (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3911             "only return normal values");
3912     // enum names from opcodes.hpp:    Op_Node Op_Set Op_RegN       Op_RegI       Op_RegP       Op_RegF       Op_RegD       Op_RegL
3913     static int typeToRegLo[Op_RegL+1] = { 0,   0,     R3_num,   R3_num,   R3_num,   F1_num,   F1_num,   R3_num };
3914     static int typeToRegHi[Op_RegL+1] = { 0,   0,     OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3915     return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3916   %}
3917 
3918   // Location of compiled Java return values.  Same as C
3919   return_value %{
3920     assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3921             (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3922             "only return normal values");
3923     // enum names from opcodes.hpp:    Op_Node Op_Set Op_RegN       Op_RegI       Op_RegP       Op_RegF       Op_RegD       Op_RegL
3924     static int typeToRegLo[Op_RegL+1] = { 0,   0,     R3_num,   R3_num,   R3_num,   F1_num,   F1_num,   R3_num };
3925     static int typeToRegHi[Op_RegL+1] = { 0,   0,     OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3926     return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3927   %}
3928 %}
3929 
3930 
3931 //----------ATTRIBUTES---------------------------------------------------------
3932 
3933 //----------Operand Attributes-------------------------------------------------
3934 op_attrib op_cost(1);          // Required cost attribute.
3935 
3936 //----------Instruction Attributes---------------------------------------------
3937 
3938 // Cost attribute. required.
3939 ins_attrib ins_cost(DEFAULT_COST);
3940 
3941 // Is this instruction a non-matching short branch variant of some
3942 // long branch? Not required.
3943 ins_attrib ins_short_branch(0);
3944 
3945 ins_attrib ins_is_TrapBasedCheckNode(true);
3946 
3947 // Number of constants.
3948 // This instruction uses the given number of constants
3949 // (optional attribute).
3950 // This is needed to determine in time whether the constant pool will
3951 // exceed 4000 entries. Before postalloc_expand the overall number of constants
3952 // is determined. It's also used to compute the constant pool size
3953 // in Output().
3954 ins_attrib ins_num_consts(0);
3955 
3956 // Required alignment attribute (must be a power of 2) specifies the
3957 // alignment that some part of the instruction (not necessarily the
3958 // start) requires. If > 1, a compute_padding() function must be
3959 // provided for the instruction.
3960 ins_attrib ins_alignment(1);
3961 
3962 // Enforce/prohibit rematerializations.
3963 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
3964 //   then rematerialization of that instruction is prohibited and the
3965 //   instruction's value will be spilled if necessary.
3966 //   Causes that MachNode::rematerialize() returns false.
3967 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
3968 //   then rematerialization should be enforced and a copy of the instruction
3969 //   should be inserted if possible; rematerialization is not guaranteed.
3970 //   Note: this may result in rematerializations in front of every use.
3971 //   Causes that MachNode::rematerialize() can return true.
3972 // (optional attribute)
3973 ins_attrib ins_cannot_rematerialize(false);
3974 ins_attrib ins_should_rematerialize(false);
3975 
3976 // Instruction has variable size depending on alignment.
3977 ins_attrib ins_variable_size_depending_on_alignment(false);
3978 
3979 // Instruction is a nop.
3980 ins_attrib ins_is_nop(false);
3981 
3982 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
3983 ins_attrib ins_use_mach_if_fast_lock_node(false);
3984 
3985 // Field for the toc offset of a constant.
3986 //
3987 // This is needed if the toc offset is not encodable as an immediate in
3988 // the PPC load instruction. If so, the upper (hi) bits of the offset are
3989 // added to the toc, and from this a load with immediate is performed.
3990 // With postalloc expand, we get two nodes that require the same offset
3991 // but which don't know about each other. The offset is only known
3992 // when the constant is added to the constant pool during emitting.
3993 // It is generated in the 'hi'-node adding the upper bits, and saved
3994 // in this node.  The 'lo'-node has a link to the 'hi'-node and reads
3995 // the offset from there when it gets encoded.
3996 ins_attrib ins_field_const_toc_offset(0);
3997 ins_attrib ins_field_const_toc_offset_hi_node(0);
3998 
3999 // A field that can hold the instructions offset in the code buffer.
4000 // Set in the nodes emitter.
4001 ins_attrib ins_field_cbuf_insts_offset(-1);
4002 
4003 // Fields for referencing a call's load-IC-node.
4004 // If the toc offset can not be encoded as an immediate in a load, we
4005 // use two nodes.
4006 ins_attrib ins_field_load_ic_hi_node(0);
4007 ins_attrib ins_field_load_ic_node(0);
4008 
4009 //----------OPERANDS-----------------------------------------------------------
4010 // Operand definitions must precede instruction definitions for correct
4011 // parsing in the ADLC because operands constitute user defined types
4012 // which are used in instruction definitions.
4013 //
4014 // Formats are generated automatically for constants and base registers.
4015 
4016 //----------Simple Operands----------------------------------------------------
4017 // Immediate Operands
4018 
4019 // Integer Immediate: 32-bit
4020 operand immI() %{
4021   match(ConI);
4022   op_cost(40);
4023   format %{ %}
4024   interface(CONST_INTER);
4025 %}
4026 
4027 operand immI8() %{
4028   predicate(Assembler::is_simm(n->get_int(), 8));
4029   op_cost(0);
4030   match(ConI);
4031   format %{ %}
4032   interface(CONST_INTER);
4033 %}
4034 
4035 // Integer Immediate: 16-bit
4036 operand immI16() %{
4037   predicate(Assembler::is_simm(n->get_int(), 16));
4038   op_cost(0);
4039   match(ConI);
4040   format %{ %}
4041   interface(CONST_INTER);
4042 %}
4043 
4044 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
4045 operand immIhi16() %{
4046   predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
4047   match(ConI);
4048   op_cost(0);
4049   format %{ %}
4050   interface(CONST_INTER);
4051 %}
4052 
4053 operand immInegpow2() %{
4054   predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
4055   match(ConI);
4056   op_cost(0);
4057   format %{ %}
4058   interface(CONST_INTER);
4059 %}
4060 
4061 operand immIpow2minus1() %{
4062   predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
4063   match(ConI);
4064   op_cost(0);
4065   format %{ %}
4066   interface(CONST_INTER);
4067 %}
4068 
4069 operand immIpowerOf2() %{
4070   predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
4071   match(ConI);
4072   op_cost(0);
4073   format %{ %}
4074   interface(CONST_INTER);
4075 %}
4076 
4077 // Unsigned Integer Immediate: the values 0-31
4078 operand uimmI5() %{
4079   predicate(Assembler::is_uimm(n->get_int(), 5));
4080   match(ConI);
4081   op_cost(0);
4082   format %{ %}
4083   interface(CONST_INTER);
4084 %}
4085 
4086 // Unsigned Integer Immediate: 6-bit
4087 operand uimmI6() %{
4088   predicate(Assembler::is_uimm(n->get_int(), 6));
4089   match(ConI);
4090   op_cost(0);
4091   format %{ %}
4092   interface(CONST_INTER);
4093 %}
4094 
4095 // Unsigned Integer Immediate:  6-bit int, greater than 32
4096 operand uimmI6_ge32() %{
4097   predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
4098   match(ConI);
4099   op_cost(0);
4100   format %{ %}
4101   interface(CONST_INTER);
4102 %}
4103 
4104 // Unsigned Integer Immediate: 15-bit
4105 operand uimmI15() %{
4106   predicate(Assembler::is_uimm(n->get_int(), 15));
4107   match(ConI);
4108   op_cost(0);
4109   format %{ %}
4110   interface(CONST_INTER);
4111 %}
4112 
4113 // Unsigned Integer Immediate: 16-bit
4114 operand uimmI16() %{
4115   predicate(Assembler::is_uimm(n->get_int(), 16));
4116   match(ConI);
4117   op_cost(0);
4118   format %{ %}
4119   interface(CONST_INTER);
4120 %}
4121 
4122 // constant 'int 0'.
4123 operand immI_0() %{
4124   predicate(n->get_int() == 0);
4125   match(ConI);
4126   op_cost(0);
4127   format %{ %}
4128   interface(CONST_INTER);
4129 %}
4130 
4131 // constant 'int 1'.
4132 operand immI_1() %{
4133   predicate(n->get_int() == 1);
4134   match(ConI);
4135   op_cost(0);
4136   format %{ %}
4137   interface(CONST_INTER);
4138 %}
4139 
4140 // constant 'int -1'.
4141 operand immI_minus1() %{
4142   predicate(n->get_int() == -1);
4143   match(ConI);
4144   op_cost(0);
4145   format %{ %}
4146   interface(CONST_INTER);
4147 %}
4148 
4149 // int value 16.
4150 operand immI_16() %{
4151   predicate(n->get_int() == 16);
4152   match(ConI);
4153   op_cost(0);
4154   format %{ %}
4155   interface(CONST_INTER);
4156 %}
4157 
4158 // int value 24.
4159 operand immI_24() %{
4160   predicate(n->get_int() == 24);
4161   match(ConI);
4162   op_cost(0);
4163   format %{ %}
4164   interface(CONST_INTER);
4165 %}
4166 
4167 // Compressed oops constants
4168 // Pointer Immediate
4169 operand immN() %{
4170   match(ConN);
4171 
4172   op_cost(10);
4173   format %{ %}
4174   interface(CONST_INTER);
4175 %}
4176 
4177 // NULL Pointer Immediate
4178 operand immN_0() %{
4179   predicate(n->get_narrowcon() == 0);
4180   match(ConN);
4181 
4182   op_cost(0);
4183   format %{ %}
4184   interface(CONST_INTER);
4185 %}
4186 
4187 // Compressed klass constants
4188 operand immNKlass() %{
4189   match(ConNKlass);
4190 
4191   op_cost(0);
4192   format %{ %}
4193   interface(CONST_INTER);
4194 %}
4195 
4196 // This operand can be used to avoid matching of an instruct
4197 // with chain rule.
4198 operand immNKlass_NM() %{
4199   match(ConNKlass);
4200   predicate(false);
4201   op_cost(0);
4202   format %{ %}
4203   interface(CONST_INTER);
4204 %}
4205 
4206 // Pointer Immediate: 64-bit
4207 operand immP() %{
4208   match(ConP);
4209   op_cost(0);
4210   format %{ %}
4211   interface(CONST_INTER);
4212 %}
4213 
4214 // Operand to avoid match of loadConP.
4215 // This operand can be used to avoid matching of an instruct
4216 // with chain rule.
4217 operand immP_NM() %{
4218   match(ConP);
4219   predicate(false);
4220   op_cost(0);
4221   format %{ %}
4222   interface(CONST_INTER);
4223 %}
4224 
4225 // costant 'pointer 0'.
4226 operand immP_0() %{
4227   predicate(n->get_ptr() == 0);
4228   match(ConP);
4229   op_cost(0);
4230   format %{ %}
4231   interface(CONST_INTER);
4232 %}
4233 
4234 // pointer 0x0 or 0x1
4235 operand immP_0or1() %{
4236   predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4237   match(ConP);
4238   op_cost(0);
4239   format %{ %}
4240   interface(CONST_INTER);
4241 %}
4242 
4243 operand immL() %{
4244   match(ConL);
4245   op_cost(40);
4246   format %{ %}
4247   interface(CONST_INTER);
4248 %}
4249 
4250 // Long Immediate: 16-bit
4251 operand immL16() %{
4252   predicate(Assembler::is_simm(n->get_long(), 16));
4253   match(ConL);
4254   op_cost(0);
4255   format %{ %}
4256   interface(CONST_INTER);
4257 %}
4258 
4259 // Long Immediate: 16-bit, 4-aligned
4260 operand immL16Alg4() %{
4261   predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4262   match(ConL);
4263   op_cost(0);
4264   format %{ %}
4265   interface(CONST_INTER);
4266 %}
4267 
4268 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4269 operand immL32hi16() %{
4270   predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4271   match(ConL);
4272   op_cost(0);
4273   format %{ %}
4274   interface(CONST_INTER);
4275 %}
4276 
4277 // Long Immediate: 32-bit
4278 operand immL32() %{
4279   predicate(Assembler::is_simm(n->get_long(), 32));
4280   match(ConL);
4281   op_cost(0);
4282   format %{ %}
4283   interface(CONST_INTER);
4284 %}
4285 
4286 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4287 operand immLhighest16() %{
4288   predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4289   match(ConL);
4290   op_cost(0);
4291   format %{ %}
4292   interface(CONST_INTER);
4293 %}
4294 
4295 operand immLnegpow2() %{
4296   predicate(is_power_of_2_long((jlong)-(n->get_long())));
4297   match(ConL);
4298   op_cost(0);
4299   format %{ %}
4300   interface(CONST_INTER);
4301 %}
4302 
4303 operand immLpow2minus1() %{
4304   predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4305             (n->get_long() != (jlong)0xffffffffffffffffL));
4306   match(ConL);
4307   op_cost(0);
4308   format %{ %}
4309   interface(CONST_INTER);
4310 %}
4311 
4312 // constant 'long 0'.
4313 operand immL_0() %{
4314   predicate(n->get_long() == 0L);
4315   match(ConL);
4316   op_cost(0);
4317   format %{ %}
4318   interface(CONST_INTER);
4319 %}
4320 
4321 // constat ' long -1'.
4322 operand immL_minus1() %{
4323   predicate(n->get_long() == -1L);
4324   match(ConL);
4325   op_cost(0);
4326   format %{ %}
4327   interface(CONST_INTER);
4328 %}
4329 
4330 // Long Immediate: low 32-bit mask
4331 operand immL_32bits() %{
4332   predicate(n->get_long() == 0xFFFFFFFFL);
4333   match(ConL);
4334   op_cost(0);
4335   format %{ %}
4336   interface(CONST_INTER);
4337 %}
4338 
4339 // Unsigned Long Immediate: 16-bit
4340 operand uimmL16() %{
4341   predicate(Assembler::is_uimm(n->get_long(), 16));
4342   match(ConL);
4343   op_cost(0);
4344   format %{ %}
4345   interface(CONST_INTER);
4346 %}
4347 
4348 // Float Immediate
4349 operand immF() %{
4350   match(ConF);
4351   op_cost(40);
4352   format %{ %}
4353   interface(CONST_INTER);
4354 %}
4355 
4356 // Float Immediate: +0.0f.
4357 operand immF_0() %{
4358   predicate(jint_cast(n->getf()) == 0);
4359   match(ConF);
4360 
4361   op_cost(0);
4362   format %{ %}
4363   interface(CONST_INTER);
4364 %}
4365 
4366 // Double Immediate
4367 operand immD() %{
4368   match(ConD);
4369   op_cost(40);
4370   format %{ %}
4371   interface(CONST_INTER);
4372 %}
4373 
4374 // Integer Register Operands
4375 // Integer Destination Register
4376 // See definition of reg_class bits32_reg_rw.
4377 operand iRegIdst() %{
4378   constraint(ALLOC_IN_RC(bits32_reg_rw));
4379   match(RegI);
4380   match(rscratch1RegI);
4381   match(rscratch2RegI);
4382   match(rarg1RegI);
4383   match(rarg2RegI);
4384   match(rarg3RegI);
4385   match(rarg4RegI);
4386   format %{ %}
4387   interface(REG_INTER);
4388 %}
4389 
4390 // Integer Source Register
4391 // See definition of reg_class bits32_reg_ro.
4392 operand iRegIsrc() %{
4393   constraint(ALLOC_IN_RC(bits32_reg_ro));
4394   match(RegI);
4395   match(rscratch1RegI);
4396   match(rscratch2RegI);
4397   match(rarg1RegI);
4398   match(rarg2RegI);
4399   match(rarg3RegI);
4400   match(rarg4RegI);
4401   format %{ %}
4402   interface(REG_INTER);
4403 %}
4404 
4405 operand rscratch1RegI() %{
4406   constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4407   match(iRegIdst);
4408   format %{ %}
4409   interface(REG_INTER);
4410 %}
4411 
4412 operand rscratch2RegI() %{
4413   constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4414   match(iRegIdst);
4415   format %{ %}
4416   interface(REG_INTER);
4417 %}
4418 
4419 operand rarg1RegI() %{
4420   constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4421   match(iRegIdst);
4422   format %{ %}
4423   interface(REG_INTER);
4424 %}
4425 
4426 operand rarg2RegI() %{
4427   constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4428   match(iRegIdst);
4429   format %{ %}
4430   interface(REG_INTER);
4431 %}
4432 
4433 operand rarg3RegI() %{
4434   constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4435   match(iRegIdst);
4436   format %{ %}
4437   interface(REG_INTER);
4438 %}
4439 
4440 operand rarg4RegI() %{
4441   constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4442   match(iRegIdst);
4443   format %{ %}
4444   interface(REG_INTER);
4445 %}
4446 
4447 operand rarg1RegL() %{
4448   constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4449   match(iRegLdst);
4450   format %{ %}
4451   interface(REG_INTER);
4452 %}
4453 
4454 operand rarg2RegL() %{
4455   constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4456   match(iRegLdst);
4457   format %{ %}
4458   interface(REG_INTER);
4459 %}
4460 
4461 operand rarg3RegL() %{
4462   constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4463   match(iRegLdst);
4464   format %{ %}
4465   interface(REG_INTER);
4466 %}
4467 
4468 operand rarg4RegL() %{
4469   constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4470   match(iRegLdst);
4471   format %{ %}
4472   interface(REG_INTER);
4473 %}
4474 
4475 // Pointer Destination Register
4476 // See definition of reg_class bits64_reg_rw.
4477 operand iRegPdst() %{
4478   constraint(ALLOC_IN_RC(bits64_reg_rw));
4479   match(RegP);
4480   match(rscratch1RegP);
4481   match(rscratch2RegP);
4482   match(rarg1RegP);
4483   match(rarg2RegP);
4484   match(rarg3RegP);
4485   match(rarg4RegP);
4486   format %{ %}
4487   interface(REG_INTER);
4488 %}
4489 
4490 // Pointer Destination Register
4491 // Operand not using r11 and r12 (killed in epilog).
4492 operand iRegPdstNoScratch() %{
4493   constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4494   match(RegP);
4495   match(rarg1RegP);
4496   match(rarg2RegP);
4497   match(rarg3RegP);
4498   match(rarg4RegP);
4499   format %{ %}
4500   interface(REG_INTER);
4501 %}
4502 
4503 // Pointer Source Register
4504 // See definition of reg_class bits64_reg_ro.
4505 operand iRegPsrc() %{
4506   constraint(ALLOC_IN_RC(bits64_reg_ro));
4507   match(RegP);
4508   match(iRegPdst);
4509   match(rscratch1RegP);
4510   match(rscratch2RegP);
4511   match(rarg1RegP);
4512   match(rarg2RegP);
4513   match(rarg3RegP);
4514   match(rarg4RegP);
4515   match(threadRegP);
4516   format %{ %}
4517   interface(REG_INTER);
4518 %}
4519 
4520 // Thread operand.
4521 operand threadRegP() %{
4522   constraint(ALLOC_IN_RC(thread_bits64_reg));
4523   match(iRegPdst);
4524   format %{ "R16" %}
4525   interface(REG_INTER);
4526 %}
4527 
4528 operand rscratch1RegP() %{
4529   constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4530   match(iRegPdst);
4531   format %{ "R11" %}
4532   interface(REG_INTER);
4533 %}
4534 
4535 operand rscratch2RegP() %{
4536   constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4537   match(iRegPdst);
4538   format %{ %}
4539   interface(REG_INTER);
4540 %}
4541 
4542 operand rarg1RegP() %{
4543   constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4544   match(iRegPdst);
4545   format %{ %}
4546   interface(REG_INTER);
4547 %}
4548 
4549 operand rarg2RegP() %{
4550   constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4551   match(iRegPdst);
4552   format %{ %}
4553   interface(REG_INTER);
4554 %}
4555 
4556 operand rarg3RegP() %{
4557   constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4558   match(iRegPdst);
4559   format %{ %}
4560   interface(REG_INTER);
4561 %}
4562 
4563 operand rarg4RegP() %{
4564   constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4565   match(iRegPdst);
4566   format %{ %}
4567   interface(REG_INTER);
4568 %}
4569 
4570 operand iRegNsrc() %{
4571   constraint(ALLOC_IN_RC(bits32_reg_ro));
4572   match(RegN);
4573   match(iRegNdst);
4574 
4575   format %{ %}
4576   interface(REG_INTER);
4577 %}
4578 
4579 operand iRegNdst() %{
4580   constraint(ALLOC_IN_RC(bits32_reg_rw));
4581   match(RegN);
4582 
4583   format %{ %}
4584   interface(REG_INTER);
4585 %}
4586 
4587 // Long Destination Register
4588 // See definition of reg_class bits64_reg_rw.
4589 operand iRegLdst() %{
4590   constraint(ALLOC_IN_RC(bits64_reg_rw));
4591   match(RegL);
4592   match(rscratch1RegL);
4593   match(rscratch2RegL);
4594   format %{ %}
4595   interface(REG_INTER);
4596 %}
4597 
4598 // Long Source Register
4599 // See definition of reg_class bits64_reg_ro.
4600 operand iRegLsrc() %{
4601   constraint(ALLOC_IN_RC(bits64_reg_ro));
4602   match(RegL);
4603   match(iRegLdst);
4604   match(rscratch1RegL);
4605   match(rscratch2RegL);
4606   format %{ %}
4607   interface(REG_INTER);
4608 %}
4609 
4610 // Special operand for ConvL2I.
4611 operand iRegL2Isrc(iRegLsrc reg) %{
4612   constraint(ALLOC_IN_RC(bits64_reg_ro));
4613   match(ConvL2I reg);
4614   format %{ "ConvL2I($reg)" %}
4615   interface(REG_INTER)
4616 %}
4617 
4618 operand rscratch1RegL() %{
4619   constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4620   match(RegL);
4621   format %{ %}
4622   interface(REG_INTER);
4623 %}
4624 
4625 operand rscratch2RegL() %{
4626   constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4627   match(RegL);
4628   format %{ %}
4629   interface(REG_INTER);
4630 %}
4631 
4632 // Condition Code Flag Registers
4633 operand flagsReg() %{
4634   constraint(ALLOC_IN_RC(int_flags));
4635   match(RegFlags);
4636   format %{ %}
4637   interface(REG_INTER);
4638 %}
4639 
4640 operand flagsRegSrc() %{
4641   constraint(ALLOC_IN_RC(int_flags_ro));
4642   match(RegFlags);
4643   match(flagsReg);
4644   match(flagsRegCR0);
4645   format %{ %}
4646   interface(REG_INTER);
4647 %}
4648 
4649 // Condition Code Flag Register CR0
4650 operand flagsRegCR0() %{
4651   constraint(ALLOC_IN_RC(int_flags_CR0));
4652   match(RegFlags);
4653   format %{ "CR0" %}
4654   interface(REG_INTER);
4655 %}
4656 
4657 operand flagsRegCR1() %{
4658   constraint(ALLOC_IN_RC(int_flags_CR1));
4659   match(RegFlags);
4660   format %{ "CR1" %}
4661   interface(REG_INTER);
4662 %}
4663 
4664 operand flagsRegCR6() %{
4665   constraint(ALLOC_IN_RC(int_flags_CR6));
4666   match(RegFlags);
4667   format %{ "CR6" %}
4668   interface(REG_INTER);
4669 %}
4670 
4671 operand regCTR() %{
4672   constraint(ALLOC_IN_RC(ctr_reg));
4673   // RegFlags should work. Introducing a RegSpecial type would cause a
4674   // lot of changes.
4675   match(RegFlags);
4676   format %{"SR_CTR" %}
4677   interface(REG_INTER);
4678 %}
4679 
4680 operand regD() %{
4681   constraint(ALLOC_IN_RC(dbl_reg));
4682   match(RegD);
4683   format %{ %}
4684   interface(REG_INTER);
4685 %}
4686 
4687 operand regF() %{
4688   constraint(ALLOC_IN_RC(flt_reg));
4689   match(RegF);
4690   format %{ %}
4691   interface(REG_INTER);
4692 %}
4693 
4694 // Special Registers
4695 
4696 // Method Register
4697 operand inline_cache_regP(iRegPdst reg) %{
4698   constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4699   match(reg);
4700   format %{ %}
4701   interface(REG_INTER);
4702 %}
4703 
4704 operand compiler_method_oop_regP(iRegPdst reg) %{
4705   constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4706   match(reg);
4707   format %{ %}
4708   interface(REG_INTER);
4709 %}
4710 
4711 operand interpreter_method_oop_regP(iRegPdst reg) %{
4712   constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4713   match(reg);
4714   format %{ %}
4715   interface(REG_INTER);
4716 %}
4717 
4718 // Operands to remove register moves in unscaled mode.
4719 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4720 operand iRegP2N(iRegPsrc reg) %{
4721   predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4722   constraint(ALLOC_IN_RC(bits64_reg_ro));
4723   match(EncodeP reg);
4724   format %{ "$reg" %}
4725   interface(REG_INTER)
4726 %}
4727 
4728 operand iRegN2P(iRegNsrc reg) %{
4729   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4730   constraint(ALLOC_IN_RC(bits32_reg_ro));
4731   match(DecodeN reg);
4732   format %{ "$reg" %}
4733   interface(REG_INTER)
4734 %}
4735 
4736 operand iRegN2P_klass(iRegNsrc reg) %{
4737   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4738   constraint(ALLOC_IN_RC(bits32_reg_ro));
4739   match(DecodeNKlass reg);
4740   format %{ "$reg" %}
4741   interface(REG_INTER)
4742 %}
4743 
4744 //----------Complex Operands---------------------------------------------------
4745 // Indirect Memory Reference
4746 operand indirect(iRegPsrc reg) %{
4747   constraint(ALLOC_IN_RC(bits64_reg_ro));
4748   match(reg);
4749   op_cost(100);
4750   format %{ "[$reg]" %}
4751   interface(MEMORY_INTER) %{
4752     base($reg);
4753     index(0x0);
4754     scale(0x0);
4755     disp(0x0);
4756   %}
4757 %}
4758 
4759 // Indirect with Offset
4760 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4761   constraint(ALLOC_IN_RC(bits64_reg_ro));
4762   match(AddP reg offset);
4763   op_cost(100);
4764   format %{ "[$reg + $offset]" %}
4765   interface(MEMORY_INTER) %{
4766     base($reg);
4767     index(0x0);
4768     scale(0x0);
4769     disp($offset);
4770   %}
4771 %}
4772 
4773 // Indirect with 4-aligned Offset
4774 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4775   constraint(ALLOC_IN_RC(bits64_reg_ro));
4776   match(AddP reg offset);
4777   op_cost(100);
4778   format %{ "[$reg + $offset]" %}
4779   interface(MEMORY_INTER) %{
4780     base($reg);
4781     index(0x0);
4782     scale(0x0);
4783     disp($offset);
4784   %}
4785 %}
4786 
4787 //----------Complex Operands for Compressed OOPs-------------------------------
4788 // Compressed OOPs with narrow_oop_shift == 0.
4789 
4790 // Indirect Memory Reference, compressed OOP
4791 operand indirectNarrow(iRegNsrc reg) %{
4792   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4793   constraint(ALLOC_IN_RC(bits64_reg_ro));
4794   match(DecodeN reg);
4795   op_cost(100);
4796   format %{ "[$reg]" %}
4797   interface(MEMORY_INTER) %{
4798     base($reg);
4799     index(0x0);
4800     scale(0x0);
4801     disp(0x0);
4802   %}
4803 %}
4804 
4805 operand indirectNarrow_klass(iRegNsrc reg) %{
4806   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4807   constraint(ALLOC_IN_RC(bits64_reg_ro));
4808   match(DecodeNKlass reg);
4809   op_cost(100);
4810   format %{ "[$reg]" %}
4811   interface(MEMORY_INTER) %{
4812     base($reg);
4813     index(0x0);
4814     scale(0x0);
4815     disp(0x0);
4816   %}
4817 %}
4818 
4819 // Indirect with Offset, compressed OOP
4820 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4821   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4822   constraint(ALLOC_IN_RC(bits64_reg_ro));
4823   match(AddP (DecodeN reg) offset);
4824   op_cost(100);
4825   format %{ "[$reg + $offset]" %}
4826   interface(MEMORY_INTER) %{
4827     base($reg);
4828     index(0x0);
4829     scale(0x0);
4830     disp($offset);
4831   %}
4832 %}
4833 
4834 operand indOffset16Narrow_klass(iRegNsrc reg, immL16 offset) %{
4835   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4836   constraint(ALLOC_IN_RC(bits64_reg_ro));
4837   match(AddP (DecodeNKlass reg) offset);
4838   op_cost(100);
4839   format %{ "[$reg + $offset]" %}
4840   interface(MEMORY_INTER) %{
4841     base($reg);
4842     index(0x0);
4843     scale(0x0);
4844     disp($offset);
4845   %}
4846 %}
4847 
4848 // Indirect with 4-aligned Offset, compressed OOP
4849 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4850   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4851   constraint(ALLOC_IN_RC(bits64_reg_ro));
4852   match(AddP (DecodeN reg) offset);
4853   op_cost(100);
4854   format %{ "[$reg + $offset]" %}
4855   interface(MEMORY_INTER) %{
4856     base($reg);
4857     index(0x0);
4858     scale(0x0);
4859     disp($offset);
4860   %}
4861 %}
4862 
4863 operand indOffset16NarrowAlg4_klass(iRegNsrc reg, immL16Alg4 offset) %{
4864   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4865   constraint(ALLOC_IN_RC(bits64_reg_ro));
4866   match(AddP (DecodeNKlass reg) offset);
4867   op_cost(100);
4868   format %{ "[$reg + $offset]" %}
4869   interface(MEMORY_INTER) %{
4870     base($reg);
4871     index(0x0);
4872     scale(0x0);
4873     disp($offset);
4874   %}
4875 %}
4876 
4877 //----------Special Memory Operands--------------------------------------------
4878 // Stack Slot Operand
4879 //
4880 // This operand is used for loading and storing temporary values on
4881 // the stack where a match requires a value to flow through memory.
4882 operand stackSlotI(sRegI reg) %{
4883   constraint(ALLOC_IN_RC(stack_slots));
4884   op_cost(100);
4885   //match(RegI);
4886   format %{ "[sp+$reg]" %}
4887   interface(MEMORY_INTER) %{
4888     base(0x1);   // R1_SP
4889     index(0x0);
4890     scale(0x0);
4891     disp($reg);  // Stack Offset
4892   %}
4893 %}
4894 
4895 operand stackSlotL(sRegL reg) %{
4896   constraint(ALLOC_IN_RC(stack_slots));
4897   op_cost(100);
4898   //match(RegL);
4899   format %{ "[sp+$reg]" %}
4900   interface(MEMORY_INTER) %{
4901     base(0x1);   // R1_SP
4902     index(0x0);
4903     scale(0x0);
4904     disp($reg);  // Stack Offset
4905   %}
4906 %}
4907 
4908 operand stackSlotP(sRegP reg) %{
4909   constraint(ALLOC_IN_RC(stack_slots));
4910   op_cost(100);
4911   //match(RegP);
4912   format %{ "[sp+$reg]" %}
4913   interface(MEMORY_INTER) %{
4914     base(0x1);   // R1_SP
4915     index(0x0);
4916     scale(0x0);
4917     disp($reg);  // Stack Offset
4918   %}
4919 %}
4920 
4921 operand stackSlotF(sRegF reg) %{
4922   constraint(ALLOC_IN_RC(stack_slots));
4923   op_cost(100);
4924   //match(RegF);
4925   format %{ "[sp+$reg]" %}
4926   interface(MEMORY_INTER) %{
4927     base(0x1);   // R1_SP
4928     index(0x0);
4929     scale(0x0);
4930     disp($reg);  // Stack Offset
4931   %}
4932 %}
4933 
4934 operand stackSlotD(sRegD reg) %{
4935   constraint(ALLOC_IN_RC(stack_slots));
4936   op_cost(100);
4937   //match(RegD);
4938   format %{ "[sp+$reg]" %}
4939   interface(MEMORY_INTER) %{
4940     base(0x1);   // R1_SP
4941     index(0x0);
4942     scale(0x0);
4943     disp($reg);  // Stack Offset
4944   %}
4945 %}
4946 
4947 // Operands for expressing Control Flow
4948 // NOTE: Label is a predefined operand which should not be redefined in
4949 //       the AD file. It is generically handled within the ADLC.
4950 
4951 //----------Conditional Branch Operands----------------------------------------
4952 // Comparison Op
4953 //
4954 // This is the operation of the comparison, and is limited to the
4955 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4956 // (!=).
4957 //
4958 // Other attributes of the comparison, such as unsignedness, are specified
4959 // by the comparison instruction that sets a condition code flags register.
4960 // That result is represented by a flags operand whose subtype is appropriate
4961 // to the unsignedness (etc.) of the comparison.
4962 //
4963 // Later, the instruction which matches both the Comparison Op (a Bool) and
4964 // the flags (produced by the Cmp) specifies the coding of the comparison op
4965 // by matching a specific subtype of Bool operand below.
4966 
4967 // When used for floating point comparisons: unordered same as less.
4968 operand cmpOp() %{
4969   match(Bool);
4970   format %{ "" %}
4971   interface(COND_INTER) %{
4972                            // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4973                            //           BO          &  BI
4974     equal(0xA);            // 10 10:   bcondCRbiIs1 & Condition::equal
4975     not_equal(0x2);        // 00 10:   bcondCRbiIs0 & Condition::equal
4976     less(0x8);             // 10 00:   bcondCRbiIs1 & Condition::less
4977     greater_equal(0x0);    // 00 00:   bcondCRbiIs0 & Condition::less
4978     less_equal(0x1);       // 00 01:   bcondCRbiIs0 & Condition::greater
4979     greater(0x9);          // 10 01:   bcondCRbiIs1 & Condition::greater
4980     overflow(0xB);         // 10 11:   bcondCRbiIs1 & Condition::summary_overflow
4981     no_overflow(0x3);      // 00 11:   bcondCRbiIs0 & Condition::summary_overflow
4982   %}
4983 %}
4984 
4985 //----------OPERAND CLASSES----------------------------------------------------
4986 // Operand Classes are groups of operands that are used to simplify
4987 // instruction definitions by not requiring the AD writer to specify
4988 // seperate instructions for every form of operand when the
4989 // instruction accepts multiple operand types with the same basic
4990 // encoding and format. The classic case of this is memory operands.
4991 // Indirect is not included since its use is limited to Compare & Swap.
4992 
4993 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indirectNarrow_klass, indOffset16Narrow, indOffset16Narrow_klass);
4994 // Memory operand where offsets are 4-aligned. Required for ld, std.
4995 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4, indOffset16NarrowAlg4_klass);
4996 opclass indirectMemory(indirect, indirectNarrow);
4997 
4998 // Special opclass for I and ConvL2I.
4999 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
5000 
5001 // Operand classes to match encode and decode. iRegN_P2N is only used
5002 // for storeN. I have never seen an encode node elsewhere.
5003 opclass iRegN_P2N(iRegNsrc, iRegP2N);
5004 opclass iRegP_N2P(iRegPsrc, iRegN2P, iRegN2P_klass);
5005 
5006 //----------PIPELINE-----------------------------------------------------------
5007 
5008 pipeline %{
5009 
5010 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
5011 // J. Res. & Dev., No. 1, Jan. 2002.
5012 
5013 //----------ATTRIBUTES---------------------------------------------------------
5014 attributes %{
5015 
5016   // Power4 instructions are of fixed length.
5017   fixed_size_instructions;
5018 
5019   // TODO: if `bundle' means number of instructions fetched
5020   // per cycle, this is 8. If `bundle' means Power4 `group', that is
5021   // max instructions issued per cycle, this is 5.
5022   max_instructions_per_bundle = 8;
5023 
5024   // A Power4 instruction is 4 bytes long.
5025   instruction_unit_size = 4;
5026 
5027   // The Power4 processor fetches 64 bytes...
5028   instruction_fetch_unit_size = 64;
5029 
5030   // ...in one line
5031   instruction_fetch_units = 1
5032 
5033   // Unused, list one so that array generated by adlc is not empty.
5034   // Aix compiler chokes if _nop_count = 0.
5035   nops(fxNop);
5036 %}
5037 
5038 //----------RESOURCES----------------------------------------------------------
5039 // Resources are the functional units available to the machine
5040 resources(
5041    PPC_BR,         // branch unit
5042    PPC_CR,         // condition unit
5043    PPC_FX1,        // integer arithmetic unit 1
5044    PPC_FX2,        // integer arithmetic unit 2
5045    PPC_LDST1,      // load/store unit 1
5046    PPC_LDST2,      // load/store unit 2
5047    PPC_FP1,        // float arithmetic unit 1
5048    PPC_FP2,        // float arithmetic unit 2
5049    PPC_LDST = PPC_LDST1 | PPC_LDST2,
5050    PPC_FX = PPC_FX1 | PPC_FX2,
5051    PPC_FP = PPC_FP1 | PPC_FP2
5052  );
5053 
5054 //----------PIPELINE DESCRIPTION-----------------------------------------------
5055 // Pipeline Description specifies the stages in the machine's pipeline
5056 pipe_desc(
5057    // Power4 longest pipeline path
5058    PPC_IF,   // instruction fetch
5059    PPC_IC,
5060    //PPC_BP, // branch prediction
5061    PPC_D0,   // decode
5062    PPC_D1,   // decode
5063    PPC_D2,   // decode
5064    PPC_D3,   // decode
5065    PPC_Xfer1,
5066    PPC_GD,   // group definition
5067    PPC_MP,   // map
5068    PPC_ISS,  // issue
5069    PPC_RF,   // resource fetch
5070    PPC_EX1,  // execute (all units)
5071    PPC_EX2,  // execute (FP, LDST)
5072    PPC_EX3,  // execute (FP, LDST)
5073    PPC_EX4,  // execute (FP)
5074    PPC_EX5,  // execute (FP)
5075    PPC_EX6,  // execute (FP)
5076    PPC_WB,   // write back
5077    PPC_Xfer2,
5078    PPC_CP
5079  );
5080 
5081 //----------PIPELINE CLASSES---------------------------------------------------
5082 // Pipeline Classes describe the stages in which input and output are
5083 // referenced by the hardware pipeline.
5084 
5085 // Simple pipeline classes.
5086 
5087 // Default pipeline class.
5088 pipe_class pipe_class_default() %{
5089   single_instruction;
5090   fixed_latency(2);
5091 %}
5092 
5093 // Pipeline class for empty instructions.
5094 pipe_class pipe_class_empty() %{
5095   single_instruction;
5096   fixed_latency(0);
5097 %}
5098 
5099 // Pipeline class for compares.
5100 pipe_class pipe_class_compare() %{
5101   single_instruction;
5102   fixed_latency(16);
5103 %}
5104 
5105 // Pipeline class for traps.
5106 pipe_class pipe_class_trap() %{
5107   single_instruction;
5108   fixed_latency(100);
5109 %}
5110 
5111 // Pipeline class for memory operations.
5112 pipe_class pipe_class_memory() %{
5113   single_instruction;
5114   fixed_latency(16);
5115 %}
5116 
5117 // Pipeline class for call.
5118 pipe_class pipe_class_call() %{
5119   single_instruction;
5120   fixed_latency(100);
5121 %}
5122 
5123 // Define the class for the Nop node.
5124 define %{
5125    MachNop = pipe_class_default;
5126 %}
5127 
5128 %}
5129 
5130 //----------INSTRUCTIONS-------------------------------------------------------
5131 
5132 // Naming of instructions:
5133 //   opA_operB / opA_operB_operC:
5134 //     Operation 'op' with one or two source operands 'oper'. Result
5135 //     type is A, source operand types are B and C.
5136 //     Iff A == B == C, B and C are left out.
5137 //
5138 // The instructions are ordered according to the following scheme:
5139 //  - loads
5140 //  - load constants
5141 //  - prefetch
5142 //  - store
5143 //  - encode/decode
5144 //  - membar
5145 //  - conditional moves
5146 //  - compare & swap
5147 //  - arithmetic and logic operations
5148 //    * int: Add, Sub, Mul, Div, Mod
5149 //    * int: lShift, arShift, urShift, rot
5150 //    * float: Add, Sub, Mul, Div
5151 //    * and, or, xor ...
5152 //  - register moves: float <-> int, reg <-> stack, repl
5153 //  - cast (high level type cast, XtoP, castPP, castII, not_null etc.
5154 //  - conv (low level type cast requiring bit changes (sign extend etc)
5155 //  - compares, range & zero checks.
5156 //  - branches
5157 //  - complex operations, intrinsics, min, max, replicate
5158 //  - lock
5159 //  - Calls
5160 //
5161 // If there are similar instructions with different types they are sorted:
5162 // int before float
5163 // small before big
5164 // signed before unsigned
5165 // e.g., loadS before loadUS before loadI before loadF.
5166 
5167 
5168 //----------Load/Store Instructions--------------------------------------------
5169 
5170 //----------Load Instructions--------------------------------------------------
5171 
5172 // Converts byte to int.
5173 // As convB2I_reg, but without match rule.  The match rule of convB2I_reg
5174 // reuses the 'amount' operand, but adlc expects that operand specification
5175 // and operands in match rule are equivalent.
5176 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5177   effect(DEF dst, USE src);
5178   format %{ "EXTSB   $dst, $src \t// byte->int" %}
5179   size(4);
5180   ins_encode %{
5181     // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5182     __ extsb($dst$$Register, $src$$Register);
5183   %}
5184   ins_pipe(pipe_class_default);
5185 %}
5186 
5187 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5188   // match-rule, false predicate
5189   match(Set dst (LoadB mem));
5190   predicate(false);
5191 
5192   format %{ "LBZ     $dst, $mem" %}
5193   size(4);
5194   ins_encode( enc_lbz(dst, mem) );
5195   ins_pipe(pipe_class_memory);
5196 %}
5197 
5198 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5199   // match-rule, false predicate
5200   match(Set dst (LoadB mem));
5201   predicate(false);
5202 
5203   format %{ "LBZ     $dst, $mem\n\t"
5204             "TWI     $dst\n\t"
5205             "ISYNC" %}
5206   size(12);
5207   ins_encode( enc_lbz_ac(dst, mem) );
5208   ins_pipe(pipe_class_memory);
5209 %}
5210 
5211 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5212 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5213   match(Set dst (LoadB mem));
5214   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5215   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5216   expand %{
5217     iRegIdst tmp;
5218     loadUB_indirect(tmp, mem);
5219     convB2I_reg_2(dst, tmp);
5220   %}
5221 %}
5222 
5223 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5224   match(Set dst (LoadB mem));
5225   ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5226   expand %{
5227     iRegIdst tmp;
5228     loadUB_indirect_ac(tmp, mem);
5229     convB2I_reg_2(dst, tmp);
5230   %}
5231 %}
5232 
5233 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5234   // match-rule, false predicate
5235   match(Set dst (LoadB mem));
5236   predicate(false);
5237 
5238   format %{ "LBZ     $dst, $mem" %}
5239   size(4);
5240   ins_encode( enc_lbz(dst, mem) );
5241   ins_pipe(pipe_class_memory);
5242 %}
5243 
5244 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5245   // match-rule, false predicate
5246   match(Set dst (LoadB mem));
5247   predicate(false);
5248 
5249   format %{ "LBZ     $dst, $mem\n\t"
5250             "TWI     $dst\n\t"
5251             "ISYNC" %}
5252   size(12);
5253   ins_encode( enc_lbz_ac(dst, mem) );
5254   ins_pipe(pipe_class_memory);
5255 %}
5256 
5257 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5258 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5259   match(Set dst (LoadB mem));
5260   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5261   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5262 
5263   expand %{
5264     iRegIdst tmp;
5265     loadUB_indOffset16(tmp, mem);
5266     convB2I_reg_2(dst, tmp);
5267   %}
5268 %}
5269 
5270 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5271   match(Set dst (LoadB mem));
5272   ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5273 
5274   expand %{
5275     iRegIdst tmp;
5276     loadUB_indOffset16_ac(tmp, mem);
5277     convB2I_reg_2(dst, tmp);
5278   %}
5279 %}
5280 
5281 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5282 instruct loadUB(iRegIdst dst, memory mem) %{
5283   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5284   match(Set dst (LoadUB mem));
5285   ins_cost(MEMORY_REF_COST);
5286 
5287   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to int" %}
5288   size(4);
5289   ins_encode( enc_lbz(dst, mem) );
5290   ins_pipe(pipe_class_memory);
5291 %}
5292 
5293 // Load  Unsigned Byte (8bit UNsigned) acquire.
5294 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5295   match(Set dst (LoadUB mem));
5296   ins_cost(3*MEMORY_REF_COST);
5297 
5298   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5299             "TWI     $dst\n\t"
5300             "ISYNC" %}
5301   size(12);
5302   ins_encode( enc_lbz_ac(dst, mem) );
5303   ins_pipe(pipe_class_memory);
5304 %}
5305 
5306 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5307 instruct loadUB2L(iRegLdst dst, memory mem) %{
5308   match(Set dst (ConvI2L (LoadUB mem)));
5309   predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5310   ins_cost(MEMORY_REF_COST);
5311 
5312   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to long" %}
5313   size(4);
5314   ins_encode( enc_lbz(dst, mem) );
5315   ins_pipe(pipe_class_memory);
5316 %}
5317 
5318 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5319   match(Set dst (ConvI2L (LoadUB mem)));
5320   ins_cost(3*MEMORY_REF_COST);
5321 
5322   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5323             "TWI     $dst\n\t"
5324             "ISYNC" %}
5325   size(12);
5326   ins_encode( enc_lbz_ac(dst, mem) );
5327   ins_pipe(pipe_class_memory);
5328 %}
5329 
5330 // Load Short (16bit signed)
5331 instruct loadS(iRegIdst dst, memory mem) %{
5332   match(Set dst (LoadS mem));
5333   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5334   ins_cost(MEMORY_REF_COST);
5335 
5336   format %{ "LHA     $dst, $mem" %}
5337   size(4);
5338   ins_encode %{
5339     // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5340     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5341     __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5342   %}
5343   ins_pipe(pipe_class_memory);
5344 %}
5345 
5346 // Load Short (16bit signed) acquire.
5347 instruct loadS_ac(iRegIdst dst, memory mem) %{
5348   match(Set dst (LoadS mem));
5349   ins_cost(3*MEMORY_REF_COST);
5350 
5351   format %{ "LHA     $dst, $mem\t acquire\n\t"
5352             "TWI     $dst\n\t"
5353             "ISYNC" %}
5354   size(12);
5355   ins_encode %{
5356     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5357     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5358     __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5359     __ twi_0($dst$$Register);
5360     __ isync();
5361   %}
5362   ins_pipe(pipe_class_memory);
5363 %}
5364 
5365 // Load Char (16bit unsigned)
5366 instruct loadUS(iRegIdst dst, memory mem) %{
5367   match(Set dst (LoadUS mem));
5368   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5369   ins_cost(MEMORY_REF_COST);
5370 
5371   format %{ "LHZ     $dst, $mem" %}
5372   size(4);
5373   ins_encode( enc_lhz(dst, mem) );
5374   ins_pipe(pipe_class_memory);
5375 %}
5376 
5377 // Load Char (16bit unsigned) acquire.
5378 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5379   match(Set dst (LoadUS mem));
5380   ins_cost(3*MEMORY_REF_COST);
5381 
5382   format %{ "LHZ     $dst, $mem \t// acquire\n\t"
5383             "TWI     $dst\n\t"
5384             "ISYNC" %}
5385   size(12);
5386   ins_encode( enc_lhz_ac(dst, mem) );
5387   ins_pipe(pipe_class_memory);
5388 %}
5389 
5390 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5391 instruct loadUS2L(iRegLdst dst, memory mem) %{
5392   match(Set dst (ConvI2L (LoadUS mem)));
5393   predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5394   ins_cost(MEMORY_REF_COST);
5395 
5396   format %{ "LHZ     $dst, $mem \t// short, zero-extend to long" %}
5397   size(4);
5398   ins_encode( enc_lhz(dst, mem) );
5399   ins_pipe(pipe_class_memory);
5400 %}
5401 
5402 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5403 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5404   match(Set dst (ConvI2L (LoadUS mem)));
5405   ins_cost(3*MEMORY_REF_COST);
5406 
5407   format %{ "LHZ     $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5408             "TWI     $dst\n\t"
5409             "ISYNC" %}
5410   size(12);
5411   ins_encode( enc_lhz_ac(dst, mem) );
5412   ins_pipe(pipe_class_memory);
5413 %}
5414 
5415 // Load Integer.
5416 instruct loadI(iRegIdst dst, memory mem) %{
5417   match(Set dst (LoadI mem));
5418   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5419   ins_cost(MEMORY_REF_COST);
5420 
5421   format %{ "LWZ     $dst, $mem" %}
5422   size(4);
5423   ins_encode( enc_lwz(dst, mem) );
5424   ins_pipe(pipe_class_memory);
5425 %}
5426 
5427 // Load Integer acquire.
5428 instruct loadI_ac(iRegIdst dst, memory mem) %{
5429   match(Set dst (LoadI mem));
5430   ins_cost(3*MEMORY_REF_COST);
5431 
5432   format %{ "LWZ     $dst, $mem \t// load acquire\n\t"
5433             "TWI     $dst\n\t"
5434             "ISYNC" %}
5435   size(12);
5436   ins_encode( enc_lwz_ac(dst, mem) );
5437   ins_pipe(pipe_class_memory);
5438 %}
5439 
5440 // Match loading integer and casting it to unsigned int in
5441 // long register.
5442 // LoadI + ConvI2L + AndL 0xffffffff.
5443 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5444   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5445   predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5446   ins_cost(MEMORY_REF_COST);
5447 
5448   format %{ "LWZ     $dst, $mem \t// zero-extend to long" %}
5449   size(4);
5450   ins_encode( enc_lwz(dst, mem) );
5451   ins_pipe(pipe_class_memory);
5452 %}
5453 
5454 // Match loading integer and casting it to long.
5455 instruct loadI2L(iRegLdst dst, memory mem) %{
5456   match(Set dst (ConvI2L (LoadI mem)));
5457   predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5458   ins_cost(MEMORY_REF_COST);
5459 
5460   format %{ "LWA     $dst, $mem \t// loadI2L" %}
5461   size(4);
5462   ins_encode %{
5463     // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5464     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5465     __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5466   %}
5467   ins_pipe(pipe_class_memory);
5468 %}
5469 
5470 // Match loading integer and casting it to long - acquire.
5471 instruct loadI2L_ac(iRegLdst dst, memory mem) %{
5472   match(Set dst (ConvI2L (LoadI mem)));
5473   ins_cost(3*MEMORY_REF_COST);
5474 
5475   format %{ "LWA     $dst, $mem \t// loadI2L acquire"
5476             "TWI     $dst\n\t"
5477             "ISYNC" %}
5478   size(12);
5479   ins_encode %{
5480     // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5481     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5482     __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5483     __ twi_0($dst$$Register);
5484     __ isync();
5485   %}
5486   ins_pipe(pipe_class_memory);
5487 %}
5488 
5489 // Load Long - aligned
5490 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5491   match(Set dst (LoadL mem));
5492   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5493   ins_cost(MEMORY_REF_COST);
5494 
5495   format %{ "LD      $dst, $mem \t// long" %}
5496   size(4);
5497   ins_encode( enc_ld(dst, mem) );
5498   ins_pipe(pipe_class_memory);
5499 %}
5500 
5501 // Load Long - aligned acquire.
5502 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5503   match(Set dst (LoadL mem));
5504   ins_cost(3*MEMORY_REF_COST);
5505 
5506   format %{ "LD      $dst, $mem \t// long acquire\n\t"
5507             "TWI     $dst\n\t"
5508             "ISYNC" %}
5509   size(12);
5510   ins_encode( enc_ld_ac(dst, mem) );
5511   ins_pipe(pipe_class_memory);
5512 %}
5513 
5514 // Load Long - UNaligned
5515 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5516   match(Set dst (LoadL_unaligned mem));
5517   // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5518   ins_cost(MEMORY_REF_COST);
5519 
5520   format %{ "LD      $dst, $mem \t// unaligned long" %}
5521   size(4);
5522   ins_encode( enc_ld(dst, mem) );
5523   ins_pipe(pipe_class_memory);
5524 %}
5525 
5526 // Load nodes for superwords
5527 
5528 // Load Aligned Packed Byte
5529 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5530   predicate(n->as_LoadVector()->memory_size() == 8);
5531   match(Set dst (LoadVector mem));
5532   ins_cost(MEMORY_REF_COST);
5533 
5534   format %{ "LD      $dst, $mem \t// load 8-byte Vector" %}
5535   size(4);
5536   ins_encode( enc_ld(dst, mem) );
5537   ins_pipe(pipe_class_memory);
5538 %}
5539 
5540 // Load Range, range = array length (=jint)
5541 instruct loadRange(iRegIdst dst, memory mem) %{
5542   match(Set dst (LoadRange mem));
5543   ins_cost(MEMORY_REF_COST);
5544 
5545   format %{ "LWZ     $dst, $mem \t// range" %}
5546   size(4);
5547   ins_encode( enc_lwz(dst, mem) );
5548   ins_pipe(pipe_class_memory);
5549 %}
5550 
5551 // Load Compressed Pointer
5552 instruct loadN(iRegNdst dst, memory mem) %{
5553   match(Set dst (LoadN mem));
5554   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5555   ins_cost(MEMORY_REF_COST);
5556 
5557   format %{ "LWZ     $dst, $mem \t// load compressed ptr" %}
5558   size(4);
5559   ins_encode( enc_lwz(dst, mem) );
5560   ins_pipe(pipe_class_memory);
5561 %}
5562 
5563 // Load Compressed Pointer acquire.
5564 instruct loadN_ac(iRegNdst dst, memory mem) %{
5565   match(Set dst (LoadN mem));
5566   ins_cost(3*MEMORY_REF_COST);
5567 
5568   format %{ "LWZ     $dst, $mem \t// load acquire compressed ptr\n\t"
5569             "TWI     $dst\n\t"
5570             "ISYNC" %}
5571   size(12);
5572   ins_encode( enc_lwz_ac(dst, mem) );
5573   ins_pipe(pipe_class_memory);
5574 %}
5575 
5576 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5577 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5578   match(Set dst (DecodeN (LoadN mem)));
5579   predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5580   ins_cost(MEMORY_REF_COST);
5581 
5582   format %{ "LWZ     $dst, $mem \t// DecodeN (unscaled)" %}
5583   size(4);
5584   ins_encode( enc_lwz(dst, mem) );
5585   ins_pipe(pipe_class_memory);
5586 %}
5587 
5588 instruct loadN2P_klass_unscaled(iRegPdst dst, memory mem) %{
5589   match(Set dst (DecodeNKlass (LoadNKlass mem)));
5590   // SAPJVM GL 2014-05-21 Differs.
5591   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0 &&
5592             _kids[0]->_leaf->as_Load()->is_unordered());
5593   ins_cost(MEMORY_REF_COST);
5594 
5595   format %{ "LWZ     $dst, $mem \t// DecodeN (unscaled)" %}
5596   size(4);
5597   ins_encode( enc_lwz(dst, mem) );
5598   ins_pipe(pipe_class_memory);
5599 %}
5600 
5601 // Load Pointer
5602 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5603   match(Set dst (LoadP mem));
5604   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5605   ins_cost(MEMORY_REF_COST);
5606 
5607   format %{ "LD      $dst, $mem \t// ptr" %}
5608   size(4);
5609   ins_encode( enc_ld(dst, mem) );
5610   ins_pipe(pipe_class_memory);
5611 %}
5612 
5613 // Load Pointer acquire.
5614 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5615   match(Set dst (LoadP mem));
5616   ins_cost(3*MEMORY_REF_COST);
5617 
5618   format %{ "LD      $dst, $mem \t// ptr acquire\n\t"
5619             "TWI     $dst\n\t"
5620             "ISYNC" %}
5621   size(12);
5622   ins_encode( enc_ld_ac(dst, mem) );
5623   ins_pipe(pipe_class_memory);
5624 %}
5625 
5626 // LoadP + CastP2L
5627 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5628   match(Set dst (CastP2X (LoadP mem)));
5629   predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5630   ins_cost(MEMORY_REF_COST);
5631 
5632   format %{ "LD      $dst, $mem \t// ptr + p2x" %}
5633   size(4);
5634   ins_encode( enc_ld(dst, mem) );
5635   ins_pipe(pipe_class_memory);
5636 %}
5637 
5638 // Load compressed klass pointer.
5639 instruct loadNKlass(iRegNdst dst, memory mem) %{
5640   match(Set dst (LoadNKlass mem));
5641   ins_cost(MEMORY_REF_COST);
5642 
5643   format %{ "LWZ     $dst, $mem \t// compressed klass ptr" %}
5644   size(4);
5645   ins_encode( enc_lwz(dst, mem) );
5646   ins_pipe(pipe_class_memory);
5647 %}
5648 
5649 // Load Klass Pointer
5650 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5651   match(Set dst (LoadKlass mem));
5652   ins_cost(MEMORY_REF_COST);
5653 
5654   format %{ "LD      $dst, $mem \t// klass ptr" %}
5655   size(4);
5656   ins_encode( enc_ld(dst, mem) );
5657   ins_pipe(pipe_class_memory);
5658 %}
5659 
5660 // Load Float
5661 instruct loadF(regF dst, memory mem) %{
5662   match(Set dst (LoadF mem));
5663   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5664   ins_cost(MEMORY_REF_COST);
5665 
5666   format %{ "LFS     $dst, $mem" %}
5667   size(4);
5668   ins_encode %{
5669     // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5670     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5671     __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5672   %}
5673   ins_pipe(pipe_class_memory);
5674 %}
5675 
5676 // Load Float acquire.
5677 instruct loadF_ac(regF dst, memory mem, flagsRegCR0 cr0) %{
5678   match(Set dst (LoadF mem));
5679   effect(TEMP cr0);
5680   ins_cost(3*MEMORY_REF_COST);
5681 
5682   format %{ "LFS     $dst, $mem \t// acquire\n\t"
5683             "FCMPU   cr0, $dst, $dst\n\t"
5684             "BNE     cr0, next\n"
5685             "next:\n\t"
5686             "ISYNC" %}
5687   size(16);
5688   ins_encode %{
5689     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5690     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5691     Label next;
5692     __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5693     __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5694     __ bne(CCR0, next);
5695     __ bind(next);
5696     __ isync();
5697   %}
5698   ins_pipe(pipe_class_memory);
5699 %}
5700 
5701 // Load Double - aligned
5702 instruct loadD(regD dst, memory mem) %{
5703   match(Set dst (LoadD mem));
5704   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5705   ins_cost(MEMORY_REF_COST);
5706 
5707   format %{ "LFD     $dst, $mem" %}
5708   size(4);
5709   ins_encode( enc_lfd(dst, mem) );
5710   ins_pipe(pipe_class_memory);
5711 %}
5712 
5713 // Load Double - aligned acquire.
5714 instruct loadD_ac(regD dst, memory mem, flagsRegCR0 cr0) %{
5715   match(Set dst (LoadD mem));
5716   effect(TEMP cr0);
5717   ins_cost(3*MEMORY_REF_COST);
5718 
5719   format %{ "LFD     $dst, $mem \t// acquire\n\t"
5720             "FCMPU   cr0, $dst, $dst\n\t"
5721             "BNE     cr0, next\n"
5722             "next:\n\t"
5723             "ISYNC" %}
5724   size(16);
5725   ins_encode %{
5726     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5727     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5728     Label next;
5729     __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5730     __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5731     __ bne(CCR0, next);
5732     __ bind(next);
5733     __ isync();
5734   %}
5735   ins_pipe(pipe_class_memory);
5736 %}
5737 
5738 // Load Double - UNaligned
5739 instruct loadD_unaligned(regD dst, memory mem) %{
5740   match(Set dst (LoadD_unaligned mem));
5741   // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5742   ins_cost(MEMORY_REF_COST);
5743 
5744   format %{ "LFD     $dst, $mem" %}
5745   size(4);
5746   ins_encode( enc_lfd(dst, mem) );
5747   ins_pipe(pipe_class_memory);
5748 %}
5749 
5750 //----------Constants--------------------------------------------------------
5751 
5752 // Load MachConstantTableBase: add hi offset to global toc.
5753 // TODO: Handle hidden register r29 in bundler!
5754 instruct loadToc_hi(iRegLdst dst) %{
5755   effect(DEF dst);
5756   ins_cost(DEFAULT_COST);
5757 
5758   format %{ "ADDIS   $dst, R29, DISP.hi \t// load TOC hi" %}
5759   size(4);
5760   ins_encode %{
5761     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5762     __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5763   %}
5764   ins_pipe(pipe_class_default);
5765 %}
5766 
5767 // Load MachConstantTableBase: add lo offset to global toc.
5768 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5769   effect(DEF dst, USE src);
5770   ins_cost(DEFAULT_COST);
5771 
5772   format %{ "ADDI    $dst, $src, DISP.lo \t// load TOC lo" %}
5773   size(4);
5774   ins_encode %{
5775     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5776     __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5777   %}
5778   ins_pipe(pipe_class_default);
5779 %}
5780 
5781 // Load 16-bit integer constant 0xssss????
5782 instruct loadConI16(iRegIdst dst, immI16 src) %{
5783   match(Set dst src);
5784 
5785   format %{ "LI      $dst, $src" %}
5786   size(4);
5787   ins_encode %{
5788     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5789     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5790   %}
5791   ins_pipe(pipe_class_default);
5792 %}
5793 
5794 // Load integer constant 0x????0000
5795 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5796   match(Set dst src);
5797   ins_cost(DEFAULT_COST);
5798 
5799   format %{ "LIS     $dst, $src.hi" %}
5800   size(4);
5801   ins_encode %{
5802     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5803     // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5804     __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5805   %}
5806   ins_pipe(pipe_class_default);
5807 %}
5808 
5809 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5810 // and sign extended), this adds the low 16 bits.
5811 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5812   // no match-rule, false predicate
5813   effect(DEF dst, USE src1, USE src2);
5814   predicate(false);
5815 
5816   format %{ "ORI     $dst, $src1.hi, $src2.lo" %}
5817   size(4);
5818   ins_encode %{
5819     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5820     __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5821   %}
5822   ins_pipe(pipe_class_default);
5823 %}
5824 
5825 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5826   match(Set dst src);
5827   ins_cost(DEFAULT_COST*2);
5828 
5829   expand %{
5830     // Would like to use $src$$constant.
5831     immI16 srcLo %{ _opnds[1]->constant() %}
5832     // srcHi can be 0000 if srcLo sign-extends to a negative number.
5833     immIhi16 srcHi %{ _opnds[1]->constant() %}
5834     iRegIdst tmpI;
5835     loadConIhi16(tmpI, srcHi);
5836     loadConI32_lo16(dst, tmpI, srcLo);
5837   %}
5838 %}
5839 
5840 // No constant pool entries required.
5841 instruct loadConL16(iRegLdst dst, immL16 src) %{
5842   match(Set dst src);
5843 
5844   format %{ "LI      $dst, $src \t// long" %}
5845   size(4);
5846   ins_encode %{
5847     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5848     __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5849   %}
5850   ins_pipe(pipe_class_default);
5851 %}
5852 
5853 // Load long constant 0xssssssss????0000
5854 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5855   match(Set dst src);
5856   ins_cost(DEFAULT_COST);
5857 
5858   format %{ "LIS     $dst, $src.hi \t// long" %}
5859   size(4);
5860   ins_encode %{
5861     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5862     __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5863   %}
5864   ins_pipe(pipe_class_default);
5865 %}
5866 
5867 // To load a 32 bit constant: merge lower 16 bits into already loaded
5868 // high 16 bits.
5869 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5870   // no match-rule, false predicate
5871   effect(DEF dst, USE src1, USE src2);
5872   predicate(false);
5873 
5874   format %{ "ORI     $dst, $src1, $src2.lo" %}
5875   size(4);
5876   ins_encode %{
5877     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5878     __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5879   %}
5880   ins_pipe(pipe_class_default);
5881 %}
5882 
5883 // Load 32-bit long constant
5884 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5885   match(Set dst src);
5886   ins_cost(DEFAULT_COST*2);
5887 
5888   expand %{
5889     // Would like to use $src$$constant.
5890     immL16     srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5891     // srcHi can be 0000 if srcLo sign-extends to a negative number.
5892     immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5893     iRegLdst tmpL;
5894     loadConL32hi16(tmpL, srcHi);
5895     loadConL32_lo16(dst, tmpL, srcLo);
5896   %}
5897 %}
5898 
5899 // Load long constant 0x????000000000000.
5900 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5901   match(Set dst src);
5902   ins_cost(DEFAULT_COST);
5903 
5904   expand %{
5905     immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5906     immI shift32 %{ 32 %}
5907     iRegLdst tmpL;
5908     loadConL32hi16(tmpL, srcHi);
5909     lshiftL_regL_immI(dst, tmpL, shift32);
5910   %}
5911 %}
5912 
5913 // Expand node for constant pool load: small offset.
5914 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5915   effect(DEF dst, USE src, USE toc);
5916   ins_cost(MEMORY_REF_COST);
5917 
5918   ins_num_consts(1);
5919   // Needed so that CallDynamicJavaDirect can compute the address of this
5920   // instruction for relocation.
5921   ins_field_cbuf_insts_offset(int);
5922 
5923   format %{ "LD      $dst, offset, $toc \t// load long $src from TOC" %}
5924   size(4);
5925   ins_encode( enc_load_long_constL(dst, src, toc) );
5926   ins_pipe(pipe_class_memory);
5927 %}
5928 
5929 // Expand node for constant pool load: large offset.
5930 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5931   effect(DEF dst, USE src, USE toc);
5932   predicate(false);
5933 
5934   ins_num_consts(1);
5935   ins_field_const_toc_offset(int);
5936   // Needed so that CallDynamicJavaDirect can compute the address of this
5937   // instruction for relocation.
5938   ins_field_cbuf_insts_offset(int);
5939 
5940   format %{ "ADDIS   $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5941   size(4);
5942   ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5943   ins_pipe(pipe_class_default);
5944 %}
5945 
5946 // Expand node for constant pool load: large offset.
5947 // No constant pool entries required.
5948 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5949   effect(DEF dst, USE src, USE base);
5950   predicate(false);
5951 
5952   ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5953 
5954   format %{ "LD      $dst, offset, $base \t// load long $src from TOC (lo)" %}
5955   size(4);
5956   ins_encode %{
5957     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5958     int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5959     __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5960   %}
5961   ins_pipe(pipe_class_memory);
5962 %}
5963 
5964 // Load long constant from constant table. Expand in case of
5965 // offset > 16 bit is needed.
5966 // Adlc adds toc node MachConstantTableBase.
5967 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5968   match(Set dst src);
5969   ins_cost(MEMORY_REF_COST);
5970 
5971   format %{ "LD      $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5972   // We can not inline the enc_class for the expand as that does not support constanttablebase.
5973   postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5974 %}
5975 
5976 // Load NULL as compressed oop.
5977 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5978   match(Set dst src);
5979   ins_cost(DEFAULT_COST);
5980 
5981   format %{ "LI      $dst, $src \t// compressed ptr" %}
5982   size(4);
5983   ins_encode %{
5984     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5985     __ li($dst$$Register, 0);
5986   %}
5987   ins_pipe(pipe_class_default);
5988 %}
5989 
5990 // Load hi part of compressed oop constant.
5991 instruct loadConN_hi(iRegNdst dst, immN src) %{
5992   effect(DEF dst, USE src);
5993   ins_cost(DEFAULT_COST);
5994 
5995   format %{ "LIS     $dst, $src \t// narrow oop hi" %}
5996   size(4);
5997   ins_encode %{
5998     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5999     __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
6000   %}
6001   ins_pipe(pipe_class_default);
6002 %}
6003 
6004 // Add lo part of compressed oop constant to already loaded hi part.
6005 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
6006   effect(DEF dst, USE src1, USE src2);
6007   ins_cost(DEFAULT_COST);
6008 
6009   format %{ "ORI     $dst, $src1, $src2 \t// narrow oop lo" %}
6010   size(4);
6011   ins_encode %{
6012     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6013     assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6014     int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
6015     RelocationHolder rspec = oop_Relocation::spec(oop_index);
6016     __ relocate(rspec, 1);
6017     __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
6018   %}
6019   ins_pipe(pipe_class_default);
6020 %}
6021 
6022 // Needed to postalloc expand loadConN: ConN is loaded as ConI
6023 // leaving the upper 32 bits with sign-extension bits.
6024 // This clears these bits: dst = src & 0xFFFFFFFF.
6025 // TODO: Eventually call this maskN_regN_FFFFFFFF.
6026 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
6027   effect(DEF dst, USE src);
6028   predicate(false);
6029 
6030   format %{ "MASK    $dst, $src, 0xFFFFFFFF" %} // mask
6031   size(4);
6032   ins_encode %{
6033     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6034     __ clrldi($dst$$Register, $src$$Register, 0x20);
6035   %}
6036   ins_pipe(pipe_class_default);
6037 %}
6038 
6039 // Optimize DecodeN for disjoint base.
6040 // Load base of compressed oops into a register
6041 instruct loadBase(iRegLdst dst) %{
6042   effect(DEF dst);
6043 
6044   format %{ "LoadConst $dst, heapbase" %}
6045   ins_encode %{
6046     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6047     __ load_const_optimized($dst$$Register, Universe::narrow_oop_base(), R0);
6048   %}
6049   ins_pipe(pipe_class_default);
6050 %}
6051 
6052 // Loading ConN must be postalloc expanded so that edges between
6053 // the nodes are safe. They may not interfere with a safepoint.
6054 // GL TODO: This needs three instructions: better put this into the constant pool.
6055 instruct loadConN_Ex(iRegNdst dst, immN src) %{
6056   match(Set dst src);
6057   ins_cost(DEFAULT_COST*2);
6058 
6059   format %{ "LoadN   $dst, $src \t// postalloc expanded" %} // mask
6060   postalloc_expand %{
6061     MachNode *m1 = new loadConN_hiNode();
6062     MachNode *m2 = new loadConN_loNode();
6063     MachNode *m3 = new clearMs32bNode();
6064     m1->add_req(NULL);
6065     m2->add_req(NULL, m1);
6066     m3->add_req(NULL, m2);
6067     m1->_opnds[0] = op_dst;
6068     m1->_opnds[1] = op_src;
6069     m2->_opnds[0] = op_dst;
6070     m2->_opnds[1] = op_dst;
6071     m2->_opnds[2] = op_src;
6072     m3->_opnds[0] = op_dst;
6073     m3->_opnds[1] = op_dst;
6074     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6075     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6076     ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6077     nodes->push(m1);
6078     nodes->push(m2);
6079     nodes->push(m3);
6080   %}
6081 %}
6082 
6083 // We have seen a safepoint between the hi and lo parts, and this node was handled
6084 // as an oop. Therefore this needs a match rule so that build_oop_map knows this is
6085 // not a narrow oop.
6086 instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{
6087   match(Set dst src);
6088   effect(DEF dst, USE src);
6089   ins_cost(DEFAULT_COST);
6090 
6091   format %{ "LIS     $dst, $src \t// narrow klass hi" %}
6092   size(4);
6093   ins_encode %{
6094     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6095     intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
6096     __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
6097   %}
6098   ins_pipe(pipe_class_default);
6099 %}
6100 
6101 // As loadConNKlass_hi this must be recognized as narrow klass, not oop!
6102 instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6103   match(Set dst src1);
6104   effect(TEMP src2);
6105   ins_cost(DEFAULT_COST);
6106 
6107   format %{ "MASK    $dst, $src2, 0xFFFFFFFF" %} // mask
6108   size(4);
6109   ins_encode %{
6110     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6111     __ clrldi($dst$$Register, $src2$$Register, 0x20);
6112   %}
6113   ins_pipe(pipe_class_default);
6114 %}
6115 
6116 // This needs a match rule so that build_oop_map knows this is
6117 // not a narrow oop.
6118 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6119   match(Set dst src1);
6120   effect(TEMP src2);
6121   ins_cost(DEFAULT_COST);
6122 
6123   format %{ "ORI     $dst, $src1, $src2 \t// narrow klass lo" %}
6124   size(4);
6125   ins_encode %{
6126     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
6127     intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
6128     assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6129     int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
6130     RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6131 
6132     __ relocate(rspec, 1);
6133     __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
6134   %}
6135   ins_pipe(pipe_class_default);
6136 %}
6137 
6138 // Loading ConNKlass must be postalloc expanded so that edges between
6139 // the nodes are safe. They may not interfere with a safepoint.
6140 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
6141   match(Set dst src);
6142   ins_cost(DEFAULT_COST*2);
6143 
6144   format %{ "LoadN   $dst, $src \t// postalloc expanded" %} // mask
6145   postalloc_expand %{
6146     // Load high bits into register. Sign extended.
6147     MachNode *m1 = new loadConNKlass_hiNode();
6148     m1->add_req(NULL);
6149     m1->_opnds[0] = op_dst;
6150     m1->_opnds[1] = op_src;
6151     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6152     nodes->push(m1);
6153 
6154     MachNode *m2 = m1;
6155     if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6156       // Value might be 1-extended. Mask out these bits.
6157       m2 = new loadConNKlass_maskNode();
6158       m2->add_req(NULL, m1);
6159       m2->_opnds[0] = op_dst;
6160       m2->_opnds[1] = op_src;
6161       m2->_opnds[2] = op_dst;
6162       ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6163       nodes->push(m2);
6164     }
6165 
6166     MachNode *m3 = new loadConNKlass_loNode();
6167     m3->add_req(NULL, m2);
6168     m3->_opnds[0] = op_dst;
6169     m3->_opnds[1] = op_src;
6170     m3->_opnds[2] = op_dst;
6171     ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6172     nodes->push(m3);
6173   %}
6174 %}
6175 
6176 // 0x1 is used in object initialization (initial object header).
6177 // No constant pool entries required.
6178 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6179   match(Set dst src);
6180 
6181   format %{ "LI      $dst, $src \t// ptr" %}
6182   size(4);
6183   ins_encode %{
6184     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6185     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6186   %}
6187   ins_pipe(pipe_class_default);
6188 %}
6189 
6190 // Expand node for constant pool load: small offset.
6191 // The match rule is needed to generate the correct bottom_type(),
6192 // however this node should never match. The use of predicate is not
6193 // possible since ADLC forbids predicates for chain rules. The higher
6194 // costs do not prevent matching in this case. For that reason the
6195 // operand immP_NM with predicate(false) is used.
6196 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6197   match(Set dst src);
6198   effect(TEMP toc);
6199 
6200   ins_num_consts(1);
6201 
6202   format %{ "LD      $dst, offset, $toc \t// load ptr $src from TOC" %}
6203   size(4);
6204   ins_encode( enc_load_long_constP(dst, src, toc) );
6205   ins_pipe(pipe_class_memory);
6206 %}
6207 
6208 // Expand node for constant pool load: large offset.
6209 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6210   effect(DEF dst, USE src, USE toc);
6211   predicate(false);
6212 
6213   ins_num_consts(1);
6214   ins_field_const_toc_offset(int);
6215 
6216   format %{ "ADDIS   $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6217   size(4);
6218   ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6219   ins_pipe(pipe_class_default);
6220 %}
6221 
6222 // Expand node for constant pool load: large offset.
6223 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6224   match(Set dst src);
6225   effect(TEMP base);
6226 
6227   ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6228 
6229   format %{ "LD      $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6230   size(4);
6231   ins_encode %{
6232     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6233     int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6234     __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6235   %}
6236   ins_pipe(pipe_class_memory);
6237 %}
6238 
6239 // Load pointer constant from constant table. Expand in case an
6240 // offset > 16 bit is needed.
6241 // Adlc adds toc node MachConstantTableBase.
6242 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6243   match(Set dst src);
6244   ins_cost(MEMORY_REF_COST);
6245 
6246   // This rule does not use "expand" because then
6247   // the result type is not known to be an Oop.  An ADLC
6248   // enhancement will be needed to make that work - not worth it!
6249 
6250   // If this instruction rematerializes, it prolongs the live range
6251   // of the toc node, causing illegal graphs.
6252   // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6253   ins_cannot_rematerialize(true);
6254 
6255   format %{ "LD    $dst, offset, $constanttablebase \t//  load ptr $src from table, postalloc expanded" %}
6256   postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6257 %}
6258 
6259 // Expand node for constant pool load: small offset.
6260 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6261   effect(DEF dst, USE src, USE toc);
6262   ins_cost(MEMORY_REF_COST);
6263 
6264   ins_num_consts(1);
6265 
6266   format %{ "LFS     $dst, offset, $toc \t// load float $src from TOC" %}
6267   size(4);
6268   ins_encode %{
6269     // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6270     address float_address = __ float_constant($src$$constant);
6271     __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6272   %}
6273   ins_pipe(pipe_class_memory);
6274 %}
6275 
6276 // Expand node for constant pool load: large offset.
6277 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6278   effect(DEF dst, USE src, USE toc);
6279   ins_cost(MEMORY_REF_COST);
6280 
6281   ins_num_consts(1);
6282 
6283   format %{ "ADDIS   $toc, $toc, offset_hi\n\t"
6284             "LFS     $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6285             "ADDIS   $toc, $toc, -offset_hi"%}
6286   size(12);
6287   ins_encode %{
6288     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6289     FloatRegister Rdst    = $dst$$FloatRegister;
6290     Register Rtoc         = $toc$$Register;
6291     address float_address = __ float_constant($src$$constant);
6292     int offset            = __ offset_to_method_toc(float_address);
6293     int hi = (offset + (1<<15))>>16;
6294     int lo = offset - hi * (1<<16);
6295 
6296     __ addis(Rtoc, Rtoc, hi);
6297     __ lfs(Rdst, lo, Rtoc);
6298     __ addis(Rtoc, Rtoc, -hi);
6299   %}
6300   ins_pipe(pipe_class_memory);
6301 %}
6302 
6303 // Adlc adds toc node MachConstantTableBase.
6304 instruct loadConF_Ex(regF dst, immF src) %{
6305   match(Set dst src);
6306   ins_cost(MEMORY_REF_COST);
6307 
6308   // See loadConP.
6309   ins_cannot_rematerialize(true);
6310 
6311   format %{ "LFS     $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6312   postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6313 %}
6314 
6315 // Expand node for constant pool load: small offset.
6316 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6317   effect(DEF dst, USE src, USE toc);
6318   ins_cost(MEMORY_REF_COST);
6319 
6320   ins_num_consts(1);
6321 
6322   format %{ "LFD     $dst, offset, $toc \t// load double $src from TOC" %}
6323   size(4);
6324   ins_encode %{
6325     // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6326     int offset =  __ offset_to_method_toc(__ double_constant($src$$constant));
6327     __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6328   %}
6329   ins_pipe(pipe_class_memory);
6330 %}
6331 
6332 // Expand node for constant pool load: large offset.
6333 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6334   effect(DEF dst, USE src, USE toc);
6335   ins_cost(MEMORY_REF_COST);
6336 
6337   ins_num_consts(1);
6338 
6339   format %{ "ADDIS   $toc, $toc, offset_hi\n\t"
6340             "LFD     $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6341             "ADDIS   $toc, $toc, -offset_hi" %}
6342   size(12);
6343   ins_encode %{
6344     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6345     FloatRegister Rdst    = $dst$$FloatRegister;
6346     Register      Rtoc    = $toc$$Register;
6347     address float_address = __ double_constant($src$$constant);
6348     int offset            = __ offset_to_method_toc(float_address);
6349     int hi = (offset + (1<<15))>>16;
6350     int lo = offset - hi * (1<<16);
6351 
6352     __ addis(Rtoc, Rtoc, hi);
6353     __ lfd(Rdst, lo, Rtoc);
6354     __ addis(Rtoc, Rtoc, -hi);
6355   %}
6356   ins_pipe(pipe_class_memory);
6357 %}
6358 
6359 // Adlc adds toc node MachConstantTableBase.
6360 instruct loadConD_Ex(regD dst, immD src) %{
6361   match(Set dst src);
6362   ins_cost(MEMORY_REF_COST);
6363 
6364   // See loadConP.
6365   ins_cannot_rematerialize(true);
6366 
6367   format %{ "ConD    $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6368   postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6369 %}
6370 
6371 // Prefetch instructions.
6372 // Must be safe to execute with invalid address (cannot fault).
6373 
6374 // Special prefetch versions which use the dcbz instruction.
6375 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6376   match(PrefetchAllocation (AddP mem src));
6377   predicate(AllocatePrefetchStyle == 3);
6378   ins_cost(MEMORY_REF_COST);
6379 
6380   format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6381   size(4);
6382   ins_encode %{
6383     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6384     __ dcbz($src$$Register, $mem$$base$$Register);
6385   %}
6386   ins_pipe(pipe_class_memory);
6387 %}
6388 
6389 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6390   match(PrefetchAllocation mem);
6391   predicate(AllocatePrefetchStyle == 3);
6392   ins_cost(MEMORY_REF_COST);
6393 
6394   format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6395   size(4);
6396   ins_encode %{
6397     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6398     __ dcbz($mem$$base$$Register);
6399   %}
6400   ins_pipe(pipe_class_memory);
6401 %}
6402 
6403 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6404   match(PrefetchAllocation (AddP mem src));
6405   predicate(AllocatePrefetchStyle != 3);
6406   ins_cost(MEMORY_REF_COST);
6407 
6408   format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6409   size(4);
6410   ins_encode %{
6411     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6412     __ dcbtst($src$$Register, $mem$$base$$Register);
6413   %}
6414   ins_pipe(pipe_class_memory);
6415 %}
6416 
6417 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6418   match(PrefetchAllocation mem);
6419   predicate(AllocatePrefetchStyle != 3);
6420   ins_cost(MEMORY_REF_COST);
6421 
6422   format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6423   size(4);
6424   ins_encode %{
6425     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6426     __ dcbtst($mem$$base$$Register);
6427   %}
6428   ins_pipe(pipe_class_memory);
6429 %}
6430 
6431 //----------Store Instructions-------------------------------------------------
6432 
6433 // Store Byte
6434 instruct storeB(memory mem, iRegIsrc src) %{
6435   match(Set mem (StoreB mem src));
6436   ins_cost(MEMORY_REF_COST);
6437 
6438   format %{ "STB     $src, $mem \t// byte" %}
6439   size(4);
6440   ins_encode %{
6441     // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6442     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6443     __ stb($src$$Register, Idisp, $mem$$base$$Register);
6444   %}
6445   ins_pipe(pipe_class_memory);
6446 %}
6447 
6448 // Store Char/Short
6449 instruct storeC(memory mem, iRegIsrc src) %{
6450   match(Set mem (StoreC mem src));
6451   ins_cost(MEMORY_REF_COST);
6452 
6453   format %{ "STH     $src, $mem \t// short" %}
6454   size(4);
6455   ins_encode %{
6456     // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6457     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6458     __ sth($src$$Register, Idisp, $mem$$base$$Register);
6459   %}
6460   ins_pipe(pipe_class_memory);
6461 %}
6462 
6463 // Store Integer
6464 instruct storeI(memory mem, iRegIsrc src) %{
6465   match(Set mem (StoreI mem src));
6466   ins_cost(MEMORY_REF_COST);
6467 
6468   format %{ "STW     $src, $mem" %}
6469   size(4);
6470   ins_encode( enc_stw(src, mem) );
6471   ins_pipe(pipe_class_memory);
6472 %}
6473 
6474 // ConvL2I + StoreI.
6475 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6476   match(Set mem (StoreI mem (ConvL2I src)));
6477   ins_cost(MEMORY_REF_COST);
6478 
6479   format %{ "STW     l2i($src), $mem" %}
6480   size(4);
6481   ins_encode( enc_stw(src, mem) );
6482   ins_pipe(pipe_class_memory);
6483 %}
6484 
6485 // Store Long
6486 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6487   match(Set mem (StoreL mem src));
6488   ins_cost(MEMORY_REF_COST);
6489 
6490   format %{ "STD     $src, $mem \t// long" %}
6491   size(4);
6492   ins_encode( enc_std(src, mem) );
6493   ins_pipe(pipe_class_memory);
6494 %}
6495 
6496 // Store super word nodes.
6497 
6498 // Store Aligned Packed Byte long register to memory
6499 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6500   predicate(n->as_StoreVector()->memory_size() == 8);
6501   match(Set mem (StoreVector mem src));
6502   ins_cost(MEMORY_REF_COST);
6503 
6504   format %{ "STD     $mem, $src \t// packed8B" %}
6505   size(4);
6506   ins_encode( enc_std(src, mem) );
6507   ins_pipe(pipe_class_memory);
6508 %}
6509 
6510 // Store Compressed Oop
6511 instruct storeN(memory dst, iRegN_P2N src) %{
6512   match(Set dst (StoreN dst src));
6513   ins_cost(MEMORY_REF_COST);
6514 
6515   format %{ "STW     $src, $dst \t// compressed oop" %}
6516   size(4);
6517   ins_encode( enc_stw(src, dst) );
6518   ins_pipe(pipe_class_memory);
6519 %}
6520 
6521 // Store Compressed KLass
6522 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6523   match(Set dst (StoreNKlass dst src));
6524   ins_cost(MEMORY_REF_COST);
6525 
6526   format %{ "STW     $src, $dst \t// compressed klass" %}
6527   size(4);
6528   ins_encode( enc_stw(src, dst) );
6529   ins_pipe(pipe_class_memory);
6530 %}
6531 
6532 // Store Pointer
6533 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6534   match(Set dst (StoreP dst src));
6535   ins_cost(MEMORY_REF_COST);
6536 
6537   format %{ "STD     $src, $dst \t// ptr" %}
6538   size(4);
6539   ins_encode( enc_std(src, dst) );
6540   ins_pipe(pipe_class_memory);
6541 %}
6542 
6543 // Store Float
6544 instruct storeF(memory mem, regF src) %{
6545   match(Set mem (StoreF mem src));
6546   ins_cost(MEMORY_REF_COST);
6547 
6548   format %{ "STFS    $src, $mem" %}
6549   size(4);
6550   ins_encode( enc_stfs(src, mem) );
6551   ins_pipe(pipe_class_memory);
6552 %}
6553 
6554 // Store Double
6555 instruct storeD(memory mem, regD src) %{
6556   match(Set mem (StoreD mem src));
6557   ins_cost(MEMORY_REF_COST);
6558 
6559   format %{ "STFD    $src, $mem" %}
6560   size(4);
6561   ins_encode( enc_stfd(src, mem) );
6562   ins_pipe(pipe_class_memory);
6563 %}
6564 
6565 //----------Store Instructions With Zeros--------------------------------------
6566 
6567 // Card-mark for CMS garbage collection.
6568 // This cardmark does an optimization so that it must not always
6569 // do a releasing store. For this, it gets the address of
6570 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6571 // (Using releaseFieldAddr in the match rule is a hack.)
6572 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
6573   match(Set mem (StoreCM mem releaseFieldAddr));
6574   effect(TEMP crx);
6575   predicate(false);
6576   ins_cost(MEMORY_REF_COST);
6577 
6578   // See loadConP.
6579   ins_cannot_rematerialize(true);
6580 
6581   format %{ "STB     #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6582   ins_encode( enc_cms_card_mark(mem, releaseFieldAddr, crx) );
6583   ins_pipe(pipe_class_memory);
6584 %}
6585 
6586 // Card-mark for CMS garbage collection.
6587 // This cardmark does an optimization so that it must not always
6588 // do a releasing store. For this, it needs the constant address of
6589 // CMSCollectorCardTableModRefBSExt::_requires_release.
6590 // This constant address is split off here by expand so we can use
6591 // adlc / matcher functionality to load it from the constant section.
6592 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6593   match(Set mem (StoreCM mem zero));
6594   predicate(UseConcMarkSweepGC);
6595 
6596   expand %{
6597     immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6598     iRegLdst releaseFieldAddress;
6599     flagsReg crx;
6600     loadConL_Ex(releaseFieldAddress, baseImm);
6601     storeCM_CMS(mem, releaseFieldAddress, crx);
6602   %}
6603 %}
6604 
6605 instruct storeCM_G1(memory mem, immI_0 zero) %{
6606   match(Set mem (StoreCM mem zero));
6607   predicate(UseG1GC);
6608   ins_cost(MEMORY_REF_COST);
6609 
6610   ins_cannot_rematerialize(true);
6611 
6612   format %{ "STB     #0, $mem \t// CMS card-mark byte store (G1)" %}
6613   size(8);
6614   ins_encode %{
6615     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6616     __ li(R0, 0);
6617     //__ release(); // G1: oops are allowed to get visible after dirty marking
6618     guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6619     __ stb(R0, $mem$$disp, $mem$$base$$Register);
6620   %}
6621   ins_pipe(pipe_class_memory);
6622 %}
6623 
6624 // Convert oop pointer into compressed form.
6625 
6626 // Nodes for postalloc expand.
6627 
6628 // Shift node for expand.
6629 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6630   // The match rule is needed to make it a 'MachTypeNode'!
6631   match(Set dst (EncodeP src));
6632   predicate(false);
6633 
6634   format %{ "SRDI    $dst, $src, 3 \t// encode" %}
6635   size(4);
6636   ins_encode %{
6637     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6638     __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6639   %}
6640   ins_pipe(pipe_class_default);
6641 %}
6642 
6643 // Add node for expand.
6644 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6645   // The match rule is needed to make it a 'MachTypeNode'!
6646   match(Set dst (EncodeP src));
6647   predicate(false);
6648 
6649   format %{ "SUB     $dst, $src, oop_base \t// encode" %}
6650   ins_encode %{
6651     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6652     __ sub_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6653   %}
6654   ins_pipe(pipe_class_default);
6655 %}
6656 
6657 // Conditional sub base.
6658 instruct cond_sub_base(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6659   // The match rule is needed to make it a 'MachTypeNode'!
6660   match(Set dst (EncodeP (Binary crx src1)));
6661   predicate(false);
6662 
6663   format %{ "BEQ     $crx, done\n\t"
6664             "SUB     $dst, $src1, heapbase \t// encode: subtract base if != NULL\n"
6665             "done:" %}
6666   ins_encode %{
6667     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6668     Label done;
6669     __ beq($crx$$CondRegister, done);
6670     __ sub_const_optimized($dst$$Register, $src1$$Register, Universe::narrow_oop_base(), R0);
6671     __ bind(done);
6672   %}
6673   ins_pipe(pipe_class_default);
6674 %}
6675 
6676 // Power 7 can use isel instruction
6677 instruct cond_set_0_oop(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6678   // The match rule is needed to make it a 'MachTypeNode'!
6679   match(Set dst (EncodeP (Binary crx src1)));
6680   predicate(false);
6681 
6682   format %{ "CMOVE   $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6683   size(4);
6684   ins_encode %{
6685     // This is a Power7 instruction for which no machine description exists.
6686     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6687     __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6688   %}
6689   ins_pipe(pipe_class_default);
6690 %}
6691 
6692 // Disjoint narrow oop base.
6693 instruct encodeP_Disjoint(iRegNdst dst, iRegPsrc src) %{
6694   match(Set dst (EncodeP src));
6695   predicate(Universe::narrow_oop_base_disjoint());
6696 
6697   format %{ "EXTRDI  $dst, $src, #32, #3 \t// encode with disjoint base" %}
6698   size(4);
6699   ins_encode %{
6700     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6701     __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6702   %}
6703   ins_pipe(pipe_class_default);
6704 %}
6705 
6706 // shift != 0, base != 0
6707 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6708   match(Set dst (EncodeP src));
6709   effect(TEMP crx);
6710   predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6711             Universe::narrow_oop_shift() != 0 &&
6712             Universe::narrow_oop_base_overlaps());
6713 
6714   format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6715   postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6716 %}
6717 
6718 // shift != 0, base != 0
6719 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6720   match(Set dst (EncodeP src));
6721   predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6722             Universe::narrow_oop_shift() != 0 &&
6723             Universe::narrow_oop_base_overlaps());
6724 
6725   format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6726   postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6727 %}
6728 
6729 // shift != 0, base == 0
6730 // TODO: This is the same as encodeP_shift. Merge!
6731 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6732   match(Set dst (EncodeP src));
6733   predicate(Universe::narrow_oop_shift() != 0 &&
6734             Universe::narrow_oop_base() ==0);
6735 
6736   format %{ "SRDI    $dst, $src, #3 \t// encodeP, $src != NULL" %}
6737   size(4);
6738   ins_encode %{
6739     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6740     __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6741   %}
6742   ins_pipe(pipe_class_default);
6743 %}
6744 
6745 // Compressed OOPs with narrow_oop_shift == 0.
6746 // shift == 0, base == 0
6747 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6748   match(Set dst (EncodeP src));
6749   predicate(Universe::narrow_oop_shift() == 0);
6750 
6751   format %{ "MR      $dst, $src \t// Ptr->Narrow" %}
6752   // variable size, 0 or 4.
6753   ins_encode %{
6754     // TODO: PPC port $archOpcode(ppc64Opcode_or);
6755     __ mr_if_needed($dst$$Register, $src$$Register);
6756   %}
6757   ins_pipe(pipe_class_default);
6758 %}
6759 
6760 // Decode nodes.
6761 
6762 // Shift node for expand.
6763 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6764   // The match rule is needed to make it a 'MachTypeNode'!
6765   match(Set dst (DecodeN src));
6766   predicate(false);
6767 
6768   format %{ "SLDI    $dst, $src, #3 \t// DecodeN" %}
6769   size(4);
6770   ins_encode %{
6771     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6772     __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6773   %}
6774   ins_pipe(pipe_class_default);
6775 %}
6776 
6777 // Add node for expand.
6778 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6779   // The match rule is needed to make it a 'MachTypeNode'!
6780   match(Set dst (DecodeN src));
6781   predicate(false);
6782 
6783   format %{ "ADD     $dst, $src, heapbase \t// DecodeN, add oop base" %}
6784   ins_encode %{
6785     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6786     __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6787   %}
6788   ins_pipe(pipe_class_default);
6789 %}
6790 
6791 // conditianal add base for expand
6792 instruct cond_add_base(iRegPdst dst, flagsRegSrc crx, iRegPsrc src) %{
6793   // The match rule is needed to make it a 'MachTypeNode'!
6794   // NOTICE that the rule is nonsense - we just have to make sure that:
6795   //  - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6796   //  - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6797   match(Set dst (DecodeN (Binary crx src)));
6798   predicate(false);
6799 
6800   format %{ "BEQ     $crx, done\n\t"
6801             "ADD     $dst, $src, heapbase \t// DecodeN: add oop base if $src != NULL\n"
6802             "done:" %}
6803   ins_encode %{
6804     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6805     Label done;
6806     __ beq($crx$$CondRegister, done);
6807     __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6808     __ bind(done);
6809   %}
6810   ins_pipe(pipe_class_default);
6811 %}
6812 
6813 instruct cond_set_0_ptr(iRegPdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6814   // The match rule is needed to make it a 'MachTypeNode'!
6815   // NOTICE that the rule is nonsense - we just have to make sure that:
6816   //  - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6817   //  - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6818   match(Set dst (DecodeN (Binary crx src1)));
6819   predicate(false);
6820 
6821   format %{ "CMOVE   $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6822   size(4);
6823   ins_encode %{
6824     // This is a Power7 instruction for which no machine description exists.
6825     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6826     __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6827   %}
6828   ins_pipe(pipe_class_default);
6829 %}
6830 
6831 //  shift != 0, base != 0
6832 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6833   match(Set dst (DecodeN src));
6834   predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6835              n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6836             Universe::narrow_oop_shift() != 0 &&
6837             Universe::narrow_oop_base() != 0);
6838   ins_cost(4 * DEFAULT_COST); // Should be more expensive than decodeN_Disjoint_isel_Ex.
6839   effect(TEMP crx);
6840 
6841   format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6842   postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6843 %}
6844 
6845 // shift != 0, base == 0
6846 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6847   match(Set dst (DecodeN src));
6848   predicate(Universe::narrow_oop_shift() != 0 &&
6849             Universe::narrow_oop_base() == 0);
6850 
6851   format %{ "SLDI    $dst, $src, #3 \t// DecodeN (zerobased)" %}
6852   size(4);
6853   ins_encode %{
6854     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6855     __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6856   %}
6857   ins_pipe(pipe_class_default);
6858 %}
6859 
6860 // Optimize DecodeN for disjoint base.
6861 // Shift narrow oop and or it into register that already contains the heap base.
6862 // Base == dst must hold, and is assured by construction in postaloc_expand.
6863 instruct decodeN_mergeDisjoint(iRegPdst dst, iRegNsrc src, iRegLsrc base) %{
6864   match(Set dst (DecodeN src));
6865   effect(TEMP base);
6866   predicate(false);
6867 
6868   format %{ "RLDIMI  $dst, $src, shift, 32-shift \t// DecodeN (disjoint base)" %}
6869   size(4);
6870   ins_encode %{
6871     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
6872     __ rldimi($dst$$Register, $src$$Register, Universe::narrow_oop_shift(), 32-Universe::narrow_oop_shift());
6873   %}
6874   ins_pipe(pipe_class_default);
6875 %}
6876 
6877 // Optimize DecodeN for disjoint base.
6878 // This node requires only one cycle on the critical path.
6879 // We must postalloc_expand as we can not express use_def effects where
6880 // the used register is L and the def'ed register P.
6881 instruct decodeN_Disjoint_notNull_Ex(iRegPdst dst, iRegNsrc src) %{
6882   match(Set dst (DecodeN src));
6883   effect(TEMP_DEF dst);
6884   predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6885              n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6886             Universe::narrow_oop_base_disjoint());
6887   ins_cost(DEFAULT_COST);
6888 
6889   format %{ "MOV     $dst, heapbase \t\n"
6890             "RLDIMI  $dst, $src, shift, 32-shift \t// decode with disjoint base" %}
6891   postalloc_expand %{
6892     loadBaseNode *n1 = new loadBaseNode();
6893     n1->add_req(NULL);
6894     n1->_opnds[0] = op_dst;
6895 
6896     decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6897     n2->add_req(n_region, n_src, n1);
6898     n2->_opnds[0] = op_dst;
6899     n2->_opnds[1] = op_src;
6900     n2->_opnds[2] = op_dst;
6901     n2->_bottom_type = _bottom_type;
6902 
6903     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6904     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6905 
6906     nodes->push(n1);
6907     nodes->push(n2);
6908   %}
6909 %}
6910 
6911 instruct decodeN_Disjoint_isel_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6912   match(Set dst (DecodeN src));
6913   effect(TEMP_DEF dst, TEMP crx);
6914   predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6915              n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6916             Universe::narrow_oop_base_disjoint() && VM_Version::has_isel());
6917   ins_cost(3 * DEFAULT_COST);
6918 
6919   format %{ "DecodeN  $dst, $src \t// decode with disjoint base using isel" %}
6920   postalloc_expand %{
6921     loadBaseNode *n1 = new loadBaseNode();
6922     n1->add_req(NULL);
6923     n1->_opnds[0] = op_dst;
6924 
6925     cmpN_reg_imm0Node *n_compare  = new cmpN_reg_imm0Node();
6926     n_compare->add_req(n_region, n_src);
6927     n_compare->_opnds[0] = op_crx;
6928     n_compare->_opnds[1] = op_src;
6929     n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
6930 
6931     decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6932     n2->add_req(n_region, n_src, n1);
6933     n2->_opnds[0] = op_dst;
6934     n2->_opnds[1] = op_src;
6935     n2->_opnds[2] = op_dst;
6936     n2->_bottom_type = _bottom_type;
6937 
6938     cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
6939     n_cond_set->add_req(n_region, n_compare, n2);
6940     n_cond_set->_opnds[0] = op_dst;
6941     n_cond_set->_opnds[1] = op_crx;
6942     n_cond_set->_opnds[2] = op_dst;
6943     n_cond_set->_bottom_type = _bottom_type;
6944 
6945     assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
6946     ra_->set_oop(n_cond_set, true);
6947 
6948     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6949     ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
6950     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6951     ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6952 
6953     nodes->push(n1);
6954     nodes->push(n_compare);
6955     nodes->push(n2);
6956     nodes->push(n_cond_set);
6957   %}
6958 %}
6959 
6960 // src != 0, shift != 0, base != 0
6961 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6962   match(Set dst (DecodeN src));
6963   predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6964              n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6965             Universe::narrow_oop_shift() != 0 &&
6966             Universe::narrow_oop_base() != 0);
6967   ins_cost(2 * DEFAULT_COST);
6968 
6969   format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6970   postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6971 %}
6972 
6973 // Compressed OOPs with narrow_oop_shift == 0.
6974 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6975   match(Set dst (DecodeN src));
6976   predicate(Universe::narrow_oop_shift() == 0);
6977   ins_cost(DEFAULT_COST);
6978 
6979   format %{ "MR      $dst, $src \t// DecodeN (unscaled)" %}
6980   // variable size, 0 or 4.
6981   ins_encode %{
6982     // TODO: PPC port $archOpcode(ppc64Opcode_or);
6983     __ mr_if_needed($dst$$Register, $src$$Register);
6984   %}
6985   ins_pipe(pipe_class_default);
6986 %}
6987 
6988 // Convert compressed oop into int for vectors alignment masking.
6989 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6990   match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6991   predicate(Universe::narrow_oop_shift() == 0);
6992   ins_cost(DEFAULT_COST);
6993 
6994   format %{ "MR      $dst, $src \t// (int)DecodeN (unscaled)" %}
6995   // variable size, 0 or 4.
6996   ins_encode %{
6997     // TODO: PPC port $archOpcode(ppc64Opcode_or);
6998     __ mr_if_needed($dst$$Register, $src$$Register);
6999   %}
7000   ins_pipe(pipe_class_default);
7001 %}
7002 
7003 // Convert klass pointer into compressed form.
7004 
7005 // Nodes for postalloc expand.
7006 
7007 // Shift node for expand.
7008 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
7009   // The match rule is needed to make it a 'MachTypeNode'!
7010   match(Set dst (EncodePKlass src));
7011   predicate(false);
7012 
7013   format %{ "SRDI    $dst, $src, 3 \t// encode" %}
7014   size(4);
7015   ins_encode %{
7016     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
7017     __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7018   %}
7019   ins_pipe(pipe_class_default);
7020 %}
7021 
7022 // Add node for expand.
7023 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7024   // The match rule is needed to make it a 'MachTypeNode'!
7025   match(Set dst (EncodePKlass (Binary base src)));
7026   predicate(false);
7027 
7028   format %{ "SUB     $dst, $base, $src \t// encode" %}
7029   size(4);
7030   ins_encode %{
7031     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7032     __ subf($dst$$Register, $base$$Register, $src$$Register);
7033   %}
7034   ins_pipe(pipe_class_default);
7035 %}
7036 
7037 // Disjoint narrow oop base.
7038 instruct encodePKlass_Disjoint(iRegNdst dst, iRegPsrc src) %{
7039   match(Set dst (EncodePKlass src));
7040   predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
7041 
7042   format %{ "EXTRDI  $dst, $src, #32, #3 \t// encode with disjoint base" %}
7043   size(4);
7044   ins_encode %{
7045     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
7046     __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32);
7047   %}
7048   ins_pipe(pipe_class_default);
7049 %}
7050 
7051 // shift != 0, base != 0
7052 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
7053   match(Set dst (EncodePKlass (Binary base src)));
7054   predicate(false);
7055 
7056   format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7057   postalloc_expand %{
7058     encodePKlass_sub_baseNode *n1 = new encodePKlass_sub_baseNode();
7059     n1->add_req(n_region, n_base, n_src);
7060     n1->_opnds[0] = op_dst;
7061     n1->_opnds[1] = op_base;
7062     n1->_opnds[2] = op_src;
7063     n1->_bottom_type = _bottom_type;
7064 
7065     encodePKlass_shiftNode *n2 = new encodePKlass_shiftNode();
7066     n2->add_req(n_region, n1);
7067     n2->_opnds[0] = op_dst;
7068     n2->_opnds[1] = op_dst;
7069     n2->_bottom_type = _bottom_type;
7070     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7071     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7072 
7073     nodes->push(n1);
7074     nodes->push(n2);
7075   %}
7076 %}
7077 
7078 // shift != 0, base != 0
7079 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
7080   match(Set dst (EncodePKlass src));
7081   //predicate(Universe::narrow_klass_shift() != 0 &&
7082   //          true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
7083 
7084   //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7085   ins_cost(DEFAULT_COST*2);  // Don't count constant.
7086   expand %{
7087     immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
7088     iRegLdst base;
7089     loadConL_Ex(base, baseImm);
7090     encodePKlass_not_null_Ex(dst, base, src);
7091   %}
7092 %}
7093 
7094 // Decode nodes.
7095 
7096 // Shift node for expand.
7097 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
7098   // The match rule is needed to make it a 'MachTypeNode'!
7099   match(Set dst (DecodeNKlass src));
7100   predicate(false);
7101 
7102   format %{ "SLDI    $dst, $src, #3 \t// DecodeNKlass" %}
7103   size(4);
7104   ins_encode %{
7105     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
7106     __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7107   %}
7108   ins_pipe(pipe_class_default);
7109 %}
7110 
7111 // Add node for expand.
7112 
7113 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7114   // The match rule is needed to make it a 'MachTypeNode'!
7115   match(Set dst (DecodeNKlass (Binary base src)));
7116   predicate(false);
7117 
7118   format %{ "ADD     $dst, $base, $src \t// DecodeNKlass, add klass base" %}
7119   size(4);
7120   ins_encode %{
7121     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7122     __ add($dst$$Register, $base$$Register, $src$$Register);
7123   %}
7124   ins_pipe(pipe_class_default);
7125 %}
7126 
7127 // src != 0, shift != 0, base != 0
7128 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
7129   match(Set dst (DecodeNKlass (Binary base src)));
7130   //effect(kill src); // We need a register for the immediate result after shifting.
7131   predicate(false);
7132 
7133   format %{ "DecodeNKlass $dst =  $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
7134   postalloc_expand %{
7135     decodeNKlass_add_baseNode *n1 = new decodeNKlass_add_baseNode();
7136     n1->add_req(n_region, n_base, n_src);
7137     n1->_opnds[0] = op_dst;
7138     n1->_opnds[1] = op_base;
7139     n1->_opnds[2] = op_src;
7140     n1->_bottom_type = _bottom_type;
7141 
7142     decodeNKlass_shiftNode *n2 = new decodeNKlass_shiftNode();
7143     n2->add_req(n_region, n1);
7144     n2->_opnds[0] = op_dst;
7145     n2->_opnds[1] = op_dst;
7146     n2->_bottom_type = _bottom_type;
7147 
7148     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7149     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7150 
7151     nodes->push(n1);
7152     nodes->push(n2);
7153   %}
7154 %}
7155 
7156 // src != 0, shift != 0, base != 0
7157 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7158   match(Set dst (DecodeNKlass src));
7159   // predicate(Universe::narrow_klass_shift() != 0 &&
7160   //           Universe::narrow_klass_base() != 0);
7161 
7162   //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7163 
7164   ins_cost(DEFAULT_COST*2);  // Don't count constant.
7165   expand %{
7166     // We add first, then we shift. Like this, we can get along with one register less.
7167     // But we have to load the base pre-shifted.
7168     immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7169     iRegLdst base;
7170     loadConL_Ex(base, baseImm);
7171     decodeNKlass_notNull_addBase_Ex(dst, base, src);
7172   %}
7173 %}
7174 
7175 //----------MemBar Instructions-----------------------------------------------
7176 // Memory barrier flavors
7177 
7178 instruct membar_acquire() %{
7179   match(LoadFence);
7180   ins_cost(4*MEMORY_REF_COST);
7181 
7182   format %{ "MEMBAR-acquire" %}
7183   size(4);
7184   ins_encode %{
7185     // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7186     __ acquire();
7187   %}
7188   ins_pipe(pipe_class_default);
7189 %}
7190 
7191 instruct unnecessary_membar_acquire() %{
7192   match(MemBarAcquire);
7193   ins_cost(0);
7194 
7195   format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7196   size(0);
7197   ins_encode( /*empty*/ );
7198   ins_pipe(pipe_class_default);
7199 %}
7200 
7201 instruct membar_acquire_lock() %{
7202   match(MemBarAcquireLock);
7203   ins_cost(0);
7204 
7205   format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7206   size(0);
7207   ins_encode( /*empty*/ );
7208   ins_pipe(pipe_class_default);
7209 %}
7210 
7211 instruct membar_release() %{
7212   match(MemBarRelease);
7213   match(StoreFence);
7214   ins_cost(4*MEMORY_REF_COST);
7215 
7216   format %{ "MEMBAR-release" %}
7217   size(4);
7218   ins_encode %{
7219     // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7220     __ release();
7221   %}
7222   ins_pipe(pipe_class_default);
7223 %}
7224 
7225 instruct membar_storestore() %{
7226   match(MemBarStoreStore);
7227   ins_cost(4*MEMORY_REF_COST);
7228 
7229   format %{ "MEMBAR-store-store" %}
7230   size(4);
7231   ins_encode %{
7232     // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7233     __ membar(Assembler::StoreStore);
7234   %}
7235   ins_pipe(pipe_class_default);
7236 %}
7237 
7238 instruct membar_release_lock() %{
7239   match(MemBarReleaseLock);
7240   ins_cost(0);
7241 
7242   format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7243   size(0);
7244   ins_encode( /*empty*/ );
7245   ins_pipe(pipe_class_default);
7246 %}
7247 
7248 instruct membar_volatile() %{
7249   match(MemBarVolatile);
7250   ins_cost(4*MEMORY_REF_COST);
7251 
7252   format %{ "MEMBAR-volatile" %}
7253   size(4);
7254   ins_encode %{
7255     // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7256     __ fence();
7257   %}
7258   ins_pipe(pipe_class_default);
7259 %}
7260 
7261 // This optimization is wrong on PPC. The following pattern is not supported:
7262 //  MemBarVolatile
7263 //   ^        ^
7264 //   |        |
7265 //  CtrlProj MemProj
7266 //   ^        ^
7267 //   |        |
7268 //   |       Load
7269 //   |
7270 //  MemBarVolatile
7271 //
7272 //  The first MemBarVolatile could get optimized out! According to
7273 //  Vladimir, this pattern can not occur on Oracle platforms.
7274 //  However, it does occur on PPC64 (because of membars in
7275 //  inline_unsafe_load_store).
7276 //
7277 // Add this node again if we found a good solution for inline_unsafe_load_store().
7278 // Don't forget to look at the implementation of post_store_load_barrier again,
7279 // we did other fixes in that method.
7280 //instruct unnecessary_membar_volatile() %{
7281 //  match(MemBarVolatile);
7282 //  predicate(Matcher::post_store_load_barrier(n));
7283 //  ins_cost(0);
7284 //
7285 //  format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7286 //  size(0);
7287 //  ins_encode( /*empty*/ );
7288 //  ins_pipe(pipe_class_default);
7289 //%}
7290 
7291 instruct membar_CPUOrder() %{
7292   match(MemBarCPUOrder);
7293   ins_cost(0);
7294 
7295   format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7296   size(0);
7297   ins_encode( /*empty*/ );
7298   ins_pipe(pipe_class_default);
7299 %}
7300 
7301 //----------Conditional Move---------------------------------------------------
7302 
7303 // Cmove using isel.
7304 instruct cmovI_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7305   match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7306   predicate(VM_Version::has_isel());
7307   ins_cost(DEFAULT_COST);
7308 
7309   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7310   size(4);
7311   ins_encode %{
7312     // This is a Power7 instruction for which no machine description
7313     // exists. Anyways, the scheduler should be off on Power7.
7314     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7315     int cc        = $cmp$$cmpcode;
7316     __ isel($dst$$Register, $crx$$CondRegister,
7317             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7318   %}
7319   ins_pipe(pipe_class_default);
7320 %}
7321 
7322 instruct cmovI_reg(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7323   match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7324   predicate(!VM_Version::has_isel());
7325   ins_cost(DEFAULT_COST+BRANCH_COST);
7326 
7327   ins_variable_size_depending_on_alignment(true);
7328 
7329   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7330   // Worst case is branch + move + stop, no stop without scheduler
7331   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7332   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7333   ins_pipe(pipe_class_default);
7334 %}
7335 
7336 instruct cmovI_imm(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, immI16 src) %{
7337   match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7338   ins_cost(DEFAULT_COST+BRANCH_COST);
7339 
7340   ins_variable_size_depending_on_alignment(true);
7341 
7342   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7343   // Worst case is branch + move + stop, no stop without scheduler
7344   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7345   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7346   ins_pipe(pipe_class_default);
7347 %}
7348 
7349 // Cmove using isel.
7350 instruct cmovL_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7351   match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7352   predicate(VM_Version::has_isel());
7353   ins_cost(DEFAULT_COST);
7354 
7355   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7356   size(4);
7357   ins_encode %{
7358     // This is a Power7 instruction for which no machine description
7359     // exists. Anyways, the scheduler should be off on Power7.
7360     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7361     int cc        = $cmp$$cmpcode;
7362     __ isel($dst$$Register, $crx$$CondRegister,
7363             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7364   %}
7365   ins_pipe(pipe_class_default);
7366 %}
7367 
7368 instruct cmovL_reg(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7369   match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7370   predicate(!VM_Version::has_isel());
7371   ins_cost(DEFAULT_COST+BRANCH_COST);
7372 
7373   ins_variable_size_depending_on_alignment(true);
7374 
7375   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7376   // Worst case is branch + move + stop, no stop without scheduler.
7377   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7378   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7379   ins_pipe(pipe_class_default);
7380 %}
7381 
7382 instruct cmovL_imm(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, immL16 src) %{
7383   match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7384   ins_cost(DEFAULT_COST+BRANCH_COST);
7385 
7386   ins_variable_size_depending_on_alignment(true);
7387 
7388   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7389   // Worst case is branch + move + stop, no stop without scheduler.
7390   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7391   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7392   ins_pipe(pipe_class_default);
7393 %}
7394 
7395 // Cmove using isel.
7396 instruct cmovN_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7397   match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7398   predicate(VM_Version::has_isel());
7399   ins_cost(DEFAULT_COST);
7400 
7401   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7402   size(4);
7403   ins_encode %{
7404     // This is a Power7 instruction for which no machine description
7405     // exists. Anyways, the scheduler should be off on Power7.
7406     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7407     int cc        = $cmp$$cmpcode;
7408     __ isel($dst$$Register, $crx$$CondRegister,
7409             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7410   %}
7411   ins_pipe(pipe_class_default);
7412 %}
7413 
7414 // Conditional move for RegN. Only cmov(reg, reg).
7415 instruct cmovN_reg(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7416   match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7417   predicate(!VM_Version::has_isel());
7418   ins_cost(DEFAULT_COST+BRANCH_COST);
7419 
7420   ins_variable_size_depending_on_alignment(true);
7421 
7422   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7423   // Worst case is branch + move + stop, no stop without scheduler.
7424   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7425   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7426   ins_pipe(pipe_class_default);
7427 %}
7428 
7429 instruct cmovN_imm(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, immN_0 src) %{
7430   match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7431   ins_cost(DEFAULT_COST+BRANCH_COST);
7432 
7433   ins_variable_size_depending_on_alignment(true);
7434 
7435   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7436   // Worst case is branch + move + stop, no stop without scheduler.
7437   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7438   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7439   ins_pipe(pipe_class_default);
7440 %}
7441 
7442 // Cmove using isel.
7443 instruct cmovP_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegPsrc src) %{
7444   match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7445   predicate(VM_Version::has_isel());
7446   ins_cost(DEFAULT_COST);
7447 
7448   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7449   size(4);
7450   ins_encode %{
7451     // This is a Power7 instruction for which no machine description
7452     // exists. Anyways, the scheduler should be off on Power7.
7453     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7454     int cc        = $cmp$$cmpcode;
7455     __ isel($dst$$Register, $crx$$CondRegister,
7456             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7457   %}
7458   ins_pipe(pipe_class_default);
7459 %}
7460 
7461 instruct cmovP_reg(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegP_N2P src) %{
7462   match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7463   predicate(!VM_Version::has_isel());
7464   ins_cost(DEFAULT_COST+BRANCH_COST);
7465 
7466   ins_variable_size_depending_on_alignment(true);
7467 
7468   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7469   // Worst case is branch + move + stop, no stop without scheduler.
7470   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7471   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7472   ins_pipe(pipe_class_default);
7473 %}
7474 
7475 instruct cmovP_imm(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, immP_0 src) %{
7476   match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7477   ins_cost(DEFAULT_COST+BRANCH_COST);
7478 
7479   ins_variable_size_depending_on_alignment(true);
7480 
7481   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7482   // Worst case is branch + move + stop, no stop without scheduler.
7483   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7484   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7485   ins_pipe(pipe_class_default);
7486 %}
7487 
7488 instruct cmovF_reg(cmpOp cmp, flagsRegSrc crx, regF dst, regF src) %{
7489   match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7490   ins_cost(DEFAULT_COST+BRANCH_COST);
7491 
7492   ins_variable_size_depending_on_alignment(true);
7493 
7494   format %{ "CMOVEF  $cmp, $crx, $dst, $src\n\t" %}
7495   // Worst case is branch + move + stop, no stop without scheduler.
7496   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7497   ins_encode %{
7498     // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7499     Label done;
7500     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7501     // Branch if not (cmp crx).
7502     __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7503     __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7504     // TODO PPC port __ endgroup_if_needed(_size == 12);
7505     __ bind(done);
7506   %}
7507   ins_pipe(pipe_class_default);
7508 %}
7509 
7510 instruct cmovD_reg(cmpOp cmp, flagsRegSrc crx, regD dst, regD src) %{
7511   match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7512   ins_cost(DEFAULT_COST+BRANCH_COST);
7513 
7514   ins_variable_size_depending_on_alignment(true);
7515 
7516   format %{ "CMOVEF  $cmp, $crx, $dst, $src\n\t" %}
7517   // Worst case is branch + move + stop, no stop without scheduler.
7518   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7519   ins_encode %{
7520     // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7521     Label done;
7522     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7523     // Branch if not (cmp crx).
7524     __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7525     __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7526     // TODO PPC port __ endgroup_if_needed(_size == 12);
7527     __ bind(done);
7528   %}
7529   ins_pipe(pipe_class_default);
7530 %}
7531 
7532 //----------Conditional_store--------------------------------------------------
7533 // Conditional-store of the updated heap-top.
7534 // Used during allocation of the shared heap.
7535 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7536 
7537 // As compareAndSwapL, but return flag register instead of boolean value in
7538 // int register.
7539 // Used by sun/misc/AtomicLongCSImpl.java.
7540 // Mem_ptr must be a memory operand, else this node does not get
7541 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7542 // can be rematerialized which leads to errors.
7543 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal, flagsRegCR0 cr0) %{
7544   match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7545   effect(TEMP cr0);
7546   format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7547   ins_encode %{
7548     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7549     __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7550                 MacroAssembler::MemBarAcq, MacroAssembler::cmpxchgx_hint_atomic_update(),
7551                 noreg, NULL, true);
7552   %}
7553   ins_pipe(pipe_class_default);
7554 %}
7555 
7556 // As compareAndSwapP, but return flag register instead of boolean value in
7557 // int register.
7558 // This instruction is matched if UseTLAB is off.
7559 // Mem_ptr must be a memory operand, else this node does not get
7560 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7561 // can be rematerialized which leads to errors.
7562 instruct storePConditional_regP_regP_regP(flagsRegCR0 cr0, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7563   match(Set cr0 (StorePConditional mem_ptr (Binary oldVal newVal)));
7564   ins_cost(2*MEMORY_REF_COST);
7565 
7566   format %{ "STDCX_  if ($cr0 = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7567   ins_encode %{
7568     // TODO: PPC port $archOpcode(ppc64Opcode_stdcx_);
7569     __ stdcx_($newVal$$Register, $mem_ptr$$Register);
7570   %}
7571   ins_pipe(pipe_class_memory);
7572 %}
7573 
7574 // Implement LoadPLocked. Must be ordered against changes of the memory location
7575 // by storePConditional.
7576 // Don't know whether this is ever used.
7577 instruct loadPLocked(iRegPdst dst, memory mem) %{
7578   match(Set dst (LoadPLocked mem));
7579   ins_cost(2*MEMORY_REF_COST);
7580 
7581   format %{ "LDARX   $dst, $mem \t// loadPLocked\n\t" %}
7582   size(4);
7583   ins_encode %{
7584     // TODO: PPC port $archOpcode(ppc64Opcode_ldarx);
7585     __ ldarx($dst$$Register, $mem$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
7586   %}
7587   ins_pipe(pipe_class_memory);
7588 %}
7589 
7590 //----------Compare-And-Swap---------------------------------------------------
7591 
7592 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7593 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))"  cannot be
7594 // matched.
7595 
7596 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7597   match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7598   effect(TEMP cr0);
7599   format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7600   // Variable size: instruction count smaller if regs are disjoint.
7601   ins_encode %{
7602     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7603     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7604     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7605                 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7606                 $res$$Register, true);
7607   %}
7608   ins_pipe(pipe_class_default);
7609 %}
7610 
7611 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
7612   match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7613   effect(TEMP cr0);
7614   format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7615   // Variable size: instruction count smaller if regs are disjoint.
7616   ins_encode %{
7617     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7618     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7619     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7620                 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7621                 $res$$Register, true);
7622   %}
7623   ins_pipe(pipe_class_default);
7624 %}
7625 
7626 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
7627   match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7628   effect(TEMP cr0);
7629   format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7630   // Variable size: instruction count smaller if regs are disjoint.
7631   ins_encode %{
7632     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7633     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7634     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7635                 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7636                 $res$$Register, NULL, true);
7637   %}
7638   ins_pipe(pipe_class_default);
7639 %}
7640 
7641 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
7642   match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7643   effect(TEMP cr0);
7644   format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7645   // Variable size: instruction count smaller if regs are disjoint.
7646   ins_encode %{
7647     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7648     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7649     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7650                 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7651                 $res$$Register, NULL, true);
7652   %}
7653   ins_pipe(pipe_class_default);
7654 %}
7655 
7656 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7657   match(Set res (GetAndAddI mem_ptr src));
7658   effect(TEMP cr0);
7659   format %{ "GetAndAddI $res, $mem_ptr, $src" %}
7660   // Variable size: instruction count smaller if regs are disjoint.
7661   ins_encode( enc_GetAndAddI(res, mem_ptr, src) );
7662   ins_pipe(pipe_class_default);
7663 %}
7664 
7665 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
7666   match(Set res (GetAndAddL mem_ptr src));
7667   effect(TEMP cr0);
7668   format %{ "GetAndAddL $res, $mem_ptr, $src" %}
7669   // Variable size: instruction count smaller if regs are disjoint.
7670   ins_encode( enc_GetAndAddL(res, mem_ptr, src) );
7671   ins_pipe(pipe_class_default);
7672 %}
7673 
7674 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7675   match(Set res (GetAndSetI mem_ptr src));
7676   effect(TEMP cr0);
7677   format %{ "GetAndSetI $res, $mem_ptr, $src" %}
7678   // Variable size: instruction count smaller if regs are disjoint.
7679   ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7680   ins_pipe(pipe_class_default);
7681 %}
7682 
7683 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
7684   match(Set res (GetAndSetL mem_ptr src));
7685   effect(TEMP cr0);
7686   format %{ "GetAndSetL $res, $mem_ptr, $src" %}
7687   // Variable size: instruction count smaller if regs are disjoint.
7688   ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7689   ins_pipe(pipe_class_default);
7690 %}
7691 
7692 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src, flagsRegCR0 cr0) %{
7693   match(Set res (GetAndSetP mem_ptr src));
7694   effect(TEMP cr0);
7695   format %{ "GetAndSetP $res, $mem_ptr, $src" %}
7696   // Variable size: instruction count smaller if regs are disjoint.
7697   ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7698   ins_pipe(pipe_class_default);
7699 %}
7700 
7701 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src, flagsRegCR0 cr0) %{
7702   match(Set res (GetAndSetN mem_ptr src));
7703   effect(TEMP cr0);
7704   format %{ "GetAndSetN $res, $mem_ptr, $src" %}
7705   // Variable size: instruction count smaller if regs are disjoint.
7706   ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7707   ins_pipe(pipe_class_default);
7708 %}
7709 
7710 //----------Arithmetic Instructions--------------------------------------------
7711 // Addition Instructions
7712 
7713 // Register Addition
7714 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7715   match(Set dst (AddI src1 src2));
7716   format %{ "ADD     $dst, $src1, $src2" %}
7717   size(4);
7718   ins_encode %{
7719     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7720     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7721   %}
7722   ins_pipe(pipe_class_default);
7723 %}
7724 
7725 // Expand does not work with above instruct. (??)
7726 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7727   // no match-rule
7728   effect(DEF dst, USE src1, USE src2);
7729   format %{ "ADD     $dst, $src1, $src2" %}
7730   size(4);
7731   ins_encode %{
7732     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7733     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7734   %}
7735   ins_pipe(pipe_class_default);
7736 %}
7737 
7738 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
7739   match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
7740   ins_cost(DEFAULT_COST*3);
7741 
7742   expand %{
7743     // FIXME: we should do this in the ideal world.
7744     iRegIdst tmp1;
7745     iRegIdst tmp2;
7746     addI_reg_reg(tmp1, src1, src2);
7747     addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
7748     addI_reg_reg(dst, tmp1, tmp2);
7749   %}
7750 %}
7751 
7752 // Immediate Addition
7753 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7754   match(Set dst (AddI src1 src2));
7755   format %{ "ADDI    $dst, $src1, $src2" %}
7756   size(4);
7757   ins_encode %{
7758     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7759     __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7760   %}
7761   ins_pipe(pipe_class_default);
7762 %}
7763 
7764 // Immediate Addition with 16-bit shifted operand
7765 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
7766   match(Set dst (AddI src1 src2));
7767   format %{ "ADDIS   $dst, $src1, $src2" %}
7768   size(4);
7769   ins_encode %{
7770     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7771     __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7772   %}
7773   ins_pipe(pipe_class_default);
7774 %}
7775 
7776 // Long Addition
7777 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7778   match(Set dst (AddL src1 src2));
7779   format %{ "ADD     $dst, $src1, $src2 \t// long" %}
7780   size(4);
7781   ins_encode %{
7782     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7783     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7784   %}
7785   ins_pipe(pipe_class_default);
7786 %}
7787 
7788 // Expand does not work with above instruct. (??)
7789 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7790   // no match-rule
7791   effect(DEF dst, USE src1, USE src2);
7792   format %{ "ADD     $dst, $src1, $src2 \t// long" %}
7793   size(4);
7794   ins_encode %{
7795     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7796     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7797   %}
7798   ins_pipe(pipe_class_default);
7799 %}
7800 
7801 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
7802   match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
7803   ins_cost(DEFAULT_COST*3);
7804 
7805   expand %{
7806     // FIXME: we should do this in the ideal world.
7807     iRegLdst tmp1;
7808     iRegLdst tmp2;
7809     addL_reg_reg(tmp1, src1, src2);
7810     addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
7811     addL_reg_reg(dst, tmp1, tmp2);
7812   %}
7813 %}
7814 
7815 // AddL + ConvL2I.
7816 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7817   match(Set dst (ConvL2I (AddL src1 src2)));
7818 
7819   format %{ "ADD     $dst, $src1, $src2 \t// long + l2i" %}
7820   size(4);
7821   ins_encode %{
7822     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7823     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7824   %}
7825   ins_pipe(pipe_class_default);
7826 %}
7827 
7828 // No constant pool entries required.
7829 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7830   match(Set dst (AddL src1 src2));
7831 
7832   format %{ "ADDI    $dst, $src1, $src2" %}
7833   size(4);
7834   ins_encode %{
7835     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7836     __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7837   %}
7838   ins_pipe(pipe_class_default);
7839 %}
7840 
7841 // Long Immediate Addition with 16-bit shifted operand.
7842 // No constant pool entries required.
7843 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
7844   match(Set dst (AddL src1 src2));
7845 
7846   format %{ "ADDIS   $dst, $src1, $src2" %}
7847   size(4);
7848   ins_encode %{
7849     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7850     __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7851   %}
7852   ins_pipe(pipe_class_default);
7853 %}
7854 
7855 // Pointer Register Addition
7856 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
7857   match(Set dst (AddP src1 src2));
7858   format %{ "ADD     $dst, $src1, $src2" %}
7859   size(4);
7860   ins_encode %{
7861     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7862     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7863   %}
7864   ins_pipe(pipe_class_default);
7865 %}
7866 
7867 // Pointer Immediate Addition
7868 // No constant pool entries required.
7869 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
7870   match(Set dst (AddP src1 src2));
7871 
7872   format %{ "ADDI    $dst, $src1, $src2" %}
7873   size(4);
7874   ins_encode %{
7875     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7876     __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7877   %}
7878   ins_pipe(pipe_class_default);
7879 %}
7880 
7881 // Pointer Immediate Addition with 16-bit shifted operand.
7882 // No constant pool entries required.
7883 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
7884   match(Set dst (AddP src1 src2));
7885 
7886   format %{ "ADDIS   $dst, $src1, $src2" %}
7887   size(4);
7888   ins_encode %{
7889     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7890     __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7891   %}
7892   ins_pipe(pipe_class_default);
7893 %}
7894 
7895 //---------------------
7896 // Subtraction Instructions
7897 
7898 // Register Subtraction
7899 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7900   match(Set dst (SubI src1 src2));
7901   format %{ "SUBF    $dst, $src2, $src1" %}
7902   size(4);
7903   ins_encode %{
7904     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7905     __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7906   %}
7907   ins_pipe(pipe_class_default);
7908 %}
7909 
7910 // Immediate Subtraction
7911 // Immediate Subtraction: The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
7912 // Don't try to use addi with - $src2$$constant since it can overflow when $src2$$constant == minI16.
7913 
7914 // SubI from constant (using subfic).
7915 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
7916   match(Set dst (SubI src1 src2));
7917   format %{ "SUBI    $dst, $src1, $src2" %}
7918 
7919   size(4);
7920   ins_encode %{
7921     // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
7922     __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
7923   %}
7924   ins_pipe(pipe_class_default);
7925 %}
7926 
7927 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
7928 // positive integers and 0xF...F for negative ones.
7929 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
7930   // no match-rule, false predicate
7931   effect(DEF dst, USE src);
7932   predicate(false);
7933 
7934   format %{ "SRAWI   $dst, $src, #31" %}
7935   size(4);
7936   ins_encode %{
7937     // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
7938     __ srawi($dst$$Register, $src$$Register, 0x1f);
7939   %}
7940   ins_pipe(pipe_class_default);
7941 %}
7942 
7943 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
7944   match(Set dst (AbsI src));
7945   ins_cost(DEFAULT_COST*3);
7946 
7947   expand %{
7948     iRegIdst tmp1;
7949     iRegIdst tmp2;
7950     signmask32I_regI(tmp1, src);
7951     xorI_reg_reg(tmp2, tmp1, src);
7952     subI_reg_reg(dst, tmp2, tmp1);
7953   %}
7954 %}
7955 
7956 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
7957   match(Set dst (SubI zero src2));
7958   format %{ "NEG     $dst, $src2" %}
7959   size(4);
7960   ins_encode %{
7961     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7962     __ neg($dst$$Register, $src2$$Register);
7963   %}
7964   ins_pipe(pipe_class_default);
7965 %}
7966 
7967 // Long subtraction
7968 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7969   match(Set dst (SubL src1 src2));
7970   format %{ "SUBF    $dst, $src2, $src1 \t// long" %}
7971   size(4);
7972   ins_encode %{
7973     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7974     __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7975   %}
7976   ins_pipe(pipe_class_default);
7977 %}
7978 
7979 // SubL + convL2I.
7980 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7981   match(Set dst (ConvL2I (SubL src1 src2)));
7982 
7983   format %{ "SUBF    $dst, $src2, $src1 \t// long + l2i" %}
7984   size(4);
7985   ins_encode %{
7986     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7987     __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7988   %}
7989   ins_pipe(pipe_class_default);
7990 %}
7991 
7992 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7993 // positive longs and 0xF...F for negative ones.
7994 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{
7995   // no match-rule, false predicate
7996   effect(DEF dst, USE src);
7997   predicate(false);
7998 
7999   format %{ "SRADI   $dst, $src, #63" %}
8000   size(4);
8001   ins_encode %{
8002     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8003     __ sradi($dst$$Register, $src$$Register, 0x3f);
8004   %}
8005   ins_pipe(pipe_class_default);
8006 %}
8007 
8008 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
8009 // positive longs and 0xF...F for negative ones.
8010 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{
8011   // no match-rule, false predicate
8012   effect(DEF dst, USE src);
8013   predicate(false);
8014 
8015   format %{ "SRADI   $dst, $src, #63" %}
8016   size(4);
8017   ins_encode %{
8018     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8019     __ sradi($dst$$Register, $src$$Register, 0x3f);
8020   %}
8021   ins_pipe(pipe_class_default);
8022 %}
8023 
8024 // Long negation
8025 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
8026   match(Set dst (SubL zero src2));
8027   format %{ "NEG     $dst, $src2 \t// long" %}
8028   size(4);
8029   ins_encode %{
8030     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8031     __ neg($dst$$Register, $src2$$Register);
8032   %}
8033   ins_pipe(pipe_class_default);
8034 %}
8035 
8036 // NegL + ConvL2I.
8037 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
8038   match(Set dst (ConvL2I (SubL zero src2)));
8039 
8040   format %{ "NEG     $dst, $src2 \t// long + l2i" %}
8041   size(4);
8042   ins_encode %{
8043     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8044     __ neg($dst$$Register, $src2$$Register);
8045   %}
8046   ins_pipe(pipe_class_default);
8047 %}
8048 
8049 // Multiplication Instructions
8050 // Integer Multiplication
8051 
8052 // Register Multiplication
8053 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8054   match(Set dst (MulI src1 src2));
8055   ins_cost(DEFAULT_COST);
8056 
8057   format %{ "MULLW   $dst, $src1, $src2" %}
8058   size(4);
8059   ins_encode %{
8060     // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
8061     __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
8062   %}
8063   ins_pipe(pipe_class_default);
8064 %}
8065 
8066 // Immediate Multiplication
8067 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
8068   match(Set dst (MulI src1 src2));
8069   ins_cost(DEFAULT_COST);
8070 
8071   format %{ "MULLI   $dst, $src1, $src2" %}
8072   size(4);
8073   ins_encode %{
8074     // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8075     __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8076   %}
8077   ins_pipe(pipe_class_default);
8078 %}
8079 
8080 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8081   match(Set dst (MulL src1 src2));
8082   ins_cost(DEFAULT_COST);
8083 
8084   format %{ "MULLD   $dst $src1, $src2 \t// long" %}
8085   size(4);
8086   ins_encode %{
8087     // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
8088     __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
8089   %}
8090   ins_pipe(pipe_class_default);
8091 %}
8092 
8093 // Multiply high for optimized long division by constant.
8094 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8095   match(Set dst (MulHiL src1 src2));
8096   ins_cost(DEFAULT_COST);
8097 
8098   format %{ "MULHD   $dst $src1, $src2 \t// long" %}
8099   size(4);
8100   ins_encode %{
8101     // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
8102     __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
8103   %}
8104   ins_pipe(pipe_class_default);
8105 %}
8106 
8107 // Immediate Multiplication
8108 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8109   match(Set dst (MulL src1 src2));
8110   ins_cost(DEFAULT_COST);
8111 
8112   format %{ "MULLI   $dst, $src1, $src2" %}
8113   size(4);
8114   ins_encode %{
8115     // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8116     __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8117   %}
8118   ins_pipe(pipe_class_default);
8119 %}
8120 
8121 // Integer Division with Immediate -1: Negate.
8122 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8123   match(Set dst (DivI src1 src2));
8124   ins_cost(DEFAULT_COST);
8125 
8126   format %{ "NEG     $dst, $src1 \t// /-1" %}
8127   size(4);
8128   ins_encode %{
8129     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8130     __ neg($dst$$Register, $src1$$Register);
8131   %}
8132   ins_pipe(pipe_class_default);
8133 %}
8134 
8135 // Integer Division with constant, but not -1.
8136 // We should be able to improve this by checking the type of src2.
8137 // It might well be that src2 is known to be positive.
8138 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8139   match(Set dst (DivI src1 src2));
8140   predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8141   ins_cost(2*DEFAULT_COST);
8142 
8143   format %{ "DIVW    $dst, $src1, $src2 \t// /not-1" %}
8144   size(4);
8145   ins_encode %{
8146     // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8147     __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8148   %}
8149   ins_pipe(pipe_class_default);
8150 %}
8151 
8152 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src1) %{
8153   effect(USE_DEF dst, USE src1, USE crx);
8154   predicate(false);
8155 
8156   ins_variable_size_depending_on_alignment(true);
8157 
8158   format %{ "CMOVE   $dst, neg($src1), $crx" %}
8159   // Worst case is branch + move + stop, no stop without scheduler.
8160   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8161   ins_encode %{
8162     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8163     Label done;
8164     __ bne($crx$$CondRegister, done);
8165     __ neg($dst$$Register, $src1$$Register);
8166     // TODO PPC port __ endgroup_if_needed(_size == 12);
8167     __ bind(done);
8168   %}
8169   ins_pipe(pipe_class_default);
8170 %}
8171 
8172 // Integer Division with Registers not containing constants.
8173 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8174   match(Set dst (DivI src1 src2));
8175   ins_cost(10*DEFAULT_COST);
8176 
8177   expand %{
8178     immI16 imm %{ (int)-1 %}
8179     flagsReg tmp1;
8180     cmpI_reg_imm16(tmp1, src2, imm);          // check src2 == -1
8181     divI_reg_regnotMinus1(dst, src1, src2);   // dst = src1 / src2
8182     cmovI_bne_negI_reg(dst, tmp1, src1);      // cmove dst = neg(src1) if src2 == -1
8183   %}
8184 %}
8185 
8186 // Long Division with Immediate -1: Negate.
8187 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8188   match(Set dst (DivL src1 src2));
8189   ins_cost(DEFAULT_COST);
8190 
8191   format %{ "NEG     $dst, $src1 \t// /-1, long" %}
8192   size(4);
8193   ins_encode %{
8194     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8195     __ neg($dst$$Register, $src1$$Register);
8196   %}
8197   ins_pipe(pipe_class_default);
8198 %}
8199 
8200 // Long Division with constant, but not -1.
8201 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8202   match(Set dst (DivL src1 src2));
8203   predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8204   ins_cost(2*DEFAULT_COST);
8205 
8206   format %{ "DIVD    $dst, $src1, $src2 \t// /not-1, long" %}
8207   size(4);
8208   ins_encode %{
8209     // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8210     __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8211   %}
8212   ins_pipe(pipe_class_default);
8213 %}
8214 
8215 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsRegSrc crx, iRegLsrc src1) %{
8216   effect(USE_DEF dst, USE src1, USE crx);
8217   predicate(false);
8218 
8219   ins_variable_size_depending_on_alignment(true);
8220 
8221   format %{ "CMOVE   $dst, neg($src1), $crx" %}
8222   // Worst case is branch + move + stop, no stop without scheduler.
8223   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8224   ins_encode %{
8225     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8226     Label done;
8227     __ bne($crx$$CondRegister, done);
8228     __ neg($dst$$Register, $src1$$Register);
8229     // TODO PPC port __ endgroup_if_needed(_size == 12);
8230     __ bind(done);
8231   %}
8232   ins_pipe(pipe_class_default);
8233 %}
8234 
8235 // Long Division with Registers not containing constants.
8236 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8237   match(Set dst (DivL src1 src2));
8238   ins_cost(10*DEFAULT_COST);
8239 
8240   expand %{
8241     immL16 imm %{ (int)-1 %}
8242     flagsReg tmp1;
8243     cmpL_reg_imm16(tmp1, src2, imm);          // check src2 == -1
8244     divL_reg_regnotMinus1(dst, src1, src2);   // dst = src1 / src2
8245     cmovL_bne_negL_reg(dst, tmp1, src1);      // cmove dst = neg(src1) if src2 == -1
8246   %}
8247 %}
8248 
8249 // Integer Remainder with registers.
8250 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8251   match(Set dst (ModI src1 src2));
8252   ins_cost(10*DEFAULT_COST);
8253 
8254   expand %{
8255     immI16 imm %{ (int)-1 %}
8256     flagsReg tmp1;
8257     iRegIdst tmp2;
8258     iRegIdst tmp3;
8259     cmpI_reg_imm16(tmp1, src2, imm);           // check src2 == -1
8260     divI_reg_regnotMinus1(tmp2, src1, src2);   // tmp2 = src1 / src2
8261     cmovI_bne_negI_reg(tmp2, tmp1, src1);      // cmove tmp2 = neg(src1) if src2 == -1
8262     mulI_reg_reg(tmp3, src2, tmp2);            // tmp3 = src2 * tmp2
8263     subI_reg_reg(dst, src1, tmp3);             // dst = src1 - tmp3
8264   %}
8265 %}
8266 
8267 // Long Remainder with registers
8268 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8269   match(Set dst (ModL src1 src2));
8270   ins_cost(10*DEFAULT_COST);
8271 
8272   expand %{
8273     immL16 imm %{ (int)-1 %}
8274     flagsReg tmp1;
8275     iRegLdst tmp2;
8276     iRegLdst tmp3;
8277     cmpL_reg_imm16(tmp1, src2, imm);             // check src2 == -1
8278     divL_reg_regnotMinus1(tmp2, src1, src2);     // tmp2 = src1 / src2
8279     cmovL_bne_negL_reg(tmp2, tmp1, src1);        // cmove tmp2 = neg(src1) if src2 == -1
8280     mulL_reg_reg(tmp3, src2, tmp2);              // tmp3 = src2 * tmp2
8281     subL_reg_reg(dst, src1, tmp3);               // dst = src1 - tmp3
8282   %}
8283 %}
8284 
8285 // Integer Shift Instructions
8286 
8287 // Register Shift Left
8288 
8289 // Clear all but the lowest #mask bits.
8290 // Used to normalize shift amounts in registers.
8291 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8292   // no match-rule, false predicate
8293   effect(DEF dst, USE src, USE mask);
8294   predicate(false);
8295 
8296   format %{ "MASK    $dst, $src, $mask \t// clear $mask upper bits" %}
8297   size(4);
8298   ins_encode %{
8299     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8300     __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8301   %}
8302   ins_pipe(pipe_class_default);
8303 %}
8304 
8305 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8306   // no match-rule, false predicate
8307   effect(DEF dst, USE src1, USE src2);
8308   predicate(false);
8309 
8310   format %{ "SLW     $dst, $src1, $src2" %}
8311   size(4);
8312   ins_encode %{
8313     // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8314     __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8315   %}
8316   ins_pipe(pipe_class_default);
8317 %}
8318 
8319 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8320   match(Set dst (LShiftI src1 src2));
8321   ins_cost(DEFAULT_COST*2);
8322   expand %{
8323     uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8324     iRegIdst tmpI;
8325     maskI_reg_imm(tmpI, src2, mask);
8326     lShiftI_reg_reg(dst, src1, tmpI);
8327   %}
8328 %}
8329 
8330 // Register Shift Left Immediate
8331 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8332   match(Set dst (LShiftI src1 src2));
8333 
8334   format %{ "SLWI    $dst, $src1, ($src2 & 0x1f)" %}
8335   size(4);
8336   ins_encode %{
8337     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8338     __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8339   %}
8340   ins_pipe(pipe_class_default);
8341 %}
8342 
8343 // AndI with negpow2-constant + LShiftI
8344 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8345   match(Set dst (LShiftI (AndI src1 src2) src3));
8346   predicate(UseRotateAndMaskInstructionsPPC64);
8347 
8348   format %{ "RLWINM  $dst, lShiftI(AndI($src1, $src2), $src3)" %}
8349   size(4);
8350   ins_encode %{
8351     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8352     long src2      = $src2$$constant;
8353     long src3      = $src3$$constant;
8354     long maskbits  = src3 + log2_long((jlong) (julong) (juint) -src2);
8355     if (maskbits >= 32) {
8356       __ li($dst$$Register, 0); // addi
8357     } else {
8358       __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
8359     }
8360   %}
8361   ins_pipe(pipe_class_default);
8362 %}
8363 
8364 // RShiftI + AndI with negpow2-constant + LShiftI
8365 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8366   match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
8367   predicate(UseRotateAndMaskInstructionsPPC64);
8368 
8369   format %{ "RLWINM  $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
8370   size(4);
8371   ins_encode %{
8372     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8373     long src2      = $src2$$constant;
8374     long src3      = $src3$$constant;
8375     long maskbits  = src3 + log2_long((jlong) (julong) (juint) -src2);
8376     if (maskbits >= 32) {
8377       __ li($dst$$Register, 0); // addi
8378     } else {
8379       __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
8380     }
8381   %}
8382   ins_pipe(pipe_class_default);
8383 %}
8384 
8385 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8386   // no match-rule, false predicate
8387   effect(DEF dst, USE src1, USE src2);
8388   predicate(false);
8389 
8390   format %{ "SLD     $dst, $src1, $src2" %}
8391   size(4);
8392   ins_encode %{
8393     // TODO: PPC port $archOpcode(ppc64Opcode_sld);
8394     __ sld($dst$$Register, $src1$$Register, $src2$$Register);
8395   %}
8396   ins_pipe(pipe_class_default);
8397 %}
8398 
8399 // Register Shift Left
8400 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8401   match(Set dst (LShiftL src1 src2));
8402   ins_cost(DEFAULT_COST*2);
8403   expand %{
8404     uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8405     iRegIdst tmpI;
8406     maskI_reg_imm(tmpI, src2, mask);
8407     lShiftL_regL_regI(dst, src1, tmpI);
8408   %}
8409 %}
8410 
8411 // Register Shift Left Immediate
8412 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8413   match(Set dst (LShiftL src1 src2));
8414   format %{ "SLDI    $dst, $src1, ($src2 & 0x3f)" %}
8415   size(4);
8416   ins_encode %{
8417     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8418     __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8419   %}
8420   ins_pipe(pipe_class_default);
8421 %}
8422 
8423 // If we shift more than 32 bits, we need not convert I2L.
8424 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
8425   match(Set dst (LShiftL (ConvI2L src1) src2));
8426   ins_cost(DEFAULT_COST);
8427 
8428   size(4);
8429   format %{ "SLDI    $dst, i2l($src1), $src2" %}
8430   ins_encode %{
8431     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8432     __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8433   %}
8434   ins_pipe(pipe_class_default);
8435 %}
8436 
8437 // Shift a postivie int to the left.
8438 // Clrlsldi clears the upper 32 bits and shifts.
8439 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
8440   match(Set dst (LShiftL (ConvI2L src1) src2));
8441   predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
8442 
8443   format %{ "SLDI    $dst, i2l(positive_int($src1)), $src2" %}
8444   size(4);
8445   ins_encode %{
8446     // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
8447     __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
8448   %}
8449   ins_pipe(pipe_class_default);
8450 %}
8451 
8452 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8453   // no match-rule, false predicate
8454   effect(DEF dst, USE src1, USE src2);
8455   predicate(false);
8456 
8457   format %{ "SRAW    $dst, $src1, $src2" %}
8458   size(4);
8459   ins_encode %{
8460     // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
8461     __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
8462   %}
8463   ins_pipe(pipe_class_default);
8464 %}
8465 
8466 // Register Arithmetic Shift Right
8467 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8468   match(Set dst (RShiftI src1 src2));
8469   ins_cost(DEFAULT_COST*2);
8470   expand %{
8471     uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8472     iRegIdst tmpI;
8473     maskI_reg_imm(tmpI, src2, mask);
8474     arShiftI_reg_reg(dst, src1, tmpI);
8475   %}
8476 %}
8477 
8478 // Register Arithmetic Shift Right Immediate
8479 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8480   match(Set dst (RShiftI src1 src2));
8481 
8482   format %{ "SRAWI   $dst, $src1, ($src2 & 0x1f)" %}
8483   size(4);
8484   ins_encode %{
8485     // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8486     __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8487   %}
8488   ins_pipe(pipe_class_default);
8489 %}
8490 
8491 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8492   // no match-rule, false predicate
8493   effect(DEF dst, USE src1, USE src2);
8494   predicate(false);
8495 
8496   format %{ "SRAD    $dst, $src1, $src2" %}
8497   size(4);
8498   ins_encode %{
8499     // TODO: PPC port $archOpcode(ppc64Opcode_srad);
8500     __ srad($dst$$Register, $src1$$Register, $src2$$Register);
8501   %}
8502   ins_pipe(pipe_class_default);
8503 %}
8504 
8505 // Register Shift Right Arithmetic Long
8506 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8507   match(Set dst (RShiftL src1 src2));
8508   ins_cost(DEFAULT_COST*2);
8509 
8510   expand %{
8511     uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8512     iRegIdst tmpI;
8513     maskI_reg_imm(tmpI, src2, mask);
8514     arShiftL_regL_regI(dst, src1, tmpI);
8515   %}
8516 %}
8517 
8518 // Register Shift Right Immediate
8519 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8520   match(Set dst (RShiftL src1 src2));
8521 
8522   format %{ "SRADI   $dst, $src1, ($src2 & 0x3f)" %}
8523   size(4);
8524   ins_encode %{
8525     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8526     __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8527   %}
8528   ins_pipe(pipe_class_default);
8529 %}
8530 
8531 // RShiftL + ConvL2I
8532 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8533   match(Set dst (ConvL2I (RShiftL src1 src2)));
8534 
8535   format %{ "SRADI   $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8536   size(4);
8537   ins_encode %{
8538     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8539     __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8540   %}
8541   ins_pipe(pipe_class_default);
8542 %}
8543 
8544 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8545   // no match-rule, false predicate
8546   effect(DEF dst, USE src1, USE src2);
8547   predicate(false);
8548 
8549   format %{ "SRW     $dst, $src1, $src2" %}
8550   size(4);
8551   ins_encode %{
8552     // TODO: PPC port $archOpcode(ppc64Opcode_srw);
8553     __ srw($dst$$Register, $src1$$Register, $src2$$Register);
8554   %}
8555   ins_pipe(pipe_class_default);
8556 %}
8557 
8558 // Register Shift Right
8559 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8560   match(Set dst (URShiftI src1 src2));
8561   ins_cost(DEFAULT_COST*2);
8562 
8563   expand %{
8564     uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8565     iRegIdst tmpI;
8566     maskI_reg_imm(tmpI, src2, mask);
8567     urShiftI_reg_reg(dst, src1, tmpI);
8568   %}
8569 %}
8570 
8571 // Register Shift Right Immediate
8572 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8573   match(Set dst (URShiftI src1 src2));
8574 
8575   format %{ "SRWI    $dst, $src1, ($src2 & 0x1f)" %}
8576   size(4);
8577   ins_encode %{
8578     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8579     __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8580   %}
8581   ins_pipe(pipe_class_default);
8582 %}
8583 
8584 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8585   // no match-rule, false predicate
8586   effect(DEF dst, USE src1, USE src2);
8587   predicate(false);
8588 
8589   format %{ "SRD     $dst, $src1, $src2" %}
8590   size(4);
8591   ins_encode %{
8592     // TODO: PPC port $archOpcode(ppc64Opcode_srd);
8593     __ srd($dst$$Register, $src1$$Register, $src2$$Register);
8594   %}
8595   ins_pipe(pipe_class_default);
8596 %}
8597 
8598 // Register Shift Right
8599 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8600   match(Set dst (URShiftL src1 src2));
8601   ins_cost(DEFAULT_COST*2);
8602 
8603   expand %{
8604     uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8605     iRegIdst tmpI;
8606     maskI_reg_imm(tmpI, src2, mask);
8607     urShiftL_regL_regI(dst, src1, tmpI);
8608   %}
8609 %}
8610 
8611 // Register Shift Right Immediate
8612 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8613   match(Set dst (URShiftL src1 src2));
8614 
8615   format %{ "SRDI    $dst, $src1, ($src2 & 0x3f)" %}
8616   size(4);
8617   ins_encode %{
8618     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8619     __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8620   %}
8621   ins_pipe(pipe_class_default);
8622 %}
8623 
8624 // URShiftL + ConvL2I.
8625 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8626   match(Set dst (ConvL2I (URShiftL src1 src2)));
8627 
8628   format %{ "SRDI    $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8629   size(4);
8630   ins_encode %{
8631     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8632     __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8633   %}
8634   ins_pipe(pipe_class_default);
8635 %}
8636 
8637 // Register Shift Right Immediate with a CastP2X
8638 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
8639   match(Set dst (URShiftL (CastP2X src1) src2));
8640 
8641   format %{ "SRDI    $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8642   size(4);
8643   ins_encode %{
8644     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8645     __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8646   %}
8647   ins_pipe(pipe_class_default);
8648 %}
8649 
8650 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
8651   match(Set dst (ConvL2I (ConvI2L src)));
8652 
8653   format %{ "EXTSW   $dst, $src \t// int->int" %}
8654   size(4);
8655   ins_encode %{
8656     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
8657     __ extsw($dst$$Register, $src$$Register);
8658   %}
8659   ins_pipe(pipe_class_default);
8660 %}
8661 
8662 //----------Rotate Instructions------------------------------------------------
8663 
8664 // Rotate Left by 8-bit immediate
8665 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
8666   match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
8667   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8668 
8669   format %{ "ROTLWI  $dst, $src, $lshift" %}
8670   size(4);
8671   ins_encode %{
8672     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8673     __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
8674   %}
8675   ins_pipe(pipe_class_default);
8676 %}
8677 
8678 // Rotate Right by 8-bit immediate
8679 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
8680   match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
8681   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8682 
8683   format %{ "ROTRWI  $dst, $rshift" %}
8684   size(4);
8685   ins_encode %{
8686     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8687     __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
8688   %}
8689   ins_pipe(pipe_class_default);
8690 %}
8691 
8692 //----------Floating Point Arithmetic Instructions-----------------------------
8693 
8694 // Add float single precision
8695 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8696   match(Set dst (AddF src1 src2));
8697 
8698   format %{ "FADDS   $dst, $src1, $src2" %}
8699   size(4);
8700   ins_encode %{
8701     // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
8702     __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8703   %}
8704   ins_pipe(pipe_class_default);
8705 %}
8706 
8707 // Add float double precision
8708 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8709   match(Set dst (AddD src1 src2));
8710 
8711   format %{ "FADD    $dst, $src1, $src2" %}
8712   size(4);
8713   ins_encode %{
8714     // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
8715     __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8716   %}
8717   ins_pipe(pipe_class_default);
8718 %}
8719 
8720 // Sub float single precision
8721 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8722   match(Set dst (SubF src1 src2));
8723 
8724   format %{ "FSUBS   $dst, $src1, $src2" %}
8725   size(4);
8726   ins_encode %{
8727     // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
8728     __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8729   %}
8730   ins_pipe(pipe_class_default);
8731 %}
8732 
8733 // Sub float double precision
8734 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8735   match(Set dst (SubD src1 src2));
8736   format %{ "FSUB    $dst, $src1, $src2" %}
8737   size(4);
8738   ins_encode %{
8739     // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
8740     __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8741   %}
8742   ins_pipe(pipe_class_default);
8743 %}
8744 
8745 // Mul float single precision
8746 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8747   match(Set dst (MulF src1 src2));
8748   format %{ "FMULS   $dst, $src1, $src2" %}
8749   size(4);
8750   ins_encode %{
8751     // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
8752     __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8753   %}
8754   ins_pipe(pipe_class_default);
8755 %}
8756 
8757 // Mul float double precision
8758 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8759   match(Set dst (MulD src1 src2));
8760   format %{ "FMUL    $dst, $src1, $src2" %}
8761   size(4);
8762   ins_encode %{
8763     // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
8764     __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8765   %}
8766   ins_pipe(pipe_class_default);
8767 %}
8768 
8769 // Div float single precision
8770 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
8771   match(Set dst (DivF src1 src2));
8772   format %{ "FDIVS   $dst, $src1, $src2" %}
8773   size(4);
8774   ins_encode %{
8775     // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
8776     __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8777   %}
8778   ins_pipe(pipe_class_default);
8779 %}
8780 
8781 // Div float double precision
8782 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8783   match(Set dst (DivD src1 src2));
8784   format %{ "FDIV    $dst, $src1, $src2" %}
8785   size(4);
8786   ins_encode %{
8787     // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
8788     __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8789   %}
8790   ins_pipe(pipe_class_default);
8791 %}
8792 
8793 // Absolute float single precision
8794 instruct absF_reg(regF dst, regF src) %{
8795   match(Set dst (AbsF src));
8796   format %{ "FABS    $dst, $src \t// float" %}
8797   size(4);
8798   ins_encode %{
8799     // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8800     __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8801   %}
8802   ins_pipe(pipe_class_default);
8803 %}
8804 
8805 // Absolute float double precision
8806 instruct absD_reg(regD dst, regD src) %{
8807   match(Set dst (AbsD src));
8808   format %{ "FABS    $dst, $src \t// double" %}
8809   size(4);
8810   ins_encode %{
8811     // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8812     __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8813   %}
8814   ins_pipe(pipe_class_default);
8815 %}
8816 
8817 instruct negF_reg(regF dst, regF src) %{
8818   match(Set dst (NegF src));
8819   format %{ "FNEG    $dst, $src \t// float" %}
8820   size(4);
8821   ins_encode %{
8822     // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8823     __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8824   %}
8825   ins_pipe(pipe_class_default);
8826 %}
8827 
8828 instruct negD_reg(regD dst, regD src) %{
8829   match(Set dst (NegD src));
8830   format %{ "FNEG    $dst, $src \t// double" %}
8831   size(4);
8832   ins_encode %{
8833     // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8834     __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8835   %}
8836   ins_pipe(pipe_class_default);
8837 %}
8838 
8839 // AbsF + NegF.
8840 instruct negF_absF_reg(regF dst, regF src) %{
8841   match(Set dst (NegF (AbsF src)));
8842   format %{ "FNABS   $dst, $src \t// float" %}
8843   size(4);
8844   ins_encode %{
8845     // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8846     __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8847   %}
8848   ins_pipe(pipe_class_default);
8849 %}
8850 
8851 // AbsD + NegD.
8852 instruct negD_absD_reg(regD dst, regD src) %{
8853   match(Set dst (NegD (AbsD src)));
8854   format %{ "FNABS   $dst, $src \t// double" %}
8855   size(4);
8856   ins_encode %{
8857     // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8858     __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8859   %}
8860   ins_pipe(pipe_class_default);
8861 %}
8862 
8863 // VM_Version::has_fsqrt() decides if this node will be used.
8864 // Sqrt float double precision
8865 instruct sqrtD_reg(regD dst, regD src) %{
8866   match(Set dst (SqrtD src));
8867   format %{ "FSQRT   $dst, $src" %}
8868   size(4);
8869   ins_encode %{
8870     // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
8871     __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
8872   %}
8873   ins_pipe(pipe_class_default);
8874 %}
8875 
8876 // Single-precision sqrt.
8877 instruct sqrtF_reg(regF dst, regF src) %{
8878   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8879   predicate(VM_Version::has_fsqrts());
8880   ins_cost(DEFAULT_COST);
8881 
8882   format %{ "FSQRTS  $dst, $src" %}
8883   size(4);
8884   ins_encode %{
8885     // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
8886     __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
8887   %}
8888   ins_pipe(pipe_class_default);
8889 %}
8890 
8891 instruct roundDouble_nop(regD dst) %{
8892   match(Set dst (RoundDouble dst));
8893   ins_cost(0);
8894 
8895   format %{ " -- \t// RoundDouble not needed - empty" %}
8896   size(0);
8897   // PPC results are already "rounded" (i.e., normal-format IEEE).
8898   ins_encode( /*empty*/ );
8899   ins_pipe(pipe_class_default);
8900 %}
8901 
8902 instruct roundFloat_nop(regF dst) %{
8903   match(Set dst (RoundFloat dst));
8904   ins_cost(0);
8905 
8906   format %{ " -- \t// RoundFloat not needed - empty" %}
8907   size(0);
8908   // PPC results are already "rounded" (i.e., normal-format IEEE).
8909   ins_encode( /*empty*/ );
8910   ins_pipe(pipe_class_default);
8911 %}
8912 
8913 //----------Logical Instructions-----------------------------------------------
8914 
8915 // And Instructions
8916 
8917 // Register And
8918 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8919   match(Set dst (AndI src1 src2));
8920   format %{ "AND     $dst, $src1, $src2" %}
8921   size(4);
8922   ins_encode %{
8923     // TODO: PPC port $archOpcode(ppc64Opcode_and);
8924     __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8925   %}
8926   ins_pipe(pipe_class_default);
8927 %}
8928 
8929 // Immediate And
8930 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
8931   match(Set dst (AndI src1 src2));
8932   effect(KILL cr0);
8933 
8934   format %{ "ANDI    $dst, $src1, $src2" %}
8935   size(4);
8936   ins_encode %{
8937     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8938     // FIXME: avoid andi_ ?
8939     __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8940   %}
8941   ins_pipe(pipe_class_default);
8942 %}
8943 
8944 // Immediate And where the immediate is a negative power of 2.
8945 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
8946   match(Set dst (AndI src1 src2));
8947   format %{ "ANDWI   $dst, $src1, $src2" %}
8948   size(4);
8949   ins_encode %{
8950     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8951     __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
8952   %}
8953   ins_pipe(pipe_class_default);
8954 %}
8955 
8956 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
8957   match(Set dst (AndI src1 src2));
8958   format %{ "ANDWI   $dst, $src1, $src2" %}
8959   size(4);
8960   ins_encode %{
8961     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8962     __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8963   %}
8964   ins_pipe(pipe_class_default);
8965 %}
8966 
8967 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
8968   match(Set dst (AndI src1 src2));
8969   predicate(UseRotateAndMaskInstructionsPPC64);
8970   format %{ "ANDWI   $dst, $src1, $src2" %}
8971   size(4);
8972   ins_encode %{
8973     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8974     __ rlwinm($dst$$Register, $src1$$Register, 0,
8975               (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
8976   %}
8977   ins_pipe(pipe_class_default);
8978 %}
8979 
8980 // Register And Long
8981 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8982   match(Set dst (AndL src1 src2));
8983   ins_cost(DEFAULT_COST);
8984 
8985   format %{ "AND     $dst, $src1, $src2 \t// long" %}
8986   size(4);
8987   ins_encode %{
8988     // TODO: PPC port $archOpcode(ppc64Opcode_and);
8989     __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8990   %}
8991   ins_pipe(pipe_class_default);
8992 %}
8993 
8994 // Immediate And long
8995 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
8996   match(Set dst (AndL src1 src2));
8997   effect(KILL cr0);
8998 
8999   format %{ "ANDI    $dst, $src1, $src2 \t// long" %}
9000   size(4);
9001   ins_encode %{
9002     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
9003     // FIXME: avoid andi_ ?
9004     __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
9005   %}
9006   ins_pipe(pipe_class_default);
9007 %}
9008 
9009 // Immediate And Long where the immediate is a negative power of 2.
9010 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
9011   match(Set dst (AndL src1 src2));
9012   format %{ "ANDDI   $dst, $src1, $src2" %}
9013   size(4);
9014   ins_encode %{
9015     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
9016     __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
9017   %}
9018   ins_pipe(pipe_class_default);
9019 %}
9020 
9021 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
9022   match(Set dst (AndL src1 src2));
9023   format %{ "ANDDI   $dst, $src1, $src2" %}
9024   size(4);
9025   ins_encode %{
9026     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9027     __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9028   %}
9029   ins_pipe(pipe_class_default);
9030 %}
9031 
9032 // AndL + ConvL2I.
9033 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
9034   match(Set dst (ConvL2I (AndL src1 src2)));
9035   ins_cost(DEFAULT_COST);
9036 
9037   format %{ "ANDDI   $dst, $src1, $src2 \t// long + l2i" %}
9038   size(4);
9039   ins_encode %{
9040     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9041     __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9042   %}
9043   ins_pipe(pipe_class_default);
9044 %}
9045 
9046 // Or Instructions
9047 
9048 // Register Or
9049 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9050   match(Set dst (OrI src1 src2));
9051   format %{ "OR      $dst, $src1, $src2" %}
9052   size(4);
9053   ins_encode %{
9054     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9055     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9056   %}
9057   ins_pipe(pipe_class_default);
9058 %}
9059 
9060 // Expand does not work with above instruct. (??)
9061 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9062   // no match-rule
9063   effect(DEF dst, USE src1, USE src2);
9064   format %{ "OR      $dst, $src1, $src2" %}
9065   size(4);
9066   ins_encode %{
9067     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9068     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9069   %}
9070   ins_pipe(pipe_class_default);
9071 %}
9072 
9073 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9074   match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
9075   ins_cost(DEFAULT_COST*3);
9076 
9077   expand %{
9078     // FIXME: we should do this in the ideal world.
9079     iRegIdst tmp1;
9080     iRegIdst tmp2;
9081     orI_reg_reg(tmp1, src1, src2);
9082     orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
9083     orI_reg_reg(dst, tmp1, tmp2);
9084   %}
9085 %}
9086 
9087 // Immediate Or
9088 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9089   match(Set dst (OrI src1 src2));
9090   format %{ "ORI     $dst, $src1, $src2" %}
9091   size(4);
9092   ins_encode %{
9093     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9094     __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
9095   %}
9096   ins_pipe(pipe_class_default);
9097 %}
9098 
9099 // Register Or Long
9100 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9101   match(Set dst (OrL src1 src2));
9102   ins_cost(DEFAULT_COST);
9103 
9104   size(4);
9105   format %{ "OR      $dst, $src1, $src2 \t// long" %}
9106   ins_encode %{
9107     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9108     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9109   %}
9110   ins_pipe(pipe_class_default);
9111 %}
9112 
9113 // OrL + ConvL2I.
9114 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9115   match(Set dst (ConvL2I (OrL src1 src2)));
9116   ins_cost(DEFAULT_COST);
9117 
9118   format %{ "OR      $dst, $src1, $src2 \t// long + l2i" %}
9119   size(4);
9120   ins_encode %{
9121     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9122     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9123   %}
9124   ins_pipe(pipe_class_default);
9125 %}
9126 
9127 // Immediate Or long
9128 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9129   match(Set dst (OrL src1 con));
9130   ins_cost(DEFAULT_COST);
9131 
9132   format %{ "ORI     $dst, $src1, $con \t// long" %}
9133   size(4);
9134   ins_encode %{
9135     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9136     __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9137   %}
9138   ins_pipe(pipe_class_default);
9139 %}
9140 
9141 // Xor Instructions
9142 
9143 // Register Xor
9144 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9145   match(Set dst (XorI src1 src2));
9146   format %{ "XOR     $dst, $src1, $src2" %}
9147   size(4);
9148   ins_encode %{
9149     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9150     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9151   %}
9152   ins_pipe(pipe_class_default);
9153 %}
9154 
9155 // Expand does not work with above instruct. (??)
9156 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9157   // no match-rule
9158   effect(DEF dst, USE src1, USE src2);
9159   format %{ "XOR     $dst, $src1, $src2" %}
9160   size(4);
9161   ins_encode %{
9162     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9163     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9164   %}
9165   ins_pipe(pipe_class_default);
9166 %}
9167 
9168 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9169   match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9170   ins_cost(DEFAULT_COST*3);
9171 
9172   expand %{
9173     // FIXME: we should do this in the ideal world.
9174     iRegIdst tmp1;
9175     iRegIdst tmp2;
9176     xorI_reg_reg(tmp1, src1, src2);
9177     xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9178     xorI_reg_reg(dst, tmp1, tmp2);
9179   %}
9180 %}
9181 
9182 // Immediate Xor
9183 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9184   match(Set dst (XorI src1 src2));
9185   format %{ "XORI    $dst, $src1, $src2" %}
9186   size(4);
9187   ins_encode %{
9188     // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9189     __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9190   %}
9191   ins_pipe(pipe_class_default);
9192 %}
9193 
9194 // Register Xor Long
9195 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9196   match(Set dst (XorL src1 src2));
9197   ins_cost(DEFAULT_COST);
9198 
9199   format %{ "XOR     $dst, $src1, $src2 \t// long" %}
9200   size(4);
9201   ins_encode %{
9202     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9203     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9204   %}
9205   ins_pipe(pipe_class_default);
9206 %}
9207 
9208 // XorL + ConvL2I.
9209 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9210   match(Set dst (ConvL2I (XorL src1 src2)));
9211   ins_cost(DEFAULT_COST);
9212 
9213   format %{ "XOR     $dst, $src1, $src2 \t// long + l2i" %}
9214   size(4);
9215   ins_encode %{
9216     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9217     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9218   %}
9219   ins_pipe(pipe_class_default);
9220 %}
9221 
9222 // Immediate Xor Long
9223 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
9224   match(Set dst (XorL src1 src2));
9225   ins_cost(DEFAULT_COST);
9226 
9227   format %{ "XORI    $dst, $src1, $src2 \t// long" %}
9228   size(4);
9229   ins_encode %{
9230     // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9231     __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9232   %}
9233   ins_pipe(pipe_class_default);
9234 %}
9235 
9236 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9237   match(Set dst (XorI src1 src2));
9238   ins_cost(DEFAULT_COST);
9239 
9240   format %{ "NOT     $dst, $src1 ($src2)" %}
9241   size(4);
9242   ins_encode %{
9243     // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9244     __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9245   %}
9246   ins_pipe(pipe_class_default);
9247 %}
9248 
9249 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9250   match(Set dst (XorL src1 src2));
9251   ins_cost(DEFAULT_COST);
9252 
9253   format %{ "NOT     $dst, $src1 ($src2) \t// long" %}
9254   size(4);
9255   ins_encode %{
9256     // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9257     __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9258   %}
9259   ins_pipe(pipe_class_default);
9260 %}
9261 
9262 // And-complement
9263 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
9264   match(Set dst (AndI (XorI src1 src2) src3));
9265   ins_cost(DEFAULT_COST);
9266 
9267   format %{ "ANDW    $dst, xori($src1, $src2), $src3" %}
9268   size(4);
9269   ins_encode( enc_andc(dst, src3, src1) );
9270   ins_pipe(pipe_class_default);
9271 %}
9272 
9273 // And-complement
9274 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9275   // no match-rule, false predicate
9276   effect(DEF dst, USE src1, USE src2);
9277   predicate(false);
9278 
9279   format %{ "ANDC    $dst, $src1, $src2" %}
9280   size(4);
9281   ins_encode %{
9282     // TODO: PPC port $archOpcode(ppc64Opcode_andc);
9283     __ andc($dst$$Register, $src1$$Register, $src2$$Register);
9284   %}
9285   ins_pipe(pipe_class_default);
9286 %}
9287 
9288 //----------Moves between int/long and float/double----------------------------
9289 //
9290 // The following rules move values from int/long registers/stack-locations
9291 // to float/double registers/stack-locations and vice versa, without doing any
9292 // conversions. These rules are used to implement the bit-conversion methods
9293 // of java.lang.Float etc., e.g.
9294 //   int   floatToIntBits(float value)
9295 //   float intBitsToFloat(int bits)
9296 //
9297 // Notes on the implementation on ppc64:
9298 // We only provide rules which move between a register and a stack-location,
9299 // because we always have to go through memory when moving between a float
9300 // register and an integer register.
9301 
9302 //---------- Chain stack slots between similar types --------
9303 
9304 // These are needed so that the rules below can match.
9305 
9306 // Load integer from stack slot
9307 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
9308   match(Set dst src);
9309   ins_cost(MEMORY_REF_COST);
9310 
9311   format %{ "LWZ     $dst, $src" %}
9312   size(4);
9313   ins_encode( enc_lwz(dst, src) );
9314   ins_pipe(pipe_class_memory);
9315 %}
9316 
9317 // Store integer to stack slot
9318 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
9319   match(Set dst src);
9320   ins_cost(MEMORY_REF_COST);
9321 
9322   format %{ "STW     $src, $dst \t// stk" %}
9323   size(4);
9324   ins_encode( enc_stw(src, dst) ); // rs=rt
9325   ins_pipe(pipe_class_memory);
9326 %}
9327 
9328 // Load long from stack slot
9329 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
9330   match(Set dst src);
9331   ins_cost(MEMORY_REF_COST);
9332 
9333   format %{ "LD      $dst, $src \t// long" %}
9334   size(4);
9335   ins_encode( enc_ld(dst, src) );
9336   ins_pipe(pipe_class_memory);
9337 %}
9338 
9339 // Store long to stack slot
9340 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
9341   match(Set dst src);
9342   ins_cost(MEMORY_REF_COST);
9343 
9344   format %{ "STD     $src, $dst \t// long" %}
9345   size(4);
9346   ins_encode( enc_std(src, dst) ); // rs=rt
9347   ins_pipe(pipe_class_memory);
9348 %}
9349 
9350 //----------Moves between int and float
9351 
9352 // Move float value from float stack-location to integer register.
9353 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
9354   match(Set dst (MoveF2I src));
9355   ins_cost(MEMORY_REF_COST);
9356 
9357   format %{ "LWZ     $dst, $src \t// MoveF2I" %}
9358   size(4);
9359   ins_encode( enc_lwz(dst, src) );
9360   ins_pipe(pipe_class_memory);
9361 %}
9362 
9363 // Move float value from float register to integer stack-location.
9364 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
9365   match(Set dst (MoveF2I src));
9366   ins_cost(MEMORY_REF_COST);
9367 
9368   format %{ "STFS    $src, $dst \t// MoveF2I" %}
9369   size(4);
9370   ins_encode( enc_stfs(src, dst) );
9371   ins_pipe(pipe_class_memory);
9372 %}
9373 
9374 // Move integer value from integer stack-location to float register.
9375 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
9376   match(Set dst (MoveI2F src));
9377   ins_cost(MEMORY_REF_COST);
9378 
9379   format %{ "LFS     $dst, $src \t// MoveI2F" %}
9380   size(4);
9381   ins_encode %{
9382     // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
9383     int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
9384     __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
9385   %}
9386   ins_pipe(pipe_class_memory);
9387 %}
9388 
9389 // Move integer value from integer register to float stack-location.
9390 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
9391   match(Set dst (MoveI2F src));
9392   ins_cost(MEMORY_REF_COST);
9393 
9394   format %{ "STW     $src, $dst \t// MoveI2F" %}
9395   size(4);
9396   ins_encode( enc_stw(src, dst) );
9397   ins_pipe(pipe_class_memory);
9398 %}
9399 
9400 //----------Moves between long and float
9401 
9402 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
9403   // no match-rule, false predicate
9404   effect(DEF dst, USE src);
9405   predicate(false);
9406 
9407   format %{ "storeD  $src, $dst \t// STACK" %}
9408   size(4);
9409   ins_encode( enc_stfd(src, dst) );
9410   ins_pipe(pipe_class_default);
9411 %}
9412 
9413 //----------Moves between long and double
9414 
9415 // Move double value from double stack-location to long register.
9416 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
9417   match(Set dst (MoveD2L src));
9418   ins_cost(MEMORY_REF_COST);
9419   size(4);
9420   format %{ "LD      $dst, $src \t// MoveD2L" %}
9421   ins_encode( enc_ld(dst, src) );
9422   ins_pipe(pipe_class_memory);
9423 %}
9424 
9425 // Move double value from double register to long stack-location.
9426 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
9427   match(Set dst (MoveD2L src));
9428   effect(DEF dst, USE src);
9429   ins_cost(MEMORY_REF_COST);
9430 
9431   format %{ "STFD    $src, $dst \t// MoveD2L" %}
9432   size(4);
9433   ins_encode( enc_stfd(src, dst) );
9434   ins_pipe(pipe_class_memory);
9435 %}
9436 
9437 // Move long value from long stack-location to double register.
9438 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
9439   match(Set dst (MoveL2D src));
9440   ins_cost(MEMORY_REF_COST);
9441 
9442   format %{ "LFD     $dst, $src \t// MoveL2D" %}
9443   size(4);
9444   ins_encode( enc_lfd(dst, src) );
9445   ins_pipe(pipe_class_memory);
9446 %}
9447 
9448 // Move long value from long register to double stack-location.
9449 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
9450   match(Set dst (MoveL2D src));
9451   ins_cost(MEMORY_REF_COST);
9452 
9453   format %{ "STD     $src, $dst \t// MoveL2D" %}
9454   size(4);
9455   ins_encode( enc_std(src, dst) );
9456   ins_pipe(pipe_class_memory);
9457 %}
9458 
9459 //----------Register Move Instructions-----------------------------------------
9460 
9461 // Replicate for Superword
9462 
9463 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
9464   predicate(false);
9465   effect(DEF dst, USE src);
9466 
9467   format %{ "MR      $dst, $src \t// replicate " %}
9468   // variable size, 0 or 4.
9469   ins_encode %{
9470     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9471     __ mr_if_needed($dst$$Register, $src$$Register);
9472   %}
9473   ins_pipe(pipe_class_default);
9474 %}
9475 
9476 //----------Cast instructions (Java-level type cast)---------------------------
9477 
9478 // Cast Long to Pointer for unsafe natives.
9479 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
9480   match(Set dst (CastX2P src));
9481 
9482   format %{ "MR      $dst, $src \t// Long->Ptr" %}
9483   // variable size, 0 or 4.
9484   ins_encode %{
9485     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9486     __ mr_if_needed($dst$$Register, $src$$Register);
9487   %}
9488  ins_pipe(pipe_class_default);
9489 %}
9490 
9491 // Cast Pointer to Long for unsafe natives.
9492 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
9493   match(Set dst (CastP2X src));
9494 
9495   format %{ "MR      $dst, $src \t// Ptr->Long" %}
9496   // variable size, 0 or 4.
9497   ins_encode %{
9498     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9499     __ mr_if_needed($dst$$Register, $src$$Register);
9500   %}
9501   ins_pipe(pipe_class_default);
9502 %}
9503 
9504 instruct castPP(iRegPdst dst) %{
9505   match(Set dst (CastPP dst));
9506   format %{ " -- \t// castPP of $dst" %}
9507   size(0);
9508   ins_encode( /*empty*/ );
9509   ins_pipe(pipe_class_default);
9510 %}
9511 
9512 instruct castII(iRegIdst dst) %{
9513   match(Set dst (CastII dst));
9514   format %{ " -- \t// castII of $dst" %}
9515   size(0);
9516   ins_encode( /*empty*/ );
9517   ins_pipe(pipe_class_default);
9518 %}
9519 
9520 instruct checkCastPP(iRegPdst dst) %{
9521   match(Set dst (CheckCastPP dst));
9522   format %{ " -- \t// checkcastPP of $dst" %}
9523   size(0);
9524   ins_encode( /*empty*/ );
9525   ins_pipe(pipe_class_default);
9526 %}
9527 
9528 //----------Convert instructions-----------------------------------------------
9529 
9530 // Convert to boolean.
9531 
9532 // int_to_bool(src) : { 1   if src != 0
9533 //                    { 0   else
9534 //
9535 // strategy:
9536 // 1) Count leading zeros of 32 bit-value src,
9537 //    this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
9538 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9539 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9540 
9541 // convI2Bool
9542 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
9543   match(Set dst (Conv2B src));
9544   predicate(UseCountLeadingZerosInstructionsPPC64);
9545   ins_cost(DEFAULT_COST);
9546 
9547   expand %{
9548     immI shiftAmount %{ 0x5 %}
9549     uimmI16 mask %{ 0x1 %}
9550     iRegIdst tmp1;
9551     iRegIdst tmp2;
9552     countLeadingZerosI(tmp1, src);
9553     urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9554     xorI_reg_uimm16(dst, tmp2, mask);
9555   %}
9556 %}
9557 
9558 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
9559   match(Set dst (Conv2B src));
9560   effect(TEMP crx);
9561   predicate(!UseCountLeadingZerosInstructionsPPC64);
9562   ins_cost(DEFAULT_COST);
9563 
9564   format %{ "CMPWI   $crx, $src, #0 \t// convI2B"
9565             "LI      $dst, #0\n\t"
9566             "BEQ     $crx, done\n\t"
9567             "LI      $dst, #1\n"
9568             "done:" %}
9569   size(16);
9570   ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
9571   ins_pipe(pipe_class_compare);
9572 %}
9573 
9574 // ConvI2B + XorI
9575 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
9576   match(Set dst (XorI (Conv2B src) mask));
9577   predicate(UseCountLeadingZerosInstructionsPPC64);
9578   ins_cost(DEFAULT_COST);
9579 
9580   expand %{
9581     immI shiftAmount %{ 0x5 %}
9582     iRegIdst tmp1;
9583     countLeadingZerosI(tmp1, src);
9584     urShiftI_reg_imm(dst, tmp1, shiftAmount);
9585   %}
9586 %}
9587 
9588 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
9589   match(Set dst (XorI (Conv2B src) mask));
9590   effect(TEMP crx);
9591   predicate(!UseCountLeadingZerosInstructionsPPC64);
9592   ins_cost(DEFAULT_COST);
9593 
9594   format %{ "CMPWI   $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
9595             "LI      $dst, #1\n\t"
9596             "BEQ     $crx, done\n\t"
9597             "LI      $dst, #0\n"
9598             "done:" %}
9599   size(16);
9600   ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
9601   ins_pipe(pipe_class_compare);
9602 %}
9603 
9604 // AndI 0b0..010..0 + ConvI2B
9605 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
9606   match(Set dst (Conv2B (AndI src mask)));
9607   predicate(UseRotateAndMaskInstructionsPPC64);
9608   ins_cost(DEFAULT_COST);
9609 
9610   format %{ "RLWINM  $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
9611   size(4);
9612   ins_encode %{
9613     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9614     __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
9615   %}
9616   ins_pipe(pipe_class_default);
9617 %}
9618 
9619 // Convert pointer to boolean.
9620 //
9621 // ptr_to_bool(src) : { 1   if src != 0
9622 //                    { 0   else
9623 //
9624 // strategy:
9625 // 1) Count leading zeros of 64 bit-value src,
9626 //    this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
9627 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9628 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9629 
9630 // ConvP2B
9631 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
9632   match(Set dst (Conv2B src));
9633   predicate(UseCountLeadingZerosInstructionsPPC64);
9634   ins_cost(DEFAULT_COST);
9635 
9636   expand %{
9637     immI shiftAmount %{ 0x6 %}
9638     uimmI16 mask %{ 0x1 %}
9639     iRegIdst tmp1;
9640     iRegIdst tmp2;
9641     countLeadingZerosP(tmp1, src);
9642     urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9643     xorI_reg_uimm16(dst, tmp2, mask);
9644   %}
9645 %}
9646 
9647 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
9648   match(Set dst (Conv2B src));
9649   effect(TEMP crx);
9650   predicate(!UseCountLeadingZerosInstructionsPPC64);
9651   ins_cost(DEFAULT_COST);
9652 
9653   format %{ "CMPDI   $crx, $src, #0 \t// convP2B"
9654             "LI      $dst, #0\n\t"
9655             "BEQ     $crx, done\n\t"
9656             "LI      $dst, #1\n"
9657             "done:" %}
9658   size(16);
9659   ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
9660   ins_pipe(pipe_class_compare);
9661 %}
9662 
9663 // ConvP2B + XorI
9664 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
9665   match(Set dst (XorI (Conv2B src) mask));
9666   predicate(UseCountLeadingZerosInstructionsPPC64);
9667   ins_cost(DEFAULT_COST);
9668 
9669   expand %{
9670     immI shiftAmount %{ 0x6 %}
9671     iRegIdst tmp1;
9672     countLeadingZerosP(tmp1, src);
9673     urShiftI_reg_imm(dst, tmp1, shiftAmount);
9674   %}
9675 %}
9676 
9677 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
9678   match(Set dst (XorI (Conv2B src) mask));
9679   effect(TEMP crx);
9680   predicate(!UseCountLeadingZerosInstructionsPPC64);
9681   ins_cost(DEFAULT_COST);
9682 
9683   format %{ "CMPDI   $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
9684             "LI      $dst, #1\n\t"
9685             "BEQ     $crx, done\n\t"
9686             "LI      $dst, #0\n"
9687             "done:" %}
9688   size(16);
9689   ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
9690   ins_pipe(pipe_class_compare);
9691 %}
9692 
9693 // if src1 < src2, return -1 else return 0
9694 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9695   match(Set dst (CmpLTMask src1 src2));
9696   ins_cost(DEFAULT_COST*4);
9697 
9698   expand %{
9699     iRegLdst src1s;
9700     iRegLdst src2s;
9701     iRegLdst diff;
9702     convI2L_reg(src1s, src1); // Ensure proper sign extension.
9703     convI2L_reg(src2s, src2); // Ensure proper sign extension.
9704     subL_reg_reg(diff, src1s, src2s);
9705     // Need to consider >=33 bit result, therefore we need signmaskL.
9706     signmask64I_regL(dst, diff);
9707   %}
9708 %}
9709 
9710 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
9711   match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
9712   format %{ "SRAWI   $dst, $src1, $src2 \t// CmpLTMask" %}
9713   size(4);
9714   ins_encode %{
9715     // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9716     __ srawi($dst$$Register, $src1$$Register, 0x1f);
9717   %}
9718   ins_pipe(pipe_class_default);
9719 %}
9720 
9721 //----------Arithmetic Conversion Instructions---------------------------------
9722 
9723 // Convert to Byte  -- nop
9724 // Convert to Short -- nop
9725 
9726 // Convert to Int
9727 
9728 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
9729   match(Set dst (RShiftI (LShiftI src amount) amount));
9730   format %{ "EXTSB   $dst, $src \t// byte->int" %}
9731   size(4);
9732   ins_encode %{
9733     // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
9734     __ extsb($dst$$Register, $src$$Register);
9735   %}
9736   ins_pipe(pipe_class_default);
9737 %}
9738 
9739 // LShiftI 16 + RShiftI 16 converts short to int.
9740 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
9741   match(Set dst (RShiftI (LShiftI src amount) amount));
9742   format %{ "EXTSH   $dst, $src \t// short->int" %}
9743   size(4);
9744   ins_encode %{
9745     // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
9746     __ extsh($dst$$Register, $src$$Register);
9747   %}
9748   ins_pipe(pipe_class_default);
9749 %}
9750 
9751 // ConvL2I + ConvI2L: Sign extend int in long register.
9752 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
9753   match(Set dst (ConvI2L (ConvL2I src)));
9754 
9755   format %{ "EXTSW   $dst, $src \t// long->long" %}
9756   size(4);
9757   ins_encode %{
9758     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9759     __ extsw($dst$$Register, $src$$Register);
9760   %}
9761   ins_pipe(pipe_class_default);
9762 %}
9763 
9764 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
9765   match(Set dst (ConvL2I src));
9766   format %{ "MR      $dst, $src \t// long->int" %}
9767   // variable size, 0 or 4
9768   ins_encode %{
9769     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9770     __ mr_if_needed($dst$$Register, $src$$Register);
9771   %}
9772   ins_pipe(pipe_class_default);
9773 %}
9774 
9775 instruct convD2IRaw_regD(regD dst, regD src) %{
9776   // no match-rule, false predicate
9777   effect(DEF dst, USE src);
9778   predicate(false);
9779 
9780   format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
9781   size(4);
9782   ins_encode %{
9783     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
9784     __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9785   %}
9786   ins_pipe(pipe_class_default);
9787 %}
9788 
9789 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsRegSrc crx, stackSlotL src) %{
9790   // no match-rule, false predicate
9791   effect(DEF dst, USE crx, USE src);
9792   predicate(false);
9793 
9794   ins_variable_size_depending_on_alignment(true);
9795 
9796   format %{ "cmovI   $crx, $dst, $src" %}
9797   // Worst case is branch + move + stop, no stop without scheduler.
9798   size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9799   ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9800   ins_pipe(pipe_class_default);
9801 %}
9802 
9803 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, stackSlotL mem) %{
9804   // no match-rule, false predicate
9805   effect(DEF dst, USE crx, USE mem);
9806   predicate(false);
9807 
9808   format %{ "CmovI   $dst, $crx, $mem \t// postalloc expanded" %}
9809   postalloc_expand %{
9810     //
9811     // replaces
9812     //
9813     //   region  dst  crx  mem
9814     //    \       |    |   /
9815     //     dst=cmovI_bso_stackSlotL_conLvalue0
9816     //
9817     // with
9818     //
9819     //   region  dst
9820     //    \       /
9821     //     dst=loadConI16(0)
9822     //      |
9823     //      ^  region  dst  crx  mem
9824     //      |   \       |    |    /
9825     //      dst=cmovI_bso_stackSlotL
9826     //
9827 
9828     // Create new nodes.
9829     MachNode *m1 = new loadConI16Node();
9830     MachNode *m2 = new cmovI_bso_stackSlotLNode();
9831 
9832     // inputs for new nodes
9833     m1->add_req(n_region);
9834     m2->add_req(n_region, n_crx, n_mem);
9835 
9836     // precedences for new nodes
9837     m2->add_prec(m1);
9838 
9839     // operands for new nodes
9840     m1->_opnds[0] = op_dst;
9841     m1->_opnds[1] = new immI16Oper(0);
9842 
9843     m2->_opnds[0] = op_dst;
9844     m2->_opnds[1] = op_crx;
9845     m2->_opnds[2] = op_mem;
9846 
9847     // registers for new nodes
9848     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9849     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9850 
9851     // Insert new nodes.
9852     nodes->push(m1);
9853     nodes->push(m2);
9854   %}
9855 %}
9856 
9857 // Double to Int conversion, NaN is mapped to 0.
9858 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
9859   match(Set dst (ConvD2I src));
9860   ins_cost(DEFAULT_COST);
9861 
9862   expand %{
9863     regD tmpD;
9864     stackSlotL tmpS;
9865     flagsReg crx;
9866     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
9867     convD2IRaw_regD(tmpD, src);                         // Convert float to int (speculated).
9868     moveD2L_reg_stack(tmpS, tmpD);                      // Store float to stack (speculated).
9869     cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9870   %}
9871 %}
9872 
9873 instruct convF2IRaw_regF(regF dst, regF src) %{
9874   // no match-rule, false predicate
9875   effect(DEF dst, USE src);
9876   predicate(false);
9877 
9878   format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
9879   size(4);
9880   ins_encode %{
9881     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9882     __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9883   %}
9884   ins_pipe(pipe_class_default);
9885 %}
9886 
9887 // Float to Int conversion, NaN is mapped to 0.
9888 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
9889   match(Set dst (ConvF2I src));
9890   ins_cost(DEFAULT_COST);
9891 
9892   expand %{
9893     regF tmpF;
9894     stackSlotL tmpS;
9895     flagsReg crx;
9896     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
9897     convF2IRaw_regF(tmpF, src);                         // Convert float to int (speculated).
9898     moveF2L_reg_stack(tmpS, tmpF);                      // Store float to stack (speculated).
9899     cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9900   %}
9901 %}
9902 
9903 // Convert to Long
9904 
9905 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
9906   match(Set dst (ConvI2L src));
9907   format %{ "EXTSW   $dst, $src \t// int->long" %}
9908   size(4);
9909   ins_encode %{
9910     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9911     __ extsw($dst$$Register, $src$$Register);
9912   %}
9913   ins_pipe(pipe_class_default);
9914 %}
9915 
9916 // Zero-extend: convert unsigned int to long (convUI2L).
9917 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
9918   match(Set dst (AndL (ConvI2L src) mask));
9919   ins_cost(DEFAULT_COST);
9920 
9921   format %{ "CLRLDI  $dst, $src, #32 \t// zero-extend int to long" %}
9922   size(4);
9923   ins_encode %{
9924     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9925     __ clrldi($dst$$Register, $src$$Register, 32);
9926   %}
9927   ins_pipe(pipe_class_default);
9928 %}
9929 
9930 // Zero-extend: convert unsigned int to long in long register.
9931 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
9932   match(Set dst (AndL src mask));
9933   ins_cost(DEFAULT_COST);
9934 
9935   format %{ "CLRLDI  $dst, $src, #32 \t// zero-extend int to long" %}
9936   size(4);
9937   ins_encode %{
9938     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9939     __ clrldi($dst$$Register, $src$$Register, 32);
9940   %}
9941   ins_pipe(pipe_class_default);
9942 %}
9943 
9944 instruct convF2LRaw_regF(regF dst, regF src) %{
9945   // no match-rule, false predicate
9946   effect(DEF dst, USE src);
9947   predicate(false);
9948 
9949   format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
9950   size(4);
9951   ins_encode %{
9952     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9953     __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9954   %}
9955   ins_pipe(pipe_class_default);
9956 %}
9957 
9958 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL src) %{
9959   // no match-rule, false predicate
9960   effect(DEF dst, USE crx, USE src);
9961   predicate(false);
9962 
9963   ins_variable_size_depending_on_alignment(true);
9964 
9965   format %{ "cmovL   $crx, $dst, $src" %}
9966   // Worst case is branch + move + stop, no stop without scheduler.
9967   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
9968   ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9969   ins_pipe(pipe_class_default);
9970 %}
9971 
9972 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, stackSlotL mem) %{
9973   // no match-rule, false predicate
9974   effect(DEF dst, USE crx, USE mem);
9975   predicate(false);
9976 
9977   format %{ "CmovL   $dst, $crx, $mem \t// postalloc expanded" %}
9978   postalloc_expand %{
9979     //
9980     // replaces
9981     //
9982     //   region  dst  crx  mem
9983     //    \       |    |   /
9984     //     dst=cmovL_bso_stackSlotL_conLvalue0
9985     //
9986     // with
9987     //
9988     //   region  dst
9989     //    \       /
9990     //     dst=loadConL16(0)
9991     //      |
9992     //      ^  region  dst  crx  mem
9993     //      |   \       |    |    /
9994     //      dst=cmovL_bso_stackSlotL
9995     //
9996 
9997     // Create new nodes.
9998     MachNode *m1 = new loadConL16Node();
9999     MachNode *m2 = new cmovL_bso_stackSlotLNode();
10000 
10001     // inputs for new nodes
10002     m1->add_req(n_region);
10003     m2->add_req(n_region, n_crx, n_mem);
10004     m2->add_prec(m1);
10005 
10006     // operands for new nodes
10007     m1->_opnds[0] = op_dst;
10008     m1->_opnds[1] = new immL16Oper(0);
10009     m2->_opnds[0] = op_dst;
10010     m2->_opnds[1] = op_crx;
10011     m2->_opnds[2] = op_mem;
10012 
10013     // registers for new nodes
10014     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10015     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10016 
10017     // Insert new nodes.
10018     nodes->push(m1);
10019     nodes->push(m2);
10020   %}
10021 %}
10022 
10023 // Float to Long conversion, NaN is mapped to 0.
10024 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
10025   match(Set dst (ConvF2L src));
10026   ins_cost(DEFAULT_COST);
10027 
10028   expand %{
10029     regF tmpF;
10030     stackSlotL tmpS;
10031     flagsReg crx;
10032     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10033     convF2LRaw_regF(tmpF, src);                         // Convert float to long (speculated).
10034     moveF2L_reg_stack(tmpS, tmpF);                      // Store float to stack (speculated).
10035     cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10036   %}
10037 %}
10038 
10039 instruct convD2LRaw_regD(regD dst, regD src) %{
10040   // no match-rule, false predicate
10041   effect(DEF dst, USE src);
10042   predicate(false);
10043 
10044   format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
10045   size(4);
10046   ins_encode %{
10047     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10048     __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10049   %}
10050   ins_pipe(pipe_class_default);
10051 %}
10052 
10053 // Double to Long conversion, NaN is mapped to 0.
10054 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
10055   match(Set dst (ConvD2L src));
10056   ins_cost(DEFAULT_COST);
10057 
10058   expand %{
10059     regD tmpD;
10060     stackSlotL tmpS;
10061     flagsReg crx;
10062     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10063     convD2LRaw_regD(tmpD, src);                         // Convert float to long (speculated).
10064     moveD2L_reg_stack(tmpS, tmpD);                      // Store float to stack (speculated).
10065     cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10066   %}
10067 %}
10068 
10069 // Convert to Float
10070 
10071 // Placed here as needed in expand.
10072 instruct convL2DRaw_regD(regD dst, regD src) %{
10073   // no match-rule, false predicate
10074   effect(DEF dst, USE src);
10075   predicate(false);
10076 
10077   format %{ "FCFID $dst, $src \t// convL2D" %}
10078   size(4);
10079   ins_encode %{
10080     // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10081     __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
10082   %}
10083   ins_pipe(pipe_class_default);
10084 %}
10085 
10086 // Placed here as needed in expand.
10087 instruct convD2F_reg(regF dst, regD src) %{
10088   match(Set dst (ConvD2F src));
10089   format %{ "FRSP    $dst, $src \t// convD2F" %}
10090   size(4);
10091   ins_encode %{
10092     // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
10093     __ frsp($dst$$FloatRegister, $src$$FloatRegister);
10094   %}
10095   ins_pipe(pipe_class_default);
10096 %}
10097 
10098 // Integer to Float conversion.
10099 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
10100   match(Set dst (ConvI2F src));
10101   predicate(!VM_Version::has_fcfids());
10102   ins_cost(DEFAULT_COST);
10103 
10104   expand %{
10105     iRegLdst tmpL;
10106     stackSlotL tmpS;
10107     regD tmpD;
10108     regD tmpD2;
10109     convI2L_reg(tmpL, src);              // Sign-extension int to long.
10110     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
10111     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
10112     convL2DRaw_regD(tmpD2, tmpD);        // Convert to double.
10113     convD2F_reg(dst, tmpD2);             // Convert double to float.
10114   %}
10115 %}
10116 
10117 instruct convL2FRaw_regF(regF dst, regD src) %{
10118   // no match-rule, false predicate
10119   effect(DEF dst, USE src);
10120   predicate(false);
10121 
10122   format %{ "FCFIDS $dst, $src \t// convL2F" %}
10123   size(4);
10124   ins_encode %{
10125     // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10126     __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10127   %}
10128   ins_pipe(pipe_class_default);
10129 %}
10130 
10131 // Integer to Float conversion. Special version for Power7.
10132 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10133   match(Set dst (ConvI2F src));
10134   predicate(VM_Version::has_fcfids());
10135   ins_cost(DEFAULT_COST);
10136 
10137   expand %{
10138     iRegLdst tmpL;
10139     stackSlotL tmpS;
10140     regD tmpD;
10141     convI2L_reg(tmpL, src);              // Sign-extension int to long.
10142     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
10143     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
10144     convL2FRaw_regF(dst, tmpD);          // Convert to float.
10145   %}
10146 %}
10147 
10148 // L2F to avoid runtime call.
10149 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10150   match(Set dst (ConvL2F src));
10151   predicate(VM_Version::has_fcfids());
10152   ins_cost(DEFAULT_COST);
10153 
10154   expand %{
10155     stackSlotL tmpS;
10156     regD tmpD;
10157     regL_to_stkL(tmpS, src);             // Store long to stack.
10158     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
10159     convL2FRaw_regF(dst, tmpD);          // Convert to float.
10160   %}
10161 %}
10162 
10163 // Moved up as used in expand.
10164 //instruct convD2F_reg(regF dst, regD src) %{%}
10165 
10166 // Convert to Double
10167 
10168 // Integer to Double conversion.
10169 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
10170   match(Set dst (ConvI2D src));
10171   ins_cost(DEFAULT_COST);
10172 
10173   expand %{
10174     iRegLdst tmpL;
10175     stackSlotL tmpS;
10176     regD tmpD;
10177     convI2L_reg(tmpL, src);              // Sign-extension int to long.
10178     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
10179     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
10180     convL2DRaw_regD(dst, tmpD);          // Convert to double.
10181   %}
10182 %}
10183 
10184 // Long to Double conversion
10185 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
10186   match(Set dst (ConvL2D src));
10187   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10188 
10189   expand %{
10190     regD tmpD;
10191     moveL2D_stack_reg(tmpD, src);
10192     convL2DRaw_regD(dst, tmpD);
10193   %}
10194 %}
10195 
10196 instruct convF2D_reg(regD dst, regF src) %{
10197   match(Set dst (ConvF2D src));
10198   format %{ "FMR     $dst, $src \t// float->double" %}
10199   // variable size, 0 or 4
10200   ins_encode %{
10201     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
10202     __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10203   %}
10204   ins_pipe(pipe_class_default);
10205 %}
10206 
10207 //----------Control Flow Instructions------------------------------------------
10208 // Compare Instructions
10209 
10210 // Compare Integers
10211 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10212   match(Set crx (CmpI src1 src2));
10213   size(4);
10214   format %{ "CMPW    $crx, $src1, $src2" %}
10215   ins_encode %{
10216     // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10217     __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10218   %}
10219   ins_pipe(pipe_class_compare);
10220 %}
10221 
10222 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
10223   match(Set crx (CmpI src1 src2));
10224   format %{ "CMPWI   $crx, $src1, $src2" %}
10225   size(4);
10226   ins_encode %{
10227     // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10228     __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10229   %}
10230   ins_pipe(pipe_class_compare);
10231 %}
10232 
10233 // (src1 & src2) == 0?
10234 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
10235   match(Set cr0 (CmpI (AndI src1 src2) zero));
10236   // r0 is killed
10237   format %{ "ANDI    R0, $src1, $src2 \t// BTST int" %}
10238   size(4);
10239   ins_encode %{
10240     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10241     __ andi_(R0, $src1$$Register, $src2$$constant);
10242   %}
10243   ins_pipe(pipe_class_compare);
10244 %}
10245 
10246 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10247   match(Set crx (CmpL src1 src2));
10248   format %{ "CMPD    $crx, $src1, $src2" %}
10249   size(4);
10250   ins_encode %{
10251     // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10252     __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
10253   %}
10254   ins_pipe(pipe_class_compare);
10255 %}
10256 
10257 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
10258   match(Set crx (CmpL src1 src2));
10259   format %{ "CMPDI   $crx, $src1, $src2" %}
10260   size(4);
10261   ins_encode %{
10262     // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10263     __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10264   %}
10265   ins_pipe(pipe_class_compare);
10266 %}
10267 
10268 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
10269   match(Set cr0 (CmpL (AndL src1 src2) zero));
10270   // r0 is killed
10271   format %{ "AND     R0, $src1, $src2 \t// BTST long" %}
10272   size(4);
10273   ins_encode %{
10274     // TODO: PPC port $archOpcode(ppc64Opcode_and_);
10275     __ and_(R0, $src1$$Register, $src2$$Register);
10276   %}
10277   ins_pipe(pipe_class_compare);
10278 %}
10279 
10280 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
10281   match(Set cr0 (CmpL (AndL src1 src2) zero));
10282   // r0 is killed
10283   format %{ "ANDI    R0, $src1, $src2 \t// BTST long" %}
10284   size(4);
10285   ins_encode %{
10286     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10287     __ andi_(R0, $src1$$Register, $src2$$constant);
10288   %}
10289   ins_pipe(pipe_class_compare);
10290 %}
10291 
10292 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsRegSrc crx) %{
10293   // no match-rule, false predicate
10294   effect(DEF dst, USE crx);
10295   predicate(false);
10296 
10297   ins_variable_size_depending_on_alignment(true);
10298 
10299   format %{ "cmovI   $crx, $dst, -1, 0, +1" %}
10300   // Worst case is branch + move + branch + move + stop, no stop without scheduler.
10301   size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
10302   ins_encode %{
10303     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
10304     Label done;
10305     // li(Rdst, 0);              // equal -> 0
10306     __ beq($crx$$CondRegister, done);
10307     __ li($dst$$Register, 1);    // greater -> +1
10308     __ bgt($crx$$CondRegister, done);
10309     __ li($dst$$Register, -1);   // unordered or less -> -1
10310     // TODO: PPC port__ endgroup_if_needed(_size == 20);
10311     __ bind(done);
10312   %}
10313   ins_pipe(pipe_class_compare);
10314 %}
10315 
10316 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsRegSrc crx) %{
10317   // no match-rule, false predicate
10318   effect(DEF dst, USE crx);
10319   predicate(false);
10320 
10321   format %{ "CmovI    $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
10322   postalloc_expand %{
10323     //
10324     // replaces
10325     //
10326     //   region  crx
10327     //    \       |
10328     //     dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
10329     //
10330     // with
10331     //
10332     //   region
10333     //    \
10334     //     dst=loadConI16(0)
10335     //      |
10336     //      ^  region  crx
10337     //      |   \       |
10338     //      dst=cmovI_conIvalueMinus1_conIvalue1
10339     //
10340 
10341     // Create new nodes.
10342     MachNode *m1 = new loadConI16Node();
10343     MachNode *m2 = new cmovI_conIvalueMinus1_conIvalue1Node();
10344 
10345     // inputs for new nodes
10346     m1->add_req(n_region);
10347     m2->add_req(n_region, n_crx);
10348     m2->add_prec(m1);
10349 
10350     // operands for new nodes
10351     m1->_opnds[0] = op_dst;
10352     m1->_opnds[1] = new immI16Oper(0);
10353     m2->_opnds[0] = op_dst;
10354     m2->_opnds[1] = op_crx;
10355 
10356     // registers for new nodes
10357     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10358     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10359 
10360     // Insert new nodes.
10361     nodes->push(m1);
10362     nodes->push(m2);
10363   %}
10364 %}
10365 
10366 // Manifest a CmpL3 result in an integer register. Very painful.
10367 // This is the test to avoid.
10368 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
10369 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10370   match(Set dst (CmpL3 src1 src2));
10371   ins_cost(DEFAULT_COST*5+BRANCH_COST);
10372 
10373   expand %{
10374     flagsReg tmp1;
10375     cmpL_reg_reg(tmp1, src1, src2);
10376     cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10377   %}
10378 %}
10379 
10380 // Implicit range checks.
10381 // A range check in the ideal world has one of the following shapes:
10382 //  - (If le (CmpU length index)), (IfTrue  throw exception)
10383 //  - (If lt (CmpU index length)), (IfFalse throw exception)
10384 //
10385 // Match range check 'If le (CmpU length index)'.
10386 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
10387   match(If cmp (CmpU src_length index));
10388   effect(USE labl);
10389   predicate(TrapBasedRangeChecks &&
10390             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
10391             PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
10392             (Matcher::branches_to_uncommon_trap(_leaf)));
10393 
10394   ins_is_TrapBasedCheckNode(true);
10395 
10396   format %{ "TWI     $index $cmp $src_length \t// RangeCheck => trap $labl" %}
10397   size(4);
10398   ins_encode %{
10399     // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10400     if ($cmp$$cmpcode == 0x1 /* less_equal */) {
10401       __ trap_range_check_le($src_length$$Register, $index$$constant);
10402     } else {
10403       // Both successors are uncommon traps, probability is 0.
10404       // Node got flipped during fixup flow.
10405       assert($cmp$$cmpcode == 0x9, "must be greater");
10406       __ trap_range_check_g($src_length$$Register, $index$$constant);
10407     }
10408   %}
10409   ins_pipe(pipe_class_trap);
10410 %}
10411 
10412 // Match range check 'If lt (CmpU index length)'.
10413 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
10414   match(If cmp (CmpU src_index src_length));
10415   effect(USE labl);
10416   predicate(TrapBasedRangeChecks &&
10417             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10418             _leaf->as_If()->_prob >= PROB_ALWAYS &&
10419             (Matcher::branches_to_uncommon_trap(_leaf)));
10420 
10421   ins_is_TrapBasedCheckNode(true);
10422 
10423   format %{ "TW      $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
10424   size(4);
10425   ins_encode %{
10426     // TODO: PPC port $archOpcode(ppc64Opcode_tw);
10427     if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10428       __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
10429     } else {
10430       // Both successors are uncommon traps, probability is 0.
10431       // Node got flipped during fixup flow.
10432       assert($cmp$$cmpcode == 0x8, "must be less");
10433       __ trap_range_check_l($src_index$$Register, $src_length$$Register);
10434     }
10435   %}
10436   ins_pipe(pipe_class_trap);
10437 %}
10438 
10439 // Match range check 'If lt (CmpU index length)'.
10440 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
10441   match(If cmp (CmpU src_index length));
10442   effect(USE labl);
10443   predicate(TrapBasedRangeChecks &&
10444             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10445             _leaf->as_If()->_prob >= PROB_ALWAYS &&
10446             (Matcher::branches_to_uncommon_trap(_leaf)));
10447 
10448   ins_is_TrapBasedCheckNode(true);
10449 
10450   format %{ "TWI     $src_index $cmp $length \t// RangeCheck => trap $labl" %}
10451   size(4);
10452   ins_encode %{
10453     // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10454     if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10455       __ trap_range_check_ge($src_index$$Register, $length$$constant);
10456     } else {
10457       // Both successors are uncommon traps, probability is 0.
10458       // Node got flipped during fixup flow.
10459       assert($cmp$$cmpcode == 0x8, "must be less");
10460       __ trap_range_check_l($src_index$$Register, $length$$constant);
10461     }
10462   %}
10463   ins_pipe(pipe_class_trap);
10464 %}
10465 
10466 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10467   match(Set crx (CmpU src1 src2));
10468   format %{ "CMPLW   $crx, $src1, $src2 \t// unsigned" %}
10469   size(4);
10470   ins_encode %{
10471     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10472     __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10473   %}
10474   ins_pipe(pipe_class_compare);
10475 %}
10476 
10477 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
10478   match(Set crx (CmpU src1 src2));
10479   size(4);
10480   format %{ "CMPLWI  $crx, $src1, $src2" %}
10481   ins_encode %{
10482     // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10483     __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10484   %}
10485   ins_pipe(pipe_class_compare);
10486 %}
10487 
10488 // Implicit zero checks (more implicit null checks).
10489 // No constant pool entries required.
10490 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
10491   match(If cmp (CmpN value zero));
10492   effect(USE labl);
10493   predicate(TrapBasedNullChecks &&
10494             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10495             _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10496             Matcher::branches_to_uncommon_trap(_leaf));
10497   ins_cost(1);
10498 
10499   ins_is_TrapBasedCheckNode(true);
10500 
10501   format %{ "TDI     $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
10502   size(4);
10503   ins_encode %{
10504     // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10505     if ($cmp$$cmpcode == 0xA) {
10506       __ trap_null_check($value$$Register);
10507     } else {
10508       // Both successors are uncommon traps, probability is 0.
10509       // Node got flipped during fixup flow.
10510       assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10511       __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10512     }
10513   %}
10514   ins_pipe(pipe_class_trap);
10515 %}
10516 
10517 // Compare narrow oops.
10518 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
10519   match(Set crx (CmpN src1 src2));
10520 
10521   size(4);
10522   ins_cost(2);
10523   format %{ "CMPLW   $crx, $src1, $src2 \t// compressed ptr" %}
10524   ins_encode %{
10525     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10526     __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10527   %}
10528   ins_pipe(pipe_class_compare);
10529 %}
10530 
10531 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
10532   match(Set crx (CmpN src1 src2));
10533   // Make this more expensive than zeroCheckN_iReg_imm0.
10534   ins_cost(2);
10535 
10536   format %{ "CMPLWI  $crx, $src1, $src2 \t// compressed ptr" %}
10537   size(4);
10538   ins_encode %{
10539     // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10540     __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10541   %}
10542   ins_pipe(pipe_class_compare);
10543 %}
10544 
10545 // Implicit zero checks (more implicit null checks).
10546 // No constant pool entries required.
10547 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
10548   match(If cmp (CmpP value zero));
10549   effect(USE labl);
10550   predicate(TrapBasedNullChecks &&
10551             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10552             _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10553             Matcher::branches_to_uncommon_trap(_leaf));
10554   ins_cost(1); // Should not be cheaper than zeroCheckN.
10555 
10556   ins_is_TrapBasedCheckNode(true);
10557 
10558   format %{ "TDI     $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
10559   size(4);
10560   ins_encode %{
10561     // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10562     if ($cmp$$cmpcode == 0xA) {
10563       __ trap_null_check($value$$Register);
10564     } else {
10565       // Both successors are uncommon traps, probability is 0.
10566       // Node got flipped during fixup flow.
10567       assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10568       __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10569     }
10570   %}
10571   ins_pipe(pipe_class_trap);
10572 %}
10573 
10574 // Compare Pointers
10575 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
10576   match(Set crx (CmpP src1 src2));
10577   format %{ "CMPLD   $crx, $src1, $src2 \t// ptr" %}
10578   size(4);
10579   ins_encode %{
10580     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10581     __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10582   %}
10583   ins_pipe(pipe_class_compare);
10584 %}
10585 
10586 // Used in postalloc expand.
10587 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
10588   // This match rule prevents reordering of node before a safepoint.
10589   // This only makes sense if this instructions is used exclusively
10590   // for the expansion of EncodeP!
10591   match(Set crx (CmpP src1 src2));
10592   predicate(false);
10593 
10594   format %{ "CMPDI   $crx, $src1, $src2" %}
10595   size(4);
10596   ins_encode %{
10597     // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10598     __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10599   %}
10600   ins_pipe(pipe_class_compare);
10601 %}
10602 
10603 //----------Float Compares----------------------------------------------------
10604 
10605 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
10606   // Needs matchrule, see cmpDUnordered.
10607   match(Set crx (CmpF src1 src2));
10608   // no match-rule, false predicate
10609   predicate(false);
10610 
10611   format %{ "cmpFUrd $crx, $src1, $src2" %}
10612   size(4);
10613   ins_encode %{
10614     // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10615     __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10616   %}
10617   ins_pipe(pipe_class_default);
10618 %}
10619 
10620 instruct cmov_bns_less(flagsReg crx) %{
10621   // no match-rule, false predicate
10622   effect(DEF crx);
10623   predicate(false);
10624 
10625   ins_variable_size_depending_on_alignment(true);
10626 
10627   format %{ "cmov    $crx" %}
10628   // Worst case is branch + move + stop, no stop without scheduler.
10629   size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
10630   ins_encode %{
10631     // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
10632     Label done;
10633     __ bns($crx$$CondRegister, done);        // not unordered -> keep crx
10634     __ li(R0, 0);
10635     __ cmpwi($crx$$CondRegister, R0, 1);     // unordered -> set crx to 'less'
10636     // TODO PPC port __ endgroup_if_needed(_size == 16);
10637     __ bind(done);
10638   %}
10639   ins_pipe(pipe_class_default);
10640 %}
10641 
10642 // Compare floating, generate condition code.
10643 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
10644   // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
10645   //
10646   // The following code sequence occurs a lot in mpegaudio:
10647   //
10648   // block BXX:
10649   // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
10650   //    cmpFUrd CCR6, F11, F9
10651   // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
10652   //    cmov CCR6
10653   // 8: instruct branchConSched:
10654   //    B_FARle CCR6, B56  P=0.500000 C=-1.000000
10655   match(Set crx (CmpF src1 src2));
10656   ins_cost(DEFAULT_COST+BRANCH_COST);
10657 
10658   format %{ "CmpF    $crx, $src1, $src2 \t// postalloc expanded" %}
10659   postalloc_expand %{
10660     //
10661     // replaces
10662     //
10663     //   region  src1  src2
10664     //    \       |     |
10665     //     crx=cmpF_reg_reg
10666     //
10667     // with
10668     //
10669     //   region  src1  src2
10670     //    \       |     |
10671     //     crx=cmpFUnordered_reg_reg
10672     //      |
10673     //      ^  region
10674     //      |   \
10675     //      crx=cmov_bns_less
10676     //
10677 
10678     // Create new nodes.
10679     MachNode *m1 = new cmpFUnordered_reg_regNode();
10680     MachNode *m2 = new cmov_bns_lessNode();
10681 
10682     // inputs for new nodes
10683     m1->add_req(n_region, n_src1, n_src2);
10684     m2->add_req(n_region);
10685     m2->add_prec(m1);
10686 
10687     // operands for new nodes
10688     m1->_opnds[0] = op_crx;
10689     m1->_opnds[1] = op_src1;
10690     m1->_opnds[2] = op_src2;
10691     m2->_opnds[0] = op_crx;
10692 
10693     // registers for new nodes
10694     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10695     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10696 
10697     // Insert new nodes.
10698     nodes->push(m1);
10699     nodes->push(m2);
10700   %}
10701 %}
10702 
10703 // Compare float, generate -1,0,1
10704 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
10705   match(Set dst (CmpF3 src1 src2));
10706   ins_cost(DEFAULT_COST*5+BRANCH_COST);
10707 
10708   expand %{
10709     flagsReg tmp1;
10710     cmpFUnordered_reg_reg(tmp1, src1, src2);
10711     cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10712   %}
10713 %}
10714 
10715 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
10716   // Needs matchrule so that ideal opcode is Cmp. This causes that gcm places the
10717   // node right before the conditional move using it.
10718   // In jck test api/java_awt/geom/QuadCurve2DFloat/index.html#SetCurveTesttestCase7,
10719   // compilation of java.awt.geom.RectangularShape::getBounds()Ljava/awt/Rectangle
10720   // crashed in register allocation where the flags Reg between cmpDUnoredered and a
10721   // conditional move was supposed to be spilled.
10722   match(Set crx (CmpD src1 src2));
10723   // False predicate, shall not be matched.
10724   predicate(false);
10725 
10726   format %{ "cmpFUrd $crx, $src1, $src2" %}
10727   size(4);
10728   ins_encode %{
10729     // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10730     __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10731   %}
10732   ins_pipe(pipe_class_default);
10733 %}
10734 
10735 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
10736   match(Set crx (CmpD src1 src2));
10737   ins_cost(DEFAULT_COST+BRANCH_COST);
10738 
10739   format %{ "CmpD    $crx, $src1, $src2 \t// postalloc expanded" %}
10740   postalloc_expand %{
10741     //
10742     // replaces
10743     //
10744     //   region  src1  src2
10745     //    \       |     |
10746     //     crx=cmpD_reg_reg
10747     //
10748     // with
10749     //
10750     //   region  src1  src2
10751     //    \       |     |
10752     //     crx=cmpDUnordered_reg_reg
10753     //      |
10754     //      ^  region
10755     //      |   \
10756     //      crx=cmov_bns_less
10757     //
10758 
10759     // create new nodes
10760     MachNode *m1 = new cmpDUnordered_reg_regNode();
10761     MachNode *m2 = new cmov_bns_lessNode();
10762 
10763     // inputs for new nodes
10764     m1->add_req(n_region, n_src1, n_src2);
10765     m2->add_req(n_region);
10766     m2->add_prec(m1);
10767 
10768     // operands for new nodes
10769     m1->_opnds[0] = op_crx;
10770     m1->_opnds[1] = op_src1;
10771     m1->_opnds[2] = op_src2;
10772     m2->_opnds[0] = op_crx;
10773 
10774     // registers for new nodes
10775     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10776     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10777 
10778     // Insert new nodes.
10779     nodes->push(m1);
10780     nodes->push(m2);
10781   %}
10782 %}
10783 
10784 // Compare double, generate -1,0,1
10785 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
10786   match(Set dst (CmpD3 src1 src2));
10787   ins_cost(DEFAULT_COST*5+BRANCH_COST);
10788 
10789   expand %{
10790     flagsReg tmp1;
10791     cmpDUnordered_reg_reg(tmp1, src1, src2);
10792     cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10793   %}
10794 %}
10795 
10796 //----------Branches---------------------------------------------------------
10797 // Jump
10798 
10799 // Direct Branch.
10800 instruct branch(label labl) %{
10801   match(Goto);
10802   effect(USE labl);
10803   ins_cost(BRANCH_COST);
10804 
10805   format %{ "B       $labl" %}
10806   size(4);
10807   ins_encode %{
10808     // TODO: PPC port $archOpcode(ppc64Opcode_b);
10809      Label d;    // dummy
10810      __ bind(d);
10811      Label* p = $labl$$label;
10812      // `p' is `NULL' when this encoding class is used only to
10813      // determine the size of the encoded instruction.
10814      Label& l = (NULL == p)? d : *(p);
10815      __ b(l);
10816   %}
10817   ins_pipe(pipe_class_default);
10818 %}
10819 
10820 // Conditional Near Branch
10821 instruct branchCon(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10822   // Same match rule as `branchConFar'.
10823   match(If cmp crx);
10824   effect(USE lbl);
10825   ins_cost(BRANCH_COST);
10826 
10827   // If set to 1 this indicates that the current instruction is a
10828   // short variant of a long branch. This avoids using this
10829   // instruction in first-pass matching. It will then only be used in
10830   // the `Shorten_branches' pass.
10831   ins_short_branch(1);
10832 
10833   format %{ "B$cmp     $crx, $lbl" %}
10834   size(4);
10835   ins_encode( enc_bc(crx, cmp, lbl) );
10836   ins_pipe(pipe_class_default);
10837 %}
10838 
10839 // This is for cases when the ppc64 `bc' instruction does not
10840 // reach far enough. So we emit a far branch here, which is more
10841 // expensive.
10842 //
10843 // Conditional Far Branch
10844 instruct branchConFar(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10845   // Same match rule as `branchCon'.
10846   match(If cmp crx);
10847   effect(USE crx, USE lbl);
10848   predicate(!false /* TODO: PPC port HB_Schedule*/);
10849   // Higher cost than `branchCon'.
10850   ins_cost(5*BRANCH_COST);
10851 
10852   // This is not a short variant of a branch, but the long variant.
10853   ins_short_branch(0);
10854 
10855   format %{ "B_FAR$cmp $crx, $lbl" %}
10856   size(8);
10857   ins_encode( enc_bc_far(crx, cmp, lbl) );
10858   ins_pipe(pipe_class_default);
10859 %}
10860 
10861 // Conditional Branch used with Power6 scheduler (can be far or short).
10862 instruct branchConSched(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10863   // Same match rule as `branchCon'.
10864   match(If cmp crx);
10865   effect(USE crx, USE lbl);
10866   predicate(false /* TODO: PPC port HB_Schedule*/);
10867   // Higher cost than `branchCon'.
10868   ins_cost(5*BRANCH_COST);
10869 
10870   // Actually size doesn't depend on alignment but on shortening.
10871   ins_variable_size_depending_on_alignment(true);
10872   // long variant.
10873   ins_short_branch(0);
10874 
10875   format %{ "B_FAR$cmp $crx, $lbl" %}
10876   size(8); // worst case
10877   ins_encode( enc_bc_short_far(crx, cmp, lbl) );
10878   ins_pipe(pipe_class_default);
10879 %}
10880 
10881 instruct branchLoopEnd(cmpOp cmp, flagsRegSrc crx, label labl) %{
10882   match(CountedLoopEnd cmp crx);
10883   effect(USE labl);
10884   ins_cost(BRANCH_COST);
10885 
10886   // short variant.
10887   ins_short_branch(1);
10888 
10889   format %{ "B$cmp     $crx, $labl \t// counted loop end" %}
10890   size(4);
10891   ins_encode( enc_bc(crx, cmp, labl) );
10892   ins_pipe(pipe_class_default);
10893 %}
10894 
10895 instruct branchLoopEndFar(cmpOp cmp, flagsRegSrc crx, label labl) %{
10896   match(CountedLoopEnd cmp crx);
10897   effect(USE labl);
10898   predicate(!false /* TODO: PPC port HB_Schedule */);
10899   ins_cost(BRANCH_COST);
10900 
10901   // Long variant.
10902   ins_short_branch(0);
10903 
10904   format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10905   size(8);
10906   ins_encode( enc_bc_far(crx, cmp, labl) );
10907   ins_pipe(pipe_class_default);
10908 %}
10909 
10910 // Conditional Branch used with Power6 scheduler (can be far or short).
10911 instruct branchLoopEndSched(cmpOp cmp, flagsRegSrc crx, label labl) %{
10912   match(CountedLoopEnd cmp crx);
10913   effect(USE labl);
10914   predicate(false /* TODO: PPC port HB_Schedule */);
10915   // Higher cost than `branchCon'.
10916   ins_cost(5*BRANCH_COST);
10917 
10918   // Actually size doesn't depend on alignment but on shortening.
10919   ins_variable_size_depending_on_alignment(true);
10920   // Long variant.
10921   ins_short_branch(0);
10922 
10923   format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10924   size(8); // worst case
10925   ins_encode( enc_bc_short_far(crx, cmp, labl) );
10926   ins_pipe(pipe_class_default);
10927 %}
10928 
10929 // ============================================================================
10930 // Java runtime operations, intrinsics and other complex operations.
10931 
10932 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10933 // array for an instance of the superklass. Set a hidden internal cache on a
10934 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10935 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10936 //
10937 // GL TODO: Improve this.
10938 // - result should not be a TEMP
10939 // - Add match rule as on sparc avoiding additional Cmp.
10940 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
10941                              iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
10942   match(Set result (PartialSubtypeCheck subklass superklass));
10943   effect(TEMP_DEF result, TEMP tmp_klass, TEMP tmp_arrayptr);
10944   ins_cost(DEFAULT_COST*10);
10945 
10946   format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
10947   ins_encode %{
10948     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10949     __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
10950                                      $tmp_klass$$Register, NULL, $result$$Register);
10951   %}
10952   ins_pipe(pipe_class_default);
10953 %}
10954 
10955 // inlined locking and unlocking
10956 
10957 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10958   match(Set crx (FastLock oop box));
10959   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10960   predicate(!Compile::current()->use_rtm());
10961 
10962   format %{ "FASTLOCK  $oop, $box, $tmp1, $tmp2, $tmp3" %}
10963   ins_encode %{
10964     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10965     __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10966                                  $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
10967                                  UseBiasedLocking && !UseOptoBiasInlining); // SAPJVM MD 2014-11-06 UseOptoBiasInlining
10968     // If locking was successfull, crx should indicate 'EQ'.
10969     // The compiler generates a branch to the runtime call to
10970     // _complete_monitor_locking_Java for the case where crx is 'NE'.
10971   %}
10972   ins_pipe(pipe_class_compare);
10973 %}
10974 
10975 // Separate version for TM. Use bound register for box to enable USE_KILL.
10976 instruct cmpFastLock_tm(flagsReg crx, iRegPdst oop, rarg2RegP box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10977   match(Set crx (FastLock oop box));
10978   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, USE_KILL box);
10979   predicate(Compile::current()->use_rtm());
10980 
10981   format %{ "FASTLOCK  $oop, $box, $tmp1, $tmp2, $tmp3 (TM)" %}
10982   ins_encode %{
10983     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10984     __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10985                                  $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
10986                                  /*Biased Locking*/ false,
10987                                  _rtm_counters, _stack_rtm_counters,
10988                                  ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
10989                                  /*TM*/ true, ra_->C->profile_rtm());
10990     // If locking was successfull, crx should indicate 'EQ'.
10991     // The compiler generates a branch to the runtime call to
10992     // _complete_monitor_locking_Java for the case where crx is 'NE'.
10993   %}
10994   ins_pipe(pipe_class_compare);
10995 %}
10996 
10997 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10998   match(Set crx (FastUnlock oop box));
10999   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
11000   predicate(!Compile::current()->use_rtm());
11001 
11002   format %{ "FASTUNLOCK  $oop, $box, $tmp1, $tmp2" %}
11003   ins_encode %{
11004     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11005     __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
11006                                    $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
11007                                    UseBiasedLocking && !UseOptoBiasInlining,
11008                                    false);
11009     // If unlocking was successfull, crx should indicate 'EQ'.
11010     // The compiler generates a branch to the runtime call to
11011     // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
11012   %}
11013   ins_pipe(pipe_class_compare);
11014 %}
11015 
11016 instruct cmpFastUnlock_tm(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
11017   match(Set crx (FastUnlock oop box));
11018   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
11019   predicate(Compile::current()->use_rtm());
11020 
11021   format %{ "FASTUNLOCK  $oop, $box, $tmp1, $tmp2 (TM)" %}
11022   ins_encode %{
11023     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11024     __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
11025                                    $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
11026                                    /*Biased Locking*/ false, /*TM*/ true);
11027     // If unlocking was successfull, crx should indicate 'EQ'.
11028     // The compiler generates a branch to the runtime call to
11029     // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
11030   %}
11031   ins_pipe(pipe_class_compare);
11032 %}
11033 
11034 // Align address.
11035 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
11036   match(Set dst (CastX2P (AndL (CastP2X src) mask)));
11037 
11038   format %{ "ANDDI   $dst, $src, $mask \t// next aligned address" %}
11039   size(4);
11040   ins_encode %{
11041     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
11042     __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
11043   %}
11044   ins_pipe(pipe_class_default);
11045 %}
11046 
11047 // Array size computation.
11048 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
11049   match(Set dst (SubL (CastP2X end) (CastP2X start)));
11050 
11051   format %{ "SUB     $dst, $end, $start \t// array size in bytes" %}
11052   size(4);
11053   ins_encode %{
11054     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
11055     __ subf($dst$$Register, $start$$Register, $end$$Register);
11056   %}
11057   ins_pipe(pipe_class_default);
11058 %}
11059 
11060 // Clear-array with dynamic array-size.
11061 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
11062   match(Set dummy (ClearArray cnt base));
11063   effect(USE_KILL cnt, USE_KILL base, KILL ctr);
11064   ins_cost(MEMORY_REF_COST);
11065 
11066   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11067 
11068   format %{ "ClearArray $cnt, $base" %}
11069   ins_encode %{
11070     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11071     __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0
11072   %}
11073   ins_pipe(pipe_class_default);
11074 %}
11075 
11076 // String_IndexOf for needle of length 1.
11077 //
11078 // Match needle into immediate operands: no loadConP node needed. Saves one
11079 // register and two instructions over string_indexOf_imm1Node.
11080 //
11081 // Assumes register result differs from all input registers.
11082 //
11083 // Preserves registers haystack, haycnt
11084 // Kills     registers tmp1, tmp2
11085 // Defines   registers result
11086 //
11087 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11088 //
11089 // Unfortunately this does not match too often. In many situations the AddP is used
11090 // by several nodes, even several StrIndexOf nodes, breaking the match tree.
11091 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11092                                   immP needleImm, immL offsetImm, immI_1 needlecntImm,
11093                                   iRegIdst tmp1, iRegIdst tmp2,
11094                                   flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11095   predicate(SpecialStringIndexOf);  // type check implicit by parameter type, See Matcher::match_rule_supported
11096   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
11097 
11098   effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1);
11099 
11100   ins_cost(150);
11101   format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
11102             "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11103 
11104   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted
11105   ins_encode %{
11106     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11107     immPOper *needleOper = (immPOper *)$needleImm;
11108     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11109     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
11110 
11111     __ string_indexof_1($result$$Register,
11112                         $haystack$$Register, $haycnt$$Register,
11113                         R0, needle_values->char_at(0),
11114                         $tmp1$$Register, $tmp2$$Register);
11115   %}
11116   ins_pipe(pipe_class_compare);
11117 %}
11118 
11119 // String_IndexOf for needle of length 1.
11120 //
11121 // Special case requires less registers and emits less instructions.
11122 //
11123 // Assumes register result differs from all input registers.
11124 //
11125 // Preserves registers haystack, haycnt
11126 // Kills     registers tmp1, tmp2, needle
11127 // Defines   registers result
11128 //
11129 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11130 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11131                              rscratch2RegP needle, immI_1 needlecntImm,
11132                              iRegIdst tmp1, iRegIdst tmp2,
11133                              flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11134   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11135   effect(USE_KILL needle, /* TDEF needle, */ TEMP_DEF result,
11136          TEMP tmp1, TEMP tmp2);
11137   // Required for EA: check if it is still a type_array.
11138   predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11139             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11140   ins_cost(180);
11141 
11142   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11143 
11144   format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11145             " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11146   ins_encode %{
11147     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11148     Node *ndl = in(operand_index($needle));  // The node that defines needle.
11149     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11150     guarantee(needle_values, "sanity");
11151     if (needle_values != NULL) {
11152       __ string_indexof_1($result$$Register,
11153                           $haystack$$Register, $haycnt$$Register,
11154                           R0, needle_values->char_at(0),
11155                           $tmp1$$Register, $tmp2$$Register);
11156     } else {
11157       __ string_indexof_1($result$$Register,
11158                           $haystack$$Register, $haycnt$$Register,
11159                           $needle$$Register, 0,
11160                           $tmp1$$Register, $tmp2$$Register);
11161     }
11162   %}
11163   ins_pipe(pipe_class_compare);
11164 %}
11165 
11166 // String_IndexOf.
11167 //
11168 // Length of needle as immediate. This saves instruction loading constant needle
11169 // length.
11170 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle
11171 // completely or do it in vector instruction. This should save registers for
11172 // needlecnt and needle.
11173 //
11174 // Assumes register result differs from all input registers.
11175 // Overwrites haycnt, needlecnt.
11176 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11177 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11178                             iRegPsrc needle, uimmI15 needlecntImm,
11179                             iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11180                             flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11181   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11182   effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
11183          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6);
11184   // Required for EA: check if it is still a type_array.
11185   predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11186             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11187   ins_cost(250);
11188 
11189   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11190 
11191   format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11192             " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11193   ins_encode %{
11194     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11195     Node *ndl = in(operand_index($needle));  // The node that defines needle.
11196     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11197 
11198     __ string_indexof($result$$Register,
11199                       $haystack$$Register, $haycnt$$Register,
11200                       $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11201                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11202   %}
11203   ins_pipe(pipe_class_compare);
11204 %}
11205 
11206 // StrIndexOf node.
11207 //
11208 // Assumes register result differs from all input registers.
11209 // Overwrites haycnt, needlecnt.
11210 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11211 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11212                         iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11213                         flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11214   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11215   effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11216          TEMP_DEF result,
11217          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6);
11218   predicate(SpecialStringIndexOf);  // See Matcher::match_rule_supported.
11219   ins_cost(300);
11220 
11221   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11222 
11223   format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11224              " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11225   ins_encode %{
11226     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11227     __ string_indexof($result$$Register,
11228                       $haystack$$Register, $haycnt$$Register,
11229                       $needle$$Register, NULL, $needlecnt$$Register, 0,  // needlecnt not constant.
11230                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11231   %}
11232   ins_pipe(pipe_class_compare);
11233 %}
11234 
11235 // String equals with immediate.
11236 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result,
11237                            iRegPdst tmp1, iRegPdst tmp2,
11238                            flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{
11239   match(Set result (StrEquals (Binary str1 str2) cntImm));
11240   effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2,
11241          KILL cr0, KILL cr6, KILL ctr);
11242   predicate(SpecialStringEquals);  // See Matcher::match_rule_supported.
11243   ins_cost(250);
11244 
11245   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11246 
11247   format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)"
11248             " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %}
11249   ins_encode %{
11250     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11251     __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant,
11252                              $result$$Register, $tmp1$$Register, $tmp2$$Register);
11253   %}
11254   ins_pipe(pipe_class_compare);
11255 %}
11256 
11257 // String equals.
11258 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11259 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result,
11260                        iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5,
11261                        flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11262   match(Set result (StrEquals (Binary str1 str2) cnt));
11263   effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11264          KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11265   predicate(SpecialStringEquals);  // See Matcher::match_rule_supported.
11266   ins_cost(300);
11267 
11268   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11269 
11270   format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result"
11271             " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11272   ins_encode %{
11273     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11274     __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register,
11275                           $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11276   %}
11277   ins_pipe(pipe_class_compare);
11278 %}
11279 
11280 // String compare.
11281 // Char[] pointers are passed in.
11282 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11283 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11284                         iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{
11285   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11286   effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP_DEF result, TEMP tmp, KILL cr0, KILL ctr);
11287   ins_cost(300);
11288 
11289   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11290 
11291   format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result"
11292             " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %}
11293   ins_encode %{
11294     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11295     __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register,
11296                       $result$$Register, $tmp$$Register);
11297   %}
11298   ins_pipe(pipe_class_compare);
11299 %}
11300 
11301 //---------- Min/Max Instructions ---------------------------------------------
11302 
11303 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11304   match(Set dst (MinI src1 src2));
11305   ins_cost(DEFAULT_COST*6);
11306 
11307   expand %{
11308     iRegLdst src1s;
11309     iRegLdst src2s;
11310     iRegLdst diff;
11311     iRegLdst sm;
11312     iRegLdst doz; // difference or zero
11313     convI2L_reg(src1s, src1); // Ensure proper sign extension.
11314     convI2L_reg(src2s, src2); // Ensure proper sign extension.
11315     subL_reg_reg(diff, src2s, src1s);
11316     // Need to consider >=33 bit result, therefore we need signmaskL.
11317     signmask64L_regL(sm, diff);
11318     andL_reg_reg(doz, diff, sm); // <=0
11319     addI_regL_regL(dst, doz, src1s);
11320   %}
11321 %}
11322 
11323 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11324   match(Set dst (MaxI src1 src2));
11325   ins_cost(DEFAULT_COST*6);
11326 
11327   expand %{
11328     iRegLdst src1s;
11329     iRegLdst src2s;
11330     iRegLdst diff;
11331     iRegLdst sm;
11332     iRegLdst doz; // difference or zero
11333     convI2L_reg(src1s, src1); // Ensure proper sign extension.
11334     convI2L_reg(src2s, src2); // Ensure proper sign extension.
11335     subL_reg_reg(diff, src2s, src1s);
11336     // Need to consider >=33 bit result, therefore we need signmaskL.
11337     signmask64L_regL(sm, diff);
11338     andcL_reg_reg(doz, diff, sm); // >=0
11339     addI_regL_regL(dst, doz, src1s);
11340   %}
11341 %}
11342 
11343 //---------- Population Count Instructions ------------------------------------
11344 
11345 // Popcnt for Power7.
11346 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
11347   match(Set dst (PopCountI src));
11348   predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11349   ins_cost(DEFAULT_COST);
11350 
11351   format %{ "POPCNTW $dst, $src" %}
11352   size(4);
11353   ins_encode %{
11354     // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11355     __ popcntw($dst$$Register, $src$$Register);
11356   %}
11357   ins_pipe(pipe_class_default);
11358 %}
11359 
11360 // Popcnt for Power7.
11361 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
11362   predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11363   match(Set dst (PopCountL src));
11364   ins_cost(DEFAULT_COST);
11365 
11366   format %{ "POPCNTD $dst, $src" %}
11367   size(4);
11368   ins_encode %{
11369     // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11370     __ popcntd($dst$$Register, $src$$Register);
11371   %}
11372   ins_pipe(pipe_class_default);
11373 %}
11374 
11375 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
11376   match(Set dst (CountLeadingZerosI src));
11377   predicate(UseCountLeadingZerosInstructionsPPC64);  // See Matcher::match_rule_supported.
11378   ins_cost(DEFAULT_COST);
11379 
11380   format %{ "CNTLZW  $dst, $src" %}
11381   size(4);
11382   ins_encode %{
11383     // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
11384     __ cntlzw($dst$$Register, $src$$Register);
11385   %}
11386   ins_pipe(pipe_class_default);
11387 %}
11388 
11389 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
11390   match(Set dst (CountLeadingZerosL src));
11391   predicate(UseCountLeadingZerosInstructionsPPC64);  // See Matcher::match_rule_supported.
11392   ins_cost(DEFAULT_COST);
11393 
11394   format %{ "CNTLZD  $dst, $src" %}
11395   size(4);
11396   ins_encode %{
11397     // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11398     __ cntlzd($dst$$Register, $src$$Register);
11399   %}
11400   ins_pipe(pipe_class_default);
11401 %}
11402 
11403 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
11404   // no match-rule, false predicate
11405   effect(DEF dst, USE src);
11406   predicate(false);
11407 
11408   format %{ "CNTLZD  $dst, $src" %}
11409   size(4);
11410   ins_encode %{
11411     // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11412     __ cntlzd($dst$$Register, $src$$Register);
11413   %}
11414   ins_pipe(pipe_class_default);
11415 %}
11416 
11417 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
11418   match(Set dst (CountTrailingZerosI src));
11419   predicate(UseCountLeadingZerosInstructionsPPC64);
11420   ins_cost(DEFAULT_COST);
11421 
11422   expand %{
11423     immI16 imm1 %{ (int)-1 %}
11424     immI16 imm2 %{ (int)32 %}
11425     immI_minus1 m1 %{ -1 %}
11426     iRegIdst tmpI1;
11427     iRegIdst tmpI2;
11428     iRegIdst tmpI3;
11429     addI_reg_imm16(tmpI1, src, imm1);
11430     andcI_reg_reg(tmpI2, src, m1, tmpI1);
11431     countLeadingZerosI(tmpI3, tmpI2);
11432     subI_imm16_reg(dst, imm2, tmpI3);
11433   %}
11434 %}
11435 
11436 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
11437   match(Set dst (CountTrailingZerosL src));
11438   predicate(UseCountLeadingZerosInstructionsPPC64);
11439   ins_cost(DEFAULT_COST);
11440 
11441   expand %{
11442     immL16 imm1 %{ (long)-1 %}
11443     immI16 imm2 %{ (int)64 %}
11444     iRegLdst tmpL1;
11445     iRegLdst tmpL2;
11446     iRegIdst tmpL3;
11447     addL_reg_imm16(tmpL1, src, imm1);
11448     andcL_reg_reg(tmpL2, tmpL1, src);
11449     countLeadingZerosL(tmpL3, tmpL2);
11450     subI_imm16_reg(dst, imm2, tmpL3);
11451  %}
11452 %}
11453 
11454 // Expand nodes for byte_reverse_int.
11455 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11456   effect(DEF dst, USE src, USE pos, USE shift);
11457   predicate(false);
11458 
11459   format %{ "INSRWI  $dst, $src, $pos, $shift" %}
11460   size(4);
11461   ins_encode %{
11462     // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11463     __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11464   %}
11465   ins_pipe(pipe_class_default);
11466 %}
11467 
11468 // As insrwi_a, but with USE_DEF.
11469 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11470   effect(USE_DEF dst, USE src, USE pos, USE shift);
11471   predicate(false);
11472 
11473   format %{ "INSRWI  $dst, $src, $pos, $shift" %}
11474   size(4);
11475   ins_encode %{
11476     // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11477     __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11478   %}
11479   ins_pipe(pipe_class_default);
11480 %}
11481 
11482 // Just slightly faster than java implementation.
11483 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
11484   match(Set dst (ReverseBytesI src));
11485   predicate(UseCountLeadingZerosInstructionsPPC64);
11486   ins_cost(DEFAULT_COST);
11487 
11488   expand %{
11489     immI16 imm24 %{ (int) 24 %}
11490     immI16 imm16 %{ (int) 16 %}
11491     immI16  imm8 %{ (int)  8 %}
11492     immI16  imm4 %{ (int)  4 %}
11493     immI16  imm0 %{ (int)  0 %}
11494     iRegLdst tmpI1;
11495     iRegLdst tmpI2;
11496     iRegLdst tmpI3;
11497 
11498     urShiftI_reg_imm(tmpI1, src, imm24);
11499     insrwi_a(dst, tmpI1, imm24, imm8);
11500     urShiftI_reg_imm(tmpI2, src, imm16);
11501     insrwi(dst, tmpI2, imm8, imm16);
11502     urShiftI_reg_imm(tmpI3, src, imm8);
11503     insrwi(dst, tmpI3, imm8, imm8);
11504     insrwi(dst, src, imm0, imm8);
11505   %}
11506 %}
11507 
11508 //---------- Replicate Vector Instructions ------------------------------------
11509 
11510 // Insrdi does replicate if src == dst.
11511 instruct repl32(iRegLdst dst) %{
11512   predicate(false);
11513   effect(USE_DEF dst);
11514 
11515   format %{ "INSRDI  $dst, #0, $dst, #32 \t// replicate" %}
11516   size(4);
11517   ins_encode %{
11518     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11519     __ insrdi($dst$$Register, $dst$$Register, 32, 0);
11520   %}
11521   ins_pipe(pipe_class_default);
11522 %}
11523 
11524 // Insrdi does replicate if src == dst.
11525 instruct repl48(iRegLdst dst) %{
11526   predicate(false);
11527   effect(USE_DEF dst);
11528 
11529   format %{ "INSRDI  $dst, #0, $dst, #48 \t// replicate" %}
11530   size(4);
11531   ins_encode %{
11532     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11533     __ insrdi($dst$$Register, $dst$$Register, 48, 0);
11534   %}
11535   ins_pipe(pipe_class_default);
11536 %}
11537 
11538 // Insrdi does replicate if src == dst.
11539 instruct repl56(iRegLdst dst) %{
11540   predicate(false);
11541   effect(USE_DEF dst);
11542 
11543   format %{ "INSRDI  $dst, #0, $dst, #56 \t// replicate" %}
11544   size(4);
11545   ins_encode %{
11546     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11547     __ insrdi($dst$$Register, $dst$$Register, 56, 0);
11548   %}
11549   ins_pipe(pipe_class_default);
11550 %}
11551 
11552 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11553   match(Set dst (ReplicateB src));
11554   predicate(n->as_Vector()->length() == 8);
11555   expand %{
11556     moveReg(dst, src);
11557     repl56(dst);
11558     repl48(dst);
11559     repl32(dst);
11560   %}
11561 %}
11562 
11563 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
11564   match(Set dst (ReplicateB zero));
11565   predicate(n->as_Vector()->length() == 8);
11566   format %{ "LI      $dst, #0 \t// replicate8B" %}
11567   size(4);
11568   ins_encode %{
11569     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11570     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11571   %}
11572   ins_pipe(pipe_class_default);
11573 %}
11574 
11575 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
11576   match(Set dst (ReplicateB src));
11577   predicate(n->as_Vector()->length() == 8);
11578   format %{ "LI      $dst, #-1 \t// replicate8B" %}
11579   size(4);
11580   ins_encode %{
11581     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11582     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11583   %}
11584   ins_pipe(pipe_class_default);
11585 %}
11586 
11587 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11588   match(Set dst (ReplicateS src));
11589   predicate(n->as_Vector()->length() == 4);
11590   expand %{
11591     moveReg(dst, src);
11592     repl48(dst);
11593     repl32(dst);
11594   %}
11595 %}
11596 
11597 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
11598   match(Set dst (ReplicateS zero));
11599   predicate(n->as_Vector()->length() == 4);
11600   format %{ "LI      $dst, #0 \t// replicate4C" %}
11601   size(4);
11602   ins_encode %{
11603     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11604     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11605   %}
11606   ins_pipe(pipe_class_default);
11607 %}
11608 
11609 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
11610   match(Set dst (ReplicateS src));
11611   predicate(n->as_Vector()->length() == 4);
11612   format %{ "LI      $dst, -1 \t// replicate4C" %}
11613   size(4);
11614   ins_encode %{
11615     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11616     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11617   %}
11618   ins_pipe(pipe_class_default);
11619 %}
11620 
11621 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11622   match(Set dst (ReplicateI src));
11623   predicate(n->as_Vector()->length() == 2);
11624   ins_cost(2 * DEFAULT_COST);
11625   expand %{
11626     moveReg(dst, src);
11627     repl32(dst);
11628   %}
11629 %}
11630 
11631 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
11632   match(Set dst (ReplicateI zero));
11633   predicate(n->as_Vector()->length() == 2);
11634   format %{ "LI      $dst, #0 \t// replicate4C" %}
11635   size(4);
11636   ins_encode %{
11637     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11638     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11639   %}
11640   ins_pipe(pipe_class_default);
11641 %}
11642 
11643 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
11644   match(Set dst (ReplicateI src));
11645   predicate(n->as_Vector()->length() == 2);
11646   format %{ "LI      $dst, -1 \t// replicate4C" %}
11647   size(4);
11648   ins_encode %{
11649     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11650     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11651   %}
11652   ins_pipe(pipe_class_default);
11653 %}
11654 
11655 // Move float to int register via stack, replicate.
11656 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
11657   match(Set dst (ReplicateF src));
11658   predicate(n->as_Vector()->length() == 2);
11659   ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
11660   expand %{
11661     stackSlotL tmpS;
11662     iRegIdst tmpI;
11663     moveF2I_reg_stack(tmpS, src);   // Move float to stack.
11664     moveF2I_stack_reg(tmpI, tmpS);  // Move stack to int reg.
11665     moveReg(dst, tmpI);             // Move int to long reg.
11666     repl32(dst);                    // Replicate bitpattern.
11667   %}
11668 %}
11669 
11670 // Replicate scalar constant to packed float values in Double register
11671 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
11672   match(Set dst (ReplicateF src));
11673   predicate(n->as_Vector()->length() == 2);
11674   ins_cost(5 * DEFAULT_COST);
11675 
11676   format %{ "LD      $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
11677   postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
11678 %}
11679 
11680 // Replicate scalar zero constant to packed float values in Double register
11681 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
11682   match(Set dst (ReplicateF zero));
11683   predicate(n->as_Vector()->length() == 2);
11684 
11685   format %{ "LI      $dst, #0 \t// replicate2F" %}
11686   ins_encode %{
11687     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11688     __ li($dst$$Register, 0x0);
11689   %}
11690   ins_pipe(pipe_class_default);
11691 %}
11692 
11693 
11694 //----------Overflow Math Instructions-----------------------------------------
11695 
11696 // Note that we have to make sure that XER.SO is reset before using overflow instructions.
11697 // Simple Overflow operations can be matched by very few instructions (e.g. addExact: xor, and_, bc).
11698 // Seems like only Long intrinsincs have an advantage. (The only expensive one is OverflowMulL.)
11699 
11700 instruct overflowAddL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
11701   match(Set cr0 (OverflowAddL op1 op2));
11702 
11703   format %{ "add_    $op1, $op2\t# overflow check long" %}
11704   ins_encode %{
11705     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11706     __ li(R0, 0);
11707     __ mtxer(R0); // clear XER.SO
11708     __ addo_(R0, $op1$$Register, $op2$$Register);
11709   %}
11710   ins_pipe(pipe_class_default);
11711 %}
11712 
11713 instruct overflowSubL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
11714   match(Set cr0 (OverflowSubL op1 op2));
11715 
11716   format %{ "subfo_  R0, $op2, $op1\t# overflow check long" %}
11717   ins_encode %{
11718     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11719     __ li(R0, 0);
11720     __ mtxer(R0); // clear XER.SO
11721     __ subfo_(R0, $op2$$Register, $op1$$Register);
11722   %}
11723   ins_pipe(pipe_class_default);
11724 %}
11725 
11726 instruct overflowNegL_reg(flagsRegCR0 cr0, immL_0 zero, iRegLsrc op2) %{
11727   match(Set cr0 (OverflowSubL zero op2));
11728 
11729   format %{ "nego_   R0, $op2\t# overflow check long" %}
11730   ins_encode %{
11731     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11732     __ li(R0, 0);
11733     __ mtxer(R0); // clear XER.SO
11734     __ nego_(R0, $op2$$Register);
11735   %}
11736   ins_pipe(pipe_class_default);
11737 %}
11738 
11739 instruct overflowMulL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
11740   match(Set cr0 (OverflowMulL op1 op2));
11741 
11742   format %{ "mulldo_ R0, $op1, $op2\t# overflow check long" %}
11743   ins_encode %{
11744     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11745     __ li(R0, 0);
11746     __ mtxer(R0); // clear XER.SO
11747     __ mulldo_(R0, $op1$$Register, $op2$$Register);
11748   %}
11749   ins_pipe(pipe_class_default);
11750 %}
11751 
11752 
11753 // ============================================================================
11754 // Safepoint Instruction
11755 
11756 instruct safePoint_poll(iRegPdst poll) %{
11757   match(SafePoint poll);
11758   predicate(LoadPollAddressFromThread);
11759 
11760   // It caused problems to add the effect that r0 is killed, but this
11761   // effect no longer needs to be mentioned, since r0 is not contained
11762   // in a reg_class.
11763 
11764   format %{ "LD      R0, #0, $poll \t// Safepoint poll for GC" %}
11765   size(4);
11766   ins_encode( enc_poll(0x0, poll) );
11767   ins_pipe(pipe_class_default);
11768 %}
11769 
11770 // Safepoint without per-thread support. Load address of page to poll
11771 // as constant.
11772 // Rscratch2RegP is R12.
11773 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
11774 // a seperate node so that the oop map is at the right location.
11775 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
11776   match(SafePoint poll);
11777   predicate(!LoadPollAddressFromThread);
11778 
11779   // It caused problems to add the effect that r0 is killed, but this
11780   // effect no longer needs to be mentioned, since r0 is not contained
11781   // in a reg_class.
11782 
11783   format %{ "LD      R0, #0, R12 \t// Safepoint poll for GC" %}
11784   ins_encode( enc_poll(0x0, poll) );
11785   ins_pipe(pipe_class_default);
11786 %}
11787 
11788 // ============================================================================
11789 // Call Instructions
11790 
11791 // Call Java Static Instruction
11792 
11793 // Schedulable version of call static node.
11794 instruct CallStaticJavaDirect(method meth) %{
11795   match(CallStaticJava);
11796   effect(USE meth);
11797   predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke());
11798   ins_cost(CALL_COST);
11799 
11800   ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11801 
11802   format %{ "CALL,static $meth \t// ==> " %}
11803   size(4);
11804   ins_encode( enc_java_static_call(meth) );
11805   ins_pipe(pipe_class_call);
11806 %}
11807 
11808 // Schedulable version of call static node.
11809 instruct CallStaticJavaDirectHandle(method meth) %{
11810   match(CallStaticJava);
11811   effect(USE meth);
11812   predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
11813   ins_cost(CALL_COST);
11814 
11815   ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11816 
11817   format %{ "CALL,static $meth \t// ==> " %}
11818   ins_encode( enc_java_handle_call(meth) );
11819   ins_pipe(pipe_class_call);
11820 %}
11821 
11822 // Call Java Dynamic Instruction
11823 
11824 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
11825 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
11826 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
11827 // The call destination must still be placed in the constant pool.
11828 instruct CallDynamicJavaDirectSched(method meth) %{
11829   match(CallDynamicJava); // To get all the data fields we need ...
11830   effect(USE meth);
11831   predicate(false);       // ... but never match.
11832 
11833   ins_field_load_ic_hi_node(loadConL_hiNode*);
11834   ins_field_load_ic_node(loadConLNode*);
11835   ins_num_consts(1 /* 1 patchable constant: call destination */);
11836 
11837   format %{ "BL        \t// dynamic $meth ==> " %}
11838   size(4);
11839   ins_encode( enc_java_dynamic_call_sched(meth) );
11840   ins_pipe(pipe_class_call);
11841 %}
11842 
11843 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
11844 // We use postalloc expanded calls if we use inline caches
11845 // and do not update method data.
11846 //
11847 // This instruction has two constants: inline cache (IC) and call destination.
11848 // Loading the inline cache will be postalloc expanded, thus leaving a call with
11849 // one constant.
11850 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
11851   match(CallDynamicJava);
11852   effect(USE meth);
11853   predicate(UseInlineCaches);
11854   ins_cost(CALL_COST);
11855 
11856   ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
11857 
11858   format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
11859   postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
11860 %}
11861 
11862 // Compound version of call dynamic java
11863 // We use postalloc expanded calls if we use inline caches
11864 // and do not update method data.
11865 instruct CallDynamicJavaDirect(method meth) %{
11866   match(CallDynamicJava);
11867   effect(USE meth);
11868   predicate(!UseInlineCaches);
11869   ins_cost(CALL_COST);
11870 
11871   // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
11872   ins_num_consts(4);
11873 
11874   format %{ "CALL,dynamic $meth \t// ==> " %}
11875   ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
11876   ins_pipe(pipe_class_call);
11877 %}
11878 
11879 // Call Runtime Instruction
11880 
11881 instruct CallRuntimeDirect(method meth) %{
11882   match(CallRuntime);
11883   effect(USE meth);
11884   ins_cost(CALL_COST);
11885 
11886   // Enc_java_to_runtime_call needs up to 3 constants: call target,
11887   // env for callee, C-toc.
11888   ins_num_consts(3);
11889 
11890   format %{ "CALL,runtime" %}
11891   ins_encode( enc_java_to_runtime_call(meth) );
11892   ins_pipe(pipe_class_call);
11893 %}
11894 
11895 // Call Leaf
11896 
11897 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
11898 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
11899   effect(DEF dst, USE src);
11900 
11901   ins_num_consts(1);
11902 
11903   format %{ "MTCTR   $src" %}
11904   size(4);
11905   ins_encode( enc_leaf_call_mtctr(src) );
11906   ins_pipe(pipe_class_default);
11907 %}
11908 
11909 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
11910 instruct CallLeafDirect(method meth) %{
11911   match(CallLeaf);   // To get the data all the data fields we need ...
11912   effect(USE meth);
11913   predicate(false);  // but never match.
11914 
11915   format %{ "BCTRL     \t// leaf call $meth ==> " %}
11916   size(4);
11917   ins_encode %{
11918     // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
11919     __ bctrl();
11920   %}
11921   ins_pipe(pipe_class_call);
11922 %}
11923 
11924 // postalloc expand of CallLeafDirect.
11925 // Load adress to call from TOC, then bl to it.
11926 instruct CallLeafDirect_Ex(method meth) %{
11927   match(CallLeaf);
11928   effect(USE meth);
11929   ins_cost(CALL_COST);
11930 
11931   // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
11932   // env for callee, C-toc.
11933   ins_num_consts(3);
11934 
11935   format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
11936   postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11937 %}
11938 
11939 // Call runtime without safepoint - same as CallLeaf.
11940 // postalloc expand of CallLeafNoFPDirect.
11941 // Load adress to call from TOC, then bl to it.
11942 instruct CallLeafNoFPDirect_Ex(method meth) %{
11943   match(CallLeafNoFP);
11944   effect(USE meth);
11945   ins_cost(CALL_COST);
11946 
11947   // Enc_java_to_runtime_call needs up to 3 constants: call target,
11948   // env for callee, C-toc.
11949   ins_num_consts(3);
11950 
11951   format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
11952   postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11953 %}
11954 
11955 // Tail Call; Jump from runtime stub to Java code.
11956 // Also known as an 'interprocedural jump'.
11957 // Target of jump will eventually return to caller.
11958 // TailJump below removes the return address.
11959 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
11960   match(TailCall jump_target method_oop);
11961   ins_cost(CALL_COST);
11962 
11963   format %{ "MTCTR   $jump_target \t// $method_oop holds method oop\n\t"
11964             "BCTR         \t// tail call" %}
11965   size(8);
11966   ins_encode %{
11967     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11968     __ mtctr($jump_target$$Register);
11969     __ bctr();
11970   %}
11971   ins_pipe(pipe_class_call);
11972 %}
11973 
11974 // Return Instruction
11975 instruct Ret() %{
11976   match(Return);
11977   format %{ "BLR      \t// branch to link register" %}
11978   size(4);
11979   ins_encode %{
11980     // TODO: PPC port $archOpcode(ppc64Opcode_blr);
11981     // LR is restored in MachEpilogNode. Just do the RET here.
11982     __ blr();
11983   %}
11984   ins_pipe(pipe_class_default);
11985 %}
11986 
11987 // Tail Jump; remove the return address; jump to target.
11988 // TailCall above leaves the return address around.
11989 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11990 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11991 // "restore" before this instruction (in Epilogue), we need to materialize it
11992 // in %i0.
11993 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
11994   match(TailJump jump_target ex_oop);
11995   ins_cost(CALL_COST);
11996 
11997   format %{ "LD      R4_ARG2 = LR\n\t"
11998             "MTCTR   $jump_target\n\t"
11999             "BCTR     \t// TailJump, exception oop: $ex_oop" %}
12000   size(12);
12001   ins_encode %{
12002     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12003     __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
12004     __ mtctr($jump_target$$Register);
12005     __ bctr();
12006   %}
12007   ins_pipe(pipe_class_call);
12008 %}
12009 
12010 // Create exception oop: created by stack-crawling runtime code.
12011 // Created exception is now available to this handler, and is setup
12012 // just prior to jumping to this handler. No code emitted.
12013 instruct CreateException(rarg1RegP ex_oop) %{
12014   match(Set ex_oop (CreateEx));
12015   ins_cost(0);
12016 
12017   format %{ " -- \t// exception oop; no code emitted" %}
12018   size(0);
12019   ins_encode( /*empty*/ );
12020   ins_pipe(pipe_class_default);
12021 %}
12022 
12023 // Rethrow exception: The exception oop will come in the first
12024 // argument position. Then JUMP (not call) to the rethrow stub code.
12025 instruct RethrowException() %{
12026   match(Rethrow);
12027   ins_cost(CALL_COST);
12028 
12029   format %{ "Jmp     rethrow_stub" %}
12030   ins_encode %{
12031     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12032     cbuf.set_insts_mark();
12033     __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
12034   %}
12035   ins_pipe(pipe_class_call);
12036 %}
12037 
12038 // Die now.
12039 instruct ShouldNotReachHere() %{
12040   match(Halt);
12041   ins_cost(CALL_COST);
12042 
12043   format %{ "ShouldNotReachHere" %}
12044   size(4);
12045   ins_encode %{
12046     // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
12047     __ trap_should_not_reach_here();
12048   %}
12049   ins_pipe(pipe_class_default);
12050 %}
12051 
12052 // This name is KNOWN by the ADLC and cannot be changed.  The ADLC
12053 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
12054 // Get a DEF on threadRegP, no costs, no encoding, use
12055 // 'ins_should_rematerialize(true)' to avoid spilling.
12056 instruct tlsLoadP(threadRegP dst) %{
12057   match(Set dst (ThreadLocal));
12058   ins_cost(0);
12059 
12060   ins_should_rematerialize(true);
12061 
12062   format %{ " -- \t// $dst=Thread::current(), empty" %}
12063   size(0);
12064   ins_encode( /*empty*/ );
12065   ins_pipe(pipe_class_empty);
12066 %}
12067 
12068 //---Some PPC specific nodes---------------------------------------------------
12069 
12070 // Stop a group.
12071 instruct endGroup() %{
12072   ins_cost(0);
12073 
12074   ins_is_nop(true);
12075 
12076   format %{ "End Bundle (ori r1, r1, 0)" %}
12077   size(4);
12078   ins_encode %{
12079     // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
12080     __ endgroup();
12081   %}
12082   ins_pipe(pipe_class_default);
12083 %}
12084 
12085 // Nop instructions
12086 
12087 instruct fxNop() %{
12088   ins_cost(0);
12089 
12090   ins_is_nop(true);
12091 
12092   format %{ "fxNop" %}
12093   size(4);
12094   ins_encode %{
12095     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12096     __ nop();
12097   %}
12098   ins_pipe(pipe_class_default);
12099 %}
12100 
12101 instruct fpNop0() %{
12102   ins_cost(0);
12103 
12104   ins_is_nop(true);
12105 
12106   format %{ "fpNop0" %}
12107   size(4);
12108   ins_encode %{
12109     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12110     __ fpnop0();
12111   %}
12112   ins_pipe(pipe_class_default);
12113 %}
12114 
12115 instruct fpNop1() %{
12116   ins_cost(0);
12117 
12118   ins_is_nop(true);
12119 
12120   format %{ "fpNop1" %}
12121   size(4);
12122   ins_encode %{
12123     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12124     __ fpnop1();
12125   %}
12126   ins_pipe(pipe_class_default);
12127 %}
12128 
12129 instruct brNop0() %{
12130   ins_cost(0);
12131   size(4);
12132   format %{ "brNop0" %}
12133   ins_encode %{
12134     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12135     __ brnop0();
12136   %}
12137   ins_is_nop(true);
12138   ins_pipe(pipe_class_default);
12139 %}
12140 
12141 instruct brNop1() %{
12142   ins_cost(0);
12143 
12144   ins_is_nop(true);
12145 
12146   format %{ "brNop1" %}
12147   size(4);
12148   ins_encode %{
12149     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12150     __ brnop1();
12151   %}
12152   ins_pipe(pipe_class_default);
12153 %}
12154 
12155 instruct brNop2() %{
12156   ins_cost(0);
12157 
12158   ins_is_nop(true);
12159 
12160   format %{ "brNop2" %}
12161   size(4);
12162   ins_encode %{
12163     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12164     __ brnop2();
12165   %}
12166   ins_pipe(pipe_class_default);
12167 %}
12168 
12169 //----------PEEPHOLE RULES-----------------------------------------------------
12170 // These must follow all instruction definitions as they use the names
12171 // defined in the instructions definitions.
12172 //
12173 // peepmatch ( root_instr_name [preceeding_instruction]* );
12174 //
12175 // peepconstraint %{
12176 // (instruction_number.operand_name relational_op instruction_number.operand_name
12177 //  [, ...] );
12178 // // instruction numbers are zero-based using left to right order in peepmatch
12179 //
12180 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12181 // // provide an instruction_number.operand_name for each operand that appears
12182 // // in the replacement instruction's match rule
12183 //
12184 // ---------VM FLAGS---------------------------------------------------------
12185 //
12186 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12187 //
12188 // Each peephole rule is given an identifying number starting with zero and
12189 // increasing by one in the order seen by the parser. An individual peephole
12190 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12191 // on the command-line.
12192 //
12193 // ---------CURRENT LIMITATIONS----------------------------------------------
12194 //
12195 // Only match adjacent instructions in same basic block
12196 // Only equality constraints
12197 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12198 // Only one replacement instruction
12199 //
12200 // ---------EXAMPLE----------------------------------------------------------
12201 //
12202 // // pertinent parts of existing instructions in architecture description
12203 // instruct movI(eRegI dst, eRegI src) %{
12204 //   match(Set dst (CopyI src));
12205 // %}
12206 //
12207 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
12208 //   match(Set dst (AddI dst src));
12209 //   effect(KILL cr);
12210 // %}
12211 //
12212 // // Change (inc mov) to lea
12213 // peephole %{
12214 //   // increment preceeded by register-register move
12215 //   peepmatch ( incI_eReg movI );
12216 //   // require that the destination register of the increment
12217 //   // match the destination register of the move
12218 //   peepconstraint ( 0.dst == 1.dst );
12219 //   // construct a replacement instruction that sets
12220 //   // the destination to ( move's source register + one )
12221 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12222 // %}
12223 //
12224 // Implementation no longer uses movX instructions since
12225 // machine-independent system no longer uses CopyX nodes.
12226 //
12227 // peephole %{
12228 //   peepmatch ( incI_eReg movI );
12229 //   peepconstraint ( 0.dst == 1.dst );
12230 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12231 // %}
12232 //
12233 // peephole %{
12234 //   peepmatch ( decI_eReg movI );
12235 //   peepconstraint ( 0.dst == 1.dst );
12236 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12237 // %}
12238 //
12239 // peephole %{
12240 //   peepmatch ( addI_eReg_imm movI );
12241 //   peepconstraint ( 0.dst == 1.dst );
12242 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12243 // %}
12244 //
12245 // peephole %{
12246 //   peepmatch ( addP_eReg_imm movP );
12247 //   peepconstraint ( 0.dst == 1.dst );
12248 //   peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12249 // %}
12250 
12251 // // Change load of spilled value to only a spill
12252 // instruct storeI(memory mem, eRegI src) %{
12253 //   match(Set mem (StoreI mem src));
12254 // %}
12255 //
12256 // instruct loadI(eRegI dst, memory mem) %{
12257 //   match(Set dst (LoadI mem));
12258 // %}
12259 //
12260 peephole %{
12261   peepmatch ( loadI storeI );
12262   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12263   peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12264 %}
12265 
12266 peephole %{
12267   peepmatch ( loadL storeL );
12268   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12269   peepreplace ( storeL( 1.mem 1.mem 1.src ) );
12270 %}
12271 
12272 peephole %{
12273   peepmatch ( loadP storeP );
12274   peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
12275   peepreplace ( storeP( 1.dst 1.dst 1.src ) );
12276 %}
12277 
12278 //----------SMARTSPILL RULES---------------------------------------------------
12279 // These must follow all instruction definitions as they use the names
12280 // defined in the instructions definitions.