1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP
26 #define CPU_X86_VM_ASSEMBLER_X86_HPP
27
28 #include "asm/register.hpp"
29 #include "vm_version_x86.hpp"
30
31 class BiasedLockingCounters;
32
33 // Contains all the definitions needed for x86 assembly code generation.
34
35 // Calling convention
36 class Argument VALUE_OBJ_CLASS_SPEC {
37 public:
38 enum {
39 #ifdef _LP64
40 #ifdef _WIN64
41 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
42 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
43 #else
44 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
45 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
46 #endif // _WIN64
47 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
48 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
49 #else
50 n_register_parameters = 0 // 0 registers used to pass arguments
51 #endif // _LP64
52 };
53 };
54
55
56 #ifdef _LP64
57 // Symbolically name the register arguments used by the c calling convention.
58 // Windows is different from linux/solaris. So much for standards...
59
60 #ifdef _WIN64
61
62 REGISTER_DECLARATION(Register, c_rarg0, rcx);
63 REGISTER_DECLARATION(Register, c_rarg1, rdx);
64 REGISTER_DECLARATION(Register, c_rarg2, r8);
65 REGISTER_DECLARATION(Register, c_rarg3, r9);
66
67 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
68 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
69 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
70 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
71
72 #else
73
74 REGISTER_DECLARATION(Register, c_rarg0, rdi);
75 REGISTER_DECLARATION(Register, c_rarg1, rsi);
76 REGISTER_DECLARATION(Register, c_rarg2, rdx);
77 REGISTER_DECLARATION(Register, c_rarg3, rcx);
78 REGISTER_DECLARATION(Register, c_rarg4, r8);
79 REGISTER_DECLARATION(Register, c_rarg5, r9);
80
81 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
82 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
83 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
84 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
85 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
86 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
87 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
88 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
89
90 #endif // _WIN64
91
92 // Symbolically name the register arguments used by the Java calling convention.
93 // We have control over the convention for java so we can do what we please.
94 // What pleases us is to offset the java calling convention so that when
95 // we call a suitable jni method the arguments are lined up and we don't
96 // have to do little shuffling. A suitable jni method is non-static and a
97 // small number of arguments (two fewer args on windows)
98 //
99 // |-------------------------------------------------------|
100 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
101 // |-------------------------------------------------------|
102 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
103 // | rdi rsi rdx rcx r8 r9 | solaris/linux
104 // |-------------------------------------------------------|
105 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
106 // |-------------------------------------------------------|
107
108 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
109 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
110 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
111 // Windows runs out of register args here
112 #ifdef _WIN64
113 REGISTER_DECLARATION(Register, j_rarg3, rdi);
114 REGISTER_DECLARATION(Register, j_rarg4, rsi);
115 #else
116 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
117 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
118 #endif /* _WIN64 */
119 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
120
121 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
122 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
123 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
124 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
125 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
126 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
127 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
128 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
129
130 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
131 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
132
133 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
134 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
135
136 #else
137 // rscratch1 will apear in 32bit code that is dead but of course must compile
138 // Using noreg ensures if the dead code is incorrectly live and executed it
139 // will cause an assertion failure
140 #define rscratch1 noreg
141 #define rscratch2 noreg
142
143 #endif // _LP64
144
145 // JSR 292
146 // On x86, the SP does not have to be saved when invoking method handle intrinsics
147 // or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg.
148 REGISTER_DECLARATION(Register, rbp_mh_SP_save, noreg);
149
150 // Address is an abstraction used to represent a memory location
151 // using any of the amd64 addressing modes with one object.
152 //
153 // Note: A register location is represented via a Register, not
154 // via an address for efficiency & simplicity reasons.
155
156 class ArrayAddress;
157
158 class Address VALUE_OBJ_CLASS_SPEC {
159 public:
160 enum ScaleFactor {
161 no_scale = -1,
162 times_1 = 0,
163 times_2 = 1,
164 times_4 = 2,
165 times_8 = 3,
166 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
167 };
168 static ScaleFactor times(int size) {
169 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
170 if (size == 8) return times_8;
171 if (size == 4) return times_4;
172 if (size == 2) return times_2;
173 return times_1;
174 }
175 static int scale_size(ScaleFactor scale) {
176 assert(scale != no_scale, "");
177 assert(((1 << (int)times_1) == 1 &&
178 (1 << (int)times_2) == 2 &&
179 (1 << (int)times_4) == 4 &&
180 (1 << (int)times_8) == 8), "");
181 return (1 << (int)scale);
182 }
183
184 private:
185 Register _base;
186 Register _index;
187 ScaleFactor _scale;
188 int _disp;
189 RelocationHolder _rspec;
190
191 // Easily misused constructors make them private
192 // %%% can we make these go away?
193 NOT_LP64(Address(address loc, RelocationHolder spec);)
194 Address(int disp, address loc, relocInfo::relocType rtype);
195 Address(int disp, address loc, RelocationHolder spec);
196
197 public:
198
199 int disp() { return _disp; }
200 // creation
201 Address()
202 : _base(noreg),
203 _index(noreg),
204 _scale(no_scale),
205 _disp(0) {
206 }
207
208 // No default displacement otherwise Register can be implicitly
209 // converted to 0(Register) which is quite a different animal.
210
211 Address(Register base, int disp)
212 : _base(base),
213 _index(noreg),
214 _scale(no_scale),
215 _disp(disp) {
216 }
217
218 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
219 : _base (base),
220 _index(index),
221 _scale(scale),
222 _disp (disp) {
223 assert(!index->is_valid() == (scale == Address::no_scale),
224 "inconsistent address");
225 }
226
227 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
228 : _base (base),
229 _index(index.register_or_noreg()),
230 _scale(scale),
231 _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
232 if (!index.is_register()) scale = Address::no_scale;
233 assert(!_index->is_valid() == (scale == Address::no_scale),
234 "inconsistent address");
235 }
236
237 Address plus_disp(int disp) const {
238 Address a = (*this);
239 a._disp += disp;
240 return a;
241 }
242 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
243 Address a = (*this);
244 a._disp += disp.constant_or_zero() * scale_size(scale);
245 if (disp.is_register()) {
246 assert(!a.index()->is_valid(), "competing indexes");
247 a._index = disp.as_register();
248 a._scale = scale;
249 }
250 return a;
251 }
252 bool is_same_address(Address a) const {
253 // disregard _rspec
254 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
255 }
256
257 // The following two overloads are used in connection with the
258 // ByteSize type (see sizes.hpp). They simplify the use of
259 // ByteSize'd arguments in assembly code. Note that their equivalent
260 // for the optimized build are the member functions with int disp
261 // argument since ByteSize is mapped to an int type in that case.
262 //
263 // Note: DO NOT introduce similar overloaded functions for WordSize
264 // arguments as in the optimized mode, both ByteSize and WordSize
265 // are mapped to the same type and thus the compiler cannot make a
266 // distinction anymore (=> compiler errors).
267
268 #ifdef ASSERT
269 Address(Register base, ByteSize disp)
270 : _base(base),
271 _index(noreg),
272 _scale(no_scale),
273 _disp(in_bytes(disp)) {
274 }
275
276 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
277 : _base(base),
278 _index(index),
279 _scale(scale),
280 _disp(in_bytes(disp)) {
281 assert(!index->is_valid() == (scale == Address::no_scale),
282 "inconsistent address");
283 }
284
285 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
286 : _base (base),
287 _index(index.register_or_noreg()),
288 _scale(scale),
289 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
290 if (!index.is_register()) scale = Address::no_scale;
291 assert(!_index->is_valid() == (scale == Address::no_scale),
292 "inconsistent address");
293 }
294
295 #endif // ASSERT
296
297 // accessors
298 bool uses(Register reg) const { return _base == reg || _index == reg; }
299 Register base() const { return _base; }
300 Register index() const { return _index; }
301 ScaleFactor scale() const { return _scale; }
302 int disp() const { return _disp; }
303
304 // Convert the raw encoding form into the form expected by the constructor for
305 // Address. An index of 4 (rsp) corresponds to having no index, so convert
306 // that to noreg for the Address constructor.
307 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
308
309 static Address make_array(ArrayAddress);
310
311 private:
312 bool base_needs_rex() const {
313 return _base != noreg && _base->encoding() >= 8;
314 }
315
316 bool index_needs_rex() const {
317 return _index != noreg &&_index->encoding() >= 8;
318 }
319
320 relocInfo::relocType reloc() const { return _rspec.type(); }
321
322 friend class Assembler;
323 friend class MacroAssembler;
324 friend class LIR_Assembler; // base/index/scale/disp
325 };
326
327 //
328 // AddressLiteral has been split out from Address because operands of this type
329 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
330 // the few instructions that need to deal with address literals are unique and the
331 // MacroAssembler does not have to implement every instruction in the Assembler
332 // in order to search for address literals that may need special handling depending
333 // on the instruction and the platform. As small step on the way to merging i486/amd64
334 // directories.
335 //
336 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
337 friend class ArrayAddress;
338 RelocationHolder _rspec;
339 // Typically we use AddressLiterals we want to use their rval
340 // However in some situations we want the lval (effect address) of the item.
341 // We provide a special factory for making those lvals.
342 bool _is_lval;
343
344 // If the target is far we'll need to load the ea of this to
345 // a register to reach it. Otherwise if near we can do rip
346 // relative addressing.
347
348 address _target;
349
350 protected:
351 // creation
352 AddressLiteral()
353 : _is_lval(false),
354 _target(NULL)
355 {}
356
357 public:
358
359
360 AddressLiteral(address target, relocInfo::relocType rtype);
361
362 AddressLiteral(address target, RelocationHolder const& rspec)
363 : _rspec(rspec),
364 _is_lval(false),
365 _target(target)
366 {}
367
368 AddressLiteral addr() {
369 AddressLiteral ret = *this;
370 ret._is_lval = true;
371 return ret;
372 }
373
374
375 private:
376
377 address target() { return _target; }
378 bool is_lval() { return _is_lval; }
379
380 relocInfo::relocType reloc() const { return _rspec.type(); }
381 const RelocationHolder& rspec() const { return _rspec; }
382
383 friend class Assembler;
384 friend class MacroAssembler;
385 friend class Address;
386 friend class LIR_Assembler;
387 };
388
389 // Convience classes
390 class RuntimeAddress: public AddressLiteral {
391
392 public:
393
394 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
395
396 };
397
398 class ExternalAddress: public AddressLiteral {
399 private:
400 static relocInfo::relocType reloc_for_target(address target) {
401 // Sometimes ExternalAddress is used for values which aren't
402 // exactly addresses, like the card table base.
403 // external_word_type can't be used for values in the first page
404 // so just skip the reloc in that case.
405 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
406 }
407
408 public:
409
410 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
411
412 };
413
414 class InternalAddress: public AddressLiteral {
415
416 public:
417
418 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
419
420 };
421
422 // x86 can do array addressing as a single operation since disp can be an absolute
423 // address amd64 can't. We create a class that expresses the concept but does extra
424 // magic on amd64 to get the final result
425
426 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
427 private:
428
429 AddressLiteral _base;
430 Address _index;
431
432 public:
433
434 ArrayAddress() {};
435 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
436 AddressLiteral base() { return _base; }
437 Address index() { return _index; }
438
439 };
440
441 // 64-bit refect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes
442 // See fxsave and xsave(EVEX enabled) documentation for layout
443 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY(2688 / wordSize);
444
445 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
446 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
447 // is what you get. The Assembler is generating code into a CodeBuffer.
448
449 class Assembler : public AbstractAssembler {
450 friend class AbstractAssembler; // for the non-virtual hack
451 friend class LIR_Assembler; // as_Address()
452 friend class StubGenerator;
453
454 public:
455 enum Condition { // The x86 condition codes used for conditional jumps/moves.
456 zero = 0x4,
457 notZero = 0x5,
458 equal = 0x4,
459 notEqual = 0x5,
460 less = 0xc,
461 lessEqual = 0xe,
462 greater = 0xf,
463 greaterEqual = 0xd,
464 below = 0x2,
465 belowEqual = 0x6,
466 above = 0x7,
467 aboveEqual = 0x3,
468 overflow = 0x0,
469 noOverflow = 0x1,
470 carrySet = 0x2,
471 carryClear = 0x3,
472 negative = 0x8,
473 positive = 0x9,
474 parity = 0xa,
475 noParity = 0xb
476 };
477
478 enum Prefix {
479 // segment overrides
480 CS_segment = 0x2e,
481 SS_segment = 0x36,
482 DS_segment = 0x3e,
483 ES_segment = 0x26,
484 FS_segment = 0x64,
485 GS_segment = 0x65,
486
487 REX = 0x40,
488
489 REX_B = 0x41,
490 REX_X = 0x42,
491 REX_XB = 0x43,
492 REX_R = 0x44,
493 REX_RB = 0x45,
494 REX_RX = 0x46,
495 REX_RXB = 0x47,
496
497 REX_W = 0x48,
498
499 REX_WB = 0x49,
500 REX_WX = 0x4A,
501 REX_WXB = 0x4B,
502 REX_WR = 0x4C,
503 REX_WRB = 0x4D,
504 REX_WRX = 0x4E,
505 REX_WRXB = 0x4F,
506
507 VEX_3bytes = 0xC4,
508 VEX_2bytes = 0xC5,
509 EVEX_4bytes = 0x62,
510 Prefix_EMPTY = 0x0
511 };
512
513 enum VexPrefix {
514 VEX_B = 0x20,
515 VEX_X = 0x40,
516 VEX_R = 0x80,
517 VEX_W = 0x80
518 };
519
520 enum ExexPrefix {
521 EVEX_F = 0x04,
522 EVEX_V = 0x08,
523 EVEX_Rb = 0x10,
524 EVEX_X = 0x40,
525 EVEX_Z = 0x80
526 };
527
528 enum VexSimdPrefix {
529 VEX_SIMD_NONE = 0x0,
530 VEX_SIMD_66 = 0x1,
531 VEX_SIMD_F3 = 0x2,
532 VEX_SIMD_F2 = 0x3
533 };
534
535 enum VexOpcode {
536 VEX_OPCODE_NONE = 0x0,
537 VEX_OPCODE_0F = 0x1,
538 VEX_OPCODE_0F_38 = 0x2,
539 VEX_OPCODE_0F_3A = 0x3,
540 VEX_OPCODE_MASK = 0x1F
541 };
542
543 enum AvxVectorLen {
544 AVX_128bit = 0x0,
545 AVX_256bit = 0x1,
546 AVX_512bit = 0x2,
547 AVX_NoVec = 0x4
548 };
549
550 enum EvexTupleType {
551 EVEX_FV = 0,
552 EVEX_HV = 4,
553 EVEX_FVM = 6,
554 EVEX_T1S = 7,
555 EVEX_T1F = 11,
556 EVEX_T2 = 13,
557 EVEX_T4 = 15,
558 EVEX_T8 = 17,
559 EVEX_HVM = 18,
560 EVEX_QVM = 19,
561 EVEX_OVM = 20,
562 EVEX_M128 = 21,
563 EVEX_DUP = 22,
564 EVEX_ETUP = 23
565 };
566
567 enum EvexInputSizeInBits {
568 EVEX_8bit = 0,
569 EVEX_16bit = 1,
570 EVEX_32bit = 2,
571 EVEX_64bit = 3
572 };
573
574 enum WhichOperand {
575 // input to locate_operand, and format code for relocations
576 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
577 disp32_operand = 1, // embedded 32-bit displacement or address
578 call32_operand = 2, // embedded 32-bit self-relative displacement
579 #ifndef _LP64
580 _WhichOperand_limit = 3
581 #else
582 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
583 _WhichOperand_limit = 4
584 #endif
585 };
586
587
588
589 // NOTE: The general philopsophy of the declarations here is that 64bit versions
590 // of instructions are freely declared without the need for wrapping them an ifdef.
591 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
592 // In the .cpp file the implementations are wrapped so that they are dropped out
593 // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL
594 // to the size it was prior to merging up the 32bit and 64bit assemblers.
595 //
596 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
597 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
598
599 private:
600
601 int _evex_encoding;
602 int _input_size_in_bits;
603 int _avx_vector_len;
604 int _tuple_type;
605 bool _is_evex_instruction;
606 bool _legacy_mode_bw;
607 bool _legacy_mode_dq;
608 bool _legacy_mode_vl;
609 bool _legacy_mode_vlbw;
610 bool _instruction_uses_vl;
611
612 // 64bit prefixes
613 int prefix_and_encode(int reg_enc, bool byteinst = false);
614 int prefixq_and_encode(int reg_enc);
615
616 int prefix_and_encode(int dst_enc, int src_enc) {
617 return prefix_and_encode(dst_enc, false, src_enc, false);
618 }
619 int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte);
620 int prefixq_and_encode(int dst_enc, int src_enc);
621
622 void prefix(Register reg);
623 void prefix(Register dst, Register src, Prefix p);
624 void prefix(Register dst, Address adr, Prefix p);
625 void prefix(Address adr);
626 void prefixq(Address adr);
627
628 void prefix(Address adr, Register reg, bool byteinst = false);
629 void prefix(Address adr, XMMRegister reg);
630 void prefixq(Address adr, Register reg);
631 void prefixq(Address adr, XMMRegister reg);
632
633 void prefetch_prefix(Address src);
634
635 void rex_prefix(Address adr, XMMRegister xreg,
636 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
637 int rex_prefix_and_encode(int dst_enc, int src_enc,
638 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
639
640 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w,
641 int nds_enc, VexSimdPrefix pre, VexOpcode opc,
642 int vector_len);
643
644 void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, bool evex_r, bool evex_v,
645 int nds_enc, VexSimdPrefix pre, VexOpcode opc,
646 bool is_extended_context, bool is_merge_context,
647 int vector_len, bool no_mask_reg );
648
649 void vex_prefix(Address adr, int nds_enc, int xreg_enc,
650 VexSimdPrefix pre, VexOpcode opc,
651 bool vex_w, int vector_len,
652 bool legacy_mode = false, bool no_mask_reg = false);
653
654 void vex_prefix(XMMRegister dst, XMMRegister nds, Address src,
655 VexSimdPrefix pre, int vector_len = AVX_128bit,
656 bool no_mask_reg = false, bool legacy_mode = false) {
657 int dst_enc = dst->encoding();
658 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
659 vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector_len, legacy_mode, no_mask_reg);
660 }
661
662 void vex_prefix_q(XMMRegister dst, XMMRegister nds, Address src,
663 VexSimdPrefix pre, int vector_len = AVX_128bit,
664 bool no_mask_reg = false) {
665 int dst_enc = dst->encoding();
666 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
667 vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, true, vector_len, false, no_mask_reg);
668 }
669
670 void vex_prefix_0F38(Register dst, Register nds, Address src, bool no_mask_reg = false) {
671 bool vex_w = false;
672 int vector_len = AVX_128bit;
673 vex_prefix(src, nds->encoding(), dst->encoding(),
674 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w,
675 vector_len, no_mask_reg);
676 }
677
678 void vex_prefix_0F38_legacy(Register dst, Register nds, Address src, bool no_mask_reg = false) {
679 bool vex_w = false;
680 int vector_len = AVX_128bit;
681 vex_prefix(src, nds->encoding(), dst->encoding(),
682 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w,
683 vector_len, true, no_mask_reg);
684 }
685
686 void vex_prefix_0F38_q(Register dst, Register nds, Address src, bool no_mask_reg = false) {
687 bool vex_w = true;
688 int vector_len = AVX_128bit;
689 vex_prefix(src, nds->encoding(), dst->encoding(),
690 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w,
691 vector_len, no_mask_reg);
692 }
693
694 void vex_prefix_0F38_q_legacy(Register dst, Register nds, Address src, bool no_mask_reg = false) {
695 bool vex_w = true;
696 int vector_len = AVX_128bit;
697 vex_prefix(src, nds->encoding(), dst->encoding(),
698 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w,
699 vector_len, true, no_mask_reg);
700 }
701
702 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
703 VexSimdPrefix pre, VexOpcode opc,
704 bool vex_w, int vector_len,
705 bool legacy_mode, bool no_mask_reg);
706
707 int vex_prefix_0F38_and_encode(Register dst, Register nds, Register src, bool no_mask_reg = false) {
708 bool vex_w = false;
709 int vector_len = AVX_128bit;
710 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
711 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector_len,
712 false, no_mask_reg);
713 }
714
715 int vex_prefix_0F38_and_encode_legacy(Register dst, Register nds, Register src, bool no_mask_reg = false) {
716 bool vex_w = false;
717 int vector_len = AVX_128bit;
718 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
719 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector_len,
720 true, no_mask_reg);
721 }
722
723 int vex_prefix_0F38_and_encode_q(Register dst, Register nds, Register src, bool no_mask_reg = false) {
724 bool vex_w = true;
725 int vector_len = AVX_128bit;
726 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
727 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector_len,
728 false, no_mask_reg);
729 }
730
731 int vex_prefix_0F38_and_encode_q_legacy(Register dst, Register nds, Register src, bool no_mask_reg = false) {
732 bool vex_w = true;
733 int vector_len = AVX_128bit;
734 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
735 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector_len,
736 true, no_mask_reg);
737 }
738
739 int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
740 VexSimdPrefix pre, int vector_len = AVX_128bit,
741 VexOpcode opc = VEX_OPCODE_0F, bool legacy_mode = false,
742 bool no_mask_reg = false) {
743 int src_enc = src->encoding();
744 int dst_enc = dst->encoding();
745 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
746 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, false, vector_len, legacy_mode, no_mask_reg);
747 }
748
749 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr,
750 VexSimdPrefix pre, bool no_mask_reg, VexOpcode opc = VEX_OPCODE_0F,
751 bool rex_w = false, int vector_len = AVX_128bit, bool legacy_mode = false);
752
753 void simd_prefix(XMMRegister dst, Address src, VexSimdPrefix pre,
754 bool no_mask_reg, VexOpcode opc = VEX_OPCODE_0F) {
755 simd_prefix(dst, xnoreg, src, pre, no_mask_reg, opc);
756 }
757
758 void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg) {
759 simd_prefix(src, dst, pre, no_mask_reg);
760 }
761 void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src,
762 VexSimdPrefix pre, bool no_mask_reg = false) {
763 bool rex_w = true;
764 simd_prefix(dst, nds, src, pre, no_mask_reg, VEX_OPCODE_0F, rex_w);
765 }
766
767 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
768 VexSimdPrefix pre, bool no_mask_reg,
769 VexOpcode opc = VEX_OPCODE_0F,
770 bool rex_w = false, int vector_len = AVX_128bit,
771 bool legacy_mode = false);
772
773 int kreg_prefix_and_encode(KRegister dst, KRegister nds, KRegister src,
774 VexSimdPrefix pre, bool no_mask_reg,
775 VexOpcode opc = VEX_OPCODE_0F,
776 bool rex_w = false, int vector_len = AVX_128bit);
777
778 int kreg_prefix_and_encode(KRegister dst, KRegister nds, Register src,
779 VexSimdPrefix pre, bool no_mask_reg,
780 VexOpcode opc = VEX_OPCODE_0F,
781 bool rex_w = false, int vector_len = AVX_128bit);
782
783 // Move/convert 32-bit integer value.
784 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src,
785 VexSimdPrefix pre, bool no_mask_reg) {
786 // It is OK to cast from Register to XMMRegister to pass argument here
787 // since only encoding is used in simd_prefix_and_encode() and number of
788 // Gen and Xmm registers are the same.
789 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, no_mask_reg, VEX_OPCODE_0F);
790 }
791 int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre, bool no_mask_reg) {
792 return simd_prefix_and_encode(dst, xnoreg, src, pre, no_mask_reg);
793 }
794 int simd_prefix_and_encode(Register dst, XMMRegister src,
795 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
796 bool no_mask_reg = false) {
797 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, no_mask_reg, opc);
798 }
799
800 // Move/convert 64-bit integer value.
801 int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src,
802 VexSimdPrefix pre, bool no_mask_reg = false) {
803 bool rex_w = true;
804 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, no_mask_reg, VEX_OPCODE_0F, rex_w);
805 }
806 int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre, bool no_mask_reg) {
807 return simd_prefix_and_encode_q(dst, xnoreg, src, pre, no_mask_reg);
808 }
809 int simd_prefix_and_encode_q(Register dst, XMMRegister src,
810 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
811 bool no_mask_reg = false) {
812 bool rex_w = true;
813 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, no_mask_reg, opc, rex_w);
814 }
815
816 // Helper functions for groups of instructions
817 void emit_arith_b(int op1, int op2, Register dst, int imm8);
818
819 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
820 // Force generation of a 4 byte immediate value even if it fits into 8bit
821 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
822 void emit_arith(int op1, int op2, Register dst, Register src);
823
824 void emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg = false, bool legacy_mode = false);
825 void emit_simd_arith_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg = false);
826 void emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg = false, bool legacy_mode = false);
827 void emit_simd_arith_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg = false);
828 void emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg = false);
829 void emit_simd_arith_nonds_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg = false);
830 void emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg = false, bool legacy_mode = false);
831 void emit_simd_arith_nonds_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg = false);
832 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
833 Address src, VexSimdPrefix pre, int vector_len,
834 bool no_mask_reg = false, bool legacy_mode = false);
835 void emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds,
836 Address src, VexSimdPrefix pre, int vector_len,
837 bool no_mask_reg = false);
838 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
839 XMMRegister src, VexSimdPrefix pre, int vector_len,
840 bool no_mask_reg = false, bool legacy_mode = false);
841 void emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds,
842 XMMRegister src, VexSimdPrefix pre, int vector_len,
843 bool no_mask_reg = false);
844
845 bool emit_compressed_disp_byte(int &disp);
846
847 void emit_operand(Register reg,
848 Register base, Register index, Address::ScaleFactor scale,
849 int disp,
850 RelocationHolder const& rspec,
851 int rip_relative_correction = 0);
852
853 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
854
855 // operands that only take the original 32bit registers
856 void emit_operand32(Register reg, Address adr);
857
858 void emit_operand(XMMRegister reg,
859 Register base, Register index, Address::ScaleFactor scale,
860 int disp,
861 RelocationHolder const& rspec);
862
863 void emit_operand(XMMRegister reg, Address adr);
864
865 void emit_operand(MMXRegister reg, Address adr);
866
867 // workaround gcc (3.2.1-7) bug
868 void emit_operand(Address adr, MMXRegister reg);
869
870
871 // Immediate-to-memory forms
872 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
873
874 void emit_farith(int b1, int b2, int i);
875
876
877 protected:
878 #ifdef ASSERT
879 void check_relocation(RelocationHolder const& rspec, int format);
880 #endif
881
882 void emit_data(jint data, relocInfo::relocType rtype, int format);
883 void emit_data(jint data, RelocationHolder const& rspec, int format);
884 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
885 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
886
887 bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
888
889 // These are all easily abused and hence protected
890
891 // 32BIT ONLY SECTION
892 #ifndef _LP64
893 // Make these disappear in 64bit mode since they would never be correct
894 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
895 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
896
897 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
898 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
899
900 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
901 #else
902 // 64BIT ONLY SECTION
903 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
904
905 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
906 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
907
908 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
909 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
910 #endif // _LP64
911
912 // These are unique in that we are ensured by the caller that the 32bit
913 // relative in these instructions will always be able to reach the potentially
914 // 64bit address described by entry. Since they can take a 64bit address they
915 // don't have the 32 suffix like the other instructions in this class.
916
917 void call_literal(address entry, RelocationHolder const& rspec);
918 void jmp_literal(address entry, RelocationHolder const& rspec);
919
920 // Avoid using directly section
921 // Instructions in this section are actually usable by anyone without danger
922 // of failure but have performance issues that are addressed my enhanced
923 // instructions which will do the proper thing base on the particular cpu.
924 // We protect them because we don't trust you...
925
926 // Don't use next inc() and dec() methods directly. INC & DEC instructions
927 // could cause a partial flag stall since they don't set CF flag.
928 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
929 // which call inc() & dec() or add() & sub() in accordance with
930 // the product flag UseIncDec value.
931
932 void decl(Register dst);
933 void decl(Address dst);
934 void decq(Register dst);
935 void decq(Address dst);
936
937 void incl(Register dst);
938 void incl(Address dst);
939 void incq(Register dst);
940 void incq(Address dst);
941
942 // New cpus require use of movsd and movss to avoid partial register stall
943 // when loading from memory. But for old Opteron use movlpd instead of movsd.
944 // The selection is done in MacroAssembler::movdbl() and movflt().
945
946 // Move Scalar Single-Precision Floating-Point Values
947 void movss(XMMRegister dst, Address src);
948 void movss(XMMRegister dst, XMMRegister src);
949 void movss(Address dst, XMMRegister src);
950
951 // Move Scalar Double-Precision Floating-Point Values
952 void movsd(XMMRegister dst, Address src);
953 void movsd(XMMRegister dst, XMMRegister src);
954 void movsd(Address dst, XMMRegister src);
955 void movlpd(XMMRegister dst, Address src);
956
957 // New cpus require use of movaps and movapd to avoid partial register stall
958 // when moving between registers.
959 void movaps(XMMRegister dst, XMMRegister src);
960 void movapd(XMMRegister dst, XMMRegister src);
961
962 // End avoid using directly
963
964
965 // Instruction prefixes
966 void prefix(Prefix p);
967
968 public:
969
970 // Creation
971 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
972 init_attributes();
973 }
974
975 // Decoding
976 static address locate_operand(address inst, WhichOperand which);
977 static address locate_next_instruction(address inst);
978
979 // Utilities
980 static bool is_polling_page_far() NOT_LP64({ return false;});
981 static bool query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
982 int cur_tuple_type, int in_size_in_bits, int cur_encoding);
983
984 // Generic instructions
985 // Does 32bit or 64bit as needed for the platform. In some sense these
986 // belong in macro assembler but there is no need for both varieties to exist
987
988 void init_attributes(void) {
989 _evex_encoding = 0;
990 _input_size_in_bits = 0;
991 _avx_vector_len = AVX_NoVec;
992 _tuple_type = EVEX_ETUP;
993 _is_evex_instruction = false;
994 _legacy_mode_bw = (VM_Version::supports_avx512bw() == false);
995 _legacy_mode_dq = (VM_Version::supports_avx512dq() == false);
996 _legacy_mode_vl = (VM_Version::supports_avx512vl() == false);
997 _legacy_mode_vlbw = (VM_Version::supports_avx512vlbw() == false);
998 _instruction_uses_vl = false;
999 }
1000
1001 void lea(Register dst, Address src);
1002
1003 void mov(Register dst, Register src);
1004
1005 void pusha();
1006 void popa();
1007
1008 void pushf();
1009 void popf();
1010
1011 void push(int32_t imm32);
1012
1013 void push(Register src);
1014
1015 void pop(Register dst);
1016
1017 // These are dummies to prevent surprise implicit conversions to Register
1018 void push(void* v);
1019 void pop(void* v);
1020
1021 // These do register sized moves/scans
1022 void rep_mov();
1023 void rep_stos();
1024 void rep_stosb();
1025 void repne_scan();
1026 #ifdef _LP64
1027 void repne_scanl();
1028 #endif
1029
1030 // Vanilla instructions in lexical order
1031
1032 void adcl(Address dst, int32_t imm32);
1033 void adcl(Address dst, Register src);
1034 void adcl(Register dst, int32_t imm32);
1035 void adcl(Register dst, Address src);
1036 void adcl(Register dst, Register src);
1037
1038 void adcq(Register dst, int32_t imm32);
1039 void adcq(Register dst, Address src);
1040 void adcq(Register dst, Register src);
1041
1042 void addl(Address dst, int32_t imm32);
1043 void addl(Address dst, Register src);
1044 void addl(Register dst, int32_t imm32);
1045 void addl(Register dst, Address src);
1046 void addl(Register dst, Register src);
1047
1048 void addq(Address dst, int32_t imm32);
1049 void addq(Address dst, Register src);
1050 void addq(Register dst, int32_t imm32);
1051 void addq(Register dst, Address src);
1052 void addq(Register dst, Register src);
1053
1054 #ifdef _LP64
1055 //Add Unsigned Integers with Carry Flag
1056 void adcxq(Register dst, Register src);
1057
1058 //Add Unsigned Integers with Overflow Flag
1059 void adoxq(Register dst, Register src);
1060 #endif
1061
1062 void addr_nop_4();
1063 void addr_nop_5();
1064 void addr_nop_7();
1065 void addr_nop_8();
1066
1067 // Add Scalar Double-Precision Floating-Point Values
1068 void addsd(XMMRegister dst, Address src);
1069 void addsd(XMMRegister dst, XMMRegister src);
1070
1071 // Add Scalar Single-Precision Floating-Point Values
1072 void addss(XMMRegister dst, Address src);
1073 void addss(XMMRegister dst, XMMRegister src);
1074
1075 // AES instructions
1076 void aesdec(XMMRegister dst, Address src);
1077 void aesdec(XMMRegister dst, XMMRegister src);
1078 void aesdeclast(XMMRegister dst, Address src);
1079 void aesdeclast(XMMRegister dst, XMMRegister src);
1080 void aesenc(XMMRegister dst, Address src);
1081 void aesenc(XMMRegister dst, XMMRegister src);
1082 void aesenclast(XMMRegister dst, Address src);
1083 void aesenclast(XMMRegister dst, XMMRegister src);
1084
1085
1086 void andl(Address dst, int32_t imm32);
1087 void andl(Register dst, int32_t imm32);
1088 void andl(Register dst, Address src);
1089 void andl(Register dst, Register src);
1090
1091 void andq(Address dst, int32_t imm32);
1092 void andq(Register dst, int32_t imm32);
1093 void andq(Register dst, Address src);
1094 void andq(Register dst, Register src);
1095
1096 // BMI instructions
1097 void andnl(Register dst, Register src1, Register src2);
1098 void andnl(Register dst, Register src1, Address src2);
1099 void andnq(Register dst, Register src1, Register src2);
1100 void andnq(Register dst, Register src1, Address src2);
1101
1102 void blsil(Register dst, Register src);
1103 void blsil(Register dst, Address src);
1104 void blsiq(Register dst, Register src);
1105 void blsiq(Register dst, Address src);
1106
1107 void blsmskl(Register dst, Register src);
1108 void blsmskl(Register dst, Address src);
1109 void blsmskq(Register dst, Register src);
1110 void blsmskq(Register dst, Address src);
1111
1112 void blsrl(Register dst, Register src);
1113 void blsrl(Register dst, Address src);
1114 void blsrq(Register dst, Register src);
1115 void blsrq(Register dst, Address src);
1116
1117 void bsfl(Register dst, Register src);
1118 void bsrl(Register dst, Register src);
1119
1120 #ifdef _LP64
1121 void bsfq(Register dst, Register src);
1122 void bsrq(Register dst, Register src);
1123 #endif
1124
1125 void bswapl(Register reg);
1126
1127 void bswapq(Register reg);
1128
1129 void call(Label& L, relocInfo::relocType rtype);
1130 void call(Register reg); // push pc; pc <- reg
1131 void call(Address adr); // push pc; pc <- adr
1132
1133 void cdql();
1134
1135 void cdqq();
1136
1137 void cld();
1138
1139 void clflush(Address adr);
1140
1141 void cmovl(Condition cc, Register dst, Register src);
1142 void cmovl(Condition cc, Register dst, Address src);
1143
1144 void cmovq(Condition cc, Register dst, Register src);
1145 void cmovq(Condition cc, Register dst, Address src);
1146
1147
1148 void cmpb(Address dst, int imm8);
1149
1150 void cmpl(Address dst, int32_t imm32);
1151
1152 void cmpl(Register dst, int32_t imm32);
1153 void cmpl(Register dst, Register src);
1154 void cmpl(Register dst, Address src);
1155
1156 void cmpq(Address dst, int32_t imm32);
1157 void cmpq(Address dst, Register src);
1158
1159 void cmpq(Register dst, int32_t imm32);
1160 void cmpq(Register dst, Register src);
1161 void cmpq(Register dst, Address src);
1162
1163 // these are dummies used to catch attempting to convert NULL to Register
1164 void cmpl(Register dst, void* junk); // dummy
1165 void cmpq(Register dst, void* junk); // dummy
1166
1167 void cmpw(Address dst, int imm16);
1168
1169 void cmpxchg8 (Address adr);
1170
1171 void cmpxchgb(Register reg, Address adr);
1172 void cmpxchgl(Register reg, Address adr);
1173
1174 void cmpxchgq(Register reg, Address adr);
1175
1176 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1177 void comisd(XMMRegister dst, Address src);
1178 void comisd(XMMRegister dst, XMMRegister src);
1179
1180 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1181 void comiss(XMMRegister dst, Address src);
1182 void comiss(XMMRegister dst, XMMRegister src);
1183
1184 // Identify processor type and features
1185 void cpuid();
1186
1187 // CRC32C
1188 void crc32(Register crc, Register v, int8_t sizeInBytes);
1189 void crc32(Register crc, Address adr, int8_t sizeInBytes);
1190
1191 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
1192 void cvtsd2ss(XMMRegister dst, XMMRegister src);
1193 void cvtsd2ss(XMMRegister dst, Address src);
1194
1195 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
1196 void cvtsi2sdl(XMMRegister dst, Register src);
1197 void cvtsi2sdl(XMMRegister dst, Address src);
1198 void cvtsi2sdq(XMMRegister dst, Register src);
1199 void cvtsi2sdq(XMMRegister dst, Address src);
1200
1201 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
1202 void cvtsi2ssl(XMMRegister dst, Register src);
1203 void cvtsi2ssl(XMMRegister dst, Address src);
1204 void cvtsi2ssq(XMMRegister dst, Register src);
1205 void cvtsi2ssq(XMMRegister dst, Address src);
1206
1207 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
1208 void cvtdq2pd(XMMRegister dst, XMMRegister src);
1209
1210 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
1211 void cvtdq2ps(XMMRegister dst, XMMRegister src);
1212
1213 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
1214 void cvtss2sd(XMMRegister dst, XMMRegister src);
1215 void cvtss2sd(XMMRegister dst, Address src);
1216
1217 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
1218 void cvttsd2sil(Register dst, Address src);
1219 void cvttsd2sil(Register dst, XMMRegister src);
1220 void cvttsd2siq(Register dst, XMMRegister src);
1221
1222 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
1223 void cvttss2sil(Register dst, XMMRegister src);
1224 void cvttss2siq(Register dst, XMMRegister src);
1225
1226 // Divide Scalar Double-Precision Floating-Point Values
1227 void divsd(XMMRegister dst, Address src);
1228 void divsd(XMMRegister dst, XMMRegister src);
1229
1230 // Divide Scalar Single-Precision Floating-Point Values
1231 void divss(XMMRegister dst, Address src);
1232 void divss(XMMRegister dst, XMMRegister src);
1233
1234 void emms();
1235
1236 void fabs();
1237
1238 void fadd(int i);
1239
1240 void fadd_d(Address src);
1241 void fadd_s(Address src);
1242
1243 // "Alternate" versions of x87 instructions place result down in FPU
1244 // stack instead of on TOS
1245
1246 void fadda(int i); // "alternate" fadd
1247 void faddp(int i = 1);
1248
1249 void fchs();
1250
1251 void fcom(int i);
1252
1253 void fcomp(int i = 1);
1254 void fcomp_d(Address src);
1255 void fcomp_s(Address src);
1256
1257 void fcompp();
1258
1259 void fcos();
1260
1261 void fdecstp();
1262
1263 void fdiv(int i);
1264 void fdiv_d(Address src);
1265 void fdivr_s(Address src);
1266 void fdiva(int i); // "alternate" fdiv
1267 void fdivp(int i = 1);
1268
1269 void fdivr(int i);
1270 void fdivr_d(Address src);
1271 void fdiv_s(Address src);
1272
1273 void fdivra(int i); // "alternate" reversed fdiv
1274
1275 void fdivrp(int i = 1);
1276
1277 void ffree(int i = 0);
1278
1279 void fild_d(Address adr);
1280 void fild_s(Address adr);
1281
1282 void fincstp();
1283
1284 void finit();
1285
1286 void fist_s (Address adr);
1287 void fistp_d(Address adr);
1288 void fistp_s(Address adr);
1289
1290 void fld1();
1291
1292 void fld_d(Address adr);
1293 void fld_s(Address adr);
1294 void fld_s(int index);
1295 void fld_x(Address adr); // extended-precision (80-bit) format
1296
1297 void fldcw(Address src);
1298
1299 void fldenv(Address src);
1300
1301 void fldlg2();
1302
1303 void fldln2();
1304
1305 void fldz();
1306
1307 void flog();
1308 void flog10();
1309
1310 void fmul(int i);
1311
1312 void fmul_d(Address src);
1313 void fmul_s(Address src);
1314
1315 void fmula(int i); // "alternate" fmul
1316
1317 void fmulp(int i = 1);
1318
1319 void fnsave(Address dst);
1320
1321 void fnstcw(Address src);
1322
1323 void fnstsw_ax();
1324
1325 void fprem();
1326 void fprem1();
1327
1328 void frstor(Address src);
1329
1330 void fsin();
1331
1332 void fsqrt();
1333
1334 void fst_d(Address adr);
1335 void fst_s(Address adr);
1336
1337 void fstp_d(Address adr);
1338 void fstp_d(int index);
1339 void fstp_s(Address adr);
1340 void fstp_x(Address adr); // extended-precision (80-bit) format
1341
1342 void fsub(int i);
1343 void fsub_d(Address src);
1344 void fsub_s(Address src);
1345
1346 void fsuba(int i); // "alternate" fsub
1347
1348 void fsubp(int i = 1);
1349
1350 void fsubr(int i);
1351 void fsubr_d(Address src);
1352 void fsubr_s(Address src);
1353
1354 void fsubra(int i); // "alternate" reversed fsub
1355
1356 void fsubrp(int i = 1);
1357
1358 void ftan();
1359
1360 void ftst();
1361
1362 void fucomi(int i = 1);
1363 void fucomip(int i = 1);
1364
1365 void fwait();
1366
1367 void fxch(int i = 1);
1368
1369 void fxrstor(Address src);
1370 void xrstor(Address src);
1371
1372 void fxsave(Address dst);
1373 void xsave(Address dst);
1374
1375 void fyl2x();
1376 void frndint();
1377 void f2xm1();
1378 void fldl2e();
1379
1380 void hlt();
1381
1382 void idivl(Register src);
1383 void divl(Register src); // Unsigned division
1384
1385 #ifdef _LP64
1386 void idivq(Register src);
1387 #endif
1388
1389 void imull(Register dst, Register src);
1390 void imull(Register dst, Register src, int value);
1391 void imull(Register dst, Address src);
1392
1393 #ifdef _LP64
1394 void imulq(Register dst, Register src);
1395 void imulq(Register dst, Register src, int value);
1396 void imulq(Register dst, Address src);
1397 #endif
1398
1399 // jcc is the generic conditional branch generator to run-
1400 // time routines, jcc is used for branches to labels. jcc
1401 // takes a branch opcode (cc) and a label (L) and generates
1402 // either a backward branch or a forward branch and links it
1403 // to the label fixup chain. Usage:
1404 //
1405 // Label L; // unbound label
1406 // jcc(cc, L); // forward branch to unbound label
1407 // bind(L); // bind label to the current pc
1408 // jcc(cc, L); // backward branch to bound label
1409 // bind(L); // illegal: a label may be bound only once
1410 //
1411 // Note: The same Label can be used for forward and backward branches
1412 // but it may be bound only once.
1413
1414 void jcc(Condition cc, Label& L, bool maybe_short = true);
1415
1416 // Conditional jump to a 8-bit offset to L.
1417 // WARNING: be very careful using this for forward jumps. If the label is
1418 // not bound within an 8-bit offset of this instruction, a run-time error
1419 // will occur.
1420 void jccb(Condition cc, Label& L);
1421
1422 void jmp(Address entry); // pc <- entry
1423
1424 // Label operations & relative jumps (PPUM Appendix D)
1425 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L
1426
1427 void jmp(Register entry); // pc <- entry
1428
1429 // Unconditional 8-bit offset jump to L.
1430 // WARNING: be very careful using this for forward jumps. If the label is
1431 // not bound within an 8-bit offset of this instruction, a run-time error
1432 // will occur.
1433 void jmpb(Label& L);
1434
1435 void ldmxcsr( Address src );
1436
1437 void leal(Register dst, Address src);
1438
1439 void leaq(Register dst, Address src);
1440
1441 void lfence();
1442
1443 void lock();
1444
1445 void lzcntl(Register dst, Register src);
1446
1447 #ifdef _LP64
1448 void lzcntq(Register dst, Register src);
1449 #endif
1450
1451 enum Membar_mask_bits {
1452 StoreStore = 1 << 3,
1453 LoadStore = 1 << 2,
1454 StoreLoad = 1 << 1,
1455 LoadLoad = 1 << 0
1456 };
1457
1458 // Serializes memory and blows flags
1459 void membar(Membar_mask_bits order_constraint) {
1460 if (os::is_MP()) {
1461 // We only have to handle StoreLoad
1462 if (order_constraint & StoreLoad) {
1463 // All usable chips support "locked" instructions which suffice
1464 // as barriers, and are much faster than the alternative of
1465 // using cpuid instruction. We use here a locked add [esp-C],0.
1466 // This is conveniently otherwise a no-op except for blowing
1467 // flags, and introducing a false dependency on target memory
1468 // location. We can't do anything with flags, but we can avoid
1469 // memory dependencies in the current method by locked-adding
1470 // somewhere else on the stack. Doing [esp+C] will collide with
1471 // something on stack in current method, hence we go for [esp-C].
1472 // It is convenient since it is almost always in data cache, for
1473 // any small C. We need to step back from SP to avoid data
1474 // dependencies with other things on below SP (callee-saves, for
1475 // example). Without a clear way to figure out the minimal safe
1476 // distance from SP, it makes sense to step back the complete
1477 // cache line, as this will also avoid possible second-order effects
1478 // with locked ops against the cache line. Our choice of offset
1479 // is bounded by x86 operand encoding, which should stay within
1480 // [-128; +127] to have the 8-byte displacement encoding.
1481 //
1482 // Any change to this code may need to revisit other places in
1483 // the code where this idiom is used, in particular the
1484 // orderAccess code.
1485
1486 int offset = -VM_Version::L1_line_size();
1487 if (offset < -128) {
1488 offset = -128;
1489 }
1490
1491 lock();
1492 addl(Address(rsp, offset), 0);// Assert the lock# signal here
1493 }
1494 }
1495 }
1496
1497 void mfence();
1498
1499 // Moves
1500
1501 void mov64(Register dst, int64_t imm64);
1502
1503 void movb(Address dst, Register src);
1504 void movb(Address dst, int imm8);
1505 void movb(Register dst, Address src);
1506
1507 void movddup(XMMRegister dst, XMMRegister src);
1508
1509 void kmovql(KRegister dst, KRegister src);
1510 void kmovql(KRegister dst, Register src);
1511 void kmovdl(KRegister dst, Register src);
1512 void kmovwl(KRegister dst, Register src);
1513 void kmovql(Address dst, KRegister src);
1514 void kmovql(KRegister dst, Address src);
1515
1516 void movdl(XMMRegister dst, Register src);
1517 void movdl(Register dst, XMMRegister src);
1518 void movdl(XMMRegister dst, Address src);
1519 void movdl(Address dst, XMMRegister src);
1520
1521 // Move Double Quadword
1522 void movdq(XMMRegister dst, Register src);
1523 void movdq(Register dst, XMMRegister src);
1524
1525 // Move Aligned Double Quadword
1526 void movdqa(XMMRegister dst, XMMRegister src);
1527 void movdqa(XMMRegister dst, Address src);
1528
1529 // Move Unaligned Double Quadword
1530 void movdqu(Address dst, XMMRegister src);
1531 void movdqu(XMMRegister dst, Address src);
1532 void movdqu(XMMRegister dst, XMMRegister src);
1533
1534 // Move Unaligned 256bit Vector
1535 void vmovdqu(Address dst, XMMRegister src);
1536 void vmovdqu(XMMRegister dst, Address src);
1537 void vmovdqu(XMMRegister dst, XMMRegister src);
1538
1539 // Move Unaligned 512bit Vector
1540 void evmovdqul(Address dst, XMMRegister src, int vector_len);
1541 void evmovdqul(XMMRegister dst, Address src, int vector_len);
1542 void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len);
1543 void evmovdquq(Address dst, XMMRegister src, int vector_len);
1544 void evmovdquq(XMMRegister dst, Address src, int vector_len);
1545 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len);
1546
1547 // Move lower 64bit to high 64bit in 128bit register
1548 void movlhps(XMMRegister dst, XMMRegister src);
1549
1550 void movl(Register dst, int32_t imm32);
1551 void movl(Address dst, int32_t imm32);
1552 void movl(Register dst, Register src);
1553 void movl(Register dst, Address src);
1554 void movl(Address dst, Register src);
1555
1556 // These dummies prevent using movl from converting a zero (like NULL) into Register
1557 // by giving the compiler two choices it can't resolve
1558
1559 void movl(Address dst, void* junk);
1560 void movl(Register dst, void* junk);
1561
1562 #ifdef _LP64
1563 void movq(Register dst, Register src);
1564 void movq(Register dst, Address src);
1565 void movq(Address dst, Register src);
1566 #endif
1567
1568 void movq(Address dst, MMXRegister src );
1569 void movq(MMXRegister dst, Address src );
1570
1571 #ifdef _LP64
1572 // These dummies prevent using movq from converting a zero (like NULL) into Register
1573 // by giving the compiler two choices it can't resolve
1574
1575 void movq(Address dst, void* dummy);
1576 void movq(Register dst, void* dummy);
1577 #endif
1578
1579 // Move Quadword
1580 void movq(Address dst, XMMRegister src);
1581 void movq(XMMRegister dst, Address src);
1582
1583 void movsbl(Register dst, Address src);
1584 void movsbl(Register dst, Register src);
1585
1586 #ifdef _LP64
1587 void movsbq(Register dst, Address src);
1588 void movsbq(Register dst, Register src);
1589
1590 // Move signed 32bit immediate to 64bit extending sign
1591 void movslq(Address dst, int32_t imm64);
1592 void movslq(Register dst, int32_t imm64);
1593
1594 void movslq(Register dst, Address src);
1595 void movslq(Register dst, Register src);
1596 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1597 #endif
1598
1599 void movswl(Register dst, Address src);
1600 void movswl(Register dst, Register src);
1601
1602 #ifdef _LP64
1603 void movswq(Register dst, Address src);
1604 void movswq(Register dst, Register src);
1605 #endif
1606
1607 void movw(Address dst, int imm16);
1608 void movw(Register dst, Address src);
1609 void movw(Address dst, Register src);
1610
1611 void movzbl(Register dst, Address src);
1612 void movzbl(Register dst, Register src);
1613
1614 #ifdef _LP64
1615 void movzbq(Register dst, Address src);
1616 void movzbq(Register dst, Register src);
1617 #endif
1618
1619 void movzwl(Register dst, Address src);
1620 void movzwl(Register dst, Register src);
1621
1622 #ifdef _LP64
1623 void movzwq(Register dst, Address src);
1624 void movzwq(Register dst, Register src);
1625 #endif
1626
1627 // Unsigned multiply with RAX destination register
1628 void mull(Address src);
1629 void mull(Register src);
1630
1631 #ifdef _LP64
1632 void mulq(Address src);
1633 void mulq(Register src);
1634 void mulxq(Register dst1, Register dst2, Register src);
1635 #endif
1636
1637 // Multiply Scalar Double-Precision Floating-Point Values
1638 void mulsd(XMMRegister dst, Address src);
1639 void mulsd(XMMRegister dst, XMMRegister src);
1640
1641 // Multiply Scalar Single-Precision Floating-Point Values
1642 void mulss(XMMRegister dst, Address src);
1643 void mulss(XMMRegister dst, XMMRegister src);
1644
1645 void negl(Register dst);
1646
1647 #ifdef _LP64
1648 void negq(Register dst);
1649 #endif
1650
1651 void nop(int i = 1);
1652
1653 void notl(Register dst);
1654
1655 #ifdef _LP64
1656 void notq(Register dst);
1657 #endif
1658
1659 void orl(Address dst, int32_t imm32);
1660 void orl(Register dst, int32_t imm32);
1661 void orl(Register dst, Address src);
1662 void orl(Register dst, Register src);
1663 void orl(Address dst, Register src);
1664
1665 void orq(Address dst, int32_t imm32);
1666 void orq(Register dst, int32_t imm32);
1667 void orq(Register dst, Address src);
1668 void orq(Register dst, Register src);
1669
1670 // Pack with unsigned saturation
1671 void packuswb(XMMRegister dst, XMMRegister src);
1672 void packuswb(XMMRegister dst, Address src);
1673 void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1674
1675 // Pemutation of 64bit words
1676 void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1677 void vpermq(XMMRegister dst, XMMRegister src, int imm8);
1678
1679 void pause();
1680
1681 // SSE4.2 string instructions
1682 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1683 void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1684
1685 // SSE 4.1 extract
1686 void pextrd(Register dst, XMMRegister src, int imm8);
1687 void pextrq(Register dst, XMMRegister src, int imm8);
1688 // SSE 2 extract
1689 void pextrw(Register dst, XMMRegister src, int imm8);
1690
1691 // SSE 4.1 insert
1692 void pinsrd(XMMRegister dst, Register src, int imm8);
1693 void pinsrq(XMMRegister dst, Register src, int imm8);
1694 // SSE 2 insert
1695 void pinsrw(XMMRegister dst, Register src, int imm8);
1696
1697 // SSE4.1 packed move
1698 void pmovzxbw(XMMRegister dst, XMMRegister src);
1699 void pmovzxbw(XMMRegister dst, Address src);
1700
1701 #ifndef _LP64 // no 32bit push/pop on amd64
1702 void popl(Address dst);
1703 #endif
1704
1705 #ifdef _LP64
1706 void popq(Address dst);
1707 #endif
1708
1709 void popcntl(Register dst, Address src);
1710 void popcntl(Register dst, Register src);
1711
1712 #ifdef _LP64
1713 void popcntq(Register dst, Address src);
1714 void popcntq(Register dst, Register src);
1715 #endif
1716
1717 // Prefetches (SSE, SSE2, 3DNOW only)
1718
1719 void prefetchnta(Address src);
1720 void prefetchr(Address src);
1721 void prefetcht0(Address src);
1722 void prefetcht1(Address src);
1723 void prefetcht2(Address src);
1724 void prefetchw(Address src);
1725
1726 // Shuffle Bytes
1727 void pshufb(XMMRegister dst, XMMRegister src);
1728 void pshufb(XMMRegister dst, Address src);
1729
1730 // Shuffle Packed Doublewords
1731 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1732 void pshufd(XMMRegister dst, Address src, int mode);
1733
1734 // Shuffle Packed Low Words
1735 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1736 void pshuflw(XMMRegister dst, Address src, int mode);
1737
1738 // Shift Right by bytes Logical DoubleQuadword Immediate
1739 void psrldq(XMMRegister dst, int shift);
1740 // Shift Left by bytes Logical DoubleQuadword Immediate
1741 void pslldq(XMMRegister dst, int shift);
1742
1743 // Logical Compare 128bit
1744 void ptest(XMMRegister dst, XMMRegister src);
1745 void ptest(XMMRegister dst, Address src);
1746 // Logical Compare 256bit
1747 void vptest(XMMRegister dst, XMMRegister src);
1748 void vptest(XMMRegister dst, Address src);
1749
1750 // Interleave Low Bytes
1751 void punpcklbw(XMMRegister dst, XMMRegister src);
1752 void punpcklbw(XMMRegister dst, Address src);
1753
1754 // Interleave Low Doublewords
1755 void punpckldq(XMMRegister dst, XMMRegister src);
1756 void punpckldq(XMMRegister dst, Address src);
1757
1758 // Interleave Low Quadwords
1759 void punpcklqdq(XMMRegister dst, XMMRegister src);
1760
1761 #ifndef _LP64 // no 32bit push/pop on amd64
1762 void pushl(Address src);
1763 #endif
1764
1765 void pushq(Address src);
1766
1767 void rcll(Register dst, int imm8);
1768
1769 void rclq(Register dst, int imm8);
1770
1771 void rcrq(Register dst, int imm8);
1772
1773 void rcpps(XMMRegister dst, XMMRegister src);
1774
1775 void rcpss(XMMRegister dst, XMMRegister src);
1776
1777 void rdtsc();
1778
1779 void ret(int imm16);
1780
1781 #ifdef _LP64
1782 void rorq(Register dst, int imm8);
1783 void rorxq(Register dst, Register src, int imm8);
1784 #endif
1785
1786 void sahf();
1787
1788 void sarl(Register dst, int imm8);
1789 void sarl(Register dst);
1790
1791 void sarq(Register dst, int imm8);
1792 void sarq(Register dst);
1793
1794 void sbbl(Address dst, int32_t imm32);
1795 void sbbl(Register dst, int32_t imm32);
1796 void sbbl(Register dst, Address src);
1797 void sbbl(Register dst, Register src);
1798
1799 void sbbq(Address dst, int32_t imm32);
1800 void sbbq(Register dst, int32_t imm32);
1801 void sbbq(Register dst, Address src);
1802 void sbbq(Register dst, Register src);
1803
1804 void setb(Condition cc, Register dst);
1805
1806 void shldl(Register dst, Register src);
1807 void shldl(Register dst, Register src, int8_t imm8);
1808
1809 void shll(Register dst, int imm8);
1810 void shll(Register dst);
1811
1812 void shlq(Register dst, int imm8);
1813 void shlq(Register dst);
1814
1815 void shrdl(Register dst, Register src);
1816
1817 void shrl(Register dst, int imm8);
1818 void shrl(Register dst);
1819
1820 void shrq(Register dst, int imm8);
1821 void shrq(Register dst);
1822
1823 void smovl(); // QQQ generic?
1824
1825 // Compute Square Root of Scalar Double-Precision Floating-Point Value
1826 void sqrtsd(XMMRegister dst, Address src);
1827 void sqrtsd(XMMRegister dst, XMMRegister src);
1828
1829 // Compute Square Root of Scalar Single-Precision Floating-Point Value
1830 void sqrtss(XMMRegister dst, Address src);
1831 void sqrtss(XMMRegister dst, XMMRegister src);
1832
1833 void std();
1834
1835 void stmxcsr( Address dst );
1836
1837 void subl(Address dst, int32_t imm32);
1838 void subl(Address dst, Register src);
1839 void subl(Register dst, int32_t imm32);
1840 void subl(Register dst, Address src);
1841 void subl(Register dst, Register src);
1842
1843 void subq(Address dst, int32_t imm32);
1844 void subq(Address dst, Register src);
1845 void subq(Register dst, int32_t imm32);
1846 void subq(Register dst, Address src);
1847 void subq(Register dst, Register src);
1848
1849 // Force generation of a 4 byte immediate value even if it fits into 8bit
1850 void subl_imm32(Register dst, int32_t imm32);
1851 void subq_imm32(Register dst, int32_t imm32);
1852
1853 // Subtract Scalar Double-Precision Floating-Point Values
1854 void subsd(XMMRegister dst, Address src);
1855 void subsd(XMMRegister dst, XMMRegister src);
1856
1857 // Subtract Scalar Single-Precision Floating-Point Values
1858 void subss(XMMRegister dst, Address src);
1859 void subss(XMMRegister dst, XMMRegister src);
1860
1861 void testb(Register dst, int imm8);
1862
1863 void testl(Register dst, int32_t imm32);
1864 void testl(Register dst, Register src);
1865 void testl(Register dst, Address src);
1866
1867 void testq(Register dst, int32_t imm32);
1868 void testq(Register dst, Register src);
1869
1870 // BMI - count trailing zeros
1871 void tzcntl(Register dst, Register src);
1872 void tzcntq(Register dst, Register src);
1873
1874 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1875 void ucomisd(XMMRegister dst, Address src);
1876 void ucomisd(XMMRegister dst, XMMRegister src);
1877
1878 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1879 void ucomiss(XMMRegister dst, Address src);
1880 void ucomiss(XMMRegister dst, XMMRegister src);
1881
1882 void xabort(int8_t imm8);
1883
1884 void xaddl(Address dst, Register src);
1885
1886 void xaddq(Address dst, Register src);
1887
1888 void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none);
1889
1890 void xchgl(Register reg, Address adr);
1891 void xchgl(Register dst, Register src);
1892
1893 void xchgq(Register reg, Address adr);
1894 void xchgq(Register dst, Register src);
1895
1896 void xend();
1897
1898 // Get Value of Extended Control Register
1899 void xgetbv();
1900
1901 void xorl(Register dst, int32_t imm32);
1902 void xorl(Register dst, Address src);
1903 void xorl(Register dst, Register src);
1904
1905 void xorq(Register dst, Address src);
1906 void xorq(Register dst, Register src);
1907
1908 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1909
1910 // AVX 3-operands scalar instructions (encoded with VEX prefix)
1911
1912 void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
1913 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1914 void vaddss(XMMRegister dst, XMMRegister nds, Address src);
1915 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1916 void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
1917 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1918 void vdivss(XMMRegister dst, XMMRegister nds, Address src);
1919 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1920 void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
1921 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1922 void vmulss(XMMRegister dst, XMMRegister nds, Address src);
1923 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1924 void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
1925 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1926 void vsubss(XMMRegister dst, XMMRegister nds, Address src);
1927 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1928
1929
1930 //====================VECTOR ARITHMETIC=====================================
1931
1932 // Add Packed Floating-Point Values
1933 void addpd(XMMRegister dst, XMMRegister src);
1934 void addps(XMMRegister dst, XMMRegister src);
1935 void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1936 void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1937 void vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1938 void vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1939
1940 // Subtract Packed Floating-Point Values
1941 void subpd(XMMRegister dst, XMMRegister src);
1942 void subps(XMMRegister dst, XMMRegister src);
1943 void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1944 void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1945 void vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1946 void vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1947
1948 // Multiply Packed Floating-Point Values
1949 void mulpd(XMMRegister dst, XMMRegister src);
1950 void mulpd(XMMRegister dst, Address src);
1951 void mulps(XMMRegister dst, XMMRegister src);
1952 void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1953 void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1954 void vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1955 void vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1956
1957 // Divide Packed Floating-Point Values
1958 void divpd(XMMRegister dst, XMMRegister src);
1959 void divps(XMMRegister dst, XMMRegister src);
1960 void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1961 void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1962 void vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1963 void vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1964
1965 // Sqrt Packed Floating-Point Values - Double precision only
1966 void vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len);
1967 void vsqrtpd(XMMRegister dst, Address src, int vector_len);
1968
1969 // Bitwise Logical AND of Packed Floating-Point Values
1970 void andpd(XMMRegister dst, XMMRegister src);
1971 void andps(XMMRegister dst, XMMRegister src);
1972 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1973 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1974 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1975 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1976
1977 void unpckhpd(XMMRegister dst, XMMRegister src);
1978 void unpcklpd(XMMRegister dst, XMMRegister src);
1979
1980 // Bitwise Logical XOR of Packed Floating-Point Values
1981 void xorpd(XMMRegister dst, XMMRegister src);
1982 void xorps(XMMRegister dst, XMMRegister src);
1983 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1984 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1985 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1986 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1987
1988 // Add horizontal packed integers
1989 void vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1990 void vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1991 void phaddw(XMMRegister dst, XMMRegister src);
1992 void phaddd(XMMRegister dst, XMMRegister src);
1993
1994 // Add packed integers
1995 void paddb(XMMRegister dst, XMMRegister src);
1996 void paddw(XMMRegister dst, XMMRegister src);
1997 void paddd(XMMRegister dst, XMMRegister src);
1998 void paddq(XMMRegister dst, XMMRegister src);
1999 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2000 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2001 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2002 void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2003 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2004 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2005 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2006 void vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2007
2008 // Sub packed integers
2009 void psubb(XMMRegister dst, XMMRegister src);
2010 void psubw(XMMRegister dst, XMMRegister src);
2011 void psubd(XMMRegister dst, XMMRegister src);
2012 void psubq(XMMRegister dst, XMMRegister src);
2013 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2014 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2015 void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2016 void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2017 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2018 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2019 void vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2020 void vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2021
2022 // Multiply packed integers (only shorts and ints)
2023 void pmullw(XMMRegister dst, XMMRegister src);
2024 void pmulld(XMMRegister dst, XMMRegister src);
2025 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2026 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2027 void vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2028 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2029 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2030 void vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2031
2032 // Shift left packed integers
2033 void psllw(XMMRegister dst, int shift);
2034 void pslld(XMMRegister dst, int shift);
2035 void psllq(XMMRegister dst, int shift);
2036 void psllw(XMMRegister dst, XMMRegister shift);
2037 void pslld(XMMRegister dst, XMMRegister shift);
2038 void psllq(XMMRegister dst, XMMRegister shift);
2039 void vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2040 void vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2041 void vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2042 void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2043 void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2044 void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2045
2046 // Logical shift right packed integers
2047 void psrlw(XMMRegister dst, int shift);
2048 void psrld(XMMRegister dst, int shift);
2049 void psrlq(XMMRegister dst, int shift);
2050 void psrlw(XMMRegister dst, XMMRegister shift);
2051 void psrld(XMMRegister dst, XMMRegister shift);
2052 void psrlq(XMMRegister dst, XMMRegister shift);
2053 void vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2054 void vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2055 void vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2056 void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2057 void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2058 void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2059
2060 // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
2061 void psraw(XMMRegister dst, int shift);
2062 void psrad(XMMRegister dst, int shift);
2063 void psraw(XMMRegister dst, XMMRegister shift);
2064 void psrad(XMMRegister dst, XMMRegister shift);
2065 void vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2066 void vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2067 void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2068 void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2069
2070 // And packed integers
2071 void pand(XMMRegister dst, XMMRegister src);
2072 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2073 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2074
2075 // Andn packed integers
2076 void pandn(XMMRegister dst, XMMRegister src);
2077
2078 // Or packed integers
2079 void por(XMMRegister dst, XMMRegister src);
2080 void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2081 void vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2082
2083 // Xor packed integers
2084 void pxor(XMMRegister dst, XMMRegister src);
2085 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2086 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2087
2088 // Copy low 128bit into high 128bit of YMM registers.
2089 void vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src);
2090 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src);
2091 void vextractf128h(XMMRegister dst, XMMRegister src);
2092 void vextracti128h(XMMRegister dst, XMMRegister src);
2093
2094 // Load/store high 128bit of YMM registers which does not destroy other half.
2095 void vinsertf128h(XMMRegister dst, Address src);
2096 void vinserti128h(XMMRegister dst, Address src);
2097 void vextractf128h(Address dst, XMMRegister src);
2098 void vextracti128h(Address dst, XMMRegister src);
2099
2100 // Copy low 256bit into high 256bit of ZMM registers.
2101 void vinserti64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src);
2102 void vinsertf64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src);
2103 void vextracti64x4h(XMMRegister dst, XMMRegister src);
2104 void vextractf64x4h(XMMRegister dst, XMMRegister src);
2105 void vextractf64x4h(Address dst, XMMRegister src);
2106 void vinsertf64x4h(XMMRegister dst, Address src);
2107
2108 // Copy targeted 128bit segments of the ZMM registers
2109 void vextracti64x2h(XMMRegister dst, XMMRegister src, int value);
2110 void vextractf64x2h(XMMRegister dst, XMMRegister src, int value);
2111 void vextractf32x4h(XMMRegister dst, XMMRegister src, int value);
2112 void vextractf32x4h(Address dst, XMMRegister src, int value);
2113 void vinsertf32x4h(XMMRegister dst, XMMRegister nds, XMMRegister src, int value);
2114 void vinsertf32x4h(XMMRegister dst, Address src, int value);
2115
2116 // duplicate 4-bytes integer data from src into 8 locations in dest
2117 void vpbroadcastd(XMMRegister dst, XMMRegister src);
2118
2119 // duplicate n-bytes integer data from src into vector_len locations in dest
2120 void evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len);
2121 void evpbroadcastb(XMMRegister dst, Address src, int vector_len);
2122 void evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
2123 void evpbroadcastw(XMMRegister dst, Address src, int vector_len);
2124 void evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len);
2125 void evpbroadcastd(XMMRegister dst, Address src, int vector_len);
2126 void evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len);
2127 void evpbroadcastq(XMMRegister dst, Address src, int vector_len);
2128
2129 void evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len);
2130 void evpbroadcastss(XMMRegister dst, Address src, int vector_len);
2131 void evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len);
2132 void evpbroadcastsd(XMMRegister dst, Address src, int vector_len);
2133
2134 void evpbroadcastb(XMMRegister dst, Register src, int vector_len);
2135 void evpbroadcastw(XMMRegister dst, Register src, int vector_len);
2136 void evpbroadcastd(XMMRegister dst, Register src, int vector_len);
2137 void evpbroadcastq(XMMRegister dst, Register src, int vector_len);
2138
2139 // Carry-Less Multiplication Quadword
2140 void pclmulqdq(XMMRegister dst, XMMRegister src, int mask);
2141 void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask);
2142
2143 // AVX instruction which is used to clear upper 128 bits of YMM registers and
2144 // to avoid transaction penalty between AVX and SSE states. There is no
2145 // penalty if legacy SSE instructions are encoded using VEX prefix because
2146 // they always clear upper 128 bits. It should be used before calling
2147 // runtime code and native libraries.
2148 void vzeroupper();
2149
2150 // AVX support for vectorized conditional move (double). The following two instructions used only coupled.
2151 void cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len);
2152 void vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
2153
2154
2155 protected:
2156 // Next instructions require address alignment 16 bytes SSE mode.
2157 // They should be called only from corresponding MacroAssembler instructions.
2158 void andpd(XMMRegister dst, Address src);
2159 void andps(XMMRegister dst, Address src);
2160 void xorpd(XMMRegister dst, Address src);
2161 void xorps(XMMRegister dst, Address src);
2162
2163 };
2164
2165 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP