1 //
   2 // Copyright (c) 2011, 2015, Oracle and/or its affiliates. All rights reserved.
   3 // Copyright 2012, 2015 SAP AG. All rights reserved.
   4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5 //
   6 // This code is free software; you can redistribute it and/or modify it
   7 // under the terms of the GNU General Public License version 2 only, as
   8 // published by the Free Software Foundation.
   9 //
  10 // This code is distributed in the hope that it will be useful, but WITHOUT
  11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13 // version 2 for more details (a copy is included in the LICENSE file that
  14 // accompanied this code).
  15 //
  16 // You should have received a copy of the GNU General Public License version
  17 // 2 along with this work; if not, write to the Free Software Foundation,
  18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19 //
  20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21 // or visit www.oracle.com if you need additional information or have any
  22 // questions.
  23 //
  24 //
  25 
  26 //
  27 // PPC64 Architecture Description File
  28 //
  29 
  30 //----------REGISTER DEFINITION BLOCK------------------------------------------
  31 // This information is used by the matcher and the register allocator to
  32 // describe individual registers and classes of registers within the target
  33 // architecture.
  34 register %{
  35 //----------Architecture Description Register Definitions----------------------
  36 // General Registers
  37 // "reg_def"  name (register save type, C convention save type,
  38 //                  ideal register type, encoding);
  39 //
  40 // Register Save Types:
  41 //
  42 //   NS  = No-Save:     The register allocator assumes that these registers
  43 //                      can be used without saving upon entry to the method, &
  44 //                      that they do not need to be saved at call sites.
  45 //
  46 //   SOC = Save-On-Call: The register allocator assumes that these registers
  47 //                      can be used without saving upon entry to the method,
  48 //                      but that they must be saved at call sites.
  49 //                      These are called "volatiles" on ppc.
  50 //
  51 //   SOE = Save-On-Entry: The register allocator assumes that these registers
  52 //                      must be saved before using them upon entry to the
  53 //                      method, but they do not need to be saved at call
  54 //                      sites.
  55 //                      These are called "nonvolatiles" on ppc.
  56 //
  57 //   AS  = Always-Save:   The register allocator assumes that these registers
  58 //                      must be saved before using them upon entry to the
  59 //                      method, & that they must be saved at call sites.
  60 //
  61 // Ideal Register Type is used to determine how to save & restore a
  62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
  63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
  64 //
  65 // The encoding number is the actual bit-pattern placed into the opcodes.
  66 //
  67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
  68 // Supplement Version 1.7 as of 2003-10-29.
  69 //
  70 // For each 64-bit register we must define two registers: the register
  71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
  72 // e.g. R3_H, which is needed by the allocator, but is not used
  73 // for stores, loads, etc.
  74 
  75 // ----------------------------
  76 // Integer/Long Registers
  77 // ----------------------------
  78 
  79   // PPC64 has 32 64-bit integer registers.
  80 
  81   // types: v = volatile, nv = non-volatile, s = system
  82   reg_def R0   ( SOC, SOC, Op_RegI,  0, R0->as_VMReg()         );  // v   used in prologs
  83   reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
  84   reg_def R1   ( NS,  NS,  Op_RegI,  1, R1->as_VMReg()         );  // s   SP
  85   reg_def R1_H ( NS,  NS,  Op_RegI, 99, R1->as_VMReg()->next() );
  86   reg_def R2   ( SOC, SOC, Op_RegI,  2, R2->as_VMReg()         );  // v   TOC
  87   reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
  88   reg_def R3   ( SOC, SOC, Op_RegI,  3, R3->as_VMReg()         );  // v   iarg1 & iret
  89   reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
  90   reg_def R4   ( SOC, SOC, Op_RegI,  4, R4->as_VMReg()         );  //     iarg2
  91   reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
  92   reg_def R5   ( SOC, SOC, Op_RegI,  5, R5->as_VMReg()         );  // v   iarg3
  93   reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
  94   reg_def R6   ( SOC, SOC, Op_RegI,  6, R6->as_VMReg()         );  // v   iarg4
  95   reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
  96   reg_def R7   ( SOC, SOC, Op_RegI,  7, R7->as_VMReg()         );  // v   iarg5
  97   reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
  98   reg_def R8   ( SOC, SOC, Op_RegI,  8, R8->as_VMReg()         );  // v   iarg6
  99   reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
 100   reg_def R9   ( SOC, SOC, Op_RegI,  9, R9->as_VMReg()         );  // v   iarg7
 101   reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
 102   reg_def R10  ( SOC, SOC, Op_RegI, 10, R10->as_VMReg()        );  // v   iarg8
 103   reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
 104   reg_def R11  ( SOC, SOC, Op_RegI, 11, R11->as_VMReg()        );  // v   ENV / scratch
 105   reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
 106   reg_def R12  ( SOC, SOC, Op_RegI, 12, R12->as_VMReg()        );  // v   scratch
 107   reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
 108   reg_def R13  ( NS,  NS,  Op_RegI, 13, R13->as_VMReg()        );  // s   system thread id
 109   reg_def R13_H( NS,  NS,  Op_RegI, 99, R13->as_VMReg()->next());
 110   reg_def R14  ( SOC, SOE, Op_RegI, 14, R14->as_VMReg()        );  // nv
 111   reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
 112   reg_def R15  ( SOC, SOE, Op_RegI, 15, R15->as_VMReg()        );  // nv
 113   reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
 114   reg_def R16  ( SOC, SOE, Op_RegI, 16, R16->as_VMReg()        );  // nv
 115   reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
 116   reg_def R17  ( SOC, SOE, Op_RegI, 17, R17->as_VMReg()        );  // nv
 117   reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
 118   reg_def R18  ( SOC, SOE, Op_RegI, 18, R18->as_VMReg()        );  // nv
 119   reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
 120   reg_def R19  ( SOC, SOE, Op_RegI, 19, R19->as_VMReg()        );  // nv
 121   reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
 122   reg_def R20  ( SOC, SOE, Op_RegI, 20, R20->as_VMReg()        );  // nv
 123   reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
 124   reg_def R21  ( SOC, SOE, Op_RegI, 21, R21->as_VMReg()        );  // nv
 125   reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
 126   reg_def R22  ( SOC, SOE, Op_RegI, 22, R22->as_VMReg()        );  // nv
 127   reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
 128   reg_def R23  ( SOC, SOE, Op_RegI, 23, R23->as_VMReg()        );  // nv
 129   reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
 130   reg_def R24  ( SOC, SOE, Op_RegI, 24, R24->as_VMReg()        );  // nv
 131   reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
 132   reg_def R25  ( SOC, SOE, Op_RegI, 25, R25->as_VMReg()        );  // nv
 133   reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
 134   reg_def R26  ( SOC, SOE, Op_RegI, 26, R26->as_VMReg()        );  // nv
 135   reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
 136   reg_def R27  ( SOC, SOE, Op_RegI, 27, R27->as_VMReg()        );  // nv
 137   reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
 138   reg_def R28  ( SOC, SOE, Op_RegI, 28, R28->as_VMReg()        );  // nv
 139   reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
 140   reg_def R29  ( SOC, SOE, Op_RegI, 29, R29->as_VMReg()        );  // nv
 141   reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
 142   reg_def R30  ( SOC, SOE, Op_RegI, 30, R30->as_VMReg()        );  // nv
 143   reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
 144   reg_def R31  ( SOC, SOE, Op_RegI, 31, R31->as_VMReg()        );  // nv
 145   reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
 146 
 147 
 148 // ----------------------------
 149 // Float/Double Registers
 150 // ----------------------------
 151 
 152   // Double Registers
 153   // The rules of ADL require that double registers be defined in pairs.
 154   // Each pair must be two 32-bit values, but not necessarily a pair of
 155   // single float registers. In each pair, ADLC-assigned register numbers
 156   // must be adjacent, with the lower number even. Finally, when the
 157   // CPU stores such a register pair to memory, the word associated with
 158   // the lower ADLC-assigned number must be stored to the lower address.
 159 
 160   // PPC64 has 32 64-bit floating-point registers. Each can store a single
 161   // or double precision floating-point value.
 162 
 163   // types: v = volatile, nv = non-volatile, s = system
 164   reg_def F0   ( SOC, SOC, Op_RegF,  0, F0->as_VMReg()         );  // v   scratch
 165   reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
 166   reg_def F1   ( SOC, SOC, Op_RegF,  1, F1->as_VMReg()         );  // v   farg1 & fret
 167   reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
 168   reg_def F2   ( SOC, SOC, Op_RegF,  2, F2->as_VMReg()         );  // v   farg2
 169   reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
 170   reg_def F3   ( SOC, SOC, Op_RegF,  3, F3->as_VMReg()         );  // v   farg3
 171   reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
 172   reg_def F4   ( SOC, SOC, Op_RegF,  4, F4->as_VMReg()         );  // v   farg4
 173   reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
 174   reg_def F5   ( SOC, SOC, Op_RegF,  5, F5->as_VMReg()         );  // v   farg5
 175   reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
 176   reg_def F6   ( SOC, SOC, Op_RegF,  6, F6->as_VMReg()         );  // v   farg6
 177   reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
 178   reg_def F7   ( SOC, SOC, Op_RegF,  7, F7->as_VMReg()         );  // v   farg7
 179   reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
 180   reg_def F8   ( SOC, SOC, Op_RegF,  8, F8->as_VMReg()         );  // v   farg8
 181   reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
 182   reg_def F9   ( SOC, SOC, Op_RegF,  9, F9->as_VMReg()         );  // v   farg9
 183   reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
 184   reg_def F10  ( SOC, SOC, Op_RegF, 10, F10->as_VMReg()        );  // v   farg10
 185   reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
 186   reg_def F11  ( SOC, SOC, Op_RegF, 11, F11->as_VMReg()        );  // v   farg11
 187   reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
 188   reg_def F12  ( SOC, SOC, Op_RegF, 12, F12->as_VMReg()        );  // v   farg12
 189   reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
 190   reg_def F13  ( SOC, SOC, Op_RegF, 13, F13->as_VMReg()        );  // v   farg13
 191   reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
 192   reg_def F14  ( SOC, SOE, Op_RegF, 14, F14->as_VMReg()        );  // nv
 193   reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
 194   reg_def F15  ( SOC, SOE, Op_RegF, 15, F15->as_VMReg()        );  // nv
 195   reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
 196   reg_def F16  ( SOC, SOE, Op_RegF, 16, F16->as_VMReg()        );  // nv
 197   reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
 198   reg_def F17  ( SOC, SOE, Op_RegF, 17, F17->as_VMReg()        );  // nv
 199   reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
 200   reg_def F18  ( SOC, SOE, Op_RegF, 18, F18->as_VMReg()        );  // nv
 201   reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
 202   reg_def F19  ( SOC, SOE, Op_RegF, 19, F19->as_VMReg()        );  // nv
 203   reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
 204   reg_def F20  ( SOC, SOE, Op_RegF, 20, F20->as_VMReg()        );  // nv
 205   reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
 206   reg_def F21  ( SOC, SOE, Op_RegF, 21, F21->as_VMReg()        );  // nv
 207   reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
 208   reg_def F22  ( SOC, SOE, Op_RegF, 22, F22->as_VMReg()        );  // nv
 209   reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
 210   reg_def F23  ( SOC, SOE, Op_RegF, 23, F23->as_VMReg()        );  // nv
 211   reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
 212   reg_def F24  ( SOC, SOE, Op_RegF, 24, F24->as_VMReg()        );  // nv
 213   reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
 214   reg_def F25  ( SOC, SOE, Op_RegF, 25, F25->as_VMReg()        );  // nv
 215   reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
 216   reg_def F26  ( SOC, SOE, Op_RegF, 26, F26->as_VMReg()        );  // nv
 217   reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
 218   reg_def F27  ( SOC, SOE, Op_RegF, 27, F27->as_VMReg()        );  // nv
 219   reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
 220   reg_def F28  ( SOC, SOE, Op_RegF, 28, F28->as_VMReg()        );  // nv
 221   reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
 222   reg_def F29  ( SOC, SOE, Op_RegF, 29, F29->as_VMReg()        );  // nv
 223   reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
 224   reg_def F30  ( SOC, SOE, Op_RegF, 30, F30->as_VMReg()        );  // nv
 225   reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
 226   reg_def F31  ( SOC, SOE, Op_RegF, 31, F31->as_VMReg()        );  // nv
 227   reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
 228 
 229 // ----------------------------
 230 // Special Registers
 231 // ----------------------------
 232 
 233 // Condition Codes Flag Registers
 234 
 235   // PPC64 has 8 condition code "registers" which are all contained
 236   // in the CR register.
 237 
 238   // types: v = volatile, nv = non-volatile, s = system
 239   reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg());  // v
 240   reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg());  // v
 241   reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg());  // nv
 242   reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg());  // nv
 243   reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg());  // nv
 244   reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg());  // v
 245   reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg());  // v
 246   reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg());  // v
 247 
 248   // Special registers of PPC64
 249 
 250   reg_def SR_XER(    SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg());     // v
 251   reg_def SR_LR(     SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg());      // v
 252   reg_def SR_CTR(    SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg());     // v
 253   reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg());  // v
 254   reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
 255   reg_def SR_PPR(    SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg());     // v
 256 
 257 
 258 // ----------------------------
 259 // Specify priority of register selection within phases of register
 260 // allocation. Highest priority is first. A useful heuristic is to
 261 // give registers a low priority when they are required by machine
 262 // instructions, like EAX and EDX on I486, and choose no-save registers
 263 // before save-on-call, & save-on-call before save-on-entry. Registers
 264 // which participate in fixed calling sequences should come last.
 265 // Registers which are used as pairs must fall on an even boundary.
 266 
 267 // It's worth about 1% on SPEC geomean to get this right.
 268 
 269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
 270 // in adGlobals_ppc.hpp which defines the <register>_num values, e.g.
 271 // R3_num. Therefore, R3_num may not be (and in reality is not)
 272 // the same as R3->encoding()! Furthermore, we cannot make any
 273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
 274 // Additionally, the function
 275 //   static enum RC rc_class(OptoReg::Name reg )
 276 // maps a given <register>_num value to its chunk type (except for flags)
 277 // and its current implementation relies on chunk0 and chunk1 having a
 278 // size of 64 each.
 279 
 280 // If you change this allocation class, please have a look at the
 281 // default values for the parameters RoundRobinIntegerRegIntervalStart
 282 // and RoundRobinFloatRegIntervalStart
 283 
 284 alloc_class chunk0 (
 285   // Chunk0 contains *all* 64 integer registers halves.
 286 
 287   // "non-volatile" registers
 288   R14, R14_H,
 289   R15, R15_H,
 290   R17, R17_H,
 291   R18, R18_H,
 292   R19, R19_H,
 293   R20, R20_H,
 294   R21, R21_H,
 295   R22, R22_H,
 296   R23, R23_H,
 297   R24, R24_H,
 298   R25, R25_H,
 299   R26, R26_H,
 300   R27, R27_H,
 301   R28, R28_H,
 302   R29, R29_H,
 303   R30, R30_H,
 304   R31, R31_H,
 305 
 306   // scratch/special registers
 307   R11, R11_H,
 308   R12, R12_H,
 309 
 310   // argument registers
 311   R10, R10_H,
 312   R9,  R9_H,
 313   R8,  R8_H,
 314   R7,  R7_H,
 315   R6,  R6_H,
 316   R5,  R5_H,
 317   R4,  R4_H,
 318   R3,  R3_H,
 319 
 320   // special registers, not available for allocation
 321   R16, R16_H,     // R16_thread
 322   R13, R13_H,     // system thread id
 323   R2,  R2_H,      // may be used for TOC
 324   R1,  R1_H,      // SP
 325   R0,  R0_H       // R0 (scratch)
 326 );
 327 
 328 // If you change this allocation class, please have a look at the
 329 // default values for the parameters RoundRobinIntegerRegIntervalStart
 330 // and RoundRobinFloatRegIntervalStart
 331 
 332 alloc_class chunk1 (
 333   // Chunk1 contains *all* 64 floating-point registers halves.
 334 
 335   // scratch register
 336   F0,  F0_H,
 337 
 338   // argument registers
 339   F13, F13_H,
 340   F12, F12_H,
 341   F11, F11_H,
 342   F10, F10_H,
 343   F9,  F9_H,
 344   F8,  F8_H,
 345   F7,  F7_H,
 346   F6,  F6_H,
 347   F5,  F5_H,
 348   F4,  F4_H,
 349   F3,  F3_H,
 350   F2,  F2_H,
 351   F1,  F1_H,
 352 
 353   // non-volatile registers
 354   F14, F14_H,
 355   F15, F15_H,
 356   F16, F16_H,
 357   F17, F17_H,
 358   F18, F18_H,
 359   F19, F19_H,
 360   F20, F20_H,
 361   F21, F21_H,
 362   F22, F22_H,
 363   F23, F23_H,
 364   F24, F24_H,
 365   F25, F25_H,
 366   F26, F26_H,
 367   F27, F27_H,
 368   F28, F28_H,
 369   F29, F29_H,
 370   F30, F30_H,
 371   F31, F31_H
 372 );
 373 
 374 alloc_class chunk2 (
 375   // Chunk2 contains *all* 8 condition code registers.
 376 
 377   CCR0,
 378   CCR1,
 379   CCR2,
 380   CCR3,
 381   CCR4,
 382   CCR5,
 383   CCR6,
 384   CCR7
 385 );
 386 
 387 alloc_class chunk3 (
 388   // special registers
 389   // These registers are not allocated, but used for nodes generated by postalloc expand.
 390   SR_XER,
 391   SR_LR,
 392   SR_CTR,
 393   SR_VRSAVE,
 394   SR_SPEFSCR,
 395   SR_PPR
 396 );
 397 
 398 //-------Architecture Description Register Classes-----------------------
 399 
 400 // Several register classes are automatically defined based upon
 401 // information in this architecture description.
 402 
 403 // 1) reg_class inline_cache_reg           ( as defined in frame section )
 404 // 2) reg_class compiler_method_oop_reg    ( as defined in frame section )
 405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
 406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
 407 //
 408 
 409 // ----------------------------
 410 // 32 Bit Register Classes
 411 // ----------------------------
 412 
 413 // We specify registers twice, once as read/write, and once read-only.
 414 // We use the read-only registers for source operands. With this, we
 415 // can include preset read only registers in this class, as a hard-coded
 416 // '0'-register. (We used to simulate this on ppc.)
 417 
 418 // 32 bit registers that can be read and written i.e. these registers
 419 // can be dest (or src) of normal instructions.
 420 reg_class bits32_reg_rw(
 421 /*R0*/              // R0
 422 /*R1*/              // SP
 423   R2,               // TOC
 424   R3,
 425   R4,
 426   R5,
 427   R6,
 428   R7,
 429   R8,
 430   R9,
 431   R10,
 432   R11,
 433   R12,
 434 /*R13*/             // system thread id
 435   R14,
 436   R15,
 437 /*R16*/             // R16_thread
 438   R17,
 439   R18,
 440   R19,
 441   R20,
 442   R21,
 443   R22,
 444   R23,
 445   R24,
 446   R25,
 447   R26,
 448   R27,
 449   R28,
 450 /*R29,*/             // global TOC
 451   R30,
 452   R31
 453 );
 454 
 455 // 32 bit registers that can only be read i.e. these registers can
 456 // only be src of all instructions.
 457 reg_class bits32_reg_ro(
 458 /*R0*/              // R0
 459 /*R1*/              // SP
 460   R2                // TOC
 461   R3,
 462   R4,
 463   R5,
 464   R6,
 465   R7,
 466   R8,
 467   R9,
 468   R10,
 469   R11,
 470   R12,
 471 /*R13*/             // system thread id
 472   R14,
 473   R15,
 474 /*R16*/             // R16_thread
 475   R17,
 476   R18,
 477   R19,
 478   R20,
 479   R21,
 480   R22,
 481   R23,
 482   R24,
 483   R25,
 484   R26,
 485   R27,
 486   R28,
 487 /*R29,*/
 488   R30,
 489   R31
 490 );
 491 
 492 reg_class rscratch1_bits32_reg(R11);
 493 reg_class rscratch2_bits32_reg(R12);
 494 reg_class rarg1_bits32_reg(R3);
 495 reg_class rarg2_bits32_reg(R4);
 496 reg_class rarg3_bits32_reg(R5);
 497 reg_class rarg4_bits32_reg(R6);
 498 
 499 // ----------------------------
 500 // 64 Bit Register Classes
 501 // ----------------------------
 502 // 64-bit build means 64-bit pointers means hi/lo pairs
 503 
 504 reg_class rscratch1_bits64_reg(R11_H, R11);
 505 reg_class rscratch2_bits64_reg(R12_H, R12);
 506 reg_class rarg1_bits64_reg(R3_H, R3);
 507 reg_class rarg2_bits64_reg(R4_H, R4);
 508 reg_class rarg3_bits64_reg(R5_H, R5);
 509 reg_class rarg4_bits64_reg(R6_H, R6);
 510 // Thread register, 'written' by tlsLoadP, see there.
 511 reg_class thread_bits64_reg(R16_H, R16);
 512 
 513 reg_class r19_bits64_reg(R19_H, R19);
 514 
 515 // 64 bit registers that can be read and written i.e. these registers
 516 // can be dest (or src) of normal instructions.
 517 reg_class bits64_reg_rw(
 518 /*R0_H,  R0*/     // R0
 519 /*R1_H,  R1*/     // SP
 520   R2_H,  R2,      // TOC
 521   R3_H,  R3,
 522   R4_H,  R4,
 523   R5_H,  R5,
 524   R6_H,  R6,
 525   R7_H,  R7,
 526   R8_H,  R8,
 527   R9_H,  R9,
 528   R10_H, R10,
 529   R11_H, R11,
 530   R12_H, R12,
 531 /*R13_H, R13*/   // system thread id
 532   R14_H, R14,
 533   R15_H, R15,
 534 /*R16_H, R16*/   // R16_thread
 535   R17_H, R17,
 536   R18_H, R18,
 537   R19_H, R19,
 538   R20_H, R20,
 539   R21_H, R21,
 540   R22_H, R22,
 541   R23_H, R23,
 542   R24_H, R24,
 543   R25_H, R25,
 544   R26_H, R26,
 545   R27_H, R27,
 546   R28_H, R28,
 547 /*R29_H, R29,*/
 548   R30_H, R30,
 549   R31_H, R31
 550 );
 551 
 552 // 64 bit registers used excluding r2, r11 and r12
 553 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
 554 // r2, r11 and r12 internally.
 555 reg_class bits64_reg_leaf_call(
 556 /*R0_H,  R0*/     // R0
 557 /*R1_H,  R1*/     // SP
 558 /*R2_H,  R2*/     // TOC
 559   R3_H,  R3,
 560   R4_H,  R4,
 561   R5_H,  R5,
 562   R6_H,  R6,
 563   R7_H,  R7,
 564   R8_H,  R8,
 565   R9_H,  R9,
 566   R10_H, R10,
 567 /*R11_H, R11*/
 568 /*R12_H, R12*/
 569 /*R13_H, R13*/   // system thread id
 570   R14_H, R14,
 571   R15_H, R15,
 572 /*R16_H, R16*/   // R16_thread
 573   R17_H, R17,
 574   R18_H, R18,
 575   R19_H, R19,
 576   R20_H, R20,
 577   R21_H, R21,
 578   R22_H, R22,
 579   R23_H, R23,
 580   R24_H, R24,
 581   R25_H, R25,
 582   R26_H, R26,
 583   R27_H, R27,
 584   R28_H, R28,
 585 /*R29_H, R29,*/
 586   R30_H, R30,
 587   R31_H, R31
 588 );
 589 
 590 // Used to hold the TOC to avoid collisions with expanded DynamicCall
 591 // which uses r19 as inline cache internally and expanded LeafCall which uses
 592 // r2, r11 and r12 internally.
 593 reg_class bits64_constant_table_base(
 594 /*R0_H,  R0*/     // R0
 595 /*R1_H,  R1*/     // SP
 596 /*R2_H,  R2*/     // TOC
 597   R3_H,  R3,
 598   R4_H,  R4,
 599   R5_H,  R5,
 600   R6_H,  R6,
 601   R7_H,  R7,
 602   R8_H,  R8,
 603   R9_H,  R9,
 604   R10_H, R10,
 605 /*R11_H, R11*/
 606 /*R12_H, R12*/
 607 /*R13_H, R13*/   // system thread id
 608   R14_H, R14,
 609   R15_H, R15,
 610 /*R16_H, R16*/   // R16_thread
 611   R17_H, R17,
 612   R18_H, R18,
 613 /*R19_H, R19*/
 614   R20_H, R20,
 615   R21_H, R21,
 616   R22_H, R22,
 617   R23_H, R23,
 618   R24_H, R24,
 619   R25_H, R25,
 620   R26_H, R26,
 621   R27_H, R27,
 622   R28_H, R28,
 623 /*R29_H, R29,*/
 624   R30_H, R30,
 625   R31_H, R31
 626 );
 627 
 628 // 64 bit registers that can only be read i.e. these registers can
 629 // only be src of all instructions.
 630 reg_class bits64_reg_ro(
 631 /*R0_H,  R0*/     // R0
 632   R1_H,  R1,
 633   R2_H,  R2,       // TOC
 634   R3_H,  R3,
 635   R4_H,  R4,
 636   R5_H,  R5,
 637   R6_H,  R6,
 638   R7_H,  R7,
 639   R8_H,  R8,
 640   R9_H,  R9,
 641   R10_H, R10,
 642   R11_H, R11,
 643   R12_H, R12,
 644 /*R13_H, R13*/   // system thread id
 645   R14_H, R14,
 646   R15_H, R15,
 647   R16_H, R16,    // R16_thread
 648   R17_H, R17,
 649   R18_H, R18,
 650   R19_H, R19,
 651   R20_H, R20,
 652   R21_H, R21,
 653   R22_H, R22,
 654   R23_H, R23,
 655   R24_H, R24,
 656   R25_H, R25,
 657   R26_H, R26,
 658   R27_H, R27,
 659   R28_H, R28,
 660 /*R29_H, R29,*/ // TODO: let allocator handle TOC!!
 661   R30_H, R30,
 662   R31_H, R31
 663 );
 664 
 665 
 666 // ----------------------------
 667 // Special Class for Condition Code Flags Register
 668 
 669 reg_class int_flags(
 670 /*CCR0*/             // scratch
 671 /*CCR1*/             // scratch
 672 /*CCR2*/             // nv!
 673 /*CCR3*/             // nv!
 674 /*CCR4*/             // nv!
 675   CCR5,
 676   CCR6,
 677   CCR7
 678 );
 679 
 680 reg_class int_flags_ro(
 681   CCR0,
 682   CCR1,
 683   CCR2,
 684   CCR3,
 685   CCR4,
 686   CCR5,
 687   CCR6,
 688   CCR7
 689 );
 690 
 691 reg_class int_flags_CR0(CCR0);
 692 reg_class int_flags_CR1(CCR1);
 693 reg_class int_flags_CR6(CCR6);
 694 reg_class ctr_reg(SR_CTR);
 695 
 696 // ----------------------------
 697 // Float Register Classes
 698 // ----------------------------
 699 
 700 reg_class flt_reg(
 701 /*F0*/              // scratch
 702   F1,
 703   F2,
 704   F3,
 705   F4,
 706   F5,
 707   F6,
 708   F7,
 709   F8,
 710   F9,
 711   F10,
 712   F11,
 713   F12,
 714   F13,
 715   F14,              // nv!
 716   F15,              // nv!
 717   F16,              // nv!
 718   F17,              // nv!
 719   F18,              // nv!
 720   F19,              // nv!
 721   F20,              // nv!
 722   F21,              // nv!
 723   F22,              // nv!
 724   F23,              // nv!
 725   F24,              // nv!
 726   F25,              // nv!
 727   F26,              // nv!
 728   F27,              // nv!
 729   F28,              // nv!
 730   F29,              // nv!
 731   F30,              // nv!
 732   F31               // nv!
 733 );
 734 
 735 // Double precision float registers have virtual `high halves' that
 736 // are needed by the allocator.
 737 reg_class dbl_reg(
 738 /*F0,  F0_H*/     // scratch
 739   F1,  F1_H,
 740   F2,  F2_H,
 741   F3,  F3_H,
 742   F4,  F4_H,
 743   F5,  F5_H,
 744   F6,  F6_H,
 745   F7,  F7_H,
 746   F8,  F8_H,
 747   F9,  F9_H,
 748   F10, F10_H,
 749   F11, F11_H,
 750   F12, F12_H,
 751   F13, F13_H,
 752   F14, F14_H,    // nv!
 753   F15, F15_H,    // nv!
 754   F16, F16_H,    // nv!
 755   F17, F17_H,    // nv!
 756   F18, F18_H,    // nv!
 757   F19, F19_H,    // nv!
 758   F20, F20_H,    // nv!
 759   F21, F21_H,    // nv!
 760   F22, F22_H,    // nv!
 761   F23, F23_H,    // nv!
 762   F24, F24_H,    // nv!
 763   F25, F25_H,    // nv!
 764   F26, F26_H,    // nv!
 765   F27, F27_H,    // nv!
 766   F28, F28_H,    // nv!
 767   F29, F29_H,    // nv!
 768   F30, F30_H,    // nv!
 769   F31, F31_H     // nv!
 770 );
 771 
 772  %}
 773 
 774 //----------DEFINITION BLOCK---------------------------------------------------
 775 // Define name --> value mappings to inform the ADLC of an integer valued name
 776 // Current support includes integer values in the range [0, 0x7FFFFFFF]
 777 // Format:
 778 //        int_def  <name>         ( <int_value>, <expression>);
 779 // Generated Code in ad_<arch>.hpp
 780 //        #define  <name>   (<expression>)
 781 //        // value == <int_value>
 782 // Generated code in ad_<arch>.cpp adlc_verification()
 783 //        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
 784 //
 785 definitions %{
 786   // The default cost (of an ALU instruction).
 787   int_def DEFAULT_COST_LOW        (     30,      30);
 788   int_def DEFAULT_COST            (    100,     100);
 789   int_def HUGE_COST               (1000000, 1000000);
 790 
 791   // Memory refs
 792   int_def MEMORY_REF_COST_LOW     (    200, DEFAULT_COST * 2);
 793   int_def MEMORY_REF_COST         (    300, DEFAULT_COST * 3);
 794 
 795   // Branches are even more expensive.
 796   int_def BRANCH_COST             (    900, DEFAULT_COST * 9);
 797   int_def CALL_COST               (   1300, DEFAULT_COST * 13);
 798 %}
 799 
 800 
 801 //----------SOURCE BLOCK-------------------------------------------------------
 802 // This is a block of C++ code which provides values, functions, and
 803 // definitions necessary in the rest of the architecture description.
 804 source_hpp %{
 805   // Header information of the source block.
 806   // Method declarations/definitions which are used outside
 807   // the ad-scope can conveniently be defined here.
 808   //
 809   // To keep related declarations/definitions/uses close together,
 810   // we switch between source %{ }% and source_hpp %{ }% freely as needed.
 811 
 812   // Returns true if Node n is followed by a MemBar node that
 813   // will do an acquire. If so, this node must not do the acquire
 814   // operation.
 815   bool followed_by_acquire(const Node *n);
 816 %}
 817 
 818 source %{
 819 
 820 // Optimize load-acquire.
 821 //
 822 // Check if acquire is unnecessary due to following operation that does
 823 // acquire anyways.
 824 // Walk the pattern:
 825 //
 826 //      n: Load.acq
 827 //           |
 828 //      MemBarAcquire
 829 //       |         |
 830 //  Proj(ctrl)  Proj(mem)
 831 //       |         |
 832 //   MemBarRelease/Volatile
 833 //
 834 bool followed_by_acquire(const Node *load) {
 835   assert(load->is_Load(), "So far implemented only for loads.");
 836 
 837   // Find MemBarAcquire.
 838   const Node *mba = NULL;
 839   for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
 840     const Node *out = load->fast_out(i);
 841     if (out->Opcode() == Op_MemBarAcquire) {
 842       if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
 843       mba = out;
 844       break;
 845     }
 846   }
 847   if (!mba) return false;
 848 
 849   // Find following MemBar node.
 850   //
 851   // The following node must be reachable by control AND memory
 852   // edge to assure no other operations are in between the two nodes.
 853   //
 854   // So first get the Proj node, mem_proj, to use it to iterate forward.
 855   Node *mem_proj = NULL;
 856   for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
 857     mem_proj = mba->fast_out(i);      // Throw out-of-bounds if proj not found
 858     assert(mem_proj->is_Proj(), "only projections here");
 859     ProjNode *proj = mem_proj->as_Proj();
 860     if (proj->_con == TypeFunc::Memory &&
 861         !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
 862       break;
 863   }
 864   assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
 865 
 866   // Search MemBar behind Proj. If there are other memory operations
 867   // behind the Proj we lost.
 868   for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
 869     Node *x = mem_proj->fast_out(j);
 870     // Proj might have an edge to a store or load node which precedes the membar.
 871     if (x->is_Mem()) return false;
 872 
 873     // On PPC64 release and volatile are implemented by an instruction
 874     // that also has acquire semantics. I.e. there is no need for an
 875     // acquire before these.
 876     int xop = x->Opcode();
 877     if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
 878       // Make sure we're not missing Call/Phi/MergeMem by checking
 879       // control edges. The control edge must directly lead back
 880       // to the MemBarAcquire
 881       Node *ctrl_proj = x->in(0);
 882       if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
 883         return true;
 884       }
 885     }
 886   }
 887 
 888   return false;
 889 }
 890 
 891 #define __ _masm.
 892 
 893 // Tertiary op of a LoadP or StoreP encoding.
 894 #define REGP_OP true
 895 
 896 // ****************************************************************************
 897 
 898 // REQUIRED FUNCTIONALITY
 899 
 900 // !!!!! Special hack to get all type of calls to specify the byte offset
 901 //       from the start of the call to the point where the return address
 902 //       will point.
 903 
 904 // PPC port: Removed use of lazy constant construct.
 905 
 906 int MachCallStaticJavaNode::ret_addr_offset() {
 907   // It's only a single branch-and-link instruction.
 908   return 4;
 909 }
 910 
 911 int MachCallDynamicJavaNode::ret_addr_offset() {
 912   // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
 913   // postalloc expanded calls if we use inline caches and do not update method data.
 914   if (UseInlineCaches)
 915     return 4;
 916 
 917   int vtable_index = this->_vtable_index;
 918   if (vtable_index < 0) {
 919     // Must be invalid_vtable_index, not nonvirtual_vtable_index.
 920     assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
 921     return 12;
 922   } else {
 923     assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
 924     return 24;
 925   }
 926 }
 927 
 928 int MachCallRuntimeNode::ret_addr_offset() {
 929 #if defined(ABI_ELFv2)
 930   return 28;
 931 #else
 932   return 40;
 933 #endif
 934 }
 935 
 936 //=============================================================================
 937 
 938 // condition code conversions
 939 
 940 static int cc_to_boint(int cc) {
 941   return Assembler::bcondCRbiIs0 | (cc & 8);
 942 }
 943 
 944 static int cc_to_inverse_boint(int cc) {
 945   return Assembler::bcondCRbiIs0 | (8-(cc & 8));
 946 }
 947 
 948 static int cc_to_biint(int cc, int flags_reg) {
 949   return (flags_reg << 2) | (cc & 3);
 950 }
 951 
 952 //=============================================================================
 953 
 954 // Compute padding required for nodes which need alignment. The padding
 955 // is the number of bytes (not instructions) which will be inserted before
 956 // the instruction. The padding must match the size of a NOP instruction.
 957 
 958 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
 959   return (3*4-current_offset)&31;
 960 }
 961 
 962 int string_indexOf_imm1Node::compute_padding(int current_offset) const {
 963   return (2*4-current_offset)&31;
 964 }
 965 
 966 int string_indexOf_immNode::compute_padding(int current_offset) const {
 967   return (3*4-current_offset)&31;
 968 }
 969 
 970 int string_indexOfNode::compute_padding(int current_offset) const {
 971   return (1*4-current_offset)&31;
 972 }
 973 
 974 int string_compareNode::compute_padding(int current_offset) const {
 975   return (4*4-current_offset)&31;
 976 }
 977 
 978 int string_equals_immNode::compute_padding(int current_offset) const {
 979   if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled).
 980   return (2*4-current_offset)&31;
 981 }
 982 
 983 int string_equalsNode::compute_padding(int current_offset) const {
 984   return (7*4-current_offset)&31;
 985 }
 986 
 987 int inlineCallClearArrayNode::compute_padding(int current_offset) const {
 988   return (2*4-current_offset)&31;
 989 }
 990 
 991 //=============================================================================
 992 
 993 // Indicate if the safepoint node needs the polling page as an input.
 994 bool SafePointNode::needs_polling_address_input() {
 995   // The address is loaded from thread by a seperate node.
 996   return true;
 997 }
 998 
 999 //=============================================================================
1000 
1001 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1002 void emit_break(CodeBuffer &cbuf) {
1003   MacroAssembler _masm(&cbuf);
1004   __ illtrap();
1005 }
1006 
1007 #ifndef PRODUCT
1008 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1009   st->print("BREAKPOINT");
1010 }
1011 #endif
1012 
1013 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1014   emit_break(cbuf);
1015 }
1016 
1017 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1018   return MachNode::size(ra_);
1019 }
1020 
1021 //=============================================================================
1022 
1023 void emit_nop(CodeBuffer &cbuf) {
1024   MacroAssembler _masm(&cbuf);
1025   __ nop();
1026 }
1027 
1028 static inline void emit_long(CodeBuffer &cbuf, int value) {
1029   *((int*)(cbuf.insts_end())) = value;
1030   cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1031 }
1032 
1033 //=============================================================================
1034 
1035 %} // interrupt source
1036 
1037 source_hpp %{ // Header information of the source block.
1038 
1039 //--------------------------------------------------------------
1040 //---<  Used for optimization in Compile::Shorten_branches  >---
1041 //--------------------------------------------------------------
1042 
1043 const uint trampoline_stub_size     =  6 * BytesPerInstWord;
1044 
1045 class CallStubImpl {
1046 
1047  public:
1048 
1049   // Emit call stub, compiled java to interpreter.
1050   static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset);
1051 
1052   // Size of call trampoline stub.
1053   // This doesn't need to be accurate to the byte, but it
1054   // must be larger than or equal to the real size of the stub.
1055   static uint size_call_trampoline() {
1056     return trampoline_stub_size;
1057   }
1058 
1059   // number of relocations needed by a call trampoline stub
1060   static uint reloc_call_trampoline() {
1061     return 5;
1062   }
1063 
1064 };
1065 
1066 %} // end source_hpp
1067 
1068 source %{
1069 
1070 // Emit a trampoline stub for a call to a target which is too far away.
1071 //
1072 // code sequences:
1073 //
1074 // call-site:
1075 //   branch-and-link to <destination> or <trampoline stub>
1076 //
1077 // Related trampoline stub for this call-site in the stub section:
1078 //   load the call target from the constant pool
1079 //   branch via CTR (LR/link still points to the call-site above)
1080 
1081 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1082   // Start the stub.
1083   address stub = __ start_a_stub(Compile::MAX_stubs_size/2);
1084   if (stub == NULL) {
1085     ciEnv::current()->record_failure("CodeCache is full");
1086     return;
1087   }
1088 
1089   // For java_to_interp stubs we use R11_scratch1 as scratch register
1090   // and in call trampoline stubs we use R12_scratch2. This way we
1091   // can distinguish them (see is_NativeCallTrampolineStub_at()).
1092   Register reg_scratch = R12_scratch2;
1093 
1094   // Create a trampoline stub relocation which relates this trampoline stub
1095   // with the call instruction at insts_call_instruction_offset in the
1096   // instructions code-section.
1097   __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset));
1098   const int stub_start_offset = __ offset();
1099 
1100   // Now, create the trampoline stub's code:
1101   // - load the TOC
1102   // - load the call target from the constant pool
1103   // - call
1104   __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1105   __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false);
1106   __ mtctr(reg_scratch);
1107   __ bctr();
1108 
1109   const address stub_start_addr = __ addr_at(stub_start_offset);
1110 
1111   // FIXME: Assert that the trampoline stub can be identified and patched.
1112 
1113   // Assert that the encoded destination_toc_offset can be identified and that it is correct.
1114   assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(),
1115          "encoded offset into the constant pool must match");
1116   // Trampoline_stub_size should be good.
1117   assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size");
1118   assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
1119 
1120   // End the stub.
1121   __ end_a_stub();
1122 }
1123 
1124 //=============================================================================
1125 
1126 // Emit an inline branch-and-link call and a related trampoline stub.
1127 //
1128 // code sequences:
1129 //
1130 // call-site:
1131 //   branch-and-link to <destination> or <trampoline stub>
1132 //
1133 // Related trampoline stub for this call-site in the stub section:
1134 //   load the call target from the constant pool
1135 //   branch via CTR (LR/link still points to the call-site above)
1136 //
1137 
1138 typedef struct {
1139   int insts_call_instruction_offset;
1140   int ret_addr_offset;
1141 } EmitCallOffsets;
1142 
1143 // Emit a branch-and-link instruction that branches to a trampoline.
1144 // - Remember the offset of the branch-and-link instruction.
1145 // - Add a relocation at the branch-and-link instruction.
1146 // - Emit a branch-and-link.
1147 // - Remember the return pc offset.
1148 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1149   EmitCallOffsets offsets = { -1, -1 };
1150   const int start_offset = __ offset();
1151   offsets.insts_call_instruction_offset = __ offset();
1152 
1153   // No entry point given, use the current pc.
1154   if (entry_point == NULL) entry_point = __ pc();
1155 
1156   if (!Compile::current()->in_scratch_emit_size()) {
1157     // Put the entry point as a constant into the constant pool.
1158     const address entry_point_toc_addr   = __ address_constant(entry_point, RelocationHolder::none);
1159     const int     entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1160 
1161     // Emit the trampoline stub which will be related to the branch-and-link below.
1162     CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1163     if (ciEnv::current()->failing()) { return offsets; } // Code cache may be full.
1164     __ relocate(rtype);
1165   }
1166 
1167   // Note: At this point we do not have the address of the trampoline
1168   // stub, and the entry point might be too far away for bl, so __ pc()
1169   // serves as dummy and the bl will be patched later.
1170   __ bl((address) __ pc());
1171 
1172   offsets.ret_addr_offset = __ offset() - start_offset;
1173 
1174   return offsets;
1175 }
1176 
1177 //=============================================================================
1178 
1179 // Factory for creating loadConL* nodes for large/small constant pool.
1180 
1181 static inline jlong replicate_immF(float con) {
1182   // Replicate float con 2 times and pack into vector.
1183   int val = *((int*)&con);
1184   jlong lval = val;
1185   lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1186   return lval;
1187 }
1188 
1189 //=============================================================================
1190 
1191 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1192 int Compile::ConstantTable::calculate_table_base_offset() const {
1193   return 0;  // absolute addressing, no offset
1194 }
1195 
1196 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1197 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1198   iRegPdstOper *op_dst = new iRegPdstOper();
1199   MachNode *m1 = new loadToc_hiNode();
1200   MachNode *m2 = new loadToc_loNode();
1201 
1202   m1->add_req(NULL);
1203   m2->add_req(NULL, m1);
1204   m1->_opnds[0] = op_dst;
1205   m2->_opnds[0] = op_dst;
1206   m2->_opnds[1] = op_dst;
1207   ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1208   ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1209   nodes->push(m1);
1210   nodes->push(m2);
1211 }
1212 
1213 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1214   // Is postalloc expanded.
1215   ShouldNotReachHere();
1216 }
1217 
1218 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1219   return 0;
1220 }
1221 
1222 #ifndef PRODUCT
1223 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1224   st->print("-- \t// MachConstantBaseNode (empty encoding)");
1225 }
1226 #endif
1227 
1228 //=============================================================================
1229 
1230 #ifndef PRODUCT
1231 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1232   Compile* C = ra_->C;
1233   const long framesize = C->frame_slots() << LogBytesPerInt;
1234 
1235   st->print("PROLOG\n\t");
1236   if (C->need_stack_bang(framesize)) {
1237     st->print("stack_overflow_check\n\t");
1238   }
1239 
1240   if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1241     st->print("save return pc\n\t");
1242     st->print("push frame %ld\n\t", -framesize);
1243   }
1244 }
1245 #endif
1246 
1247 // Macro used instead of the common __ to emulate the pipes of PPC.
1248 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1249 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1250 // still no scheduling of this code is possible, the micro scheduler is aware of the
1251 // code and can update its internal data. The following mechanism is used to achieve this:
1252 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1253 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1254 #if 0 // TODO: PPC port
1255 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling())                    \
1256                   C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1257                 _masm.
1258 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling())                    \
1259                   C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1260 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling())                 \
1261                   C->hb_scheduling()->_pdScheduling->advance_offset
1262 #else
1263 #define ___(op) if (UsePower6SchedulerPPC64)                                          \
1264                   Unimplemented();                                                    \
1265                 _masm.
1266 #define ___stop if (UsePower6SchedulerPPC64)                                          \
1267                   Unimplemented()
1268 #define ___advance if (UsePower6SchedulerPPC64)                                       \
1269                   Unimplemented()
1270 #endif
1271 
1272 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1273   Compile* C = ra_->C;
1274   MacroAssembler _masm(&cbuf);
1275 
1276   const long framesize = C->frame_size_in_bytes();
1277   assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment");
1278 
1279   const bool method_is_frameless      = false /* TODO: PPC port C->is_frameless_method()*/;
1280 
1281   const Register return_pc            = R20; // Must match return_addr() in frame section.
1282   const Register callers_sp           = R21;
1283   const Register push_frame_temp      = R22;
1284   const Register toc_temp             = R23;
1285   assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1286 
1287   if (method_is_frameless) {
1288     // Add nop at beginning of all frameless methods to prevent any
1289     // oop instructions from getting overwritten by make_not_entrant
1290     // (patching attempt would fail).
1291     ___(nop) nop();
1292   } else {
1293     // Get return pc.
1294     ___(mflr) mflr(return_pc);
1295   }
1296 
1297   // Calls to C2R adapters often do not accept exceptional returns.
1298   // We require that their callers must bang for them. But be
1299   // careful, because some VM calls (such as call site linkage) can
1300   // use several kilobytes of stack. But the stack safety zone should
1301   // account for that. See bugs 4446381, 4468289, 4497237.
1302 
1303   int bangsize = C->bang_size_in_bytes();
1304   assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect");
1305   if (C->need_stack_bang(bangsize) && UseStackBanging) {
1306     // Unfortunately we cannot use the function provided in
1307     // assembler.cpp as we have to emulate the pipes. So I had to
1308     // insert the code of generate_stack_overflow_check(), see
1309     // assembler.cpp for some illuminative comments.
1310     const int page_size = os::vm_page_size();
1311     int bang_end = StackShadowPages * page_size;
1312 
1313     // This is how far the previous frame's stack banging extended.
1314     const int bang_end_safe = bang_end;
1315 
1316     if (bangsize > page_size) {
1317       bang_end += bangsize;
1318     }
1319 
1320     int bang_offset = bang_end_safe;
1321 
1322     while (bang_offset <= bang_end) {
1323       // Need at least one stack bang at end of shadow zone.
1324 
1325       // Again I had to copy code, this time from assembler_ppc.cpp,
1326       // bang_stack_with_offset - see there for comments.
1327 
1328       // Stack grows down, caller passes positive offset.
1329       assert(bang_offset > 0, "must bang with positive offset");
1330 
1331       long stdoffset = -bang_offset;
1332 
1333       if (Assembler::is_simm(stdoffset, 16)) {
1334         // Signed 16 bit offset, a simple std is ok.
1335         if (UseLoadInstructionsForStackBangingPPC64) {
1336           ___(ld) ld(R0,  (int)(signed short)stdoffset, R1_SP);
1337         } else {
1338           ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1339         }
1340       } else if (Assembler::is_simm(stdoffset, 31)) {
1341         // Use largeoffset calculations for addis & ld/std.
1342         const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1343         const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1344 
1345         Register tmp = R11;
1346         ___(addis) addis(tmp, R1_SP, hi);
1347         if (UseLoadInstructionsForStackBangingPPC64) {
1348           ___(ld) ld(R0, lo, tmp);
1349         } else {
1350           ___(std) std(R0, lo, tmp);
1351         }
1352       } else {
1353         ShouldNotReachHere();
1354       }
1355 
1356       bang_offset += page_size;
1357     }
1358     // R11 trashed
1359   } // C->need_stack_bang(framesize) && UseStackBanging
1360 
1361   unsigned int bytes = (unsigned int)framesize;
1362   long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1363   ciMethod *currMethod = C->method();
1364 
1365   // Optimized version for most common case.
1366   if (UsePower6SchedulerPPC64 &&
1367       !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1368       !(false /* ConstantsALot TODO: PPC port*/)) {
1369     ___(or) mr(callers_sp, R1_SP);
1370     ___(std) std(return_pc, _abi(lr), R1_SP);
1371     ___(stdu) stdu(R1_SP, -offset, R1_SP);
1372     return;
1373   }
1374 
1375   if (!method_is_frameless) {
1376     // Get callers sp.
1377     ___(or) mr(callers_sp, R1_SP);
1378 
1379     // Push method's frame, modifies SP.
1380     assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1381     // The ABI is already accounted for in 'framesize' via the
1382     // 'out_preserve' area.
1383     Register tmp = push_frame_temp;
1384     // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1385     if (Assembler::is_simm(-offset, 16)) {
1386       ___(stdu) stdu(R1_SP, -offset, R1_SP);
1387     } else {
1388       long x = -offset;
1389       // Had to insert load_const(tmp, -offset).
1390       ___(addis)  lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1391       ___(ori)    ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1392       ___(rldicr) sldi(tmp, tmp, 32);
1393       ___(oris)   oris(tmp, tmp, (x & 0xffff0000) >> 16);
1394       ___(ori)    ori( tmp, tmp, (x & 0x0000ffff));
1395 
1396       ___(stdux) stdux(R1_SP, R1_SP, tmp);
1397     }
1398   }
1399 #if 0 // TODO: PPC port
1400   // For testing large constant pools, emit a lot of constants to constant pool.
1401   // "Randomize" const_size.
1402   if (ConstantsALot) {
1403     const int num_consts = const_size();
1404     for (int i = 0; i < num_consts; i++) {
1405       __ long_constant(0xB0B5B00BBABE);
1406     }
1407   }
1408 #endif
1409   if (!method_is_frameless) {
1410     // Save return pc.
1411     ___(std) std(return_pc, _abi(lr), callers_sp);
1412   }
1413 }
1414 #undef ___
1415 #undef ___stop
1416 #undef ___advance
1417 
1418 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1419   // Variable size. determine dynamically.
1420   return MachNode::size(ra_);
1421 }
1422 
1423 int MachPrologNode::reloc() const {
1424   // Return number of relocatable values contained in this instruction.
1425   return 1; // 1 reloc entry for load_const(toc).
1426 }
1427 
1428 //=============================================================================
1429 
1430 #ifndef PRODUCT
1431 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1432   Compile* C = ra_->C;
1433 
1434   st->print("EPILOG\n\t");
1435   st->print("restore return pc\n\t");
1436   st->print("pop frame\n\t");
1437 
1438   if (do_polling() && C->is_method_compilation()) {
1439     st->print("touch polling page\n\t");
1440   }
1441 }
1442 #endif
1443 
1444 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1445   Compile* C = ra_->C;
1446   MacroAssembler _masm(&cbuf);
1447 
1448   const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1449   assert(framesize >= 0, "negative frame-size?");
1450 
1451   const bool method_needs_polling = do_polling() && C->is_method_compilation();
1452   const bool method_is_frameless  = false /* TODO: PPC port C->is_frameless_method()*/;
1453   const Register return_pc        = R11;
1454   const Register polling_page     = R12;
1455 
1456   if (!method_is_frameless) {
1457     // Restore return pc relative to callers' sp.
1458     __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1459   }
1460 
1461   if (method_needs_polling) {
1462     if (LoadPollAddressFromThread) {
1463       // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1464       Unimplemented();
1465     } else {
1466       __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1467     }
1468   }
1469 
1470   if (!method_is_frameless) {
1471     // Move return pc to LR.
1472     __ mtlr(return_pc);
1473     // Pop frame (fixed frame-size).
1474     __ addi(R1_SP, R1_SP, (int)framesize);
1475   }
1476 
1477   if (method_needs_polling) {
1478     // We need to mark the code position where the load from the safepoint
1479     // polling page was emitted as relocInfo::poll_return_type here.
1480     __ relocate(relocInfo::poll_return_type);
1481     __ load_from_polling_page(polling_page);
1482   }
1483 }
1484 
1485 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1486   // Variable size. Determine dynamically.
1487   return MachNode::size(ra_);
1488 }
1489 
1490 int MachEpilogNode::reloc() const {
1491   // Return number of relocatable values contained in this instruction.
1492   return 1; // 1 for load_from_polling_page.
1493 }
1494 
1495 const Pipeline * MachEpilogNode::pipeline() const {
1496   return MachNode::pipeline_class();
1497 }
1498 
1499 // This method seems to be obsolete. It is declared in machnode.hpp
1500 // and defined in all *.ad files, but it is never called. Should we
1501 // get rid of it?
1502 int MachEpilogNode::safepoint_offset() const {
1503   assert(do_polling(), "no return for this epilog node");
1504   return 0;
1505 }
1506 
1507 #if 0 // TODO: PPC port
1508 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1509   MacroAssembler _masm(&cbuf);
1510   if (LoadPollAddressFromThread) {
1511     _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1512   } else {
1513     _masm.nop();
1514   }
1515 }
1516 
1517 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1518   if (LoadPollAddressFromThread) {
1519     return 4;
1520   } else {
1521     return 4;
1522   }
1523 }
1524 
1525 #ifndef PRODUCT
1526 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1527   st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1528 }
1529 #endif
1530 
1531 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1532   return RSCRATCH1_BITS64_REG_mask();
1533 }
1534 #endif // PPC port
1535 
1536 // =============================================================================
1537 
1538 // Figure out which register class each belongs in: rc_int, rc_float or
1539 // rc_stack.
1540 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1541 
1542 static enum RC rc_class(OptoReg::Name reg) {
1543   // Return the register class for the given register. The given register
1544   // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1545   // enumeration in adGlobals_ppc.hpp.
1546 
1547   if (reg == OptoReg::Bad) return rc_bad;
1548 
1549   // We have 64 integer register halves, starting at index 0.
1550   if (reg < 64) return rc_int;
1551 
1552   // We have 64 floating-point register halves, starting at index 64.
1553   if (reg < 64+64) return rc_float;
1554 
1555   // Between float regs & stack are the flags regs.
1556   assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1557 
1558   return rc_stack;
1559 }
1560 
1561 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1562                         bool do_print, Compile* C, outputStream *st) {
1563 
1564   assert(opcode == Assembler::LD_OPCODE   ||
1565          opcode == Assembler::STD_OPCODE  ||
1566          opcode == Assembler::LWZ_OPCODE  ||
1567          opcode == Assembler::STW_OPCODE  ||
1568          opcode == Assembler::LFD_OPCODE  ||
1569          opcode == Assembler::STFD_OPCODE ||
1570          opcode == Assembler::LFS_OPCODE  ||
1571          opcode == Assembler::STFS_OPCODE,
1572          "opcode not supported");
1573 
1574   if (cbuf) {
1575     int d =
1576       (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1577         Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1578       : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1579     emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1580   }
1581 #ifndef PRODUCT
1582   else if (do_print) {
1583     st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1584               op_str,
1585               Matcher::regName[reg],
1586               offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1587   }
1588 #endif
1589   return 4; // size
1590 }
1591 
1592 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1593   Compile* C = ra_->C;
1594 
1595   // Get registers to move.
1596   OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1597   OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1598   OptoReg::Name dst_hi = ra_->get_reg_second(this);
1599   OptoReg::Name dst_lo = ra_->get_reg_first(this);
1600 
1601   enum RC src_hi_rc = rc_class(src_hi);
1602   enum RC src_lo_rc = rc_class(src_lo);
1603   enum RC dst_hi_rc = rc_class(dst_hi);
1604   enum RC dst_lo_rc = rc_class(dst_lo);
1605 
1606   assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1607   if (src_hi != OptoReg::Bad)
1608     assert((src_lo&1)==0 && src_lo+1==src_hi &&
1609            (dst_lo&1)==0 && dst_lo+1==dst_hi,
1610            "expected aligned-adjacent pairs");
1611   // Generate spill code!
1612   int size = 0;
1613 
1614   if (src_lo == dst_lo && src_hi == dst_hi)
1615     return size;            // Self copy, no move.
1616 
1617   // --------------------------------------
1618   // Memory->Memory Spill. Use R0 to hold the value.
1619   if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1620     int src_offset = ra_->reg2offset(src_lo);
1621     int dst_offset = ra_->reg2offset(dst_lo);
1622     if (src_hi != OptoReg::Bad) {
1623       assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1624              "expected same type of move for high parts");
1625       size += ld_st_helper(cbuf, "LD  ", Assembler::LD_OPCODE,  R0_num, src_offset, !do_size, C, st);
1626       if (!cbuf && !do_size) st->print("\n\t");
1627       size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1628     } else {
1629       size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1630       if (!cbuf && !do_size) st->print("\n\t");
1631       size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1632     }
1633     return size;
1634   }
1635 
1636   // --------------------------------------
1637   // Check for float->int copy; requires a trip through memory.
1638   if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1639     Unimplemented();
1640   }
1641 
1642   // --------------------------------------
1643   // Check for integer reg-reg copy.
1644   if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1645       Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1646       Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1647       size = (Rsrc != Rdst) ? 4 : 0;
1648 
1649       if (cbuf) {
1650         MacroAssembler _masm(cbuf);
1651         if (size) {
1652           __ mr(Rdst, Rsrc);
1653         }
1654       }
1655 #ifndef PRODUCT
1656       else if (!do_size) {
1657         if (size) {
1658           st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1659         } else {
1660           st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1661         }
1662       }
1663 #endif
1664       return size;
1665   }
1666 
1667   // Check for integer store.
1668   if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1669     int dst_offset = ra_->reg2offset(dst_lo);
1670     if (src_hi != OptoReg::Bad) {
1671       assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1672              "expected same type of move for high parts");
1673       size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1674     } else {
1675       size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1676     }
1677     return size;
1678   }
1679 
1680   // Check for integer load.
1681   if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1682     int src_offset = ra_->reg2offset(src_lo);
1683     if (src_hi != OptoReg::Bad) {
1684       assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1685              "expected same type of move for high parts");
1686       size += ld_st_helper(cbuf, "LD  ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1687     } else {
1688       size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1689     }
1690     return size;
1691   }
1692 
1693   // Check for float reg-reg copy.
1694   if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1695     if (cbuf) {
1696       MacroAssembler _masm(cbuf);
1697       FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1698       FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1699       __ fmr(Rdst, Rsrc);
1700     }
1701 #ifndef PRODUCT
1702     else if (!do_size) {
1703       st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1704     }
1705 #endif
1706     return 4;
1707   }
1708 
1709   // Check for float store.
1710   if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1711     int dst_offset = ra_->reg2offset(dst_lo);
1712     if (src_hi != OptoReg::Bad) {
1713       assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1714              "expected same type of move for high parts");
1715       size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1716     } else {
1717       size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1718     }
1719     return size;
1720   }
1721 
1722   // Check for float load.
1723   if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1724     int src_offset = ra_->reg2offset(src_lo);
1725     if (src_hi != OptoReg::Bad) {
1726       assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1727              "expected same type of move for high parts");
1728       size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1729     } else {
1730       size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1731     }
1732     return size;
1733   }
1734 
1735   // --------------------------------------------------------------------
1736   // Check for hi bits still needing moving. Only happens for misaligned
1737   // arguments to native calls.
1738   if (src_hi == dst_hi)
1739     return size;               // Self copy; no move.
1740 
1741   assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1742   ShouldNotReachHere(); // Unimplemented
1743   return 0;
1744 }
1745 
1746 #ifndef PRODUCT
1747 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1748   if (!ra_)
1749     st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1750   else
1751     implementation(NULL, ra_, false, st);
1752 }
1753 #endif
1754 
1755 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1756   implementation(&cbuf, ra_, false, NULL);
1757 }
1758 
1759 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1760   return implementation(NULL, ra_, true, NULL);
1761 }
1762 
1763 #if 0 // TODO: PPC port
1764 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1765 #ifndef PRODUCT
1766   if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1767 #endif
1768   assert(ra_->node_regs_max_index() != 0, "");
1769 
1770   // Get registers to move.
1771   OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1772   OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1773   OptoReg::Name dst_hi = ra_->get_reg_second(n);
1774   OptoReg::Name dst_lo = ra_->get_reg_first(n);
1775 
1776   enum RC src_lo_rc = rc_class(src_lo);
1777   enum RC dst_lo_rc = rc_class(dst_lo);
1778 
1779   if (src_lo == dst_lo && src_hi == dst_hi)
1780     return ppc64Opcode_none;            // Self copy, no move.
1781 
1782   // --------------------------------------
1783   // Memory->Memory Spill. Use R0 to hold the value.
1784   if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1785     return ppc64Opcode_compound;
1786   }
1787 
1788   // --------------------------------------
1789   // Check for float->int copy; requires a trip through memory.
1790   if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1791     Unimplemented();
1792   }
1793 
1794   // --------------------------------------
1795   // Check for integer reg-reg copy.
1796   if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1797     Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1798     Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1799     if (Rsrc == Rdst) {
1800       return ppc64Opcode_none;
1801     } else {
1802       return ppc64Opcode_or;
1803     }
1804   }
1805 
1806   // Check for integer store.
1807   if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1808     if (src_hi != OptoReg::Bad) {
1809       return ppc64Opcode_std;
1810     } else {
1811       return ppc64Opcode_stw;
1812     }
1813   }
1814 
1815   // Check for integer load.
1816   if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1817     if (src_hi != OptoReg::Bad) {
1818       return ppc64Opcode_ld;
1819     } else {
1820       return ppc64Opcode_lwz;
1821     }
1822   }
1823 
1824   // Check for float reg-reg copy.
1825   if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1826     return ppc64Opcode_fmr;
1827   }
1828 
1829   // Check for float store.
1830   if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1831     if (src_hi != OptoReg::Bad) {
1832       return ppc64Opcode_stfd;
1833     } else {
1834       return ppc64Opcode_stfs;
1835     }
1836   }
1837 
1838   // Check for float load.
1839   if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1840     if (src_hi != OptoReg::Bad) {
1841       return ppc64Opcode_lfd;
1842     } else {
1843       return ppc64Opcode_lfs;
1844     }
1845   }
1846 
1847   // --------------------------------------------------------------------
1848   // Check for hi bits still needing moving. Only happens for misaligned
1849   // arguments to native calls.
1850   if (src_hi == dst_hi) {
1851     return ppc64Opcode_none;               // Self copy; no move.
1852   }
1853 
1854   ShouldNotReachHere();
1855   return ppc64Opcode_undefined;
1856 }
1857 #endif // PPC port
1858 
1859 #ifndef PRODUCT
1860 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1861   st->print("NOP \t// %d nops to pad for loops.", _count);
1862 }
1863 #endif
1864 
1865 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1866   MacroAssembler _masm(&cbuf);
1867   // _count contains the number of nops needed for padding.
1868   for (int i = 0; i < _count; i++) {
1869     __ nop();
1870   }
1871 }
1872 
1873 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1874   return _count * 4;
1875 }
1876 
1877 #ifndef PRODUCT
1878 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1879   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1880   char reg_str[128];
1881   ra_->dump_register(this, reg_str);
1882   st->print("ADDI    %s, SP, %d \t// box node", reg_str, offset);
1883 }
1884 #endif
1885 
1886 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1887   MacroAssembler _masm(&cbuf);
1888 
1889   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1890   int reg    = ra_->get_encode(this);
1891 
1892   if (Assembler::is_simm(offset, 16)) {
1893     __ addi(as_Register(reg), R1, offset);
1894   } else {
1895     ShouldNotReachHere();
1896   }
1897 }
1898 
1899 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1900   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1901   return 4;
1902 }
1903 
1904 #ifndef PRODUCT
1905 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1906   st->print_cr("---- MachUEPNode ----");
1907   st->print_cr("...");
1908 }
1909 #endif
1910 
1911 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1912   // This is the unverified entry point.
1913   MacroAssembler _masm(&cbuf);
1914 
1915   // Inline_cache contains a klass.
1916   Register ic_klass       = as_Register(Matcher::inline_cache_reg_encode());
1917   Register receiver_klass = R12_scratch2;  // tmp
1918 
1919   assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
1920   assert(R11_scratch1 == R11, "need prologue scratch register");
1921 
1922   // Check for NULL argument if we don't have implicit null checks.
1923   if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
1924     if (TrapBasedNullChecks) {
1925       __ trap_null_check(R3_ARG1);
1926     } else {
1927       Label valid;
1928       __ cmpdi(CCR0, R3_ARG1, 0);
1929       __ bne_predict_taken(CCR0, valid);
1930       // We have a null argument, branch to ic_miss_stub.
1931       __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1932                            relocInfo::runtime_call_type);
1933       __ bind(valid);
1934     }
1935   }
1936   // Assume argument is not NULL, load klass from receiver.
1937   __ load_klass(receiver_klass, R3_ARG1);
1938 
1939   if (TrapBasedICMissChecks) {
1940     __ trap_ic_miss_check(receiver_klass, ic_klass);
1941   } else {
1942     Label valid;
1943     __ cmpd(CCR0, receiver_klass, ic_klass);
1944     __ beq_predict_taken(CCR0, valid);
1945     // We have an unexpected klass, branch to ic_miss_stub.
1946     __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1947                          relocInfo::runtime_call_type);
1948     __ bind(valid);
1949   }
1950 
1951   // Argument is valid and klass is as expected, continue.
1952 }
1953 
1954 #if 0 // TODO: PPC port
1955 // Optimize UEP code on z (save a load_const() call in main path).
1956 int MachUEPNode::ep_offset() {
1957   return 0;
1958 }
1959 #endif
1960 
1961 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1962   // Variable size. Determine dynamically.
1963   return MachNode::size(ra_);
1964 }
1965 
1966 //=============================================================================
1967 
1968 %} // interrupt source
1969 
1970 source_hpp %{ // Header information of the source block.
1971 
1972 class HandlerImpl {
1973 
1974  public:
1975 
1976   static int emit_exception_handler(CodeBuffer &cbuf);
1977   static int emit_deopt_handler(CodeBuffer& cbuf);
1978 
1979   static uint size_exception_handler() {
1980     // The exception_handler is a b64_patchable.
1981     return MacroAssembler::b64_patchable_size;
1982   }
1983 
1984   static uint size_deopt_handler() {
1985     // The deopt_handler is a bl64_patchable.
1986     return MacroAssembler::bl64_patchable_size;
1987   }
1988 
1989 };
1990 
1991 %} // end source_hpp
1992 
1993 source %{
1994 
1995 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
1996   MacroAssembler _masm(&cbuf);
1997 
1998   address base = __ start_a_stub(size_exception_handler());
1999   if (base == NULL) return 0; // CodeBuffer::expand failed
2000 
2001   int offset = __ offset();
2002   __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
2003                        relocInfo::runtime_call_type);
2004   assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
2005   __ end_a_stub();
2006 
2007   return offset;
2008 }
2009 
2010 // The deopt_handler is like the exception handler, but it calls to
2011 // the deoptimization blob instead of jumping to the exception blob.
2012 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
2013   MacroAssembler _masm(&cbuf);
2014 
2015   address base = __ start_a_stub(size_deopt_handler());
2016   if (base == NULL) return 0; // CodeBuffer::expand failed
2017 
2018   int offset = __ offset();
2019   __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
2020                         relocInfo::runtime_call_type);
2021   assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
2022   __ end_a_stub();
2023 
2024   return offset;
2025 }
2026 
2027 //=============================================================================
2028 
2029 // Use a frame slots bias for frameless methods if accessing the stack.
2030 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2031   if (as_Register(reg_enc) == R1_SP) {
2032     return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2033   }
2034   return 0;
2035 }
2036 
2037 const bool Matcher::match_rule_supported(int opcode) {
2038   if (!has_match_rule(opcode))
2039     return false;
2040 
2041   switch (opcode) {
2042   case Op_SqrtD:
2043     return VM_Version::has_fsqrt();
2044   case Op_CountLeadingZerosI:
2045   case Op_CountLeadingZerosL:
2046   case Op_CountTrailingZerosI:
2047   case Op_CountTrailingZerosL:
2048     if (!UseCountLeadingZerosInstructionsPPC64)
2049       return false;
2050     break;
2051 
2052   case Op_PopCountI:
2053   case Op_PopCountL:
2054     return (UsePopCountInstruction && VM_Version::has_popcntw());
2055 
2056   case Op_StrComp:
2057     return SpecialStringCompareTo && !CompactStrings;
2058   case Op_StrEquals:
2059     return SpecialStringEquals && !CompactStrings;
2060   case Op_StrIndexOf:
2061     return SpecialStringIndexOf && !CompactStrings;
2062   }
2063 
2064   return true;  // Per default match rules are supported.
2065 }
2066 
2067 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
2068 
2069   // TODO
2070   // identify extra cases that we might want to provide match rules for
2071   // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
2072   bool ret_value = match_rule_supported(opcode);
2073   // Add rules here.
2074 
2075   return ret_value;  // Per default match rules are supported.
2076 }
2077 
2078 const int Matcher::float_pressure(int default_pressure_threshold) {
2079   return default_pressure_threshold;
2080 }
2081 
2082 int Matcher::regnum_to_fpu_offset(int regnum) {
2083   // No user for this method?
2084   Unimplemented();
2085   return 999;
2086 }
2087 
2088 const bool Matcher::convL2FSupported(void) {
2089   // fcfids can do the conversion (>= Power7).
2090   // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2091   return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2092 }
2093 
2094 // Vector width in bytes.
2095 const int Matcher::vector_width_in_bytes(BasicType bt) {
2096   assert(MaxVectorSize == 8, "");
2097   return 8;
2098 }
2099 
2100 // Vector ideal reg.
2101 const int Matcher::vector_ideal_reg(int size) {
2102   assert(MaxVectorSize == 8 && size == 8, "");
2103   return Op_RegL;
2104 }
2105 
2106 const int Matcher::vector_shift_count_ideal_reg(int size) {
2107   fatal("vector shift is not supported");
2108   return Node::NotAMachineReg;
2109 }
2110 
2111 // Limits on vector size (number of elements) loaded into vector.
2112 const int Matcher::max_vector_size(const BasicType bt) {
2113   assert(is_java_primitive(bt), "only primitive type vectors");
2114   return vector_width_in_bytes(bt)/type2aelembytes(bt);
2115 }
2116 
2117 const int Matcher::min_vector_size(const BasicType bt) {
2118   return max_vector_size(bt); // Same as max.
2119 }
2120 
2121 // PPC doesn't support misaligned vectors store/load.
2122 const bool Matcher::misaligned_vectors_ok() {
2123   return false;
2124 }
2125 
2126 // PPC AES support not yet implemented
2127 const bool Matcher::pass_original_key_for_aes() {
2128   return false;
2129 }
2130 
2131 // RETURNS: whether this branch offset is short enough that a short
2132 // branch can be used.
2133 //
2134 // If the platform does not provide any short branch variants, then
2135 // this method should return `false' for offset 0.
2136 //
2137 // `Compile::Fill_buffer' will decide on basis of this information
2138 // whether to do the pass `Compile::Shorten_branches' at all.
2139 //
2140 // And `Compile::Shorten_branches' will decide on basis of this
2141 // information whether to replace particular branch sites by short
2142 // ones.
2143 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2144   // Is the offset within the range of a ppc64 pc relative branch?
2145   bool b;
2146 
2147   const int safety_zone = 3 * BytesPerInstWord;
2148   b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2149                          29 - 16 + 1 + 2);
2150   return b;
2151 }
2152 
2153 const bool Matcher::isSimpleConstant64(jlong value) {
2154   // Probably always true, even if a temp register is required.
2155   return true;
2156 }
2157 /* TODO: PPC port
2158 // Make a new machine dependent decode node (with its operands).
2159 MachTypeNode *Matcher::make_decode_node() {
2160   assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2161          "This method is only implemented for unscaled cOops mode so far");
2162   MachTypeNode *decode = new decodeN_unscaledNode();
2163   decode->set_opnd_array(0, new iRegPdstOper());
2164   decode->set_opnd_array(1, new iRegNsrcOper());
2165   return decode;
2166 }
2167 */
2168 // Threshold size for cleararray.
2169 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2170 
2171 // false => size gets scaled to BytesPerLong, ok.
2172 const bool Matcher::init_array_count_is_in_bytes = false;
2173 
2174 // Use conditional move (CMOVL) on Power7.
2175 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2176 
2177 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2178 // fsel doesn't accept a condition register as input, so this would be slightly different.
2179 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2180 
2181 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2182 const bool Matcher::require_postalloc_expand = true;
2183 
2184 // Should the Matcher clone shifts on addressing modes, expecting them to
2185 // be subsumed into complex addressing expressions or compute them into
2186 // registers? True for Intel but false for most RISCs.
2187 const bool Matcher::clone_shift_expressions = false;
2188 
2189 // Do we need to mask the count passed to shift instructions or does
2190 // the cpu only look at the lower 5/6 bits anyway?
2191 // PowerPC requires masked shift counts.
2192 const bool Matcher::need_masked_shift_count = true;
2193 
2194 // This affects two different things:
2195 //  - how Decode nodes are matched
2196 //  - how ImplicitNullCheck opportunities are recognized
2197 // If true, the matcher will try to remove all Decodes and match them
2198 // (as operands) into nodes. NullChecks are not prepared to deal with
2199 // Decodes by final_graph_reshaping().
2200 // If false, final_graph_reshaping() forces the decode behind the Cmp
2201 // for a NullCheck. The matcher matches the Decode node into a register.
2202 // Implicit_null_check optimization moves the Decode along with the
2203 // memory operation back up before the NullCheck.
2204 bool Matcher::narrow_oop_use_complex_address() {
2205   // TODO: PPC port if (MatchDecodeNodes) return true;
2206   return false;
2207 }
2208 
2209 bool Matcher::narrow_klass_use_complex_address() {
2210   NOT_LP64(ShouldNotCallThis());
2211   assert(UseCompressedClassPointers, "only for compressed klass code");
2212   // TODO: PPC port if (MatchDecodeNodes) return true;
2213   return false;
2214 }
2215 
2216 // Is it better to copy float constants, or load them directly from memory?
2217 // Intel can load a float constant from a direct address, requiring no
2218 // extra registers. Most RISCs will have to materialize an address into a
2219 // register first, so they would do better to copy the constant from stack.
2220 const bool Matcher::rematerialize_float_constants = false;
2221 
2222 // If CPU can load and store mis-aligned doubles directly then no fixup is
2223 // needed. Else we split the double into 2 integer pieces and move it
2224 // piece-by-piece. Only happens when passing doubles into C code as the
2225 // Java calling convention forces doubles to be aligned.
2226 const bool Matcher::misaligned_doubles_ok = true;
2227 
2228 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2229  Unimplemented();
2230 }
2231 
2232 // Advertise here if the CPU requires explicit rounding operations
2233 // to implement the UseStrictFP mode.
2234 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2235 
2236 // Do floats take an entire double register or just half?
2237 //
2238 // A float occupies a ppc64 double register. For the allocator, a
2239 // ppc64 double register appears as a pair of float registers.
2240 bool Matcher::float_in_double() { return true; }
2241 
2242 // Do ints take an entire long register or just half?
2243 // The relevant question is how the int is callee-saved:
2244 // the whole long is written but de-opt'ing will have to extract
2245 // the relevant 32 bits.
2246 const bool Matcher::int_in_long = true;
2247 
2248 // Constants for c2c and c calling conventions.
2249 
2250 const MachRegisterNumbers iarg_reg[8] = {
2251   R3_num, R4_num, R5_num, R6_num,
2252   R7_num, R8_num, R9_num, R10_num
2253 };
2254 
2255 const MachRegisterNumbers farg_reg[13] = {
2256   F1_num, F2_num, F3_num, F4_num,
2257   F5_num, F6_num, F7_num, F8_num,
2258   F9_num, F10_num, F11_num, F12_num,
2259   F13_num
2260 };
2261 
2262 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2263 
2264 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2265 
2266 // Return whether or not this register is ever used as an argument. This
2267 // function is used on startup to build the trampoline stubs in generateOptoStub.
2268 // Registers not mentioned will be killed by the VM call in the trampoline, and
2269 // arguments in those registers not be available to the callee.
2270 bool Matcher::can_be_java_arg(int reg) {
2271   // We return true for all registers contained in iarg_reg[] and
2272   // farg_reg[] and their virtual halves.
2273   // We must include the virtual halves in order to get STDs and LDs
2274   // instead of STWs and LWs in the trampoline stubs.
2275 
2276   if (   reg == R3_num  || reg == R3_H_num
2277       || reg == R4_num  || reg == R4_H_num
2278       || reg == R5_num  || reg == R5_H_num
2279       || reg == R6_num  || reg == R6_H_num
2280       || reg == R7_num  || reg == R7_H_num
2281       || reg == R8_num  || reg == R8_H_num
2282       || reg == R9_num  || reg == R9_H_num
2283       || reg == R10_num || reg == R10_H_num)
2284     return true;
2285 
2286   if (   reg == F1_num  || reg == F1_H_num
2287       || reg == F2_num  || reg == F2_H_num
2288       || reg == F3_num  || reg == F3_H_num
2289       || reg == F4_num  || reg == F4_H_num
2290       || reg == F5_num  || reg == F5_H_num
2291       || reg == F6_num  || reg == F6_H_num
2292       || reg == F7_num  || reg == F7_H_num
2293       || reg == F8_num  || reg == F8_H_num
2294       || reg == F9_num  || reg == F9_H_num
2295       || reg == F10_num || reg == F10_H_num
2296       || reg == F11_num || reg == F11_H_num
2297       || reg == F12_num || reg == F12_H_num
2298       || reg == F13_num || reg == F13_H_num)
2299     return true;
2300 
2301   return false;
2302 }
2303 
2304 bool Matcher::is_spillable_arg(int reg) {
2305   return can_be_java_arg(reg);
2306 }
2307 
2308 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2309   return false;
2310 }
2311 
2312 // Register for DIVI projection of divmodI.
2313 RegMask Matcher::divI_proj_mask() {
2314   ShouldNotReachHere();
2315   return RegMask();
2316 }
2317 
2318 // Register for MODI projection of divmodI.
2319 RegMask Matcher::modI_proj_mask() {
2320   ShouldNotReachHere();
2321   return RegMask();
2322 }
2323 
2324 // Register for DIVL projection of divmodL.
2325 RegMask Matcher::divL_proj_mask() {
2326   ShouldNotReachHere();
2327   return RegMask();
2328 }
2329 
2330 // Register for MODL projection of divmodL.
2331 RegMask Matcher::modL_proj_mask() {
2332   ShouldNotReachHere();
2333   return RegMask();
2334 }
2335 
2336 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2337   return RegMask();
2338 }
2339 
2340 %}
2341 
2342 //----------ENCODING BLOCK-----------------------------------------------------
2343 // This block specifies the encoding classes used by the compiler to output
2344 // byte streams. Encoding classes are parameterized macros used by
2345 // Machine Instruction Nodes in order to generate the bit encoding of the
2346 // instruction. Operands specify their base encoding interface with the
2347 // interface keyword. There are currently supported four interfaces,
2348 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2349 // operand to generate a function which returns its register number when
2350 // queried. CONST_INTER causes an operand to generate a function which
2351 // returns the value of the constant when queried. MEMORY_INTER causes an
2352 // operand to generate four functions which return the Base Register, the
2353 // Index Register, the Scale Value, and the Offset Value of the operand when
2354 // queried. COND_INTER causes an operand to generate six functions which
2355 // return the encoding code (ie - encoding bits for the instruction)
2356 // associated with each basic boolean condition for a conditional instruction.
2357 //
2358 // Instructions specify two basic values for encoding. Again, a function
2359 // is available to check if the constant displacement is an oop. They use the
2360 // ins_encode keyword to specify their encoding classes (which must be
2361 // a sequence of enc_class names, and their parameters, specified in
2362 // the encoding block), and they use the
2363 // opcode keyword to specify, in order, their primary, secondary, and
2364 // tertiary opcode. Only the opcode sections which a particular instruction
2365 // needs for encoding need to be specified.
2366 encode %{
2367   enc_class enc_unimplemented %{
2368     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2369     MacroAssembler _masm(&cbuf);
2370     __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2371   %}
2372 
2373   enc_class enc_untested %{
2374 #ifdef ASSERT
2375     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2376     MacroAssembler _masm(&cbuf);
2377     __ untested("Untested mach node encoding in AD file.");
2378 #else
2379     // TODO: PPC port $archOpcode(ppc64Opcode_none);
2380 #endif
2381   %}
2382 
2383   enc_class enc_lbz(iRegIdst dst, memory mem) %{
2384     // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2385     MacroAssembler _masm(&cbuf);
2386     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2387     __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2388   %}
2389 
2390   // Load acquire.
2391   enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2392     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2393     MacroAssembler _masm(&cbuf);
2394     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2395     __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2396     __ twi_0($dst$$Register);
2397     __ isync();
2398   %}
2399 
2400   enc_class enc_lhz(iRegIdst dst, memory mem) %{
2401     // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2402 
2403     MacroAssembler _masm(&cbuf);
2404     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2405     __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2406   %}
2407 
2408   // Load acquire.
2409   enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2410     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2411 
2412     MacroAssembler _masm(&cbuf);
2413     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2414     __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2415     __ twi_0($dst$$Register);
2416     __ isync();
2417   %}
2418 
2419   enc_class enc_lwz(iRegIdst dst, memory mem) %{
2420     // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2421 
2422     MacroAssembler _masm(&cbuf);
2423     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2424     __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2425   %}
2426 
2427   // Load acquire.
2428   enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2429     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2430 
2431     MacroAssembler _masm(&cbuf);
2432     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2433     __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2434     __ twi_0($dst$$Register);
2435     __ isync();
2436   %}
2437 
2438   enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2439     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2440     MacroAssembler _masm(&cbuf);
2441     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2442     // Operand 'ds' requires 4-alignment.
2443     assert((Idisp & 0x3) == 0, "unaligned offset");
2444     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2445   %}
2446 
2447   // Load acquire.
2448   enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2449     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2450     MacroAssembler _masm(&cbuf);
2451     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2452     // Operand 'ds' requires 4-alignment.
2453     assert((Idisp & 0x3) == 0, "unaligned offset");
2454     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2455     __ twi_0($dst$$Register);
2456     __ isync();
2457   %}
2458 
2459   enc_class enc_lfd(RegF dst, memory mem) %{
2460     // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2461     MacroAssembler _masm(&cbuf);
2462     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2463     __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2464   %}
2465 
2466   enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2467     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2468 
2469     MacroAssembler _masm(&cbuf);
2470     int toc_offset = 0;
2471 
2472     if (!ra_->C->in_scratch_emit_size()) {
2473       address const_toc_addr;
2474       // Create a non-oop constant, no relocation needed.
2475       // If it is an IC, it has a virtual_call_Relocation.
2476       const_toc_addr = __ long_constant((jlong)$src$$constant);
2477 
2478       // Get the constant's TOC offset.
2479       toc_offset = __ offset_to_method_toc(const_toc_addr);
2480 
2481       // Keep the current instruction offset in mind.
2482       ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2483     }
2484 
2485     __ ld($dst$$Register, toc_offset, $toc$$Register);
2486   %}
2487 
2488   enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2489     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2490 
2491     MacroAssembler _masm(&cbuf);
2492 
2493     if (!ra_->C->in_scratch_emit_size()) {
2494       address const_toc_addr;
2495       // Create a non-oop constant, no relocation needed.
2496       // If it is an IC, it has a virtual_call_Relocation.
2497       const_toc_addr = __ long_constant((jlong)$src$$constant);
2498 
2499       // Get the constant's TOC offset.
2500       const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2501       // Store the toc offset of the constant.
2502       ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2503 
2504       // Also keep the current instruction offset in mind.
2505       ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2506     }
2507 
2508     __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2509   %}
2510 
2511 %} // encode
2512 
2513 source %{
2514 
2515 typedef struct {
2516   loadConL_hiNode *_large_hi;
2517   loadConL_loNode *_large_lo;
2518   loadConLNode    *_small;
2519   MachNode        *_last;
2520 } loadConLNodesTuple;
2521 
2522 loadConLNodesTuple loadConLNodesTuple_create(PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2523                                              OptoReg::Name reg_second, OptoReg::Name reg_first) {
2524   loadConLNodesTuple nodes;
2525 
2526   const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2527   if (large_constant_pool) {
2528     // Create new nodes.
2529     loadConL_hiNode *m1 = new loadConL_hiNode();
2530     loadConL_loNode *m2 = new loadConL_loNode();
2531 
2532     // inputs for new nodes
2533     m1->add_req(NULL, toc);
2534     m2->add_req(NULL, m1);
2535 
2536     // operands for new nodes
2537     m1->_opnds[0] = new iRegLdstOper(); // dst
2538     m1->_opnds[1] = immSrc;             // src
2539     m1->_opnds[2] = new iRegPdstOper(); // toc
2540     m2->_opnds[0] = new iRegLdstOper(); // dst
2541     m2->_opnds[1] = immSrc;             // src
2542     m2->_opnds[2] = new iRegLdstOper(); // base
2543 
2544     // Initialize ins_attrib TOC fields.
2545     m1->_const_toc_offset = -1;
2546     m2->_const_toc_offset_hi_node = m1;
2547 
2548     // Initialize ins_attrib instruction offset.
2549     m1->_cbuf_insts_offset = -1;
2550 
2551     // register allocation for new nodes
2552     ra_->set_pair(m1->_idx, reg_second, reg_first);
2553     ra_->set_pair(m2->_idx, reg_second, reg_first);
2554 
2555     // Create result.
2556     nodes._large_hi = m1;
2557     nodes._large_lo = m2;
2558     nodes._small = NULL;
2559     nodes._last = nodes._large_lo;
2560     assert(m2->bottom_type()->isa_long(), "must be long");
2561   } else {
2562     loadConLNode *m2 = new loadConLNode();
2563 
2564     // inputs for new nodes
2565     m2->add_req(NULL, toc);
2566 
2567     // operands for new nodes
2568     m2->_opnds[0] = new iRegLdstOper(); // dst
2569     m2->_opnds[1] = immSrc;             // src
2570     m2->_opnds[2] = new iRegPdstOper(); // toc
2571 
2572     // Initialize ins_attrib instruction offset.
2573     m2->_cbuf_insts_offset = -1;
2574 
2575     // register allocation for new nodes
2576     ra_->set_pair(m2->_idx, reg_second, reg_first);
2577 
2578     // Create result.
2579     nodes._large_hi = NULL;
2580     nodes._large_lo = NULL;
2581     nodes._small = m2;
2582     nodes._last = nodes._small;
2583     assert(m2->bottom_type()->isa_long(), "must be long");
2584   }
2585 
2586   return nodes;
2587 }
2588 
2589 %} // source
2590 
2591 encode %{
2592   // Postalloc expand emitter for loading a long constant from the method's TOC.
2593   // Enc_class needed as consttanttablebase is not supported by postalloc
2594   // expand.
2595   enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2596     // Create new nodes.
2597     loadConLNodesTuple loadConLNodes =
2598       loadConLNodesTuple_create(ra_, n_toc, op_src,
2599                                 ra_->get_reg_second(this), ra_->get_reg_first(this));
2600 
2601     // Push new nodes.
2602     if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2603     if (loadConLNodes._last)     nodes->push(loadConLNodes._last);
2604 
2605     // some asserts
2606     assert(nodes->length() >= 1, "must have created at least 1 node");
2607     assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2608   %}
2609 
2610   enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2611     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2612 
2613     MacroAssembler _masm(&cbuf);
2614     int toc_offset = 0;
2615 
2616     if (!ra_->C->in_scratch_emit_size()) {
2617       intptr_t val = $src$$constant;
2618       relocInfo::relocType constant_reloc = $src->constant_reloc();  // src
2619       address const_toc_addr;
2620       if (constant_reloc == relocInfo::oop_type) {
2621         // Create an oop constant and a corresponding relocation.
2622         AddressLiteral a = __ allocate_oop_address((jobject)val);
2623         const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2624         __ relocate(a.rspec());
2625       } else if (constant_reloc == relocInfo::metadata_type) {
2626         AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2627         const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2628         __ relocate(a.rspec());
2629       } else {
2630         // Create a non-oop constant, no relocation needed.
2631         const_toc_addr = __ long_constant((jlong)$src$$constant);
2632       }
2633 
2634       // Get the constant's TOC offset.
2635       toc_offset = __ offset_to_method_toc(const_toc_addr);
2636     }
2637 
2638     __ ld($dst$$Register, toc_offset, $toc$$Register);
2639   %}
2640 
2641   enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2642     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2643 
2644     MacroAssembler _masm(&cbuf);
2645     if (!ra_->C->in_scratch_emit_size()) {
2646       intptr_t val = $src$$constant;
2647       relocInfo::relocType constant_reloc = $src->constant_reloc();  // src
2648       address const_toc_addr;
2649       if (constant_reloc == relocInfo::oop_type) {
2650         // Create an oop constant and a corresponding relocation.
2651         AddressLiteral a = __ allocate_oop_address((jobject)val);
2652         const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2653         __ relocate(a.rspec());
2654       } else if (constant_reloc == relocInfo::metadata_type) {
2655         AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2656         const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2657         __ relocate(a.rspec());
2658       } else {  // non-oop pointers, e.g. card mark base, heap top
2659         // Create a non-oop constant, no relocation needed.
2660         const_toc_addr = __ long_constant((jlong)$src$$constant);
2661       }
2662 
2663       // Get the constant's TOC offset.
2664       const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2665       // Store the toc offset of the constant.
2666       ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2667     }
2668 
2669     __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2670   %}
2671 
2672   // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2673   // Enc_class needed as consttanttablebase is not supported by postalloc
2674   // expand.
2675   enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2676     const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2677     if (large_constant_pool) {
2678       // Create new nodes.
2679       loadConP_hiNode *m1 = new loadConP_hiNode();
2680       loadConP_loNode *m2 = new loadConP_loNode();
2681 
2682       // inputs for new nodes
2683       m1->add_req(NULL, n_toc);
2684       m2->add_req(NULL, m1);
2685 
2686       // operands for new nodes
2687       m1->_opnds[0] = new iRegPdstOper(); // dst
2688       m1->_opnds[1] = op_src;             // src
2689       m1->_opnds[2] = new iRegPdstOper(); // toc
2690       m2->_opnds[0] = new iRegPdstOper(); // dst
2691       m2->_opnds[1] = op_src;             // src
2692       m2->_opnds[2] = new iRegLdstOper(); // base
2693 
2694       // Initialize ins_attrib TOC fields.
2695       m1->_const_toc_offset = -1;
2696       m2->_const_toc_offset_hi_node = m1;
2697 
2698       // Register allocation for new nodes.
2699       ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2700       ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2701 
2702       nodes->push(m1);
2703       nodes->push(m2);
2704       assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2705     } else {
2706       loadConPNode *m2 = new loadConPNode();
2707 
2708       // inputs for new nodes
2709       m2->add_req(NULL, n_toc);
2710 
2711       // operands for new nodes
2712       m2->_opnds[0] = new iRegPdstOper(); // dst
2713       m2->_opnds[1] = op_src;             // src
2714       m2->_opnds[2] = new iRegPdstOper(); // toc
2715 
2716       // Register allocation for new nodes.
2717       ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2718 
2719       nodes->push(m2);
2720       assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2721     }
2722   %}
2723 
2724   // Enc_class needed as consttanttablebase is not supported by postalloc
2725   // expand.
2726   enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2727     bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2728 
2729     MachNode *m2;
2730     if (large_constant_pool) {
2731       m2 = new loadConFCompNode();
2732     } else {
2733       m2 = new loadConFNode();
2734     }
2735     // inputs for new nodes
2736     m2->add_req(NULL, n_toc);
2737 
2738     // operands for new nodes
2739     m2->_opnds[0] = op_dst;
2740     m2->_opnds[1] = op_src;
2741     m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2742 
2743     // register allocation for new nodes
2744     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2745     nodes->push(m2);
2746   %}
2747 
2748   // Enc_class needed as consttanttablebase is not supported by postalloc
2749   // expand.
2750   enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2751     bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2752 
2753     MachNode *m2;
2754     if (large_constant_pool) {
2755       m2 = new loadConDCompNode();
2756     } else {
2757       m2 = new loadConDNode();
2758     }
2759     // inputs for new nodes
2760     m2->add_req(NULL, n_toc);
2761 
2762     // operands for new nodes
2763     m2->_opnds[0] = op_dst;
2764     m2->_opnds[1] = op_src;
2765     m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2766 
2767     // register allocation for new nodes
2768     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2769     nodes->push(m2);
2770   %}
2771 
2772   enc_class enc_stw(iRegIsrc src, memory mem) %{
2773     // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2774     MacroAssembler _masm(&cbuf);
2775     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2776     __ stw($src$$Register, Idisp, $mem$$base$$Register);
2777   %}
2778 
2779   enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2780     // TODO: PPC port $archOpcode(ppc64Opcode_std);
2781     MacroAssembler _masm(&cbuf);
2782     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2783     // Operand 'ds' requires 4-alignment.
2784     assert((Idisp & 0x3) == 0, "unaligned offset");
2785     __ std($src$$Register, Idisp, $mem$$base$$Register);
2786   %}
2787 
2788   enc_class enc_stfs(RegF src, memory mem) %{
2789     // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2790     MacroAssembler _masm(&cbuf);
2791     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2792     __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2793   %}
2794 
2795   enc_class enc_stfd(RegF src, memory mem) %{
2796     // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2797     MacroAssembler _masm(&cbuf);
2798     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2799     __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2800   %}
2801 
2802   // Use release_store for card-marking to ensure that previous
2803   // oop-stores are visible before the card-mark change.
2804   enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
2805     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2806     // FIXME: Implement this as a cmove and use a fixed condition code
2807     // register which is written on every transition to compiled code,
2808     // e.g. in call-stub and when returning from runtime stubs.
2809     //
2810     // Proposed code sequence for the cmove implementation:
2811     //
2812     // Label skip_release;
2813     // __ beq(CCRfixed, skip_release);
2814     // __ release();
2815     // __ bind(skip_release);
2816     // __ stb(card mark);
2817 
2818     MacroAssembler _masm(&cbuf);
2819     Label skip_storestore;
2820 
2821 #if 0 // TODO: PPC port
2822     // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2823     // StoreStore barrier conditionally.
2824     __ lwz(R0, 0, $releaseFieldAddr$$Register);
2825     __ cmpwi($crx$$CondRegister, R0, 0);
2826     __ beq_predict_taken($crx$$CondRegister, skip_storestore);
2827 #endif
2828     __ li(R0, 0);
2829     __ membar(Assembler::StoreStore);
2830 #if 0 // TODO: PPC port
2831     __ bind(skip_storestore);
2832 #endif
2833 
2834     // Do the store.
2835     if ($mem$$index == 0) {
2836       __ stb(R0, $mem$$disp, $mem$$base$$Register);
2837     } else {
2838       assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2839       __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2840     }
2841   %}
2842 
2843   enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2844 
2845     if (VM_Version::has_isel()) {
2846       // use isel instruction with Power 7
2847       cmpP_reg_imm16Node *n_compare  = new cmpP_reg_imm16Node();
2848       encodeP_subNode    *n_sub_base = new encodeP_subNode();
2849       encodeP_shiftNode  *n_shift    = new encodeP_shiftNode();
2850       cond_set_0_oopNode *n_cond_set = new cond_set_0_oopNode();
2851 
2852       n_compare->add_req(n_region, n_src);
2853       n_compare->_opnds[0] = op_crx;
2854       n_compare->_opnds[1] = op_src;
2855       n_compare->_opnds[2] = new immL16Oper(0);
2856 
2857       n_sub_base->add_req(n_region, n_src);
2858       n_sub_base->_opnds[0] = op_dst;
2859       n_sub_base->_opnds[1] = op_src;
2860       n_sub_base->_bottom_type = _bottom_type;
2861 
2862       n_shift->add_req(n_region, n_sub_base);
2863       n_shift->_opnds[0] = op_dst;
2864       n_shift->_opnds[1] = op_dst;
2865       n_shift->_bottom_type = _bottom_type;
2866 
2867       n_cond_set->add_req(n_region, n_compare, n_shift);
2868       n_cond_set->_opnds[0] = op_dst;
2869       n_cond_set->_opnds[1] = op_crx;
2870       n_cond_set->_opnds[2] = op_dst;
2871       n_cond_set->_bottom_type = _bottom_type;
2872 
2873       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2874       ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2875       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2876       ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2877 
2878       nodes->push(n_compare);
2879       nodes->push(n_sub_base);
2880       nodes->push(n_shift);
2881       nodes->push(n_cond_set);
2882 
2883     } else {
2884       // before Power 7
2885       moveRegNode        *n_move     = new moveRegNode();
2886       cmpP_reg_imm16Node *n_compare  = new cmpP_reg_imm16Node();
2887       encodeP_shiftNode  *n_shift    = new encodeP_shiftNode();
2888       cond_sub_baseNode  *n_sub_base = new cond_sub_baseNode();
2889 
2890       n_move->add_req(n_region, n_src);
2891       n_move->_opnds[0] = op_dst;
2892       n_move->_opnds[1] = op_src;
2893       ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2894 
2895       n_compare->add_req(n_region, n_src);
2896       n_compare->add_prec(n_move);
2897 
2898       n_compare->_opnds[0] = op_crx;
2899       n_compare->_opnds[1] = op_src;
2900       n_compare->_opnds[2] = new immL16Oper(0);
2901 
2902       n_sub_base->add_req(n_region, n_compare, n_src);
2903       n_sub_base->_opnds[0] = op_dst;
2904       n_sub_base->_opnds[1] = op_crx;
2905       n_sub_base->_opnds[2] = op_src;
2906       n_sub_base->_bottom_type = _bottom_type;
2907 
2908       n_shift->add_req(n_region, n_sub_base);
2909       n_shift->_opnds[0] = op_dst;
2910       n_shift->_opnds[1] = op_dst;
2911       n_shift->_bottom_type = _bottom_type;
2912 
2913       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2914       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2915       ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2916       ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2917 
2918       nodes->push(n_move);
2919       nodes->push(n_compare);
2920       nodes->push(n_sub_base);
2921       nodes->push(n_shift);
2922     }
2923 
2924     assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2925   %}
2926 
2927   enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
2928 
2929     encodeP_subNode *n1 = new encodeP_subNode();
2930     n1->add_req(n_region, n_src);
2931     n1->_opnds[0] = op_dst;
2932     n1->_opnds[1] = op_src;
2933     n1->_bottom_type = _bottom_type;
2934 
2935     encodeP_shiftNode *n2 = new encodeP_shiftNode();
2936     n2->add_req(n_region, n1);
2937     n2->_opnds[0] = op_dst;
2938     n2->_opnds[1] = op_dst;
2939     n2->_bottom_type = _bottom_type;
2940     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2941     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2942 
2943     nodes->push(n1);
2944     nodes->push(n2);
2945     assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2946   %}
2947 
2948   enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
2949     decodeN_shiftNode *n_shift    = new decodeN_shiftNode();
2950     cmpN_reg_imm0Node *n_compare  = new cmpN_reg_imm0Node();
2951 
2952     n_compare->add_req(n_region, n_src);
2953     n_compare->_opnds[0] = op_crx;
2954     n_compare->_opnds[1] = op_src;
2955     n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
2956 
2957     n_shift->add_req(n_region, n_src);
2958     n_shift->_opnds[0] = op_dst;
2959     n_shift->_opnds[1] = op_src;
2960     n_shift->_bottom_type = _bottom_type;
2961 
2962     if (VM_Version::has_isel()) {
2963       // use isel instruction with Power 7
2964 
2965       decodeN_addNode *n_add_base = new decodeN_addNode();
2966       n_add_base->add_req(n_region, n_shift);
2967       n_add_base->_opnds[0] = op_dst;
2968       n_add_base->_opnds[1] = op_dst;
2969       n_add_base->_bottom_type = _bottom_type;
2970 
2971       cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
2972       n_cond_set->add_req(n_region, n_compare, n_add_base);
2973       n_cond_set->_opnds[0] = op_dst;
2974       n_cond_set->_opnds[1] = op_crx;
2975       n_cond_set->_opnds[2] = op_dst;
2976       n_cond_set->_bottom_type = _bottom_type;
2977 
2978       assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
2979       ra_->set_oop(n_cond_set, true);
2980 
2981       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2982       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2983       ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2984       ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2985 
2986       nodes->push(n_compare);
2987       nodes->push(n_shift);
2988       nodes->push(n_add_base);
2989       nodes->push(n_cond_set);
2990 
2991     } else {
2992       // before Power 7
2993       cond_add_baseNode *n_add_base = new cond_add_baseNode();
2994 
2995       n_add_base->add_req(n_region, n_compare, n_shift);
2996       n_add_base->_opnds[0] = op_dst;
2997       n_add_base->_opnds[1] = op_crx;
2998       n_add_base->_opnds[2] = op_dst;
2999       n_add_base->_bottom_type = _bottom_type;
3000 
3001       assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3002       ra_->set_oop(n_add_base, true);
3003 
3004       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3005       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3006       ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3007 
3008       nodes->push(n_compare);
3009       nodes->push(n_shift);
3010       nodes->push(n_add_base);
3011     }
3012   %}
3013 
3014   enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3015     decodeN_shiftNode *n1 = new decodeN_shiftNode();
3016     n1->add_req(n_region, n_src);
3017     n1->_opnds[0] = op_dst;
3018     n1->_opnds[1] = op_src;
3019     n1->_bottom_type = _bottom_type;
3020 
3021     decodeN_addNode *n2 = new decodeN_addNode();
3022     n2->add_req(n_region, n1);
3023     n2->_opnds[0] = op_dst;
3024     n2->_opnds[1] = op_dst;
3025     n2->_bottom_type = _bottom_type;
3026     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3027     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3028 
3029     assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3030     ra_->set_oop(n2, true);
3031 
3032     nodes->push(n1);
3033     nodes->push(n2);
3034   %}
3035 
3036   enc_class enc_cmove_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src, cmpOp cmp) %{
3037     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3038 
3039     MacroAssembler _masm(&cbuf);
3040     int cc        = $cmp$$cmpcode;
3041     int flags_reg = $crx$$reg;
3042     Label done;
3043     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3044     // Branch if not (cmp crx).
3045     __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3046     __ mr($dst$$Register, $src$$Register);
3047     // TODO PPC port __ endgroup_if_needed(_size == 12);
3048     __ bind(done);
3049   %}
3050 
3051   enc_class enc_cmove_imm(iRegIdst dst, flagsRegSrc crx, immI16 src, cmpOp cmp) %{
3052     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3053 
3054     MacroAssembler _masm(&cbuf);
3055     Label done;
3056     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3057     // Branch if not (cmp crx).
3058     __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3059     __ li($dst$$Register, $src$$constant);
3060     // TODO PPC port __ endgroup_if_needed(_size == 12);
3061     __ bind(done);
3062   %}
3063 
3064   // New atomics.
3065   enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3066     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3067 
3068     MacroAssembler _masm(&cbuf);
3069     Register Rtmp   = R0;
3070     Register Rres   = $res$$Register;
3071     Register Rsrc   = $src$$Register;
3072     Register Rptr   = $mem_ptr$$Register;
3073     bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3074     Register Rold   = RegCollision ? Rtmp : Rres;
3075 
3076     Label Lretry;
3077     __ bind(Lretry);
3078     __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3079     __ add(Rtmp, Rsrc, Rold);
3080     __ stwcx_(Rtmp, Rptr);
3081     if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3082       __ bne_predict_not_taken(CCR0, Lretry);
3083     } else {
3084       __ bne(                  CCR0, Lretry);
3085     }
3086     if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3087     __ fence();
3088   %}
3089 
3090   enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3091     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3092 
3093     MacroAssembler _masm(&cbuf);
3094     Register Rtmp   = R0;
3095     Register Rres   = $res$$Register;
3096     Register Rsrc   = $src$$Register;
3097     Register Rptr   = $mem_ptr$$Register;
3098     bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3099     Register Rold   = RegCollision ? Rtmp : Rres;
3100 
3101     Label Lretry;
3102     __ bind(Lretry);
3103     __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3104     __ add(Rtmp, Rsrc, Rold);
3105     __ stdcx_(Rtmp, Rptr);
3106     if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3107       __ bne_predict_not_taken(CCR0, Lretry);
3108     } else {
3109       __ bne(                  CCR0, Lretry);
3110     }
3111     if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3112     __ fence();
3113   %}
3114 
3115   enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3116     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3117 
3118     MacroAssembler _masm(&cbuf);
3119     Register Rtmp   = R0;
3120     Register Rres   = $res$$Register;
3121     Register Rsrc   = $src$$Register;
3122     Register Rptr   = $mem_ptr$$Register;
3123     bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3124     Register Rold   = RegCollision ? Rtmp : Rres;
3125 
3126     Label Lretry;
3127     __ bind(Lretry);
3128     __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3129     __ stwcx_(Rsrc, Rptr);
3130     if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3131       __ bne_predict_not_taken(CCR0, Lretry);
3132     } else {
3133       __ bne(                  CCR0, Lretry);
3134     }
3135     if (RegCollision) __ mr(Rres, Rtmp);
3136     __ fence();
3137   %}
3138 
3139   enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3140     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3141 
3142     MacroAssembler _masm(&cbuf);
3143     Register Rtmp   = R0;
3144     Register Rres   = $res$$Register;
3145     Register Rsrc   = $src$$Register;
3146     Register Rptr   = $mem_ptr$$Register;
3147     bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3148     Register Rold   = RegCollision ? Rtmp : Rres;
3149 
3150     Label Lretry;
3151     __ bind(Lretry);
3152     __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3153     __ stdcx_(Rsrc, Rptr);
3154     if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3155       __ bne_predict_not_taken(CCR0, Lretry);
3156     } else {
3157       __ bne(                  CCR0, Lretry);
3158     }
3159     if (RegCollision) __ mr(Rres, Rtmp);
3160     __ fence();
3161   %}
3162 
3163   // This enc_class is needed so that scheduler gets proper
3164   // input mapping for latency computation.
3165   enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3166     // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3167     MacroAssembler _masm(&cbuf);
3168     __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3169   %}
3170 
3171   enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3172     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3173 
3174     MacroAssembler _masm(&cbuf);
3175 
3176     Label done;
3177     __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3178     __ li($dst$$Register, $zero$$constant);
3179     __ beq($crx$$CondRegister, done);
3180     __ li($dst$$Register, $notzero$$constant);
3181     __ bind(done);
3182   %}
3183 
3184   enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3185     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3186 
3187     MacroAssembler _masm(&cbuf);
3188 
3189     Label done;
3190     __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3191     __ li($dst$$Register, $zero$$constant);
3192     __ beq($crx$$CondRegister, done);
3193     __ li($dst$$Register, $notzero$$constant);
3194     __ bind(done);
3195   %}
3196 
3197   enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL mem ) %{
3198     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3199 
3200     MacroAssembler _masm(&cbuf);
3201     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3202     Label done;
3203     __ bso($crx$$CondRegister, done);
3204     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3205     // TODO PPC port __ endgroup_if_needed(_size == 12);
3206     __ bind(done);
3207   %}
3208 
3209   enc_class enc_bc(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3210     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3211 
3212     MacroAssembler _masm(&cbuf);
3213     Label d;   // dummy
3214     __ bind(d);
3215     Label* p = ($lbl$$label);
3216     // `p' is `NULL' when this encoding class is used only to
3217     // determine the size of the encoded instruction.
3218     Label& l = (NULL == p)? d : *(p);
3219     int cc = $cmp$$cmpcode;
3220     int flags_reg = $crx$$reg;
3221     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3222     int bhint = Assembler::bhintNoHint;
3223 
3224     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3225       if (_prob <= PROB_NEVER) {
3226         bhint = Assembler::bhintIsNotTaken;
3227       } else if (_prob >= PROB_ALWAYS) {
3228         bhint = Assembler::bhintIsTaken;
3229       }
3230     }
3231 
3232     __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3233           cc_to_biint(cc, flags_reg),
3234           l);
3235   %}
3236 
3237   enc_class enc_bc_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3238     // The scheduler doesn't know about branch shortening, so we set the opcode
3239     // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3240     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3241 
3242     MacroAssembler _masm(&cbuf);
3243     Label d;    // dummy
3244     __ bind(d);
3245     Label* p = ($lbl$$label);
3246     // `p' is `NULL' when this encoding class is used only to
3247     // determine the size of the encoded instruction.
3248     Label& l = (NULL == p)? d : *(p);
3249     int cc = $cmp$$cmpcode;
3250     int flags_reg = $crx$$reg;
3251     int bhint = Assembler::bhintNoHint;
3252 
3253     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3254       if (_prob <= PROB_NEVER) {
3255         bhint = Assembler::bhintIsNotTaken;
3256       } else if (_prob >= PROB_ALWAYS) {
3257         bhint = Assembler::bhintIsTaken;
3258       }
3259     }
3260 
3261     // Tell the conditional far branch to optimize itself when being relocated.
3262     __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3263                   cc_to_biint(cc, flags_reg),
3264                   l,
3265                   MacroAssembler::bc_far_optimize_on_relocate);
3266   %}
3267 
3268   // Branch used with Power6 scheduling (can be shortened without changing the node).
3269   enc_class enc_bc_short_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3270     // The scheduler doesn't know about branch shortening, so we set the opcode
3271     // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3272     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3273 
3274     MacroAssembler _masm(&cbuf);
3275     Label d;   // dummy
3276     __ bind(d);
3277     Label* p = ($lbl$$label);
3278     // `p' is `NULL' when this encoding class is used only to
3279     // determine the size of the encoded instruction.
3280     Label& l = (NULL == p)? d : *(p);
3281     int cc = $cmp$$cmpcode;
3282     int flags_reg = $crx$$reg;
3283     int bhint = Assembler::bhintNoHint;
3284 
3285     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3286       if (_prob <= PROB_NEVER) {
3287         bhint = Assembler::bhintIsNotTaken;
3288       } else if (_prob >= PROB_ALWAYS) {
3289         bhint = Assembler::bhintIsTaken;
3290       }
3291     }
3292 
3293 #if 0 // TODO: PPC port
3294     if (_size == 8) {
3295       // Tell the conditional far branch to optimize itself when being relocated.
3296       __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3297                     cc_to_biint(cc, flags_reg),
3298                     l,
3299                     MacroAssembler::bc_far_optimize_on_relocate);
3300     } else {
3301       __ bc    (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3302                     cc_to_biint(cc, flags_reg),
3303                     l);
3304     }
3305 #endif
3306     Unimplemented();
3307   %}
3308 
3309   // Postalloc expand emitter for loading a replicatef float constant from
3310   // the method's TOC.
3311   // Enc_class needed as consttanttablebase is not supported by postalloc
3312   // expand.
3313   enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3314     // Create new nodes.
3315 
3316     // Make an operand with the bit pattern to load as float.
3317     immLOper *op_repl = new immLOper((jlong)replicate_immF(op_src->constantF()));
3318 
3319     loadConLNodesTuple loadConLNodes =
3320       loadConLNodesTuple_create(ra_, n_toc, op_repl,
3321                                 ra_->get_reg_second(this), ra_->get_reg_first(this));
3322 
3323     // Push new nodes.
3324     if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3325     if (loadConLNodes._last)     nodes->push(loadConLNodes._last);
3326 
3327     assert(nodes->length() >= 1, "must have created at least 1 node");
3328     assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3329   %}
3330 
3331   // This enc_class is needed so that scheduler gets proper
3332   // input mapping for latency computation.
3333   enc_class enc_poll(immI dst, iRegLdst poll) %{
3334     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3335     // Fake operand dst needed for PPC scheduler.
3336     assert($dst$$constant == 0x0, "dst must be 0x0");
3337 
3338     MacroAssembler _masm(&cbuf);
3339     // Mark the code position where the load from the safepoint
3340     // polling page was emitted as relocInfo::poll_type.
3341     __ relocate(relocInfo::poll_type);
3342     __ load_from_polling_page($poll$$Register);
3343   %}
3344 
3345   // A Java static call or a runtime call.
3346   //
3347   // Branch-and-link relative to a trampoline.
3348   // The trampoline loads the target address and does a long branch to there.
3349   // In case we call java, the trampoline branches to a interpreter_stub
3350   // which loads the inline cache and the real call target from the constant pool.
3351   //
3352   // This basically looks like this:
3353   //
3354   // >>>> consts      -+  -+
3355   //                   |   |- offset1
3356   // [call target1]    | <-+
3357   // [IC cache]        |- offset2
3358   // [call target2] <--+
3359   //
3360   // <<<< consts
3361   // >>>> insts
3362   //
3363   // bl offset16               -+  -+             ??? // How many bits available?
3364   //                            |   |
3365   // <<<< insts                 |   |
3366   // >>>> stubs                 |   |
3367   //                            |   |- trampoline_stub_Reloc
3368   // trampoline stub:           | <-+
3369   //   r2 = toc                 |
3370   //   r2 = [r2 + offset1]      |       // Load call target1 from const section
3371   //   mtctr r2                 |
3372   //   bctr                     |- static_stub_Reloc
3373   // comp_to_interp_stub:   <---+
3374   //   r1 = toc
3375   //   ICreg = [r1 + IC_offset]         // Load IC from const section
3376   //   r1    = [r1 + offset2]           // Load call target2 from const section
3377   //   mtctr r1
3378   //   bctr
3379   //
3380   // <<<< stubs
3381   //
3382   // The call instruction in the code either
3383   // - Branches directly to a compiled method if the offset is encodable in instruction.
3384   // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3385   // - Branches to the compiled_to_interp stub if the target is interpreted.
3386   //
3387   // Further there are three relocations from the loads to the constants in
3388   // the constant section.
3389   //
3390   // Usage of r1 and r2 in the stubs allows to distinguish them.
3391   enc_class enc_java_static_call(method meth) %{
3392     // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3393 
3394     MacroAssembler _masm(&cbuf);
3395     address entry_point = (address)$meth$$method;
3396 
3397     if (!_method) {
3398       // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3399       emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3400     } else {
3401       // Remember the offset not the address.
3402       const int start_offset = __ offset();
3403       // The trampoline stub.
3404       if (!Compile::current()->in_scratch_emit_size()) {
3405         // No entry point given, use the current pc.
3406         // Make sure branch fits into
3407         if (entry_point == 0) entry_point = __ pc();
3408 
3409         // Put the entry point as a constant into the constant pool.
3410         const address entry_point_toc_addr   = __ address_constant(entry_point, RelocationHolder::none);
3411         const int     entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3412 
3413         // Emit the trampoline stub which will be related to the branch-and-link below.
3414         CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3415         if (ciEnv::current()->failing()) { return; } // Code cache may be full.
3416         __ relocate(_optimized_virtual ?
3417                     relocInfo::opt_virtual_call_type : relocInfo::static_call_type);
3418       }
3419 
3420       // The real call.
3421       // Note: At this point we do not have the address of the trampoline
3422       // stub, and the entry point might be too far away for bl, so __ pc()
3423       // serves as dummy and the bl will be patched later.
3424       cbuf.set_insts_mark();
3425       __ bl(__ pc());  // Emits a relocation.
3426 
3427       // The stub for call to interpreter.
3428       address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
3429       if (stub == NULL) {
3430         ciEnv::current()->record_failure("CodeCache is full");
3431         return;
3432       }
3433     }
3434   %}
3435 
3436   // Emit a method handle call.
3437   //
3438   // Method handle calls from compiled to compiled are going thru a
3439   // c2i -> i2c adapter, extending the frame for their arguments. The
3440   // caller however, returns directly to the compiled callee, that has
3441   // to cope with the extended frame. We restore the original frame by
3442   // loading the callers sp and adding the calculated framesize.
3443   enc_class enc_java_handle_call(method meth) %{
3444     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3445 
3446     MacroAssembler _masm(&cbuf);
3447     address entry_point = (address)$meth$$method;
3448 
3449     // Remember the offset not the address.
3450     const int start_offset = __ offset();
3451     // The trampoline stub.
3452     if (!ra_->C->in_scratch_emit_size()) {
3453       // No entry point given, use the current pc.
3454       // Make sure branch fits into
3455       if (entry_point == 0) entry_point = __ pc();
3456 
3457       // Put the entry point as a constant into the constant pool.
3458       const address entry_point_toc_addr   = __ address_constant(entry_point, RelocationHolder::none);
3459       const int     entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3460 
3461       // Emit the trampoline stub which will be related to the branch-and-link below.
3462       CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3463       if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3464       assert(_optimized_virtual, "methodHandle call should be a virtual call");
3465       __ relocate(relocInfo::opt_virtual_call_type);
3466     }
3467 
3468     // The real call.
3469     // Note: At this point we do not have the address of the trampoline
3470     // stub, and the entry point might be too far away for bl, so __ pc()
3471     // serves as dummy and the bl will be patched later.
3472     cbuf.set_insts_mark();
3473     __ bl(__ pc());  // Emits a relocation.
3474 
3475     assert(_method, "execute next statement conditionally");
3476     // The stub for call to interpreter.
3477     address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
3478     if (stub == NULL) {
3479       ciEnv::current()->record_failure("CodeCache is full");
3480       return;
3481     }
3482 
3483     // Restore original sp.
3484     __ ld(R11_scratch1, 0, R1_SP); // Load caller sp.
3485     const long framesize = ra_->C->frame_slots() << LogBytesPerInt;
3486     unsigned int bytes = (unsigned int)framesize;
3487     long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
3488     if (Assembler::is_simm(-offset, 16)) {
3489       __ addi(R1_SP, R11_scratch1, -offset);
3490     } else {
3491       __ load_const_optimized(R12_scratch2, -offset);
3492       __ add(R1_SP, R11_scratch1, R12_scratch2);
3493     }
3494 #ifdef ASSERT
3495   __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp.
3496   __ cmpd(CCR0, R11_scratch1, R12_scratch2);
3497   __ asm_assert_eq("backlink changed", 0x8000);
3498 #endif
3499     // If fails should store backlink before unextending.
3500 
3501     if (ra_->C->env()->failing()) {
3502       return;
3503     }
3504   %}
3505 
3506   // Second node of expanded dynamic call - the call.
3507   enc_class enc_java_dynamic_call_sched(method meth) %{
3508     // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3509 
3510     MacroAssembler _masm(&cbuf);
3511 
3512     if (!ra_->C->in_scratch_emit_size()) {
3513       // Create a call trampoline stub for the given method.
3514       const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3515       const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3516       const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3517       CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3518       if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3519 
3520       // Build relocation at call site with ic position as data.
3521       assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3522              (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3523              "must have one, but can't have both");
3524       assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3525              (_load_ic_node != NULL    && _load_ic_node->_cbuf_insts_offset != -1),
3526              "must contain instruction offset");
3527       const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3528         ? _load_ic_hi_node->_cbuf_insts_offset
3529         : _load_ic_node->_cbuf_insts_offset;
3530       const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3531       assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3532              "should be load from TOC");
3533 
3534       __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
3535     }
3536 
3537     // At this point I do not have the address of the trampoline stub,
3538     // and the entry point might be too far away for bl. Pc() serves
3539     // as dummy and bl will be patched later.
3540     __ bl((address) __ pc());
3541   %}
3542 
3543   // postalloc expand emitter for virtual calls.
3544   enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3545 
3546     // Create the nodes for loading the IC from the TOC.
3547     loadConLNodesTuple loadConLNodes_IC =
3548       loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong)Universe::non_oop_word()),
3549                                 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3550 
3551     // Create the call node.
3552     CallDynamicJavaDirectSchedNode *call = new CallDynamicJavaDirectSchedNode();
3553     call->_method_handle_invoke = _method_handle_invoke;
3554     call->_vtable_index      = _vtable_index;
3555     call->_method            = _method;
3556     call->_bci               = _bci;
3557     call->_optimized_virtual = _optimized_virtual;
3558     call->_tf                = _tf;
3559     call->_entry_point       = _entry_point;
3560     call->_cnt               = _cnt;
3561     call->_argsize           = _argsize;
3562     call->_oop_map           = _oop_map;
3563     call->_jvms              = _jvms;
3564     call->_jvmadj            = _jvmadj;
3565     call->_in_rms            = _in_rms;
3566     call->_nesting           = _nesting;
3567 
3568     // New call needs all inputs of old call.
3569     // Req...
3570     for (uint i = 0; i < req(); ++i) {
3571       // The expanded node does not need toc any more.
3572       // Add the inline cache constant here instead. This expresses the
3573       // register of the inline cache must be live at the call.
3574       // Else we would have to adapt JVMState by -1.
3575       if (i == mach_constant_base_node_input()) {
3576         call->add_req(loadConLNodes_IC._last);
3577       } else {
3578         call->add_req(in(i));
3579       }
3580     }
3581     // ...as well as prec
3582     for (uint i = req(); i < len(); ++i) {
3583       call->add_prec(in(i));
3584     }
3585 
3586     // Remember nodes loading the inline cache into r19.
3587     call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3588     call->_load_ic_node    = loadConLNodes_IC._small;
3589 
3590     // Operands for new nodes.
3591     call->_opnds[0] = _opnds[0];
3592     call->_opnds[1] = _opnds[1];
3593 
3594     // Only the inline cache is associated with a register.
3595     assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3596 
3597     // Push new nodes.
3598     if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3599     if (loadConLNodes_IC._last)     nodes->push(loadConLNodes_IC._last);
3600     nodes->push(call);
3601   %}
3602 
3603   // Compound version of call dynamic
3604   // Toc is only passed so that it can be used in ins_encode statement.
3605   // In the code we have to use $constanttablebase.
3606   enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3607     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3608     MacroAssembler _masm(&cbuf);
3609     int start_offset = __ offset();
3610 
3611     Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3612 #if 0
3613     int vtable_index = this->_vtable_index;
3614     if (_vtable_index < 0) {
3615       // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3616       assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3617       Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3618 
3619       // Virtual call relocation will point to ic load.
3620       address virtual_call_meta_addr = __ pc();
3621       // Load a clear inline cache.
3622       AddressLiteral empty_ic((address) Universe::non_oop_word());
3623       __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc);
3624       // CALL to fixup routine.  Fixup routine uses ScopeDesc info
3625       // to determine who we intended to call.
3626       __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3627       emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3628       assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3629              "Fix constant in ret_addr_offset()");
3630     } else {
3631       assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3632       // Go thru the vtable. Get receiver klass. Receiver already
3633       // checked for non-null. If we'll go thru a C2I adapter, the
3634       // interpreter expects method in R19_method.
3635 
3636       __ load_klass(R11_scratch1, R3);
3637 
3638       int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size();
3639       int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes();
3640       __ li(R19_method, v_off);
3641       __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3642       // NOTE: for vtable dispatches, the vtable entry will never be
3643       // null. However it may very well end up in handle_wrong_method
3644       // if the method is abstract for the particular class.
3645       __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3646       // Call target. Either compiled code or C2I adapter.
3647       __ mtctr(R11_scratch1);
3648       __ bctrl();
3649       if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3650         tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3651       }
3652       assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3653              "Fix constant in ret_addr_offset()");
3654     }
3655 #endif
3656     Unimplemented();  // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3657   %}
3658 
3659   // a runtime call
3660   enc_class enc_java_to_runtime_call (method meth) %{
3661     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3662 
3663     MacroAssembler _masm(&cbuf);
3664     const address start_pc = __ pc();
3665 
3666 #if defined(ABI_ELFv2)
3667     address entry= !($meth$$method) ? NULL : (address)$meth$$method;
3668     __ call_c(entry, relocInfo::runtime_call_type);
3669 #else
3670     // The function we're going to call.
3671     FunctionDescriptor fdtemp;
3672     const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3673 
3674     Register Rtoc = R12_scratch2;
3675     // Calculate the method's TOC.
3676     __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3677     // Put entry, env, toc into the constant pool, this needs up to 3 constant
3678     // pool entries; call_c_using_toc will optimize the call.
3679     __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3680 #endif
3681 
3682     // Check the ret_addr_offset.
3683     assert(((MachCallRuntimeNode*)this)->ret_addr_offset() ==  __ last_calls_return_pc() - start_pc,
3684            "Fix constant in ret_addr_offset()");
3685   %}
3686 
3687   // Move to ctr for leaf call.
3688   // This enc_class is needed so that scheduler gets proper
3689   // input mapping for latency computation.
3690   enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3691     // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3692     MacroAssembler _masm(&cbuf);
3693     __ mtctr($src$$Register);
3694   %}
3695 
3696   // Postalloc expand emitter for runtime leaf calls.
3697   enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3698     loadConLNodesTuple loadConLNodes_Entry;
3699 #if defined(ABI_ELFv2)
3700     jlong entry_address = (jlong) this->entry_point();
3701     assert(entry_address, "need address here");
3702     loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3703                                                     OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3704 #else
3705     // Get the struct that describes the function we are about to call.
3706     FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3707     assert(fd, "need fd here");
3708     jlong entry_address = (jlong) fd->entry();
3709     // new nodes
3710     loadConLNodesTuple loadConLNodes_Env;
3711     loadConLNodesTuple loadConLNodes_Toc;
3712 
3713     // Create nodes and operands for loading the entry point.
3714     loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3715                                                     OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3716 
3717 
3718     // Create nodes and operands for loading the env pointer.
3719     if (fd->env() != NULL) {
3720       loadConLNodes_Env = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->env()),
3721                                                     OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3722     } else {
3723       loadConLNodes_Env._large_hi = NULL;
3724       loadConLNodes_Env._large_lo = NULL;
3725       loadConLNodes_Env._small    = NULL;
3726       loadConLNodes_Env._last = new loadConL16Node();
3727       loadConLNodes_Env._last->_opnds[0] = new iRegLdstOper();
3728       loadConLNodes_Env._last->_opnds[1] = new immL16Oper(0);
3729       ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3730     }
3731 
3732     // Create nodes and operands for loading the Toc point.
3733     loadConLNodes_Toc = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->toc()),
3734                                                   OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3735 #endif // ABI_ELFv2
3736     // mtctr node
3737     MachNode *mtctr = new CallLeafDirect_mtctrNode();
3738 
3739     assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3740     mtctr->add_req(0, loadConLNodes_Entry._last);
3741 
3742     mtctr->_opnds[0] = new iRegLdstOper();
3743     mtctr->_opnds[1] = new iRegLdstOper();
3744 
3745     // call node
3746     MachCallLeafNode *call = new CallLeafDirectNode();
3747 
3748     call->_opnds[0] = _opnds[0];
3749     call->_opnds[1] = new methodOper((intptr_t) entry_address); // May get set later.
3750 
3751     // Make the new call node look like the old one.
3752     call->_name        = _name;
3753     call->_tf          = _tf;
3754     call->_entry_point = _entry_point;
3755     call->_cnt         = _cnt;
3756     call->_argsize     = _argsize;
3757     call->_oop_map     = _oop_map;
3758     guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3759     call->_jvms        = NULL;
3760     call->_jvmadj      = _jvmadj;
3761     call->_in_rms      = _in_rms;
3762     call->_nesting     = _nesting;
3763 
3764 
3765     // New call needs all inputs of old call.
3766     // Req...
3767     for (uint i = 0; i < req(); ++i) {
3768       if (i != mach_constant_base_node_input()) {
3769         call->add_req(in(i));
3770       }
3771     }
3772 
3773     // These must be reqired edges, as the registers are live up to
3774     // the call. Else the constants are handled as kills.
3775     call->add_req(mtctr);
3776 #if !defined(ABI_ELFv2)
3777     call->add_req(loadConLNodes_Env._last);
3778     call->add_req(loadConLNodes_Toc._last);
3779 #endif
3780 
3781     // ...as well as prec
3782     for (uint i = req(); i < len(); ++i) {
3783       call->add_prec(in(i));
3784     }
3785 
3786     // registers
3787     ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3788 
3789     // Insert the new nodes.
3790     if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3791     if (loadConLNodes_Entry._last)     nodes->push(loadConLNodes_Entry._last);
3792 #if !defined(ABI_ELFv2)
3793     if (loadConLNodes_Env._large_hi)   nodes->push(loadConLNodes_Env._large_hi);
3794     if (loadConLNodes_Env._last)       nodes->push(loadConLNodes_Env._last);
3795     if (loadConLNodes_Toc._large_hi)   nodes->push(loadConLNodes_Toc._large_hi);
3796     if (loadConLNodes_Toc._last)       nodes->push(loadConLNodes_Toc._last);
3797 #endif
3798     nodes->push(mtctr);
3799     nodes->push(call);
3800   %}
3801 %}
3802 
3803 //----------FRAME--------------------------------------------------------------
3804 // Definition of frame structure and management information.
3805 
3806 frame %{
3807   // What direction does stack grow in (assumed to be same for native & Java).
3808   stack_direction(TOWARDS_LOW);
3809 
3810   // These two registers define part of the calling convention between
3811   // compiled code and the interpreter.
3812 
3813   // Inline Cache Register or method for I2C.
3814   inline_cache_reg(R19); // R19_method
3815 
3816   // Method Oop Register when calling interpreter.
3817   interpreter_method_oop_reg(R19); // R19_method
3818 
3819   // Optional: name the operand used by cisc-spilling to access
3820   // [stack_pointer + offset].
3821   cisc_spilling_operand_name(indOffset);
3822 
3823   // Number of stack slots consumed by a Monitor enter.
3824   sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3825 
3826   // Compiled code's Frame Pointer.
3827   frame_pointer(R1); // R1_SP
3828 
3829   // Interpreter stores its frame pointer in a register which is
3830   // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3831   // interpreted java to compiled java.
3832   //
3833   // R14_state holds pointer to caller's cInterpreter.
3834   interpreter_frame_pointer(R14); // R14_state
3835 
3836   stack_alignment(frame::alignment_in_bytes);
3837 
3838   in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3839 
3840   // Number of outgoing stack slots killed above the
3841   // out_preserve_stack_slots for calls to C. Supports the var-args
3842   // backing area for register parms.
3843   //
3844   varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3845 
3846   // The after-PROLOG location of the return address. Location of
3847   // return address specifies a type (REG or STACK) and a number
3848   // representing the register number (i.e. - use a register name) or
3849   // stack slot.
3850   //
3851   // A: Link register is stored in stack slot ...
3852   // M:  ... but it's in the caller's frame according to PPC-64 ABI.
3853   // J: Therefore, we make sure that the link register is also in R11_scratch1
3854   //    at the end of the prolog.
3855   // B: We use R20, now.
3856   //return_addr(REG R20);
3857 
3858   // G: After reading the comments made by all the luminaries on their
3859   //    failure to tell the compiler where the return address really is,
3860   //    I hardly dare to try myself.  However, I'm convinced it's in slot
3861   //    4 what apparently works and saves us some spills.
3862   return_addr(STACK 4);
3863 
3864   // This is the body of the function
3865   //
3866   // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3867   //                                  uint length,      // length of array
3868   //                                  bool is_outgoing)
3869   //
3870   // The `sig' array is to be updated. sig[j] represents the location
3871   // of the j-th argument, either a register or a stack slot.
3872 
3873   // Comment taken from i486.ad:
3874   // Body of function which returns an integer array locating
3875   // arguments either in registers or in stack slots. Passed an array
3876   // of ideal registers called "sig" and a "length" count. Stack-slot
3877   // offsets are based on outgoing arguments, i.e. a CALLER setting up
3878   // arguments for a CALLEE. Incoming stack arguments are
3879   // automatically biased by the preserve_stack_slots field above.
3880   calling_convention %{
3881     // No difference between ingoing/outgoing. Just pass false.
3882     SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3883   %}
3884 
3885   // Comment taken from i486.ad:
3886   // Body of function which returns an integer array locating
3887   // arguments either in registers or in stack slots. Passed an array
3888   // of ideal registers called "sig" and a "length" count. Stack-slot
3889   // offsets are based on outgoing arguments, i.e. a CALLER setting up
3890   // arguments for a CALLEE. Incoming stack arguments are
3891   // automatically biased by the preserve_stack_slots field above.
3892   c_calling_convention %{
3893     // This is obviously always outgoing.
3894     // C argument in register AND stack slot.
3895     (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3896   %}
3897 
3898   // Location of native (C/C++) and interpreter return values. This
3899   // is specified to be the same as Java. In the 32-bit VM, long
3900   // values are actually returned from native calls in O0:O1 and
3901   // returned to the interpreter in I0:I1. The copying to and from
3902   // the register pairs is done by the appropriate call and epilog
3903   // opcodes. This simplifies the register allocator.
3904   c_return_value %{
3905     assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3906             (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3907             "only return normal values");
3908     // enum names from opcodes.hpp:    Op_Node Op_Set Op_RegN       Op_RegI       Op_RegP       Op_RegF       Op_RegD       Op_RegL
3909     static int typeToRegLo[Op_RegL+1] = { 0,   0,     R3_num,   R3_num,   R3_num,   F1_num,   F1_num,   R3_num };
3910     static int typeToRegHi[Op_RegL+1] = { 0,   0,     OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3911     return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3912   %}
3913 
3914   // Location of compiled Java return values.  Same as C
3915   return_value %{
3916     assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3917             (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3918             "only return normal values");
3919     // enum names from opcodes.hpp:    Op_Node Op_Set Op_RegN       Op_RegI       Op_RegP       Op_RegF       Op_RegD       Op_RegL
3920     static int typeToRegLo[Op_RegL+1] = { 0,   0,     R3_num,   R3_num,   R3_num,   F1_num,   F1_num,   R3_num };
3921     static int typeToRegHi[Op_RegL+1] = { 0,   0,     OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3922     return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3923   %}
3924 %}
3925 
3926 
3927 //----------ATTRIBUTES---------------------------------------------------------
3928 
3929 //----------Operand Attributes-------------------------------------------------
3930 op_attrib op_cost(1);          // Required cost attribute.
3931 
3932 //----------Instruction Attributes---------------------------------------------
3933 
3934 // Cost attribute. required.
3935 ins_attrib ins_cost(DEFAULT_COST);
3936 
3937 // Is this instruction a non-matching short branch variant of some
3938 // long branch? Not required.
3939 ins_attrib ins_short_branch(0);
3940 
3941 ins_attrib ins_is_TrapBasedCheckNode(true);
3942 
3943 // Number of constants.
3944 // This instruction uses the given number of constants
3945 // (optional attribute).
3946 // This is needed to determine in time whether the constant pool will
3947 // exceed 4000 entries. Before postalloc_expand the overall number of constants
3948 // is determined. It's also used to compute the constant pool size
3949 // in Output().
3950 ins_attrib ins_num_consts(0);
3951 
3952 // Required alignment attribute (must be a power of 2) specifies the
3953 // alignment that some part of the instruction (not necessarily the
3954 // start) requires. If > 1, a compute_padding() function must be
3955 // provided for the instruction.
3956 ins_attrib ins_alignment(1);
3957 
3958 // Enforce/prohibit rematerializations.
3959 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
3960 //   then rematerialization of that instruction is prohibited and the
3961 //   instruction's value will be spilled if necessary.
3962 //   Causes that MachNode::rematerialize() returns false.
3963 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
3964 //   then rematerialization should be enforced and a copy of the instruction
3965 //   should be inserted if possible; rematerialization is not guaranteed.
3966 //   Note: this may result in rematerializations in front of every use.
3967 //   Causes that MachNode::rematerialize() can return true.
3968 // (optional attribute)
3969 ins_attrib ins_cannot_rematerialize(false);
3970 ins_attrib ins_should_rematerialize(false);
3971 
3972 // Instruction has variable size depending on alignment.
3973 ins_attrib ins_variable_size_depending_on_alignment(false);
3974 
3975 // Instruction is a nop.
3976 ins_attrib ins_is_nop(false);
3977 
3978 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
3979 ins_attrib ins_use_mach_if_fast_lock_node(false);
3980 
3981 // Field for the toc offset of a constant.
3982 //
3983 // This is needed if the toc offset is not encodable as an immediate in
3984 // the PPC load instruction. If so, the upper (hi) bits of the offset are
3985 // added to the toc, and from this a load with immediate is performed.
3986 // With postalloc expand, we get two nodes that require the same offset
3987 // but which don't know about each other. The offset is only known
3988 // when the constant is added to the constant pool during emitting.
3989 // It is generated in the 'hi'-node adding the upper bits, and saved
3990 // in this node.  The 'lo'-node has a link to the 'hi'-node and reads
3991 // the offset from there when it gets encoded.
3992 ins_attrib ins_field_const_toc_offset(0);
3993 ins_attrib ins_field_const_toc_offset_hi_node(0);
3994 
3995 // A field that can hold the instructions offset in the code buffer.
3996 // Set in the nodes emitter.
3997 ins_attrib ins_field_cbuf_insts_offset(-1);
3998 
3999 // Fields for referencing a call's load-IC-node.
4000 // If the toc offset can not be encoded as an immediate in a load, we
4001 // use two nodes.
4002 ins_attrib ins_field_load_ic_hi_node(0);
4003 ins_attrib ins_field_load_ic_node(0);
4004 
4005 //----------OPERANDS-----------------------------------------------------------
4006 // Operand definitions must precede instruction definitions for correct
4007 // parsing in the ADLC because operands constitute user defined types
4008 // which are used in instruction definitions.
4009 //
4010 // Formats are generated automatically for constants and base registers.
4011 
4012 //----------Simple Operands----------------------------------------------------
4013 // Immediate Operands
4014 
4015 // Integer Immediate: 32-bit
4016 operand immI() %{
4017   match(ConI);
4018   op_cost(40);
4019   format %{ %}
4020   interface(CONST_INTER);
4021 %}
4022 
4023 operand immI8() %{
4024   predicate(Assembler::is_simm(n->get_int(), 8));
4025   op_cost(0);
4026   match(ConI);
4027   format %{ %}
4028   interface(CONST_INTER);
4029 %}
4030 
4031 // Integer Immediate: 16-bit
4032 operand immI16() %{
4033   predicate(Assembler::is_simm(n->get_int(), 16));
4034   op_cost(0);
4035   match(ConI);
4036   format %{ %}
4037   interface(CONST_INTER);
4038 %}
4039 
4040 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
4041 operand immIhi16() %{
4042   predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
4043   match(ConI);
4044   op_cost(0);
4045   format %{ %}
4046   interface(CONST_INTER);
4047 %}
4048 
4049 operand immInegpow2() %{
4050   predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
4051   match(ConI);
4052   op_cost(0);
4053   format %{ %}
4054   interface(CONST_INTER);
4055 %}
4056 
4057 operand immIpow2minus1() %{
4058   predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
4059   match(ConI);
4060   op_cost(0);
4061   format %{ %}
4062   interface(CONST_INTER);
4063 %}
4064 
4065 operand immIpowerOf2() %{
4066   predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
4067   match(ConI);
4068   op_cost(0);
4069   format %{ %}
4070   interface(CONST_INTER);
4071 %}
4072 
4073 // Unsigned Integer Immediate: the values 0-31
4074 operand uimmI5() %{
4075   predicate(Assembler::is_uimm(n->get_int(), 5));
4076   match(ConI);
4077   op_cost(0);
4078   format %{ %}
4079   interface(CONST_INTER);
4080 %}
4081 
4082 // Unsigned Integer Immediate: 6-bit
4083 operand uimmI6() %{
4084   predicate(Assembler::is_uimm(n->get_int(), 6));
4085   match(ConI);
4086   op_cost(0);
4087   format %{ %}
4088   interface(CONST_INTER);
4089 %}
4090 
4091 // Unsigned Integer Immediate:  6-bit int, greater than 32
4092 operand uimmI6_ge32() %{
4093   predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
4094   match(ConI);
4095   op_cost(0);
4096   format %{ %}
4097   interface(CONST_INTER);
4098 %}
4099 
4100 // Unsigned Integer Immediate: 15-bit
4101 operand uimmI15() %{
4102   predicate(Assembler::is_uimm(n->get_int(), 15));
4103   match(ConI);
4104   op_cost(0);
4105   format %{ %}
4106   interface(CONST_INTER);
4107 %}
4108 
4109 // Unsigned Integer Immediate: 16-bit
4110 operand uimmI16() %{
4111   predicate(Assembler::is_uimm(n->get_int(), 16));
4112   match(ConI);
4113   op_cost(0);
4114   format %{ %}
4115   interface(CONST_INTER);
4116 %}
4117 
4118 // constant 'int 0'.
4119 operand immI_0() %{
4120   predicate(n->get_int() == 0);
4121   match(ConI);
4122   op_cost(0);
4123   format %{ %}
4124   interface(CONST_INTER);
4125 %}
4126 
4127 // constant 'int 1'.
4128 operand immI_1() %{
4129   predicate(n->get_int() == 1);
4130   match(ConI);
4131   op_cost(0);
4132   format %{ %}
4133   interface(CONST_INTER);
4134 %}
4135 
4136 // constant 'int -1'.
4137 operand immI_minus1() %{
4138   predicate(n->get_int() == -1);
4139   match(ConI);
4140   op_cost(0);
4141   format %{ %}
4142   interface(CONST_INTER);
4143 %}
4144 
4145 // int value 16.
4146 operand immI_16() %{
4147   predicate(n->get_int() == 16);
4148   match(ConI);
4149   op_cost(0);
4150   format %{ %}
4151   interface(CONST_INTER);
4152 %}
4153 
4154 // int value 24.
4155 operand immI_24() %{
4156   predicate(n->get_int() == 24);
4157   match(ConI);
4158   op_cost(0);
4159   format %{ %}
4160   interface(CONST_INTER);
4161 %}
4162 
4163 // Compressed oops constants
4164 // Pointer Immediate
4165 operand immN() %{
4166   match(ConN);
4167 
4168   op_cost(10);
4169   format %{ %}
4170   interface(CONST_INTER);
4171 %}
4172 
4173 // NULL Pointer Immediate
4174 operand immN_0() %{
4175   predicate(n->get_narrowcon() == 0);
4176   match(ConN);
4177 
4178   op_cost(0);
4179   format %{ %}
4180   interface(CONST_INTER);
4181 %}
4182 
4183 // Compressed klass constants
4184 operand immNKlass() %{
4185   match(ConNKlass);
4186 
4187   op_cost(0);
4188   format %{ %}
4189   interface(CONST_INTER);
4190 %}
4191 
4192 // This operand can be used to avoid matching of an instruct
4193 // with chain rule.
4194 operand immNKlass_NM() %{
4195   match(ConNKlass);
4196   predicate(false);
4197   op_cost(0);
4198   format %{ %}
4199   interface(CONST_INTER);
4200 %}
4201 
4202 // Pointer Immediate: 64-bit
4203 operand immP() %{
4204   match(ConP);
4205   op_cost(0);
4206   format %{ %}
4207   interface(CONST_INTER);
4208 %}
4209 
4210 // Operand to avoid match of loadConP.
4211 // This operand can be used to avoid matching of an instruct
4212 // with chain rule.
4213 operand immP_NM() %{
4214   match(ConP);
4215   predicate(false);
4216   op_cost(0);
4217   format %{ %}
4218   interface(CONST_INTER);
4219 %}
4220 
4221 // costant 'pointer 0'.
4222 operand immP_0() %{
4223   predicate(n->get_ptr() == 0);
4224   match(ConP);
4225   op_cost(0);
4226   format %{ %}
4227   interface(CONST_INTER);
4228 %}
4229 
4230 // pointer 0x0 or 0x1
4231 operand immP_0or1() %{
4232   predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4233   match(ConP);
4234   op_cost(0);
4235   format %{ %}
4236   interface(CONST_INTER);
4237 %}
4238 
4239 operand immL() %{
4240   match(ConL);
4241   op_cost(40);
4242   format %{ %}
4243   interface(CONST_INTER);
4244 %}
4245 
4246 // Long Immediate: 16-bit
4247 operand immL16() %{
4248   predicate(Assembler::is_simm(n->get_long(), 16));
4249   match(ConL);
4250   op_cost(0);
4251   format %{ %}
4252   interface(CONST_INTER);
4253 %}
4254 
4255 // Long Immediate: 16-bit, 4-aligned
4256 operand immL16Alg4() %{
4257   predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4258   match(ConL);
4259   op_cost(0);
4260   format %{ %}
4261   interface(CONST_INTER);
4262 %}
4263 
4264 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4265 operand immL32hi16() %{
4266   predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4267   match(ConL);
4268   op_cost(0);
4269   format %{ %}
4270   interface(CONST_INTER);
4271 %}
4272 
4273 // Long Immediate: 32-bit
4274 operand immL32() %{
4275   predicate(Assembler::is_simm(n->get_long(), 32));
4276   match(ConL);
4277   op_cost(0);
4278   format %{ %}
4279   interface(CONST_INTER);
4280 %}
4281 
4282 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4283 operand immLhighest16() %{
4284   predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4285   match(ConL);
4286   op_cost(0);
4287   format %{ %}
4288   interface(CONST_INTER);
4289 %}
4290 
4291 operand immLnegpow2() %{
4292   predicate(is_power_of_2_long((jlong)-(n->get_long())));
4293   match(ConL);
4294   op_cost(0);
4295   format %{ %}
4296   interface(CONST_INTER);
4297 %}
4298 
4299 operand immLpow2minus1() %{
4300   predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4301             (n->get_long() != (jlong)0xffffffffffffffffL));
4302   match(ConL);
4303   op_cost(0);
4304   format %{ %}
4305   interface(CONST_INTER);
4306 %}
4307 
4308 // constant 'long 0'.
4309 operand immL_0() %{
4310   predicate(n->get_long() == 0L);
4311   match(ConL);
4312   op_cost(0);
4313   format %{ %}
4314   interface(CONST_INTER);
4315 %}
4316 
4317 // constat ' long -1'.
4318 operand immL_minus1() %{
4319   predicate(n->get_long() == -1L);
4320   match(ConL);
4321   op_cost(0);
4322   format %{ %}
4323   interface(CONST_INTER);
4324 %}
4325 
4326 // Long Immediate: low 32-bit mask
4327 operand immL_32bits() %{
4328   predicate(n->get_long() == 0xFFFFFFFFL);
4329   match(ConL);
4330   op_cost(0);
4331   format %{ %}
4332   interface(CONST_INTER);
4333 %}
4334 
4335 // Unsigned Long Immediate: 16-bit
4336 operand uimmL16() %{
4337   predicate(Assembler::is_uimm(n->get_long(), 16));
4338   match(ConL);
4339   op_cost(0);
4340   format %{ %}
4341   interface(CONST_INTER);
4342 %}
4343 
4344 // Float Immediate
4345 operand immF() %{
4346   match(ConF);
4347   op_cost(40);
4348   format %{ %}
4349   interface(CONST_INTER);
4350 %}
4351 
4352 // Float Immediate: +0.0f.
4353 operand immF_0() %{
4354   predicate(jint_cast(n->getf()) == 0);
4355   match(ConF);
4356 
4357   op_cost(0);
4358   format %{ %}
4359   interface(CONST_INTER);
4360 %}
4361 
4362 // Double Immediate
4363 operand immD() %{
4364   match(ConD);
4365   op_cost(40);
4366   format %{ %}
4367   interface(CONST_INTER);
4368 %}
4369 
4370 // Integer Register Operands
4371 // Integer Destination Register
4372 // See definition of reg_class bits32_reg_rw.
4373 operand iRegIdst() %{
4374   constraint(ALLOC_IN_RC(bits32_reg_rw));
4375   match(RegI);
4376   match(rscratch1RegI);
4377   match(rscratch2RegI);
4378   match(rarg1RegI);
4379   match(rarg2RegI);
4380   match(rarg3RegI);
4381   match(rarg4RegI);
4382   format %{ %}
4383   interface(REG_INTER);
4384 %}
4385 
4386 // Integer Source Register
4387 // See definition of reg_class bits32_reg_ro.
4388 operand iRegIsrc() %{
4389   constraint(ALLOC_IN_RC(bits32_reg_ro));
4390   match(RegI);
4391   match(rscratch1RegI);
4392   match(rscratch2RegI);
4393   match(rarg1RegI);
4394   match(rarg2RegI);
4395   match(rarg3RegI);
4396   match(rarg4RegI);
4397   format %{ %}
4398   interface(REG_INTER);
4399 %}
4400 
4401 operand rscratch1RegI() %{
4402   constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4403   match(iRegIdst);
4404   format %{ %}
4405   interface(REG_INTER);
4406 %}
4407 
4408 operand rscratch2RegI() %{
4409   constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4410   match(iRegIdst);
4411   format %{ %}
4412   interface(REG_INTER);
4413 %}
4414 
4415 operand rarg1RegI() %{
4416   constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4417   match(iRegIdst);
4418   format %{ %}
4419   interface(REG_INTER);
4420 %}
4421 
4422 operand rarg2RegI() %{
4423   constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4424   match(iRegIdst);
4425   format %{ %}
4426   interface(REG_INTER);
4427 %}
4428 
4429 operand rarg3RegI() %{
4430   constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4431   match(iRegIdst);
4432   format %{ %}
4433   interface(REG_INTER);
4434 %}
4435 
4436 operand rarg4RegI() %{
4437   constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4438   match(iRegIdst);
4439   format %{ %}
4440   interface(REG_INTER);
4441 %}
4442 
4443 operand rarg1RegL() %{
4444   constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4445   match(iRegLdst);
4446   format %{ %}
4447   interface(REG_INTER);
4448 %}
4449 
4450 operand rarg2RegL() %{
4451   constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4452   match(iRegLdst);
4453   format %{ %}
4454   interface(REG_INTER);
4455 %}
4456 
4457 operand rarg3RegL() %{
4458   constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4459   match(iRegLdst);
4460   format %{ %}
4461   interface(REG_INTER);
4462 %}
4463 
4464 operand rarg4RegL() %{
4465   constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4466   match(iRegLdst);
4467   format %{ %}
4468   interface(REG_INTER);
4469 %}
4470 
4471 // Pointer Destination Register
4472 // See definition of reg_class bits64_reg_rw.
4473 operand iRegPdst() %{
4474   constraint(ALLOC_IN_RC(bits64_reg_rw));
4475   match(RegP);
4476   match(rscratch1RegP);
4477   match(rscratch2RegP);
4478   match(rarg1RegP);
4479   match(rarg2RegP);
4480   match(rarg3RegP);
4481   match(rarg4RegP);
4482   format %{ %}
4483   interface(REG_INTER);
4484 %}
4485 
4486 // Pointer Destination Register
4487 // Operand not using r11 and r12 (killed in epilog).
4488 operand iRegPdstNoScratch() %{
4489   constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4490   match(RegP);
4491   match(rarg1RegP);
4492   match(rarg2RegP);
4493   match(rarg3RegP);
4494   match(rarg4RegP);
4495   format %{ %}
4496   interface(REG_INTER);
4497 %}
4498 
4499 // Pointer Source Register
4500 // See definition of reg_class bits64_reg_ro.
4501 operand iRegPsrc() %{
4502   constraint(ALLOC_IN_RC(bits64_reg_ro));
4503   match(RegP);
4504   match(iRegPdst);
4505   match(rscratch1RegP);
4506   match(rscratch2RegP);
4507   match(rarg1RegP);
4508   match(rarg2RegP);
4509   match(rarg3RegP);
4510   match(rarg4RegP);
4511   match(threadRegP);
4512   format %{ %}
4513   interface(REG_INTER);
4514 %}
4515 
4516 // Thread operand.
4517 operand threadRegP() %{
4518   constraint(ALLOC_IN_RC(thread_bits64_reg));
4519   match(iRegPdst);
4520   format %{ "R16" %}
4521   interface(REG_INTER);
4522 %}
4523 
4524 operand rscratch1RegP() %{
4525   constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4526   match(iRegPdst);
4527   format %{ "R11" %}
4528   interface(REG_INTER);
4529 %}
4530 
4531 operand rscratch2RegP() %{
4532   constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4533   match(iRegPdst);
4534   format %{ %}
4535   interface(REG_INTER);
4536 %}
4537 
4538 operand rarg1RegP() %{
4539   constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4540   match(iRegPdst);
4541   format %{ %}
4542   interface(REG_INTER);
4543 %}
4544 
4545 operand rarg2RegP() %{
4546   constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4547   match(iRegPdst);
4548   format %{ %}
4549   interface(REG_INTER);
4550 %}
4551 
4552 operand rarg3RegP() %{
4553   constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4554   match(iRegPdst);
4555   format %{ %}
4556   interface(REG_INTER);
4557 %}
4558 
4559 operand rarg4RegP() %{
4560   constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4561   match(iRegPdst);
4562   format %{ %}
4563   interface(REG_INTER);
4564 %}
4565 
4566 operand iRegNsrc() %{
4567   constraint(ALLOC_IN_RC(bits32_reg_ro));
4568   match(RegN);
4569   match(iRegNdst);
4570 
4571   format %{ %}
4572   interface(REG_INTER);
4573 %}
4574 
4575 operand iRegNdst() %{
4576   constraint(ALLOC_IN_RC(bits32_reg_rw));
4577   match(RegN);
4578 
4579   format %{ %}
4580   interface(REG_INTER);
4581 %}
4582 
4583 // Long Destination Register
4584 // See definition of reg_class bits64_reg_rw.
4585 operand iRegLdst() %{
4586   constraint(ALLOC_IN_RC(bits64_reg_rw));
4587   match(RegL);
4588   match(rscratch1RegL);
4589   match(rscratch2RegL);
4590   format %{ %}
4591   interface(REG_INTER);
4592 %}
4593 
4594 // Long Source Register
4595 // See definition of reg_class bits64_reg_ro.
4596 operand iRegLsrc() %{
4597   constraint(ALLOC_IN_RC(bits64_reg_ro));
4598   match(RegL);
4599   match(iRegLdst);
4600   match(rscratch1RegL);
4601   match(rscratch2RegL);
4602   format %{ %}
4603   interface(REG_INTER);
4604 %}
4605 
4606 // Special operand for ConvL2I.
4607 operand iRegL2Isrc(iRegLsrc reg) %{
4608   constraint(ALLOC_IN_RC(bits64_reg_ro));
4609   match(ConvL2I reg);
4610   format %{ "ConvL2I($reg)" %}
4611   interface(REG_INTER)
4612 %}
4613 
4614 operand rscratch1RegL() %{
4615   constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4616   match(RegL);
4617   format %{ %}
4618   interface(REG_INTER);
4619 %}
4620 
4621 operand rscratch2RegL() %{
4622   constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4623   match(RegL);
4624   format %{ %}
4625   interface(REG_INTER);
4626 %}
4627 
4628 // Condition Code Flag Registers
4629 operand flagsReg() %{
4630   constraint(ALLOC_IN_RC(int_flags));
4631   match(RegFlags);
4632   format %{ %}
4633   interface(REG_INTER);
4634 %}
4635 
4636 operand flagsRegSrc() %{
4637   constraint(ALLOC_IN_RC(int_flags_ro));
4638   match(RegFlags);
4639   match(flagsReg);
4640   match(flagsRegCR0);
4641   format %{ %}
4642   interface(REG_INTER);
4643 %}
4644 
4645 // Condition Code Flag Register CR0
4646 operand flagsRegCR0() %{
4647   constraint(ALLOC_IN_RC(int_flags_CR0));
4648   match(RegFlags);
4649   format %{ "CR0" %}
4650   interface(REG_INTER);
4651 %}
4652 
4653 operand flagsRegCR1() %{
4654   constraint(ALLOC_IN_RC(int_flags_CR1));
4655   match(RegFlags);
4656   format %{ "CR1" %}
4657   interface(REG_INTER);
4658 %}
4659 
4660 operand flagsRegCR6() %{
4661   constraint(ALLOC_IN_RC(int_flags_CR6));
4662   match(RegFlags);
4663   format %{ "CR6" %}
4664   interface(REG_INTER);
4665 %}
4666 
4667 operand regCTR() %{
4668   constraint(ALLOC_IN_RC(ctr_reg));
4669   // RegFlags should work. Introducing a RegSpecial type would cause a
4670   // lot of changes.
4671   match(RegFlags);
4672   format %{"SR_CTR" %}
4673   interface(REG_INTER);
4674 %}
4675 
4676 operand regD() %{
4677   constraint(ALLOC_IN_RC(dbl_reg));
4678   match(RegD);
4679   format %{ %}
4680   interface(REG_INTER);
4681 %}
4682 
4683 operand regF() %{
4684   constraint(ALLOC_IN_RC(flt_reg));
4685   match(RegF);
4686   format %{ %}
4687   interface(REG_INTER);
4688 %}
4689 
4690 // Special Registers
4691 
4692 // Method Register
4693 operand inline_cache_regP(iRegPdst reg) %{
4694   constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4695   match(reg);
4696   format %{ %}
4697   interface(REG_INTER);
4698 %}
4699 
4700 operand compiler_method_oop_regP(iRegPdst reg) %{
4701   constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4702   match(reg);
4703   format %{ %}
4704   interface(REG_INTER);
4705 %}
4706 
4707 operand interpreter_method_oop_regP(iRegPdst reg) %{
4708   constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4709   match(reg);
4710   format %{ %}
4711   interface(REG_INTER);
4712 %}
4713 
4714 // Operands to remove register moves in unscaled mode.
4715 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4716 operand iRegP2N(iRegPsrc reg) %{
4717   predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4718   constraint(ALLOC_IN_RC(bits64_reg_ro));
4719   match(EncodeP reg);
4720   format %{ "$reg" %}
4721   interface(REG_INTER)
4722 %}
4723 
4724 operand iRegN2P(iRegNsrc reg) %{
4725   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4726   constraint(ALLOC_IN_RC(bits32_reg_ro));
4727   match(DecodeN reg);
4728   format %{ "$reg" %}
4729   interface(REG_INTER)
4730 %}
4731 
4732 operand iRegN2P_klass(iRegNsrc reg) %{
4733   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4734   constraint(ALLOC_IN_RC(bits32_reg_ro));
4735   match(DecodeNKlass reg);
4736   format %{ "$reg" %}
4737   interface(REG_INTER)
4738 %}
4739 
4740 //----------Complex Operands---------------------------------------------------
4741 // Indirect Memory Reference
4742 operand indirect(iRegPsrc reg) %{
4743   constraint(ALLOC_IN_RC(bits64_reg_ro));
4744   match(reg);
4745   op_cost(100);
4746   format %{ "[$reg]" %}
4747   interface(MEMORY_INTER) %{
4748     base($reg);
4749     index(0x0);
4750     scale(0x0);
4751     disp(0x0);
4752   %}
4753 %}
4754 
4755 // Indirect with Offset
4756 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4757   constraint(ALLOC_IN_RC(bits64_reg_ro));
4758   match(AddP reg offset);
4759   op_cost(100);
4760   format %{ "[$reg + $offset]" %}
4761   interface(MEMORY_INTER) %{
4762     base($reg);
4763     index(0x0);
4764     scale(0x0);
4765     disp($offset);
4766   %}
4767 %}
4768 
4769 // Indirect with 4-aligned Offset
4770 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4771   constraint(ALLOC_IN_RC(bits64_reg_ro));
4772   match(AddP reg offset);
4773   op_cost(100);
4774   format %{ "[$reg + $offset]" %}
4775   interface(MEMORY_INTER) %{
4776     base($reg);
4777     index(0x0);
4778     scale(0x0);
4779     disp($offset);
4780   %}
4781 %}
4782 
4783 //----------Complex Operands for Compressed OOPs-------------------------------
4784 // Compressed OOPs with narrow_oop_shift == 0.
4785 
4786 // Indirect Memory Reference, compressed OOP
4787 operand indirectNarrow(iRegNsrc reg) %{
4788   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4789   constraint(ALLOC_IN_RC(bits64_reg_ro));
4790   match(DecodeN reg);
4791   op_cost(100);
4792   format %{ "[$reg]" %}
4793   interface(MEMORY_INTER) %{
4794     base($reg);
4795     index(0x0);
4796     scale(0x0);
4797     disp(0x0);
4798   %}
4799 %}
4800 
4801 operand indirectNarrow_klass(iRegNsrc reg) %{
4802   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4803   constraint(ALLOC_IN_RC(bits64_reg_ro));
4804   match(DecodeNKlass reg);
4805   op_cost(100);
4806   format %{ "[$reg]" %}
4807   interface(MEMORY_INTER) %{
4808     base($reg);
4809     index(0x0);
4810     scale(0x0);
4811     disp(0x0);
4812   %}
4813 %}
4814 
4815 // Indirect with Offset, compressed OOP
4816 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4817   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4818   constraint(ALLOC_IN_RC(bits64_reg_ro));
4819   match(AddP (DecodeN reg) offset);
4820   op_cost(100);
4821   format %{ "[$reg + $offset]" %}
4822   interface(MEMORY_INTER) %{
4823     base($reg);
4824     index(0x0);
4825     scale(0x0);
4826     disp($offset);
4827   %}
4828 %}
4829 
4830 operand indOffset16Narrow_klass(iRegNsrc reg, immL16 offset) %{
4831   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4832   constraint(ALLOC_IN_RC(bits64_reg_ro));
4833   match(AddP (DecodeNKlass reg) offset);
4834   op_cost(100);
4835   format %{ "[$reg + $offset]" %}
4836   interface(MEMORY_INTER) %{
4837     base($reg);
4838     index(0x0);
4839     scale(0x0);
4840     disp($offset);
4841   %}
4842 %}
4843 
4844 // Indirect with 4-aligned Offset, compressed OOP
4845 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4846   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4847   constraint(ALLOC_IN_RC(bits64_reg_ro));
4848   match(AddP (DecodeN reg) offset);
4849   op_cost(100);
4850   format %{ "[$reg + $offset]" %}
4851   interface(MEMORY_INTER) %{
4852     base($reg);
4853     index(0x0);
4854     scale(0x0);
4855     disp($offset);
4856   %}
4857 %}
4858 
4859 operand indOffset16NarrowAlg4_klass(iRegNsrc reg, immL16Alg4 offset) %{
4860   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4861   constraint(ALLOC_IN_RC(bits64_reg_ro));
4862   match(AddP (DecodeNKlass reg) offset);
4863   op_cost(100);
4864   format %{ "[$reg + $offset]" %}
4865   interface(MEMORY_INTER) %{
4866     base($reg);
4867     index(0x0);
4868     scale(0x0);
4869     disp($offset);
4870   %}
4871 %}
4872 
4873 //----------Special Memory Operands--------------------------------------------
4874 // Stack Slot Operand
4875 //
4876 // This operand is used for loading and storing temporary values on
4877 // the stack where a match requires a value to flow through memory.
4878 operand stackSlotI(sRegI reg) %{
4879   constraint(ALLOC_IN_RC(stack_slots));
4880   op_cost(100);
4881   //match(RegI);
4882   format %{ "[sp+$reg]" %}
4883   interface(MEMORY_INTER) %{
4884     base(0x1);   // R1_SP
4885     index(0x0);
4886     scale(0x0);
4887     disp($reg);  // Stack Offset
4888   %}
4889 %}
4890 
4891 operand stackSlotL(sRegL reg) %{
4892   constraint(ALLOC_IN_RC(stack_slots));
4893   op_cost(100);
4894   //match(RegL);
4895   format %{ "[sp+$reg]" %}
4896   interface(MEMORY_INTER) %{
4897     base(0x1);   // R1_SP
4898     index(0x0);
4899     scale(0x0);
4900     disp($reg);  // Stack Offset
4901   %}
4902 %}
4903 
4904 operand stackSlotP(sRegP reg) %{
4905   constraint(ALLOC_IN_RC(stack_slots));
4906   op_cost(100);
4907   //match(RegP);
4908   format %{ "[sp+$reg]" %}
4909   interface(MEMORY_INTER) %{
4910     base(0x1);   // R1_SP
4911     index(0x0);
4912     scale(0x0);
4913     disp($reg);  // Stack Offset
4914   %}
4915 %}
4916 
4917 operand stackSlotF(sRegF reg) %{
4918   constraint(ALLOC_IN_RC(stack_slots));
4919   op_cost(100);
4920   //match(RegF);
4921   format %{ "[sp+$reg]" %}
4922   interface(MEMORY_INTER) %{
4923     base(0x1);   // R1_SP
4924     index(0x0);
4925     scale(0x0);
4926     disp($reg);  // Stack Offset
4927   %}
4928 %}
4929 
4930 operand stackSlotD(sRegD reg) %{
4931   constraint(ALLOC_IN_RC(stack_slots));
4932   op_cost(100);
4933   //match(RegD);
4934   format %{ "[sp+$reg]" %}
4935   interface(MEMORY_INTER) %{
4936     base(0x1);   // R1_SP
4937     index(0x0);
4938     scale(0x0);
4939     disp($reg);  // Stack Offset
4940   %}
4941 %}
4942 
4943 // Operands for expressing Control Flow
4944 // NOTE: Label is a predefined operand which should not be redefined in
4945 //       the AD file. It is generically handled within the ADLC.
4946 
4947 //----------Conditional Branch Operands----------------------------------------
4948 // Comparison Op
4949 //
4950 // This is the operation of the comparison, and is limited to the
4951 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4952 // (!=).
4953 //
4954 // Other attributes of the comparison, such as unsignedness, are specified
4955 // by the comparison instruction that sets a condition code flags register.
4956 // That result is represented by a flags operand whose subtype is appropriate
4957 // to the unsignedness (etc.) of the comparison.
4958 //
4959 // Later, the instruction which matches both the Comparison Op (a Bool) and
4960 // the flags (produced by the Cmp) specifies the coding of the comparison op
4961 // by matching a specific subtype of Bool operand below.
4962 
4963 // When used for floating point comparisons: unordered same as less.
4964 operand cmpOp() %{
4965   match(Bool);
4966   format %{ "" %}
4967   interface(COND_INTER) %{
4968                            // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4969                            //           BO          &  BI
4970     equal(0xA);            // 10 10:   bcondCRbiIs1 & Condition::equal
4971     not_equal(0x2);        // 00 10:   bcondCRbiIs0 & Condition::equal
4972     less(0x8);             // 10 00:   bcondCRbiIs1 & Condition::less
4973     greater_equal(0x0);    // 00 00:   bcondCRbiIs0 & Condition::less
4974     less_equal(0x1);       // 00 01:   bcondCRbiIs0 & Condition::greater
4975     greater(0x9);          // 10 01:   bcondCRbiIs1 & Condition::greater
4976     overflow(0xB);         // 10 11:   bcondCRbiIs1 & Condition::summary_overflow
4977     no_overflow(0x3);      // 00 11:   bcondCRbiIs0 & Condition::summary_overflow
4978   %}
4979 %}
4980 
4981 //----------OPERAND CLASSES----------------------------------------------------
4982 // Operand Classes are groups of operands that are used to simplify
4983 // instruction definitions by not requiring the AD writer to specify
4984 // seperate instructions for every form of operand when the
4985 // instruction accepts multiple operand types with the same basic
4986 // encoding and format. The classic case of this is memory operands.
4987 // Indirect is not included since its use is limited to Compare & Swap.
4988 
4989 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indirectNarrow_klass, indOffset16Narrow, indOffset16Narrow_klass);
4990 // Memory operand where offsets are 4-aligned. Required for ld, std.
4991 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4, indOffset16NarrowAlg4_klass);
4992 opclass indirectMemory(indirect, indirectNarrow);
4993 
4994 // Special opclass for I and ConvL2I.
4995 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
4996 
4997 // Operand classes to match encode and decode. iRegN_P2N is only used
4998 // for storeN. I have never seen an encode node elsewhere.
4999 opclass iRegN_P2N(iRegNsrc, iRegP2N);
5000 opclass iRegP_N2P(iRegPsrc, iRegN2P, iRegN2P_klass);
5001 
5002 //----------PIPELINE-----------------------------------------------------------
5003 
5004 pipeline %{
5005 
5006 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
5007 // J. Res. & Dev., No. 1, Jan. 2002.
5008 
5009 //----------ATTRIBUTES---------------------------------------------------------
5010 attributes %{
5011 
5012   // Power4 instructions are of fixed length.
5013   fixed_size_instructions;
5014 
5015   // TODO: if `bundle' means number of instructions fetched
5016   // per cycle, this is 8. If `bundle' means Power4 `group', that is
5017   // max instructions issued per cycle, this is 5.
5018   max_instructions_per_bundle = 8;
5019 
5020   // A Power4 instruction is 4 bytes long.
5021   instruction_unit_size = 4;
5022 
5023   // The Power4 processor fetches 64 bytes...
5024   instruction_fetch_unit_size = 64;
5025 
5026   // ...in one line
5027   instruction_fetch_units = 1
5028 
5029   // Unused, list one so that array generated by adlc is not empty.
5030   // Aix compiler chokes if _nop_count = 0.
5031   nops(fxNop);
5032 %}
5033 
5034 //----------RESOURCES----------------------------------------------------------
5035 // Resources are the functional units available to the machine
5036 resources(
5037    PPC_BR,         // branch unit
5038    PPC_CR,         // condition unit
5039    PPC_FX1,        // integer arithmetic unit 1
5040    PPC_FX2,        // integer arithmetic unit 2
5041    PPC_LDST1,      // load/store unit 1
5042    PPC_LDST2,      // load/store unit 2
5043    PPC_FP1,        // float arithmetic unit 1
5044    PPC_FP2,        // float arithmetic unit 2
5045    PPC_LDST = PPC_LDST1 | PPC_LDST2,
5046    PPC_FX = PPC_FX1 | PPC_FX2,
5047    PPC_FP = PPC_FP1 | PPC_FP2
5048  );
5049 
5050 //----------PIPELINE DESCRIPTION-----------------------------------------------
5051 // Pipeline Description specifies the stages in the machine's pipeline
5052 pipe_desc(
5053    // Power4 longest pipeline path
5054    PPC_IF,   // instruction fetch
5055    PPC_IC,
5056    //PPC_BP, // branch prediction
5057    PPC_D0,   // decode
5058    PPC_D1,   // decode
5059    PPC_D2,   // decode
5060    PPC_D3,   // decode
5061    PPC_Xfer1,
5062    PPC_GD,   // group definition
5063    PPC_MP,   // map
5064    PPC_ISS,  // issue
5065    PPC_RF,   // resource fetch
5066    PPC_EX1,  // execute (all units)
5067    PPC_EX2,  // execute (FP, LDST)
5068    PPC_EX3,  // execute (FP, LDST)
5069    PPC_EX4,  // execute (FP)
5070    PPC_EX5,  // execute (FP)
5071    PPC_EX6,  // execute (FP)
5072    PPC_WB,   // write back
5073    PPC_Xfer2,
5074    PPC_CP
5075  );
5076 
5077 //----------PIPELINE CLASSES---------------------------------------------------
5078 // Pipeline Classes describe the stages in which input and output are
5079 // referenced by the hardware pipeline.
5080 
5081 // Simple pipeline classes.
5082 
5083 // Default pipeline class.
5084 pipe_class pipe_class_default() %{
5085   single_instruction;
5086   fixed_latency(2);
5087 %}
5088 
5089 // Pipeline class for empty instructions.
5090 pipe_class pipe_class_empty() %{
5091   single_instruction;
5092   fixed_latency(0);
5093 %}
5094 
5095 // Pipeline class for compares.
5096 pipe_class pipe_class_compare() %{
5097   single_instruction;
5098   fixed_latency(16);
5099 %}
5100 
5101 // Pipeline class for traps.
5102 pipe_class pipe_class_trap() %{
5103   single_instruction;
5104   fixed_latency(100);
5105 %}
5106 
5107 // Pipeline class for memory operations.
5108 pipe_class pipe_class_memory() %{
5109   single_instruction;
5110   fixed_latency(16);
5111 %}
5112 
5113 // Pipeline class for call.
5114 pipe_class pipe_class_call() %{
5115   single_instruction;
5116   fixed_latency(100);
5117 %}
5118 
5119 // Define the class for the Nop node.
5120 define %{
5121    MachNop = pipe_class_default;
5122 %}
5123 
5124 %}
5125 
5126 //----------INSTRUCTIONS-------------------------------------------------------
5127 
5128 // Naming of instructions:
5129 //   opA_operB / opA_operB_operC:
5130 //     Operation 'op' with one or two source operands 'oper'. Result
5131 //     type is A, source operand types are B and C.
5132 //     Iff A == B == C, B and C are left out.
5133 //
5134 // The instructions are ordered according to the following scheme:
5135 //  - loads
5136 //  - load constants
5137 //  - prefetch
5138 //  - store
5139 //  - encode/decode
5140 //  - membar
5141 //  - conditional moves
5142 //  - compare & swap
5143 //  - arithmetic and logic operations
5144 //    * int: Add, Sub, Mul, Div, Mod
5145 //    * int: lShift, arShift, urShift, rot
5146 //    * float: Add, Sub, Mul, Div
5147 //    * and, or, xor ...
5148 //  - register moves: float <-> int, reg <-> stack, repl
5149 //  - cast (high level type cast, XtoP, castPP, castII, not_null etc.
5150 //  - conv (low level type cast requiring bit changes (sign extend etc)
5151 //  - compares, range & zero checks.
5152 //  - branches
5153 //  - complex operations, intrinsics, min, max, replicate
5154 //  - lock
5155 //  - Calls
5156 //
5157 // If there are similar instructions with different types they are sorted:
5158 // int before float
5159 // small before big
5160 // signed before unsigned
5161 // e.g., loadS before loadUS before loadI before loadF.
5162 
5163 
5164 //----------Load/Store Instructions--------------------------------------------
5165 
5166 //----------Load Instructions--------------------------------------------------
5167 
5168 // Converts byte to int.
5169 // As convB2I_reg, but without match rule.  The match rule of convB2I_reg
5170 // reuses the 'amount' operand, but adlc expects that operand specification
5171 // and operands in match rule are equivalent.
5172 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5173   effect(DEF dst, USE src);
5174   format %{ "EXTSB   $dst, $src \t// byte->int" %}
5175   size(4);
5176   ins_encode %{
5177     // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5178     __ extsb($dst$$Register, $src$$Register);
5179   %}
5180   ins_pipe(pipe_class_default);
5181 %}
5182 
5183 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5184   // match-rule, false predicate
5185   match(Set dst (LoadB mem));
5186   predicate(false);
5187 
5188   format %{ "LBZ     $dst, $mem" %}
5189   size(4);
5190   ins_encode( enc_lbz(dst, mem) );
5191   ins_pipe(pipe_class_memory);
5192 %}
5193 
5194 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5195   // match-rule, false predicate
5196   match(Set dst (LoadB mem));
5197   predicate(false);
5198 
5199   format %{ "LBZ     $dst, $mem\n\t"
5200             "TWI     $dst\n\t"
5201             "ISYNC" %}
5202   size(12);
5203   ins_encode( enc_lbz_ac(dst, mem) );
5204   ins_pipe(pipe_class_memory);
5205 %}
5206 
5207 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5208 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5209   match(Set dst (LoadB mem));
5210   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5211   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5212   expand %{
5213     iRegIdst tmp;
5214     loadUB_indirect(tmp, mem);
5215     convB2I_reg_2(dst, tmp);
5216   %}
5217 %}
5218 
5219 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5220   match(Set dst (LoadB mem));
5221   ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5222   expand %{
5223     iRegIdst tmp;
5224     loadUB_indirect_ac(tmp, mem);
5225     convB2I_reg_2(dst, tmp);
5226   %}
5227 %}
5228 
5229 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5230   // match-rule, false predicate
5231   match(Set dst (LoadB mem));
5232   predicate(false);
5233 
5234   format %{ "LBZ     $dst, $mem" %}
5235   size(4);
5236   ins_encode( enc_lbz(dst, mem) );
5237   ins_pipe(pipe_class_memory);
5238 %}
5239 
5240 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5241   // match-rule, false predicate
5242   match(Set dst (LoadB mem));
5243   predicate(false);
5244 
5245   format %{ "LBZ     $dst, $mem\n\t"
5246             "TWI     $dst\n\t"
5247             "ISYNC" %}
5248   size(12);
5249   ins_encode( enc_lbz_ac(dst, mem) );
5250   ins_pipe(pipe_class_memory);
5251 %}
5252 
5253 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5254 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5255   match(Set dst (LoadB mem));
5256   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5257   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5258 
5259   expand %{
5260     iRegIdst tmp;
5261     loadUB_indOffset16(tmp, mem);
5262     convB2I_reg_2(dst, tmp);
5263   %}
5264 %}
5265 
5266 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5267   match(Set dst (LoadB mem));
5268   ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5269 
5270   expand %{
5271     iRegIdst tmp;
5272     loadUB_indOffset16_ac(tmp, mem);
5273     convB2I_reg_2(dst, tmp);
5274   %}
5275 %}
5276 
5277 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5278 instruct loadUB(iRegIdst dst, memory mem) %{
5279   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5280   match(Set dst (LoadUB mem));
5281   ins_cost(MEMORY_REF_COST);
5282 
5283   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to int" %}
5284   size(4);
5285   ins_encode( enc_lbz(dst, mem) );
5286   ins_pipe(pipe_class_memory);
5287 %}
5288 
5289 // Load  Unsigned Byte (8bit UNsigned) acquire.
5290 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5291   match(Set dst (LoadUB mem));
5292   ins_cost(3*MEMORY_REF_COST);
5293 
5294   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5295             "TWI     $dst\n\t"
5296             "ISYNC" %}
5297   size(12);
5298   ins_encode( enc_lbz_ac(dst, mem) );
5299   ins_pipe(pipe_class_memory);
5300 %}
5301 
5302 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5303 instruct loadUB2L(iRegLdst dst, memory mem) %{
5304   match(Set dst (ConvI2L (LoadUB mem)));
5305   predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5306   ins_cost(MEMORY_REF_COST);
5307 
5308   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to long" %}
5309   size(4);
5310   ins_encode( enc_lbz(dst, mem) );
5311   ins_pipe(pipe_class_memory);
5312 %}
5313 
5314 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5315   match(Set dst (ConvI2L (LoadUB mem)));
5316   ins_cost(3*MEMORY_REF_COST);
5317 
5318   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5319             "TWI     $dst\n\t"
5320             "ISYNC" %}
5321   size(12);
5322   ins_encode( enc_lbz_ac(dst, mem) );
5323   ins_pipe(pipe_class_memory);
5324 %}
5325 
5326 // Load Short (16bit signed)
5327 instruct loadS(iRegIdst dst, memory mem) %{
5328   match(Set dst (LoadS mem));
5329   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5330   ins_cost(MEMORY_REF_COST);
5331 
5332   format %{ "LHA     $dst, $mem" %}
5333   size(4);
5334   ins_encode %{
5335     // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5336     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5337     __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5338   %}
5339   ins_pipe(pipe_class_memory);
5340 %}
5341 
5342 // Load Short (16bit signed) acquire.
5343 instruct loadS_ac(iRegIdst dst, memory mem) %{
5344   match(Set dst (LoadS mem));
5345   ins_cost(3*MEMORY_REF_COST);
5346 
5347   format %{ "LHA     $dst, $mem\t acquire\n\t"
5348             "TWI     $dst\n\t"
5349             "ISYNC" %}
5350   size(12);
5351   ins_encode %{
5352     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5353     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5354     __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5355     __ twi_0($dst$$Register);
5356     __ isync();
5357   %}
5358   ins_pipe(pipe_class_memory);
5359 %}
5360 
5361 // Load Char (16bit unsigned)
5362 instruct loadUS(iRegIdst dst, memory mem) %{
5363   match(Set dst (LoadUS mem));
5364   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5365   ins_cost(MEMORY_REF_COST);
5366 
5367   format %{ "LHZ     $dst, $mem" %}
5368   size(4);
5369   ins_encode( enc_lhz(dst, mem) );
5370   ins_pipe(pipe_class_memory);
5371 %}
5372 
5373 // Load Char (16bit unsigned) acquire.
5374 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5375   match(Set dst (LoadUS mem));
5376   ins_cost(3*MEMORY_REF_COST);
5377 
5378   format %{ "LHZ     $dst, $mem \t// acquire\n\t"
5379             "TWI     $dst\n\t"
5380             "ISYNC" %}
5381   size(12);
5382   ins_encode( enc_lhz_ac(dst, mem) );
5383   ins_pipe(pipe_class_memory);
5384 %}
5385 
5386 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5387 instruct loadUS2L(iRegLdst dst, memory mem) %{
5388   match(Set dst (ConvI2L (LoadUS mem)));
5389   predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5390   ins_cost(MEMORY_REF_COST);
5391 
5392   format %{ "LHZ     $dst, $mem \t// short, zero-extend to long" %}
5393   size(4);
5394   ins_encode( enc_lhz(dst, mem) );
5395   ins_pipe(pipe_class_memory);
5396 %}
5397 
5398 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5399 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5400   match(Set dst (ConvI2L (LoadUS mem)));
5401   ins_cost(3*MEMORY_REF_COST);
5402 
5403   format %{ "LHZ     $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5404             "TWI     $dst\n\t"
5405             "ISYNC" %}
5406   size(12);
5407   ins_encode( enc_lhz_ac(dst, mem) );
5408   ins_pipe(pipe_class_memory);
5409 %}
5410 
5411 // Load Integer.
5412 instruct loadI(iRegIdst dst, memory mem) %{
5413   match(Set dst (LoadI mem));
5414   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5415   ins_cost(MEMORY_REF_COST);
5416 
5417   format %{ "LWZ     $dst, $mem" %}
5418   size(4);
5419   ins_encode( enc_lwz(dst, mem) );
5420   ins_pipe(pipe_class_memory);
5421 %}
5422 
5423 // Load Integer acquire.
5424 instruct loadI_ac(iRegIdst dst, memory mem) %{
5425   match(Set dst (LoadI mem));
5426   ins_cost(3*MEMORY_REF_COST);
5427 
5428   format %{ "LWZ     $dst, $mem \t// load acquire\n\t"
5429             "TWI     $dst\n\t"
5430             "ISYNC" %}
5431   size(12);
5432   ins_encode( enc_lwz_ac(dst, mem) );
5433   ins_pipe(pipe_class_memory);
5434 %}
5435 
5436 // Match loading integer and casting it to unsigned int in
5437 // long register.
5438 // LoadI + ConvI2L + AndL 0xffffffff.
5439 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5440   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5441   predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5442   ins_cost(MEMORY_REF_COST);
5443 
5444   format %{ "LWZ     $dst, $mem \t// zero-extend to long" %}
5445   size(4);
5446   ins_encode( enc_lwz(dst, mem) );
5447   ins_pipe(pipe_class_memory);
5448 %}
5449 
5450 // Match loading integer and casting it to long.
5451 instruct loadI2L(iRegLdst dst, memory mem) %{
5452   match(Set dst (ConvI2L (LoadI mem)));
5453   predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5454   ins_cost(MEMORY_REF_COST);
5455 
5456   format %{ "LWA     $dst, $mem \t// loadI2L" %}
5457   size(4);
5458   ins_encode %{
5459     // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5460     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5461     __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5462   %}
5463   ins_pipe(pipe_class_memory);
5464 %}
5465 
5466 // Match loading integer and casting it to long - acquire.
5467 instruct loadI2L_ac(iRegLdst dst, memory mem) %{
5468   match(Set dst (ConvI2L (LoadI mem)));
5469   ins_cost(3*MEMORY_REF_COST);
5470 
5471   format %{ "LWA     $dst, $mem \t// loadI2L acquire"
5472             "TWI     $dst\n\t"
5473             "ISYNC" %}
5474   size(12);
5475   ins_encode %{
5476     // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5477     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5478     __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5479     __ twi_0($dst$$Register);
5480     __ isync();
5481   %}
5482   ins_pipe(pipe_class_memory);
5483 %}
5484 
5485 // Load Long - aligned
5486 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5487   match(Set dst (LoadL mem));
5488   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5489   ins_cost(MEMORY_REF_COST);
5490 
5491   format %{ "LD      $dst, $mem \t// long" %}
5492   size(4);
5493   ins_encode( enc_ld(dst, mem) );
5494   ins_pipe(pipe_class_memory);
5495 %}
5496 
5497 // Load Long - aligned acquire.
5498 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5499   match(Set dst (LoadL mem));
5500   ins_cost(3*MEMORY_REF_COST);
5501 
5502   format %{ "LD      $dst, $mem \t// long acquire\n\t"
5503             "TWI     $dst\n\t"
5504             "ISYNC" %}
5505   size(12);
5506   ins_encode( enc_ld_ac(dst, mem) );
5507   ins_pipe(pipe_class_memory);
5508 %}
5509 
5510 // Load Long - UNaligned
5511 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5512   match(Set dst (LoadL_unaligned mem));
5513   // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5514   ins_cost(MEMORY_REF_COST);
5515 
5516   format %{ "LD      $dst, $mem \t// unaligned long" %}
5517   size(4);
5518   ins_encode( enc_ld(dst, mem) );
5519   ins_pipe(pipe_class_memory);
5520 %}
5521 
5522 // Load nodes for superwords
5523 
5524 // Load Aligned Packed Byte
5525 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5526   predicate(n->as_LoadVector()->memory_size() == 8);
5527   match(Set dst (LoadVector mem));
5528   ins_cost(MEMORY_REF_COST);
5529 
5530   format %{ "LD      $dst, $mem \t// load 8-byte Vector" %}
5531   size(4);
5532   ins_encode( enc_ld(dst, mem) );
5533   ins_pipe(pipe_class_memory);
5534 %}
5535 
5536 // Load Range, range = array length (=jint)
5537 instruct loadRange(iRegIdst dst, memory mem) %{
5538   match(Set dst (LoadRange mem));
5539   ins_cost(MEMORY_REF_COST);
5540 
5541   format %{ "LWZ     $dst, $mem \t// range" %}
5542   size(4);
5543   ins_encode( enc_lwz(dst, mem) );
5544   ins_pipe(pipe_class_memory);
5545 %}
5546 
5547 // Load Compressed Pointer
5548 instruct loadN(iRegNdst dst, memory mem) %{
5549   match(Set dst (LoadN mem));
5550   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5551   ins_cost(MEMORY_REF_COST);
5552 
5553   format %{ "LWZ     $dst, $mem \t// load compressed ptr" %}
5554   size(4);
5555   ins_encode( enc_lwz(dst, mem) );
5556   ins_pipe(pipe_class_memory);
5557 %}
5558 
5559 // Load Compressed Pointer acquire.
5560 instruct loadN_ac(iRegNdst dst, memory mem) %{
5561   match(Set dst (LoadN mem));
5562   ins_cost(3*MEMORY_REF_COST);
5563 
5564   format %{ "LWZ     $dst, $mem \t// load acquire compressed ptr\n\t"
5565             "TWI     $dst\n\t"
5566             "ISYNC" %}
5567   size(12);
5568   ins_encode( enc_lwz_ac(dst, mem) );
5569   ins_pipe(pipe_class_memory);
5570 %}
5571 
5572 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5573 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5574   match(Set dst (DecodeN (LoadN mem)));
5575   predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5576   ins_cost(MEMORY_REF_COST);
5577 
5578   format %{ "LWZ     $dst, $mem \t// DecodeN (unscaled)" %}
5579   size(4);
5580   ins_encode( enc_lwz(dst, mem) );
5581   ins_pipe(pipe_class_memory);
5582 %}
5583 
5584 instruct loadN2P_klass_unscaled(iRegPdst dst, memory mem) %{
5585   match(Set dst (DecodeNKlass (LoadNKlass mem)));
5586   // SAPJVM GL 2014-05-21 Differs.
5587   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0 &&
5588             _kids[0]->_leaf->as_Load()->is_unordered());
5589   ins_cost(MEMORY_REF_COST);
5590 
5591   format %{ "LWZ     $dst, $mem \t// DecodeN (unscaled)" %}
5592   size(4);
5593   ins_encode( enc_lwz(dst, mem) );
5594   ins_pipe(pipe_class_memory);
5595 %}
5596 
5597 // Load Pointer
5598 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5599   match(Set dst (LoadP mem));
5600   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5601   ins_cost(MEMORY_REF_COST);
5602 
5603   format %{ "LD      $dst, $mem \t// ptr" %}
5604   size(4);
5605   ins_encode( enc_ld(dst, mem) );
5606   ins_pipe(pipe_class_memory);
5607 %}
5608 
5609 // Load Pointer acquire.
5610 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5611   match(Set dst (LoadP mem));
5612   ins_cost(3*MEMORY_REF_COST);
5613 
5614   format %{ "LD      $dst, $mem \t// ptr acquire\n\t"
5615             "TWI     $dst\n\t"
5616             "ISYNC" %}
5617   size(12);
5618   ins_encode( enc_ld_ac(dst, mem) );
5619   ins_pipe(pipe_class_memory);
5620 %}
5621 
5622 // LoadP + CastP2L
5623 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5624   match(Set dst (CastP2X (LoadP mem)));
5625   predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5626   ins_cost(MEMORY_REF_COST);
5627 
5628   format %{ "LD      $dst, $mem \t// ptr + p2x" %}
5629   size(4);
5630   ins_encode( enc_ld(dst, mem) );
5631   ins_pipe(pipe_class_memory);
5632 %}
5633 
5634 // Load compressed klass pointer.
5635 instruct loadNKlass(iRegNdst dst, memory mem) %{
5636   match(Set dst (LoadNKlass mem));
5637   ins_cost(MEMORY_REF_COST);
5638 
5639   format %{ "LWZ     $dst, $mem \t// compressed klass ptr" %}
5640   size(4);
5641   ins_encode( enc_lwz(dst, mem) );
5642   ins_pipe(pipe_class_memory);
5643 %}
5644 
5645 // Load Klass Pointer
5646 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5647   match(Set dst (LoadKlass mem));
5648   ins_cost(MEMORY_REF_COST);
5649 
5650   format %{ "LD      $dst, $mem \t// klass ptr" %}
5651   size(4);
5652   ins_encode( enc_ld(dst, mem) );
5653   ins_pipe(pipe_class_memory);
5654 %}
5655 
5656 // Load Float
5657 instruct loadF(regF dst, memory mem) %{
5658   match(Set dst (LoadF mem));
5659   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5660   ins_cost(MEMORY_REF_COST);
5661 
5662   format %{ "LFS     $dst, $mem" %}
5663   size(4);
5664   ins_encode %{
5665     // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5666     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5667     __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5668   %}
5669   ins_pipe(pipe_class_memory);
5670 %}
5671 
5672 // Load Float acquire.
5673 instruct loadF_ac(regF dst, memory mem, flagsRegCR0 cr0) %{
5674   match(Set dst (LoadF mem));
5675   effect(TEMP cr0);
5676   ins_cost(3*MEMORY_REF_COST);
5677 
5678   format %{ "LFS     $dst, $mem \t// acquire\n\t"
5679             "FCMPU   cr0, $dst, $dst\n\t"
5680             "BNE     cr0, next\n"
5681             "next:\n\t"
5682             "ISYNC" %}
5683   size(16);
5684   ins_encode %{
5685     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5686     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5687     Label next;
5688     __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5689     __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5690     __ bne(CCR0, next);
5691     __ bind(next);
5692     __ isync();
5693   %}
5694   ins_pipe(pipe_class_memory);
5695 %}
5696 
5697 // Load Double - aligned
5698 instruct loadD(regD dst, memory mem) %{
5699   match(Set dst (LoadD mem));
5700   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5701   ins_cost(MEMORY_REF_COST);
5702 
5703   format %{ "LFD     $dst, $mem" %}
5704   size(4);
5705   ins_encode( enc_lfd(dst, mem) );
5706   ins_pipe(pipe_class_memory);
5707 %}
5708 
5709 // Load Double - aligned acquire.
5710 instruct loadD_ac(regD dst, memory mem, flagsRegCR0 cr0) %{
5711   match(Set dst (LoadD mem));
5712   effect(TEMP cr0);
5713   ins_cost(3*MEMORY_REF_COST);
5714 
5715   format %{ "LFD     $dst, $mem \t// acquire\n\t"
5716             "FCMPU   cr0, $dst, $dst\n\t"
5717             "BNE     cr0, next\n"
5718             "next:\n\t"
5719             "ISYNC" %}
5720   size(16);
5721   ins_encode %{
5722     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5723     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5724     Label next;
5725     __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5726     __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5727     __ bne(CCR0, next);
5728     __ bind(next);
5729     __ isync();
5730   %}
5731   ins_pipe(pipe_class_memory);
5732 %}
5733 
5734 // Load Double - UNaligned
5735 instruct loadD_unaligned(regD dst, memory mem) %{
5736   match(Set dst (LoadD_unaligned mem));
5737   // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5738   ins_cost(MEMORY_REF_COST);
5739 
5740   format %{ "LFD     $dst, $mem" %}
5741   size(4);
5742   ins_encode( enc_lfd(dst, mem) );
5743   ins_pipe(pipe_class_memory);
5744 %}
5745 
5746 //----------Constants--------------------------------------------------------
5747 
5748 // Load MachConstantTableBase: add hi offset to global toc.
5749 // TODO: Handle hidden register r29 in bundler!
5750 instruct loadToc_hi(iRegLdst dst) %{
5751   effect(DEF dst);
5752   ins_cost(DEFAULT_COST);
5753 
5754   format %{ "ADDIS   $dst, R29, DISP.hi \t// load TOC hi" %}
5755   size(4);
5756   ins_encode %{
5757     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5758     __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5759   %}
5760   ins_pipe(pipe_class_default);
5761 %}
5762 
5763 // Load MachConstantTableBase: add lo offset to global toc.
5764 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5765   effect(DEF dst, USE src);
5766   ins_cost(DEFAULT_COST);
5767 
5768   format %{ "ADDI    $dst, $src, DISP.lo \t// load TOC lo" %}
5769   size(4);
5770   ins_encode %{
5771     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5772     __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5773   %}
5774   ins_pipe(pipe_class_default);
5775 %}
5776 
5777 // Load 16-bit integer constant 0xssss????
5778 instruct loadConI16(iRegIdst dst, immI16 src) %{
5779   match(Set dst src);
5780 
5781   format %{ "LI      $dst, $src" %}
5782   size(4);
5783   ins_encode %{
5784     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5785     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5786   %}
5787   ins_pipe(pipe_class_default);
5788 %}
5789 
5790 // Load integer constant 0x????0000
5791 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5792   match(Set dst src);
5793   ins_cost(DEFAULT_COST);
5794 
5795   format %{ "LIS     $dst, $src.hi" %}
5796   size(4);
5797   ins_encode %{
5798     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5799     // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5800     __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5801   %}
5802   ins_pipe(pipe_class_default);
5803 %}
5804 
5805 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5806 // and sign extended), this adds the low 16 bits.
5807 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5808   // no match-rule, false predicate
5809   effect(DEF dst, USE src1, USE src2);
5810   predicate(false);
5811 
5812   format %{ "ORI     $dst, $src1.hi, $src2.lo" %}
5813   size(4);
5814   ins_encode %{
5815     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5816     __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5817   %}
5818   ins_pipe(pipe_class_default);
5819 %}
5820 
5821 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5822   match(Set dst src);
5823   ins_cost(DEFAULT_COST*2);
5824 
5825   expand %{
5826     // Would like to use $src$$constant.
5827     immI16 srcLo %{ _opnds[1]->constant() %}
5828     // srcHi can be 0000 if srcLo sign-extends to a negative number.
5829     immIhi16 srcHi %{ _opnds[1]->constant() %}
5830     iRegIdst tmpI;
5831     loadConIhi16(tmpI, srcHi);
5832     loadConI32_lo16(dst, tmpI, srcLo);
5833   %}
5834 %}
5835 
5836 // No constant pool entries required.
5837 instruct loadConL16(iRegLdst dst, immL16 src) %{
5838   match(Set dst src);
5839 
5840   format %{ "LI      $dst, $src \t// long" %}
5841   size(4);
5842   ins_encode %{
5843     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5844     __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5845   %}
5846   ins_pipe(pipe_class_default);
5847 %}
5848 
5849 // Load long constant 0xssssssss????0000
5850 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5851   match(Set dst src);
5852   ins_cost(DEFAULT_COST);
5853 
5854   format %{ "LIS     $dst, $src.hi \t// long" %}
5855   size(4);
5856   ins_encode %{
5857     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5858     __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5859   %}
5860   ins_pipe(pipe_class_default);
5861 %}
5862 
5863 // To load a 32 bit constant: merge lower 16 bits into already loaded
5864 // high 16 bits.
5865 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5866   // no match-rule, false predicate
5867   effect(DEF dst, USE src1, USE src2);
5868   predicate(false);
5869 
5870   format %{ "ORI     $dst, $src1, $src2.lo" %}
5871   size(4);
5872   ins_encode %{
5873     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5874     __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5875   %}
5876   ins_pipe(pipe_class_default);
5877 %}
5878 
5879 // Load 32-bit long constant
5880 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5881   match(Set dst src);
5882   ins_cost(DEFAULT_COST*2);
5883 
5884   expand %{
5885     // Would like to use $src$$constant.
5886     immL16     srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5887     // srcHi can be 0000 if srcLo sign-extends to a negative number.
5888     immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5889     iRegLdst tmpL;
5890     loadConL32hi16(tmpL, srcHi);
5891     loadConL32_lo16(dst, tmpL, srcLo);
5892   %}
5893 %}
5894 
5895 // Load long constant 0x????000000000000.
5896 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5897   match(Set dst src);
5898   ins_cost(DEFAULT_COST);
5899 
5900   expand %{
5901     immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5902     immI shift32 %{ 32 %}
5903     iRegLdst tmpL;
5904     loadConL32hi16(tmpL, srcHi);
5905     lshiftL_regL_immI(dst, tmpL, shift32);
5906   %}
5907 %}
5908 
5909 // Expand node for constant pool load: small offset.
5910 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5911   effect(DEF dst, USE src, USE toc);
5912   ins_cost(MEMORY_REF_COST);
5913 
5914   ins_num_consts(1);
5915   // Needed so that CallDynamicJavaDirect can compute the address of this
5916   // instruction for relocation.
5917   ins_field_cbuf_insts_offset(int);
5918 
5919   format %{ "LD      $dst, offset, $toc \t// load long $src from TOC" %}
5920   size(4);
5921   ins_encode( enc_load_long_constL(dst, src, toc) );
5922   ins_pipe(pipe_class_memory);
5923 %}
5924 
5925 // Expand node for constant pool load: large offset.
5926 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5927   effect(DEF dst, USE src, USE toc);
5928   predicate(false);
5929 
5930   ins_num_consts(1);
5931   ins_field_const_toc_offset(int);
5932   // Needed so that CallDynamicJavaDirect can compute the address of this
5933   // instruction for relocation.
5934   ins_field_cbuf_insts_offset(int);
5935 
5936   format %{ "ADDIS   $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5937   size(4);
5938   ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5939   ins_pipe(pipe_class_default);
5940 %}
5941 
5942 // Expand node for constant pool load: large offset.
5943 // No constant pool entries required.
5944 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5945   effect(DEF dst, USE src, USE base);
5946   predicate(false);
5947 
5948   ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5949 
5950   format %{ "LD      $dst, offset, $base \t// load long $src from TOC (lo)" %}
5951   size(4);
5952   ins_encode %{
5953     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5954     int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5955     __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5956   %}
5957   ins_pipe(pipe_class_memory);
5958 %}
5959 
5960 // Load long constant from constant table. Expand in case of
5961 // offset > 16 bit is needed.
5962 // Adlc adds toc node MachConstantTableBase.
5963 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5964   match(Set dst src);
5965   ins_cost(MEMORY_REF_COST);
5966 
5967   format %{ "LD      $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5968   // We can not inline the enc_class for the expand as that does not support constanttablebase.
5969   postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5970 %}
5971 
5972 // Load NULL as compressed oop.
5973 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5974   match(Set dst src);
5975   ins_cost(DEFAULT_COST);
5976 
5977   format %{ "LI      $dst, $src \t// compressed ptr" %}
5978   size(4);
5979   ins_encode %{
5980     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5981     __ li($dst$$Register, 0);
5982   %}
5983   ins_pipe(pipe_class_default);
5984 %}
5985 
5986 // Load hi part of compressed oop constant.
5987 instruct loadConN_hi(iRegNdst dst, immN src) %{
5988   effect(DEF dst, USE src);
5989   ins_cost(DEFAULT_COST);
5990 
5991   format %{ "LIS     $dst, $src \t// narrow oop hi" %}
5992   size(4);
5993   ins_encode %{
5994     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5995     __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
5996   %}
5997   ins_pipe(pipe_class_default);
5998 %}
5999 
6000 // Add lo part of compressed oop constant to already loaded hi part.
6001 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
6002   effect(DEF dst, USE src1, USE src2);
6003   ins_cost(DEFAULT_COST);
6004 
6005   format %{ "ORI     $dst, $src1, $src2 \t// narrow oop lo" %}
6006   size(4);
6007   ins_encode %{
6008     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6009     assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6010     int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
6011     RelocationHolder rspec = oop_Relocation::spec(oop_index);
6012     __ relocate(rspec, 1);
6013     __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
6014   %}
6015   ins_pipe(pipe_class_default);
6016 %}
6017 
6018 // Needed to postalloc expand loadConN: ConN is loaded as ConI
6019 // leaving the upper 32 bits with sign-extension bits.
6020 // This clears these bits: dst = src & 0xFFFFFFFF.
6021 // TODO: Eventually call this maskN_regN_FFFFFFFF.
6022 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
6023   effect(DEF dst, USE src);
6024   predicate(false);
6025 
6026   format %{ "MASK    $dst, $src, 0xFFFFFFFF" %} // mask
6027   size(4);
6028   ins_encode %{
6029     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6030     __ clrldi($dst$$Register, $src$$Register, 0x20);
6031   %}
6032   ins_pipe(pipe_class_default);
6033 %}
6034 
6035 // Optimize DecodeN for disjoint base.
6036 // Load base of compressed oops into a register
6037 instruct loadBase(iRegLdst dst) %{
6038   effect(DEF dst);
6039 
6040   format %{ "LoadConst $dst, heapbase" %}
6041   ins_encode %{
6042     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6043     __ load_const_optimized($dst$$Register, Universe::narrow_oop_base(), R0);
6044   %}
6045   ins_pipe(pipe_class_default);
6046 %}
6047 
6048 // Loading ConN must be postalloc expanded so that edges between
6049 // the nodes are safe. They may not interfere with a safepoint.
6050 // GL TODO: This needs three instructions: better put this into the constant pool.
6051 instruct loadConN_Ex(iRegNdst dst, immN src) %{
6052   match(Set dst src);
6053   ins_cost(DEFAULT_COST*2);
6054 
6055   format %{ "LoadN   $dst, $src \t// postalloc expanded" %} // mask
6056   postalloc_expand %{
6057     MachNode *m1 = new loadConN_hiNode();
6058     MachNode *m2 = new loadConN_loNode();
6059     MachNode *m3 = new clearMs32bNode();
6060     m1->add_req(NULL);
6061     m2->add_req(NULL, m1);
6062     m3->add_req(NULL, m2);
6063     m1->_opnds[0] = op_dst;
6064     m1->_opnds[1] = op_src;
6065     m2->_opnds[0] = op_dst;
6066     m2->_opnds[1] = op_dst;
6067     m2->_opnds[2] = op_src;
6068     m3->_opnds[0] = op_dst;
6069     m3->_opnds[1] = op_dst;
6070     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6071     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6072     ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6073     nodes->push(m1);
6074     nodes->push(m2);
6075     nodes->push(m3);
6076   %}
6077 %}
6078 
6079 // We have seen a safepoint between the hi and lo parts, and this node was handled
6080 // as an oop. Therefore this needs a match rule so that build_oop_map knows this is
6081 // not a narrow oop.
6082 instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{
6083   match(Set dst src);
6084   effect(DEF dst, USE src);
6085   ins_cost(DEFAULT_COST);
6086 
6087   format %{ "LIS     $dst, $src \t// narrow klass hi" %}
6088   size(4);
6089   ins_encode %{
6090     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6091     intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
6092     __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
6093   %}
6094   ins_pipe(pipe_class_default);
6095 %}
6096 
6097 // As loadConNKlass_hi this must be recognized as narrow klass, not oop!
6098 instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6099   match(Set dst src1);
6100   effect(TEMP src2);
6101   ins_cost(DEFAULT_COST);
6102 
6103   format %{ "MASK    $dst, $src2, 0xFFFFFFFF" %} // mask
6104   size(4);
6105   ins_encode %{
6106     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6107     __ clrldi($dst$$Register, $src2$$Register, 0x20);
6108   %}
6109   ins_pipe(pipe_class_default);
6110 %}
6111 
6112 // This needs a match rule so that build_oop_map knows this is
6113 // not a narrow oop.
6114 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6115   match(Set dst src1);
6116   effect(TEMP src2);
6117   ins_cost(DEFAULT_COST);
6118 
6119   format %{ "ORI     $dst, $src1, $src2 \t// narrow klass lo" %}
6120   size(4);
6121   ins_encode %{
6122     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
6123     intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
6124     assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6125     int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
6126     RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6127 
6128     __ relocate(rspec, 1);
6129     __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
6130   %}
6131   ins_pipe(pipe_class_default);
6132 %}
6133 
6134 // Loading ConNKlass must be postalloc expanded so that edges between
6135 // the nodes are safe. They may not interfere with a safepoint.
6136 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
6137   match(Set dst src);
6138   ins_cost(DEFAULT_COST*2);
6139 
6140   format %{ "LoadN   $dst, $src \t// postalloc expanded" %} // mask
6141   postalloc_expand %{
6142     // Load high bits into register. Sign extended.
6143     MachNode *m1 = new loadConNKlass_hiNode();
6144     m1->add_req(NULL);
6145     m1->_opnds[0] = op_dst;
6146     m1->_opnds[1] = op_src;
6147     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6148     nodes->push(m1);
6149 
6150     MachNode *m2 = m1;
6151     if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6152       // Value might be 1-extended. Mask out these bits.
6153       m2 = new loadConNKlass_maskNode();
6154       m2->add_req(NULL, m1);
6155       m2->_opnds[0] = op_dst;
6156       m2->_opnds[1] = op_src;
6157       m2->_opnds[2] = op_dst;
6158       ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6159       nodes->push(m2);
6160     }
6161 
6162     MachNode *m3 = new loadConNKlass_loNode();
6163     m3->add_req(NULL, m2);
6164     m3->_opnds[0] = op_dst;
6165     m3->_opnds[1] = op_src;
6166     m3->_opnds[2] = op_dst;
6167     ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6168     nodes->push(m3);
6169   %}
6170 %}
6171 
6172 // 0x1 is used in object initialization (initial object header).
6173 // No constant pool entries required.
6174 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6175   match(Set dst src);
6176 
6177   format %{ "LI      $dst, $src \t// ptr" %}
6178   size(4);
6179   ins_encode %{
6180     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6181     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6182   %}
6183   ins_pipe(pipe_class_default);
6184 %}
6185 
6186 // Expand node for constant pool load: small offset.
6187 // The match rule is needed to generate the correct bottom_type(),
6188 // however this node should never match. The use of predicate is not
6189 // possible since ADLC forbids predicates for chain rules. The higher
6190 // costs do not prevent matching in this case. For that reason the
6191 // operand immP_NM with predicate(false) is used.
6192 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6193   match(Set dst src);
6194   effect(TEMP toc);
6195 
6196   ins_num_consts(1);
6197 
6198   format %{ "LD      $dst, offset, $toc \t// load ptr $src from TOC" %}
6199   size(4);
6200   ins_encode( enc_load_long_constP(dst, src, toc) );
6201   ins_pipe(pipe_class_memory);
6202 %}
6203 
6204 // Expand node for constant pool load: large offset.
6205 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6206   effect(DEF dst, USE src, USE toc);
6207   predicate(false);
6208 
6209   ins_num_consts(1);
6210   ins_field_const_toc_offset(int);
6211 
6212   format %{ "ADDIS   $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6213   size(4);
6214   ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6215   ins_pipe(pipe_class_default);
6216 %}
6217 
6218 // Expand node for constant pool load: large offset.
6219 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6220   match(Set dst src);
6221   effect(TEMP base);
6222 
6223   ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6224 
6225   format %{ "LD      $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6226   size(4);
6227   ins_encode %{
6228     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6229     int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6230     __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6231   %}
6232   ins_pipe(pipe_class_memory);
6233 %}
6234 
6235 // Load pointer constant from constant table. Expand in case an
6236 // offset > 16 bit is needed.
6237 // Adlc adds toc node MachConstantTableBase.
6238 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6239   match(Set dst src);
6240   ins_cost(MEMORY_REF_COST);
6241 
6242   // This rule does not use "expand" because then
6243   // the result type is not known to be an Oop.  An ADLC
6244   // enhancement will be needed to make that work - not worth it!
6245 
6246   // If this instruction rematerializes, it prolongs the live range
6247   // of the toc node, causing illegal graphs.
6248   // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6249   ins_cannot_rematerialize(true);
6250 
6251   format %{ "LD    $dst, offset, $constanttablebase \t//  load ptr $src from table, postalloc expanded" %}
6252   postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6253 %}
6254 
6255 // Expand node for constant pool load: small offset.
6256 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6257   effect(DEF dst, USE src, USE toc);
6258   ins_cost(MEMORY_REF_COST);
6259 
6260   ins_num_consts(1);
6261 
6262   format %{ "LFS     $dst, offset, $toc \t// load float $src from TOC" %}
6263   size(4);
6264   ins_encode %{
6265     // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6266     address float_address = __ float_constant($src$$constant);
6267     __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6268   %}
6269   ins_pipe(pipe_class_memory);
6270 %}
6271 
6272 // Expand node for constant pool load: large offset.
6273 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6274   effect(DEF dst, USE src, USE toc);
6275   ins_cost(MEMORY_REF_COST);
6276 
6277   ins_num_consts(1);
6278 
6279   format %{ "ADDIS   $toc, $toc, offset_hi\n\t"
6280             "LFS     $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6281             "ADDIS   $toc, $toc, -offset_hi"%}
6282   size(12);
6283   ins_encode %{
6284     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6285     FloatRegister Rdst    = $dst$$FloatRegister;
6286     Register Rtoc         = $toc$$Register;
6287     address float_address = __ float_constant($src$$constant);
6288     int offset            = __ offset_to_method_toc(float_address);
6289     int hi = (offset + (1<<15))>>16;
6290     int lo = offset - hi * (1<<16);
6291 
6292     __ addis(Rtoc, Rtoc, hi);
6293     __ lfs(Rdst, lo, Rtoc);
6294     __ addis(Rtoc, Rtoc, -hi);
6295   %}
6296   ins_pipe(pipe_class_memory);
6297 %}
6298 
6299 // Adlc adds toc node MachConstantTableBase.
6300 instruct loadConF_Ex(regF dst, immF src) %{
6301   match(Set dst src);
6302   ins_cost(MEMORY_REF_COST);
6303 
6304   // See loadConP.
6305   ins_cannot_rematerialize(true);
6306 
6307   format %{ "LFS     $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6308   postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6309 %}
6310 
6311 // Expand node for constant pool load: small offset.
6312 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6313   effect(DEF dst, USE src, USE toc);
6314   ins_cost(MEMORY_REF_COST);
6315 
6316   ins_num_consts(1);
6317 
6318   format %{ "LFD     $dst, offset, $toc \t// load double $src from TOC" %}
6319   size(4);
6320   ins_encode %{
6321     // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6322     int offset =  __ offset_to_method_toc(__ double_constant($src$$constant));
6323     __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6324   %}
6325   ins_pipe(pipe_class_memory);
6326 %}
6327 
6328 // Expand node for constant pool load: large offset.
6329 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6330   effect(DEF dst, USE src, USE toc);
6331   ins_cost(MEMORY_REF_COST);
6332 
6333   ins_num_consts(1);
6334 
6335   format %{ "ADDIS   $toc, $toc, offset_hi\n\t"
6336             "LFD     $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6337             "ADDIS   $toc, $toc, -offset_hi" %}
6338   size(12);
6339   ins_encode %{
6340     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6341     FloatRegister Rdst    = $dst$$FloatRegister;
6342     Register      Rtoc    = $toc$$Register;
6343     address float_address = __ double_constant($src$$constant);
6344     int offset            = __ offset_to_method_toc(float_address);
6345     int hi = (offset + (1<<15))>>16;
6346     int lo = offset - hi * (1<<16);
6347 
6348     __ addis(Rtoc, Rtoc, hi);
6349     __ lfd(Rdst, lo, Rtoc);
6350     __ addis(Rtoc, Rtoc, -hi);
6351   %}
6352   ins_pipe(pipe_class_memory);
6353 %}
6354 
6355 // Adlc adds toc node MachConstantTableBase.
6356 instruct loadConD_Ex(regD dst, immD src) %{
6357   match(Set dst src);
6358   ins_cost(MEMORY_REF_COST);
6359 
6360   // See loadConP.
6361   ins_cannot_rematerialize(true);
6362 
6363   format %{ "ConD    $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6364   postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6365 %}
6366 
6367 // Prefetch instructions.
6368 // Must be safe to execute with invalid address (cannot fault).
6369 
6370 // Special prefetch versions which use the dcbz instruction.
6371 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6372   match(PrefetchAllocation (AddP mem src));
6373   predicate(AllocatePrefetchStyle == 3);
6374   ins_cost(MEMORY_REF_COST);
6375 
6376   format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6377   size(4);
6378   ins_encode %{
6379     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6380     __ dcbz($src$$Register, $mem$$base$$Register);
6381   %}
6382   ins_pipe(pipe_class_memory);
6383 %}
6384 
6385 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6386   match(PrefetchAllocation mem);
6387   predicate(AllocatePrefetchStyle == 3);
6388   ins_cost(MEMORY_REF_COST);
6389 
6390   format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6391   size(4);
6392   ins_encode %{
6393     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6394     __ dcbz($mem$$base$$Register);
6395   %}
6396   ins_pipe(pipe_class_memory);
6397 %}
6398 
6399 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6400   match(PrefetchAllocation (AddP mem src));
6401   predicate(AllocatePrefetchStyle != 3);
6402   ins_cost(MEMORY_REF_COST);
6403 
6404   format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6405   size(4);
6406   ins_encode %{
6407     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6408     __ dcbtst($src$$Register, $mem$$base$$Register);
6409   %}
6410   ins_pipe(pipe_class_memory);
6411 %}
6412 
6413 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6414   match(PrefetchAllocation mem);
6415   predicate(AllocatePrefetchStyle != 3);
6416   ins_cost(MEMORY_REF_COST);
6417 
6418   format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6419   size(4);
6420   ins_encode %{
6421     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6422     __ dcbtst($mem$$base$$Register);
6423   %}
6424   ins_pipe(pipe_class_memory);
6425 %}
6426 
6427 //----------Store Instructions-------------------------------------------------
6428 
6429 // Store Byte
6430 instruct storeB(memory mem, iRegIsrc src) %{
6431   match(Set mem (StoreB mem src));
6432   ins_cost(MEMORY_REF_COST);
6433 
6434   format %{ "STB     $src, $mem \t// byte" %}
6435   size(4);
6436   ins_encode %{
6437     // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6438     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6439     __ stb($src$$Register, Idisp, $mem$$base$$Register);
6440   %}
6441   ins_pipe(pipe_class_memory);
6442 %}
6443 
6444 // Store Char/Short
6445 instruct storeC(memory mem, iRegIsrc src) %{
6446   match(Set mem (StoreC mem src));
6447   ins_cost(MEMORY_REF_COST);
6448 
6449   format %{ "STH     $src, $mem \t// short" %}
6450   size(4);
6451   ins_encode %{
6452     // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6453     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6454     __ sth($src$$Register, Idisp, $mem$$base$$Register);
6455   %}
6456   ins_pipe(pipe_class_memory);
6457 %}
6458 
6459 // Store Integer
6460 instruct storeI(memory mem, iRegIsrc src) %{
6461   match(Set mem (StoreI mem src));
6462   ins_cost(MEMORY_REF_COST);
6463 
6464   format %{ "STW     $src, $mem" %}
6465   size(4);
6466   ins_encode( enc_stw(src, mem) );
6467   ins_pipe(pipe_class_memory);
6468 %}
6469 
6470 // ConvL2I + StoreI.
6471 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6472   match(Set mem (StoreI mem (ConvL2I src)));
6473   ins_cost(MEMORY_REF_COST);
6474 
6475   format %{ "STW     l2i($src), $mem" %}
6476   size(4);
6477   ins_encode( enc_stw(src, mem) );
6478   ins_pipe(pipe_class_memory);
6479 %}
6480 
6481 // Store Long
6482 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6483   match(Set mem (StoreL mem src));
6484   ins_cost(MEMORY_REF_COST);
6485 
6486   format %{ "STD     $src, $mem \t// long" %}
6487   size(4);
6488   ins_encode( enc_std(src, mem) );
6489   ins_pipe(pipe_class_memory);
6490 %}
6491 
6492 // Store super word nodes.
6493 
6494 // Store Aligned Packed Byte long register to memory
6495 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6496   predicate(n->as_StoreVector()->memory_size() == 8);
6497   match(Set mem (StoreVector mem src));
6498   ins_cost(MEMORY_REF_COST);
6499 
6500   format %{ "STD     $mem, $src \t// packed8B" %}
6501   size(4);
6502   ins_encode( enc_std(src, mem) );
6503   ins_pipe(pipe_class_memory);
6504 %}
6505 
6506 // Store Compressed Oop
6507 instruct storeN(memory dst, iRegN_P2N src) %{
6508   match(Set dst (StoreN dst src));
6509   ins_cost(MEMORY_REF_COST);
6510 
6511   format %{ "STW     $src, $dst \t// compressed oop" %}
6512   size(4);
6513   ins_encode( enc_stw(src, dst) );
6514   ins_pipe(pipe_class_memory);
6515 %}
6516 
6517 // Store Compressed KLass
6518 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6519   match(Set dst (StoreNKlass dst src));
6520   ins_cost(MEMORY_REF_COST);
6521 
6522   format %{ "STW     $src, $dst \t// compressed klass" %}
6523   size(4);
6524   ins_encode( enc_stw(src, dst) );
6525   ins_pipe(pipe_class_memory);
6526 %}
6527 
6528 // Store Pointer
6529 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6530   match(Set dst (StoreP dst src));
6531   ins_cost(MEMORY_REF_COST);
6532 
6533   format %{ "STD     $src, $dst \t// ptr" %}
6534   size(4);
6535   ins_encode( enc_std(src, dst) );
6536   ins_pipe(pipe_class_memory);
6537 %}
6538 
6539 // Store Float
6540 instruct storeF(memory mem, regF src) %{
6541   match(Set mem (StoreF mem src));
6542   ins_cost(MEMORY_REF_COST);
6543 
6544   format %{ "STFS    $src, $mem" %}
6545   size(4);
6546   ins_encode( enc_stfs(src, mem) );
6547   ins_pipe(pipe_class_memory);
6548 %}
6549 
6550 // Store Double
6551 instruct storeD(memory mem, regD src) %{
6552   match(Set mem (StoreD mem src));
6553   ins_cost(MEMORY_REF_COST);
6554 
6555   format %{ "STFD    $src, $mem" %}
6556   size(4);
6557   ins_encode( enc_stfd(src, mem) );
6558   ins_pipe(pipe_class_memory);
6559 %}
6560 
6561 //----------Store Instructions With Zeros--------------------------------------
6562 
6563 // Card-mark for CMS garbage collection.
6564 // This cardmark does an optimization so that it must not always
6565 // do a releasing store. For this, it gets the address of
6566 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6567 // (Using releaseFieldAddr in the match rule is a hack.)
6568 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
6569   match(Set mem (StoreCM mem releaseFieldAddr));
6570   effect(TEMP crx);
6571   predicate(false);
6572   ins_cost(MEMORY_REF_COST);
6573 
6574   // See loadConP.
6575   ins_cannot_rematerialize(true);
6576 
6577   format %{ "STB     #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6578   ins_encode( enc_cms_card_mark(mem, releaseFieldAddr, crx) );
6579   ins_pipe(pipe_class_memory);
6580 %}
6581 
6582 // Card-mark for CMS garbage collection.
6583 // This cardmark does an optimization so that it must not always
6584 // do a releasing store. For this, it needs the constant address of
6585 // CMSCollectorCardTableModRefBSExt::_requires_release.
6586 // This constant address is split off here by expand so we can use
6587 // adlc / matcher functionality to load it from the constant section.
6588 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6589   match(Set mem (StoreCM mem zero));
6590   predicate(UseConcMarkSweepGC);
6591 
6592   expand %{
6593     immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6594     iRegLdst releaseFieldAddress;
6595     flagsReg crx;
6596     loadConL_Ex(releaseFieldAddress, baseImm);
6597     storeCM_CMS(mem, releaseFieldAddress, crx);
6598   %}
6599 %}
6600 
6601 instruct storeCM_G1(memory mem, immI_0 zero) %{
6602   match(Set mem (StoreCM mem zero));
6603   predicate(UseG1GC);
6604   ins_cost(MEMORY_REF_COST);
6605 
6606   ins_cannot_rematerialize(true);
6607 
6608   format %{ "STB     #0, $mem \t// CMS card-mark byte store (G1)" %}
6609   size(8);
6610   ins_encode %{
6611     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6612     __ li(R0, 0);
6613     //__ release(); // G1: oops are allowed to get visible after dirty marking
6614     guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6615     __ stb(R0, $mem$$disp, $mem$$base$$Register);
6616   %}
6617   ins_pipe(pipe_class_memory);
6618 %}
6619 
6620 // Convert oop pointer into compressed form.
6621 
6622 // Nodes for postalloc expand.
6623 
6624 // Shift node for expand.
6625 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6626   // The match rule is needed to make it a 'MachTypeNode'!
6627   match(Set dst (EncodeP src));
6628   predicate(false);
6629 
6630   format %{ "SRDI    $dst, $src, 3 \t// encode" %}
6631   size(4);
6632   ins_encode %{
6633     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6634     __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6635   %}
6636   ins_pipe(pipe_class_default);
6637 %}
6638 
6639 // Add node for expand.
6640 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6641   // The match rule is needed to make it a 'MachTypeNode'!
6642   match(Set dst (EncodeP src));
6643   predicate(false);
6644 
6645   format %{ "SUB     $dst, $src, oop_base \t// encode" %}
6646   ins_encode %{
6647     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6648     __ sub_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6649   %}
6650   ins_pipe(pipe_class_default);
6651 %}
6652 
6653 // Conditional sub base.
6654 instruct cond_sub_base(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6655   // The match rule is needed to make it a 'MachTypeNode'!
6656   match(Set dst (EncodeP (Binary crx src1)));
6657   predicate(false);
6658 
6659   format %{ "BEQ     $crx, done\n\t"
6660             "SUB     $dst, $src1, heapbase \t// encode: subtract base if != NULL\n"
6661             "done:" %}
6662   ins_encode %{
6663     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6664     Label done;
6665     __ beq($crx$$CondRegister, done);
6666     __ sub_const_optimized($dst$$Register, $src1$$Register, Universe::narrow_oop_base(), R0);
6667     __ bind(done);
6668   %}
6669   ins_pipe(pipe_class_default);
6670 %}
6671 
6672 // Power 7 can use isel instruction
6673 instruct cond_set_0_oop(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6674   // The match rule is needed to make it a 'MachTypeNode'!
6675   match(Set dst (EncodeP (Binary crx src1)));
6676   predicate(false);
6677 
6678   format %{ "CMOVE   $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6679   size(4);
6680   ins_encode %{
6681     // This is a Power7 instruction for which no machine description exists.
6682     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6683     __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6684   %}
6685   ins_pipe(pipe_class_default);
6686 %}
6687 
6688 // Disjoint narrow oop base.
6689 instruct encodeP_Disjoint(iRegNdst dst, iRegPsrc src) %{
6690   match(Set dst (EncodeP src));
6691   predicate(Universe::narrow_oop_base_disjoint());
6692 
6693   format %{ "EXTRDI  $dst, $src, #32, #3 \t// encode with disjoint base" %}
6694   size(4);
6695   ins_encode %{
6696     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6697     __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6698   %}
6699   ins_pipe(pipe_class_default);
6700 %}
6701 
6702 // shift != 0, base != 0
6703 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6704   match(Set dst (EncodeP src));
6705   effect(TEMP crx);
6706   predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6707             Universe::narrow_oop_shift() != 0 &&
6708             Universe::narrow_oop_base_overlaps());
6709 
6710   format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6711   postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6712 %}
6713 
6714 // shift != 0, base != 0
6715 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6716   match(Set dst (EncodeP src));
6717   predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6718             Universe::narrow_oop_shift() != 0 &&
6719             Universe::narrow_oop_base_overlaps());
6720 
6721   format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6722   postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6723 %}
6724 
6725 // shift != 0, base == 0
6726 // TODO: This is the same as encodeP_shift. Merge!
6727 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6728   match(Set dst (EncodeP src));
6729   predicate(Universe::narrow_oop_shift() != 0 &&
6730             Universe::narrow_oop_base() ==0);
6731 
6732   format %{ "SRDI    $dst, $src, #3 \t// encodeP, $src != NULL" %}
6733   size(4);
6734   ins_encode %{
6735     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6736     __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6737   %}
6738   ins_pipe(pipe_class_default);
6739 %}
6740 
6741 // Compressed OOPs with narrow_oop_shift == 0.
6742 // shift == 0, base == 0
6743 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6744   match(Set dst (EncodeP src));
6745   predicate(Universe::narrow_oop_shift() == 0);
6746 
6747   format %{ "MR      $dst, $src \t// Ptr->Narrow" %}
6748   // variable size, 0 or 4.
6749   ins_encode %{
6750     // TODO: PPC port $archOpcode(ppc64Opcode_or);
6751     __ mr_if_needed($dst$$Register, $src$$Register);
6752   %}
6753   ins_pipe(pipe_class_default);
6754 %}
6755 
6756 // Decode nodes.
6757 
6758 // Shift node for expand.
6759 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6760   // The match rule is needed to make it a 'MachTypeNode'!
6761   match(Set dst (DecodeN src));
6762   predicate(false);
6763 
6764   format %{ "SLDI    $dst, $src, #3 \t// DecodeN" %}
6765   size(4);
6766   ins_encode %{
6767     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6768     __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6769   %}
6770   ins_pipe(pipe_class_default);
6771 %}
6772 
6773 // Add node for expand.
6774 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6775   // The match rule is needed to make it a 'MachTypeNode'!
6776   match(Set dst (DecodeN src));
6777   predicate(false);
6778 
6779   format %{ "ADD     $dst, $src, heapbase \t// DecodeN, add oop base" %}
6780   ins_encode %{
6781     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6782     __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6783   %}
6784   ins_pipe(pipe_class_default);
6785 %}
6786 
6787 // conditianal add base for expand
6788 instruct cond_add_base(iRegPdst dst, flagsRegSrc crx, iRegPsrc src) %{
6789   // The match rule is needed to make it a 'MachTypeNode'!
6790   // NOTICE that the rule is nonsense - we just have to make sure that:
6791   //  - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6792   //  - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6793   match(Set dst (DecodeN (Binary crx src)));
6794   predicate(false);
6795 
6796   format %{ "BEQ     $crx, done\n\t"
6797             "ADD     $dst, $src, heapbase \t// DecodeN: add oop base if $src != NULL\n"
6798             "done:" %}
6799   ins_encode %{
6800     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6801     Label done;
6802     __ beq($crx$$CondRegister, done);
6803     __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6804     __ bind(done);
6805   %}
6806   ins_pipe(pipe_class_default);
6807 %}
6808 
6809 instruct cond_set_0_ptr(iRegPdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6810   // The match rule is needed to make it a 'MachTypeNode'!
6811   // NOTICE that the rule is nonsense - we just have to make sure that:
6812   //  - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6813   //  - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6814   match(Set dst (DecodeN (Binary crx src1)));
6815   predicate(false);
6816 
6817   format %{ "CMOVE   $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6818   size(4);
6819   ins_encode %{
6820     // This is a Power7 instruction for which no machine description exists.
6821     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6822     __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6823   %}
6824   ins_pipe(pipe_class_default);
6825 %}
6826 
6827 //  shift != 0, base != 0
6828 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6829   match(Set dst (DecodeN src));
6830   predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6831              n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6832             Universe::narrow_oop_shift() != 0 &&
6833             Universe::narrow_oop_base() != 0);
6834   ins_cost(4 * DEFAULT_COST); // Should be more expensive than decodeN_Disjoint_isel_Ex.
6835   effect(TEMP crx);
6836 
6837   format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6838   postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6839 %}
6840 
6841 // shift != 0, base == 0
6842 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6843   match(Set dst (DecodeN src));
6844   predicate(Universe::narrow_oop_shift() != 0 &&
6845             Universe::narrow_oop_base() == 0);
6846 
6847   format %{ "SLDI    $dst, $src, #3 \t// DecodeN (zerobased)" %}
6848   size(4);
6849   ins_encode %{
6850     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6851     __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6852   %}
6853   ins_pipe(pipe_class_default);
6854 %}
6855 
6856 // Optimize DecodeN for disjoint base.
6857 // Shift narrow oop and or it into register that already contains the heap base.
6858 // Base == dst must hold, and is assured by construction in postaloc_expand.
6859 instruct decodeN_mergeDisjoint(iRegPdst dst, iRegNsrc src, iRegLsrc base) %{
6860   match(Set dst (DecodeN src));
6861   effect(TEMP base);
6862   predicate(false);
6863 
6864   format %{ "RLDIMI  $dst, $src, shift, 32-shift \t// DecodeN (disjoint base)" %}
6865   size(4);
6866   ins_encode %{
6867     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
6868     __ rldimi($dst$$Register, $src$$Register, Universe::narrow_oop_shift(), 32-Universe::narrow_oop_shift());
6869   %}
6870   ins_pipe(pipe_class_default);
6871 %}
6872 
6873 // Optimize DecodeN for disjoint base.
6874 // This node requires only one cycle on the critical path.
6875 // We must postalloc_expand as we can not express use_def effects where
6876 // the used register is L and the def'ed register P.
6877 instruct decodeN_Disjoint_notNull_Ex(iRegPdst dst, iRegNsrc src) %{
6878   match(Set dst (DecodeN src));
6879   effect(TEMP_DEF dst);
6880   predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6881              n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6882             Universe::narrow_oop_base_disjoint());
6883   ins_cost(DEFAULT_COST);
6884 
6885   format %{ "MOV     $dst, heapbase \t\n"
6886             "RLDIMI  $dst, $src, shift, 32-shift \t// decode with disjoint base" %}
6887   postalloc_expand %{
6888     loadBaseNode *n1 = new loadBaseNode();
6889     n1->add_req(NULL);
6890     n1->_opnds[0] = op_dst;
6891 
6892     decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6893     n2->add_req(n_region, n_src, n1);
6894     n2->_opnds[0] = op_dst;
6895     n2->_opnds[1] = op_src;
6896     n2->_opnds[2] = op_dst;
6897     n2->_bottom_type = _bottom_type;
6898 
6899     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6900     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6901 
6902     nodes->push(n1);
6903     nodes->push(n2);
6904   %}
6905 %}
6906 
6907 instruct decodeN_Disjoint_isel_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6908   match(Set dst (DecodeN src));
6909   effect(TEMP_DEF dst, TEMP crx);
6910   predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6911              n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6912             Universe::narrow_oop_base_disjoint() && VM_Version::has_isel());
6913   ins_cost(3 * DEFAULT_COST);
6914 
6915   format %{ "DecodeN  $dst, $src \t// decode with disjoint base using isel" %}
6916   postalloc_expand %{
6917     loadBaseNode *n1 = new loadBaseNode();
6918     n1->add_req(NULL);
6919     n1->_opnds[0] = op_dst;
6920 
6921     cmpN_reg_imm0Node *n_compare  = new cmpN_reg_imm0Node();
6922     n_compare->add_req(n_region, n_src);
6923     n_compare->_opnds[0] = op_crx;
6924     n_compare->_opnds[1] = op_src;
6925     n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
6926 
6927     decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6928     n2->add_req(n_region, n_src, n1);
6929     n2->_opnds[0] = op_dst;
6930     n2->_opnds[1] = op_src;
6931     n2->_opnds[2] = op_dst;
6932     n2->_bottom_type = _bottom_type;
6933 
6934     cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
6935     n_cond_set->add_req(n_region, n_compare, n2);
6936     n_cond_set->_opnds[0] = op_dst;
6937     n_cond_set->_opnds[1] = op_crx;
6938     n_cond_set->_opnds[2] = op_dst;
6939     n_cond_set->_bottom_type = _bottom_type;
6940 
6941     assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
6942     ra_->set_oop(n_cond_set, true);
6943 
6944     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6945     ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
6946     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6947     ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6948 
6949     nodes->push(n1);
6950     nodes->push(n_compare);
6951     nodes->push(n2);
6952     nodes->push(n_cond_set);
6953   %}
6954 %}
6955 
6956 // src != 0, shift != 0, base != 0
6957 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6958   match(Set dst (DecodeN src));
6959   predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6960              n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6961             Universe::narrow_oop_shift() != 0 &&
6962             Universe::narrow_oop_base() != 0);
6963   ins_cost(2 * DEFAULT_COST);
6964 
6965   format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6966   postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6967 %}
6968 
6969 // Compressed OOPs with narrow_oop_shift == 0.
6970 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6971   match(Set dst (DecodeN src));
6972   predicate(Universe::narrow_oop_shift() == 0);
6973   ins_cost(DEFAULT_COST);
6974 
6975   format %{ "MR      $dst, $src \t// DecodeN (unscaled)" %}
6976   // variable size, 0 or 4.
6977   ins_encode %{
6978     // TODO: PPC port $archOpcode(ppc64Opcode_or);
6979     __ mr_if_needed($dst$$Register, $src$$Register);
6980   %}
6981   ins_pipe(pipe_class_default);
6982 %}
6983 
6984 // Convert compressed oop into int for vectors alignment masking.
6985 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6986   match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6987   predicate(Universe::narrow_oop_shift() == 0);
6988   ins_cost(DEFAULT_COST);
6989 
6990   format %{ "MR      $dst, $src \t// (int)DecodeN (unscaled)" %}
6991   // variable size, 0 or 4.
6992   ins_encode %{
6993     // TODO: PPC port $archOpcode(ppc64Opcode_or);
6994     __ mr_if_needed($dst$$Register, $src$$Register);
6995   %}
6996   ins_pipe(pipe_class_default);
6997 %}
6998 
6999 // Convert klass pointer into compressed form.
7000 
7001 // Nodes for postalloc expand.
7002 
7003 // Shift node for expand.
7004 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
7005   // The match rule is needed to make it a 'MachTypeNode'!
7006   match(Set dst (EncodePKlass src));
7007   predicate(false);
7008 
7009   format %{ "SRDI    $dst, $src, 3 \t// encode" %}
7010   size(4);
7011   ins_encode %{
7012     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
7013     __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7014   %}
7015   ins_pipe(pipe_class_default);
7016 %}
7017 
7018 // Add node for expand.
7019 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7020   // The match rule is needed to make it a 'MachTypeNode'!
7021   match(Set dst (EncodePKlass (Binary base src)));
7022   predicate(false);
7023 
7024   format %{ "SUB     $dst, $base, $src \t// encode" %}
7025   size(4);
7026   ins_encode %{
7027     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7028     __ subf($dst$$Register, $base$$Register, $src$$Register);
7029   %}
7030   ins_pipe(pipe_class_default);
7031 %}
7032 
7033 // Disjoint narrow oop base.
7034 instruct encodePKlass_Disjoint(iRegNdst dst, iRegPsrc src) %{
7035   match(Set dst (EncodePKlass src));
7036   predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
7037 
7038   format %{ "EXTRDI  $dst, $src, #32, #3 \t// encode with disjoint base" %}
7039   size(4);
7040   ins_encode %{
7041     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
7042     __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32);
7043   %}
7044   ins_pipe(pipe_class_default);
7045 %}
7046 
7047 // shift != 0, base != 0
7048 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
7049   match(Set dst (EncodePKlass (Binary base src)));
7050   predicate(false);
7051 
7052   format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7053   postalloc_expand %{
7054     encodePKlass_sub_baseNode *n1 = new encodePKlass_sub_baseNode();
7055     n1->add_req(n_region, n_base, n_src);
7056     n1->_opnds[0] = op_dst;
7057     n1->_opnds[1] = op_base;
7058     n1->_opnds[2] = op_src;
7059     n1->_bottom_type = _bottom_type;
7060 
7061     encodePKlass_shiftNode *n2 = new encodePKlass_shiftNode();
7062     n2->add_req(n_region, n1);
7063     n2->_opnds[0] = op_dst;
7064     n2->_opnds[1] = op_dst;
7065     n2->_bottom_type = _bottom_type;
7066     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7067     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7068 
7069     nodes->push(n1);
7070     nodes->push(n2);
7071   %}
7072 %}
7073 
7074 // shift != 0, base != 0
7075 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
7076   match(Set dst (EncodePKlass src));
7077   //predicate(Universe::narrow_klass_shift() != 0 &&
7078   //          true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
7079 
7080   //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7081   ins_cost(DEFAULT_COST*2);  // Don't count constant.
7082   expand %{
7083     immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
7084     iRegLdst base;
7085     loadConL_Ex(base, baseImm);
7086     encodePKlass_not_null_Ex(dst, base, src);
7087   %}
7088 %}
7089 
7090 // Decode nodes.
7091 
7092 // Shift node for expand.
7093 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
7094   // The match rule is needed to make it a 'MachTypeNode'!
7095   match(Set dst (DecodeNKlass src));
7096   predicate(false);
7097 
7098   format %{ "SLDI    $dst, $src, #3 \t// DecodeNKlass" %}
7099   size(4);
7100   ins_encode %{
7101     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
7102     __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7103   %}
7104   ins_pipe(pipe_class_default);
7105 %}
7106 
7107 // Add node for expand.
7108 
7109 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7110   // The match rule is needed to make it a 'MachTypeNode'!
7111   match(Set dst (DecodeNKlass (Binary base src)));
7112   predicate(false);
7113 
7114   format %{ "ADD     $dst, $base, $src \t// DecodeNKlass, add klass base" %}
7115   size(4);
7116   ins_encode %{
7117     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7118     __ add($dst$$Register, $base$$Register, $src$$Register);
7119   %}
7120   ins_pipe(pipe_class_default);
7121 %}
7122 
7123 // src != 0, shift != 0, base != 0
7124 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
7125   match(Set dst (DecodeNKlass (Binary base src)));
7126   //effect(kill src); // We need a register for the immediate result after shifting.
7127   predicate(false);
7128 
7129   format %{ "DecodeNKlass $dst =  $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
7130   postalloc_expand %{
7131     decodeNKlass_add_baseNode *n1 = new decodeNKlass_add_baseNode();
7132     n1->add_req(n_region, n_base, n_src);
7133     n1->_opnds[0] = op_dst;
7134     n1->_opnds[1] = op_base;
7135     n1->_opnds[2] = op_src;
7136     n1->_bottom_type = _bottom_type;
7137 
7138     decodeNKlass_shiftNode *n2 = new decodeNKlass_shiftNode();
7139     n2->add_req(n_region, n1);
7140     n2->_opnds[0] = op_dst;
7141     n2->_opnds[1] = op_dst;
7142     n2->_bottom_type = _bottom_type;
7143 
7144     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7145     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7146 
7147     nodes->push(n1);
7148     nodes->push(n2);
7149   %}
7150 %}
7151 
7152 // src != 0, shift != 0, base != 0
7153 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7154   match(Set dst (DecodeNKlass src));
7155   // predicate(Universe::narrow_klass_shift() != 0 &&
7156   //           Universe::narrow_klass_base() != 0);
7157 
7158   //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7159 
7160   ins_cost(DEFAULT_COST*2);  // Don't count constant.
7161   expand %{
7162     // We add first, then we shift. Like this, we can get along with one register less.
7163     // But we have to load the base pre-shifted.
7164     immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7165     iRegLdst base;
7166     loadConL_Ex(base, baseImm);
7167     decodeNKlass_notNull_addBase_Ex(dst, base, src);
7168   %}
7169 %}
7170 
7171 //----------MemBar Instructions-----------------------------------------------
7172 // Memory barrier flavors
7173 
7174 instruct membar_acquire() %{
7175   match(LoadFence);
7176   ins_cost(4*MEMORY_REF_COST);
7177 
7178   format %{ "MEMBAR-acquire" %}
7179   size(4);
7180   ins_encode %{
7181     // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7182     __ acquire();
7183   %}
7184   ins_pipe(pipe_class_default);
7185 %}
7186 
7187 instruct unnecessary_membar_acquire() %{
7188   match(MemBarAcquire);
7189   ins_cost(0);
7190 
7191   format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7192   size(0);
7193   ins_encode( /*empty*/ );
7194   ins_pipe(pipe_class_default);
7195 %}
7196 
7197 instruct membar_acquire_lock() %{
7198   match(MemBarAcquireLock);
7199   ins_cost(0);
7200 
7201   format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7202   size(0);
7203   ins_encode( /*empty*/ );
7204   ins_pipe(pipe_class_default);
7205 %}
7206 
7207 instruct membar_release() %{
7208   match(MemBarRelease);
7209   match(StoreFence);
7210   ins_cost(4*MEMORY_REF_COST);
7211 
7212   format %{ "MEMBAR-release" %}
7213   size(4);
7214   ins_encode %{
7215     // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7216     __ release();
7217   %}
7218   ins_pipe(pipe_class_default);
7219 %}
7220 
7221 instruct membar_storestore() %{
7222   match(MemBarStoreStore);
7223   ins_cost(4*MEMORY_REF_COST);
7224 
7225   format %{ "MEMBAR-store-store" %}
7226   size(4);
7227   ins_encode %{
7228     // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7229     __ membar(Assembler::StoreStore);
7230   %}
7231   ins_pipe(pipe_class_default);
7232 %}
7233 
7234 instruct membar_release_lock() %{
7235   match(MemBarReleaseLock);
7236   ins_cost(0);
7237 
7238   format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7239   size(0);
7240   ins_encode( /*empty*/ );
7241   ins_pipe(pipe_class_default);
7242 %}
7243 
7244 instruct membar_volatile() %{
7245   match(MemBarVolatile);
7246   ins_cost(4*MEMORY_REF_COST);
7247 
7248   format %{ "MEMBAR-volatile" %}
7249   size(4);
7250   ins_encode %{
7251     // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7252     __ fence();
7253   %}
7254   ins_pipe(pipe_class_default);
7255 %}
7256 
7257 // This optimization is wrong on PPC. The following pattern is not supported:
7258 //  MemBarVolatile
7259 //   ^        ^
7260 //   |        |
7261 //  CtrlProj MemProj
7262 //   ^        ^
7263 //   |        |
7264 //   |       Load
7265 //   |
7266 //  MemBarVolatile
7267 //
7268 //  The first MemBarVolatile could get optimized out! According to
7269 //  Vladimir, this pattern can not occur on Oracle platforms.
7270 //  However, it does occur on PPC64 (because of membars in
7271 //  inline_unsafe_load_store).
7272 //
7273 // Add this node again if we found a good solution for inline_unsafe_load_store().
7274 // Don't forget to look at the implementation of post_store_load_barrier again,
7275 // we did other fixes in that method.
7276 //instruct unnecessary_membar_volatile() %{
7277 //  match(MemBarVolatile);
7278 //  predicate(Matcher::post_store_load_barrier(n));
7279 //  ins_cost(0);
7280 //
7281 //  format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7282 //  size(0);
7283 //  ins_encode( /*empty*/ );
7284 //  ins_pipe(pipe_class_default);
7285 //%}
7286 
7287 instruct membar_CPUOrder() %{
7288   match(MemBarCPUOrder);
7289   ins_cost(0);
7290 
7291   format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7292   size(0);
7293   ins_encode( /*empty*/ );
7294   ins_pipe(pipe_class_default);
7295 %}
7296 
7297 //----------Conditional Move---------------------------------------------------
7298 
7299 // Cmove using isel.
7300 instruct cmovI_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7301   match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7302   predicate(VM_Version::has_isel());
7303   ins_cost(DEFAULT_COST);
7304 
7305   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7306   size(4);
7307   ins_encode %{
7308     // This is a Power7 instruction for which no machine description
7309     // exists. Anyways, the scheduler should be off on Power7.
7310     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7311     int cc        = $cmp$$cmpcode;
7312     __ isel($dst$$Register, $crx$$CondRegister,
7313             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7314   %}
7315   ins_pipe(pipe_class_default);
7316 %}
7317 
7318 instruct cmovI_reg(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7319   match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7320   predicate(!VM_Version::has_isel());
7321   ins_cost(DEFAULT_COST+BRANCH_COST);
7322 
7323   ins_variable_size_depending_on_alignment(true);
7324 
7325   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7326   // Worst case is branch + move + stop, no stop without scheduler
7327   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7328   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7329   ins_pipe(pipe_class_default);
7330 %}
7331 
7332 instruct cmovI_imm(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, immI16 src) %{
7333   match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7334   ins_cost(DEFAULT_COST+BRANCH_COST);
7335 
7336   ins_variable_size_depending_on_alignment(true);
7337 
7338   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7339   // Worst case is branch + move + stop, no stop without scheduler
7340   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7341   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7342   ins_pipe(pipe_class_default);
7343 %}
7344 
7345 // Cmove using isel.
7346 instruct cmovL_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7347   match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7348   predicate(VM_Version::has_isel());
7349   ins_cost(DEFAULT_COST);
7350 
7351   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7352   size(4);
7353   ins_encode %{
7354     // This is a Power7 instruction for which no machine description
7355     // exists. Anyways, the scheduler should be off on Power7.
7356     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7357     int cc        = $cmp$$cmpcode;
7358     __ isel($dst$$Register, $crx$$CondRegister,
7359             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7360   %}
7361   ins_pipe(pipe_class_default);
7362 %}
7363 
7364 instruct cmovL_reg(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7365   match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7366   predicate(!VM_Version::has_isel());
7367   ins_cost(DEFAULT_COST+BRANCH_COST);
7368 
7369   ins_variable_size_depending_on_alignment(true);
7370 
7371   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7372   // Worst case is branch + move + stop, no stop without scheduler.
7373   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7374   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7375   ins_pipe(pipe_class_default);
7376 %}
7377 
7378 instruct cmovL_imm(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, immL16 src) %{
7379   match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7380   ins_cost(DEFAULT_COST+BRANCH_COST);
7381 
7382   ins_variable_size_depending_on_alignment(true);
7383 
7384   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7385   // Worst case is branch + move + stop, no stop without scheduler.
7386   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7387   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7388   ins_pipe(pipe_class_default);
7389 %}
7390 
7391 // Cmove using isel.
7392 instruct cmovN_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7393   match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7394   predicate(VM_Version::has_isel());
7395   ins_cost(DEFAULT_COST);
7396 
7397   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7398   size(4);
7399   ins_encode %{
7400     // This is a Power7 instruction for which no machine description
7401     // exists. Anyways, the scheduler should be off on Power7.
7402     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7403     int cc        = $cmp$$cmpcode;
7404     __ isel($dst$$Register, $crx$$CondRegister,
7405             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7406   %}
7407   ins_pipe(pipe_class_default);
7408 %}
7409 
7410 // Conditional move for RegN. Only cmov(reg, reg).
7411 instruct cmovN_reg(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7412   match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7413   predicate(!VM_Version::has_isel());
7414   ins_cost(DEFAULT_COST+BRANCH_COST);
7415 
7416   ins_variable_size_depending_on_alignment(true);
7417 
7418   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7419   // Worst case is branch + move + stop, no stop without scheduler.
7420   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7421   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7422   ins_pipe(pipe_class_default);
7423 %}
7424 
7425 instruct cmovN_imm(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, immN_0 src) %{
7426   match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7427   ins_cost(DEFAULT_COST+BRANCH_COST);
7428 
7429   ins_variable_size_depending_on_alignment(true);
7430 
7431   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7432   // Worst case is branch + move + stop, no stop without scheduler.
7433   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7434   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7435   ins_pipe(pipe_class_default);
7436 %}
7437 
7438 // Cmove using isel.
7439 instruct cmovP_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegPsrc src) %{
7440   match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7441   predicate(VM_Version::has_isel());
7442   ins_cost(DEFAULT_COST);
7443 
7444   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7445   size(4);
7446   ins_encode %{
7447     // This is a Power7 instruction for which no machine description
7448     // exists. Anyways, the scheduler should be off on Power7.
7449     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7450     int cc        = $cmp$$cmpcode;
7451     __ isel($dst$$Register, $crx$$CondRegister,
7452             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7453   %}
7454   ins_pipe(pipe_class_default);
7455 %}
7456 
7457 instruct cmovP_reg(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegP_N2P src) %{
7458   match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7459   predicate(!VM_Version::has_isel());
7460   ins_cost(DEFAULT_COST+BRANCH_COST);
7461 
7462   ins_variable_size_depending_on_alignment(true);
7463 
7464   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7465   // Worst case is branch + move + stop, no stop without scheduler.
7466   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7467   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7468   ins_pipe(pipe_class_default);
7469 %}
7470 
7471 instruct cmovP_imm(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, immP_0 src) %{
7472   match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7473   ins_cost(DEFAULT_COST+BRANCH_COST);
7474 
7475   ins_variable_size_depending_on_alignment(true);
7476 
7477   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7478   // Worst case is branch + move + stop, no stop without scheduler.
7479   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7480   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7481   ins_pipe(pipe_class_default);
7482 %}
7483 
7484 instruct cmovF_reg(cmpOp cmp, flagsRegSrc crx, regF dst, regF src) %{
7485   match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7486   ins_cost(DEFAULT_COST+BRANCH_COST);
7487 
7488   ins_variable_size_depending_on_alignment(true);
7489 
7490   format %{ "CMOVEF  $cmp, $crx, $dst, $src\n\t" %}
7491   // Worst case is branch + move + stop, no stop without scheduler.
7492   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7493   ins_encode %{
7494     // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7495     Label done;
7496     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7497     // Branch if not (cmp crx).
7498     __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7499     __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7500     // TODO PPC port __ endgroup_if_needed(_size == 12);
7501     __ bind(done);
7502   %}
7503   ins_pipe(pipe_class_default);
7504 %}
7505 
7506 instruct cmovD_reg(cmpOp cmp, flagsRegSrc crx, regD dst, regD src) %{
7507   match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7508   ins_cost(DEFAULT_COST+BRANCH_COST);
7509 
7510   ins_variable_size_depending_on_alignment(true);
7511 
7512   format %{ "CMOVEF  $cmp, $crx, $dst, $src\n\t" %}
7513   // Worst case is branch + move + stop, no stop without scheduler.
7514   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7515   ins_encode %{
7516     // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7517     Label done;
7518     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7519     // Branch if not (cmp crx).
7520     __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7521     __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7522     // TODO PPC port __ endgroup_if_needed(_size == 12);
7523     __ bind(done);
7524   %}
7525   ins_pipe(pipe_class_default);
7526 %}
7527 
7528 //----------Conditional_store--------------------------------------------------
7529 // Conditional-store of the updated heap-top.
7530 // Used during allocation of the shared heap.
7531 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7532 
7533 // As compareAndSwapL, but return flag register instead of boolean value in
7534 // int register.
7535 // Used by sun/misc/AtomicLongCSImpl.java.
7536 // Mem_ptr must be a memory operand, else this node does not get
7537 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7538 // can be rematerialized which leads to errors.
7539 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal, flagsRegCR0 cr0) %{
7540   match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7541   effect(TEMP cr0);
7542   format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7543   ins_encode %{
7544     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7545     __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7546                 MacroAssembler::MemBarAcq, MacroAssembler::cmpxchgx_hint_atomic_update(),
7547                 noreg, NULL, true);
7548   %}
7549   ins_pipe(pipe_class_default);
7550 %}
7551 
7552 // As compareAndSwapP, but return flag register instead of boolean value in
7553 // int register.
7554 // This instruction is matched if UseTLAB is off.
7555 // Mem_ptr must be a memory operand, else this node does not get
7556 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7557 // can be rematerialized which leads to errors.
7558 instruct storePConditional_regP_regP_regP(flagsRegCR0 cr0, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7559   match(Set cr0 (StorePConditional mem_ptr (Binary oldVal newVal)));
7560   ins_cost(2*MEMORY_REF_COST);
7561 
7562   format %{ "STDCX_  if ($cr0 = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7563   ins_encode %{
7564     // TODO: PPC port $archOpcode(ppc64Opcode_stdcx_);
7565     __ stdcx_($newVal$$Register, $mem_ptr$$Register);
7566   %}
7567   ins_pipe(pipe_class_memory);
7568 %}
7569 
7570 // Implement LoadPLocked. Must be ordered against changes of the memory location
7571 // by storePConditional.
7572 // Don't know whether this is ever used.
7573 instruct loadPLocked(iRegPdst dst, memory mem) %{
7574   match(Set dst (LoadPLocked mem));
7575   ins_cost(2*MEMORY_REF_COST);
7576 
7577   format %{ "LDARX   $dst, $mem \t// loadPLocked\n\t" %}
7578   size(4);
7579   ins_encode %{
7580     // TODO: PPC port $archOpcode(ppc64Opcode_ldarx);
7581     __ ldarx($dst$$Register, $mem$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
7582   %}
7583   ins_pipe(pipe_class_memory);
7584 %}
7585 
7586 //----------Compare-And-Swap---------------------------------------------------
7587 
7588 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7589 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))"  cannot be
7590 // matched.
7591 
7592 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7593   match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7594   effect(TEMP cr0);
7595   format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7596   // Variable size: instruction count smaller if regs are disjoint.
7597   ins_encode %{
7598     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7599     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7600     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7601                 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7602                 $res$$Register, true);
7603   %}
7604   ins_pipe(pipe_class_default);
7605 %}
7606 
7607 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
7608   match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7609   effect(TEMP cr0);
7610   format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7611   // Variable size: instruction count smaller if regs are disjoint.
7612   ins_encode %{
7613     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7614     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7615     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7616                 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7617                 $res$$Register, true);
7618   %}
7619   ins_pipe(pipe_class_default);
7620 %}
7621 
7622 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
7623   match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7624   effect(TEMP cr0);
7625   format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7626   // Variable size: instruction count smaller if regs are disjoint.
7627   ins_encode %{
7628     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7629     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7630     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7631                 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7632                 $res$$Register, NULL, true);
7633   %}
7634   ins_pipe(pipe_class_default);
7635 %}
7636 
7637 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
7638   match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7639   effect(TEMP cr0);
7640   format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7641   // Variable size: instruction count smaller if regs are disjoint.
7642   ins_encode %{
7643     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7644     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7645     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7646                 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7647                 $res$$Register, NULL, true);
7648   %}
7649   ins_pipe(pipe_class_default);
7650 %}
7651 
7652 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7653   match(Set res (GetAndAddI mem_ptr src));
7654   effect(TEMP cr0);
7655   format %{ "GetAndAddI $res, $mem_ptr, $src" %}
7656   // Variable size: instruction count smaller if regs are disjoint.
7657   ins_encode( enc_GetAndAddI(res, mem_ptr, src) );
7658   ins_pipe(pipe_class_default);
7659 %}
7660 
7661 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
7662   match(Set res (GetAndAddL mem_ptr src));
7663   effect(TEMP cr0);
7664   format %{ "GetAndAddL $res, $mem_ptr, $src" %}
7665   // Variable size: instruction count smaller if regs are disjoint.
7666   ins_encode( enc_GetAndAddL(res, mem_ptr, src) );
7667   ins_pipe(pipe_class_default);
7668 %}
7669 
7670 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7671   match(Set res (GetAndSetI mem_ptr src));
7672   effect(TEMP cr0);
7673   format %{ "GetAndSetI $res, $mem_ptr, $src" %}
7674   // Variable size: instruction count smaller if regs are disjoint.
7675   ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7676   ins_pipe(pipe_class_default);
7677 %}
7678 
7679 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
7680   match(Set res (GetAndSetL mem_ptr src));
7681   effect(TEMP cr0);
7682   format %{ "GetAndSetL $res, $mem_ptr, $src" %}
7683   // Variable size: instruction count smaller if regs are disjoint.
7684   ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7685   ins_pipe(pipe_class_default);
7686 %}
7687 
7688 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src, flagsRegCR0 cr0) %{
7689   match(Set res (GetAndSetP mem_ptr src));
7690   effect(TEMP cr0);
7691   format %{ "GetAndSetP $res, $mem_ptr, $src" %}
7692   // Variable size: instruction count smaller if regs are disjoint.
7693   ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7694   ins_pipe(pipe_class_default);
7695 %}
7696 
7697 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src, flagsRegCR0 cr0) %{
7698   match(Set res (GetAndSetN mem_ptr src));
7699   effect(TEMP cr0);
7700   format %{ "GetAndSetN $res, $mem_ptr, $src" %}
7701   // Variable size: instruction count smaller if regs are disjoint.
7702   ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7703   ins_pipe(pipe_class_default);
7704 %}
7705 
7706 //----------Arithmetic Instructions--------------------------------------------
7707 // Addition Instructions
7708 
7709 // Register Addition
7710 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7711   match(Set dst (AddI src1 src2));
7712   format %{ "ADD     $dst, $src1, $src2" %}
7713   size(4);
7714   ins_encode %{
7715     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7716     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7717   %}
7718   ins_pipe(pipe_class_default);
7719 %}
7720 
7721 // Expand does not work with above instruct. (??)
7722 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7723   // no match-rule
7724   effect(DEF dst, USE src1, USE src2);
7725   format %{ "ADD     $dst, $src1, $src2" %}
7726   size(4);
7727   ins_encode %{
7728     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7729     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7730   %}
7731   ins_pipe(pipe_class_default);
7732 %}
7733 
7734 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
7735   match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
7736   ins_cost(DEFAULT_COST*3);
7737 
7738   expand %{
7739     // FIXME: we should do this in the ideal world.
7740     iRegIdst tmp1;
7741     iRegIdst tmp2;
7742     addI_reg_reg(tmp1, src1, src2);
7743     addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
7744     addI_reg_reg(dst, tmp1, tmp2);
7745   %}
7746 %}
7747 
7748 // Immediate Addition
7749 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7750   match(Set dst (AddI src1 src2));
7751   format %{ "ADDI    $dst, $src1, $src2" %}
7752   size(4);
7753   ins_encode %{
7754     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7755     __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7756   %}
7757   ins_pipe(pipe_class_default);
7758 %}
7759 
7760 // Immediate Addition with 16-bit shifted operand
7761 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
7762   match(Set dst (AddI src1 src2));
7763   format %{ "ADDIS   $dst, $src1, $src2" %}
7764   size(4);
7765   ins_encode %{
7766     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7767     __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7768   %}
7769   ins_pipe(pipe_class_default);
7770 %}
7771 
7772 // Long Addition
7773 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7774   match(Set dst (AddL src1 src2));
7775   format %{ "ADD     $dst, $src1, $src2 \t// long" %}
7776   size(4);
7777   ins_encode %{
7778     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7779     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7780   %}
7781   ins_pipe(pipe_class_default);
7782 %}
7783 
7784 // Expand does not work with above instruct. (??)
7785 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7786   // no match-rule
7787   effect(DEF dst, USE src1, USE src2);
7788   format %{ "ADD     $dst, $src1, $src2 \t// long" %}
7789   size(4);
7790   ins_encode %{
7791     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7792     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7793   %}
7794   ins_pipe(pipe_class_default);
7795 %}
7796 
7797 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
7798   match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
7799   ins_cost(DEFAULT_COST*3);
7800 
7801   expand %{
7802     // FIXME: we should do this in the ideal world.
7803     iRegLdst tmp1;
7804     iRegLdst tmp2;
7805     addL_reg_reg(tmp1, src1, src2);
7806     addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
7807     addL_reg_reg(dst, tmp1, tmp2);
7808   %}
7809 %}
7810 
7811 // AddL + ConvL2I.
7812 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7813   match(Set dst (ConvL2I (AddL src1 src2)));
7814 
7815   format %{ "ADD     $dst, $src1, $src2 \t// long + l2i" %}
7816   size(4);
7817   ins_encode %{
7818     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7819     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7820   %}
7821   ins_pipe(pipe_class_default);
7822 %}
7823 
7824 // No constant pool entries required.
7825 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7826   match(Set dst (AddL src1 src2));
7827 
7828   format %{ "ADDI    $dst, $src1, $src2" %}
7829   size(4);
7830   ins_encode %{
7831     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7832     __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7833   %}
7834   ins_pipe(pipe_class_default);
7835 %}
7836 
7837 // Long Immediate Addition with 16-bit shifted operand.
7838 // No constant pool entries required.
7839 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
7840   match(Set dst (AddL src1 src2));
7841 
7842   format %{ "ADDIS   $dst, $src1, $src2" %}
7843   size(4);
7844   ins_encode %{
7845     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7846     __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7847   %}
7848   ins_pipe(pipe_class_default);
7849 %}
7850 
7851 // Pointer Register Addition
7852 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
7853   match(Set dst (AddP src1 src2));
7854   format %{ "ADD     $dst, $src1, $src2" %}
7855   size(4);
7856   ins_encode %{
7857     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7858     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7859   %}
7860   ins_pipe(pipe_class_default);
7861 %}
7862 
7863 // Pointer Immediate Addition
7864 // No constant pool entries required.
7865 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
7866   match(Set dst (AddP src1 src2));
7867 
7868   format %{ "ADDI    $dst, $src1, $src2" %}
7869   size(4);
7870   ins_encode %{
7871     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7872     __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7873   %}
7874   ins_pipe(pipe_class_default);
7875 %}
7876 
7877 // Pointer Immediate Addition with 16-bit shifted operand.
7878 // No constant pool entries required.
7879 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
7880   match(Set dst (AddP src1 src2));
7881 
7882   format %{ "ADDIS   $dst, $src1, $src2" %}
7883   size(4);
7884   ins_encode %{
7885     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7886     __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7887   %}
7888   ins_pipe(pipe_class_default);
7889 %}
7890 
7891 //---------------------
7892 // Subtraction Instructions
7893 
7894 // Register Subtraction
7895 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7896   match(Set dst (SubI src1 src2));
7897   format %{ "SUBF    $dst, $src2, $src1" %}
7898   size(4);
7899   ins_encode %{
7900     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7901     __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7902   %}
7903   ins_pipe(pipe_class_default);
7904 %}
7905 
7906 // Immediate Subtraction
7907 // Immediate Subtraction: The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
7908 // Don't try to use addi with - $src2$$constant since it can overflow when $src2$$constant == minI16.
7909 
7910 // SubI from constant (using subfic).
7911 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
7912   match(Set dst (SubI src1 src2));
7913   format %{ "SUBI    $dst, $src1, $src2" %}
7914 
7915   size(4);
7916   ins_encode %{
7917     // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
7918     __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
7919   %}
7920   ins_pipe(pipe_class_default);
7921 %}
7922 
7923 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
7924 // positive integers and 0xF...F for negative ones.
7925 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
7926   // no match-rule, false predicate
7927   effect(DEF dst, USE src);
7928   predicate(false);
7929 
7930   format %{ "SRAWI   $dst, $src, #31" %}
7931   size(4);
7932   ins_encode %{
7933     // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
7934     __ srawi($dst$$Register, $src$$Register, 0x1f);
7935   %}
7936   ins_pipe(pipe_class_default);
7937 %}
7938 
7939 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
7940   match(Set dst (AbsI src));
7941   ins_cost(DEFAULT_COST*3);
7942 
7943   expand %{
7944     iRegIdst tmp1;
7945     iRegIdst tmp2;
7946     signmask32I_regI(tmp1, src);
7947     xorI_reg_reg(tmp2, tmp1, src);
7948     subI_reg_reg(dst, tmp2, tmp1);
7949   %}
7950 %}
7951 
7952 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
7953   match(Set dst (SubI zero src2));
7954   format %{ "NEG     $dst, $src2" %}
7955   size(4);
7956   ins_encode %{
7957     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7958     __ neg($dst$$Register, $src2$$Register);
7959   %}
7960   ins_pipe(pipe_class_default);
7961 %}
7962 
7963 // Long subtraction
7964 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7965   match(Set dst (SubL src1 src2));
7966   format %{ "SUBF    $dst, $src2, $src1 \t// long" %}
7967   size(4);
7968   ins_encode %{
7969     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7970     __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7971   %}
7972   ins_pipe(pipe_class_default);
7973 %}
7974 
7975 // SubL + convL2I.
7976 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7977   match(Set dst (ConvL2I (SubL src1 src2)));
7978 
7979   format %{ "SUBF    $dst, $src2, $src1 \t// long + l2i" %}
7980   size(4);
7981   ins_encode %{
7982     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7983     __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7984   %}
7985   ins_pipe(pipe_class_default);
7986 %}
7987 
7988 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7989 // positive longs and 0xF...F for negative ones.
7990 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{
7991   // no match-rule, false predicate
7992   effect(DEF dst, USE src);
7993   predicate(false);
7994 
7995   format %{ "SRADI   $dst, $src, #63" %}
7996   size(4);
7997   ins_encode %{
7998     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7999     __ sradi($dst$$Register, $src$$Register, 0x3f);
8000   %}
8001   ins_pipe(pipe_class_default);
8002 %}
8003 
8004 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
8005 // positive longs and 0xF...F for negative ones.
8006 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{
8007   // no match-rule, false predicate
8008   effect(DEF dst, USE src);
8009   predicate(false);
8010 
8011   format %{ "SRADI   $dst, $src, #63" %}
8012   size(4);
8013   ins_encode %{
8014     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8015     __ sradi($dst$$Register, $src$$Register, 0x3f);
8016   %}
8017   ins_pipe(pipe_class_default);
8018 %}
8019 
8020 // Long negation
8021 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
8022   match(Set dst (SubL zero src2));
8023   format %{ "NEG     $dst, $src2 \t// long" %}
8024   size(4);
8025   ins_encode %{
8026     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8027     __ neg($dst$$Register, $src2$$Register);
8028   %}
8029   ins_pipe(pipe_class_default);
8030 %}
8031 
8032 // NegL + ConvL2I.
8033 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
8034   match(Set dst (ConvL2I (SubL zero src2)));
8035 
8036   format %{ "NEG     $dst, $src2 \t// long + l2i" %}
8037   size(4);
8038   ins_encode %{
8039     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8040     __ neg($dst$$Register, $src2$$Register);
8041   %}
8042   ins_pipe(pipe_class_default);
8043 %}
8044 
8045 // Multiplication Instructions
8046 // Integer Multiplication
8047 
8048 // Register Multiplication
8049 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8050   match(Set dst (MulI src1 src2));
8051   ins_cost(DEFAULT_COST);
8052 
8053   format %{ "MULLW   $dst, $src1, $src2" %}
8054   size(4);
8055   ins_encode %{
8056     // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
8057     __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
8058   %}
8059   ins_pipe(pipe_class_default);
8060 %}
8061 
8062 // Immediate Multiplication
8063 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
8064   match(Set dst (MulI src1 src2));
8065   ins_cost(DEFAULT_COST);
8066 
8067   format %{ "MULLI   $dst, $src1, $src2" %}
8068   size(4);
8069   ins_encode %{
8070     // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8071     __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8072   %}
8073   ins_pipe(pipe_class_default);
8074 %}
8075 
8076 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8077   match(Set dst (MulL src1 src2));
8078   ins_cost(DEFAULT_COST);
8079 
8080   format %{ "MULLD   $dst $src1, $src2 \t// long" %}
8081   size(4);
8082   ins_encode %{
8083     // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
8084     __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
8085   %}
8086   ins_pipe(pipe_class_default);
8087 %}
8088 
8089 // Multiply high for optimized long division by constant.
8090 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8091   match(Set dst (MulHiL src1 src2));
8092   ins_cost(DEFAULT_COST);
8093 
8094   format %{ "MULHD   $dst $src1, $src2 \t// long" %}
8095   size(4);
8096   ins_encode %{
8097     // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
8098     __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
8099   %}
8100   ins_pipe(pipe_class_default);
8101 %}
8102 
8103 // Immediate Multiplication
8104 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8105   match(Set dst (MulL src1 src2));
8106   ins_cost(DEFAULT_COST);
8107 
8108   format %{ "MULLI   $dst, $src1, $src2" %}
8109   size(4);
8110   ins_encode %{
8111     // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8112     __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8113   %}
8114   ins_pipe(pipe_class_default);
8115 %}
8116 
8117 // Integer Division with Immediate -1: Negate.
8118 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8119   match(Set dst (DivI src1 src2));
8120   ins_cost(DEFAULT_COST);
8121 
8122   format %{ "NEG     $dst, $src1 \t// /-1" %}
8123   size(4);
8124   ins_encode %{
8125     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8126     __ neg($dst$$Register, $src1$$Register);
8127   %}
8128   ins_pipe(pipe_class_default);
8129 %}
8130 
8131 // Integer Division with constant, but not -1.
8132 // We should be able to improve this by checking the type of src2.
8133 // It might well be that src2 is known to be positive.
8134 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8135   match(Set dst (DivI src1 src2));
8136   predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8137   ins_cost(2*DEFAULT_COST);
8138 
8139   format %{ "DIVW    $dst, $src1, $src2 \t// /not-1" %}
8140   size(4);
8141   ins_encode %{
8142     // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8143     __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8144   %}
8145   ins_pipe(pipe_class_default);
8146 %}
8147 
8148 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src1) %{
8149   effect(USE_DEF dst, USE src1, USE crx);
8150   predicate(false);
8151 
8152   ins_variable_size_depending_on_alignment(true);
8153 
8154   format %{ "CMOVE   $dst, neg($src1), $crx" %}
8155   // Worst case is branch + move + stop, no stop without scheduler.
8156   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8157   ins_encode %{
8158     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8159     Label done;
8160     __ bne($crx$$CondRegister, done);
8161     __ neg($dst$$Register, $src1$$Register);
8162     // TODO PPC port __ endgroup_if_needed(_size == 12);
8163     __ bind(done);
8164   %}
8165   ins_pipe(pipe_class_default);
8166 %}
8167 
8168 // Integer Division with Registers not containing constants.
8169 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8170   match(Set dst (DivI src1 src2));
8171   ins_cost(10*DEFAULT_COST);
8172 
8173   expand %{
8174     immI16 imm %{ (int)-1 %}
8175     flagsReg tmp1;
8176     cmpI_reg_imm16(tmp1, src2, imm);          // check src2 == -1
8177     divI_reg_regnotMinus1(dst, src1, src2);   // dst = src1 / src2
8178     cmovI_bne_negI_reg(dst, tmp1, src1);      // cmove dst = neg(src1) if src2 == -1
8179   %}
8180 %}
8181 
8182 // Long Division with Immediate -1: Negate.
8183 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8184   match(Set dst (DivL src1 src2));
8185   ins_cost(DEFAULT_COST);
8186 
8187   format %{ "NEG     $dst, $src1 \t// /-1, long" %}
8188   size(4);
8189   ins_encode %{
8190     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8191     __ neg($dst$$Register, $src1$$Register);
8192   %}
8193   ins_pipe(pipe_class_default);
8194 %}
8195 
8196 // Long Division with constant, but not -1.
8197 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8198   match(Set dst (DivL src1 src2));
8199   predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8200   ins_cost(2*DEFAULT_COST);
8201 
8202   format %{ "DIVD    $dst, $src1, $src2 \t// /not-1, long" %}
8203   size(4);
8204   ins_encode %{
8205     // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8206     __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8207   %}
8208   ins_pipe(pipe_class_default);
8209 %}
8210 
8211 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsRegSrc crx, iRegLsrc src1) %{
8212   effect(USE_DEF dst, USE src1, USE crx);
8213   predicate(false);
8214 
8215   ins_variable_size_depending_on_alignment(true);
8216 
8217   format %{ "CMOVE   $dst, neg($src1), $crx" %}
8218   // Worst case is branch + move + stop, no stop without scheduler.
8219   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8220   ins_encode %{
8221     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8222     Label done;
8223     __ bne($crx$$CondRegister, done);
8224     __ neg($dst$$Register, $src1$$Register);
8225     // TODO PPC port __ endgroup_if_needed(_size == 12);
8226     __ bind(done);
8227   %}
8228   ins_pipe(pipe_class_default);
8229 %}
8230 
8231 // Long Division with Registers not containing constants.
8232 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8233   match(Set dst (DivL src1 src2));
8234   ins_cost(10*DEFAULT_COST);
8235 
8236   expand %{
8237     immL16 imm %{ (int)-1 %}
8238     flagsReg tmp1;
8239     cmpL_reg_imm16(tmp1, src2, imm);          // check src2 == -1
8240     divL_reg_regnotMinus1(dst, src1, src2);   // dst = src1 / src2
8241     cmovL_bne_negL_reg(dst, tmp1, src1);      // cmove dst = neg(src1) if src2 == -1
8242   %}
8243 %}
8244 
8245 // Integer Remainder with registers.
8246 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8247   match(Set dst (ModI src1 src2));
8248   ins_cost(10*DEFAULT_COST);
8249 
8250   expand %{
8251     immI16 imm %{ (int)-1 %}
8252     flagsReg tmp1;
8253     iRegIdst tmp2;
8254     iRegIdst tmp3;
8255     cmpI_reg_imm16(tmp1, src2, imm);           // check src2 == -1
8256     divI_reg_regnotMinus1(tmp2, src1, src2);   // tmp2 = src1 / src2
8257     cmovI_bne_negI_reg(tmp2, tmp1, src1);      // cmove tmp2 = neg(src1) if src2 == -1
8258     mulI_reg_reg(tmp3, src2, tmp2);            // tmp3 = src2 * tmp2
8259     subI_reg_reg(dst, src1, tmp3);             // dst = src1 - tmp3
8260   %}
8261 %}
8262 
8263 // Long Remainder with registers
8264 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8265   match(Set dst (ModL src1 src2));
8266   ins_cost(10*DEFAULT_COST);
8267 
8268   expand %{
8269     immL16 imm %{ (int)-1 %}
8270     flagsReg tmp1;
8271     iRegLdst tmp2;
8272     iRegLdst tmp3;
8273     cmpL_reg_imm16(tmp1, src2, imm);             // check src2 == -1
8274     divL_reg_regnotMinus1(tmp2, src1, src2);     // tmp2 = src1 / src2
8275     cmovL_bne_negL_reg(tmp2, tmp1, src1);        // cmove tmp2 = neg(src1) if src2 == -1
8276     mulL_reg_reg(tmp3, src2, tmp2);              // tmp3 = src2 * tmp2
8277     subL_reg_reg(dst, src1, tmp3);               // dst = src1 - tmp3
8278   %}
8279 %}
8280 
8281 // Integer Shift Instructions
8282 
8283 // Register Shift Left
8284 
8285 // Clear all but the lowest #mask bits.
8286 // Used to normalize shift amounts in registers.
8287 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8288   // no match-rule, false predicate
8289   effect(DEF dst, USE src, USE mask);
8290   predicate(false);
8291 
8292   format %{ "MASK    $dst, $src, $mask \t// clear $mask upper bits" %}
8293   size(4);
8294   ins_encode %{
8295     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8296     __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8297   %}
8298   ins_pipe(pipe_class_default);
8299 %}
8300 
8301 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8302   // no match-rule, false predicate
8303   effect(DEF dst, USE src1, USE src2);
8304   predicate(false);
8305 
8306   format %{ "SLW     $dst, $src1, $src2" %}
8307   size(4);
8308   ins_encode %{
8309     // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8310     __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8311   %}
8312   ins_pipe(pipe_class_default);
8313 %}
8314 
8315 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8316   match(Set dst (LShiftI src1 src2));
8317   ins_cost(DEFAULT_COST*2);
8318   expand %{
8319     uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8320     iRegIdst tmpI;
8321     maskI_reg_imm(tmpI, src2, mask);
8322     lShiftI_reg_reg(dst, src1, tmpI);
8323   %}
8324 %}
8325 
8326 // Register Shift Left Immediate
8327 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8328   match(Set dst (LShiftI src1 src2));
8329 
8330   format %{ "SLWI    $dst, $src1, ($src2 & 0x1f)" %}
8331   size(4);
8332   ins_encode %{
8333     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8334     __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8335   %}
8336   ins_pipe(pipe_class_default);
8337 %}
8338 
8339 // AndI with negpow2-constant + LShiftI
8340 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8341   match(Set dst (LShiftI (AndI src1 src2) src3));
8342   predicate(UseRotateAndMaskInstructionsPPC64);
8343 
8344   format %{ "RLWINM  $dst, lShiftI(AndI($src1, $src2), $src3)" %}
8345   size(4);
8346   ins_encode %{
8347     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8348     long src2      = $src2$$constant;
8349     long src3      = $src3$$constant;
8350     long maskbits  = src3 + log2_long((jlong) (julong) (juint) -src2);
8351     if (maskbits >= 32) {
8352       __ li($dst$$Register, 0); // addi
8353     } else {
8354       __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
8355     }
8356   %}
8357   ins_pipe(pipe_class_default);
8358 %}
8359 
8360 // RShiftI + AndI with negpow2-constant + LShiftI
8361 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8362   match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
8363   predicate(UseRotateAndMaskInstructionsPPC64);
8364 
8365   format %{ "RLWINM  $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
8366   size(4);
8367   ins_encode %{
8368     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8369     long src2      = $src2$$constant;
8370     long src3      = $src3$$constant;
8371     long maskbits  = src3 + log2_long((jlong) (julong) (juint) -src2);
8372     if (maskbits >= 32) {
8373       __ li($dst$$Register, 0); // addi
8374     } else {
8375       __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
8376     }
8377   %}
8378   ins_pipe(pipe_class_default);
8379 %}
8380 
8381 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8382   // no match-rule, false predicate
8383   effect(DEF dst, USE src1, USE src2);
8384   predicate(false);
8385 
8386   format %{ "SLD     $dst, $src1, $src2" %}
8387   size(4);
8388   ins_encode %{
8389     // TODO: PPC port $archOpcode(ppc64Opcode_sld);
8390     __ sld($dst$$Register, $src1$$Register, $src2$$Register);
8391   %}
8392   ins_pipe(pipe_class_default);
8393 %}
8394 
8395 // Register Shift Left
8396 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8397   match(Set dst (LShiftL src1 src2));
8398   ins_cost(DEFAULT_COST*2);
8399   expand %{
8400     uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8401     iRegIdst tmpI;
8402     maskI_reg_imm(tmpI, src2, mask);
8403     lShiftL_regL_regI(dst, src1, tmpI);
8404   %}
8405 %}
8406 
8407 // Register Shift Left Immediate
8408 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8409   match(Set dst (LShiftL src1 src2));
8410   format %{ "SLDI    $dst, $src1, ($src2 & 0x3f)" %}
8411   size(4);
8412   ins_encode %{
8413     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8414     __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8415   %}
8416   ins_pipe(pipe_class_default);
8417 %}
8418 
8419 // If we shift more than 32 bits, we need not convert I2L.
8420 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
8421   match(Set dst (LShiftL (ConvI2L src1) src2));
8422   ins_cost(DEFAULT_COST);
8423 
8424   size(4);
8425   format %{ "SLDI    $dst, i2l($src1), $src2" %}
8426   ins_encode %{
8427     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8428     __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8429   %}
8430   ins_pipe(pipe_class_default);
8431 %}
8432 
8433 // Shift a postivie int to the left.
8434 // Clrlsldi clears the upper 32 bits and shifts.
8435 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
8436   match(Set dst (LShiftL (ConvI2L src1) src2));
8437   predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
8438 
8439   format %{ "SLDI    $dst, i2l(positive_int($src1)), $src2" %}
8440   size(4);
8441   ins_encode %{
8442     // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
8443     __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
8444   %}
8445   ins_pipe(pipe_class_default);
8446 %}
8447 
8448 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8449   // no match-rule, false predicate
8450   effect(DEF dst, USE src1, USE src2);
8451   predicate(false);
8452 
8453   format %{ "SRAW    $dst, $src1, $src2" %}
8454   size(4);
8455   ins_encode %{
8456     // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
8457     __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
8458   %}
8459   ins_pipe(pipe_class_default);
8460 %}
8461 
8462 // Register Arithmetic Shift Right
8463 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8464   match(Set dst (RShiftI src1 src2));
8465   ins_cost(DEFAULT_COST*2);
8466   expand %{
8467     uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8468     iRegIdst tmpI;
8469     maskI_reg_imm(tmpI, src2, mask);
8470     arShiftI_reg_reg(dst, src1, tmpI);
8471   %}
8472 %}
8473 
8474 // Register Arithmetic Shift Right Immediate
8475 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8476   match(Set dst (RShiftI src1 src2));
8477 
8478   format %{ "SRAWI   $dst, $src1, ($src2 & 0x1f)" %}
8479   size(4);
8480   ins_encode %{
8481     // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8482     __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8483   %}
8484   ins_pipe(pipe_class_default);
8485 %}
8486 
8487 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8488   // no match-rule, false predicate
8489   effect(DEF dst, USE src1, USE src2);
8490   predicate(false);
8491 
8492   format %{ "SRAD    $dst, $src1, $src2" %}
8493   size(4);
8494   ins_encode %{
8495     // TODO: PPC port $archOpcode(ppc64Opcode_srad);
8496     __ srad($dst$$Register, $src1$$Register, $src2$$Register);
8497   %}
8498   ins_pipe(pipe_class_default);
8499 %}
8500 
8501 // Register Shift Right Arithmetic Long
8502 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8503   match(Set dst (RShiftL src1 src2));
8504   ins_cost(DEFAULT_COST*2);
8505 
8506   expand %{
8507     uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8508     iRegIdst tmpI;
8509     maskI_reg_imm(tmpI, src2, mask);
8510     arShiftL_regL_regI(dst, src1, tmpI);
8511   %}
8512 %}
8513 
8514 // Register Shift Right Immediate
8515 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8516   match(Set dst (RShiftL src1 src2));
8517 
8518   format %{ "SRADI   $dst, $src1, ($src2 & 0x3f)" %}
8519   size(4);
8520   ins_encode %{
8521     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8522     __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8523   %}
8524   ins_pipe(pipe_class_default);
8525 %}
8526 
8527 // RShiftL + ConvL2I
8528 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8529   match(Set dst (ConvL2I (RShiftL src1 src2)));
8530 
8531   format %{ "SRADI   $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8532   size(4);
8533   ins_encode %{
8534     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8535     __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8536   %}
8537   ins_pipe(pipe_class_default);
8538 %}
8539 
8540 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8541   // no match-rule, false predicate
8542   effect(DEF dst, USE src1, USE src2);
8543   predicate(false);
8544 
8545   format %{ "SRW     $dst, $src1, $src2" %}
8546   size(4);
8547   ins_encode %{
8548     // TODO: PPC port $archOpcode(ppc64Opcode_srw);
8549     __ srw($dst$$Register, $src1$$Register, $src2$$Register);
8550   %}
8551   ins_pipe(pipe_class_default);
8552 %}
8553 
8554 // Register Shift Right
8555 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8556   match(Set dst (URShiftI src1 src2));
8557   ins_cost(DEFAULT_COST*2);
8558 
8559   expand %{
8560     uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8561     iRegIdst tmpI;
8562     maskI_reg_imm(tmpI, src2, mask);
8563     urShiftI_reg_reg(dst, src1, tmpI);
8564   %}
8565 %}
8566 
8567 // Register Shift Right Immediate
8568 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8569   match(Set dst (URShiftI src1 src2));
8570 
8571   format %{ "SRWI    $dst, $src1, ($src2 & 0x1f)" %}
8572   size(4);
8573   ins_encode %{
8574     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8575     __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8576   %}
8577   ins_pipe(pipe_class_default);
8578 %}
8579 
8580 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8581   // no match-rule, false predicate
8582   effect(DEF dst, USE src1, USE src2);
8583   predicate(false);
8584 
8585   format %{ "SRD     $dst, $src1, $src2" %}
8586   size(4);
8587   ins_encode %{
8588     // TODO: PPC port $archOpcode(ppc64Opcode_srd);
8589     __ srd($dst$$Register, $src1$$Register, $src2$$Register);
8590   %}
8591   ins_pipe(pipe_class_default);
8592 %}
8593 
8594 // Register Shift Right
8595 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8596   match(Set dst (URShiftL src1 src2));
8597   ins_cost(DEFAULT_COST*2);
8598 
8599   expand %{
8600     uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8601     iRegIdst tmpI;
8602     maskI_reg_imm(tmpI, src2, mask);
8603     urShiftL_regL_regI(dst, src1, tmpI);
8604   %}
8605 %}
8606 
8607 // Register Shift Right Immediate
8608 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8609   match(Set dst (URShiftL src1 src2));
8610 
8611   format %{ "SRDI    $dst, $src1, ($src2 & 0x3f)" %}
8612   size(4);
8613   ins_encode %{
8614     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8615     __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8616   %}
8617   ins_pipe(pipe_class_default);
8618 %}
8619 
8620 // URShiftL + ConvL2I.
8621 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8622   match(Set dst (ConvL2I (URShiftL src1 src2)));
8623 
8624   format %{ "SRDI    $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8625   size(4);
8626   ins_encode %{
8627     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8628     __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8629   %}
8630   ins_pipe(pipe_class_default);
8631 %}
8632 
8633 // Register Shift Right Immediate with a CastP2X
8634 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
8635   match(Set dst (URShiftL (CastP2X src1) src2));
8636 
8637   format %{ "SRDI    $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8638   size(4);
8639   ins_encode %{
8640     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8641     __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8642   %}
8643   ins_pipe(pipe_class_default);
8644 %}
8645 
8646 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
8647   match(Set dst (ConvL2I (ConvI2L src)));
8648 
8649   format %{ "EXTSW   $dst, $src \t// int->int" %}
8650   size(4);
8651   ins_encode %{
8652     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
8653     __ extsw($dst$$Register, $src$$Register);
8654   %}
8655   ins_pipe(pipe_class_default);
8656 %}
8657 
8658 //----------Rotate Instructions------------------------------------------------
8659 
8660 // Rotate Left by 8-bit immediate
8661 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
8662   match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
8663   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8664 
8665   format %{ "ROTLWI  $dst, $src, $lshift" %}
8666   size(4);
8667   ins_encode %{
8668     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8669     __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
8670   %}
8671   ins_pipe(pipe_class_default);
8672 %}
8673 
8674 // Rotate Right by 8-bit immediate
8675 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
8676   match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
8677   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8678 
8679   format %{ "ROTRWI  $dst, $rshift" %}
8680   size(4);
8681   ins_encode %{
8682     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8683     __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
8684   %}
8685   ins_pipe(pipe_class_default);
8686 %}
8687 
8688 //----------Floating Point Arithmetic Instructions-----------------------------
8689 
8690 // Add float single precision
8691 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8692   match(Set dst (AddF src1 src2));
8693 
8694   format %{ "FADDS   $dst, $src1, $src2" %}
8695   size(4);
8696   ins_encode %{
8697     // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
8698     __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8699   %}
8700   ins_pipe(pipe_class_default);
8701 %}
8702 
8703 // Add float double precision
8704 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8705   match(Set dst (AddD src1 src2));
8706 
8707   format %{ "FADD    $dst, $src1, $src2" %}
8708   size(4);
8709   ins_encode %{
8710     // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
8711     __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8712   %}
8713   ins_pipe(pipe_class_default);
8714 %}
8715 
8716 // Sub float single precision
8717 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8718   match(Set dst (SubF src1 src2));
8719 
8720   format %{ "FSUBS   $dst, $src1, $src2" %}
8721   size(4);
8722   ins_encode %{
8723     // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
8724     __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8725   %}
8726   ins_pipe(pipe_class_default);
8727 %}
8728 
8729 // Sub float double precision
8730 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8731   match(Set dst (SubD src1 src2));
8732   format %{ "FSUB    $dst, $src1, $src2" %}
8733   size(4);
8734   ins_encode %{
8735     // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
8736     __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8737   %}
8738   ins_pipe(pipe_class_default);
8739 %}
8740 
8741 // Mul float single precision
8742 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8743   match(Set dst (MulF src1 src2));
8744   format %{ "FMULS   $dst, $src1, $src2" %}
8745   size(4);
8746   ins_encode %{
8747     // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
8748     __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8749   %}
8750   ins_pipe(pipe_class_default);
8751 %}
8752 
8753 // Mul float double precision
8754 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8755   match(Set dst (MulD src1 src2));
8756   format %{ "FMUL    $dst, $src1, $src2" %}
8757   size(4);
8758   ins_encode %{
8759     // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
8760     __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8761   %}
8762   ins_pipe(pipe_class_default);
8763 %}
8764 
8765 // Div float single precision
8766 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
8767   match(Set dst (DivF src1 src2));
8768   format %{ "FDIVS   $dst, $src1, $src2" %}
8769   size(4);
8770   ins_encode %{
8771     // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
8772     __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8773   %}
8774   ins_pipe(pipe_class_default);
8775 %}
8776 
8777 // Div float double precision
8778 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8779   match(Set dst (DivD src1 src2));
8780   format %{ "FDIV    $dst, $src1, $src2" %}
8781   size(4);
8782   ins_encode %{
8783     // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
8784     __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8785   %}
8786   ins_pipe(pipe_class_default);
8787 %}
8788 
8789 // Absolute float single precision
8790 instruct absF_reg(regF dst, regF src) %{
8791   match(Set dst (AbsF src));
8792   format %{ "FABS    $dst, $src \t// float" %}
8793   size(4);
8794   ins_encode %{
8795     // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8796     __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8797   %}
8798   ins_pipe(pipe_class_default);
8799 %}
8800 
8801 // Absolute float double precision
8802 instruct absD_reg(regD dst, regD src) %{
8803   match(Set dst (AbsD src));
8804   format %{ "FABS    $dst, $src \t// double" %}
8805   size(4);
8806   ins_encode %{
8807     // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8808     __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8809   %}
8810   ins_pipe(pipe_class_default);
8811 %}
8812 
8813 instruct negF_reg(regF dst, regF src) %{
8814   match(Set dst (NegF src));
8815   format %{ "FNEG    $dst, $src \t// float" %}
8816   size(4);
8817   ins_encode %{
8818     // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8819     __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8820   %}
8821   ins_pipe(pipe_class_default);
8822 %}
8823 
8824 instruct negD_reg(regD dst, regD src) %{
8825   match(Set dst (NegD src));
8826   format %{ "FNEG    $dst, $src \t// double" %}
8827   size(4);
8828   ins_encode %{
8829     // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8830     __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8831   %}
8832   ins_pipe(pipe_class_default);
8833 %}
8834 
8835 // AbsF + NegF.
8836 instruct negF_absF_reg(regF dst, regF src) %{
8837   match(Set dst (NegF (AbsF src)));
8838   format %{ "FNABS   $dst, $src \t// float" %}
8839   size(4);
8840   ins_encode %{
8841     // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8842     __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8843   %}
8844   ins_pipe(pipe_class_default);
8845 %}
8846 
8847 // AbsD + NegD.
8848 instruct negD_absD_reg(regD dst, regD src) %{
8849   match(Set dst (NegD (AbsD src)));
8850   format %{ "FNABS   $dst, $src \t// double" %}
8851   size(4);
8852   ins_encode %{
8853     // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8854     __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8855   %}
8856   ins_pipe(pipe_class_default);
8857 %}
8858 
8859 // VM_Version::has_fsqrt() decides if this node will be used.
8860 // Sqrt float double precision
8861 instruct sqrtD_reg(regD dst, regD src) %{
8862   match(Set dst (SqrtD src));
8863   format %{ "FSQRT   $dst, $src" %}
8864   size(4);
8865   ins_encode %{
8866     // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
8867     __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
8868   %}
8869   ins_pipe(pipe_class_default);
8870 %}
8871 
8872 // Single-precision sqrt.
8873 instruct sqrtF_reg(regF dst, regF src) %{
8874   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8875   predicate(VM_Version::has_fsqrts());
8876   ins_cost(DEFAULT_COST);
8877 
8878   format %{ "FSQRTS  $dst, $src" %}
8879   size(4);
8880   ins_encode %{
8881     // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
8882     __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
8883   %}
8884   ins_pipe(pipe_class_default);
8885 %}
8886 
8887 instruct roundDouble_nop(regD dst) %{
8888   match(Set dst (RoundDouble dst));
8889   ins_cost(0);
8890 
8891   format %{ " -- \t// RoundDouble not needed - empty" %}
8892   size(0);
8893   // PPC results are already "rounded" (i.e., normal-format IEEE).
8894   ins_encode( /*empty*/ );
8895   ins_pipe(pipe_class_default);
8896 %}
8897 
8898 instruct roundFloat_nop(regF dst) %{
8899   match(Set dst (RoundFloat dst));
8900   ins_cost(0);
8901 
8902   format %{ " -- \t// RoundFloat not needed - empty" %}
8903   size(0);
8904   // PPC results are already "rounded" (i.e., normal-format IEEE).
8905   ins_encode( /*empty*/ );
8906   ins_pipe(pipe_class_default);
8907 %}
8908 
8909 //----------Logical Instructions-----------------------------------------------
8910 
8911 // And Instructions
8912 
8913 // Register And
8914 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8915   match(Set dst (AndI src1 src2));
8916   format %{ "AND     $dst, $src1, $src2" %}
8917   size(4);
8918   ins_encode %{
8919     // TODO: PPC port $archOpcode(ppc64Opcode_and);
8920     __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8921   %}
8922   ins_pipe(pipe_class_default);
8923 %}
8924 
8925 // Immediate And
8926 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
8927   match(Set dst (AndI src1 src2));
8928   effect(KILL cr0);
8929 
8930   format %{ "ANDI    $dst, $src1, $src2" %}
8931   size(4);
8932   ins_encode %{
8933     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8934     // FIXME: avoid andi_ ?
8935     __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8936   %}
8937   ins_pipe(pipe_class_default);
8938 %}
8939 
8940 // Immediate And where the immediate is a negative power of 2.
8941 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
8942   match(Set dst (AndI src1 src2));
8943   format %{ "ANDWI   $dst, $src1, $src2" %}
8944   size(4);
8945   ins_encode %{
8946     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8947     __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
8948   %}
8949   ins_pipe(pipe_class_default);
8950 %}
8951 
8952 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
8953   match(Set dst (AndI src1 src2));
8954   format %{ "ANDWI   $dst, $src1, $src2" %}
8955   size(4);
8956   ins_encode %{
8957     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8958     __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8959   %}
8960   ins_pipe(pipe_class_default);
8961 %}
8962 
8963 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
8964   match(Set dst (AndI src1 src2));
8965   predicate(UseRotateAndMaskInstructionsPPC64);
8966   format %{ "ANDWI   $dst, $src1, $src2" %}
8967   size(4);
8968   ins_encode %{
8969     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8970     __ rlwinm($dst$$Register, $src1$$Register, 0,
8971               (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
8972   %}
8973   ins_pipe(pipe_class_default);
8974 %}
8975 
8976 // Register And Long
8977 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8978   match(Set dst (AndL src1 src2));
8979   ins_cost(DEFAULT_COST);
8980 
8981   format %{ "AND     $dst, $src1, $src2 \t// long" %}
8982   size(4);
8983   ins_encode %{
8984     // TODO: PPC port $archOpcode(ppc64Opcode_and);
8985     __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8986   %}
8987   ins_pipe(pipe_class_default);
8988 %}
8989 
8990 // Immediate And long
8991 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
8992   match(Set dst (AndL src1 src2));
8993   effect(KILL cr0);
8994 
8995   format %{ "ANDI    $dst, $src1, $src2 \t// long" %}
8996   size(4);
8997   ins_encode %{
8998     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8999     // FIXME: avoid andi_ ?
9000     __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
9001   %}
9002   ins_pipe(pipe_class_default);
9003 %}
9004 
9005 // Immediate And Long where the immediate is a negative power of 2.
9006 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
9007   match(Set dst (AndL src1 src2));
9008   format %{ "ANDDI   $dst, $src1, $src2" %}
9009   size(4);
9010   ins_encode %{
9011     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
9012     __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
9013   %}
9014   ins_pipe(pipe_class_default);
9015 %}
9016 
9017 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
9018   match(Set dst (AndL src1 src2));
9019   format %{ "ANDDI   $dst, $src1, $src2" %}
9020   size(4);
9021   ins_encode %{
9022     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9023     __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9024   %}
9025   ins_pipe(pipe_class_default);
9026 %}
9027 
9028 // AndL + ConvL2I.
9029 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
9030   match(Set dst (ConvL2I (AndL src1 src2)));
9031   ins_cost(DEFAULT_COST);
9032 
9033   format %{ "ANDDI   $dst, $src1, $src2 \t// long + l2i" %}
9034   size(4);
9035   ins_encode %{
9036     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9037     __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9038   %}
9039   ins_pipe(pipe_class_default);
9040 %}
9041 
9042 // Or Instructions
9043 
9044 // Register Or
9045 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9046   match(Set dst (OrI src1 src2));
9047   format %{ "OR      $dst, $src1, $src2" %}
9048   size(4);
9049   ins_encode %{
9050     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9051     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9052   %}
9053   ins_pipe(pipe_class_default);
9054 %}
9055 
9056 // Expand does not work with above instruct. (??)
9057 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9058   // no match-rule
9059   effect(DEF dst, USE src1, USE src2);
9060   format %{ "OR      $dst, $src1, $src2" %}
9061   size(4);
9062   ins_encode %{
9063     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9064     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9065   %}
9066   ins_pipe(pipe_class_default);
9067 %}
9068 
9069 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9070   match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
9071   ins_cost(DEFAULT_COST*3);
9072 
9073   expand %{
9074     // FIXME: we should do this in the ideal world.
9075     iRegIdst tmp1;
9076     iRegIdst tmp2;
9077     orI_reg_reg(tmp1, src1, src2);
9078     orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
9079     orI_reg_reg(dst, tmp1, tmp2);
9080   %}
9081 %}
9082 
9083 // Immediate Or
9084 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9085   match(Set dst (OrI src1 src2));
9086   format %{ "ORI     $dst, $src1, $src2" %}
9087   size(4);
9088   ins_encode %{
9089     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9090     __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
9091   %}
9092   ins_pipe(pipe_class_default);
9093 %}
9094 
9095 // Register Or Long
9096 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9097   match(Set dst (OrL src1 src2));
9098   ins_cost(DEFAULT_COST);
9099 
9100   size(4);
9101   format %{ "OR      $dst, $src1, $src2 \t// long" %}
9102   ins_encode %{
9103     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9104     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9105   %}
9106   ins_pipe(pipe_class_default);
9107 %}
9108 
9109 // OrL + ConvL2I.
9110 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9111   match(Set dst (ConvL2I (OrL src1 src2)));
9112   ins_cost(DEFAULT_COST);
9113 
9114   format %{ "OR      $dst, $src1, $src2 \t// long + l2i" %}
9115   size(4);
9116   ins_encode %{
9117     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9118     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9119   %}
9120   ins_pipe(pipe_class_default);
9121 %}
9122 
9123 // Immediate Or long
9124 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9125   match(Set dst (OrL src1 con));
9126   ins_cost(DEFAULT_COST);
9127 
9128   format %{ "ORI     $dst, $src1, $con \t// long" %}
9129   size(4);
9130   ins_encode %{
9131     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9132     __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9133   %}
9134   ins_pipe(pipe_class_default);
9135 %}
9136 
9137 // Xor Instructions
9138 
9139 // Register Xor
9140 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9141   match(Set dst (XorI src1 src2));
9142   format %{ "XOR     $dst, $src1, $src2" %}
9143   size(4);
9144   ins_encode %{
9145     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9146     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9147   %}
9148   ins_pipe(pipe_class_default);
9149 %}
9150 
9151 // Expand does not work with above instruct. (??)
9152 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9153   // no match-rule
9154   effect(DEF dst, USE src1, USE src2);
9155   format %{ "XOR     $dst, $src1, $src2" %}
9156   size(4);
9157   ins_encode %{
9158     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9159     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9160   %}
9161   ins_pipe(pipe_class_default);
9162 %}
9163 
9164 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9165   match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9166   ins_cost(DEFAULT_COST*3);
9167 
9168   expand %{
9169     // FIXME: we should do this in the ideal world.
9170     iRegIdst tmp1;
9171     iRegIdst tmp2;
9172     xorI_reg_reg(tmp1, src1, src2);
9173     xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9174     xorI_reg_reg(dst, tmp1, tmp2);
9175   %}
9176 %}
9177 
9178 // Immediate Xor
9179 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9180   match(Set dst (XorI src1 src2));
9181   format %{ "XORI    $dst, $src1, $src2" %}
9182   size(4);
9183   ins_encode %{
9184     // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9185     __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9186   %}
9187   ins_pipe(pipe_class_default);
9188 %}
9189 
9190 // Register Xor Long
9191 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9192   match(Set dst (XorL src1 src2));
9193   ins_cost(DEFAULT_COST);
9194 
9195   format %{ "XOR     $dst, $src1, $src2 \t// long" %}
9196   size(4);
9197   ins_encode %{
9198     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9199     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9200   %}
9201   ins_pipe(pipe_class_default);
9202 %}
9203 
9204 // XorL + ConvL2I.
9205 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9206   match(Set dst (ConvL2I (XorL src1 src2)));
9207   ins_cost(DEFAULT_COST);
9208 
9209   format %{ "XOR     $dst, $src1, $src2 \t// long + l2i" %}
9210   size(4);
9211   ins_encode %{
9212     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9213     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9214   %}
9215   ins_pipe(pipe_class_default);
9216 %}
9217 
9218 // Immediate Xor Long
9219 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
9220   match(Set dst (XorL src1 src2));
9221   ins_cost(DEFAULT_COST);
9222 
9223   format %{ "XORI    $dst, $src1, $src2 \t// long" %}
9224   size(4);
9225   ins_encode %{
9226     // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9227     __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9228   %}
9229   ins_pipe(pipe_class_default);
9230 %}
9231 
9232 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9233   match(Set dst (XorI src1 src2));
9234   ins_cost(DEFAULT_COST);
9235 
9236   format %{ "NOT     $dst, $src1 ($src2)" %}
9237   size(4);
9238   ins_encode %{
9239     // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9240     __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9241   %}
9242   ins_pipe(pipe_class_default);
9243 %}
9244 
9245 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9246   match(Set dst (XorL src1 src2));
9247   ins_cost(DEFAULT_COST);
9248 
9249   format %{ "NOT     $dst, $src1 ($src2) \t// long" %}
9250   size(4);
9251   ins_encode %{
9252     // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9253     __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9254   %}
9255   ins_pipe(pipe_class_default);
9256 %}
9257 
9258 // And-complement
9259 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
9260   match(Set dst (AndI (XorI src1 src2) src3));
9261   ins_cost(DEFAULT_COST);
9262 
9263   format %{ "ANDW    $dst, xori($src1, $src2), $src3" %}
9264   size(4);
9265   ins_encode( enc_andc(dst, src3, src1) );
9266   ins_pipe(pipe_class_default);
9267 %}
9268 
9269 // And-complement
9270 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9271   // no match-rule, false predicate
9272   effect(DEF dst, USE src1, USE src2);
9273   predicate(false);
9274 
9275   format %{ "ANDC    $dst, $src1, $src2" %}
9276   size(4);
9277   ins_encode %{
9278     // TODO: PPC port $archOpcode(ppc64Opcode_andc);
9279     __ andc($dst$$Register, $src1$$Register, $src2$$Register);
9280   %}
9281   ins_pipe(pipe_class_default);
9282 %}
9283 
9284 //----------Moves between int/long and float/double----------------------------
9285 //
9286 // The following rules move values from int/long registers/stack-locations
9287 // to float/double registers/stack-locations and vice versa, without doing any
9288 // conversions. These rules are used to implement the bit-conversion methods
9289 // of java.lang.Float etc., e.g.
9290 //   int   floatToIntBits(float value)
9291 //   float intBitsToFloat(int bits)
9292 //
9293 // Notes on the implementation on ppc64:
9294 // We only provide rules which move between a register and a stack-location,
9295 // because we always have to go through memory when moving between a float
9296 // register and an integer register.
9297 
9298 //---------- Chain stack slots between similar types --------
9299 
9300 // These are needed so that the rules below can match.
9301 
9302 // Load integer from stack slot
9303 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
9304   match(Set dst src);
9305   ins_cost(MEMORY_REF_COST);
9306 
9307   format %{ "LWZ     $dst, $src" %}
9308   size(4);
9309   ins_encode( enc_lwz(dst, src) );
9310   ins_pipe(pipe_class_memory);
9311 %}
9312 
9313 // Store integer to stack slot
9314 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
9315   match(Set dst src);
9316   ins_cost(MEMORY_REF_COST);
9317 
9318   format %{ "STW     $src, $dst \t// stk" %}
9319   size(4);
9320   ins_encode( enc_stw(src, dst) ); // rs=rt
9321   ins_pipe(pipe_class_memory);
9322 %}
9323 
9324 // Load long from stack slot
9325 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
9326   match(Set dst src);
9327   ins_cost(MEMORY_REF_COST);
9328 
9329   format %{ "LD      $dst, $src \t// long" %}
9330   size(4);
9331   ins_encode( enc_ld(dst, src) );
9332   ins_pipe(pipe_class_memory);
9333 %}
9334 
9335 // Store long to stack slot
9336 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
9337   match(Set dst src);
9338   ins_cost(MEMORY_REF_COST);
9339 
9340   format %{ "STD     $src, $dst \t// long" %}
9341   size(4);
9342   ins_encode( enc_std(src, dst) ); // rs=rt
9343   ins_pipe(pipe_class_memory);
9344 %}
9345 
9346 //----------Moves between int and float
9347 
9348 // Move float value from float stack-location to integer register.
9349 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
9350   match(Set dst (MoveF2I src));
9351   ins_cost(MEMORY_REF_COST);
9352 
9353   format %{ "LWZ     $dst, $src \t// MoveF2I" %}
9354   size(4);
9355   ins_encode( enc_lwz(dst, src) );
9356   ins_pipe(pipe_class_memory);
9357 %}
9358 
9359 // Move float value from float register to integer stack-location.
9360 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
9361   match(Set dst (MoveF2I src));
9362   ins_cost(MEMORY_REF_COST);
9363 
9364   format %{ "STFS    $src, $dst \t// MoveF2I" %}
9365   size(4);
9366   ins_encode( enc_stfs(src, dst) );
9367   ins_pipe(pipe_class_memory);
9368 %}
9369 
9370 // Move integer value from integer stack-location to float register.
9371 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
9372   match(Set dst (MoveI2F src));
9373   ins_cost(MEMORY_REF_COST);
9374 
9375   format %{ "LFS     $dst, $src \t// MoveI2F" %}
9376   size(4);
9377   ins_encode %{
9378     // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
9379     int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
9380     __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
9381   %}
9382   ins_pipe(pipe_class_memory);
9383 %}
9384 
9385 // Move integer value from integer register to float stack-location.
9386 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
9387   match(Set dst (MoveI2F src));
9388   ins_cost(MEMORY_REF_COST);
9389 
9390   format %{ "STW     $src, $dst \t// MoveI2F" %}
9391   size(4);
9392   ins_encode( enc_stw(src, dst) );
9393   ins_pipe(pipe_class_memory);
9394 %}
9395 
9396 //----------Moves between long and float
9397 
9398 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
9399   // no match-rule, false predicate
9400   effect(DEF dst, USE src);
9401   predicate(false);
9402 
9403   format %{ "storeD  $src, $dst \t// STACK" %}
9404   size(4);
9405   ins_encode( enc_stfd(src, dst) );
9406   ins_pipe(pipe_class_default);
9407 %}
9408 
9409 //----------Moves between long and double
9410 
9411 // Move double value from double stack-location to long register.
9412 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
9413   match(Set dst (MoveD2L src));
9414   ins_cost(MEMORY_REF_COST);
9415   size(4);
9416   format %{ "LD      $dst, $src \t// MoveD2L" %}
9417   ins_encode( enc_ld(dst, src) );
9418   ins_pipe(pipe_class_memory);
9419 %}
9420 
9421 // Move double value from double register to long stack-location.
9422 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
9423   match(Set dst (MoveD2L src));
9424   effect(DEF dst, USE src);
9425   ins_cost(MEMORY_REF_COST);
9426 
9427   format %{ "STFD    $src, $dst \t// MoveD2L" %}
9428   size(4);
9429   ins_encode( enc_stfd(src, dst) );
9430   ins_pipe(pipe_class_memory);
9431 %}
9432 
9433 // Move long value from long stack-location to double register.
9434 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
9435   match(Set dst (MoveL2D src));
9436   ins_cost(MEMORY_REF_COST);
9437 
9438   format %{ "LFD     $dst, $src \t// MoveL2D" %}
9439   size(4);
9440   ins_encode( enc_lfd(dst, src) );
9441   ins_pipe(pipe_class_memory);
9442 %}
9443 
9444 // Move long value from long register to double stack-location.
9445 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
9446   match(Set dst (MoveL2D src));
9447   ins_cost(MEMORY_REF_COST);
9448 
9449   format %{ "STD     $src, $dst \t// MoveL2D" %}
9450   size(4);
9451   ins_encode( enc_std(src, dst) );
9452   ins_pipe(pipe_class_memory);
9453 %}
9454 
9455 //----------Register Move Instructions-----------------------------------------
9456 
9457 // Replicate for Superword
9458 
9459 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
9460   predicate(false);
9461   effect(DEF dst, USE src);
9462 
9463   format %{ "MR      $dst, $src \t// replicate " %}
9464   // variable size, 0 or 4.
9465   ins_encode %{
9466     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9467     __ mr_if_needed($dst$$Register, $src$$Register);
9468   %}
9469   ins_pipe(pipe_class_default);
9470 %}
9471 
9472 //----------Cast instructions (Java-level type cast)---------------------------
9473 
9474 // Cast Long to Pointer for unsafe natives.
9475 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
9476   match(Set dst (CastX2P src));
9477 
9478   format %{ "MR      $dst, $src \t// Long->Ptr" %}
9479   // variable size, 0 or 4.
9480   ins_encode %{
9481     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9482     __ mr_if_needed($dst$$Register, $src$$Register);
9483   %}
9484  ins_pipe(pipe_class_default);
9485 %}
9486 
9487 // Cast Pointer to Long for unsafe natives.
9488 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
9489   match(Set dst (CastP2X src));
9490 
9491   format %{ "MR      $dst, $src \t// Ptr->Long" %}
9492   // variable size, 0 or 4.
9493   ins_encode %{
9494     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9495     __ mr_if_needed($dst$$Register, $src$$Register);
9496   %}
9497   ins_pipe(pipe_class_default);
9498 %}
9499 
9500 instruct castPP(iRegPdst dst) %{
9501   match(Set dst (CastPP dst));
9502   format %{ " -- \t// castPP of $dst" %}
9503   size(0);
9504   ins_encode( /*empty*/ );
9505   ins_pipe(pipe_class_default);
9506 %}
9507 
9508 instruct castII(iRegIdst dst) %{
9509   match(Set dst (CastII dst));
9510   format %{ " -- \t// castII of $dst" %}
9511   size(0);
9512   ins_encode( /*empty*/ );
9513   ins_pipe(pipe_class_default);
9514 %}
9515 
9516 instruct checkCastPP(iRegPdst dst) %{
9517   match(Set dst (CheckCastPP dst));
9518   format %{ " -- \t// checkcastPP of $dst" %}
9519   size(0);
9520   ins_encode( /*empty*/ );
9521   ins_pipe(pipe_class_default);
9522 %}
9523 
9524 //----------Convert instructions-----------------------------------------------
9525 
9526 // Convert to boolean.
9527 
9528 // int_to_bool(src) : { 1   if src != 0
9529 //                    { 0   else
9530 //
9531 // strategy:
9532 // 1) Count leading zeros of 32 bit-value src,
9533 //    this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
9534 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9535 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9536 
9537 // convI2Bool
9538 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
9539   match(Set dst (Conv2B src));
9540   predicate(UseCountLeadingZerosInstructionsPPC64);
9541   ins_cost(DEFAULT_COST);
9542 
9543   expand %{
9544     immI shiftAmount %{ 0x5 %}
9545     uimmI16 mask %{ 0x1 %}
9546     iRegIdst tmp1;
9547     iRegIdst tmp2;
9548     countLeadingZerosI(tmp1, src);
9549     urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9550     xorI_reg_uimm16(dst, tmp2, mask);
9551   %}
9552 %}
9553 
9554 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
9555   match(Set dst (Conv2B src));
9556   effect(TEMP crx);
9557   predicate(!UseCountLeadingZerosInstructionsPPC64);
9558   ins_cost(DEFAULT_COST);
9559 
9560   format %{ "CMPWI   $crx, $src, #0 \t// convI2B"
9561             "LI      $dst, #0\n\t"
9562             "BEQ     $crx, done\n\t"
9563             "LI      $dst, #1\n"
9564             "done:" %}
9565   size(16);
9566   ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
9567   ins_pipe(pipe_class_compare);
9568 %}
9569 
9570 // ConvI2B + XorI
9571 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
9572   match(Set dst (XorI (Conv2B src) mask));
9573   predicate(UseCountLeadingZerosInstructionsPPC64);
9574   ins_cost(DEFAULT_COST);
9575 
9576   expand %{
9577     immI shiftAmount %{ 0x5 %}
9578     iRegIdst tmp1;
9579     countLeadingZerosI(tmp1, src);
9580     urShiftI_reg_imm(dst, tmp1, shiftAmount);
9581   %}
9582 %}
9583 
9584 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
9585   match(Set dst (XorI (Conv2B src) mask));
9586   effect(TEMP crx);
9587   predicate(!UseCountLeadingZerosInstructionsPPC64);
9588   ins_cost(DEFAULT_COST);
9589 
9590   format %{ "CMPWI   $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
9591             "LI      $dst, #1\n\t"
9592             "BEQ     $crx, done\n\t"
9593             "LI      $dst, #0\n"
9594             "done:" %}
9595   size(16);
9596   ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
9597   ins_pipe(pipe_class_compare);
9598 %}
9599 
9600 // AndI 0b0..010..0 + ConvI2B
9601 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
9602   match(Set dst (Conv2B (AndI src mask)));
9603   predicate(UseRotateAndMaskInstructionsPPC64);
9604   ins_cost(DEFAULT_COST);
9605 
9606   format %{ "RLWINM  $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
9607   size(4);
9608   ins_encode %{
9609     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9610     __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
9611   %}
9612   ins_pipe(pipe_class_default);
9613 %}
9614 
9615 // Convert pointer to boolean.
9616 //
9617 // ptr_to_bool(src) : { 1   if src != 0
9618 //                    { 0   else
9619 //
9620 // strategy:
9621 // 1) Count leading zeros of 64 bit-value src,
9622 //    this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
9623 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9624 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9625 
9626 // ConvP2B
9627 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
9628   match(Set dst (Conv2B src));
9629   predicate(UseCountLeadingZerosInstructionsPPC64);
9630   ins_cost(DEFAULT_COST);
9631 
9632   expand %{
9633     immI shiftAmount %{ 0x6 %}
9634     uimmI16 mask %{ 0x1 %}
9635     iRegIdst tmp1;
9636     iRegIdst tmp2;
9637     countLeadingZerosP(tmp1, src);
9638     urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9639     xorI_reg_uimm16(dst, tmp2, mask);
9640   %}
9641 %}
9642 
9643 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
9644   match(Set dst (Conv2B src));
9645   effect(TEMP crx);
9646   predicate(!UseCountLeadingZerosInstructionsPPC64);
9647   ins_cost(DEFAULT_COST);
9648 
9649   format %{ "CMPDI   $crx, $src, #0 \t// convP2B"
9650             "LI      $dst, #0\n\t"
9651             "BEQ     $crx, done\n\t"
9652             "LI      $dst, #1\n"
9653             "done:" %}
9654   size(16);
9655   ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
9656   ins_pipe(pipe_class_compare);
9657 %}
9658 
9659 // ConvP2B + XorI
9660 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
9661   match(Set dst (XorI (Conv2B src) mask));
9662   predicate(UseCountLeadingZerosInstructionsPPC64);
9663   ins_cost(DEFAULT_COST);
9664 
9665   expand %{
9666     immI shiftAmount %{ 0x6 %}
9667     iRegIdst tmp1;
9668     countLeadingZerosP(tmp1, src);
9669     urShiftI_reg_imm(dst, tmp1, shiftAmount);
9670   %}
9671 %}
9672 
9673 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
9674   match(Set dst (XorI (Conv2B src) mask));
9675   effect(TEMP crx);
9676   predicate(!UseCountLeadingZerosInstructionsPPC64);
9677   ins_cost(DEFAULT_COST);
9678 
9679   format %{ "CMPDI   $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
9680             "LI      $dst, #1\n\t"
9681             "BEQ     $crx, done\n\t"
9682             "LI      $dst, #0\n"
9683             "done:" %}
9684   size(16);
9685   ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
9686   ins_pipe(pipe_class_compare);
9687 %}
9688 
9689 // if src1 < src2, return -1 else return 0
9690 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9691   match(Set dst (CmpLTMask src1 src2));
9692   ins_cost(DEFAULT_COST*4);
9693 
9694   expand %{
9695     iRegLdst src1s;
9696     iRegLdst src2s;
9697     iRegLdst diff;
9698     convI2L_reg(src1s, src1); // Ensure proper sign extension.
9699     convI2L_reg(src2s, src2); // Ensure proper sign extension.
9700     subL_reg_reg(diff, src1s, src2s);
9701     // Need to consider >=33 bit result, therefore we need signmaskL.
9702     signmask64I_regL(dst, diff);
9703   %}
9704 %}
9705 
9706 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
9707   match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
9708   format %{ "SRAWI   $dst, $src1, $src2 \t// CmpLTMask" %}
9709   size(4);
9710   ins_encode %{
9711     // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9712     __ srawi($dst$$Register, $src1$$Register, 0x1f);
9713   %}
9714   ins_pipe(pipe_class_default);
9715 %}
9716 
9717 //----------Arithmetic Conversion Instructions---------------------------------
9718 
9719 // Convert to Byte  -- nop
9720 // Convert to Short -- nop
9721 
9722 // Convert to Int
9723 
9724 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
9725   match(Set dst (RShiftI (LShiftI src amount) amount));
9726   format %{ "EXTSB   $dst, $src \t// byte->int" %}
9727   size(4);
9728   ins_encode %{
9729     // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
9730     __ extsb($dst$$Register, $src$$Register);
9731   %}
9732   ins_pipe(pipe_class_default);
9733 %}
9734 
9735 // LShiftI 16 + RShiftI 16 converts short to int.
9736 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
9737   match(Set dst (RShiftI (LShiftI src amount) amount));
9738   format %{ "EXTSH   $dst, $src \t// short->int" %}
9739   size(4);
9740   ins_encode %{
9741     // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
9742     __ extsh($dst$$Register, $src$$Register);
9743   %}
9744   ins_pipe(pipe_class_default);
9745 %}
9746 
9747 // ConvL2I + ConvI2L: Sign extend int in long register.
9748 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
9749   match(Set dst (ConvI2L (ConvL2I src)));
9750 
9751   format %{ "EXTSW   $dst, $src \t// long->long" %}
9752   size(4);
9753   ins_encode %{
9754     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9755     __ extsw($dst$$Register, $src$$Register);
9756   %}
9757   ins_pipe(pipe_class_default);
9758 %}
9759 
9760 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
9761   match(Set dst (ConvL2I src));
9762   format %{ "MR      $dst, $src \t// long->int" %}
9763   // variable size, 0 or 4
9764   ins_encode %{
9765     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9766     __ mr_if_needed($dst$$Register, $src$$Register);
9767   %}
9768   ins_pipe(pipe_class_default);
9769 %}
9770 
9771 instruct convD2IRaw_regD(regD dst, regD src) %{
9772   // no match-rule, false predicate
9773   effect(DEF dst, USE src);
9774   predicate(false);
9775 
9776   format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
9777   size(4);
9778   ins_encode %{
9779     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
9780     __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9781   %}
9782   ins_pipe(pipe_class_default);
9783 %}
9784 
9785 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsRegSrc crx, stackSlotL src) %{
9786   // no match-rule, false predicate
9787   effect(DEF dst, USE crx, USE src);
9788   predicate(false);
9789 
9790   ins_variable_size_depending_on_alignment(true);
9791 
9792   format %{ "cmovI   $crx, $dst, $src" %}
9793   // Worst case is branch + move + stop, no stop without scheduler.
9794   size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9795   ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9796   ins_pipe(pipe_class_default);
9797 %}
9798 
9799 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, stackSlotL mem) %{
9800   // no match-rule, false predicate
9801   effect(DEF dst, USE crx, USE mem);
9802   predicate(false);
9803 
9804   format %{ "CmovI   $dst, $crx, $mem \t// postalloc expanded" %}
9805   postalloc_expand %{
9806     //
9807     // replaces
9808     //
9809     //   region  dst  crx  mem
9810     //    \       |    |   /
9811     //     dst=cmovI_bso_stackSlotL_conLvalue0
9812     //
9813     // with
9814     //
9815     //   region  dst
9816     //    \       /
9817     //     dst=loadConI16(0)
9818     //      |
9819     //      ^  region  dst  crx  mem
9820     //      |   \       |    |    /
9821     //      dst=cmovI_bso_stackSlotL
9822     //
9823 
9824     // Create new nodes.
9825     MachNode *m1 = new loadConI16Node();
9826     MachNode *m2 = new cmovI_bso_stackSlotLNode();
9827 
9828     // inputs for new nodes
9829     m1->add_req(n_region);
9830     m2->add_req(n_region, n_crx, n_mem);
9831 
9832     // precedences for new nodes
9833     m2->add_prec(m1);
9834 
9835     // operands for new nodes
9836     m1->_opnds[0] = op_dst;
9837     m1->_opnds[1] = new immI16Oper(0);
9838 
9839     m2->_opnds[0] = op_dst;
9840     m2->_opnds[1] = op_crx;
9841     m2->_opnds[2] = op_mem;
9842 
9843     // registers for new nodes
9844     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9845     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9846 
9847     // Insert new nodes.
9848     nodes->push(m1);
9849     nodes->push(m2);
9850   %}
9851 %}
9852 
9853 // Double to Int conversion, NaN is mapped to 0.
9854 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
9855   match(Set dst (ConvD2I src));
9856   ins_cost(DEFAULT_COST);
9857 
9858   expand %{
9859     regD tmpD;
9860     stackSlotL tmpS;
9861     flagsReg crx;
9862     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
9863     convD2IRaw_regD(tmpD, src);                         // Convert float to int (speculated).
9864     moveD2L_reg_stack(tmpS, tmpD);                      // Store float to stack (speculated).
9865     cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9866   %}
9867 %}
9868 
9869 instruct convF2IRaw_regF(regF dst, regF src) %{
9870   // no match-rule, false predicate
9871   effect(DEF dst, USE src);
9872   predicate(false);
9873 
9874   format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
9875   size(4);
9876   ins_encode %{
9877     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9878     __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9879   %}
9880   ins_pipe(pipe_class_default);
9881 %}
9882 
9883 // Float to Int conversion, NaN is mapped to 0.
9884 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
9885   match(Set dst (ConvF2I src));
9886   ins_cost(DEFAULT_COST);
9887 
9888   expand %{
9889     regF tmpF;
9890     stackSlotL tmpS;
9891     flagsReg crx;
9892     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
9893     convF2IRaw_regF(tmpF, src);                         // Convert float to int (speculated).
9894     moveF2L_reg_stack(tmpS, tmpF);                      // Store float to stack (speculated).
9895     cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9896   %}
9897 %}
9898 
9899 // Convert to Long
9900 
9901 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
9902   match(Set dst (ConvI2L src));
9903   format %{ "EXTSW   $dst, $src \t// int->long" %}
9904   size(4);
9905   ins_encode %{
9906     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9907     __ extsw($dst$$Register, $src$$Register);
9908   %}
9909   ins_pipe(pipe_class_default);
9910 %}
9911 
9912 // Zero-extend: convert unsigned int to long (convUI2L).
9913 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
9914   match(Set dst (AndL (ConvI2L src) mask));
9915   ins_cost(DEFAULT_COST);
9916 
9917   format %{ "CLRLDI  $dst, $src, #32 \t// zero-extend int to long" %}
9918   size(4);
9919   ins_encode %{
9920     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9921     __ clrldi($dst$$Register, $src$$Register, 32);
9922   %}
9923   ins_pipe(pipe_class_default);
9924 %}
9925 
9926 // Zero-extend: convert unsigned int to long in long register.
9927 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
9928   match(Set dst (AndL src mask));
9929   ins_cost(DEFAULT_COST);
9930 
9931   format %{ "CLRLDI  $dst, $src, #32 \t// zero-extend int to long" %}
9932   size(4);
9933   ins_encode %{
9934     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9935     __ clrldi($dst$$Register, $src$$Register, 32);
9936   %}
9937   ins_pipe(pipe_class_default);
9938 %}
9939 
9940 instruct convF2LRaw_regF(regF dst, regF src) %{
9941   // no match-rule, false predicate
9942   effect(DEF dst, USE src);
9943   predicate(false);
9944 
9945   format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
9946   size(4);
9947   ins_encode %{
9948     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9949     __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9950   %}
9951   ins_pipe(pipe_class_default);
9952 %}
9953 
9954 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL src) %{
9955   // no match-rule, false predicate
9956   effect(DEF dst, USE crx, USE src);
9957   predicate(false);
9958 
9959   ins_variable_size_depending_on_alignment(true);
9960 
9961   format %{ "cmovL   $crx, $dst, $src" %}
9962   // Worst case is branch + move + stop, no stop without scheduler.
9963   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
9964   ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9965   ins_pipe(pipe_class_default);
9966 %}
9967 
9968 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, stackSlotL mem) %{
9969   // no match-rule, false predicate
9970   effect(DEF dst, USE crx, USE mem);
9971   predicate(false);
9972 
9973   format %{ "CmovL   $dst, $crx, $mem \t// postalloc expanded" %}
9974   postalloc_expand %{
9975     //
9976     // replaces
9977     //
9978     //   region  dst  crx  mem
9979     //    \       |    |   /
9980     //     dst=cmovL_bso_stackSlotL_conLvalue0
9981     //
9982     // with
9983     //
9984     //   region  dst
9985     //    \       /
9986     //     dst=loadConL16(0)
9987     //      |
9988     //      ^  region  dst  crx  mem
9989     //      |   \       |    |    /
9990     //      dst=cmovL_bso_stackSlotL
9991     //
9992 
9993     // Create new nodes.
9994     MachNode *m1 = new loadConL16Node();
9995     MachNode *m2 = new cmovL_bso_stackSlotLNode();
9996 
9997     // inputs for new nodes
9998     m1->add_req(n_region);
9999     m2->add_req(n_region, n_crx, n_mem);
10000     m2->add_prec(m1);
10001 
10002     // operands for new nodes
10003     m1->_opnds[0] = op_dst;
10004     m1->_opnds[1] = new immL16Oper(0);
10005     m2->_opnds[0] = op_dst;
10006     m2->_opnds[1] = op_crx;
10007     m2->_opnds[2] = op_mem;
10008 
10009     // registers for new nodes
10010     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10011     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10012 
10013     // Insert new nodes.
10014     nodes->push(m1);
10015     nodes->push(m2);
10016   %}
10017 %}
10018 
10019 // Float to Long conversion, NaN is mapped to 0.
10020 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
10021   match(Set dst (ConvF2L src));
10022   ins_cost(DEFAULT_COST);
10023 
10024   expand %{
10025     regF tmpF;
10026     stackSlotL tmpS;
10027     flagsReg crx;
10028     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10029     convF2LRaw_regF(tmpF, src);                         // Convert float to long (speculated).
10030     moveF2L_reg_stack(tmpS, tmpF);                      // Store float to stack (speculated).
10031     cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10032   %}
10033 %}
10034 
10035 instruct convD2LRaw_regD(regD dst, regD src) %{
10036   // no match-rule, false predicate
10037   effect(DEF dst, USE src);
10038   predicate(false);
10039 
10040   format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
10041   size(4);
10042   ins_encode %{
10043     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10044     __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10045   %}
10046   ins_pipe(pipe_class_default);
10047 %}
10048 
10049 // Double to Long conversion, NaN is mapped to 0.
10050 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
10051   match(Set dst (ConvD2L src));
10052   ins_cost(DEFAULT_COST);
10053 
10054   expand %{
10055     regD tmpD;
10056     stackSlotL tmpS;
10057     flagsReg crx;
10058     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10059     convD2LRaw_regD(tmpD, src);                         // Convert float to long (speculated).
10060     moveD2L_reg_stack(tmpS, tmpD);                      // Store float to stack (speculated).
10061     cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10062   %}
10063 %}
10064 
10065 // Convert to Float
10066 
10067 // Placed here as needed in expand.
10068 instruct convL2DRaw_regD(regD dst, regD src) %{
10069   // no match-rule, false predicate
10070   effect(DEF dst, USE src);
10071   predicate(false);
10072 
10073   format %{ "FCFID $dst, $src \t// convL2D" %}
10074   size(4);
10075   ins_encode %{
10076     // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10077     __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
10078   %}
10079   ins_pipe(pipe_class_default);
10080 %}
10081 
10082 // Placed here as needed in expand.
10083 instruct convD2F_reg(regF dst, regD src) %{
10084   match(Set dst (ConvD2F src));
10085   format %{ "FRSP    $dst, $src \t// convD2F" %}
10086   size(4);
10087   ins_encode %{
10088     // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
10089     __ frsp($dst$$FloatRegister, $src$$FloatRegister);
10090   %}
10091   ins_pipe(pipe_class_default);
10092 %}
10093 
10094 // Integer to Float conversion.
10095 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
10096   match(Set dst (ConvI2F src));
10097   predicate(!VM_Version::has_fcfids());
10098   ins_cost(DEFAULT_COST);
10099 
10100   expand %{
10101     iRegLdst tmpL;
10102     stackSlotL tmpS;
10103     regD tmpD;
10104     regD tmpD2;
10105     convI2L_reg(tmpL, src);              // Sign-extension int to long.
10106     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
10107     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
10108     convL2DRaw_regD(tmpD2, tmpD);        // Convert to double.
10109     convD2F_reg(dst, tmpD2);             // Convert double to float.
10110   %}
10111 %}
10112 
10113 instruct convL2FRaw_regF(regF dst, regD src) %{
10114   // no match-rule, false predicate
10115   effect(DEF dst, USE src);
10116   predicate(false);
10117 
10118   format %{ "FCFIDS $dst, $src \t// convL2F" %}
10119   size(4);
10120   ins_encode %{
10121     // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10122     __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10123   %}
10124   ins_pipe(pipe_class_default);
10125 %}
10126 
10127 // Integer to Float conversion. Special version for Power7.
10128 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10129   match(Set dst (ConvI2F src));
10130   predicate(VM_Version::has_fcfids());
10131   ins_cost(DEFAULT_COST);
10132 
10133   expand %{
10134     iRegLdst tmpL;
10135     stackSlotL tmpS;
10136     regD tmpD;
10137     convI2L_reg(tmpL, src);              // Sign-extension int to long.
10138     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
10139     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
10140     convL2FRaw_regF(dst, tmpD);          // Convert to float.
10141   %}
10142 %}
10143 
10144 // L2F to avoid runtime call.
10145 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10146   match(Set dst (ConvL2F src));
10147   predicate(VM_Version::has_fcfids());
10148   ins_cost(DEFAULT_COST);
10149 
10150   expand %{
10151     stackSlotL tmpS;
10152     regD tmpD;
10153     regL_to_stkL(tmpS, src);             // Store long to stack.
10154     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
10155     convL2FRaw_regF(dst, tmpD);          // Convert to float.
10156   %}
10157 %}
10158 
10159 // Moved up as used in expand.
10160 //instruct convD2F_reg(regF dst, regD src) %{%}
10161 
10162 // Convert to Double
10163 
10164 // Integer to Double conversion.
10165 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
10166   match(Set dst (ConvI2D src));
10167   ins_cost(DEFAULT_COST);
10168 
10169   expand %{
10170     iRegLdst tmpL;
10171     stackSlotL tmpS;
10172     regD tmpD;
10173     convI2L_reg(tmpL, src);              // Sign-extension int to long.
10174     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
10175     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
10176     convL2DRaw_regD(dst, tmpD);          // Convert to double.
10177   %}
10178 %}
10179 
10180 // Long to Double conversion
10181 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
10182   match(Set dst (ConvL2D src));
10183   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10184 
10185   expand %{
10186     regD tmpD;
10187     moveL2D_stack_reg(tmpD, src);
10188     convL2DRaw_regD(dst, tmpD);
10189   %}
10190 %}
10191 
10192 instruct convF2D_reg(regD dst, regF src) %{
10193   match(Set dst (ConvF2D src));
10194   format %{ "FMR     $dst, $src \t// float->double" %}
10195   // variable size, 0 or 4
10196   ins_encode %{
10197     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
10198     __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10199   %}
10200   ins_pipe(pipe_class_default);
10201 %}
10202 
10203 //----------Control Flow Instructions------------------------------------------
10204 // Compare Instructions
10205 
10206 // Compare Integers
10207 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10208   match(Set crx (CmpI src1 src2));
10209   size(4);
10210   format %{ "CMPW    $crx, $src1, $src2" %}
10211   ins_encode %{
10212     // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10213     __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10214   %}
10215   ins_pipe(pipe_class_compare);
10216 %}
10217 
10218 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
10219   match(Set crx (CmpI src1 src2));
10220   format %{ "CMPWI   $crx, $src1, $src2" %}
10221   size(4);
10222   ins_encode %{
10223     // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10224     __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10225   %}
10226   ins_pipe(pipe_class_compare);
10227 %}
10228 
10229 // (src1 & src2) == 0?
10230 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
10231   match(Set cr0 (CmpI (AndI src1 src2) zero));
10232   // r0 is killed
10233   format %{ "ANDI    R0, $src1, $src2 \t// BTST int" %}
10234   size(4);
10235   ins_encode %{
10236     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10237     __ andi_(R0, $src1$$Register, $src2$$constant);
10238   %}
10239   ins_pipe(pipe_class_compare);
10240 %}
10241 
10242 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10243   match(Set crx (CmpL src1 src2));
10244   format %{ "CMPD    $crx, $src1, $src2" %}
10245   size(4);
10246   ins_encode %{
10247     // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10248     __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
10249   %}
10250   ins_pipe(pipe_class_compare);
10251 %}
10252 
10253 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
10254   match(Set crx (CmpL src1 src2));
10255   format %{ "CMPDI   $crx, $src1, $src2" %}
10256   size(4);
10257   ins_encode %{
10258     // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10259     __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10260   %}
10261   ins_pipe(pipe_class_compare);
10262 %}
10263 
10264 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
10265   match(Set cr0 (CmpL (AndL src1 src2) zero));
10266   // r0 is killed
10267   format %{ "AND     R0, $src1, $src2 \t// BTST long" %}
10268   size(4);
10269   ins_encode %{
10270     // TODO: PPC port $archOpcode(ppc64Opcode_and_);
10271     __ and_(R0, $src1$$Register, $src2$$Register);
10272   %}
10273   ins_pipe(pipe_class_compare);
10274 %}
10275 
10276 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
10277   match(Set cr0 (CmpL (AndL src1 src2) zero));
10278   // r0 is killed
10279   format %{ "ANDI    R0, $src1, $src2 \t// BTST long" %}
10280   size(4);
10281   ins_encode %{
10282     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10283     __ andi_(R0, $src1$$Register, $src2$$constant);
10284   %}
10285   ins_pipe(pipe_class_compare);
10286 %}
10287 
10288 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsRegSrc crx) %{
10289   // no match-rule, false predicate
10290   effect(DEF dst, USE crx);
10291   predicate(false);
10292 
10293   ins_variable_size_depending_on_alignment(true);
10294 
10295   format %{ "cmovI   $crx, $dst, -1, 0, +1" %}
10296   // Worst case is branch + move + branch + move + stop, no stop without scheduler.
10297   size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
10298   ins_encode %{
10299     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
10300     Label done;
10301     // li(Rdst, 0);              // equal -> 0
10302     __ beq($crx$$CondRegister, done);
10303     __ li($dst$$Register, 1);    // greater -> +1
10304     __ bgt($crx$$CondRegister, done);
10305     __ li($dst$$Register, -1);   // unordered or less -> -1
10306     // TODO: PPC port__ endgroup_if_needed(_size == 20);
10307     __ bind(done);
10308   %}
10309   ins_pipe(pipe_class_compare);
10310 %}
10311 
10312 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsRegSrc crx) %{
10313   // no match-rule, false predicate
10314   effect(DEF dst, USE crx);
10315   predicate(false);
10316 
10317   format %{ "CmovI    $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
10318   postalloc_expand %{
10319     //
10320     // replaces
10321     //
10322     //   region  crx
10323     //    \       |
10324     //     dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
10325     //
10326     // with
10327     //
10328     //   region
10329     //    \
10330     //     dst=loadConI16(0)
10331     //      |
10332     //      ^  region  crx
10333     //      |   \       |
10334     //      dst=cmovI_conIvalueMinus1_conIvalue1
10335     //
10336 
10337     // Create new nodes.
10338     MachNode *m1 = new loadConI16Node();
10339     MachNode *m2 = new cmovI_conIvalueMinus1_conIvalue1Node();
10340 
10341     // inputs for new nodes
10342     m1->add_req(n_region);
10343     m2->add_req(n_region, n_crx);
10344     m2->add_prec(m1);
10345 
10346     // operands for new nodes
10347     m1->_opnds[0] = op_dst;
10348     m1->_opnds[1] = new immI16Oper(0);
10349     m2->_opnds[0] = op_dst;
10350     m2->_opnds[1] = op_crx;
10351 
10352     // registers for new nodes
10353     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10354     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10355 
10356     // Insert new nodes.
10357     nodes->push(m1);
10358     nodes->push(m2);
10359   %}
10360 %}
10361 
10362 // Manifest a CmpL3 result in an integer register. Very painful.
10363 // This is the test to avoid.
10364 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
10365 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10366   match(Set dst (CmpL3 src1 src2));
10367   ins_cost(DEFAULT_COST*5+BRANCH_COST);
10368 
10369   expand %{
10370     flagsReg tmp1;
10371     cmpL_reg_reg(tmp1, src1, src2);
10372     cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10373   %}
10374 %}
10375 
10376 // Implicit range checks.
10377 // A range check in the ideal world has one of the following shapes:
10378 //  - (If le (CmpU length index)), (IfTrue  throw exception)
10379 //  - (If lt (CmpU index length)), (IfFalse throw exception)
10380 //
10381 // Match range check 'If le (CmpU length index)'.
10382 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
10383   match(If cmp (CmpU src_length index));
10384   effect(USE labl);
10385   predicate(TrapBasedRangeChecks &&
10386             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
10387             PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
10388             (Matcher::branches_to_uncommon_trap(_leaf)));
10389 
10390   ins_is_TrapBasedCheckNode(true);
10391 
10392   format %{ "TWI     $index $cmp $src_length \t// RangeCheck => trap $labl" %}
10393   size(4);
10394   ins_encode %{
10395     // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10396     if ($cmp$$cmpcode == 0x1 /* less_equal */) {
10397       __ trap_range_check_le($src_length$$Register, $index$$constant);
10398     } else {
10399       // Both successors are uncommon traps, probability is 0.
10400       // Node got flipped during fixup flow.
10401       assert($cmp$$cmpcode == 0x9, "must be greater");
10402       __ trap_range_check_g($src_length$$Register, $index$$constant);
10403     }
10404   %}
10405   ins_pipe(pipe_class_trap);
10406 %}
10407 
10408 // Match range check 'If lt (CmpU index length)'.
10409 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
10410   match(If cmp (CmpU src_index src_length));
10411   effect(USE labl);
10412   predicate(TrapBasedRangeChecks &&
10413             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10414             _leaf->as_If()->_prob >= PROB_ALWAYS &&
10415             (Matcher::branches_to_uncommon_trap(_leaf)));
10416 
10417   ins_is_TrapBasedCheckNode(true);
10418 
10419   format %{ "TW      $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
10420   size(4);
10421   ins_encode %{
10422     // TODO: PPC port $archOpcode(ppc64Opcode_tw);
10423     if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10424       __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
10425     } else {
10426       // Both successors are uncommon traps, probability is 0.
10427       // Node got flipped during fixup flow.
10428       assert($cmp$$cmpcode == 0x8, "must be less");
10429       __ trap_range_check_l($src_index$$Register, $src_length$$Register);
10430     }
10431   %}
10432   ins_pipe(pipe_class_trap);
10433 %}
10434 
10435 // Match range check 'If lt (CmpU index length)'.
10436 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
10437   match(If cmp (CmpU src_index length));
10438   effect(USE labl);
10439   predicate(TrapBasedRangeChecks &&
10440             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10441             _leaf->as_If()->_prob >= PROB_ALWAYS &&
10442             (Matcher::branches_to_uncommon_trap(_leaf)));
10443 
10444   ins_is_TrapBasedCheckNode(true);
10445 
10446   format %{ "TWI     $src_index $cmp $length \t// RangeCheck => trap $labl" %}
10447   size(4);
10448   ins_encode %{
10449     // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10450     if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10451       __ trap_range_check_ge($src_index$$Register, $length$$constant);
10452     } else {
10453       // Both successors are uncommon traps, probability is 0.
10454       // Node got flipped during fixup flow.
10455       assert($cmp$$cmpcode == 0x8, "must be less");
10456       __ trap_range_check_l($src_index$$Register, $length$$constant);
10457     }
10458   %}
10459   ins_pipe(pipe_class_trap);
10460 %}
10461 
10462 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10463   match(Set crx (CmpU src1 src2));
10464   format %{ "CMPLW   $crx, $src1, $src2 \t// unsigned" %}
10465   size(4);
10466   ins_encode %{
10467     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10468     __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10469   %}
10470   ins_pipe(pipe_class_compare);
10471 %}
10472 
10473 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
10474   match(Set crx (CmpU src1 src2));
10475   size(4);
10476   format %{ "CMPLWI  $crx, $src1, $src2" %}
10477   ins_encode %{
10478     // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10479     __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10480   %}
10481   ins_pipe(pipe_class_compare);
10482 %}
10483 
10484 // Implicit zero checks (more implicit null checks).
10485 // No constant pool entries required.
10486 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
10487   match(If cmp (CmpN value zero));
10488   effect(USE labl);
10489   predicate(TrapBasedNullChecks &&
10490             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10491             _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10492             Matcher::branches_to_uncommon_trap(_leaf));
10493   ins_cost(1);
10494 
10495   ins_is_TrapBasedCheckNode(true);
10496 
10497   format %{ "TDI     $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
10498   size(4);
10499   ins_encode %{
10500     // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10501     if ($cmp$$cmpcode == 0xA) {
10502       __ trap_null_check($value$$Register);
10503     } else {
10504       // Both successors are uncommon traps, probability is 0.
10505       // Node got flipped during fixup flow.
10506       assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10507       __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10508     }
10509   %}
10510   ins_pipe(pipe_class_trap);
10511 %}
10512 
10513 // Compare narrow oops.
10514 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
10515   match(Set crx (CmpN src1 src2));
10516 
10517   size(4);
10518   ins_cost(2);
10519   format %{ "CMPLW   $crx, $src1, $src2 \t// compressed ptr" %}
10520   ins_encode %{
10521     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10522     __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10523   %}
10524   ins_pipe(pipe_class_compare);
10525 %}
10526 
10527 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
10528   match(Set crx (CmpN src1 src2));
10529   // Make this more expensive than zeroCheckN_iReg_imm0.
10530   ins_cost(2);
10531 
10532   format %{ "CMPLWI  $crx, $src1, $src2 \t// compressed ptr" %}
10533   size(4);
10534   ins_encode %{
10535     // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10536     __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10537   %}
10538   ins_pipe(pipe_class_compare);
10539 %}
10540 
10541 // Implicit zero checks (more implicit null checks).
10542 // No constant pool entries required.
10543 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
10544   match(If cmp (CmpP value zero));
10545   effect(USE labl);
10546   predicate(TrapBasedNullChecks &&
10547             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10548             _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10549             Matcher::branches_to_uncommon_trap(_leaf));
10550   ins_cost(1); // Should not be cheaper than zeroCheckN.
10551 
10552   ins_is_TrapBasedCheckNode(true);
10553 
10554   format %{ "TDI     $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
10555   size(4);
10556   ins_encode %{
10557     // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10558     if ($cmp$$cmpcode == 0xA) {
10559       __ trap_null_check($value$$Register);
10560     } else {
10561       // Both successors are uncommon traps, probability is 0.
10562       // Node got flipped during fixup flow.
10563       assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10564       __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10565     }
10566   %}
10567   ins_pipe(pipe_class_trap);
10568 %}
10569 
10570 // Compare Pointers
10571 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
10572   match(Set crx (CmpP src1 src2));
10573   format %{ "CMPLD   $crx, $src1, $src2 \t// ptr" %}
10574   size(4);
10575   ins_encode %{
10576     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10577     __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10578   %}
10579   ins_pipe(pipe_class_compare);
10580 %}
10581 
10582 // Used in postalloc expand.
10583 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
10584   // This match rule prevents reordering of node before a safepoint.
10585   // This only makes sense if this instructions is used exclusively
10586   // for the expansion of EncodeP!
10587   match(Set crx (CmpP src1 src2));
10588   predicate(false);
10589 
10590   format %{ "CMPDI   $crx, $src1, $src2" %}
10591   size(4);
10592   ins_encode %{
10593     // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10594     __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10595   %}
10596   ins_pipe(pipe_class_compare);
10597 %}
10598 
10599 //----------Float Compares----------------------------------------------------
10600 
10601 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
10602   // Needs matchrule, see cmpDUnordered.
10603   match(Set crx (CmpF src1 src2));
10604   // no match-rule, false predicate
10605   predicate(false);
10606 
10607   format %{ "cmpFUrd $crx, $src1, $src2" %}
10608   size(4);
10609   ins_encode %{
10610     // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10611     __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10612   %}
10613   ins_pipe(pipe_class_default);
10614 %}
10615 
10616 instruct cmov_bns_less(flagsReg crx) %{
10617   // no match-rule, false predicate
10618   effect(DEF crx);
10619   predicate(false);
10620 
10621   ins_variable_size_depending_on_alignment(true);
10622 
10623   format %{ "cmov    $crx" %}
10624   // Worst case is branch + move + stop, no stop without scheduler.
10625   size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
10626   ins_encode %{
10627     // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
10628     Label done;
10629     __ bns($crx$$CondRegister, done);        // not unordered -> keep crx
10630     __ li(R0, 0);
10631     __ cmpwi($crx$$CondRegister, R0, 1);     // unordered -> set crx to 'less'
10632     // TODO PPC port __ endgroup_if_needed(_size == 16);
10633     __ bind(done);
10634   %}
10635   ins_pipe(pipe_class_default);
10636 %}
10637 
10638 // Compare floating, generate condition code.
10639 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
10640   // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
10641   //
10642   // The following code sequence occurs a lot in mpegaudio:
10643   //
10644   // block BXX:
10645   // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
10646   //    cmpFUrd CCR6, F11, F9
10647   // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
10648   //    cmov CCR6
10649   // 8: instruct branchConSched:
10650   //    B_FARle CCR6, B56  P=0.500000 C=-1.000000
10651   match(Set crx (CmpF src1 src2));
10652   ins_cost(DEFAULT_COST+BRANCH_COST);
10653 
10654   format %{ "CmpF    $crx, $src1, $src2 \t// postalloc expanded" %}
10655   postalloc_expand %{
10656     //
10657     // replaces
10658     //
10659     //   region  src1  src2
10660     //    \       |     |
10661     //     crx=cmpF_reg_reg
10662     //
10663     // with
10664     //
10665     //   region  src1  src2
10666     //    \       |     |
10667     //     crx=cmpFUnordered_reg_reg
10668     //      |
10669     //      ^  region
10670     //      |   \
10671     //      crx=cmov_bns_less
10672     //
10673 
10674     // Create new nodes.
10675     MachNode *m1 = new cmpFUnordered_reg_regNode();
10676     MachNode *m2 = new cmov_bns_lessNode();
10677 
10678     // inputs for new nodes
10679     m1->add_req(n_region, n_src1, n_src2);
10680     m2->add_req(n_region);
10681     m2->add_prec(m1);
10682 
10683     // operands for new nodes
10684     m1->_opnds[0] = op_crx;
10685     m1->_opnds[1] = op_src1;
10686     m1->_opnds[2] = op_src2;
10687     m2->_opnds[0] = op_crx;
10688 
10689     // registers for new nodes
10690     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10691     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10692 
10693     // Insert new nodes.
10694     nodes->push(m1);
10695     nodes->push(m2);
10696   %}
10697 %}
10698 
10699 // Compare float, generate -1,0,1
10700 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
10701   match(Set dst (CmpF3 src1 src2));
10702   ins_cost(DEFAULT_COST*5+BRANCH_COST);
10703 
10704   expand %{
10705     flagsReg tmp1;
10706     cmpFUnordered_reg_reg(tmp1, src1, src2);
10707     cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10708   %}
10709 %}
10710 
10711 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
10712   // Needs matchrule so that ideal opcode is Cmp. This causes that gcm places the
10713   // node right before the conditional move using it.
10714   // In jck test api/java_awt/geom/QuadCurve2DFloat/index.html#SetCurveTesttestCase7,
10715   // compilation of java.awt.geom.RectangularShape::getBounds()Ljava/awt/Rectangle
10716   // crashed in register allocation where the flags Reg between cmpDUnoredered and a
10717   // conditional move was supposed to be spilled.
10718   match(Set crx (CmpD src1 src2));
10719   // False predicate, shall not be matched.
10720   predicate(false);
10721 
10722   format %{ "cmpFUrd $crx, $src1, $src2" %}
10723   size(4);
10724   ins_encode %{
10725     // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10726     __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10727   %}
10728   ins_pipe(pipe_class_default);
10729 %}
10730 
10731 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
10732   match(Set crx (CmpD src1 src2));
10733   ins_cost(DEFAULT_COST+BRANCH_COST);
10734 
10735   format %{ "CmpD    $crx, $src1, $src2 \t// postalloc expanded" %}
10736   postalloc_expand %{
10737     //
10738     // replaces
10739     //
10740     //   region  src1  src2
10741     //    \       |     |
10742     //     crx=cmpD_reg_reg
10743     //
10744     // with
10745     //
10746     //   region  src1  src2
10747     //    \       |     |
10748     //     crx=cmpDUnordered_reg_reg
10749     //      |
10750     //      ^  region
10751     //      |   \
10752     //      crx=cmov_bns_less
10753     //
10754 
10755     // create new nodes
10756     MachNode *m1 = new cmpDUnordered_reg_regNode();
10757     MachNode *m2 = new cmov_bns_lessNode();
10758 
10759     // inputs for new nodes
10760     m1->add_req(n_region, n_src1, n_src2);
10761     m2->add_req(n_region);
10762     m2->add_prec(m1);
10763 
10764     // operands for new nodes
10765     m1->_opnds[0] = op_crx;
10766     m1->_opnds[1] = op_src1;
10767     m1->_opnds[2] = op_src2;
10768     m2->_opnds[0] = op_crx;
10769 
10770     // registers for new nodes
10771     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10772     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10773 
10774     // Insert new nodes.
10775     nodes->push(m1);
10776     nodes->push(m2);
10777   %}
10778 %}
10779 
10780 // Compare double, generate -1,0,1
10781 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
10782   match(Set dst (CmpD3 src1 src2));
10783   ins_cost(DEFAULT_COST*5+BRANCH_COST);
10784 
10785   expand %{
10786     flagsReg tmp1;
10787     cmpDUnordered_reg_reg(tmp1, src1, src2);
10788     cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10789   %}
10790 %}
10791 
10792 //----------Branches---------------------------------------------------------
10793 // Jump
10794 
10795 // Direct Branch.
10796 instruct branch(label labl) %{
10797   match(Goto);
10798   effect(USE labl);
10799   ins_cost(BRANCH_COST);
10800 
10801   format %{ "B       $labl" %}
10802   size(4);
10803   ins_encode %{
10804     // TODO: PPC port $archOpcode(ppc64Opcode_b);
10805      Label d;    // dummy
10806      __ bind(d);
10807      Label* p = $labl$$label;
10808      // `p' is `NULL' when this encoding class is used only to
10809      // determine the size of the encoded instruction.
10810      Label& l = (NULL == p)? d : *(p);
10811      __ b(l);
10812   %}
10813   ins_pipe(pipe_class_default);
10814 %}
10815 
10816 // Conditional Near Branch
10817 instruct branchCon(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10818   // Same match rule as `branchConFar'.
10819   match(If cmp crx);
10820   effect(USE lbl);
10821   ins_cost(BRANCH_COST);
10822 
10823   // If set to 1 this indicates that the current instruction is a
10824   // short variant of a long branch. This avoids using this
10825   // instruction in first-pass matching. It will then only be used in
10826   // the `Shorten_branches' pass.
10827   ins_short_branch(1);
10828 
10829   format %{ "B$cmp     $crx, $lbl" %}
10830   size(4);
10831   ins_encode( enc_bc(crx, cmp, lbl) );
10832   ins_pipe(pipe_class_default);
10833 %}
10834 
10835 // This is for cases when the ppc64 `bc' instruction does not
10836 // reach far enough. So we emit a far branch here, which is more
10837 // expensive.
10838 //
10839 // Conditional Far Branch
10840 instruct branchConFar(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10841   // Same match rule as `branchCon'.
10842   match(If cmp crx);
10843   effect(USE crx, USE lbl);
10844   predicate(!false /* TODO: PPC port HB_Schedule*/);
10845   // Higher cost than `branchCon'.
10846   ins_cost(5*BRANCH_COST);
10847 
10848   // This is not a short variant of a branch, but the long variant.
10849   ins_short_branch(0);
10850 
10851   format %{ "B_FAR$cmp $crx, $lbl" %}
10852   size(8);
10853   ins_encode( enc_bc_far(crx, cmp, lbl) );
10854   ins_pipe(pipe_class_default);
10855 %}
10856 
10857 // Conditional Branch used with Power6 scheduler (can be far or short).
10858 instruct branchConSched(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10859   // Same match rule as `branchCon'.
10860   match(If cmp crx);
10861   effect(USE crx, USE lbl);
10862   predicate(false /* TODO: PPC port HB_Schedule*/);
10863   // Higher cost than `branchCon'.
10864   ins_cost(5*BRANCH_COST);
10865 
10866   // Actually size doesn't depend on alignment but on shortening.
10867   ins_variable_size_depending_on_alignment(true);
10868   // long variant.
10869   ins_short_branch(0);
10870 
10871   format %{ "B_FAR$cmp $crx, $lbl" %}
10872   size(8); // worst case
10873   ins_encode( enc_bc_short_far(crx, cmp, lbl) );
10874   ins_pipe(pipe_class_default);
10875 %}
10876 
10877 instruct branchLoopEnd(cmpOp cmp, flagsRegSrc crx, label labl) %{
10878   match(CountedLoopEnd cmp crx);
10879   effect(USE labl);
10880   ins_cost(BRANCH_COST);
10881 
10882   // short variant.
10883   ins_short_branch(1);
10884 
10885   format %{ "B$cmp     $crx, $labl \t// counted loop end" %}
10886   size(4);
10887   ins_encode( enc_bc(crx, cmp, labl) );
10888   ins_pipe(pipe_class_default);
10889 %}
10890 
10891 instruct branchLoopEndFar(cmpOp cmp, flagsRegSrc crx, label labl) %{
10892   match(CountedLoopEnd cmp crx);
10893   effect(USE labl);
10894   predicate(!false /* TODO: PPC port HB_Schedule */);
10895   ins_cost(BRANCH_COST);
10896 
10897   // Long variant.
10898   ins_short_branch(0);
10899 
10900   format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10901   size(8);
10902   ins_encode( enc_bc_far(crx, cmp, labl) );
10903   ins_pipe(pipe_class_default);
10904 %}
10905 
10906 // Conditional Branch used with Power6 scheduler (can be far or short).
10907 instruct branchLoopEndSched(cmpOp cmp, flagsRegSrc crx, label labl) %{
10908   match(CountedLoopEnd cmp crx);
10909   effect(USE labl);
10910   predicate(false /* TODO: PPC port HB_Schedule */);
10911   // Higher cost than `branchCon'.
10912   ins_cost(5*BRANCH_COST);
10913 
10914   // Actually size doesn't depend on alignment but on shortening.
10915   ins_variable_size_depending_on_alignment(true);
10916   // Long variant.
10917   ins_short_branch(0);
10918 
10919   format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10920   size(8); // worst case
10921   ins_encode( enc_bc_short_far(crx, cmp, labl) );
10922   ins_pipe(pipe_class_default);
10923 %}
10924 
10925 // ============================================================================
10926 // Java runtime operations, intrinsics and other complex operations.
10927 
10928 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10929 // array for an instance of the superklass. Set a hidden internal cache on a
10930 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10931 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10932 //
10933 // GL TODO: Improve this.
10934 // - result should not be a TEMP
10935 // - Add match rule as on sparc avoiding additional Cmp.
10936 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
10937                              iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
10938   match(Set result (PartialSubtypeCheck subklass superklass));
10939   effect(TEMP_DEF result, TEMP tmp_klass, TEMP tmp_arrayptr);
10940   ins_cost(DEFAULT_COST*10);
10941 
10942   format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
10943   ins_encode %{
10944     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10945     __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
10946                                      $tmp_klass$$Register, NULL, $result$$Register);
10947   %}
10948   ins_pipe(pipe_class_default);
10949 %}
10950 
10951 // inlined locking and unlocking
10952 
10953 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10954   match(Set crx (FastLock oop box));
10955   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10956   predicate(!Compile::current()->use_rtm());
10957 
10958   format %{ "FASTLOCK  $oop, $box, $tmp1, $tmp2, $tmp3" %}
10959   ins_encode %{
10960     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10961     __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10962                                  $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
10963                                  UseBiasedLocking && !UseOptoBiasInlining); // SAPJVM MD 2014-11-06 UseOptoBiasInlining
10964     // If locking was successfull, crx should indicate 'EQ'.
10965     // The compiler generates a branch to the runtime call to
10966     // _complete_monitor_locking_Java for the case where crx is 'NE'.
10967   %}
10968   ins_pipe(pipe_class_compare);
10969 %}
10970 
10971 // Separate version for TM. Use bound register for box to enable USE_KILL.
10972 instruct cmpFastLock_tm(flagsReg crx, iRegPdst oop, rarg2RegP box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10973   match(Set crx (FastLock oop box));
10974   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, USE_KILL box);
10975   predicate(Compile::current()->use_rtm());
10976 
10977   format %{ "FASTLOCK  $oop, $box, $tmp1, $tmp2, $tmp3 (TM)" %}
10978   ins_encode %{
10979     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10980     __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10981                                  $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
10982                                  /*Biased Locking*/ false,
10983                                  _rtm_counters, _stack_rtm_counters,
10984                                  ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
10985                                  /*TM*/ true, ra_->C->profile_rtm());
10986     // If locking was successfull, crx should indicate 'EQ'.
10987     // The compiler generates a branch to the runtime call to
10988     // _complete_monitor_locking_Java for the case where crx is 'NE'.
10989   %}
10990   ins_pipe(pipe_class_compare);
10991 %}
10992 
10993 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10994   match(Set crx (FastUnlock oop box));
10995   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10996   predicate(!Compile::current()->use_rtm());
10997 
10998   format %{ "FASTUNLOCK  $oop, $box, $tmp1, $tmp2" %}
10999   ins_encode %{
11000     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11001     __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
11002                                    $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
11003                                    UseBiasedLocking && !UseOptoBiasInlining,
11004                                    false);
11005     // If unlocking was successfull, crx should indicate 'EQ'.
11006     // The compiler generates a branch to the runtime call to
11007     // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
11008   %}
11009   ins_pipe(pipe_class_compare);
11010 %}
11011 
11012 instruct cmpFastUnlock_tm(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
11013   match(Set crx (FastUnlock oop box));
11014   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
11015   predicate(Compile::current()->use_rtm());
11016 
11017   format %{ "FASTUNLOCK  $oop, $box, $tmp1, $tmp2 (TM)" %}
11018   ins_encode %{
11019     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11020     __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
11021                                    $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
11022                                    /*Biased Locking*/ false, /*TM*/ true);
11023     // If unlocking was successfull, crx should indicate 'EQ'.
11024     // The compiler generates a branch to the runtime call to
11025     // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
11026   %}
11027   ins_pipe(pipe_class_compare);
11028 %}
11029 
11030 // Align address.
11031 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
11032   match(Set dst (CastX2P (AndL (CastP2X src) mask)));
11033 
11034   format %{ "ANDDI   $dst, $src, $mask \t// next aligned address" %}
11035   size(4);
11036   ins_encode %{
11037     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
11038     __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
11039   %}
11040   ins_pipe(pipe_class_default);
11041 %}
11042 
11043 // Array size computation.
11044 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
11045   match(Set dst (SubL (CastP2X end) (CastP2X start)));
11046 
11047   format %{ "SUB     $dst, $end, $start \t// array size in bytes" %}
11048   size(4);
11049   ins_encode %{
11050     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
11051     __ subf($dst$$Register, $start$$Register, $end$$Register);
11052   %}
11053   ins_pipe(pipe_class_default);
11054 %}
11055 
11056 // Clear-array with dynamic array-size.
11057 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
11058   match(Set dummy (ClearArray cnt base));
11059   effect(USE_KILL cnt, USE_KILL base, KILL ctr);
11060   ins_cost(MEMORY_REF_COST);
11061 
11062   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11063 
11064   format %{ "ClearArray $cnt, $base" %}
11065   ins_encode %{
11066     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11067     __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0
11068   %}
11069   ins_pipe(pipe_class_default);
11070 %}
11071 
11072 // String_IndexOf for needle of length 1.
11073 //
11074 // Match needle into immediate operands: no loadConP node needed. Saves one
11075 // register and two instructions over string_indexOf_imm1Node.
11076 //
11077 // Assumes register result differs from all input registers.
11078 //
11079 // Preserves registers haystack, haycnt
11080 // Kills     registers tmp1, tmp2
11081 // Defines   registers result
11082 //
11083 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11084 //
11085 // Unfortunately this does not match too often. In many situations the AddP is used
11086 // by several nodes, even several StrIndexOf nodes, breaking the match tree.
11087 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11088                                   immP needleImm, immL offsetImm, immI_1 needlecntImm,
11089                                   iRegIdst tmp1, iRegIdst tmp2,
11090                                   flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11091   predicate(SpecialStringIndexOf && !CompactStrings);  // type check implicit by parameter type, See Matcher::match_rule_supported
11092   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
11093 
11094   effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1);
11095 
11096   ins_cost(150);
11097   format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
11098             "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11099 
11100   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted
11101   ins_encode %{
11102     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11103     immPOper *needleOper = (immPOper *)$needleImm;
11104     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11105     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
11106 
11107     __ string_indexof_1($result$$Register,
11108                         $haystack$$Register, $haycnt$$Register,
11109                         R0, needle_values->char_at(0),
11110                         $tmp1$$Register, $tmp2$$Register);
11111   %}
11112   ins_pipe(pipe_class_compare);
11113 %}
11114 
11115 // String_IndexOf for needle of length 1.
11116 //
11117 // Special case requires less registers and emits less instructions.
11118 //
11119 // Assumes register result differs from all input registers.
11120 //
11121 // Preserves registers haystack, haycnt
11122 // Kills     registers tmp1, tmp2, needle
11123 // Defines   registers result
11124 //
11125 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11126 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11127                              rscratch2RegP needle, immI_1 needlecntImm,
11128                              iRegIdst tmp1, iRegIdst tmp2,
11129                              flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11130   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11131   effect(USE_KILL needle, /* TDEF needle, */ TEMP_DEF result,
11132          TEMP tmp1, TEMP tmp2);
11133   // Required for EA: check if it is still a type_array.
11134   predicate(SpecialStringIndexOf && !CompactStrings && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11135             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11136   ins_cost(180);
11137 
11138   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11139 
11140   format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11141             " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11142   ins_encode %{
11143     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11144     Node *ndl = in(operand_index($needle));  // The node that defines needle.
11145     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11146     guarantee(needle_values, "sanity");
11147     if (needle_values != NULL) {
11148       __ string_indexof_1($result$$Register,
11149                           $haystack$$Register, $haycnt$$Register,
11150                           R0, needle_values->char_at(0),
11151                           $tmp1$$Register, $tmp2$$Register);
11152     } else {
11153       __ string_indexof_1($result$$Register,
11154                           $haystack$$Register, $haycnt$$Register,
11155                           $needle$$Register, 0,
11156                           $tmp1$$Register, $tmp2$$Register);
11157     }
11158   %}
11159   ins_pipe(pipe_class_compare);
11160 %}
11161 
11162 // String_IndexOf.
11163 //
11164 // Length of needle as immediate. This saves instruction loading constant needle
11165 // length.
11166 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle
11167 // completely or do it in vector instruction. This should save registers for
11168 // needlecnt and needle.
11169 //
11170 // Assumes register result differs from all input registers.
11171 // Overwrites haycnt, needlecnt.
11172 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11173 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11174                             iRegPsrc needle, uimmI15 needlecntImm,
11175                             iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11176                             flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11177   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11178   effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
11179          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6);
11180   // Required for EA: check if it is still a type_array.
11181   predicate(SpecialStringIndexOf && !CompactStrings && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11182             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11183   ins_cost(250);
11184 
11185   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11186 
11187   format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11188             " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11189   ins_encode %{
11190     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11191     Node *ndl = in(operand_index($needle));  // The node that defines needle.
11192     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11193 
11194     __ string_indexof($result$$Register,
11195                       $haystack$$Register, $haycnt$$Register,
11196                       $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11197                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11198   %}
11199   ins_pipe(pipe_class_compare);
11200 %}
11201 
11202 // StrIndexOf node.
11203 //
11204 // Assumes register result differs from all input registers.
11205 // Overwrites haycnt, needlecnt.
11206 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11207 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11208                         iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11209                         flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11210   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11211   effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11212          TEMP_DEF result,
11213          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6);
11214   predicate(SpecialStringIndexOf && !CompactStrings);  // See Matcher::match_rule_supported.
11215   ins_cost(300);
11216 
11217   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11218 
11219   format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11220              " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11221   ins_encode %{
11222     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11223     __ string_indexof($result$$Register,
11224                       $haystack$$Register, $haycnt$$Register,
11225                       $needle$$Register, NULL, $needlecnt$$Register, 0,  // needlecnt not constant.
11226                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11227   %}
11228   ins_pipe(pipe_class_compare);
11229 %}
11230 
11231 // String equals with immediate.
11232 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result,
11233                            iRegPdst tmp1, iRegPdst tmp2,
11234                            flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{
11235   match(Set result (StrEquals (Binary str1 str2) cntImm));
11236   effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2,
11237          KILL cr0, KILL cr6, KILL ctr);
11238   predicate(SpecialStringEquals && !CompactStrings);  // See Matcher::match_rule_supported.
11239   ins_cost(250);
11240 
11241   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11242 
11243   format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)"
11244             " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %}
11245   ins_encode %{
11246     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11247     __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant,
11248                              $result$$Register, $tmp1$$Register, $tmp2$$Register);
11249   %}
11250   ins_pipe(pipe_class_compare);
11251 %}
11252 
11253 // String equals.
11254 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11255 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result,
11256                        iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5,
11257                        flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11258   match(Set result (StrEquals (Binary str1 str2) cnt));
11259   effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11260          KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11261   predicate(SpecialStringEquals && !CompactStrings);  // See Matcher::match_rule_supported.
11262   ins_cost(300);
11263 
11264   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11265 
11266   format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result"
11267             " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11268   ins_encode %{
11269     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11270     __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register,
11271                           $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11272   %}
11273   ins_pipe(pipe_class_compare);
11274 %}
11275 
11276 // String compare.
11277 // Char[] pointers are passed in.
11278 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11279 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11280                         iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{
11281   predicate(!CompactStrings);
11282   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11283   effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP_DEF result, TEMP tmp, KILL cr0, KILL ctr);
11284   ins_cost(300);
11285 
11286   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11287 
11288   format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result"
11289             " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %}
11290   ins_encode %{
11291     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11292     __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register,
11293                       $result$$Register, $tmp$$Register);
11294   %}
11295   ins_pipe(pipe_class_compare);
11296 %}
11297 
11298 //---------- Min/Max Instructions ---------------------------------------------
11299 
11300 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11301   match(Set dst (MinI src1 src2));
11302   ins_cost(DEFAULT_COST*6);
11303 
11304   expand %{
11305     iRegLdst src1s;
11306     iRegLdst src2s;
11307     iRegLdst diff;
11308     iRegLdst sm;
11309     iRegLdst doz; // difference or zero
11310     convI2L_reg(src1s, src1); // Ensure proper sign extension.
11311     convI2L_reg(src2s, src2); // Ensure proper sign extension.
11312     subL_reg_reg(diff, src2s, src1s);
11313     // Need to consider >=33 bit result, therefore we need signmaskL.
11314     signmask64L_regL(sm, diff);
11315     andL_reg_reg(doz, diff, sm); // <=0
11316     addI_regL_regL(dst, doz, src1s);
11317   %}
11318 %}
11319 
11320 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11321   match(Set dst (MaxI src1 src2));
11322   ins_cost(DEFAULT_COST*6);
11323 
11324   expand %{
11325     iRegLdst src1s;
11326     iRegLdst src2s;
11327     iRegLdst diff;
11328     iRegLdst sm;
11329     iRegLdst doz; // difference or zero
11330     convI2L_reg(src1s, src1); // Ensure proper sign extension.
11331     convI2L_reg(src2s, src2); // Ensure proper sign extension.
11332     subL_reg_reg(diff, src2s, src1s);
11333     // Need to consider >=33 bit result, therefore we need signmaskL.
11334     signmask64L_regL(sm, diff);
11335     andcL_reg_reg(doz, diff, sm); // >=0
11336     addI_regL_regL(dst, doz, src1s);
11337   %}
11338 %}
11339 
11340 //---------- Population Count Instructions ------------------------------------
11341 
11342 // Popcnt for Power7.
11343 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
11344   match(Set dst (PopCountI src));
11345   predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11346   ins_cost(DEFAULT_COST);
11347 
11348   format %{ "POPCNTW $dst, $src" %}
11349   size(4);
11350   ins_encode %{
11351     // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11352     __ popcntw($dst$$Register, $src$$Register);
11353   %}
11354   ins_pipe(pipe_class_default);
11355 %}
11356 
11357 // Popcnt for Power7.
11358 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
11359   predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11360   match(Set dst (PopCountL src));
11361   ins_cost(DEFAULT_COST);
11362 
11363   format %{ "POPCNTD $dst, $src" %}
11364   size(4);
11365   ins_encode %{
11366     // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11367     __ popcntd($dst$$Register, $src$$Register);
11368   %}
11369   ins_pipe(pipe_class_default);
11370 %}
11371 
11372 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
11373   match(Set dst (CountLeadingZerosI src));
11374   predicate(UseCountLeadingZerosInstructionsPPC64);  // See Matcher::match_rule_supported.
11375   ins_cost(DEFAULT_COST);
11376 
11377   format %{ "CNTLZW  $dst, $src" %}
11378   size(4);
11379   ins_encode %{
11380     // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
11381     __ cntlzw($dst$$Register, $src$$Register);
11382   %}
11383   ins_pipe(pipe_class_default);
11384 %}
11385 
11386 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
11387   match(Set dst (CountLeadingZerosL src));
11388   predicate(UseCountLeadingZerosInstructionsPPC64);  // See Matcher::match_rule_supported.
11389   ins_cost(DEFAULT_COST);
11390 
11391   format %{ "CNTLZD  $dst, $src" %}
11392   size(4);
11393   ins_encode %{
11394     // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11395     __ cntlzd($dst$$Register, $src$$Register);
11396   %}
11397   ins_pipe(pipe_class_default);
11398 %}
11399 
11400 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
11401   // no match-rule, false predicate
11402   effect(DEF dst, USE src);
11403   predicate(false);
11404 
11405   format %{ "CNTLZD  $dst, $src" %}
11406   size(4);
11407   ins_encode %{
11408     // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11409     __ cntlzd($dst$$Register, $src$$Register);
11410   %}
11411   ins_pipe(pipe_class_default);
11412 %}
11413 
11414 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
11415   match(Set dst (CountTrailingZerosI src));
11416   predicate(UseCountLeadingZerosInstructionsPPC64);
11417   ins_cost(DEFAULT_COST);
11418 
11419   expand %{
11420     immI16 imm1 %{ (int)-1 %}
11421     immI16 imm2 %{ (int)32 %}
11422     immI_minus1 m1 %{ -1 %}
11423     iRegIdst tmpI1;
11424     iRegIdst tmpI2;
11425     iRegIdst tmpI3;
11426     addI_reg_imm16(tmpI1, src, imm1);
11427     andcI_reg_reg(tmpI2, src, m1, tmpI1);
11428     countLeadingZerosI(tmpI3, tmpI2);
11429     subI_imm16_reg(dst, imm2, tmpI3);
11430   %}
11431 %}
11432 
11433 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
11434   match(Set dst (CountTrailingZerosL src));
11435   predicate(UseCountLeadingZerosInstructionsPPC64);
11436   ins_cost(DEFAULT_COST);
11437 
11438   expand %{
11439     immL16 imm1 %{ (long)-1 %}
11440     immI16 imm2 %{ (int)64 %}
11441     iRegLdst tmpL1;
11442     iRegLdst tmpL2;
11443     iRegIdst tmpL3;
11444     addL_reg_imm16(tmpL1, src, imm1);
11445     andcL_reg_reg(tmpL2, tmpL1, src);
11446     countLeadingZerosL(tmpL3, tmpL2);
11447     subI_imm16_reg(dst, imm2, tmpL3);
11448  %}
11449 %}
11450 
11451 // Expand nodes for byte_reverse_int.
11452 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11453   effect(DEF dst, USE src, USE pos, USE shift);
11454   predicate(false);
11455 
11456   format %{ "INSRWI  $dst, $src, $pos, $shift" %}
11457   size(4);
11458   ins_encode %{
11459     // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11460     __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11461   %}
11462   ins_pipe(pipe_class_default);
11463 %}
11464 
11465 // As insrwi_a, but with USE_DEF.
11466 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11467   effect(USE_DEF dst, USE src, USE pos, USE shift);
11468   predicate(false);
11469 
11470   format %{ "INSRWI  $dst, $src, $pos, $shift" %}
11471   size(4);
11472   ins_encode %{
11473     // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11474     __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11475   %}
11476   ins_pipe(pipe_class_default);
11477 %}
11478 
11479 // Just slightly faster than java implementation.
11480 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
11481   match(Set dst (ReverseBytesI src));
11482   predicate(UseCountLeadingZerosInstructionsPPC64);
11483   ins_cost(DEFAULT_COST);
11484 
11485   expand %{
11486     immI16 imm24 %{ (int) 24 %}
11487     immI16 imm16 %{ (int) 16 %}
11488     immI16  imm8 %{ (int)  8 %}
11489     immI16  imm4 %{ (int)  4 %}
11490     immI16  imm0 %{ (int)  0 %}
11491     iRegLdst tmpI1;
11492     iRegLdst tmpI2;
11493     iRegLdst tmpI3;
11494 
11495     urShiftI_reg_imm(tmpI1, src, imm24);
11496     insrwi_a(dst, tmpI1, imm24, imm8);
11497     urShiftI_reg_imm(tmpI2, src, imm16);
11498     insrwi(dst, tmpI2, imm8, imm16);
11499     urShiftI_reg_imm(tmpI3, src, imm8);
11500     insrwi(dst, tmpI3, imm8, imm8);
11501     insrwi(dst, src, imm0, imm8);
11502   %}
11503 %}
11504 
11505 //---------- Replicate Vector Instructions ------------------------------------
11506 
11507 // Insrdi does replicate if src == dst.
11508 instruct repl32(iRegLdst dst) %{
11509   predicate(false);
11510   effect(USE_DEF dst);
11511 
11512   format %{ "INSRDI  $dst, #0, $dst, #32 \t// replicate" %}
11513   size(4);
11514   ins_encode %{
11515     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11516     __ insrdi($dst$$Register, $dst$$Register, 32, 0);
11517   %}
11518   ins_pipe(pipe_class_default);
11519 %}
11520 
11521 // Insrdi does replicate if src == dst.
11522 instruct repl48(iRegLdst dst) %{
11523   predicate(false);
11524   effect(USE_DEF dst);
11525 
11526   format %{ "INSRDI  $dst, #0, $dst, #48 \t// replicate" %}
11527   size(4);
11528   ins_encode %{
11529     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11530     __ insrdi($dst$$Register, $dst$$Register, 48, 0);
11531   %}
11532   ins_pipe(pipe_class_default);
11533 %}
11534 
11535 // Insrdi does replicate if src == dst.
11536 instruct repl56(iRegLdst dst) %{
11537   predicate(false);
11538   effect(USE_DEF dst);
11539 
11540   format %{ "INSRDI  $dst, #0, $dst, #56 \t// replicate" %}
11541   size(4);
11542   ins_encode %{
11543     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11544     __ insrdi($dst$$Register, $dst$$Register, 56, 0);
11545   %}
11546   ins_pipe(pipe_class_default);
11547 %}
11548 
11549 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11550   match(Set dst (ReplicateB src));
11551   predicate(n->as_Vector()->length() == 8);
11552   expand %{
11553     moveReg(dst, src);
11554     repl56(dst);
11555     repl48(dst);
11556     repl32(dst);
11557   %}
11558 %}
11559 
11560 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
11561   match(Set dst (ReplicateB zero));
11562   predicate(n->as_Vector()->length() == 8);
11563   format %{ "LI      $dst, #0 \t// replicate8B" %}
11564   size(4);
11565   ins_encode %{
11566     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11567     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11568   %}
11569   ins_pipe(pipe_class_default);
11570 %}
11571 
11572 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
11573   match(Set dst (ReplicateB src));
11574   predicate(n->as_Vector()->length() == 8);
11575   format %{ "LI      $dst, #-1 \t// replicate8B" %}
11576   size(4);
11577   ins_encode %{
11578     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11579     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11580   %}
11581   ins_pipe(pipe_class_default);
11582 %}
11583 
11584 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11585   match(Set dst (ReplicateS src));
11586   predicate(n->as_Vector()->length() == 4);
11587   expand %{
11588     moveReg(dst, src);
11589     repl48(dst);
11590     repl32(dst);
11591   %}
11592 %}
11593 
11594 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
11595   match(Set dst (ReplicateS zero));
11596   predicate(n->as_Vector()->length() == 4);
11597   format %{ "LI      $dst, #0 \t// replicate4C" %}
11598   size(4);
11599   ins_encode %{
11600     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11601     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11602   %}
11603   ins_pipe(pipe_class_default);
11604 %}
11605 
11606 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
11607   match(Set dst (ReplicateS src));
11608   predicate(n->as_Vector()->length() == 4);
11609   format %{ "LI      $dst, -1 \t// replicate4C" %}
11610   size(4);
11611   ins_encode %{
11612     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11613     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11614   %}
11615   ins_pipe(pipe_class_default);
11616 %}
11617 
11618 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11619   match(Set dst (ReplicateI src));
11620   predicate(n->as_Vector()->length() == 2);
11621   ins_cost(2 * DEFAULT_COST);
11622   expand %{
11623     moveReg(dst, src);
11624     repl32(dst);
11625   %}
11626 %}
11627 
11628 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
11629   match(Set dst (ReplicateI zero));
11630   predicate(n->as_Vector()->length() == 2);
11631   format %{ "LI      $dst, #0 \t// replicate4C" %}
11632   size(4);
11633   ins_encode %{
11634     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11635     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11636   %}
11637   ins_pipe(pipe_class_default);
11638 %}
11639 
11640 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
11641   match(Set dst (ReplicateI src));
11642   predicate(n->as_Vector()->length() == 2);
11643   format %{ "LI      $dst, -1 \t// replicate4C" %}
11644   size(4);
11645   ins_encode %{
11646     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11647     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11648   %}
11649   ins_pipe(pipe_class_default);
11650 %}
11651 
11652 // Move float to int register via stack, replicate.
11653 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
11654   match(Set dst (ReplicateF src));
11655   predicate(n->as_Vector()->length() == 2);
11656   ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
11657   expand %{
11658     stackSlotL tmpS;
11659     iRegIdst tmpI;
11660     moveF2I_reg_stack(tmpS, src);   // Move float to stack.
11661     moveF2I_stack_reg(tmpI, tmpS);  // Move stack to int reg.
11662     moveReg(dst, tmpI);             // Move int to long reg.
11663     repl32(dst);                    // Replicate bitpattern.
11664   %}
11665 %}
11666 
11667 // Replicate scalar constant to packed float values in Double register
11668 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
11669   match(Set dst (ReplicateF src));
11670   predicate(n->as_Vector()->length() == 2);
11671   ins_cost(5 * DEFAULT_COST);
11672 
11673   format %{ "LD      $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
11674   postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
11675 %}
11676 
11677 // Replicate scalar zero constant to packed float values in Double register
11678 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
11679   match(Set dst (ReplicateF zero));
11680   predicate(n->as_Vector()->length() == 2);
11681 
11682   format %{ "LI      $dst, #0 \t// replicate2F" %}
11683   ins_encode %{
11684     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11685     __ li($dst$$Register, 0x0);
11686   %}
11687   ins_pipe(pipe_class_default);
11688 %}
11689 
11690 
11691 //----------Overflow Math Instructions-----------------------------------------
11692 
11693 // Note that we have to make sure that XER.SO is reset before using overflow instructions.
11694 // Simple Overflow operations can be matched by very few instructions (e.g. addExact: xor, and_, bc).
11695 // Seems like only Long intrinsincs have an advantage. (The only expensive one is OverflowMulL.)
11696 
11697 instruct overflowAddL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
11698   match(Set cr0 (OverflowAddL op1 op2));
11699 
11700   format %{ "add_    $op1, $op2\t# overflow check long" %}
11701   ins_encode %{
11702     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11703     __ li(R0, 0);
11704     __ mtxer(R0); // clear XER.SO
11705     __ addo_(R0, $op1$$Register, $op2$$Register);
11706   %}
11707   ins_pipe(pipe_class_default);
11708 %}
11709 
11710 instruct overflowSubL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
11711   match(Set cr0 (OverflowSubL op1 op2));
11712 
11713   format %{ "subfo_  R0, $op2, $op1\t# overflow check long" %}
11714   ins_encode %{
11715     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11716     __ li(R0, 0);
11717     __ mtxer(R0); // clear XER.SO
11718     __ subfo_(R0, $op2$$Register, $op1$$Register);
11719   %}
11720   ins_pipe(pipe_class_default);
11721 %}
11722 
11723 instruct overflowNegL_reg(flagsRegCR0 cr0, immL_0 zero, iRegLsrc op2) %{
11724   match(Set cr0 (OverflowSubL zero op2));
11725 
11726   format %{ "nego_   R0, $op2\t# overflow check long" %}
11727   ins_encode %{
11728     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11729     __ li(R0, 0);
11730     __ mtxer(R0); // clear XER.SO
11731     __ nego_(R0, $op2$$Register);
11732   %}
11733   ins_pipe(pipe_class_default);
11734 %}
11735 
11736 instruct overflowMulL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
11737   match(Set cr0 (OverflowMulL op1 op2));
11738 
11739   format %{ "mulldo_ R0, $op1, $op2\t# overflow check long" %}
11740   ins_encode %{
11741     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11742     __ li(R0, 0);
11743     __ mtxer(R0); // clear XER.SO
11744     __ mulldo_(R0, $op1$$Register, $op2$$Register);
11745   %}
11746   ins_pipe(pipe_class_default);
11747 %}
11748 
11749 
11750 // ============================================================================
11751 // Safepoint Instruction
11752 
11753 instruct safePoint_poll(iRegPdst poll) %{
11754   match(SafePoint poll);
11755   predicate(LoadPollAddressFromThread);
11756 
11757   // It caused problems to add the effect that r0 is killed, but this
11758   // effect no longer needs to be mentioned, since r0 is not contained
11759   // in a reg_class.
11760 
11761   format %{ "LD      R0, #0, $poll \t// Safepoint poll for GC" %}
11762   size(4);
11763   ins_encode( enc_poll(0x0, poll) );
11764   ins_pipe(pipe_class_default);
11765 %}
11766 
11767 // Safepoint without per-thread support. Load address of page to poll
11768 // as constant.
11769 // Rscratch2RegP is R12.
11770 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
11771 // a seperate node so that the oop map is at the right location.
11772 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
11773   match(SafePoint poll);
11774   predicate(!LoadPollAddressFromThread);
11775 
11776   // It caused problems to add the effect that r0 is killed, but this
11777   // effect no longer needs to be mentioned, since r0 is not contained
11778   // in a reg_class.
11779 
11780   format %{ "LD      R0, #0, R12 \t// Safepoint poll for GC" %}
11781   ins_encode( enc_poll(0x0, poll) );
11782   ins_pipe(pipe_class_default);
11783 %}
11784 
11785 // ============================================================================
11786 // Call Instructions
11787 
11788 // Call Java Static Instruction
11789 
11790 // Schedulable version of call static node.
11791 instruct CallStaticJavaDirect(method meth) %{
11792   match(CallStaticJava);
11793   effect(USE meth);
11794   predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke());
11795   ins_cost(CALL_COST);
11796 
11797   ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11798 
11799   format %{ "CALL,static $meth \t// ==> " %}
11800   size(4);
11801   ins_encode( enc_java_static_call(meth) );
11802   ins_pipe(pipe_class_call);
11803 %}
11804 
11805 // Schedulable version of call static node.
11806 instruct CallStaticJavaDirectHandle(method meth) %{
11807   match(CallStaticJava);
11808   effect(USE meth);
11809   predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
11810   ins_cost(CALL_COST);
11811 
11812   ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11813 
11814   format %{ "CALL,static $meth \t// ==> " %}
11815   ins_encode( enc_java_handle_call(meth) );
11816   ins_pipe(pipe_class_call);
11817 %}
11818 
11819 // Call Java Dynamic Instruction
11820 
11821 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
11822 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
11823 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
11824 // The call destination must still be placed in the constant pool.
11825 instruct CallDynamicJavaDirectSched(method meth) %{
11826   match(CallDynamicJava); // To get all the data fields we need ...
11827   effect(USE meth);
11828   predicate(false);       // ... but never match.
11829 
11830   ins_field_load_ic_hi_node(loadConL_hiNode*);
11831   ins_field_load_ic_node(loadConLNode*);
11832   ins_num_consts(1 /* 1 patchable constant: call destination */);
11833 
11834   format %{ "BL        \t// dynamic $meth ==> " %}
11835   size(4);
11836   ins_encode( enc_java_dynamic_call_sched(meth) );
11837   ins_pipe(pipe_class_call);
11838 %}
11839 
11840 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
11841 // We use postalloc expanded calls if we use inline caches
11842 // and do not update method data.
11843 //
11844 // This instruction has two constants: inline cache (IC) and call destination.
11845 // Loading the inline cache will be postalloc expanded, thus leaving a call with
11846 // one constant.
11847 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
11848   match(CallDynamicJava);
11849   effect(USE meth);
11850   predicate(UseInlineCaches);
11851   ins_cost(CALL_COST);
11852 
11853   ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
11854 
11855   format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
11856   postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
11857 %}
11858 
11859 // Compound version of call dynamic java
11860 // We use postalloc expanded calls if we use inline caches
11861 // and do not update method data.
11862 instruct CallDynamicJavaDirect(method meth) %{
11863   match(CallDynamicJava);
11864   effect(USE meth);
11865   predicate(!UseInlineCaches);
11866   ins_cost(CALL_COST);
11867 
11868   // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
11869   ins_num_consts(4);
11870 
11871   format %{ "CALL,dynamic $meth \t// ==> " %}
11872   ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
11873   ins_pipe(pipe_class_call);
11874 %}
11875 
11876 // Call Runtime Instruction
11877 
11878 instruct CallRuntimeDirect(method meth) %{
11879   match(CallRuntime);
11880   effect(USE meth);
11881   ins_cost(CALL_COST);
11882 
11883   // Enc_java_to_runtime_call needs up to 3 constants: call target,
11884   // env for callee, C-toc.
11885   ins_num_consts(3);
11886 
11887   format %{ "CALL,runtime" %}
11888   ins_encode( enc_java_to_runtime_call(meth) );
11889   ins_pipe(pipe_class_call);
11890 %}
11891 
11892 // Call Leaf
11893 
11894 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
11895 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
11896   effect(DEF dst, USE src);
11897 
11898   ins_num_consts(1);
11899 
11900   format %{ "MTCTR   $src" %}
11901   size(4);
11902   ins_encode( enc_leaf_call_mtctr(src) );
11903   ins_pipe(pipe_class_default);
11904 %}
11905 
11906 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
11907 instruct CallLeafDirect(method meth) %{
11908   match(CallLeaf);   // To get the data all the data fields we need ...
11909   effect(USE meth);
11910   predicate(false);  // but never match.
11911 
11912   format %{ "BCTRL     \t// leaf call $meth ==> " %}
11913   size(4);
11914   ins_encode %{
11915     // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
11916     __ bctrl();
11917   %}
11918   ins_pipe(pipe_class_call);
11919 %}
11920 
11921 // postalloc expand of CallLeafDirect.
11922 // Load adress to call from TOC, then bl to it.
11923 instruct CallLeafDirect_Ex(method meth) %{
11924   match(CallLeaf);
11925   effect(USE meth);
11926   ins_cost(CALL_COST);
11927 
11928   // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
11929   // env for callee, C-toc.
11930   ins_num_consts(3);
11931 
11932   format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
11933   postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11934 %}
11935 
11936 // Call runtime without safepoint - same as CallLeaf.
11937 // postalloc expand of CallLeafNoFPDirect.
11938 // Load adress to call from TOC, then bl to it.
11939 instruct CallLeafNoFPDirect_Ex(method meth) %{
11940   match(CallLeafNoFP);
11941   effect(USE meth);
11942   ins_cost(CALL_COST);
11943 
11944   // Enc_java_to_runtime_call needs up to 3 constants: call target,
11945   // env for callee, C-toc.
11946   ins_num_consts(3);
11947 
11948   format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
11949   postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11950 %}
11951 
11952 // Tail Call; Jump from runtime stub to Java code.
11953 // Also known as an 'interprocedural jump'.
11954 // Target of jump will eventually return to caller.
11955 // TailJump below removes the return address.
11956 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
11957   match(TailCall jump_target method_oop);
11958   ins_cost(CALL_COST);
11959 
11960   format %{ "MTCTR   $jump_target \t// $method_oop holds method oop\n\t"
11961             "BCTR         \t// tail call" %}
11962   size(8);
11963   ins_encode %{
11964     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11965     __ mtctr($jump_target$$Register);
11966     __ bctr();
11967   %}
11968   ins_pipe(pipe_class_call);
11969 %}
11970 
11971 // Return Instruction
11972 instruct Ret() %{
11973   match(Return);
11974   format %{ "BLR      \t// branch to link register" %}
11975   size(4);
11976   ins_encode %{
11977     // TODO: PPC port $archOpcode(ppc64Opcode_blr);
11978     // LR is restored in MachEpilogNode. Just do the RET here.
11979     __ blr();
11980   %}
11981   ins_pipe(pipe_class_default);
11982 %}
11983 
11984 // Tail Jump; remove the return address; jump to target.
11985 // TailCall above leaves the return address around.
11986 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11987 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11988 // "restore" before this instruction (in Epilogue), we need to materialize it
11989 // in %i0.
11990 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
11991   match(TailJump jump_target ex_oop);
11992   ins_cost(CALL_COST);
11993 
11994   format %{ "LD      R4_ARG2 = LR\n\t"
11995             "MTCTR   $jump_target\n\t"
11996             "BCTR     \t// TailJump, exception oop: $ex_oop" %}
11997   size(12);
11998   ins_encode %{
11999     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12000     __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
12001     __ mtctr($jump_target$$Register);
12002     __ bctr();
12003   %}
12004   ins_pipe(pipe_class_call);
12005 %}
12006 
12007 // Create exception oop: created by stack-crawling runtime code.
12008 // Created exception is now available to this handler, and is setup
12009 // just prior to jumping to this handler. No code emitted.
12010 instruct CreateException(rarg1RegP ex_oop) %{
12011   match(Set ex_oop (CreateEx));
12012   ins_cost(0);
12013 
12014   format %{ " -- \t// exception oop; no code emitted" %}
12015   size(0);
12016   ins_encode( /*empty*/ );
12017   ins_pipe(pipe_class_default);
12018 %}
12019 
12020 // Rethrow exception: The exception oop will come in the first
12021 // argument position. Then JUMP (not call) to the rethrow stub code.
12022 instruct RethrowException() %{
12023   match(Rethrow);
12024   ins_cost(CALL_COST);
12025 
12026   format %{ "Jmp     rethrow_stub" %}
12027   ins_encode %{
12028     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12029     cbuf.set_insts_mark();
12030     __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
12031   %}
12032   ins_pipe(pipe_class_call);
12033 %}
12034 
12035 // Die now.
12036 instruct ShouldNotReachHere() %{
12037   match(Halt);
12038   ins_cost(CALL_COST);
12039 
12040   format %{ "ShouldNotReachHere" %}
12041   size(4);
12042   ins_encode %{
12043     // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
12044     __ trap_should_not_reach_here();
12045   %}
12046   ins_pipe(pipe_class_default);
12047 %}
12048 
12049 // This name is KNOWN by the ADLC and cannot be changed.  The ADLC
12050 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
12051 // Get a DEF on threadRegP, no costs, no encoding, use
12052 // 'ins_should_rematerialize(true)' to avoid spilling.
12053 instruct tlsLoadP(threadRegP dst) %{
12054   match(Set dst (ThreadLocal));
12055   ins_cost(0);
12056 
12057   ins_should_rematerialize(true);
12058 
12059   format %{ " -- \t// $dst=Thread::current(), empty" %}
12060   size(0);
12061   ins_encode( /*empty*/ );
12062   ins_pipe(pipe_class_empty);
12063 %}
12064 
12065 //---Some PPC specific nodes---------------------------------------------------
12066 
12067 // Stop a group.
12068 instruct endGroup() %{
12069   ins_cost(0);
12070 
12071   ins_is_nop(true);
12072 
12073   format %{ "End Bundle (ori r1, r1, 0)" %}
12074   size(4);
12075   ins_encode %{
12076     // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
12077     __ endgroup();
12078   %}
12079   ins_pipe(pipe_class_default);
12080 %}
12081 
12082 // Nop instructions
12083 
12084 instruct fxNop() %{
12085   ins_cost(0);
12086 
12087   ins_is_nop(true);
12088 
12089   format %{ "fxNop" %}
12090   size(4);
12091   ins_encode %{
12092     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12093     __ nop();
12094   %}
12095   ins_pipe(pipe_class_default);
12096 %}
12097 
12098 instruct fpNop0() %{
12099   ins_cost(0);
12100 
12101   ins_is_nop(true);
12102 
12103   format %{ "fpNop0" %}
12104   size(4);
12105   ins_encode %{
12106     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12107     __ fpnop0();
12108   %}
12109   ins_pipe(pipe_class_default);
12110 %}
12111 
12112 instruct fpNop1() %{
12113   ins_cost(0);
12114 
12115   ins_is_nop(true);
12116 
12117   format %{ "fpNop1" %}
12118   size(4);
12119   ins_encode %{
12120     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12121     __ fpnop1();
12122   %}
12123   ins_pipe(pipe_class_default);
12124 %}
12125 
12126 instruct brNop0() %{
12127   ins_cost(0);
12128   size(4);
12129   format %{ "brNop0" %}
12130   ins_encode %{
12131     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12132     __ brnop0();
12133   %}
12134   ins_is_nop(true);
12135   ins_pipe(pipe_class_default);
12136 %}
12137 
12138 instruct brNop1() %{
12139   ins_cost(0);
12140 
12141   ins_is_nop(true);
12142 
12143   format %{ "brNop1" %}
12144   size(4);
12145   ins_encode %{
12146     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12147     __ brnop1();
12148   %}
12149   ins_pipe(pipe_class_default);
12150 %}
12151 
12152 instruct brNop2() %{
12153   ins_cost(0);
12154 
12155   ins_is_nop(true);
12156 
12157   format %{ "brNop2" %}
12158   size(4);
12159   ins_encode %{
12160     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12161     __ brnop2();
12162   %}
12163   ins_pipe(pipe_class_default);
12164 %}
12165 
12166 //----------PEEPHOLE RULES-----------------------------------------------------
12167 // These must follow all instruction definitions as they use the names
12168 // defined in the instructions definitions.
12169 //
12170 // peepmatch ( root_instr_name [preceeding_instruction]* );
12171 //
12172 // peepconstraint %{
12173 // (instruction_number.operand_name relational_op instruction_number.operand_name
12174 //  [, ...] );
12175 // // instruction numbers are zero-based using left to right order in peepmatch
12176 //
12177 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12178 // // provide an instruction_number.operand_name for each operand that appears
12179 // // in the replacement instruction's match rule
12180 //
12181 // ---------VM FLAGS---------------------------------------------------------
12182 //
12183 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12184 //
12185 // Each peephole rule is given an identifying number starting with zero and
12186 // increasing by one in the order seen by the parser. An individual peephole
12187 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12188 // on the command-line.
12189 //
12190 // ---------CURRENT LIMITATIONS----------------------------------------------
12191 //
12192 // Only match adjacent instructions in same basic block
12193 // Only equality constraints
12194 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12195 // Only one replacement instruction
12196 //
12197 // ---------EXAMPLE----------------------------------------------------------
12198 //
12199 // // pertinent parts of existing instructions in architecture description
12200 // instruct movI(eRegI dst, eRegI src) %{
12201 //   match(Set dst (CopyI src));
12202 // %}
12203 //
12204 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
12205 //   match(Set dst (AddI dst src));
12206 //   effect(KILL cr);
12207 // %}
12208 //
12209 // // Change (inc mov) to lea
12210 // peephole %{
12211 //   // increment preceeded by register-register move
12212 //   peepmatch ( incI_eReg movI );
12213 //   // require that the destination register of the increment
12214 //   // match the destination register of the move
12215 //   peepconstraint ( 0.dst == 1.dst );
12216 //   // construct a replacement instruction that sets
12217 //   // the destination to ( move's source register + one )
12218 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12219 // %}
12220 //
12221 // Implementation no longer uses movX instructions since
12222 // machine-independent system no longer uses CopyX nodes.
12223 //
12224 // peephole %{
12225 //   peepmatch ( incI_eReg movI );
12226 //   peepconstraint ( 0.dst == 1.dst );
12227 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12228 // %}
12229 //
12230 // peephole %{
12231 //   peepmatch ( decI_eReg movI );
12232 //   peepconstraint ( 0.dst == 1.dst );
12233 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12234 // %}
12235 //
12236 // peephole %{
12237 //   peepmatch ( addI_eReg_imm movI );
12238 //   peepconstraint ( 0.dst == 1.dst );
12239 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12240 // %}
12241 //
12242 // peephole %{
12243 //   peepmatch ( addP_eReg_imm movP );
12244 //   peepconstraint ( 0.dst == 1.dst );
12245 //   peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12246 // %}
12247 
12248 // // Change load of spilled value to only a spill
12249 // instruct storeI(memory mem, eRegI src) %{
12250 //   match(Set mem (StoreI mem src));
12251 // %}
12252 //
12253 // instruct loadI(eRegI dst, memory mem) %{
12254 //   match(Set dst (LoadI mem));
12255 // %}
12256 //
12257 peephole %{
12258   peepmatch ( loadI storeI );
12259   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12260   peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12261 %}
12262 
12263 peephole %{
12264   peepmatch ( loadL storeL );
12265   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12266   peepreplace ( storeL( 1.mem 1.mem 1.src ) );
12267 %}
12268 
12269 peephole %{
12270   peepmatch ( loadP storeP );
12271   peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
12272   peepreplace ( storeP( 1.dst 1.dst 1.src ) );
12273 %}
12274 
12275 //----------SMARTSPILL RULES---------------------------------------------------
12276 // These must follow all instruction definitions as they use the names
12277 // defined in the instructions definitions.
--- EOF ---