1 //
2 // Copyright (c) 1998, 2015, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
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20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Header information of the source block.
461 // Method declarations/definitions which are used outside
462 // the ad-scope can conveniently be defined here.
463 //
464 // To keep related declarations/definitions/uses close together,
465 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
466
467 // Must be visible to the DFA in dfa_sparc.cpp
468 extern bool can_branch_register( Node *bol, Node *cmp );
469
470 extern bool use_block_zeroing(Node* count);
471
472 // Macros to extract hi & lo halves from a long pair.
473 // G0 is not part of any long pair, so assert on that.
474 // Prevents accidentally using G1 instead of G0.
475 #define LONG_HI_REG(x) (x)
476 #define LONG_LO_REG(x) (x)
477
478 class CallStubImpl {
479
480 //--------------------------------------------------------------
481 //---< Used for optimization in Compile::Shorten_branches >---
482 //--------------------------------------------------------------
483
484 public:
485 // Size of call trampoline stub.
486 static uint size_call_trampoline() {
487 return 0; // no call trampolines on this platform
488 }
489
490 // number of relocations needed by a call trampoline stub
491 static uint reloc_call_trampoline() {
492 return 0; // no call trampolines on this platform
493 }
494 };
495
496 class HandlerImpl {
497
498 public:
499
500 static int emit_exception_handler(CodeBuffer &cbuf);
501 static int emit_deopt_handler(CodeBuffer& cbuf);
502
503 static uint size_exception_handler() {
504 if (TraceJumps) {
505 return (400); // just a guess
506 }
507 return ( NativeJump::instruction_size ); // sethi;jmp;nop
508 }
509
510 static uint size_deopt_handler() {
511 if (TraceJumps) {
512 return (400); // just a guess
513 }
514 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
515 }
516 };
517
518 %}
519
520 source %{
521 #define __ _masm.
522
523 // tertiary op of a LoadP or StoreP encoding
524 #define REGP_OP true
525
526 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
527 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
528 static Register reg_to_register_object(int register_encoding);
529
530 // Used by the DFA in dfa_sparc.cpp.
531 // Check for being able to use a V9 branch-on-register. Requires a
532 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
533 // extended. Doesn't work following an integer ADD, for example, because of
534 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
535 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
536 // replace them with zero, which could become sign-extension in a different OS
537 // release. There's no obvious reason why an interrupt will ever fill these
538 // bits with non-zero junk (the registers are reloaded with standard LD
539 // instructions which either zero-fill or sign-fill).
540 bool can_branch_register( Node *bol, Node *cmp ) {
541 if( !BranchOnRegister ) return false;
542 #ifdef _LP64
543 if( cmp->Opcode() == Op_CmpP )
544 return true; // No problems with pointer compares
545 #endif
546 if( cmp->Opcode() == Op_CmpL )
547 return true; // No problems with long compares
548
549 if( !SparcV9RegsHiBitsZero ) return false;
550 if( bol->as_Bool()->_test._test != BoolTest::ne &&
551 bol->as_Bool()->_test._test != BoolTest::eq )
552 return false;
553
554 // Check for comparing against a 'safe' value. Any operation which
555 // clears out the high word is safe. Thus, loads and certain shifts
556 // are safe, as are non-negative constants. Any operation which
557 // preserves zero bits in the high word is safe as long as each of its
558 // inputs are safe. Thus, phis and bitwise booleans are safe if their
559 // inputs are safe. At present, the only important case to recognize
560 // seems to be loads. Constants should fold away, and shifts &
561 // logicals can use the 'cc' forms.
562 Node *x = cmp->in(1);
563 if( x->is_Load() ) return true;
564 if( x->is_Phi() ) {
565 for( uint i = 1; i < x->req(); i++ )
566 if( !x->in(i)->is_Load() )
567 return false;
568 return true;
569 }
570 return false;
571 }
572
573 bool use_block_zeroing(Node* count) {
574 // Use BIS for zeroing if count is not constant
575 // or it is >= BlockZeroingLowLimit.
576 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
577 }
578
579 // ****************************************************************************
580
581 // REQUIRED FUNCTIONALITY
582
583 // !!!!! Special hack to get all type of calls to specify the byte offset
584 // from the start of the call to the point where the return address
585 // will point.
586 // The "return address" is the address of the call instruction, plus 8.
587
588 int MachCallStaticJavaNode::ret_addr_offset() {
589 int offset = NativeCall::instruction_size; // call; delay slot
590 if (_method_handle_invoke)
591 offset += 4; // restore SP
592 return offset;
593 }
594
595 int MachCallDynamicJavaNode::ret_addr_offset() {
596 int vtable_index = this->_vtable_index;
597 if (vtable_index < 0) {
598 // must be invalid_vtable_index, not nonvirtual_vtable_index
599 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
600 return (NativeMovConstReg::instruction_size +
601 NativeCall::instruction_size); // sethi; setlo; call; delay slot
602 } else {
603 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
604 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
605 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
606 int klass_load_size;
607 if (UseCompressedClassPointers) {
608 assert(Universe::heap() != NULL, "java heap should be initialized");
609 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
610 } else {
611 klass_load_size = 1*BytesPerInstWord;
612 }
613 if (Assembler::is_simm13(v_off)) {
614 return klass_load_size +
615 (2*BytesPerInstWord + // ld_ptr, ld_ptr
616 NativeCall::instruction_size); // call; delay slot
617 } else {
618 return klass_load_size +
619 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
620 NativeCall::instruction_size); // call; delay slot
621 }
622 }
623 }
624
625 int MachCallRuntimeNode::ret_addr_offset() {
626 #ifdef _LP64
627 if (MacroAssembler::is_far_target(entry_point())) {
628 return NativeFarCall::instruction_size;
629 } else {
630 return NativeCall::instruction_size;
631 }
632 #else
633 return NativeCall::instruction_size; // call; delay slot
634 #endif
635 }
636
637 // Indicate if the safepoint node needs the polling page as an input.
638 // Since Sparc does not have absolute addressing, it does.
639 bool SafePointNode::needs_polling_address_input() {
640 return true;
641 }
642
643 // emit an interrupt that is caught by the debugger (for debugging compiler)
644 void emit_break(CodeBuffer &cbuf) {
645 MacroAssembler _masm(&cbuf);
646 __ breakpoint_trap();
647 }
648
649 #ifndef PRODUCT
650 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
651 st->print("TA");
652 }
653 #endif
654
655 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
656 emit_break(cbuf);
657 }
658
659 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
660 return MachNode::size(ra_);
661 }
662
663 // Traceable jump
664 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
665 MacroAssembler _masm(&cbuf);
666 Register rdest = reg_to_register_object(jump_target);
667 __ JMP(rdest, 0);
668 __ delayed()->nop();
669 }
670
671 // Traceable jump and set exception pc
672 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
673 MacroAssembler _masm(&cbuf);
674 Register rdest = reg_to_register_object(jump_target);
675 __ JMP(rdest, 0);
676 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
677 }
678
679 void emit_nop(CodeBuffer &cbuf) {
680 MacroAssembler _masm(&cbuf);
681 __ nop();
682 }
683
684 void emit_illtrap(CodeBuffer &cbuf) {
685 MacroAssembler _masm(&cbuf);
686 __ illtrap(0);
687 }
688
689
690 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
691 assert(n->rule() != loadUB_rule, "");
692
693 intptr_t offset = 0;
694 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
695 const Node* addr = n->get_base_and_disp(offset, adr_type);
696 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
697 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
698 assert(addr->bottom_type()->isa_oopptr() == atype, "");
699 atype = atype->add_offset(offset);
700 assert(disp32 == offset, "wrong disp32");
701 return atype->_offset;
702 }
703
704
705 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
706 assert(n->rule() != loadUB_rule, "");
707
708 intptr_t offset = 0;
709 Node* addr = n->in(2);
710 assert(addr->bottom_type()->isa_oopptr() == atype, "");
711 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
712 Node* a = addr->in(2/*AddPNode::Address*/);
713 Node* o = addr->in(3/*AddPNode::Offset*/);
714 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
715 atype = a->bottom_type()->is_ptr()->add_offset(offset);
716 assert(atype->isa_oop_ptr(), "still an oop");
717 }
718 offset = atype->is_ptr()->_offset;
719 if (offset != Type::OffsetBot) offset += disp32;
720 return offset;
721 }
722
723 static inline jdouble replicate_immI(int con, int count, int width) {
724 // Load a constant replicated "count" times with width "width"
725 assert(count*width == 8 && width <= 4, "sanity");
726 int bit_width = width * 8;
727 jlong val = con;
728 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
729 for (int i = 0; i < count - 1; i++) {
730 val |= (val << bit_width);
731 }
732 jdouble dval = *((jdouble*) &val); // coerce to double type
733 return dval;
734 }
735
736 static inline jdouble replicate_immF(float con) {
737 // Replicate float con 2 times and pack into vector.
738 int val = *((int*)&con);
739 jlong lval = val;
740 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
741 jdouble dval = *((jdouble*) &lval); // coerce to double type
742 return dval;
743 }
744
745 // Standard Sparc opcode form2 field breakdown
746 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
747 f0 &= (1<<19)-1; // Mask displacement to 19 bits
748 int op = (f30 << 30) |
749 (f29 << 29) |
750 (f25 << 25) |
751 (f22 << 22) |
752 (f20 << 20) |
753 (f19 << 19) |
754 (f0 << 0);
755 cbuf.insts()->emit_int32(op);
756 }
757
758 // Standard Sparc opcode form2 field breakdown
759 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
760 f0 >>= 10; // Drop 10 bits
761 f0 &= (1<<22)-1; // Mask displacement to 22 bits
762 int op = (f30 << 30) |
763 (f25 << 25) |
764 (f22 << 22) |
765 (f0 << 0);
766 cbuf.insts()->emit_int32(op);
767 }
768
769 // Standard Sparc opcode form3 field breakdown
770 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
771 int op = (f30 << 30) |
772 (f25 << 25) |
773 (f19 << 19) |
774 (f14 << 14) |
775 (f5 << 5) |
776 (f0 << 0);
777 cbuf.insts()->emit_int32(op);
778 }
779
780 // Standard Sparc opcode form3 field breakdown
781 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
782 simm13 &= (1<<13)-1; // Mask to 13 bits
783 int op = (f30 << 30) |
784 (f25 << 25) |
785 (f19 << 19) |
786 (f14 << 14) |
787 (1 << 13) | // bit to indicate immediate-mode
788 (simm13<<0);
789 cbuf.insts()->emit_int32(op);
790 }
791
792 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
793 simm10 &= (1<<10)-1; // Mask to 10 bits
794 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
795 }
796
797 #ifdef ASSERT
798 // Helper function for VerifyOops in emit_form3_mem_reg
799 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
800 warning("VerifyOops encountered unexpected instruction:");
801 n->dump(2);
802 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
803 }
804 #endif
805
806
807 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
808 int src1_enc, int disp32, int src2_enc, int dst_enc) {
809
810 #ifdef ASSERT
811 // The following code implements the +VerifyOops feature.
812 // It verifies oop values which are loaded into or stored out of
813 // the current method activation. +VerifyOops complements techniques
814 // like ScavengeALot, because it eagerly inspects oops in transit,
815 // as they enter or leave the stack, as opposed to ScavengeALot,
816 // which inspects oops "at rest", in the stack or heap, at safepoints.
817 // For this reason, +VerifyOops can sometimes detect bugs very close
818 // to their point of creation. It can also serve as a cross-check
819 // on the validity of oop maps, when used toegether with ScavengeALot.
820
821 // It would be good to verify oops at other points, especially
822 // when an oop is used as a base pointer for a load or store.
823 // This is presently difficult, because it is hard to know when
824 // a base address is biased or not. (If we had such information,
825 // it would be easy and useful to make a two-argument version of
826 // verify_oop which unbiases the base, and performs verification.)
827
828 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
829 bool is_verified_oop_base = false;
830 bool is_verified_oop_load = false;
831 bool is_verified_oop_store = false;
832 int tmp_enc = -1;
833 if (VerifyOops && src1_enc != R_SP_enc) {
834 // classify the op, mainly for an assert check
835 int st_op = 0, ld_op = 0;
836 switch (primary) {
837 case Assembler::stb_op3: st_op = Op_StoreB; break;
838 case Assembler::sth_op3: st_op = Op_StoreC; break;
839 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
840 case Assembler::stw_op3: st_op = Op_StoreI; break;
841 case Assembler::std_op3: st_op = Op_StoreL; break;
842 case Assembler::stf_op3: st_op = Op_StoreF; break;
843 case Assembler::stdf_op3: st_op = Op_StoreD; break;
844
845 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
846 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
847 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
848 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
849 case Assembler::ldx_op3: // may become LoadP or stay LoadI
850 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
851 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
852 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
853 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
854 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
855 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
856
857 default: ShouldNotReachHere();
858 }
859 if (tertiary == REGP_OP) {
860 if (st_op == Op_StoreI) st_op = Op_StoreP;
861 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
862 else ShouldNotReachHere();
863 if (st_op) {
864 // a store
865 // inputs are (0:control, 1:memory, 2:address, 3:value)
866 Node* n2 = n->in(3);
867 if (n2 != NULL) {
868 const Type* t = n2->bottom_type();
869 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
870 }
871 } else {
872 // a load
873 const Type* t = n->bottom_type();
874 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
875 }
876 }
877
878 if (ld_op) {
879 // a Load
880 // inputs are (0:control, 1:memory, 2:address)
881 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
882 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
883 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
884 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
885 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
886 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
887 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
888 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
889 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
890 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
891 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
892 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
893 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
894 !(n->rule() == loadUB_rule)) {
895 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
896 }
897 } else if (st_op) {
898 // a Store
899 // inputs are (0:control, 1:memory, 2:address, 3:value)
900 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
901 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
902 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
903 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
904 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
905 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
906 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
907 verify_oops_warning(n, n->ideal_Opcode(), st_op);
908 }
909 }
910
911 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
912 Node* addr = n->in(2);
913 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
914 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
915 if (atype != NULL) {
916 intptr_t offset = get_offset_from_base(n, atype, disp32);
917 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
918 if (offset != offset_2) {
919 get_offset_from_base(n, atype, disp32);
920 get_offset_from_base_2(n, atype, disp32);
921 }
922 assert(offset == offset_2, "different offsets");
923 if (offset == disp32) {
924 // we now know that src1 is a true oop pointer
925 is_verified_oop_base = true;
926 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
927 if( primary == Assembler::ldd_op3 ) {
928 is_verified_oop_base = false; // Cannot 'ldd' into O7
929 } else {
930 tmp_enc = dst_enc;
931 dst_enc = R_O7_enc; // Load into O7; preserve source oop
932 assert(src1_enc != dst_enc, "");
933 }
934 }
935 }
936 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
937 || offset == oopDesc::mark_offset_in_bytes())) {
938 // loading the mark should not be allowed either, but
939 // we don't check this since it conflicts with InlineObjectHash
940 // usage of LoadINode to get the mark. We could keep the
941 // check if we create a new LoadMarkNode
942 // but do not verify the object before its header is initialized
943 ShouldNotReachHere();
944 }
945 }
946 }
947 }
948 }
949 #endif
950
951 uint instr;
952 instr = (Assembler::ldst_op << 30)
953 | (dst_enc << 25)
954 | (primary << 19)
955 | (src1_enc << 14);
956
957 uint index = src2_enc;
958 int disp = disp32;
959
960 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
961 disp += STACK_BIAS;
962 // Quick fix for JDK-8029668: check that stack offset fits, bailout if not
963 if (!Assembler::is_simm13(disp)) {
964 ra->C->record_method_not_compilable("unable to handle large constant offsets");
965 return;
966 }
967 }
968
969 // We should have a compiler bailout here rather than a guarantee.
970 // Better yet would be some mechanism to handle variable-size matches correctly.
971 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
972
973 if( disp == 0 ) {
974 // use reg-reg form
975 // bit 13 is already zero
976 instr |= index;
977 } else {
978 // use reg-imm form
979 instr |= 0x00002000; // set bit 13 to one
980 instr |= disp & 0x1FFF;
981 }
982
983 cbuf.insts()->emit_int32(instr);
984
985 #ifdef ASSERT
986 {
987 MacroAssembler _masm(&cbuf);
988 if (is_verified_oop_base) {
989 __ verify_oop(reg_to_register_object(src1_enc));
990 }
991 if (is_verified_oop_store) {
992 __ verify_oop(reg_to_register_object(dst_enc));
993 }
994 if (tmp_enc != -1) {
995 __ mov(O7, reg_to_register_object(tmp_enc));
996 }
997 if (is_verified_oop_load) {
998 __ verify_oop(reg_to_register_object(dst_enc));
999 }
1000 }
1001 #endif
1002 }
1003
1004 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
1005 // The method which records debug information at every safepoint
1006 // expects the call to be the first instruction in the snippet as
1007 // it creates a PcDesc structure which tracks the offset of a call
1008 // from the start of the codeBlob. This offset is computed as
1009 // code_end() - code_begin() of the code which has been emitted
1010 // so far.
1011 // In this particular case we have skirted around the problem by
1012 // putting the "mov" instruction in the delay slot but the problem
1013 // may bite us again at some other point and a cleaner/generic
1014 // solution using relocations would be needed.
1015 MacroAssembler _masm(&cbuf);
1016 __ set_inst_mark();
1017
1018 // We flush the current window just so that there is a valid stack copy
1019 // the fact that the current window becomes active again instantly is
1020 // not a problem there is nothing live in it.
1021
1022 #ifdef ASSERT
1023 int startpos = __ offset();
1024 #endif /* ASSERT */
1025
1026 __ call((address)entry_point, rtype);
1027
1028 if (preserve_g2) __ delayed()->mov(G2, L7);
1029 else __ delayed()->nop();
1030
1031 if (preserve_g2) __ mov(L7, G2);
1032
1033 #ifdef ASSERT
1034 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
1035 #ifdef _LP64
1036 // Trash argument dump slots.
1037 __ set(0xb0b8ac0db0b8ac0d, G1);
1038 __ mov(G1, G5);
1039 __ stx(G1, SP, STACK_BIAS + 0x80);
1040 __ stx(G1, SP, STACK_BIAS + 0x88);
1041 __ stx(G1, SP, STACK_BIAS + 0x90);
1042 __ stx(G1, SP, STACK_BIAS + 0x98);
1043 __ stx(G1, SP, STACK_BIAS + 0xA0);
1044 __ stx(G1, SP, STACK_BIAS + 0xA8);
1045 #else // _LP64
1046 // this is also a native call, so smash the first 7 stack locations,
1047 // and the various registers
1048
1049 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1050 // while [SP+0x44..0x58] are the argument dump slots.
1051 __ set((intptr_t)0xbaadf00d, G1);
1052 __ mov(G1, G5);
1053 __ sllx(G1, 32, G1);
1054 __ or3(G1, G5, G1);
1055 __ mov(G1, G5);
1056 __ stx(G1, SP, 0x40);
1057 __ stx(G1, SP, 0x48);
1058 __ stx(G1, SP, 0x50);
1059 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1060 #endif // _LP64
1061 }
1062 #endif /*ASSERT*/
1063 }
1064
1065 //=============================================================================
1066 // REQUIRED FUNCTIONALITY for encoding
1067 void emit_lo(CodeBuffer &cbuf, int val) { }
1068 void emit_hi(CodeBuffer &cbuf, int val) { }
1069
1070
1071 //=============================================================================
1072 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1073
1074 int Compile::ConstantTable::calculate_table_base_offset() const {
1075 if (UseRDPCForConstantTableBase) {
1076 // The table base offset might be less but then it fits into
1077 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1078 return Assembler::min_simm13();
1079 } else {
1080 int offset = -(size() / 2);
1081 if (!Assembler::is_simm13(offset)) {
1082 offset = Assembler::min_simm13();
1083 }
1084 return offset;
1085 }
1086 }
1087
1088 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1089 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1090 ShouldNotReachHere();
1091 }
1092
1093 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1094 Compile* C = ra_->C;
1095 Compile::ConstantTable& constant_table = C->constant_table();
1096 MacroAssembler _masm(&cbuf);
1097
1098 Register r = as_Register(ra_->get_encode(this));
1099 CodeSection* consts_section = __ code()->consts();
1100 int consts_size = consts_section->align_at_start(consts_section->size());
1101 assert(constant_table.size() == consts_size, "must be: %d == %d", constant_table.size(), consts_size);
1102
1103 if (UseRDPCForConstantTableBase) {
1104 // For the following RDPC logic to work correctly the consts
1105 // section must be allocated right before the insts section. This
1106 // assert checks for that. The layout and the SECT_* constants
1107 // are defined in src/share/vm/asm/codeBuffer.hpp.
1108 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1109 int insts_offset = __ offset();
1110
1111 // Layout:
1112 //
1113 // |----------- consts section ------------|----------- insts section -----------...
1114 // |------ constant table -----|- padding -|------------------x----
1115 // \ current PC (RDPC instruction)
1116 // |<------------- consts_size ----------->|<- insts_offset ->|
1117 // \ table base
1118 // The table base offset is later added to the load displacement
1119 // so it has to be negative.
1120 int table_base_offset = -(consts_size + insts_offset);
1121 int disp;
1122
1123 // If the displacement from the current PC to the constant table
1124 // base fits into simm13 we set the constant table base to the
1125 // current PC.
1126 if (Assembler::is_simm13(table_base_offset)) {
1127 constant_table.set_table_base_offset(table_base_offset);
1128 disp = 0;
1129 } else {
1130 // Otherwise we set the constant table base offset to the
1131 // maximum negative displacement of load instructions to keep
1132 // the disp as small as possible:
1133 //
1134 // |<------------- consts_size ----------->|<- insts_offset ->|
1135 // |<--------- min_simm13 --------->|<-------- disp --------->|
1136 // \ table base
1137 table_base_offset = Assembler::min_simm13();
1138 constant_table.set_table_base_offset(table_base_offset);
1139 disp = (consts_size + insts_offset) + table_base_offset;
1140 }
1141
1142 __ rdpc(r);
1143
1144 if (disp != 0) {
1145 assert(r != O7, "need temporary");
1146 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1147 }
1148 }
1149 else {
1150 // Materialize the constant table base.
1151 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1152 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1153 AddressLiteral base(baseaddr, rspec);
1154 __ set(base, r);
1155 }
1156 }
1157
1158 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1159 if (UseRDPCForConstantTableBase) {
1160 // This is really the worst case but generally it's only 1 instruction.
1161 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1162 } else {
1163 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1164 }
1165 }
1166
1167 #ifndef PRODUCT
1168 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1169 char reg[128];
1170 ra_->dump_register(this, reg);
1171 if (UseRDPCForConstantTableBase) {
1172 st->print("RDPC %s\t! constant table base", reg);
1173 } else {
1174 st->print("SET &constanttable,%s\t! constant table base", reg);
1175 }
1176 }
1177 #endif
1178
1179
1180 //=============================================================================
1181
1182 #ifndef PRODUCT
1183 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1184 Compile* C = ra_->C;
1185
1186 for (int i = 0; i < OptoPrologueNops; i++) {
1187 st->print_cr("NOP"); st->print("\t");
1188 }
1189
1190 if( VerifyThread ) {
1191 st->print_cr("Verify_Thread"); st->print("\t");
1192 }
1193
1194 size_t framesize = C->frame_size_in_bytes();
1195 int bangsize = C->bang_size_in_bytes();
1196
1197 // Calls to C2R adapters often do not accept exceptional returns.
1198 // We require that their callers must bang for them. But be careful, because
1199 // some VM calls (such as call site linkage) can use several kilobytes of
1200 // stack. But the stack safety zone should account for that.
1201 // See bugs 4446381, 4468289, 4497237.
1202 if (C->need_stack_bang(bangsize)) {
1203 st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t");
1204 }
1205
1206 if (Assembler::is_simm13(-framesize)) {
1207 st->print ("SAVE R_SP,-" SIZE_FORMAT ",R_SP",framesize);
1208 } else {
1209 st->print_cr("SETHI R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1210 st->print_cr("ADD R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1211 st->print ("SAVE R_SP,R_G3,R_SP");
1212 }
1213
1214 }
1215 #endif
1216
1217 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1218 Compile* C = ra_->C;
1219 MacroAssembler _masm(&cbuf);
1220
1221 for (int i = 0; i < OptoPrologueNops; i++) {
1222 __ nop();
1223 }
1224
1225 __ verify_thread();
1226
1227 size_t framesize = C->frame_size_in_bytes();
1228 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1229 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1230 int bangsize = C->bang_size_in_bytes();
1231
1232 // Calls to C2R adapters often do not accept exceptional returns.
1233 // We require that their callers must bang for them. But be careful, because
1234 // some VM calls (such as call site linkage) can use several kilobytes of
1235 // stack. But the stack safety zone should account for that.
1236 // See bugs 4446381, 4468289, 4497237.
1237 if (C->need_stack_bang(bangsize)) {
1238 __ generate_stack_overflow_check(bangsize);
1239 }
1240
1241 if (Assembler::is_simm13(-framesize)) {
1242 __ save(SP, -framesize, SP);
1243 } else {
1244 __ sethi(-framesize & ~0x3ff, G3);
1245 __ add(G3, -framesize & 0x3ff, G3);
1246 __ save(SP, G3, SP);
1247 }
1248 C->set_frame_complete( __ offset() );
1249
1250 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1251 // NOTE: We set the table base offset here because users might be
1252 // emitted before MachConstantBaseNode.
1253 Compile::ConstantTable& constant_table = C->constant_table();
1254 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1255 }
1256 }
1257
1258 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1259 return MachNode::size(ra_);
1260 }
1261
1262 int MachPrologNode::reloc() const {
1263 return 10; // a large enough number
1264 }
1265
1266 //=============================================================================
1267 #ifndef PRODUCT
1268 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1269 Compile* C = ra_->C;
1270
1271 if(do_polling() && ra_->C->is_method_compilation()) {
1272 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1273 #ifdef _LP64
1274 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1275 #else
1276 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1277 #endif
1278 }
1279
1280 if(do_polling()) {
1281 if (UseCBCond && !ra_->C->is_method_compilation()) {
1282 st->print("NOP\n\t");
1283 }
1284 st->print("RET\n\t");
1285 }
1286
1287 st->print("RESTORE");
1288 }
1289 #endif
1290
1291 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1292 MacroAssembler _masm(&cbuf);
1293 Compile* C = ra_->C;
1294
1295 __ verify_thread();
1296
1297 // If this does safepoint polling, then do it here
1298 if(do_polling() && ra_->C->is_method_compilation()) {
1299 AddressLiteral polling_page(os::get_polling_page());
1300 __ sethi(polling_page, L0);
1301 __ relocate(relocInfo::poll_return_type);
1302 __ ld_ptr(L0, 0, G0);
1303 }
1304
1305 // If this is a return, then stuff the restore in the delay slot
1306 if(do_polling()) {
1307 if (UseCBCond && !ra_->C->is_method_compilation()) {
1308 // Insert extra padding for the case when the epilogue is preceded by
1309 // a cbcond jump, which can't be followed by a CTI instruction
1310 __ nop();
1311 }
1312 __ ret();
1313 __ delayed()->restore();
1314 } else {
1315 __ restore();
1316 }
1317 }
1318
1319 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1320 return MachNode::size(ra_);
1321 }
1322
1323 int MachEpilogNode::reloc() const {
1324 return 16; // a large enough number
1325 }
1326
1327 const Pipeline * MachEpilogNode::pipeline() const {
1328 return MachNode::pipeline_class();
1329 }
1330
1331 int MachEpilogNode::safepoint_offset() const {
1332 assert( do_polling(), "no return for this epilog node");
1333 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1334 }
1335
1336 //=============================================================================
1337
1338 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1339 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1340 static enum RC rc_class( OptoReg::Name reg ) {
1341 if( !OptoReg::is_valid(reg) ) return rc_bad;
1342 if (OptoReg::is_stack(reg)) return rc_stack;
1343 VMReg r = OptoReg::as_VMReg(reg);
1344 if (r->is_Register()) return rc_int;
1345 assert(r->is_FloatRegister(), "must be");
1346 return rc_float;
1347 }
1348
1349 static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1350 if (cbuf) {
1351 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1352 }
1353 #ifndef PRODUCT
1354 else if (!do_size) {
1355 if (size != 0) st->print("\n\t");
1356 if (is_load) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1357 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1358 }
1359 #endif
1360 return size+4;
1361 }
1362
1363 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1364 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1365 #ifndef PRODUCT
1366 else if( !do_size ) {
1367 if( size != 0 ) st->print("\n\t");
1368 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1369 }
1370 #endif
1371 return size+4;
1372 }
1373
1374 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1375 PhaseRegAlloc *ra_,
1376 bool do_size,
1377 outputStream* st ) const {
1378 // Get registers to move
1379 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1380 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1381 OptoReg::Name dst_second = ra_->get_reg_second(this );
1382 OptoReg::Name dst_first = ra_->get_reg_first(this );
1383
1384 enum RC src_second_rc = rc_class(src_second);
1385 enum RC src_first_rc = rc_class(src_first);
1386 enum RC dst_second_rc = rc_class(dst_second);
1387 enum RC dst_first_rc = rc_class(dst_first);
1388
1389 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1390
1391 // Generate spill code!
1392 int size = 0;
1393
1394 if( src_first == dst_first && src_second == dst_second )
1395 return size; // Self copy, no move
1396
1397 // --------------------------------------
1398 // Check for mem-mem move. Load into unused float registers and fall into
1399 // the float-store case.
1400 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1401 int offset = ra_->reg2offset(src_first);
1402 // Further check for aligned-adjacent pair, so we can use a double load
1403 if( (src_first&1)==0 && src_first+1 == src_second ) {
1404 src_second = OptoReg::Name(R_F31_num);
1405 src_second_rc = rc_float;
1406 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1407 } else {
1408 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1409 }
1410 src_first = OptoReg::Name(R_F30_num);
1411 src_first_rc = rc_float;
1412 }
1413
1414 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1415 int offset = ra_->reg2offset(src_second);
1416 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1417 src_second = OptoReg::Name(R_F31_num);
1418 src_second_rc = rc_float;
1419 }
1420
1421 // --------------------------------------
1422 // Check for float->int copy; requires a trip through memory
1423 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1424 int offset = frame::register_save_words*wordSize;
1425 if (cbuf) {
1426 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1427 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1428 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1429 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1430 }
1431 #ifndef PRODUCT
1432 else if (!do_size) {
1433 if (size != 0) st->print("\n\t");
1434 st->print( "SUB R_SP,16,R_SP\n");
1435 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1436 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1437 st->print("\tADD R_SP,16,R_SP\n");
1438 }
1439 #endif
1440 size += 16;
1441 }
1442
1443 // Check for float->int copy on T4
1444 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1445 // Further check for aligned-adjacent pair, so we can use a double move
1446 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1447 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1448 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1449 }
1450 // Check for int->float copy on T4
1451 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1452 // Further check for aligned-adjacent pair, so we can use a double move
1453 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1454 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1455 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1456 }
1457
1458 // --------------------------------------
1459 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1460 // In such cases, I have to do the big-endian swap. For aligned targets, the
1461 // hardware does the flop for me. Doubles are always aligned, so no problem
1462 // there. Misaligned sources only come from native-long-returns (handled
1463 // special below).
1464 #ifndef _LP64
1465 if( src_first_rc == rc_int && // source is already big-endian
1466 src_second_rc != rc_bad && // 64-bit move
1467 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1468 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1469 // Do the big-endian flop.
1470 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1471 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1472 }
1473 #endif
1474
1475 // --------------------------------------
1476 // Check for integer reg-reg copy
1477 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1478 #ifndef _LP64
1479 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1480 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1481 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1482 // operand contains the least significant word of the 64-bit value and vice versa.
1483 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1484 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1485 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1486 if( cbuf ) {
1487 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1488 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1489 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1490 #ifndef PRODUCT
1491 } else if( !do_size ) {
1492 if( size != 0 ) st->print("\n\t");
1493 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1494 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1495 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1496 #endif
1497 }
1498 return size+12;
1499 }
1500 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1501 // returning a long value in I0/I1
1502 // a SpillCopy must be able to target a return instruction's reg_class
1503 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1504 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1505 // operand contains the least significant word of the 64-bit value and vice versa.
1506 OptoReg::Name tdest = dst_first;
1507
1508 if (src_first == dst_first) {
1509 tdest = OptoReg::Name(R_O7_num);
1510 size += 4;
1511 }
1512
1513 if( cbuf ) {
1514 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1515 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1516 // ShrL_reg_imm6
1517 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1518 // ShrR_reg_imm6 src, 0, dst
1519 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1520 if (tdest != dst_first) {
1521 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1522 }
1523 }
1524 #ifndef PRODUCT
1525 else if( !do_size ) {
1526 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1527 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1528 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1529 if (tdest != dst_first) {
1530 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1531 }
1532 }
1533 #endif // PRODUCT
1534 return size+8;
1535 }
1536 #endif // !_LP64
1537 // Else normal reg-reg copy
1538 assert( src_second != dst_first, "smashed second before evacuating it" );
1539 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1540 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1541 // This moves an aligned adjacent pair.
1542 // See if we are done.
1543 if( src_first+1 == src_second && dst_first+1 == dst_second )
1544 return size;
1545 }
1546
1547 // Check for integer store
1548 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1549 int offset = ra_->reg2offset(dst_first);
1550 // Further check for aligned-adjacent pair, so we can use a double store
1551 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1552 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1553 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1554 }
1555
1556 // Check for integer load
1557 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1558 int offset = ra_->reg2offset(src_first);
1559 // Further check for aligned-adjacent pair, so we can use a double load
1560 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1561 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1562 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1563 }
1564
1565 // Check for float reg-reg copy
1566 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1567 // Further check for aligned-adjacent pair, so we can use a double move
1568 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1569 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1570 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1571 }
1572
1573 // Check for float store
1574 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1575 int offset = ra_->reg2offset(dst_first);
1576 // Further check for aligned-adjacent pair, so we can use a double store
1577 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1578 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1579 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1580 }
1581
1582 // Check for float load
1583 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1584 int offset = ra_->reg2offset(src_first);
1585 // Further check for aligned-adjacent pair, so we can use a double load
1586 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1587 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1588 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1589 }
1590
1591 // --------------------------------------------------------------------
1592 // Check for hi bits still needing moving. Only happens for misaligned
1593 // arguments to native calls.
1594 if( src_second == dst_second )
1595 return size; // Self copy; no move
1596 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1597
1598 #ifndef _LP64
1599 // In the LP64 build, all registers can be moved as aligned/adjacent
1600 // pairs, so there's never any need to move the high bits separately.
1601 // The 32-bit builds have to deal with the 32-bit ABI which can force
1602 // all sorts of silly alignment problems.
1603
1604 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1605 // 32-bits of a 64-bit register, but are needed in low bits of another
1606 // register (else it's a hi-bits-to-hi-bits copy which should have
1607 // happened already as part of a 64-bit move)
1608 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1609 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1610 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1611 // Shift src_second down to dst_second's low bits.
1612 if( cbuf ) {
1613 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1614 #ifndef PRODUCT
1615 } else if( !do_size ) {
1616 if( size != 0 ) st->print("\n\t");
1617 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1618 #endif
1619 }
1620 return size+4;
1621 }
1622
1623 // Check for high word integer store. Must down-shift the hi bits
1624 // into a temp register, then fall into the case of storing int bits.
1625 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1626 // Shift src_second down to dst_second's low bits.
1627 if( cbuf ) {
1628 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1629 #ifndef PRODUCT
1630 } else if( !do_size ) {
1631 if( size != 0 ) st->print("\n\t");
1632 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1633 #endif
1634 }
1635 size+=4;
1636 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1637 }
1638
1639 // Check for high word integer load
1640 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1641 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1642
1643 // Check for high word integer store
1644 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1645 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1646
1647 // Check for high word float store
1648 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1649 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1650
1651 #endif // !_LP64
1652
1653 Unimplemented();
1654 }
1655
1656 #ifndef PRODUCT
1657 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1658 implementation( NULL, ra_, false, st );
1659 }
1660 #endif
1661
1662 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1663 implementation( &cbuf, ra_, false, NULL );
1664 }
1665
1666 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1667 return implementation( NULL, ra_, true, NULL );
1668 }
1669
1670 //=============================================================================
1671 #ifndef PRODUCT
1672 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1673 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1674 }
1675 #endif
1676
1677 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1678 MacroAssembler _masm(&cbuf);
1679 for(int i = 0; i < _count; i += 1) {
1680 __ nop();
1681 }
1682 }
1683
1684 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1685 return 4 * _count;
1686 }
1687
1688
1689 //=============================================================================
1690 #ifndef PRODUCT
1691 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1692 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1693 int reg = ra_->get_reg_first(this);
1694 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1695 }
1696 #endif
1697
1698 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1699 MacroAssembler _masm(&cbuf);
1700 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1701 int reg = ra_->get_encode(this);
1702
1703 if (Assembler::is_simm13(offset)) {
1704 __ add(SP, offset, reg_to_register_object(reg));
1705 } else {
1706 __ set(offset, O7);
1707 __ add(SP, O7, reg_to_register_object(reg));
1708 }
1709 }
1710
1711 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1712 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1713 assert(ra_ == ra_->C->regalloc(), "sanity");
1714 return ra_->C->scratch_emit_size(this);
1715 }
1716
1717 //=============================================================================
1718 #ifndef PRODUCT
1719 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1720 st->print_cr("\nUEP:");
1721 #ifdef _LP64
1722 if (UseCompressedClassPointers) {
1723 assert(Universe::heap() != NULL, "java heap should be initialized");
1724 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1725 if (Universe::narrow_klass_base() != 0) {
1726 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base");
1727 if (Universe::narrow_klass_shift() != 0) {
1728 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1729 }
1730 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1731 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base");
1732 } else {
1733 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1734 }
1735 } else {
1736 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1737 }
1738 st->print_cr("\tCMP R_G5,R_G3" );
1739 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1740 #else // _LP64
1741 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1742 st->print_cr("\tCMP R_G5,R_G3" );
1743 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1744 #endif // _LP64
1745 }
1746 #endif
1747
1748 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1749 MacroAssembler _masm(&cbuf);
1750 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1751 Register temp_reg = G3;
1752 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1753
1754 // Load klass from receiver
1755 __ load_klass(O0, temp_reg);
1756 // Compare against expected klass
1757 __ cmp(temp_reg, G5_ic_reg);
1758 // Branch to miss code, checks xcc or icc depending
1759 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1760 }
1761
1762 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1763 return MachNode::size(ra_);
1764 }
1765
1766
1767 //=============================================================================
1768
1769
1770 // Emit exception handler code.
1771 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
1772 Register temp_reg = G3;
1773 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1774 MacroAssembler _masm(&cbuf);
1775
1776 address base = __ start_a_stub(size_exception_handler());
1777 if (base == NULL) {
1778 ciEnv::current()->record_failure("CodeCache is full");
1779 return 0; // CodeBuffer::expand failed
1780 }
1781
1782 int offset = __ offset();
1783
1784 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1785 __ delayed()->nop();
1786
1787 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1788
1789 __ end_a_stub();
1790
1791 return offset;
1792 }
1793
1794 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1795 // Can't use any of the current frame's registers as we may have deopted
1796 // at a poll and everything (including G3) can be live.
1797 Register temp_reg = L0;
1798 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1799 MacroAssembler _masm(&cbuf);
1800
1801 address base = __ start_a_stub(size_deopt_handler());
1802 if (base == NULL) {
1803 ciEnv::current()->record_failure("CodeCache is full");
1804 return 0; // CodeBuffer::expand failed
1805 }
1806
1807 int offset = __ offset();
1808 __ save_frame(0);
1809 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1810 __ delayed()->restore();
1811
1812 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1813
1814 __ end_a_stub();
1815 return offset;
1816
1817 }
1818
1819 // Given a register encoding, produce a Integer Register object
1820 static Register reg_to_register_object(int register_encoding) {
1821 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1822 return as_Register(register_encoding);
1823 }
1824
1825 // Given a register encoding, produce a single-precision Float Register object
1826 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1827 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1828 return as_SingleFloatRegister(register_encoding);
1829 }
1830
1831 // Given a register encoding, produce a double-precision Float Register object
1832 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1833 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1834 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1835 return as_DoubleFloatRegister(register_encoding);
1836 }
1837
1838 const bool Matcher::match_rule_supported(int opcode) {
1839 if (!has_match_rule(opcode))
1840 return false;
1841
1842 switch (opcode) {
1843 case Op_CountLeadingZerosI:
1844 case Op_CountLeadingZerosL:
1845 case Op_CountTrailingZerosI:
1846 case Op_CountTrailingZerosL:
1847 case Op_PopCountI:
1848 case Op_PopCountL:
1849 if (!UsePopCountInstruction)
1850 return false;
1851 case Op_CompareAndSwapL:
1852 #ifdef _LP64
1853 case Op_CompareAndSwapP:
1854 #endif
1855 if (!VM_Version::supports_cx8())
1856 return false;
1857 break;
1858 }
1859
1860 return true; // Per default match rules are supported.
1861 }
1862
1863 const int Matcher::float_pressure(int default_pressure_threshold) {
1864 return default_pressure_threshold;
1865 }
1866
1867 int Matcher::regnum_to_fpu_offset(int regnum) {
1868 return regnum - 32; // The FP registers are in the second chunk
1869 }
1870
1871 #ifdef ASSERT
1872 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1873 #endif
1874
1875 // Vector width in bytes
1876 const int Matcher::vector_width_in_bytes(BasicType bt) {
1877 assert(MaxVectorSize == 8, "");
1878 return 8;
1879 }
1880
1881 // Vector ideal reg
1882 const int Matcher::vector_ideal_reg(int size) {
1883 assert(MaxVectorSize == 8, "");
1884 return Op_RegD;
1885 }
1886
1887 const int Matcher::vector_shift_count_ideal_reg(int size) {
1888 fatal("vector shift is not supported");
1889 return Node::NotAMachineReg;
1890 }
1891
1892 // Limits on vector size (number of elements) loaded into vector.
1893 const int Matcher::max_vector_size(const BasicType bt) {
1894 assert(is_java_primitive(bt), "only primitive type vectors");
1895 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1896 }
1897
1898 const int Matcher::min_vector_size(const BasicType bt) {
1899 return max_vector_size(bt); // Same as max.
1900 }
1901
1902 // SPARC doesn't support misaligned vectors store/load.
1903 const bool Matcher::misaligned_vectors_ok() {
1904 return false;
1905 }
1906
1907 // Current (2013) SPARC platforms need to read original key
1908 // to construct decryption expanded key
1909 const bool Matcher::pass_original_key_for_aes() {
1910 return true;
1911 }
1912
1913 // USII supports fxtof through the whole range of number, USIII doesn't
1914 const bool Matcher::convL2FSupported(void) {
1915 return VM_Version::has_fast_fxtof();
1916 }
1917
1918 // Is this branch offset short enough that a short branch can be used?
1919 //
1920 // NOTE: If the platform does not provide any short branch variants, then
1921 // this method should return false for offset 0.
1922 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1923 // The passed offset is relative to address of the branch.
1924 // Don't need to adjust the offset.
1925 return UseCBCond && Assembler::is_simm12(offset);
1926 }
1927
1928 const bool Matcher::isSimpleConstant64(jlong value) {
1929 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1930 // Depends on optimizations in MacroAssembler::setx.
1931 int hi = (int)(value >> 32);
1932 int lo = (int)(value & ~0);
1933 return (hi == 0) || (hi == -1) || (lo == 0);
1934 }
1935
1936 // No scaling for the parameter the ClearArray node.
1937 const bool Matcher::init_array_count_is_in_bytes = true;
1938
1939 // Threshold size for cleararray.
1940 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1941
1942 // No additional cost for CMOVL.
1943 const int Matcher::long_cmove_cost() { return 0; }
1944
1945 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1946 const int Matcher::float_cmove_cost() {
1947 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1948 }
1949
1950 // Does the CPU require late expand (see block.cpp for description of late expand)?
1951 const bool Matcher::require_postalloc_expand = false;
1952
1953 // Should the Matcher clone shifts on addressing modes, expecting them to
1954 // be subsumed into complex addressing expressions or compute them into
1955 // registers? True for Intel but false for most RISCs
1956 const bool Matcher::clone_shift_expressions = false;
1957
1958 // Do we need to mask the count passed to shift instructions or does
1959 // the cpu only look at the lower 5/6 bits anyway?
1960 const bool Matcher::need_masked_shift_count = false;
1961
1962 bool Matcher::narrow_oop_use_complex_address() {
1963 NOT_LP64(ShouldNotCallThis());
1964 assert(UseCompressedOops, "only for compressed oops code");
1965 return false;
1966 }
1967
1968 bool Matcher::narrow_klass_use_complex_address() {
1969 NOT_LP64(ShouldNotCallThis());
1970 assert(UseCompressedClassPointers, "only for compressed klass code");
1971 return false;
1972 }
1973
1974 // Is it better to copy float constants, or load them directly from memory?
1975 // Intel can load a float constant from a direct address, requiring no
1976 // extra registers. Most RISCs will have to materialize an address into a
1977 // register first, so they would do better to copy the constant from stack.
1978 const bool Matcher::rematerialize_float_constants = false;
1979
1980 // If CPU can load and store mis-aligned doubles directly then no fixup is
1981 // needed. Else we split the double into 2 integer pieces and move it
1982 // piece-by-piece. Only happens when passing doubles into C code as the
1983 // Java calling convention forces doubles to be aligned.
1984 #ifdef _LP64
1985 const bool Matcher::misaligned_doubles_ok = true;
1986 #else
1987 const bool Matcher::misaligned_doubles_ok = false;
1988 #endif
1989
1990 // No-op on SPARC.
1991 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1992 }
1993
1994 // Advertise here if the CPU requires explicit rounding operations
1995 // to implement the UseStrictFP mode.
1996 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1997
1998 // Are floats converted to double when stored to stack during deoptimization?
1999 // Sparc does not handle callee-save floats.
2000 bool Matcher::float_in_double() { return false; }
2001
2002 // Do ints take an entire long register or just half?
2003 // Note that we if-def off of _LP64.
2004 // The relevant question is how the int is callee-saved. In _LP64
2005 // the whole long is written but de-opt'ing will have to extract
2006 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
2007 #ifdef _LP64
2008 const bool Matcher::int_in_long = true;
2009 #else
2010 const bool Matcher::int_in_long = false;
2011 #endif
2012
2013 // Return whether or not this register is ever used as an argument. This
2014 // function is used on startup to build the trampoline stubs in generateOptoStub.
2015 // Registers not mentioned will be killed by the VM call in the trampoline, and
2016 // arguments in those registers not be available to the callee.
2017 bool Matcher::can_be_java_arg( int reg ) {
2018 // Standard sparc 6 args in registers
2019 if( reg == R_I0_num ||
2020 reg == R_I1_num ||
2021 reg == R_I2_num ||
2022 reg == R_I3_num ||
2023 reg == R_I4_num ||
2024 reg == R_I5_num ) return true;
2025 #ifdef _LP64
2026 // 64-bit builds can pass 64-bit pointers and longs in
2027 // the high I registers
2028 if( reg == R_I0H_num ||
2029 reg == R_I1H_num ||
2030 reg == R_I2H_num ||
2031 reg == R_I3H_num ||
2032 reg == R_I4H_num ||
2033 reg == R_I5H_num ) return true;
2034
2035 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
2036 return true;
2037 }
2038
2039 #else
2040 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
2041 // Longs cannot be passed in O regs, because O regs become I regs
2042 // after a 'save' and I regs get their high bits chopped off on
2043 // interrupt.
2044 if( reg == R_G1H_num || reg == R_G1_num ) return true;
2045 if( reg == R_G4H_num || reg == R_G4_num ) return true;
2046 #endif
2047 // A few float args in registers
2048 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
2049
2050 return false;
2051 }
2052
2053 bool Matcher::is_spillable_arg( int reg ) {
2054 return can_be_java_arg(reg);
2055 }
2056
2057 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
2058 // Use hardware SDIVX instruction when it is
2059 // faster than a code which use multiply.
2060 return VM_Version::has_fast_idiv();
2061 }
2062
2063 // Register for DIVI projection of divmodI
2064 RegMask Matcher::divI_proj_mask() {
2065 ShouldNotReachHere();
2066 return RegMask();
2067 }
2068
2069 // Register for MODI projection of divmodI
2070 RegMask Matcher::modI_proj_mask() {
2071 ShouldNotReachHere();
2072 return RegMask();
2073 }
2074
2075 // Register for DIVL projection of divmodL
2076 RegMask Matcher::divL_proj_mask() {
2077 ShouldNotReachHere();
2078 return RegMask();
2079 }
2080
2081 // Register for MODL projection of divmodL
2082 RegMask Matcher::modL_proj_mask() {
2083 ShouldNotReachHere();
2084 return RegMask();
2085 }
2086
2087 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2088 return L7_REGP_mask();
2089 }
2090
2091 %}
2092
2093
2094 // The intptr_t operand types, defined by textual substitution.
2095 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2096 #ifdef _LP64
2097 #define immX immL
2098 #define immX13 immL13
2099 #define immX13m7 immL13m7
2100 #define iRegX iRegL
2101 #define g1RegX g1RegL
2102 #else
2103 #define immX immI
2104 #define immX13 immI13
2105 #define immX13m7 immI13m7
2106 #define iRegX iRegI
2107 #define g1RegX g1RegI
2108 #endif
2109
2110 //----------ENCODING BLOCK-----------------------------------------------------
2111 // This block specifies the encoding classes used by the compiler to output
2112 // byte streams. Encoding classes are parameterized macros used by
2113 // Machine Instruction Nodes in order to generate the bit encoding of the
2114 // instruction. Operands specify their base encoding interface with the
2115 // interface keyword. There are currently supported four interfaces,
2116 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2117 // operand to generate a function which returns its register number when
2118 // queried. CONST_INTER causes an operand to generate a function which
2119 // returns the value of the constant when queried. MEMORY_INTER causes an
2120 // operand to generate four functions which return the Base Register, the
2121 // Index Register, the Scale Value, and the Offset Value of the operand when
2122 // queried. COND_INTER causes an operand to generate six functions which
2123 // return the encoding code (ie - encoding bits for the instruction)
2124 // associated with each basic boolean condition for a conditional instruction.
2125 //
2126 // Instructions specify two basic values for encoding. Again, a function
2127 // is available to check if the constant displacement is an oop. They use the
2128 // ins_encode keyword to specify their encoding classes (which must be
2129 // a sequence of enc_class names, and their parameters, specified in
2130 // the encoding block), and they use the
2131 // opcode keyword to specify, in order, their primary, secondary, and
2132 // tertiary opcode. Only the opcode sections which a particular instruction
2133 // needs for encoding need to be specified.
2134 encode %{
2135 enc_class enc_untested %{
2136 #ifdef ASSERT
2137 MacroAssembler _masm(&cbuf);
2138 __ untested("encoding");
2139 #endif
2140 %}
2141
2142 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2143 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
2144 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2145 %}
2146
2147 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2148 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2149 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2150 %}
2151
2152 enc_class form3_mem_prefetch_read( memory mem ) %{
2153 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2154 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2155 %}
2156
2157 enc_class form3_mem_prefetch_write( memory mem ) %{
2158 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2159 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2160 %}
2161
2162 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2163 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2164 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2165 guarantee($mem$$index == R_G0_enc, "double index?");
2166 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2167 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2168 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2169 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2170 %}
2171
2172 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2173 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2174 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2175 guarantee($mem$$index == R_G0_enc, "double index?");
2176 // Load long with 2 instructions
2177 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2178 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2179 %}
2180
2181 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2182 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2183 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2184 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2185 %}
2186
2187 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2188 // Encode a reg-reg copy. If it is useless, then empty encoding.
2189 if( $rs2$$reg != $rd$$reg )
2190 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2191 %}
2192
2193 // Target lo half of long
2194 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2195 // Encode a reg-reg copy. If it is useless, then empty encoding.
2196 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2197 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2198 %}
2199
2200 // Source lo half of long
2201 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2202 // Encode a reg-reg copy. If it is useless, then empty encoding.
2203 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2204 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2205 %}
2206
2207 // Target hi half of long
2208 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2209 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2210 %}
2211
2212 // Source lo half of long, and leave it sign extended.
2213 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2214 // Sign extend low half
2215 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2216 %}
2217
2218 // Source hi half of long, and leave it sign extended.
2219 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2220 // Shift high half to low half
2221 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2222 %}
2223
2224 // Source hi half of long
2225 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2226 // Encode a reg-reg copy. If it is useless, then empty encoding.
2227 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2228 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2229 %}
2230
2231 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2232 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2233 %}
2234
2235 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2236 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2237 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2238 %}
2239
2240 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2241 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2242 // clear if nothing else is happening
2243 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2244 // blt,a,pn done
2245 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2246 // mov dst,-1 in delay slot
2247 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2248 %}
2249
2250 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2251 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2252 %}
2253
2254 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2255 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2256 %}
2257
2258 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2259 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2260 %}
2261
2262 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2263 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2264 %}
2265
2266 enc_class move_return_pc_to_o1() %{
2267 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2268 %}
2269
2270 #ifdef _LP64
2271 /* %%% merge with enc_to_bool */
2272 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2273 MacroAssembler _masm(&cbuf);
2274
2275 Register src_reg = reg_to_register_object($src$$reg);
2276 Register dst_reg = reg_to_register_object($dst$$reg);
2277 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2278 %}
2279 #endif
2280
2281 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2282 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2283 MacroAssembler _masm(&cbuf);
2284
2285 Register p_reg = reg_to_register_object($p$$reg);
2286 Register q_reg = reg_to_register_object($q$$reg);
2287 Register y_reg = reg_to_register_object($y$$reg);
2288 Register tmp_reg = reg_to_register_object($tmp$$reg);
2289
2290 __ subcc( p_reg, q_reg, p_reg );
2291 __ add ( p_reg, y_reg, tmp_reg );
2292 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2293 %}
2294
2295 enc_class form_d2i_helper(regD src, regF dst) %{
2296 // fcmp %fcc0,$src,$src
2297 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2298 // branch %fcc0 not-nan, predict taken
2299 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2300 // fdtoi $src,$dst
2301 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2302 // fitos $dst,$dst (if nan)
2303 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2304 // clear $dst (if nan)
2305 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2306 // carry on here...
2307 %}
2308
2309 enc_class form_d2l_helper(regD src, regD dst) %{
2310 // fcmp %fcc0,$src,$src check for NAN
2311 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2312 // branch %fcc0 not-nan, predict taken
2313 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2314 // fdtox $src,$dst convert in delay slot
2315 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2316 // fxtod $dst,$dst (if nan)
2317 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2318 // clear $dst (if nan)
2319 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2320 // carry on here...
2321 %}
2322
2323 enc_class form_f2i_helper(regF src, regF dst) %{
2324 // fcmps %fcc0,$src,$src
2325 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2326 // branch %fcc0 not-nan, predict taken
2327 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2328 // fstoi $src,$dst
2329 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2330 // fitos $dst,$dst (if nan)
2331 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2332 // clear $dst (if nan)
2333 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2334 // carry on here...
2335 %}
2336
2337 enc_class form_f2l_helper(regF src, regD dst) %{
2338 // fcmps %fcc0,$src,$src
2339 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2340 // branch %fcc0 not-nan, predict taken
2341 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2342 // fstox $src,$dst
2343 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2344 // fxtod $dst,$dst (if nan)
2345 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2346 // clear $dst (if nan)
2347 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2348 // carry on here...
2349 %}
2350
2351 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2352 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2353 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2354 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2355
2356 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2357
2358 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2359 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2360
2361 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2362 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2363 %}
2364
2365 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2366 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2367 %}
2368
2369 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2370 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2371 %}
2372
2373 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2374 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2375 %}
2376
2377 enc_class form3_convI2F(regF rs2, regF rd) %{
2378 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2379 %}
2380
2381 // Encloding class for traceable jumps
2382 enc_class form_jmpl(g3RegP dest) %{
2383 emit_jmpl(cbuf, $dest$$reg);
2384 %}
2385
2386 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2387 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2388 %}
2389
2390 enc_class form2_nop() %{
2391 emit_nop(cbuf);
2392 %}
2393
2394 enc_class form2_illtrap() %{
2395 emit_illtrap(cbuf);
2396 %}
2397
2398
2399 // Compare longs and convert into -1, 0, 1.
2400 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2401 // CMP $src1,$src2
2402 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2403 // blt,a,pn done
2404 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2405 // mov dst,-1 in delay slot
2406 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2407 // bgt,a,pn done
2408 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2409 // mov dst,1 in delay slot
2410 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2411 // CLR $dst
2412 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2413 %}
2414
2415 enc_class enc_PartialSubtypeCheck() %{
2416 MacroAssembler _masm(&cbuf);
2417 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2418 __ delayed()->nop();
2419 %}
2420
2421 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2422 MacroAssembler _masm(&cbuf);
2423 Label* L = $labl$$label;
2424 Assembler::Predict predict_taken =
2425 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2426
2427 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2428 __ delayed()->nop();
2429 %}
2430
2431 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2432 MacroAssembler _masm(&cbuf);
2433 Label* L = $labl$$label;
2434 Assembler::Predict predict_taken =
2435 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2436
2437 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2438 __ delayed()->nop();
2439 %}
2440
2441 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2442 int op = (Assembler::arith_op << 30) |
2443 ($dst$$reg << 25) |
2444 (Assembler::movcc_op3 << 19) |
2445 (1 << 18) | // cc2 bit for 'icc'
2446 ($cmp$$cmpcode << 14) |
2447 (0 << 13) | // select register move
2448 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2449 ($src$$reg << 0);
2450 cbuf.insts()->emit_int32(op);
2451 %}
2452
2453 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2454 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2455 int op = (Assembler::arith_op << 30) |
2456 ($dst$$reg << 25) |
2457 (Assembler::movcc_op3 << 19) |
2458 (1 << 18) | // cc2 bit for 'icc'
2459 ($cmp$$cmpcode << 14) |
2460 (1 << 13) | // select immediate move
2461 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2462 (simm11 << 0);
2463 cbuf.insts()->emit_int32(op);
2464 %}
2465
2466 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2467 int op = (Assembler::arith_op << 30) |
2468 ($dst$$reg << 25) |
2469 (Assembler::movcc_op3 << 19) |
2470 (0 << 18) | // cc2 bit for 'fccX'
2471 ($cmp$$cmpcode << 14) |
2472 (0 << 13) | // select register move
2473 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2474 ($src$$reg << 0);
2475 cbuf.insts()->emit_int32(op);
2476 %}
2477
2478 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2479 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2480 int op = (Assembler::arith_op << 30) |
2481 ($dst$$reg << 25) |
2482 (Assembler::movcc_op3 << 19) |
2483 (0 << 18) | // cc2 bit for 'fccX'
2484 ($cmp$$cmpcode << 14) |
2485 (1 << 13) | // select immediate move
2486 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2487 (simm11 << 0);
2488 cbuf.insts()->emit_int32(op);
2489 %}
2490
2491 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2492 int op = (Assembler::arith_op << 30) |
2493 ($dst$$reg << 25) |
2494 (Assembler::fpop2_op3 << 19) |
2495 (0 << 18) |
2496 ($cmp$$cmpcode << 14) |
2497 (1 << 13) | // select register move
2498 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2499 ($primary << 5) | // select single, double or quad
2500 ($src$$reg << 0);
2501 cbuf.insts()->emit_int32(op);
2502 %}
2503
2504 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2505 int op = (Assembler::arith_op << 30) |
2506 ($dst$$reg << 25) |
2507 (Assembler::fpop2_op3 << 19) |
2508 (0 << 18) |
2509 ($cmp$$cmpcode << 14) |
2510 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2511 ($primary << 5) | // select single, double or quad
2512 ($src$$reg << 0);
2513 cbuf.insts()->emit_int32(op);
2514 %}
2515
2516 // Used by the MIN/MAX encodings. Same as a CMOV, but
2517 // the condition comes from opcode-field instead of an argument.
2518 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2519 int op = (Assembler::arith_op << 30) |
2520 ($dst$$reg << 25) |
2521 (Assembler::movcc_op3 << 19) |
2522 (1 << 18) | // cc2 bit for 'icc'
2523 ($primary << 14) |
2524 (0 << 13) | // select register move
2525 (0 << 11) | // cc1, cc0 bits for 'icc'
2526 ($src$$reg << 0);
2527 cbuf.insts()->emit_int32(op);
2528 %}
2529
2530 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2531 int op = (Assembler::arith_op << 30) |
2532 ($dst$$reg << 25) |
2533 (Assembler::movcc_op3 << 19) |
2534 (6 << 16) | // cc2 bit for 'xcc'
2535 ($primary << 14) |
2536 (0 << 13) | // select register move
2537 (0 << 11) | // cc1, cc0 bits for 'icc'
2538 ($src$$reg << 0);
2539 cbuf.insts()->emit_int32(op);
2540 %}
2541
2542 enc_class Set13( immI13 src, iRegI rd ) %{
2543 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2544 %}
2545
2546 enc_class SetHi22( immI src, iRegI rd ) %{
2547 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2548 %}
2549
2550 enc_class Set32( immI src, iRegI rd ) %{
2551 MacroAssembler _masm(&cbuf);
2552 __ set($src$$constant, reg_to_register_object($rd$$reg));
2553 %}
2554
2555 enc_class call_epilog %{
2556 if( VerifyStackAtCalls ) {
2557 MacroAssembler _masm(&cbuf);
2558 int framesize = ra_->C->frame_size_in_bytes();
2559 Register temp_reg = G3;
2560 __ add(SP, framesize, temp_reg);
2561 __ cmp(temp_reg, FP);
2562 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2563 }
2564 %}
2565
2566 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2567 // to G1 so the register allocator will not have to deal with the misaligned register
2568 // pair.
2569 enc_class adjust_long_from_native_call %{
2570 #ifndef _LP64
2571 if (returns_long()) {
2572 // sllx O0,32,O0
2573 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2574 // srl O1,0,O1
2575 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2576 // or O0,O1,G1
2577 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2578 }
2579 #endif
2580 %}
2581
2582 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2583 // CALL directly to the runtime
2584 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2585 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2586 /*preserve_g2=*/true);
2587 %}
2588
2589 enc_class preserve_SP %{
2590 MacroAssembler _masm(&cbuf);
2591 __ mov(SP, L7_mh_SP_save);
2592 %}
2593
2594 enc_class restore_SP %{
2595 MacroAssembler _masm(&cbuf);
2596 __ mov(L7_mh_SP_save, SP);
2597 %}
2598
2599 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2600 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2601 // who we intended to call.
2602 if (!_method) {
2603 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2604 } else if (_optimized_virtual) {
2605 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2606 } else {
2607 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2608 }
2609 if (_method) { // Emit stub for static call.
2610 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
2611 // Stub does not fit into scratch buffer if TraceJumps is enabled
2612 if (stub == NULL && !(TraceJumps && Compile::current()->in_scratch_emit_size())) {
2613 ciEnv::current()->record_failure("CodeCache is full");
2614 return;
2615 }
2616 }
2617 %}
2618
2619 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2620 MacroAssembler _masm(&cbuf);
2621 __ set_inst_mark();
2622 int vtable_index = this->_vtable_index;
2623 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2624 if (vtable_index < 0) {
2625 // must be invalid_vtable_index, not nonvirtual_vtable_index
2626 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2627 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2628 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2629 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2630 __ ic_call((address)$meth$$method);
2631 } else {
2632 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2633 // Just go thru the vtable
2634 // get receiver klass (receiver already checked for non-null)
2635 // If we end up going thru a c2i adapter interpreter expects method in G5
2636 int off = __ offset();
2637 __ load_klass(O0, G3_scratch);
2638 int klass_load_size;
2639 if (UseCompressedClassPointers) {
2640 assert(Universe::heap() != NULL, "java heap should be initialized");
2641 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2642 } else {
2643 klass_load_size = 1*BytesPerInstWord;
2644 }
2645 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2646 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2647 if (Assembler::is_simm13(v_off)) {
2648 __ ld_ptr(G3, v_off, G5_method);
2649 } else {
2650 // Generate 2 instructions
2651 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2652 __ or3(G5_method, v_off & 0x3ff, G5_method);
2653 // ld_ptr, set_hi, set
2654 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2655 "Unexpected instruction size(s)");
2656 __ ld_ptr(G3, G5_method, G5_method);
2657 }
2658 // NOTE: for vtable dispatches, the vtable entry will never be null.
2659 // However it may very well end up in handle_wrong_method if the
2660 // method is abstract for the particular class.
2661 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2662 // jump to target (either compiled code or c2iadapter)
2663 __ jmpl(G3_scratch, G0, O7);
2664 __ delayed()->nop();
2665 }
2666 %}
2667
2668 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2669 MacroAssembler _masm(&cbuf);
2670
2671 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2672 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2673 // we might be calling a C2I adapter which needs it.
2674
2675 assert(temp_reg != G5_ic_reg, "conflicting registers");
2676 // Load nmethod
2677 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2678
2679 // CALL to compiled java, indirect the contents of G3
2680 __ set_inst_mark();
2681 __ callr(temp_reg, G0);
2682 __ delayed()->nop();
2683 %}
2684
2685 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2686 MacroAssembler _masm(&cbuf);
2687 Register Rdividend = reg_to_register_object($src1$$reg);
2688 Register Rdivisor = reg_to_register_object($src2$$reg);
2689 Register Rresult = reg_to_register_object($dst$$reg);
2690
2691 __ sra(Rdivisor, 0, Rdivisor);
2692 __ sra(Rdividend, 0, Rdividend);
2693 __ sdivx(Rdividend, Rdivisor, Rresult);
2694 %}
2695
2696 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2697 MacroAssembler _masm(&cbuf);
2698
2699 Register Rdividend = reg_to_register_object($src1$$reg);
2700 int divisor = $imm$$constant;
2701 Register Rresult = reg_to_register_object($dst$$reg);
2702
2703 __ sra(Rdividend, 0, Rdividend);
2704 __ sdivx(Rdividend, divisor, Rresult);
2705 %}
2706
2707 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2708 MacroAssembler _masm(&cbuf);
2709 Register Rsrc1 = reg_to_register_object($src1$$reg);
2710 Register Rsrc2 = reg_to_register_object($src2$$reg);
2711 Register Rdst = reg_to_register_object($dst$$reg);
2712
2713 __ sra( Rsrc1, 0, Rsrc1 );
2714 __ sra( Rsrc2, 0, Rsrc2 );
2715 __ mulx( Rsrc1, Rsrc2, Rdst );
2716 __ srlx( Rdst, 32, Rdst );
2717 %}
2718
2719 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2720 MacroAssembler _masm(&cbuf);
2721 Register Rdividend = reg_to_register_object($src1$$reg);
2722 Register Rdivisor = reg_to_register_object($src2$$reg);
2723 Register Rresult = reg_to_register_object($dst$$reg);
2724 Register Rscratch = reg_to_register_object($scratch$$reg);
2725
2726 assert(Rdividend != Rscratch, "");
2727 assert(Rdivisor != Rscratch, "");
2728
2729 __ sra(Rdividend, 0, Rdividend);
2730 __ sra(Rdivisor, 0, Rdivisor);
2731 __ sdivx(Rdividend, Rdivisor, Rscratch);
2732 __ mulx(Rscratch, Rdivisor, Rscratch);
2733 __ sub(Rdividend, Rscratch, Rresult);
2734 %}
2735
2736 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2737 MacroAssembler _masm(&cbuf);
2738
2739 Register Rdividend = reg_to_register_object($src1$$reg);
2740 int divisor = $imm$$constant;
2741 Register Rresult = reg_to_register_object($dst$$reg);
2742 Register Rscratch = reg_to_register_object($scratch$$reg);
2743
2744 assert(Rdividend != Rscratch, "");
2745
2746 __ sra(Rdividend, 0, Rdividend);
2747 __ sdivx(Rdividend, divisor, Rscratch);
2748 __ mulx(Rscratch, divisor, Rscratch);
2749 __ sub(Rdividend, Rscratch, Rresult);
2750 %}
2751
2752 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2753 MacroAssembler _masm(&cbuf);
2754
2755 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2756 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2757
2758 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2759 %}
2760
2761 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2762 MacroAssembler _masm(&cbuf);
2763
2764 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2765 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2766
2767 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2768 %}
2769
2770 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2771 MacroAssembler _masm(&cbuf);
2772
2773 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2774 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2775
2776 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2777 %}
2778
2779 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2780 MacroAssembler _masm(&cbuf);
2781
2782 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2783 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2784
2785 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2786 %}
2787
2788 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2789 MacroAssembler _masm(&cbuf);
2790
2791 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2792 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2793
2794 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2795 %}
2796
2797 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2798 MacroAssembler _masm(&cbuf);
2799
2800 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2801 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2802
2803 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2804 %}
2805
2806 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2807 MacroAssembler _masm(&cbuf);
2808
2809 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2810 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2811
2812 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2813 %}
2814
2815 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2816 MacroAssembler _masm(&cbuf);
2817
2818 Register Roop = reg_to_register_object($oop$$reg);
2819 Register Rbox = reg_to_register_object($box$$reg);
2820 Register Rscratch = reg_to_register_object($scratch$$reg);
2821 Register Rmark = reg_to_register_object($scratch2$$reg);
2822
2823 assert(Roop != Rscratch, "");
2824 assert(Roop != Rmark, "");
2825 assert(Rbox != Rscratch, "");
2826 assert(Rbox != Rmark, "");
2827
2828 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2829 %}
2830
2831 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2832 MacroAssembler _masm(&cbuf);
2833
2834 Register Roop = reg_to_register_object($oop$$reg);
2835 Register Rbox = reg_to_register_object($box$$reg);
2836 Register Rscratch = reg_to_register_object($scratch$$reg);
2837 Register Rmark = reg_to_register_object($scratch2$$reg);
2838
2839 assert(Roop != Rscratch, "");
2840 assert(Roop != Rmark, "");
2841 assert(Rbox != Rscratch, "");
2842 assert(Rbox != Rmark, "");
2843
2844 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2845 %}
2846
2847 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2848 MacroAssembler _masm(&cbuf);
2849 Register Rmem = reg_to_register_object($mem$$reg);
2850 Register Rold = reg_to_register_object($old$$reg);
2851 Register Rnew = reg_to_register_object($new$$reg);
2852
2853 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2854 __ cmp( Rold, Rnew );
2855 %}
2856
2857 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2858 Register Rmem = reg_to_register_object($mem$$reg);
2859 Register Rold = reg_to_register_object($old$$reg);
2860 Register Rnew = reg_to_register_object($new$$reg);
2861
2862 MacroAssembler _masm(&cbuf);
2863 __ mov(Rnew, O7);
2864 __ casx(Rmem, Rold, O7);
2865 __ cmp( Rold, O7 );
2866 %}
2867
2868 // raw int cas, used for compareAndSwap
2869 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2870 Register Rmem = reg_to_register_object($mem$$reg);
2871 Register Rold = reg_to_register_object($old$$reg);
2872 Register Rnew = reg_to_register_object($new$$reg);
2873
2874 MacroAssembler _masm(&cbuf);
2875 __ mov(Rnew, O7);
2876 __ cas(Rmem, Rold, O7);
2877 __ cmp( Rold, O7 );
2878 %}
2879
2880 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2881 Register Rres = reg_to_register_object($res$$reg);
2882
2883 MacroAssembler _masm(&cbuf);
2884 __ mov(1, Rres);
2885 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2886 %}
2887
2888 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2889 Register Rres = reg_to_register_object($res$$reg);
2890
2891 MacroAssembler _masm(&cbuf);
2892 __ mov(1, Rres);
2893 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2894 %}
2895
2896 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2897 MacroAssembler _masm(&cbuf);
2898 Register Rdst = reg_to_register_object($dst$$reg);
2899 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2900 : reg_to_DoubleFloatRegister_object($src1$$reg);
2901 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2902 : reg_to_DoubleFloatRegister_object($src2$$reg);
2903
2904 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2905 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2906 %}
2907
2908 enc_class enc_rethrow() %{
2909 cbuf.set_insts_mark();
2910 Register temp_reg = G3;
2911 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
2912 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
2913 MacroAssembler _masm(&cbuf);
2914 #ifdef ASSERT
2915 __ save_frame(0);
2916 AddressLiteral last_rethrow_addrlit(&last_rethrow);
2917 __ sethi(last_rethrow_addrlit, L1);
2918 Address addr(L1, last_rethrow_addrlit.low10());
2919 __ rdpc(L2);
2920 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
2921 __ st_ptr(L2, addr);
2922 __ restore();
2923 #endif
2924 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
2925 __ delayed()->nop();
2926 %}
2927
2928 enc_class emit_mem_nop() %{
2929 // Generates the instruction LDUXA [o6,g0],#0x82,g0
2930 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
2931 %}
2932
2933 enc_class emit_fadd_nop() %{
2934 // Generates the instruction FMOVS f31,f31
2935 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
2936 %}
2937
2938 enc_class emit_br_nop() %{
2939 // Generates the instruction BPN,PN .
2940 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
2941 %}
2942
2943 enc_class enc_membar_acquire %{
2944 MacroAssembler _masm(&cbuf);
2945 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
2946 %}
2947
2948 enc_class enc_membar_release %{
2949 MacroAssembler _masm(&cbuf);
2950 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
2951 %}
2952
2953 enc_class enc_membar_volatile %{
2954 MacroAssembler _masm(&cbuf);
2955 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
2956 %}
2957
2958 %}
2959
2960 //----------FRAME--------------------------------------------------------------
2961 // Definition of frame structure and management information.
2962 //
2963 // S T A C K L A Y O U T Allocators stack-slot number
2964 // | (to get allocators register number
2965 // G Owned by | | v add VMRegImpl::stack0)
2966 // r CALLER | |
2967 // o | +--------+ pad to even-align allocators stack-slot
2968 // w V | pad0 | numbers; owned by CALLER
2969 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2970 // h ^ | in | 5
2971 // | | args | 4 Holes in incoming args owned by SELF
2972 // | | | | 3
2973 // | | +--------+
2974 // V | | old out| Empty on Intel, window on Sparc
2975 // | old |preserve| Must be even aligned.
2976 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
2977 // | | in | 3 area for Intel ret address
2978 // Owned by |preserve| Empty on Sparc.
2979 // SELF +--------+
2980 // | | pad2 | 2 pad to align old SP
2981 // | +--------+ 1
2982 // | | locks | 0
2983 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
2984 // | | pad1 | 11 pad to align new SP
2985 // | +--------+
2986 // | | | 10
2987 // | | spills | 9 spills
2988 // V | | 8 (pad0 slot for callee)
2989 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2990 // ^ | out | 7
2991 // | | args | 6 Holes in outgoing args owned by CALLEE
2992 // Owned by +--------+
2993 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2994 // | new |preserve| Must be even-aligned.
2995 // | SP-+--------+----> Matcher::_new_SP, even aligned
2996 // | | |
2997 //
2998 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2999 // known from SELF's arguments and the Java calling convention.
3000 // Region 6-7 is determined per call site.
3001 // Note 2: If the calling convention leaves holes in the incoming argument
3002 // area, those holes are owned by SELF. Holes in the outgoing area
3003 // are owned by the CALLEE. Holes should not be nessecary in the
3004 // incoming area, as the Java calling convention is completely under
3005 // the control of the AD file. Doubles can be sorted and packed to
3006 // avoid holes. Holes in the outgoing arguments may be necessary for
3007 // varargs C calling conventions.
3008 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3009 // even aligned with pad0 as needed.
3010 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3011 // region 6-11 is even aligned; it may be padded out more so that
3012 // the region from SP to FP meets the minimum stack alignment.
3013
3014 frame %{
3015 // What direction does stack grow in (assumed to be same for native & Java)
3016 stack_direction(TOWARDS_LOW);
3017
3018 // These two registers define part of the calling convention
3019 // between compiled code and the interpreter.
3020 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
3021 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3022
3023 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3024 cisc_spilling_operand_name(indOffset);
3025
3026 // Number of stack slots consumed by a Monitor enter
3027 #ifdef _LP64
3028 sync_stack_slots(2);
3029 #else
3030 sync_stack_slots(1);
3031 #endif
3032
3033 // Compiled code's Frame Pointer
3034 frame_pointer(R_SP);
3035
3036 // Stack alignment requirement
3037 stack_alignment(StackAlignmentInBytes);
3038 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3039 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3040
3041 // Number of stack slots between incoming argument block and the start of
3042 // a new frame. The PROLOG must add this many slots to the stack. The
3043 // EPILOG must remove this many slots.
3044 in_preserve_stack_slots(0);
3045
3046 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3047 // for calls to C. Supports the var-args backing area for register parms.
3048 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3049 #ifdef _LP64
3050 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3051 varargs_C_out_slots_killed(12);
3052 #else
3053 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3054 varargs_C_out_slots_killed( 7);
3055 #endif
3056
3057 // The after-PROLOG location of the return address. Location of
3058 // return address specifies a type (REG or STACK) and a number
3059 // representing the register number (i.e. - use a register name) or
3060 // stack slot.
3061 return_addr(REG R_I7); // Ret Addr is in register I7
3062
3063 // Body of function which returns an OptoRegs array locating
3064 // arguments either in registers or in stack slots for calling
3065 // java
3066 calling_convention %{
3067 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3068
3069 %}
3070
3071 // Body of function which returns an OptoRegs array locating
3072 // arguments either in registers or in stack slots for calling
3073 // C.
3074 c_calling_convention %{
3075 // This is obviously always outgoing
3076 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3077 %}
3078
3079 // Location of native (C/C++) and interpreter return values. This is specified to
3080 // be the same as Java. In the 32-bit VM, long values are actually returned from
3081 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3082 // to and from the register pairs is done by the appropriate call and epilog
3083 // opcodes. This simplifies the register allocator.
3084 c_return_value %{
3085 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3086 #ifdef _LP64
3087 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3088 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3089 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3090 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3091 #else // !_LP64
3092 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3093 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3094 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3095 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3096 #endif
3097 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3098 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3099 %}
3100
3101 // Location of compiled Java return values. Same as C
3102 return_value %{
3103 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3104 #ifdef _LP64
3105 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3106 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3107 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3108 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3109 #else // !_LP64
3110 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3111 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3112 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3113 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3114 #endif
3115 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3116 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3117 %}
3118
3119 %}
3120
3121
3122 //----------ATTRIBUTES---------------------------------------------------------
3123 //----------Operand Attributes-------------------------------------------------
3124 op_attrib op_cost(1); // Required cost attribute
3125
3126 //----------Instruction Attributes---------------------------------------------
3127 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3128 ins_attrib ins_size(32); // Required size attribute (in bits)
3129
3130 // avoid_back_to_back attribute is an expression that must return
3131 // one of the following values defined in MachNode:
3132 // AVOID_NONE - instruction can be placed anywhere
3133 // AVOID_BEFORE - instruction cannot be placed after an
3134 // instruction with MachNode::AVOID_AFTER
3135 // AVOID_AFTER - the next instruction cannot be the one
3136 // with MachNode::AVOID_BEFORE
3137 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at
3138 // the same time
3139 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE);
3140
3141 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3142 // non-matching short branch variant of some
3143 // long branch?
3144
3145 //----------OPERANDS-----------------------------------------------------------
3146 // Operand definitions must precede instruction definitions for correct parsing
3147 // in the ADLC because operands constitute user defined types which are used in
3148 // instruction definitions.
3149
3150 //----------Simple Operands----------------------------------------------------
3151 // Immediate Operands
3152 // Integer Immediate: 32-bit
3153 operand immI() %{
3154 match(ConI);
3155
3156 op_cost(0);
3157 // formats are generated automatically for constants and base registers
3158 format %{ %}
3159 interface(CONST_INTER);
3160 %}
3161
3162 // Integer Immediate: 0-bit
3163 operand immI0() %{
3164 predicate(n->get_int() == 0);
3165 match(ConI);
3166 op_cost(0);
3167
3168 format %{ %}
3169 interface(CONST_INTER);
3170 %}
3171
3172 // Integer Immediate: 5-bit
3173 operand immI5() %{
3174 predicate(Assembler::is_simm5(n->get_int()));
3175 match(ConI);
3176 op_cost(0);
3177 format %{ %}
3178 interface(CONST_INTER);
3179 %}
3180
3181 // Integer Immediate: 8-bit
3182 operand immI8() %{
3183 predicate(Assembler::is_simm8(n->get_int()));
3184 match(ConI);
3185 op_cost(0);
3186 format %{ %}
3187 interface(CONST_INTER);
3188 %}
3189
3190 // Integer Immediate: the value 10
3191 operand immI10() %{
3192 predicate(n->get_int() == 10);
3193 match(ConI);
3194 op_cost(0);
3195
3196 format %{ %}
3197 interface(CONST_INTER);
3198 %}
3199
3200 // Integer Immediate: 11-bit
3201 operand immI11() %{
3202 predicate(Assembler::is_simm11(n->get_int()));
3203 match(ConI);
3204 op_cost(0);
3205 format %{ %}
3206 interface(CONST_INTER);
3207 %}
3208
3209 // Integer Immediate: 13-bit
3210 operand immI13() %{
3211 predicate(Assembler::is_simm13(n->get_int()));
3212 match(ConI);
3213 op_cost(0);
3214
3215 format %{ %}
3216 interface(CONST_INTER);
3217 %}
3218
3219 // Integer Immediate: 13-bit minus 7
3220 operand immI13m7() %{
3221 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3222 match(ConI);
3223 op_cost(0);
3224
3225 format %{ %}
3226 interface(CONST_INTER);
3227 %}
3228
3229 // Integer Immediate: 16-bit
3230 operand immI16() %{
3231 predicate(Assembler::is_simm16(n->get_int()));
3232 match(ConI);
3233 op_cost(0);
3234 format %{ %}
3235 interface(CONST_INTER);
3236 %}
3237
3238 // Integer Immediate: the values 1-31
3239 operand immI_1_31() %{
3240 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3241 match(ConI);
3242 op_cost(0);
3243
3244 format %{ %}
3245 interface(CONST_INTER);
3246 %}
3247
3248 // Integer Immediate: the values 32-63
3249 operand immI_32_63() %{
3250 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3251 match(ConI);
3252 op_cost(0);
3253
3254 format %{ %}
3255 interface(CONST_INTER);
3256 %}
3257
3258 // Immediates for special shifts (sign extend)
3259
3260 // Integer Immediate: the value 16
3261 operand immI_16() %{
3262 predicate(n->get_int() == 16);
3263 match(ConI);
3264 op_cost(0);
3265
3266 format %{ %}
3267 interface(CONST_INTER);
3268 %}
3269
3270 // Integer Immediate: the value 24
3271 operand immI_24() %{
3272 predicate(n->get_int() == 24);
3273 match(ConI);
3274 op_cost(0);
3275
3276 format %{ %}
3277 interface(CONST_INTER);
3278 %}
3279 // Integer Immediate: the value 255
3280 operand immI_255() %{
3281 predicate( n->get_int() == 255 );
3282 match(ConI);
3283 op_cost(0);
3284
3285 format %{ %}
3286 interface(CONST_INTER);
3287 %}
3288
3289 // Integer Immediate: the value 65535
3290 operand immI_65535() %{
3291 predicate(n->get_int() == 65535);
3292 match(ConI);
3293 op_cost(0);
3294
3295 format %{ %}
3296 interface(CONST_INTER);
3297 %}
3298
3299 // Integer Immediate: the values 0-31
3300 operand immU5() %{
3301 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3302 match(ConI);
3303 op_cost(0);
3304
3305 format %{ %}
3306 interface(CONST_INTER);
3307 %}
3308
3309 // Integer Immediate: 6-bit
3310 operand immU6() %{
3311 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3312 match(ConI);
3313 op_cost(0);
3314 format %{ %}
3315 interface(CONST_INTER);
3316 %}
3317
3318 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3319 operand immU12() %{
3320 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3321 match(ConI);
3322 op_cost(0);
3323
3324 format %{ %}
3325 interface(CONST_INTER);
3326 %}
3327
3328 // Integer Immediate non-negative
3329 operand immU31()
3330 %{
3331 predicate(n->get_int() >= 0);
3332 match(ConI);
3333
3334 op_cost(0);
3335 format %{ %}
3336 interface(CONST_INTER);
3337 %}
3338
3339 // Long Immediate: the value FF
3340 operand immL_FF() %{
3341 predicate( n->get_long() == 0xFFL );
3342 match(ConL);
3343 op_cost(0);
3344
3345 format %{ %}
3346 interface(CONST_INTER);
3347 %}
3348
3349 // Long Immediate: the value FFFF
3350 operand immL_FFFF() %{
3351 predicate( n->get_long() == 0xFFFFL );
3352 match(ConL);
3353 op_cost(0);
3354
3355 format %{ %}
3356 interface(CONST_INTER);
3357 %}
3358
3359 // Pointer Immediate: 32 or 64-bit
3360 operand immP() %{
3361 match(ConP);
3362
3363 op_cost(5);
3364 // formats are generated automatically for constants and base registers
3365 format %{ %}
3366 interface(CONST_INTER);
3367 %}
3368
3369 #ifdef _LP64
3370 // Pointer Immediate: 64-bit
3371 operand immP_set() %{
3372 predicate(!VM_Version::is_niagara_plus());
3373 match(ConP);
3374
3375 op_cost(5);
3376 // formats are generated automatically for constants and base registers
3377 format %{ %}
3378 interface(CONST_INTER);
3379 %}
3380
3381 // Pointer Immediate: 64-bit
3382 // From Niagara2 processors on a load should be better than materializing.
3383 operand immP_load() %{
3384 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3385 match(ConP);
3386
3387 op_cost(5);
3388 // formats are generated automatically for constants and base registers
3389 format %{ %}
3390 interface(CONST_INTER);
3391 %}
3392
3393 // Pointer Immediate: 64-bit
3394 operand immP_no_oop_cheap() %{
3395 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3396 match(ConP);
3397
3398 op_cost(5);
3399 // formats are generated automatically for constants and base registers
3400 format %{ %}
3401 interface(CONST_INTER);
3402 %}
3403 #endif
3404
3405 operand immP13() %{
3406 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3407 match(ConP);
3408 op_cost(0);
3409
3410 format %{ %}
3411 interface(CONST_INTER);
3412 %}
3413
3414 operand immP0() %{
3415 predicate(n->get_ptr() == 0);
3416 match(ConP);
3417 op_cost(0);
3418
3419 format %{ %}
3420 interface(CONST_INTER);
3421 %}
3422
3423 operand immP_poll() %{
3424 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3425 match(ConP);
3426
3427 // formats are generated automatically for constants and base registers
3428 format %{ %}
3429 interface(CONST_INTER);
3430 %}
3431
3432 // Pointer Immediate
3433 operand immN()
3434 %{
3435 match(ConN);
3436
3437 op_cost(10);
3438 format %{ %}
3439 interface(CONST_INTER);
3440 %}
3441
3442 operand immNKlass()
3443 %{
3444 match(ConNKlass);
3445
3446 op_cost(10);
3447 format %{ %}
3448 interface(CONST_INTER);
3449 %}
3450
3451 // NULL Pointer Immediate
3452 operand immN0()
3453 %{
3454 predicate(n->get_narrowcon() == 0);
3455 match(ConN);
3456
3457 op_cost(0);
3458 format %{ %}
3459 interface(CONST_INTER);
3460 %}
3461
3462 operand immL() %{
3463 match(ConL);
3464 op_cost(40);
3465 // formats are generated automatically for constants and base registers
3466 format %{ %}
3467 interface(CONST_INTER);
3468 %}
3469
3470 operand immL0() %{
3471 predicate(n->get_long() == 0L);
3472 match(ConL);
3473 op_cost(0);
3474 // formats are generated automatically for constants and base registers
3475 format %{ %}
3476 interface(CONST_INTER);
3477 %}
3478
3479 // Integer Immediate: 5-bit
3480 operand immL5() %{
3481 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3482 match(ConL);
3483 op_cost(0);
3484 format %{ %}
3485 interface(CONST_INTER);
3486 %}
3487
3488 // Long Immediate: 13-bit
3489 operand immL13() %{
3490 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3491 match(ConL);
3492 op_cost(0);
3493
3494 format %{ %}
3495 interface(CONST_INTER);
3496 %}
3497
3498 // Long Immediate: 13-bit minus 7
3499 operand immL13m7() %{
3500 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3501 match(ConL);
3502 op_cost(0);
3503
3504 format %{ %}
3505 interface(CONST_INTER);
3506 %}
3507
3508 // Long Immediate: low 32-bit mask
3509 operand immL_32bits() %{
3510 predicate(n->get_long() == 0xFFFFFFFFL);
3511 match(ConL);
3512 op_cost(0);
3513
3514 format %{ %}
3515 interface(CONST_INTER);
3516 %}
3517
3518 // Long Immediate: cheap (materialize in <= 3 instructions)
3519 operand immL_cheap() %{
3520 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3521 match(ConL);
3522 op_cost(0);
3523
3524 format %{ %}
3525 interface(CONST_INTER);
3526 %}
3527
3528 // Long Immediate: expensive (materialize in > 3 instructions)
3529 operand immL_expensive() %{
3530 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3531 match(ConL);
3532 op_cost(0);
3533
3534 format %{ %}
3535 interface(CONST_INTER);
3536 %}
3537
3538 // Double Immediate
3539 operand immD() %{
3540 match(ConD);
3541
3542 op_cost(40);
3543 format %{ %}
3544 interface(CONST_INTER);
3545 %}
3546
3547 // Double Immediate: +0.0d
3548 operand immD0() %{
3549 predicate(jlong_cast(n->getd()) == 0);
3550 match(ConD);
3551
3552 op_cost(0);
3553 format %{ %}
3554 interface(CONST_INTER);
3555 %}
3556
3557 // Float Immediate
3558 operand immF() %{
3559 match(ConF);
3560
3561 op_cost(20);
3562 format %{ %}
3563 interface(CONST_INTER);
3564 %}
3565
3566 // Float Immediate: +0.0f
3567 operand immF0() %{
3568 predicate(jint_cast(n->getf()) == 0);
3569 match(ConF);
3570
3571 op_cost(0);
3572 format %{ %}
3573 interface(CONST_INTER);
3574 %}
3575
3576 // Integer Register Operands
3577 // Integer Register
3578 operand iRegI() %{
3579 constraint(ALLOC_IN_RC(int_reg));
3580 match(RegI);
3581
3582 match(notemp_iRegI);
3583 match(g1RegI);
3584 match(o0RegI);
3585 match(iRegIsafe);
3586
3587 format %{ %}
3588 interface(REG_INTER);
3589 %}
3590
3591 operand notemp_iRegI() %{
3592 constraint(ALLOC_IN_RC(notemp_int_reg));
3593 match(RegI);
3594
3595 match(o0RegI);
3596
3597 format %{ %}
3598 interface(REG_INTER);
3599 %}
3600
3601 operand o0RegI() %{
3602 constraint(ALLOC_IN_RC(o0_regI));
3603 match(iRegI);
3604
3605 format %{ %}
3606 interface(REG_INTER);
3607 %}
3608
3609 // Pointer Register
3610 operand iRegP() %{
3611 constraint(ALLOC_IN_RC(ptr_reg));
3612 match(RegP);
3613
3614 match(lock_ptr_RegP);
3615 match(g1RegP);
3616 match(g2RegP);
3617 match(g3RegP);
3618 match(g4RegP);
3619 match(i0RegP);
3620 match(o0RegP);
3621 match(o1RegP);
3622 match(l7RegP);
3623
3624 format %{ %}
3625 interface(REG_INTER);
3626 %}
3627
3628 operand sp_ptr_RegP() %{
3629 constraint(ALLOC_IN_RC(sp_ptr_reg));
3630 match(RegP);
3631 match(iRegP);
3632
3633 format %{ %}
3634 interface(REG_INTER);
3635 %}
3636
3637 operand lock_ptr_RegP() %{
3638 constraint(ALLOC_IN_RC(lock_ptr_reg));
3639 match(RegP);
3640 match(i0RegP);
3641 match(o0RegP);
3642 match(o1RegP);
3643 match(l7RegP);
3644
3645 format %{ %}
3646 interface(REG_INTER);
3647 %}
3648
3649 operand g1RegP() %{
3650 constraint(ALLOC_IN_RC(g1_regP));
3651 match(iRegP);
3652
3653 format %{ %}
3654 interface(REG_INTER);
3655 %}
3656
3657 operand g2RegP() %{
3658 constraint(ALLOC_IN_RC(g2_regP));
3659 match(iRegP);
3660
3661 format %{ %}
3662 interface(REG_INTER);
3663 %}
3664
3665 operand g3RegP() %{
3666 constraint(ALLOC_IN_RC(g3_regP));
3667 match(iRegP);
3668
3669 format %{ %}
3670 interface(REG_INTER);
3671 %}
3672
3673 operand g1RegI() %{
3674 constraint(ALLOC_IN_RC(g1_regI));
3675 match(iRegI);
3676
3677 format %{ %}
3678 interface(REG_INTER);
3679 %}
3680
3681 operand g3RegI() %{
3682 constraint(ALLOC_IN_RC(g3_regI));
3683 match(iRegI);
3684
3685 format %{ %}
3686 interface(REG_INTER);
3687 %}
3688
3689 operand g4RegI() %{
3690 constraint(ALLOC_IN_RC(g4_regI));
3691 match(iRegI);
3692
3693 format %{ %}
3694 interface(REG_INTER);
3695 %}
3696
3697 operand g4RegP() %{
3698 constraint(ALLOC_IN_RC(g4_regP));
3699 match(iRegP);
3700
3701 format %{ %}
3702 interface(REG_INTER);
3703 %}
3704
3705 operand i0RegP() %{
3706 constraint(ALLOC_IN_RC(i0_regP));
3707 match(iRegP);
3708
3709 format %{ %}
3710 interface(REG_INTER);
3711 %}
3712
3713 operand o0RegP() %{
3714 constraint(ALLOC_IN_RC(o0_regP));
3715 match(iRegP);
3716
3717 format %{ %}
3718 interface(REG_INTER);
3719 %}
3720
3721 operand o1RegP() %{
3722 constraint(ALLOC_IN_RC(o1_regP));
3723 match(iRegP);
3724
3725 format %{ %}
3726 interface(REG_INTER);
3727 %}
3728
3729 operand o2RegP() %{
3730 constraint(ALLOC_IN_RC(o2_regP));
3731 match(iRegP);
3732
3733 format %{ %}
3734 interface(REG_INTER);
3735 %}
3736
3737 operand o7RegP() %{
3738 constraint(ALLOC_IN_RC(o7_regP));
3739 match(iRegP);
3740
3741 format %{ %}
3742 interface(REG_INTER);
3743 %}
3744
3745 operand l7RegP() %{
3746 constraint(ALLOC_IN_RC(l7_regP));
3747 match(iRegP);
3748
3749 format %{ %}
3750 interface(REG_INTER);
3751 %}
3752
3753 operand o7RegI() %{
3754 constraint(ALLOC_IN_RC(o7_regI));
3755 match(iRegI);
3756
3757 format %{ %}
3758 interface(REG_INTER);
3759 %}
3760
3761 operand iRegN() %{
3762 constraint(ALLOC_IN_RC(int_reg));
3763 match(RegN);
3764
3765 format %{ %}
3766 interface(REG_INTER);
3767 %}
3768
3769 // Long Register
3770 operand iRegL() %{
3771 constraint(ALLOC_IN_RC(long_reg));
3772 match(RegL);
3773
3774 format %{ %}
3775 interface(REG_INTER);
3776 %}
3777
3778 operand o2RegL() %{
3779 constraint(ALLOC_IN_RC(o2_regL));
3780 match(iRegL);
3781
3782 format %{ %}
3783 interface(REG_INTER);
3784 %}
3785
3786 operand o7RegL() %{
3787 constraint(ALLOC_IN_RC(o7_regL));
3788 match(iRegL);
3789
3790 format %{ %}
3791 interface(REG_INTER);
3792 %}
3793
3794 operand g1RegL() %{
3795 constraint(ALLOC_IN_RC(g1_regL));
3796 match(iRegL);
3797
3798 format %{ %}
3799 interface(REG_INTER);
3800 %}
3801
3802 operand g3RegL() %{
3803 constraint(ALLOC_IN_RC(g3_regL));
3804 match(iRegL);
3805
3806 format %{ %}
3807 interface(REG_INTER);
3808 %}
3809
3810 // Int Register safe
3811 // This is 64bit safe
3812 operand iRegIsafe() %{
3813 constraint(ALLOC_IN_RC(long_reg));
3814
3815 match(iRegI);
3816
3817 format %{ %}
3818 interface(REG_INTER);
3819 %}
3820
3821 // Condition Code Flag Register
3822 operand flagsReg() %{
3823 constraint(ALLOC_IN_RC(int_flags));
3824 match(RegFlags);
3825
3826 format %{ "ccr" %} // both ICC and XCC
3827 interface(REG_INTER);
3828 %}
3829
3830 // Condition Code Register, unsigned comparisons.
3831 operand flagsRegU() %{
3832 constraint(ALLOC_IN_RC(int_flags));
3833 match(RegFlags);
3834
3835 format %{ "icc_U" %}
3836 interface(REG_INTER);
3837 %}
3838
3839 // Condition Code Register, pointer comparisons.
3840 operand flagsRegP() %{
3841 constraint(ALLOC_IN_RC(int_flags));
3842 match(RegFlags);
3843
3844 #ifdef _LP64
3845 format %{ "xcc_P" %}
3846 #else
3847 format %{ "icc_P" %}
3848 #endif
3849 interface(REG_INTER);
3850 %}
3851
3852 // Condition Code Register, long comparisons.
3853 operand flagsRegL() %{
3854 constraint(ALLOC_IN_RC(int_flags));
3855 match(RegFlags);
3856
3857 format %{ "xcc_L" %}
3858 interface(REG_INTER);
3859 %}
3860
3861 // Condition Code Register, floating comparisons, unordered same as "less".
3862 operand flagsRegF() %{
3863 constraint(ALLOC_IN_RC(float_flags));
3864 match(RegFlags);
3865 match(flagsRegF0);
3866
3867 format %{ %}
3868 interface(REG_INTER);
3869 %}
3870
3871 operand flagsRegF0() %{
3872 constraint(ALLOC_IN_RC(float_flag0));
3873 match(RegFlags);
3874
3875 format %{ %}
3876 interface(REG_INTER);
3877 %}
3878
3879
3880 // Condition Code Flag Register used by long compare
3881 operand flagsReg_long_LTGE() %{
3882 constraint(ALLOC_IN_RC(int_flags));
3883 match(RegFlags);
3884 format %{ "icc_LTGE" %}
3885 interface(REG_INTER);
3886 %}
3887 operand flagsReg_long_EQNE() %{
3888 constraint(ALLOC_IN_RC(int_flags));
3889 match(RegFlags);
3890 format %{ "icc_EQNE" %}
3891 interface(REG_INTER);
3892 %}
3893 operand flagsReg_long_LEGT() %{
3894 constraint(ALLOC_IN_RC(int_flags));
3895 match(RegFlags);
3896 format %{ "icc_LEGT" %}
3897 interface(REG_INTER);
3898 %}
3899
3900
3901 operand regD() %{
3902 constraint(ALLOC_IN_RC(dflt_reg));
3903 match(RegD);
3904
3905 match(regD_low);
3906
3907 format %{ %}
3908 interface(REG_INTER);
3909 %}
3910
3911 operand regF() %{
3912 constraint(ALLOC_IN_RC(sflt_reg));
3913 match(RegF);
3914
3915 format %{ %}
3916 interface(REG_INTER);
3917 %}
3918
3919 operand regD_low() %{
3920 constraint(ALLOC_IN_RC(dflt_low_reg));
3921 match(regD);
3922
3923 format %{ %}
3924 interface(REG_INTER);
3925 %}
3926
3927 // Special Registers
3928
3929 // Method Register
3930 operand inline_cache_regP(iRegP reg) %{
3931 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
3932 match(reg);
3933 format %{ %}
3934 interface(REG_INTER);
3935 %}
3936
3937 operand interpreter_method_oop_regP(iRegP reg) %{
3938 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
3939 match(reg);
3940 format %{ %}
3941 interface(REG_INTER);
3942 %}
3943
3944
3945 //----------Complex Operands---------------------------------------------------
3946 // Indirect Memory Reference
3947 operand indirect(sp_ptr_RegP reg) %{
3948 constraint(ALLOC_IN_RC(sp_ptr_reg));
3949 match(reg);
3950
3951 op_cost(100);
3952 format %{ "[$reg]" %}
3953 interface(MEMORY_INTER) %{
3954 base($reg);
3955 index(0x0);
3956 scale(0x0);
3957 disp(0x0);
3958 %}
3959 %}
3960
3961 // Indirect with simm13 Offset
3962 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
3963 constraint(ALLOC_IN_RC(sp_ptr_reg));
3964 match(AddP reg offset);
3965
3966 op_cost(100);
3967 format %{ "[$reg + $offset]" %}
3968 interface(MEMORY_INTER) %{
3969 base($reg);
3970 index(0x0);
3971 scale(0x0);
3972 disp($offset);
3973 %}
3974 %}
3975
3976 // Indirect with simm13 Offset minus 7
3977 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
3978 constraint(ALLOC_IN_RC(sp_ptr_reg));
3979 match(AddP reg offset);
3980
3981 op_cost(100);
3982 format %{ "[$reg + $offset]" %}
3983 interface(MEMORY_INTER) %{
3984 base($reg);
3985 index(0x0);
3986 scale(0x0);
3987 disp($offset);
3988 %}
3989 %}
3990
3991 // Note: Intel has a swapped version also, like this:
3992 //operand indOffsetX(iRegI reg, immP offset) %{
3993 // constraint(ALLOC_IN_RC(int_reg));
3994 // match(AddP offset reg);
3995 //
3996 // op_cost(100);
3997 // format %{ "[$reg + $offset]" %}
3998 // interface(MEMORY_INTER) %{
3999 // base($reg);
4000 // index(0x0);
4001 // scale(0x0);
4002 // disp($offset);
4003 // %}
4004 //%}
4005 //// However, it doesn't make sense for SPARC, since
4006 // we have no particularly good way to embed oops in
4007 // single instructions.
4008
4009 // Indirect with Register Index
4010 operand indIndex(iRegP addr, iRegX index) %{
4011 constraint(ALLOC_IN_RC(ptr_reg));
4012 match(AddP addr index);
4013
4014 op_cost(100);
4015 format %{ "[$addr + $index]" %}
4016 interface(MEMORY_INTER) %{
4017 base($addr);
4018 index($index);
4019 scale(0x0);
4020 disp(0x0);
4021 %}
4022 %}
4023
4024 //----------Special Memory Operands--------------------------------------------
4025 // Stack Slot Operand - This operand is used for loading and storing temporary
4026 // values on the stack where a match requires a value to
4027 // flow through memory.
4028 operand stackSlotI(sRegI reg) %{
4029 constraint(ALLOC_IN_RC(stack_slots));
4030 op_cost(100);
4031 //match(RegI);
4032 format %{ "[$reg]" %}
4033 interface(MEMORY_INTER) %{
4034 base(0xE); // R_SP
4035 index(0x0);
4036 scale(0x0);
4037 disp($reg); // Stack Offset
4038 %}
4039 %}
4040
4041 operand stackSlotP(sRegP reg) %{
4042 constraint(ALLOC_IN_RC(stack_slots));
4043 op_cost(100);
4044 //match(RegP);
4045 format %{ "[$reg]" %}
4046 interface(MEMORY_INTER) %{
4047 base(0xE); // R_SP
4048 index(0x0);
4049 scale(0x0);
4050 disp($reg); // Stack Offset
4051 %}
4052 %}
4053
4054 operand stackSlotF(sRegF reg) %{
4055 constraint(ALLOC_IN_RC(stack_slots));
4056 op_cost(100);
4057 //match(RegF);
4058 format %{ "[$reg]" %}
4059 interface(MEMORY_INTER) %{
4060 base(0xE); // R_SP
4061 index(0x0);
4062 scale(0x0);
4063 disp($reg); // Stack Offset
4064 %}
4065 %}
4066 operand stackSlotD(sRegD reg) %{
4067 constraint(ALLOC_IN_RC(stack_slots));
4068 op_cost(100);
4069 //match(RegD);
4070 format %{ "[$reg]" %}
4071 interface(MEMORY_INTER) %{
4072 base(0xE); // R_SP
4073 index(0x0);
4074 scale(0x0);
4075 disp($reg); // Stack Offset
4076 %}
4077 %}
4078 operand stackSlotL(sRegL reg) %{
4079 constraint(ALLOC_IN_RC(stack_slots));
4080 op_cost(100);
4081 //match(RegL);
4082 format %{ "[$reg]" %}
4083 interface(MEMORY_INTER) %{
4084 base(0xE); // R_SP
4085 index(0x0);
4086 scale(0x0);
4087 disp($reg); // Stack Offset
4088 %}
4089 %}
4090
4091 // Operands for expressing Control Flow
4092 // NOTE: Label is a predefined operand which should not be redefined in
4093 // the AD file. It is generically handled within the ADLC.
4094
4095 //----------Conditional Branch Operands----------------------------------------
4096 // Comparison Op - This is the operation of the comparison, and is limited to
4097 // the following set of codes:
4098 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4099 //
4100 // Other attributes of the comparison, such as unsignedness, are specified
4101 // by the comparison instruction that sets a condition code flags register.
4102 // That result is represented by a flags operand whose subtype is appropriate
4103 // to the unsignedness (etc.) of the comparison.
4104 //
4105 // Later, the instruction which matches both the Comparison Op (a Bool) and
4106 // the flags (produced by the Cmp) specifies the coding of the comparison op
4107 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4108
4109 operand cmpOp() %{
4110 match(Bool);
4111
4112 format %{ "" %}
4113 interface(COND_INTER) %{
4114 equal(0x1);
4115 not_equal(0x9);
4116 less(0x3);
4117 greater_equal(0xB);
4118 less_equal(0x2);
4119 greater(0xA);
4120 overflow(0x7);
4121 no_overflow(0xF);
4122 %}
4123 %}
4124
4125 // Comparison Op, unsigned
4126 operand cmpOpU() %{
4127 match(Bool);
4128 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4129 n->as_Bool()->_test._test != BoolTest::no_overflow);
4130
4131 format %{ "u" %}
4132 interface(COND_INTER) %{
4133 equal(0x1);
4134 not_equal(0x9);
4135 less(0x5);
4136 greater_equal(0xD);
4137 less_equal(0x4);
4138 greater(0xC);
4139 overflow(0x7);
4140 no_overflow(0xF);
4141 %}
4142 %}
4143
4144 // Comparison Op, pointer (same as unsigned)
4145 operand cmpOpP() %{
4146 match(Bool);
4147 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4148 n->as_Bool()->_test._test != BoolTest::no_overflow);
4149
4150 format %{ "p" %}
4151 interface(COND_INTER) %{
4152 equal(0x1);
4153 not_equal(0x9);
4154 less(0x5);
4155 greater_equal(0xD);
4156 less_equal(0x4);
4157 greater(0xC);
4158 overflow(0x7);
4159 no_overflow(0xF);
4160 %}
4161 %}
4162
4163 // Comparison Op, branch-register encoding
4164 operand cmpOp_reg() %{
4165 match(Bool);
4166 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4167 n->as_Bool()->_test._test != BoolTest::no_overflow);
4168
4169 format %{ "" %}
4170 interface(COND_INTER) %{
4171 equal (0x1);
4172 not_equal (0x5);
4173 less (0x3);
4174 greater_equal(0x7);
4175 less_equal (0x2);
4176 greater (0x6);
4177 overflow(0x7); // not supported
4178 no_overflow(0xF); // not supported
4179 %}
4180 %}
4181
4182 // Comparison Code, floating, unordered same as less
4183 operand cmpOpF() %{
4184 match(Bool);
4185 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4186 n->as_Bool()->_test._test != BoolTest::no_overflow);
4187
4188 format %{ "fl" %}
4189 interface(COND_INTER) %{
4190 equal(0x9);
4191 not_equal(0x1);
4192 less(0x3);
4193 greater_equal(0xB);
4194 less_equal(0xE);
4195 greater(0x6);
4196
4197 overflow(0x7); // not supported
4198 no_overflow(0xF); // not supported
4199 %}
4200 %}
4201
4202 // Used by long compare
4203 operand cmpOp_commute() %{
4204 match(Bool);
4205 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4206 n->as_Bool()->_test._test != BoolTest::no_overflow);
4207
4208 format %{ "" %}
4209 interface(COND_INTER) %{
4210 equal(0x1);
4211 not_equal(0x9);
4212 less(0xA);
4213 greater_equal(0x2);
4214 less_equal(0xB);
4215 greater(0x3);
4216 overflow(0x7);
4217 no_overflow(0xF);
4218 %}
4219 %}
4220
4221 //----------OPERAND CLASSES----------------------------------------------------
4222 // Operand Classes are groups of operands that are used to simplify
4223 // instruction definitions by not requiring the AD writer to specify separate
4224 // instructions for every form of operand when the instruction accepts
4225 // multiple operand types with the same basic encoding and format. The classic
4226 // case of this is memory operands.
4227 opclass memory( indirect, indOffset13, indIndex );
4228 opclass indIndexMemory( indIndex );
4229
4230 //----------PIPELINE-----------------------------------------------------------
4231 pipeline %{
4232
4233 //----------ATTRIBUTES---------------------------------------------------------
4234 attributes %{
4235 fixed_size_instructions; // Fixed size instructions
4236 branch_has_delay_slot; // Branch has delay slot following
4237 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4238 instruction_unit_size = 4; // An instruction is 4 bytes long
4239 instruction_fetch_unit_size = 16; // The processor fetches one line
4240 instruction_fetch_units = 1; // of 16 bytes
4241
4242 // List of nop instructions
4243 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4244 %}
4245
4246 //----------RESOURCES----------------------------------------------------------
4247 // Resources are the functional units available to the machine
4248 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4249
4250 //----------PIPELINE DESCRIPTION-----------------------------------------------
4251 // Pipeline Description specifies the stages in the machine's pipeline
4252
4253 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4254
4255 //----------PIPELINE CLASSES---------------------------------------------------
4256 // Pipeline Classes describe the stages in which input and output are
4257 // referenced by the hardware pipeline.
4258
4259 // Integer ALU reg-reg operation
4260 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4261 single_instruction;
4262 dst : E(write);
4263 src1 : R(read);
4264 src2 : R(read);
4265 IALU : R;
4266 %}
4267
4268 // Integer ALU reg-reg long operation
4269 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4270 instruction_count(2);
4271 dst : E(write);
4272 src1 : R(read);
4273 src2 : R(read);
4274 IALU : R;
4275 IALU : R;
4276 %}
4277
4278 // Integer ALU reg-reg long dependent operation
4279 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4280 instruction_count(1); multiple_bundles;
4281 dst : E(write);
4282 src1 : R(read);
4283 src2 : R(read);
4284 cr : E(write);
4285 IALU : R(2);
4286 %}
4287
4288 // Integer ALU reg-imm operaion
4289 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4290 single_instruction;
4291 dst : E(write);
4292 src1 : R(read);
4293 IALU : R;
4294 %}
4295
4296 // Integer ALU reg-reg operation with condition code
4297 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4298 single_instruction;
4299 dst : E(write);
4300 cr : E(write);
4301 src1 : R(read);
4302 src2 : R(read);
4303 IALU : R;
4304 %}
4305
4306 // Integer ALU reg-imm operation with condition code
4307 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4308 single_instruction;
4309 dst : E(write);
4310 cr : E(write);
4311 src1 : R(read);
4312 IALU : R;
4313 %}
4314
4315 // Integer ALU zero-reg operation
4316 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4317 single_instruction;
4318 dst : E(write);
4319 src2 : R(read);
4320 IALU : R;
4321 %}
4322
4323 // Integer ALU zero-reg operation with condition code only
4324 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4325 single_instruction;
4326 cr : E(write);
4327 src : R(read);
4328 IALU : R;
4329 %}
4330
4331 // Integer ALU reg-reg operation with condition code only
4332 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4333 single_instruction;
4334 cr : E(write);
4335 src1 : R(read);
4336 src2 : R(read);
4337 IALU : R;
4338 %}
4339
4340 // Integer ALU reg-imm operation with condition code only
4341 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4342 single_instruction;
4343 cr : E(write);
4344 src1 : R(read);
4345 IALU : R;
4346 %}
4347
4348 // Integer ALU reg-reg-zero operation with condition code only
4349 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4350 single_instruction;
4351 cr : E(write);
4352 src1 : R(read);
4353 src2 : R(read);
4354 IALU : R;
4355 %}
4356
4357 // Integer ALU reg-imm-zero operation with condition code only
4358 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4359 single_instruction;
4360 cr : E(write);
4361 src1 : R(read);
4362 IALU : R;
4363 %}
4364
4365 // Integer ALU reg-reg operation with condition code, src1 modified
4366 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4367 single_instruction;
4368 cr : E(write);
4369 src1 : E(write);
4370 src1 : R(read);
4371 src2 : R(read);
4372 IALU : R;
4373 %}
4374
4375 // Integer ALU reg-imm operation with condition code, src1 modified
4376 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4377 single_instruction;
4378 cr : E(write);
4379 src1 : E(write);
4380 src1 : R(read);
4381 IALU : R;
4382 %}
4383
4384 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4385 multiple_bundles;
4386 dst : E(write)+4;
4387 cr : E(write);
4388 src1 : R(read);
4389 src2 : R(read);
4390 IALU : R(3);
4391 BR : R(2);
4392 %}
4393
4394 // Integer ALU operation
4395 pipe_class ialu_none(iRegI dst) %{
4396 single_instruction;
4397 dst : E(write);
4398 IALU : R;
4399 %}
4400
4401 // Integer ALU reg operation
4402 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4403 single_instruction; may_have_no_code;
4404 dst : E(write);
4405 src : R(read);
4406 IALU : R;
4407 %}
4408
4409 // Integer ALU reg conditional operation
4410 // This instruction has a 1 cycle stall, and cannot execute
4411 // in the same cycle as the instruction setting the condition
4412 // code. We kludge this by pretending to read the condition code
4413 // 1 cycle earlier, and by marking the functional units as busy
4414 // for 2 cycles with the result available 1 cycle later than
4415 // is really the case.
4416 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4417 single_instruction;
4418 op2_out : C(write);
4419 op1 : R(read);
4420 cr : R(read); // This is really E, with a 1 cycle stall
4421 BR : R(2);
4422 MS : R(2);
4423 %}
4424
4425 #ifdef _LP64
4426 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4427 instruction_count(1); multiple_bundles;
4428 dst : C(write)+1;
4429 src : R(read)+1;
4430 IALU : R(1);
4431 BR : E(2);
4432 MS : E(2);
4433 %}
4434 #endif
4435
4436 // Integer ALU reg operation
4437 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4438 single_instruction; may_have_no_code;
4439 dst : E(write);
4440 src : R(read);
4441 IALU : R;
4442 %}
4443 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4444 single_instruction; may_have_no_code;
4445 dst : E(write);
4446 src : R(read);
4447 IALU : R;
4448 %}
4449
4450 // Two integer ALU reg operations
4451 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4452 instruction_count(2);
4453 dst : E(write);
4454 src : R(read);
4455 A0 : R;
4456 A1 : R;
4457 %}
4458
4459 // Two integer ALU reg operations
4460 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4461 instruction_count(2); may_have_no_code;
4462 dst : E(write);
4463 src : R(read);
4464 A0 : R;
4465 A1 : R;
4466 %}
4467
4468 // Integer ALU imm operation
4469 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4470 single_instruction;
4471 dst : E(write);
4472 IALU : R;
4473 %}
4474
4475 // Integer ALU reg-reg with carry operation
4476 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4477 single_instruction;
4478 dst : E(write);
4479 src1 : R(read);
4480 src2 : R(read);
4481 IALU : R;
4482 %}
4483
4484 // Integer ALU cc operation
4485 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4486 single_instruction;
4487 dst : E(write);
4488 cc : R(read);
4489 IALU : R;
4490 %}
4491
4492 // Integer ALU cc / second IALU operation
4493 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4494 instruction_count(1); multiple_bundles;
4495 dst : E(write)+1;
4496 src : R(read);
4497 IALU : R;
4498 %}
4499
4500 // Integer ALU cc / second IALU operation
4501 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4502 instruction_count(1); multiple_bundles;
4503 dst : E(write)+1;
4504 p : R(read);
4505 q : R(read);
4506 IALU : R;
4507 %}
4508
4509 // Integer ALU hi-lo-reg operation
4510 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4511 instruction_count(1); multiple_bundles;
4512 dst : E(write)+1;
4513 IALU : R(2);
4514 %}
4515
4516 // Float ALU hi-lo-reg operation (with temp)
4517 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4518 instruction_count(1); multiple_bundles;
4519 dst : E(write)+1;
4520 IALU : R(2);
4521 %}
4522
4523 // Long Constant
4524 pipe_class loadConL( iRegL dst, immL src ) %{
4525 instruction_count(2); multiple_bundles;
4526 dst : E(write)+1;
4527 IALU : R(2);
4528 IALU : R(2);
4529 %}
4530
4531 // Pointer Constant
4532 pipe_class loadConP( iRegP dst, immP src ) %{
4533 instruction_count(0); multiple_bundles;
4534 fixed_latency(6);
4535 %}
4536
4537 // Polling Address
4538 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4539 #ifdef _LP64
4540 instruction_count(0); multiple_bundles;
4541 fixed_latency(6);
4542 #else
4543 dst : E(write);
4544 IALU : R;
4545 #endif
4546 %}
4547
4548 // Long Constant small
4549 pipe_class loadConLlo( iRegL dst, immL src ) %{
4550 instruction_count(2);
4551 dst : E(write);
4552 IALU : R;
4553 IALU : R;
4554 %}
4555
4556 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4557 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4558 instruction_count(1); multiple_bundles;
4559 src : R(read);
4560 dst : M(write)+1;
4561 IALU : R;
4562 MS : E;
4563 %}
4564
4565 // Integer ALU nop operation
4566 pipe_class ialu_nop() %{
4567 single_instruction;
4568 IALU : R;
4569 %}
4570
4571 // Integer ALU nop operation
4572 pipe_class ialu_nop_A0() %{
4573 single_instruction;
4574 A0 : R;
4575 %}
4576
4577 // Integer ALU nop operation
4578 pipe_class ialu_nop_A1() %{
4579 single_instruction;
4580 A1 : R;
4581 %}
4582
4583 // Integer Multiply reg-reg operation
4584 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4585 single_instruction;
4586 dst : E(write);
4587 src1 : R(read);
4588 src2 : R(read);
4589 MS : R(5);
4590 %}
4591
4592 // Integer Multiply reg-imm operation
4593 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4594 single_instruction;
4595 dst : E(write);
4596 src1 : R(read);
4597 MS : R(5);
4598 %}
4599
4600 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4601 single_instruction;
4602 dst : E(write)+4;
4603 src1 : R(read);
4604 src2 : R(read);
4605 MS : R(6);
4606 %}
4607
4608 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4609 single_instruction;
4610 dst : E(write)+4;
4611 src1 : R(read);
4612 MS : R(6);
4613 %}
4614
4615 // Integer Divide reg-reg
4616 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4617 instruction_count(1); multiple_bundles;
4618 dst : E(write);
4619 temp : E(write);
4620 src1 : R(read);
4621 src2 : R(read);
4622 temp : R(read);
4623 MS : R(38);
4624 %}
4625
4626 // Integer Divide reg-imm
4627 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4628 instruction_count(1); multiple_bundles;
4629 dst : E(write);
4630 temp : E(write);
4631 src1 : R(read);
4632 temp : R(read);
4633 MS : R(38);
4634 %}
4635
4636 // Long Divide
4637 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4638 dst : E(write)+71;
4639 src1 : R(read);
4640 src2 : R(read)+1;
4641 MS : R(70);
4642 %}
4643
4644 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4645 dst : E(write)+71;
4646 src1 : R(read);
4647 MS : R(70);
4648 %}
4649
4650 // Floating Point Add Float
4651 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4652 single_instruction;
4653 dst : X(write);
4654 src1 : E(read);
4655 src2 : E(read);
4656 FA : R;
4657 %}
4658
4659 // Floating Point Add Double
4660 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4661 single_instruction;
4662 dst : X(write);
4663 src1 : E(read);
4664 src2 : E(read);
4665 FA : R;
4666 %}
4667
4668 // Floating Point Conditional Move based on integer flags
4669 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4670 single_instruction;
4671 dst : X(write);
4672 src : E(read);
4673 cr : R(read);
4674 FA : R(2);
4675 BR : R(2);
4676 %}
4677
4678 // Floating Point Conditional Move based on integer flags
4679 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4680 single_instruction;
4681 dst : X(write);
4682 src : E(read);
4683 cr : R(read);
4684 FA : R(2);
4685 BR : R(2);
4686 %}
4687
4688 // Floating Point Multiply Float
4689 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4690 single_instruction;
4691 dst : X(write);
4692 src1 : E(read);
4693 src2 : E(read);
4694 FM : R;
4695 %}
4696
4697 // Floating Point Multiply Double
4698 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4699 single_instruction;
4700 dst : X(write);
4701 src1 : E(read);
4702 src2 : E(read);
4703 FM : R;
4704 %}
4705
4706 // Floating Point Divide Float
4707 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4708 single_instruction;
4709 dst : X(write);
4710 src1 : E(read);
4711 src2 : E(read);
4712 FM : R;
4713 FDIV : C(14);
4714 %}
4715
4716 // Floating Point Divide Double
4717 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4718 single_instruction;
4719 dst : X(write);
4720 src1 : E(read);
4721 src2 : E(read);
4722 FM : R;
4723 FDIV : C(17);
4724 %}
4725
4726 // Floating Point Move/Negate/Abs Float
4727 pipe_class faddF_reg(regF dst, regF src) %{
4728 single_instruction;
4729 dst : W(write);
4730 src : E(read);
4731 FA : R(1);
4732 %}
4733
4734 // Floating Point Move/Negate/Abs Double
4735 pipe_class faddD_reg(regD dst, regD src) %{
4736 single_instruction;
4737 dst : W(write);
4738 src : E(read);
4739 FA : R;
4740 %}
4741
4742 // Floating Point Convert F->D
4743 pipe_class fcvtF2D(regD dst, regF src) %{
4744 single_instruction;
4745 dst : X(write);
4746 src : E(read);
4747 FA : R;
4748 %}
4749
4750 // Floating Point Convert I->D
4751 pipe_class fcvtI2D(regD dst, regF src) %{
4752 single_instruction;
4753 dst : X(write);
4754 src : E(read);
4755 FA : R;
4756 %}
4757
4758 // Floating Point Convert LHi->D
4759 pipe_class fcvtLHi2D(regD dst, regD src) %{
4760 single_instruction;
4761 dst : X(write);
4762 src : E(read);
4763 FA : R;
4764 %}
4765
4766 // Floating Point Convert L->D
4767 pipe_class fcvtL2D(regD dst, regF src) %{
4768 single_instruction;
4769 dst : X(write);
4770 src : E(read);
4771 FA : R;
4772 %}
4773
4774 // Floating Point Convert L->F
4775 pipe_class fcvtL2F(regD dst, regF src) %{
4776 single_instruction;
4777 dst : X(write);
4778 src : E(read);
4779 FA : R;
4780 %}
4781
4782 // Floating Point Convert D->F
4783 pipe_class fcvtD2F(regD dst, regF src) %{
4784 single_instruction;
4785 dst : X(write);
4786 src : E(read);
4787 FA : R;
4788 %}
4789
4790 // Floating Point Convert I->L
4791 pipe_class fcvtI2L(regD dst, regF src) %{
4792 single_instruction;
4793 dst : X(write);
4794 src : E(read);
4795 FA : R;
4796 %}
4797
4798 // Floating Point Convert D->F
4799 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4800 instruction_count(1); multiple_bundles;
4801 dst : X(write)+6;
4802 src : E(read);
4803 FA : R;
4804 %}
4805
4806 // Floating Point Convert D->L
4807 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4808 instruction_count(1); multiple_bundles;
4809 dst : X(write)+6;
4810 src : E(read);
4811 FA : R;
4812 %}
4813
4814 // Floating Point Convert F->I
4815 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4816 instruction_count(1); multiple_bundles;
4817 dst : X(write)+6;
4818 src : E(read);
4819 FA : R;
4820 %}
4821
4822 // Floating Point Convert F->L
4823 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4824 instruction_count(1); multiple_bundles;
4825 dst : X(write)+6;
4826 src : E(read);
4827 FA : R;
4828 %}
4829
4830 // Floating Point Convert I->F
4831 pipe_class fcvtI2F(regF dst, regF src) %{
4832 single_instruction;
4833 dst : X(write);
4834 src : E(read);
4835 FA : R;
4836 %}
4837
4838 // Floating Point Compare
4839 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4840 single_instruction;
4841 cr : X(write);
4842 src1 : E(read);
4843 src2 : E(read);
4844 FA : R;
4845 %}
4846
4847 // Floating Point Compare
4848 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4849 single_instruction;
4850 cr : X(write);
4851 src1 : E(read);
4852 src2 : E(read);
4853 FA : R;
4854 %}
4855
4856 // Floating Add Nop
4857 pipe_class fadd_nop() %{
4858 single_instruction;
4859 FA : R;
4860 %}
4861
4862 // Integer Store to Memory
4863 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4864 single_instruction;
4865 mem : R(read);
4866 src : C(read);
4867 MS : R;
4868 %}
4869
4870 // Integer Store to Memory
4871 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4872 single_instruction;
4873 mem : R(read);
4874 src : C(read);
4875 MS : R;
4876 %}
4877
4878 // Integer Store Zero to Memory
4879 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4880 single_instruction;
4881 mem : R(read);
4882 MS : R;
4883 %}
4884
4885 // Special Stack Slot Store
4886 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4887 single_instruction;
4888 stkSlot : R(read);
4889 src : C(read);
4890 MS : R;
4891 %}
4892
4893 // Special Stack Slot Store
4894 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4895 instruction_count(2); multiple_bundles;
4896 stkSlot : R(read);
4897 src : C(read);
4898 MS : R(2);
4899 %}
4900
4901 // Float Store
4902 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4903 single_instruction;
4904 mem : R(read);
4905 src : C(read);
4906 MS : R;
4907 %}
4908
4909 // Float Store
4910 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4911 single_instruction;
4912 mem : R(read);
4913 MS : R;
4914 %}
4915
4916 // Double Store
4917 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
4918 instruction_count(1);
4919 mem : R(read);
4920 src : C(read);
4921 MS : R;
4922 %}
4923
4924 // Double Store
4925 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
4926 single_instruction;
4927 mem : R(read);
4928 MS : R;
4929 %}
4930
4931 // Special Stack Slot Float Store
4932 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
4933 single_instruction;
4934 stkSlot : R(read);
4935 src : C(read);
4936 MS : R;
4937 %}
4938
4939 // Special Stack Slot Double Store
4940 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
4941 single_instruction;
4942 stkSlot : R(read);
4943 src : C(read);
4944 MS : R;
4945 %}
4946
4947 // Integer Load (when sign bit propagation not needed)
4948 pipe_class iload_mem(iRegI dst, memory mem) %{
4949 single_instruction;
4950 mem : R(read);
4951 dst : C(write);
4952 MS : R;
4953 %}
4954
4955 // Integer Load from stack operand
4956 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
4957 single_instruction;
4958 mem : R(read);
4959 dst : C(write);
4960 MS : R;
4961 %}
4962
4963 // Integer Load (when sign bit propagation or masking is needed)
4964 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
4965 single_instruction;
4966 mem : R(read);
4967 dst : M(write);
4968 MS : R;
4969 %}
4970
4971 // Float Load
4972 pipe_class floadF_mem(regF dst, memory mem) %{
4973 single_instruction;
4974 mem : R(read);
4975 dst : M(write);
4976 MS : R;
4977 %}
4978
4979 // Float Load
4980 pipe_class floadD_mem(regD dst, memory mem) %{
4981 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
4982 mem : R(read);
4983 dst : M(write);
4984 MS : R;
4985 %}
4986
4987 // Float Load
4988 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
4989 single_instruction;
4990 stkSlot : R(read);
4991 dst : M(write);
4992 MS : R;
4993 %}
4994
4995 // Float Load
4996 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
4997 single_instruction;
4998 stkSlot : R(read);
4999 dst : M(write);
5000 MS : R;
5001 %}
5002
5003 // Memory Nop
5004 pipe_class mem_nop() %{
5005 single_instruction;
5006 MS : R;
5007 %}
5008
5009 pipe_class sethi(iRegP dst, immI src) %{
5010 single_instruction;
5011 dst : E(write);
5012 IALU : R;
5013 %}
5014
5015 pipe_class loadPollP(iRegP poll) %{
5016 single_instruction;
5017 poll : R(read);
5018 MS : R;
5019 %}
5020
5021 pipe_class br(Universe br, label labl) %{
5022 single_instruction_with_delay_slot;
5023 BR : R;
5024 %}
5025
5026 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5027 single_instruction_with_delay_slot;
5028 cr : E(read);
5029 BR : R;
5030 %}
5031
5032 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5033 single_instruction_with_delay_slot;
5034 op1 : E(read);
5035 BR : R;
5036 MS : R;
5037 %}
5038
5039 // Compare and branch
5040 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5041 instruction_count(2); has_delay_slot;
5042 cr : E(write);
5043 src1 : R(read);
5044 src2 : R(read);
5045 IALU : R;
5046 BR : R;
5047 %}
5048
5049 // Compare and branch
5050 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5051 instruction_count(2); has_delay_slot;
5052 cr : E(write);
5053 src1 : R(read);
5054 IALU : R;
5055 BR : R;
5056 %}
5057
5058 // Compare and branch using cbcond
5059 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5060 single_instruction;
5061 src1 : E(read);
5062 src2 : E(read);
5063 IALU : R;
5064 BR : R;
5065 %}
5066
5067 // Compare and branch using cbcond
5068 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5069 single_instruction;
5070 src1 : E(read);
5071 IALU : R;
5072 BR : R;
5073 %}
5074
5075 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5076 single_instruction_with_delay_slot;
5077 cr : E(read);
5078 BR : R;
5079 %}
5080
5081 pipe_class br_nop() %{
5082 single_instruction;
5083 BR : R;
5084 %}
5085
5086 pipe_class simple_call(method meth) %{
5087 instruction_count(2); multiple_bundles; force_serialization;
5088 fixed_latency(100);
5089 BR : R(1);
5090 MS : R(1);
5091 A0 : R(1);
5092 %}
5093
5094 pipe_class compiled_call(method meth) %{
5095 instruction_count(1); multiple_bundles; force_serialization;
5096 fixed_latency(100);
5097 MS : R(1);
5098 %}
5099
5100 pipe_class call(method meth) %{
5101 instruction_count(0); multiple_bundles; force_serialization;
5102 fixed_latency(100);
5103 %}
5104
5105 pipe_class tail_call(Universe ignore, label labl) %{
5106 single_instruction; has_delay_slot;
5107 fixed_latency(100);
5108 BR : R(1);
5109 MS : R(1);
5110 %}
5111
5112 pipe_class ret(Universe ignore) %{
5113 single_instruction; has_delay_slot;
5114 BR : R(1);
5115 MS : R(1);
5116 %}
5117
5118 pipe_class ret_poll(g3RegP poll) %{
5119 instruction_count(3); has_delay_slot;
5120 poll : E(read);
5121 MS : R;
5122 %}
5123
5124 // The real do-nothing guy
5125 pipe_class empty( ) %{
5126 instruction_count(0);
5127 %}
5128
5129 pipe_class long_memory_op() %{
5130 instruction_count(0); multiple_bundles; force_serialization;
5131 fixed_latency(25);
5132 MS : R(1);
5133 %}
5134
5135 // Check-cast
5136 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5137 array : R(read);
5138 match : R(read);
5139 IALU : R(2);
5140 BR : R(2);
5141 MS : R;
5142 %}
5143
5144 // Convert FPU flags into +1,0,-1
5145 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5146 src1 : E(read);
5147 src2 : E(read);
5148 dst : E(write);
5149 FA : R;
5150 MS : R(2);
5151 BR : R(2);
5152 %}
5153
5154 // Compare for p < q, and conditionally add y
5155 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5156 p : E(read);
5157 q : E(read);
5158 y : E(read);
5159 IALU : R(3)
5160 %}
5161
5162 // Perform a compare, then move conditionally in a branch delay slot.
5163 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5164 src2 : E(read);
5165 srcdst : E(read);
5166 IALU : R;
5167 BR : R;
5168 %}
5169
5170 // Define the class for the Nop node
5171 define %{
5172 MachNop = ialu_nop;
5173 %}
5174
5175 %}
5176
5177 //----------INSTRUCTIONS-------------------------------------------------------
5178
5179 //------------Special Stack Slot instructions - no match rules-----------------
5180 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5181 // No match rule to avoid chain rule match.
5182 effect(DEF dst, USE src);
5183 ins_cost(MEMORY_REF_COST);
5184 size(4);
5185 format %{ "LDF $src,$dst\t! stkI to regF" %}
5186 opcode(Assembler::ldf_op3);
5187 ins_encode(simple_form3_mem_reg(src, dst));
5188 ins_pipe(floadF_stk);
5189 %}
5190
5191 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5192 // No match rule to avoid chain rule match.
5193 effect(DEF dst, USE src);
5194 ins_cost(MEMORY_REF_COST);
5195 size(4);
5196 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5197 opcode(Assembler::lddf_op3);
5198 ins_encode(simple_form3_mem_reg(src, dst));
5199 ins_pipe(floadD_stk);
5200 %}
5201
5202 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5203 // No match rule to avoid chain rule match.
5204 effect(DEF dst, USE src);
5205 ins_cost(MEMORY_REF_COST);
5206 size(4);
5207 format %{ "STF $src,$dst\t! regF to stkI" %}
5208 opcode(Assembler::stf_op3);
5209 ins_encode(simple_form3_mem_reg(dst, src));
5210 ins_pipe(fstoreF_stk_reg);
5211 %}
5212
5213 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5214 // No match rule to avoid chain rule match.
5215 effect(DEF dst, USE src);
5216 ins_cost(MEMORY_REF_COST);
5217 size(4);
5218 format %{ "STDF $src,$dst\t! regD to stkL" %}
5219 opcode(Assembler::stdf_op3);
5220 ins_encode(simple_form3_mem_reg(dst, src));
5221 ins_pipe(fstoreD_stk_reg);
5222 %}
5223
5224 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5225 effect(DEF dst, USE src);
5226 ins_cost(MEMORY_REF_COST*2);
5227 size(8);
5228 format %{ "STW $src,$dst.hi\t! long\n\t"
5229 "STW R_G0,$dst.lo" %}
5230 opcode(Assembler::stw_op3);
5231 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5232 ins_pipe(lstoreI_stk_reg);
5233 %}
5234
5235 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5236 // No match rule to avoid chain rule match.
5237 effect(DEF dst, USE src);
5238 ins_cost(MEMORY_REF_COST);
5239 size(4);
5240 format %{ "STX $src,$dst\t! regL to stkD" %}
5241 opcode(Assembler::stx_op3);
5242 ins_encode(simple_form3_mem_reg( dst, src ) );
5243 ins_pipe(istore_stk_reg);
5244 %}
5245
5246 //---------- Chain stack slots between similar types --------
5247
5248 // Load integer from stack slot
5249 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5250 match(Set dst src);
5251 ins_cost(MEMORY_REF_COST);
5252
5253 size(4);
5254 format %{ "LDUW $src,$dst\t!stk" %}
5255 opcode(Assembler::lduw_op3);
5256 ins_encode(simple_form3_mem_reg( src, dst ) );
5257 ins_pipe(iload_mem);
5258 %}
5259
5260 // Store integer to stack slot
5261 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5262 match(Set dst src);
5263 ins_cost(MEMORY_REF_COST);
5264
5265 size(4);
5266 format %{ "STW $src,$dst\t!stk" %}
5267 opcode(Assembler::stw_op3);
5268 ins_encode(simple_form3_mem_reg( dst, src ) );
5269 ins_pipe(istore_mem_reg);
5270 %}
5271
5272 // Load long from stack slot
5273 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5274 match(Set dst src);
5275
5276 ins_cost(MEMORY_REF_COST);
5277 size(4);
5278 format %{ "LDX $src,$dst\t! long" %}
5279 opcode(Assembler::ldx_op3);
5280 ins_encode(simple_form3_mem_reg( src, dst ) );
5281 ins_pipe(iload_mem);
5282 %}
5283
5284 // Store long to stack slot
5285 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5286 match(Set dst src);
5287
5288 ins_cost(MEMORY_REF_COST);
5289 size(4);
5290 format %{ "STX $src,$dst\t! long" %}
5291 opcode(Assembler::stx_op3);
5292 ins_encode(simple_form3_mem_reg( dst, src ) );
5293 ins_pipe(istore_mem_reg);
5294 %}
5295
5296 #ifdef _LP64
5297 // Load pointer from stack slot, 64-bit encoding
5298 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5299 match(Set dst src);
5300 ins_cost(MEMORY_REF_COST);
5301 size(4);
5302 format %{ "LDX $src,$dst\t!ptr" %}
5303 opcode(Assembler::ldx_op3);
5304 ins_encode(simple_form3_mem_reg( src, dst ) );
5305 ins_pipe(iload_mem);
5306 %}
5307
5308 // Store pointer to stack slot
5309 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5310 match(Set dst src);
5311 ins_cost(MEMORY_REF_COST);
5312 size(4);
5313 format %{ "STX $src,$dst\t!ptr" %}
5314 opcode(Assembler::stx_op3);
5315 ins_encode(simple_form3_mem_reg( dst, src ) );
5316 ins_pipe(istore_mem_reg);
5317 %}
5318 #else // _LP64
5319 // Load pointer from stack slot, 32-bit encoding
5320 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5321 match(Set dst src);
5322 ins_cost(MEMORY_REF_COST);
5323 format %{ "LDUW $src,$dst\t!ptr" %}
5324 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5325 ins_encode(simple_form3_mem_reg( src, dst ) );
5326 ins_pipe(iload_mem);
5327 %}
5328
5329 // Store pointer to stack slot
5330 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5331 match(Set dst src);
5332 ins_cost(MEMORY_REF_COST);
5333 format %{ "STW $src,$dst\t!ptr" %}
5334 opcode(Assembler::stw_op3, Assembler::ldst_op);
5335 ins_encode(simple_form3_mem_reg( dst, src ) );
5336 ins_pipe(istore_mem_reg);
5337 %}
5338 #endif // _LP64
5339
5340 //------------Special Nop instructions for bundling - no match rules-----------
5341 // Nop using the A0 functional unit
5342 instruct Nop_A0() %{
5343 ins_cost(0);
5344
5345 format %{ "NOP ! Alu Pipeline" %}
5346 opcode(Assembler::or_op3, Assembler::arith_op);
5347 ins_encode( form2_nop() );
5348 ins_pipe(ialu_nop_A0);
5349 %}
5350
5351 // Nop using the A1 functional unit
5352 instruct Nop_A1( ) %{
5353 ins_cost(0);
5354
5355 format %{ "NOP ! Alu Pipeline" %}
5356 opcode(Assembler::or_op3, Assembler::arith_op);
5357 ins_encode( form2_nop() );
5358 ins_pipe(ialu_nop_A1);
5359 %}
5360
5361 // Nop using the memory functional unit
5362 instruct Nop_MS( ) %{
5363 ins_cost(0);
5364
5365 format %{ "NOP ! Memory Pipeline" %}
5366 ins_encode( emit_mem_nop );
5367 ins_pipe(mem_nop);
5368 %}
5369
5370 // Nop using the floating add functional unit
5371 instruct Nop_FA( ) %{
5372 ins_cost(0);
5373
5374 format %{ "NOP ! Floating Add Pipeline" %}
5375 ins_encode( emit_fadd_nop );
5376 ins_pipe(fadd_nop);
5377 %}
5378
5379 // Nop using the branch functional unit
5380 instruct Nop_BR( ) %{
5381 ins_cost(0);
5382
5383 format %{ "NOP ! Branch Pipeline" %}
5384 ins_encode( emit_br_nop );
5385 ins_pipe(br_nop);
5386 %}
5387
5388 //----------Load/Store/Move Instructions---------------------------------------
5389 //----------Load Instructions--------------------------------------------------
5390 // Load Byte (8bit signed)
5391 instruct loadB(iRegI dst, memory mem) %{
5392 match(Set dst (LoadB mem));
5393 ins_cost(MEMORY_REF_COST);
5394
5395 size(4);
5396 format %{ "LDSB $mem,$dst\t! byte" %}
5397 ins_encode %{
5398 __ ldsb($mem$$Address, $dst$$Register);
5399 %}
5400 ins_pipe(iload_mask_mem);
5401 %}
5402
5403 // Load Byte (8bit signed) into a Long Register
5404 instruct loadB2L(iRegL dst, memory mem) %{
5405 match(Set dst (ConvI2L (LoadB mem)));
5406 ins_cost(MEMORY_REF_COST);
5407
5408 size(4);
5409 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5410 ins_encode %{
5411 __ ldsb($mem$$Address, $dst$$Register);
5412 %}
5413 ins_pipe(iload_mask_mem);
5414 %}
5415
5416 // Load Unsigned Byte (8bit UNsigned) into an int reg
5417 instruct loadUB(iRegI dst, memory mem) %{
5418 match(Set dst (LoadUB mem));
5419 ins_cost(MEMORY_REF_COST);
5420
5421 size(4);
5422 format %{ "LDUB $mem,$dst\t! ubyte" %}
5423 ins_encode %{
5424 __ ldub($mem$$Address, $dst$$Register);
5425 %}
5426 ins_pipe(iload_mem);
5427 %}
5428
5429 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5430 instruct loadUB2L(iRegL dst, memory mem) %{
5431 match(Set dst (ConvI2L (LoadUB mem)));
5432 ins_cost(MEMORY_REF_COST);
5433
5434 size(4);
5435 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5436 ins_encode %{
5437 __ ldub($mem$$Address, $dst$$Register);
5438 %}
5439 ins_pipe(iload_mem);
5440 %}
5441
5442 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5443 instruct loadUB2L_immI(iRegL dst, memory mem, immI mask) %{
5444 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5445 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5446
5447 size(2*4);
5448 format %{ "LDUB $mem,$dst\t# ubyte & 32-bit mask -> long\n\t"
5449 "AND $dst,right_n_bits($mask, 8),$dst" %}
5450 ins_encode %{
5451 __ ldub($mem$$Address, $dst$$Register);
5452 __ and3($dst$$Register, $mask$$constant & right_n_bits(8), $dst$$Register);
5453 %}
5454 ins_pipe(iload_mem);
5455 %}
5456
5457 // Load Short (16bit signed)
5458 instruct loadS(iRegI dst, memory mem) %{
5459 match(Set dst (LoadS mem));
5460 ins_cost(MEMORY_REF_COST);
5461
5462 size(4);
5463 format %{ "LDSH $mem,$dst\t! short" %}
5464 ins_encode %{
5465 __ ldsh($mem$$Address, $dst$$Register);
5466 %}
5467 ins_pipe(iload_mask_mem);
5468 %}
5469
5470 // Load Short (16 bit signed) to Byte (8 bit signed)
5471 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5472 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5473 ins_cost(MEMORY_REF_COST);
5474
5475 size(4);
5476
5477 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5478 ins_encode %{
5479 __ ldsb($mem$$Address, $dst$$Register, 1);
5480 %}
5481 ins_pipe(iload_mask_mem);
5482 %}
5483
5484 // Load Short (16bit signed) into a Long Register
5485 instruct loadS2L(iRegL dst, memory mem) %{
5486 match(Set dst (ConvI2L (LoadS mem)));
5487 ins_cost(MEMORY_REF_COST);
5488
5489 size(4);
5490 format %{ "LDSH $mem,$dst\t! short -> long" %}
5491 ins_encode %{
5492 __ ldsh($mem$$Address, $dst$$Register);
5493 %}
5494 ins_pipe(iload_mask_mem);
5495 %}
5496
5497 // Load Unsigned Short/Char (16bit UNsigned)
5498 instruct loadUS(iRegI dst, memory mem) %{
5499 match(Set dst (LoadUS mem));
5500 ins_cost(MEMORY_REF_COST);
5501
5502 size(4);
5503 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5504 ins_encode %{
5505 __ lduh($mem$$Address, $dst$$Register);
5506 %}
5507 ins_pipe(iload_mem);
5508 %}
5509
5510 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5511 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5512 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5513 ins_cost(MEMORY_REF_COST);
5514
5515 size(4);
5516 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5517 ins_encode %{
5518 __ ldsb($mem$$Address, $dst$$Register, 1);
5519 %}
5520 ins_pipe(iload_mask_mem);
5521 %}
5522
5523 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5524 instruct loadUS2L(iRegL dst, memory mem) %{
5525 match(Set dst (ConvI2L (LoadUS mem)));
5526 ins_cost(MEMORY_REF_COST);
5527
5528 size(4);
5529 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5530 ins_encode %{
5531 __ lduh($mem$$Address, $dst$$Register);
5532 %}
5533 ins_pipe(iload_mem);
5534 %}
5535
5536 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5537 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5538 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5539 ins_cost(MEMORY_REF_COST);
5540
5541 size(4);
5542 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5543 ins_encode %{
5544 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5545 %}
5546 ins_pipe(iload_mem);
5547 %}
5548
5549 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5550 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5551 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5552 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5553
5554 size(2*4);
5555 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5556 "AND $dst,$mask,$dst" %}
5557 ins_encode %{
5558 Register Rdst = $dst$$Register;
5559 __ lduh($mem$$Address, Rdst);
5560 __ and3(Rdst, $mask$$constant, Rdst);
5561 %}
5562 ins_pipe(iload_mem);
5563 %}
5564
5565 // Load Unsigned Short/Char (16bit UNsigned) with a 32-bit mask into a Long Register
5566 instruct loadUS2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5567 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5568 effect(TEMP dst, TEMP tmp);
5569 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5570
5571 format %{ "LDUH $mem,$dst\t! ushort/char & 32-bit mask -> long\n\t"
5572 "SET right_n_bits($mask, 16),$tmp\n\t"
5573 "AND $dst,$tmp,$dst" %}
5574 ins_encode %{
5575 Register Rdst = $dst$$Register;
5576 Register Rtmp = $tmp$$Register;
5577 __ lduh($mem$$Address, Rdst);
5578 __ set($mask$$constant & right_n_bits(16), Rtmp);
5579 __ and3(Rdst, Rtmp, Rdst);
5580 %}
5581 ins_pipe(iload_mem);
5582 %}
5583
5584 // Load Integer
5585 instruct loadI(iRegI dst, memory mem) %{
5586 match(Set dst (LoadI mem));
5587 ins_cost(MEMORY_REF_COST);
5588
5589 size(4);
5590 format %{ "LDUW $mem,$dst\t! int" %}
5591 ins_encode %{
5592 __ lduw($mem$$Address, $dst$$Register);
5593 %}
5594 ins_pipe(iload_mem);
5595 %}
5596
5597 // Load Integer to Byte (8 bit signed)
5598 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5599 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5600 ins_cost(MEMORY_REF_COST);
5601
5602 size(4);
5603
5604 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5605 ins_encode %{
5606 __ ldsb($mem$$Address, $dst$$Register, 3);
5607 %}
5608 ins_pipe(iload_mask_mem);
5609 %}
5610
5611 // Load Integer to Unsigned Byte (8 bit UNsigned)
5612 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5613 match(Set dst (AndI (LoadI mem) mask));
5614 ins_cost(MEMORY_REF_COST);
5615
5616 size(4);
5617
5618 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5619 ins_encode %{
5620 __ ldub($mem$$Address, $dst$$Register, 3);
5621 %}
5622 ins_pipe(iload_mask_mem);
5623 %}
5624
5625 // Load Integer to Short (16 bit signed)
5626 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5627 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5628 ins_cost(MEMORY_REF_COST);
5629
5630 size(4);
5631
5632 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5633 ins_encode %{
5634 __ ldsh($mem$$Address, $dst$$Register, 2);
5635 %}
5636 ins_pipe(iload_mask_mem);
5637 %}
5638
5639 // Load Integer to Unsigned Short (16 bit UNsigned)
5640 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5641 match(Set dst (AndI (LoadI mem) mask));
5642 ins_cost(MEMORY_REF_COST);
5643
5644 size(4);
5645
5646 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5647 ins_encode %{
5648 __ lduh($mem$$Address, $dst$$Register, 2);
5649 %}
5650 ins_pipe(iload_mask_mem);
5651 %}
5652
5653 // Load Integer into a Long Register
5654 instruct loadI2L(iRegL dst, memory mem) %{
5655 match(Set dst (ConvI2L (LoadI mem)));
5656 ins_cost(MEMORY_REF_COST);
5657
5658 size(4);
5659 format %{ "LDSW $mem,$dst\t! int -> long" %}
5660 ins_encode %{
5661 __ ldsw($mem$$Address, $dst$$Register);
5662 %}
5663 ins_pipe(iload_mask_mem);
5664 %}
5665
5666 // Load Integer with mask 0xFF into a Long Register
5667 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5668 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5669 ins_cost(MEMORY_REF_COST);
5670
5671 size(4);
5672 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5673 ins_encode %{
5674 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5675 %}
5676 ins_pipe(iload_mem);
5677 %}
5678
5679 // Load Integer with mask 0xFFFF into a Long Register
5680 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5681 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5682 ins_cost(MEMORY_REF_COST);
5683
5684 size(4);
5685 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5686 ins_encode %{
5687 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5688 %}
5689 ins_pipe(iload_mem);
5690 %}
5691
5692 // Load Integer with a 12-bit mask into a Long Register
5693 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5694 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5695 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5696
5697 size(2*4);
5698 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t"
5699 "AND $dst,$mask,$dst" %}
5700 ins_encode %{
5701 Register Rdst = $dst$$Register;
5702 __ lduw($mem$$Address, Rdst);
5703 __ and3(Rdst, $mask$$constant, Rdst);
5704 %}
5705 ins_pipe(iload_mem);
5706 %}
5707
5708 // Load Integer with a 31-bit mask into a Long Register
5709 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5710 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5711 effect(TEMP dst, TEMP tmp);
5712 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5713
5714 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t"
5715 "SET $mask,$tmp\n\t"
5716 "AND $dst,$tmp,$dst" %}
5717 ins_encode %{
5718 Register Rdst = $dst$$Register;
5719 Register Rtmp = $tmp$$Register;
5720 __ lduw($mem$$Address, Rdst);
5721 __ set($mask$$constant, Rtmp);
5722 __ and3(Rdst, Rtmp, Rdst);
5723 %}
5724 ins_pipe(iload_mem);
5725 %}
5726
5727 // Load Unsigned Integer into a Long Register
5728 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5729 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5730 ins_cost(MEMORY_REF_COST);
5731
5732 size(4);
5733 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5734 ins_encode %{
5735 __ lduw($mem$$Address, $dst$$Register);
5736 %}
5737 ins_pipe(iload_mem);
5738 %}
5739
5740 // Load Long - aligned
5741 instruct loadL(iRegL dst, memory mem ) %{
5742 match(Set dst (LoadL mem));
5743 ins_cost(MEMORY_REF_COST);
5744
5745 size(4);
5746 format %{ "LDX $mem,$dst\t! long" %}
5747 ins_encode %{
5748 __ ldx($mem$$Address, $dst$$Register);
5749 %}
5750 ins_pipe(iload_mem);
5751 %}
5752
5753 // Load Long - UNaligned
5754 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5755 match(Set dst (LoadL_unaligned mem));
5756 effect(KILL tmp);
5757 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5758 size(16);
5759 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5760 "\tLDUW $mem ,$dst\n"
5761 "\tSLLX #32, $dst, $dst\n"
5762 "\tOR $dst, R_O7, $dst" %}
5763 opcode(Assembler::lduw_op3);
5764 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5765 ins_pipe(iload_mem);
5766 %}
5767
5768 // Load Range
5769 instruct loadRange(iRegI dst, memory mem) %{
5770 match(Set dst (LoadRange mem));
5771 ins_cost(MEMORY_REF_COST);
5772
5773 size(4);
5774 format %{ "LDUW $mem,$dst\t! range" %}
5775 opcode(Assembler::lduw_op3);
5776 ins_encode(simple_form3_mem_reg( mem, dst ) );
5777 ins_pipe(iload_mem);
5778 %}
5779
5780 // Load Integer into %f register (for fitos/fitod)
5781 instruct loadI_freg(regF dst, memory mem) %{
5782 match(Set dst (LoadI mem));
5783 ins_cost(MEMORY_REF_COST);
5784 size(4);
5785
5786 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5787 opcode(Assembler::ldf_op3);
5788 ins_encode(simple_form3_mem_reg( mem, dst ) );
5789 ins_pipe(floadF_mem);
5790 %}
5791
5792 // Load Pointer
5793 instruct loadP(iRegP dst, memory mem) %{
5794 match(Set dst (LoadP mem));
5795 ins_cost(MEMORY_REF_COST);
5796 size(4);
5797
5798 #ifndef _LP64
5799 format %{ "LDUW $mem,$dst\t! ptr" %}
5800 ins_encode %{
5801 __ lduw($mem$$Address, $dst$$Register);
5802 %}
5803 #else
5804 format %{ "LDX $mem,$dst\t! ptr" %}
5805 ins_encode %{
5806 __ ldx($mem$$Address, $dst$$Register);
5807 %}
5808 #endif
5809 ins_pipe(iload_mem);
5810 %}
5811
5812 // Load Compressed Pointer
5813 instruct loadN(iRegN dst, memory mem) %{
5814 match(Set dst (LoadN mem));
5815 ins_cost(MEMORY_REF_COST);
5816 size(4);
5817
5818 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5819 ins_encode %{
5820 __ lduw($mem$$Address, $dst$$Register);
5821 %}
5822 ins_pipe(iload_mem);
5823 %}
5824
5825 // Load Klass Pointer
5826 instruct loadKlass(iRegP dst, memory mem) %{
5827 match(Set dst (LoadKlass mem));
5828 ins_cost(MEMORY_REF_COST);
5829 size(4);
5830
5831 #ifndef _LP64
5832 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5833 ins_encode %{
5834 __ lduw($mem$$Address, $dst$$Register);
5835 %}
5836 #else
5837 format %{ "LDX $mem,$dst\t! klass ptr" %}
5838 ins_encode %{
5839 __ ldx($mem$$Address, $dst$$Register);
5840 %}
5841 #endif
5842 ins_pipe(iload_mem);
5843 %}
5844
5845 // Load narrow Klass Pointer
5846 instruct loadNKlass(iRegN dst, memory mem) %{
5847 match(Set dst (LoadNKlass mem));
5848 ins_cost(MEMORY_REF_COST);
5849 size(4);
5850
5851 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5852 ins_encode %{
5853 __ lduw($mem$$Address, $dst$$Register);
5854 %}
5855 ins_pipe(iload_mem);
5856 %}
5857
5858 // Load Double
5859 instruct loadD(regD dst, memory mem) %{
5860 match(Set dst (LoadD mem));
5861 ins_cost(MEMORY_REF_COST);
5862
5863 size(4);
5864 format %{ "LDDF $mem,$dst" %}
5865 opcode(Assembler::lddf_op3);
5866 ins_encode(simple_form3_mem_reg( mem, dst ) );
5867 ins_pipe(floadD_mem);
5868 %}
5869
5870 // Load Double - UNaligned
5871 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5872 match(Set dst (LoadD_unaligned mem));
5873 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5874 size(8);
5875 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5876 "\tLDF $mem+4,$dst.lo\t!" %}
5877 opcode(Assembler::ldf_op3);
5878 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5879 ins_pipe(iload_mem);
5880 %}
5881
5882 // Load Float
5883 instruct loadF(regF dst, memory mem) %{
5884 match(Set dst (LoadF mem));
5885 ins_cost(MEMORY_REF_COST);
5886
5887 size(4);
5888 format %{ "LDF $mem,$dst" %}
5889 opcode(Assembler::ldf_op3);
5890 ins_encode(simple_form3_mem_reg( mem, dst ) );
5891 ins_pipe(floadF_mem);
5892 %}
5893
5894 // Load Constant
5895 instruct loadConI( iRegI dst, immI src ) %{
5896 match(Set dst src);
5897 ins_cost(DEFAULT_COST * 3/2);
5898 format %{ "SET $src,$dst" %}
5899 ins_encode( Set32(src, dst) );
5900 ins_pipe(ialu_hi_lo_reg);
5901 %}
5902
5903 instruct loadConI13( iRegI dst, immI13 src ) %{
5904 match(Set dst src);
5905
5906 size(4);
5907 format %{ "MOV $src,$dst" %}
5908 ins_encode( Set13( src, dst ) );
5909 ins_pipe(ialu_imm);
5910 %}
5911
5912 #ifndef _LP64
5913 instruct loadConP(iRegP dst, immP con) %{
5914 match(Set dst con);
5915 ins_cost(DEFAULT_COST * 3/2);
5916 format %{ "SET $con,$dst\t!ptr" %}
5917 ins_encode %{
5918 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5919 intptr_t val = $con$$constant;
5920 if (constant_reloc == relocInfo::oop_type) {
5921 __ set_oop_constant((jobject) val, $dst$$Register);
5922 } else if (constant_reloc == relocInfo::metadata_type) {
5923 __ set_metadata_constant((Metadata*)val, $dst$$Register);
5924 } else { // non-oop pointers, e.g. card mark base, heap top
5925 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5926 __ set(val, $dst$$Register);
5927 }
5928 %}
5929 ins_pipe(loadConP);
5930 %}
5931 #else
5932 instruct loadConP_set(iRegP dst, immP_set con) %{
5933 match(Set dst con);
5934 ins_cost(DEFAULT_COST * 3/2);
5935 format %{ "SET $con,$dst\t! ptr" %}
5936 ins_encode %{
5937 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5938 intptr_t val = $con$$constant;
5939 if (constant_reloc == relocInfo::oop_type) {
5940 __ set_oop_constant((jobject) val, $dst$$Register);
5941 } else if (constant_reloc == relocInfo::metadata_type) {
5942 __ set_metadata_constant((Metadata*)val, $dst$$Register);
5943 } else { // non-oop pointers, e.g. card mark base, heap top
5944 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5945 __ set(val, $dst$$Register);
5946 }
5947 %}
5948 ins_pipe(loadConP);
5949 %}
5950
5951 instruct loadConP_load(iRegP dst, immP_load con) %{
5952 match(Set dst con);
5953 ins_cost(MEMORY_REF_COST);
5954 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
5955 ins_encode %{
5956 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
5957 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
5958 %}
5959 ins_pipe(loadConP);
5960 %}
5961
5962 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
5963 match(Set dst con);
5964 ins_cost(DEFAULT_COST * 3/2);
5965 format %{ "SET $con,$dst\t! non-oop ptr" %}
5966 ins_encode %{
5967 if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) {
5968 __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register);
5969 } else {
5970 __ set($con$$constant, $dst$$Register);
5971 }
5972 %}
5973 ins_pipe(loadConP);
5974 %}
5975 #endif // _LP64
5976
5977 instruct loadConP0(iRegP dst, immP0 src) %{
5978 match(Set dst src);
5979
5980 size(4);
5981 format %{ "CLR $dst\t!ptr" %}
5982 ins_encode %{
5983 __ clr($dst$$Register);
5984 %}
5985 ins_pipe(ialu_imm);
5986 %}
5987
5988 instruct loadConP_poll(iRegP dst, immP_poll src) %{
5989 match(Set dst src);
5990 ins_cost(DEFAULT_COST);
5991 format %{ "SET $src,$dst\t!ptr" %}
5992 ins_encode %{
5993 AddressLiteral polling_page(os::get_polling_page());
5994 __ sethi(polling_page, reg_to_register_object($dst$$reg));
5995 %}
5996 ins_pipe(loadConP_poll);
5997 %}
5998
5999 instruct loadConN0(iRegN dst, immN0 src) %{
6000 match(Set dst src);
6001
6002 size(4);
6003 format %{ "CLR $dst\t! compressed NULL ptr" %}
6004 ins_encode %{
6005 __ clr($dst$$Register);
6006 %}
6007 ins_pipe(ialu_imm);
6008 %}
6009
6010 instruct loadConN(iRegN dst, immN src) %{
6011 match(Set dst src);
6012 ins_cost(DEFAULT_COST * 3/2);
6013 format %{ "SET $src,$dst\t! compressed ptr" %}
6014 ins_encode %{
6015 Register dst = $dst$$Register;
6016 __ set_narrow_oop((jobject)$src$$constant, dst);
6017 %}
6018 ins_pipe(ialu_hi_lo_reg);
6019 %}
6020
6021 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6022 match(Set dst src);
6023 ins_cost(DEFAULT_COST * 3/2);
6024 format %{ "SET $src,$dst\t! compressed klass ptr" %}
6025 ins_encode %{
6026 Register dst = $dst$$Register;
6027 __ set_narrow_klass((Klass*)$src$$constant, dst);
6028 %}
6029 ins_pipe(ialu_hi_lo_reg);
6030 %}
6031
6032 // Materialize long value (predicated by immL_cheap).
6033 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6034 match(Set dst con);
6035 effect(KILL tmp);
6036 ins_cost(DEFAULT_COST * 3);
6037 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6038 ins_encode %{
6039 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6040 %}
6041 ins_pipe(loadConL);
6042 %}
6043
6044 // Load long value from constant table (predicated by immL_expensive).
6045 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6046 match(Set dst con);
6047 ins_cost(MEMORY_REF_COST);
6048 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6049 ins_encode %{
6050 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6051 __ ldx($constanttablebase, con_offset, $dst$$Register);
6052 %}
6053 ins_pipe(loadConL);
6054 %}
6055
6056 instruct loadConL0( iRegL dst, immL0 src ) %{
6057 match(Set dst src);
6058 ins_cost(DEFAULT_COST);
6059 size(4);
6060 format %{ "CLR $dst\t! long" %}
6061 ins_encode( Set13( src, dst ) );
6062 ins_pipe(ialu_imm);
6063 %}
6064
6065 instruct loadConL13( iRegL dst, immL13 src ) %{
6066 match(Set dst src);
6067 ins_cost(DEFAULT_COST * 2);
6068
6069 size(4);
6070 format %{ "MOV $src,$dst\t! long" %}
6071 ins_encode( Set13( src, dst ) );
6072 ins_pipe(ialu_imm);
6073 %}
6074
6075 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6076 match(Set dst con);
6077 effect(KILL tmp);
6078 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6079 ins_encode %{
6080 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6081 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6082 %}
6083 ins_pipe(loadConFD);
6084 %}
6085
6086 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6087 match(Set dst con);
6088 effect(KILL tmp);
6089 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6090 ins_encode %{
6091 // XXX This is a quick fix for 6833573.
6092 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6093 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6094 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6095 %}
6096 ins_pipe(loadConFD);
6097 %}
6098
6099 // Prefetch instructions for allocation.
6100 // Must be safe to execute with invalid address (cannot fault).
6101
6102 instruct prefetchAlloc( memory mem ) %{
6103 predicate(AllocatePrefetchInstr == 0);
6104 match( PrefetchAllocation mem );
6105 ins_cost(MEMORY_REF_COST);
6106 size(4);
6107
6108 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6109 opcode(Assembler::prefetch_op3);
6110 ins_encode( form3_mem_prefetch_write( mem ) );
6111 ins_pipe(iload_mem);
6112 %}
6113
6114 // Use BIS instruction to prefetch for allocation.
6115 // Could fault, need space at the end of TLAB.
6116 instruct prefetchAlloc_bis( iRegP dst ) %{
6117 predicate(AllocatePrefetchInstr == 1);
6118 match( PrefetchAllocation dst );
6119 ins_cost(MEMORY_REF_COST);
6120 size(4);
6121
6122 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6123 ins_encode %{
6124 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6125 %}
6126 ins_pipe(istore_mem_reg);
6127 %}
6128
6129 // Next code is used for finding next cache line address to prefetch.
6130 #ifndef _LP64
6131 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6132 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6133 ins_cost(DEFAULT_COST);
6134 size(4);
6135
6136 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6137 ins_encode %{
6138 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6139 %}
6140 ins_pipe(ialu_reg_imm);
6141 %}
6142 #else
6143 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6144 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6145 ins_cost(DEFAULT_COST);
6146 size(4);
6147
6148 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6149 ins_encode %{
6150 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6151 %}
6152 ins_pipe(ialu_reg_imm);
6153 %}
6154 #endif
6155
6156 //----------Store Instructions-------------------------------------------------
6157 // Store Byte
6158 instruct storeB(memory mem, iRegI src) %{
6159 match(Set mem (StoreB mem src));
6160 ins_cost(MEMORY_REF_COST);
6161
6162 size(4);
6163 format %{ "STB $src,$mem\t! byte" %}
6164 opcode(Assembler::stb_op3);
6165 ins_encode(simple_form3_mem_reg( mem, src ) );
6166 ins_pipe(istore_mem_reg);
6167 %}
6168
6169 instruct storeB0(memory mem, immI0 src) %{
6170 match(Set mem (StoreB mem src));
6171 ins_cost(MEMORY_REF_COST);
6172
6173 size(4);
6174 format %{ "STB $src,$mem\t! byte" %}
6175 opcode(Assembler::stb_op3);
6176 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6177 ins_pipe(istore_mem_zero);
6178 %}
6179
6180 instruct storeCM0(memory mem, immI0 src) %{
6181 match(Set mem (StoreCM mem src));
6182 ins_cost(MEMORY_REF_COST);
6183
6184 size(4);
6185 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6186 opcode(Assembler::stb_op3);
6187 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6188 ins_pipe(istore_mem_zero);
6189 %}
6190
6191 // Store Char/Short
6192 instruct storeC(memory mem, iRegI src) %{
6193 match(Set mem (StoreC mem src));
6194 ins_cost(MEMORY_REF_COST);
6195
6196 size(4);
6197 format %{ "STH $src,$mem\t! short" %}
6198 opcode(Assembler::sth_op3);
6199 ins_encode(simple_form3_mem_reg( mem, src ) );
6200 ins_pipe(istore_mem_reg);
6201 %}
6202
6203 instruct storeC0(memory mem, immI0 src) %{
6204 match(Set mem (StoreC mem src));
6205 ins_cost(MEMORY_REF_COST);
6206
6207 size(4);
6208 format %{ "STH $src,$mem\t! short" %}
6209 opcode(Assembler::sth_op3);
6210 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6211 ins_pipe(istore_mem_zero);
6212 %}
6213
6214 // Store Integer
6215 instruct storeI(memory mem, iRegI src) %{
6216 match(Set mem (StoreI mem src));
6217 ins_cost(MEMORY_REF_COST);
6218
6219 size(4);
6220 format %{ "STW $src,$mem" %}
6221 opcode(Assembler::stw_op3);
6222 ins_encode(simple_form3_mem_reg( mem, src ) );
6223 ins_pipe(istore_mem_reg);
6224 %}
6225
6226 // Store Long
6227 instruct storeL(memory mem, iRegL src) %{
6228 match(Set mem (StoreL mem src));
6229 ins_cost(MEMORY_REF_COST);
6230 size(4);
6231 format %{ "STX $src,$mem\t! long" %}
6232 opcode(Assembler::stx_op3);
6233 ins_encode(simple_form3_mem_reg( mem, src ) );
6234 ins_pipe(istore_mem_reg);
6235 %}
6236
6237 instruct storeI0(memory mem, immI0 src) %{
6238 match(Set mem (StoreI mem src));
6239 ins_cost(MEMORY_REF_COST);
6240
6241 size(4);
6242 format %{ "STW $src,$mem" %}
6243 opcode(Assembler::stw_op3);
6244 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6245 ins_pipe(istore_mem_zero);
6246 %}
6247
6248 instruct storeL0(memory mem, immL0 src) %{
6249 match(Set mem (StoreL mem src));
6250 ins_cost(MEMORY_REF_COST);
6251
6252 size(4);
6253 format %{ "STX $src,$mem" %}
6254 opcode(Assembler::stx_op3);
6255 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6256 ins_pipe(istore_mem_zero);
6257 %}
6258
6259 // Store Integer from float register (used after fstoi)
6260 instruct storeI_Freg(memory mem, regF src) %{
6261 match(Set mem (StoreI mem src));
6262 ins_cost(MEMORY_REF_COST);
6263
6264 size(4);
6265 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6266 opcode(Assembler::stf_op3);
6267 ins_encode(simple_form3_mem_reg( mem, src ) );
6268 ins_pipe(fstoreF_mem_reg);
6269 %}
6270
6271 // Store Pointer
6272 instruct storeP(memory dst, sp_ptr_RegP src) %{
6273 match(Set dst (StoreP dst src));
6274 ins_cost(MEMORY_REF_COST);
6275 size(4);
6276
6277 #ifndef _LP64
6278 format %{ "STW $src,$dst\t! ptr" %}
6279 opcode(Assembler::stw_op3, 0, REGP_OP);
6280 #else
6281 format %{ "STX $src,$dst\t! ptr" %}
6282 opcode(Assembler::stx_op3, 0, REGP_OP);
6283 #endif
6284 ins_encode( form3_mem_reg( dst, src ) );
6285 ins_pipe(istore_mem_spORreg);
6286 %}
6287
6288 instruct storeP0(memory dst, immP0 src) %{
6289 match(Set dst (StoreP dst src));
6290 ins_cost(MEMORY_REF_COST);
6291 size(4);
6292
6293 #ifndef _LP64
6294 format %{ "STW $src,$dst\t! ptr" %}
6295 opcode(Assembler::stw_op3, 0, REGP_OP);
6296 #else
6297 format %{ "STX $src,$dst\t! ptr" %}
6298 opcode(Assembler::stx_op3, 0, REGP_OP);
6299 #endif
6300 ins_encode( form3_mem_reg( dst, R_G0 ) );
6301 ins_pipe(istore_mem_zero);
6302 %}
6303
6304 // Store Compressed Pointer
6305 instruct storeN(memory dst, iRegN src) %{
6306 match(Set dst (StoreN dst src));
6307 ins_cost(MEMORY_REF_COST);
6308 size(4);
6309
6310 format %{ "STW $src,$dst\t! compressed ptr" %}
6311 ins_encode %{
6312 Register base = as_Register($dst$$base);
6313 Register index = as_Register($dst$$index);
6314 Register src = $src$$Register;
6315 if (index != G0) {
6316 __ stw(src, base, index);
6317 } else {
6318 __ stw(src, base, $dst$$disp);
6319 }
6320 %}
6321 ins_pipe(istore_mem_spORreg);
6322 %}
6323
6324 instruct storeNKlass(memory dst, iRegN src) %{
6325 match(Set dst (StoreNKlass dst src));
6326 ins_cost(MEMORY_REF_COST);
6327 size(4);
6328
6329 format %{ "STW $src,$dst\t! compressed klass ptr" %}
6330 ins_encode %{
6331 Register base = as_Register($dst$$base);
6332 Register index = as_Register($dst$$index);
6333 Register src = $src$$Register;
6334 if (index != G0) {
6335 __ stw(src, base, index);
6336 } else {
6337 __ stw(src, base, $dst$$disp);
6338 }
6339 %}
6340 ins_pipe(istore_mem_spORreg);
6341 %}
6342
6343 instruct storeN0(memory dst, immN0 src) %{
6344 match(Set dst (StoreN dst src));
6345 ins_cost(MEMORY_REF_COST);
6346 size(4);
6347
6348 format %{ "STW $src,$dst\t! compressed ptr" %}
6349 ins_encode %{
6350 Register base = as_Register($dst$$base);
6351 Register index = as_Register($dst$$index);
6352 if (index != G0) {
6353 __ stw(0, base, index);
6354 } else {
6355 __ stw(0, base, $dst$$disp);
6356 }
6357 %}
6358 ins_pipe(istore_mem_zero);
6359 %}
6360
6361 // Store Double
6362 instruct storeD( memory mem, regD src) %{
6363 match(Set mem (StoreD mem src));
6364 ins_cost(MEMORY_REF_COST);
6365
6366 size(4);
6367 format %{ "STDF $src,$mem" %}
6368 opcode(Assembler::stdf_op3);
6369 ins_encode(simple_form3_mem_reg( mem, src ) );
6370 ins_pipe(fstoreD_mem_reg);
6371 %}
6372
6373 instruct storeD0( memory mem, immD0 src) %{
6374 match(Set mem (StoreD mem src));
6375 ins_cost(MEMORY_REF_COST);
6376
6377 size(4);
6378 format %{ "STX $src,$mem" %}
6379 opcode(Assembler::stx_op3);
6380 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6381 ins_pipe(fstoreD_mem_zero);
6382 %}
6383
6384 // Store Float
6385 instruct storeF( memory mem, regF src) %{
6386 match(Set mem (StoreF mem src));
6387 ins_cost(MEMORY_REF_COST);
6388
6389 size(4);
6390 format %{ "STF $src,$mem" %}
6391 opcode(Assembler::stf_op3);
6392 ins_encode(simple_form3_mem_reg( mem, src ) );
6393 ins_pipe(fstoreF_mem_reg);
6394 %}
6395
6396 instruct storeF0( memory mem, immF0 src) %{
6397 match(Set mem (StoreF mem src));
6398 ins_cost(MEMORY_REF_COST);
6399
6400 size(4);
6401 format %{ "STW $src,$mem\t! storeF0" %}
6402 opcode(Assembler::stw_op3);
6403 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6404 ins_pipe(fstoreF_mem_zero);
6405 %}
6406
6407 // Convert oop pointer into compressed form
6408 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6409 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6410 match(Set dst (EncodeP src));
6411 format %{ "encode_heap_oop $src, $dst" %}
6412 ins_encode %{
6413 __ encode_heap_oop($src$$Register, $dst$$Register);
6414 %}
6415 ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE);
6416 ins_pipe(ialu_reg);
6417 %}
6418
6419 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6420 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6421 match(Set dst (EncodeP src));
6422 format %{ "encode_heap_oop_not_null $src, $dst" %}
6423 ins_encode %{
6424 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6425 %}
6426 ins_pipe(ialu_reg);
6427 %}
6428
6429 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6430 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6431 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6432 match(Set dst (DecodeN src));
6433 format %{ "decode_heap_oop $src, $dst" %}
6434 ins_encode %{
6435 __ decode_heap_oop($src$$Register, $dst$$Register);
6436 %}
6437 ins_pipe(ialu_reg);
6438 %}
6439
6440 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6441 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6442 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6443 match(Set dst (DecodeN src));
6444 format %{ "decode_heap_oop_not_null $src, $dst" %}
6445 ins_encode %{
6446 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6447 %}
6448 ins_pipe(ialu_reg);
6449 %}
6450
6451 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6452 match(Set dst (EncodePKlass src));
6453 format %{ "encode_klass_not_null $src, $dst" %}
6454 ins_encode %{
6455 __ encode_klass_not_null($src$$Register, $dst$$Register);
6456 %}
6457 ins_pipe(ialu_reg);
6458 %}
6459
6460 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6461 match(Set dst (DecodeNKlass src));
6462 format %{ "decode_klass_not_null $src, $dst" %}
6463 ins_encode %{
6464 __ decode_klass_not_null($src$$Register, $dst$$Register);
6465 %}
6466 ins_pipe(ialu_reg);
6467 %}
6468
6469 //----------MemBar Instructions-----------------------------------------------
6470 // Memory barrier flavors
6471
6472 instruct membar_acquire() %{
6473 match(MemBarAcquire);
6474 match(LoadFence);
6475 ins_cost(4*MEMORY_REF_COST);
6476
6477 size(0);
6478 format %{ "MEMBAR-acquire" %}
6479 ins_encode( enc_membar_acquire );
6480 ins_pipe(long_memory_op);
6481 %}
6482
6483 instruct membar_acquire_lock() %{
6484 match(MemBarAcquireLock);
6485 ins_cost(0);
6486
6487 size(0);
6488 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6489 ins_encode( );
6490 ins_pipe(empty);
6491 %}
6492
6493 instruct membar_release() %{
6494 match(MemBarRelease);
6495 match(StoreFence);
6496 ins_cost(4*MEMORY_REF_COST);
6497
6498 size(0);
6499 format %{ "MEMBAR-release" %}
6500 ins_encode( enc_membar_release );
6501 ins_pipe(long_memory_op);
6502 %}
6503
6504 instruct membar_release_lock() %{
6505 match(MemBarReleaseLock);
6506 ins_cost(0);
6507
6508 size(0);
6509 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6510 ins_encode( );
6511 ins_pipe(empty);
6512 %}
6513
6514 instruct membar_volatile() %{
6515 match(MemBarVolatile);
6516 ins_cost(4*MEMORY_REF_COST);
6517
6518 size(4);
6519 format %{ "MEMBAR-volatile" %}
6520 ins_encode( enc_membar_volatile );
6521 ins_pipe(long_memory_op);
6522 %}
6523
6524 instruct unnecessary_membar_volatile() %{
6525 match(MemBarVolatile);
6526 predicate(Matcher::post_store_load_barrier(n));
6527 ins_cost(0);
6528
6529 size(0);
6530 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6531 ins_encode( );
6532 ins_pipe(empty);
6533 %}
6534
6535 instruct membar_storestore() %{
6536 match(MemBarStoreStore);
6537 ins_cost(0);
6538
6539 size(0);
6540 format %{ "!MEMBAR-storestore (empty encoding)" %}
6541 ins_encode( );
6542 ins_pipe(empty);
6543 %}
6544
6545 //----------Register Move Instructions-----------------------------------------
6546 instruct roundDouble_nop(regD dst) %{
6547 match(Set dst (RoundDouble dst));
6548 ins_cost(0);
6549 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6550 ins_encode( );
6551 ins_pipe(empty);
6552 %}
6553
6554
6555 instruct roundFloat_nop(regF dst) %{
6556 match(Set dst (RoundFloat dst));
6557 ins_cost(0);
6558 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6559 ins_encode( );
6560 ins_pipe(empty);
6561 %}
6562
6563
6564 // Cast Index to Pointer for unsafe natives
6565 instruct castX2P(iRegX src, iRegP dst) %{
6566 match(Set dst (CastX2P src));
6567
6568 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6569 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6570 ins_pipe(ialu_reg);
6571 %}
6572
6573 // Cast Pointer to Index for unsafe natives
6574 instruct castP2X(iRegP src, iRegX dst) %{
6575 match(Set dst (CastP2X src));
6576
6577 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6578 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6579 ins_pipe(ialu_reg);
6580 %}
6581
6582 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6583 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6584 match(Set stkSlot src); // chain rule
6585 ins_cost(MEMORY_REF_COST);
6586 format %{ "STDF $src,$stkSlot\t!stk" %}
6587 opcode(Assembler::stdf_op3);
6588 ins_encode(simple_form3_mem_reg(stkSlot, src));
6589 ins_pipe(fstoreD_stk_reg);
6590 %}
6591
6592 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6593 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6594 match(Set dst stkSlot); // chain rule
6595 ins_cost(MEMORY_REF_COST);
6596 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6597 opcode(Assembler::lddf_op3);
6598 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6599 ins_pipe(floadD_stk);
6600 %}
6601
6602 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6603 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6604 match(Set stkSlot src); // chain rule
6605 ins_cost(MEMORY_REF_COST);
6606 format %{ "STF $src,$stkSlot\t!stk" %}
6607 opcode(Assembler::stf_op3);
6608 ins_encode(simple_form3_mem_reg(stkSlot, src));
6609 ins_pipe(fstoreF_stk_reg);
6610 %}
6611
6612 //----------Conditional Move---------------------------------------------------
6613 // Conditional move
6614 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6615 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6616 ins_cost(150);
6617 format %{ "MOV$cmp $pcc,$src,$dst" %}
6618 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6619 ins_pipe(ialu_reg);
6620 %}
6621
6622 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6623 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6624 ins_cost(140);
6625 format %{ "MOV$cmp $pcc,$src,$dst" %}
6626 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6627 ins_pipe(ialu_imm);
6628 %}
6629
6630 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6631 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6632 ins_cost(150);
6633 size(4);
6634 format %{ "MOV$cmp $icc,$src,$dst" %}
6635 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6636 ins_pipe(ialu_reg);
6637 %}
6638
6639 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6640 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6641 ins_cost(140);
6642 size(4);
6643 format %{ "MOV$cmp $icc,$src,$dst" %}
6644 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6645 ins_pipe(ialu_imm);
6646 %}
6647
6648 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6649 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6650 ins_cost(150);
6651 size(4);
6652 format %{ "MOV$cmp $icc,$src,$dst" %}
6653 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6654 ins_pipe(ialu_reg);
6655 %}
6656
6657 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6658 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6659 ins_cost(140);
6660 size(4);
6661 format %{ "MOV$cmp $icc,$src,$dst" %}
6662 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6663 ins_pipe(ialu_imm);
6664 %}
6665
6666 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6667 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6668 ins_cost(150);
6669 size(4);
6670 format %{ "MOV$cmp $fcc,$src,$dst" %}
6671 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6672 ins_pipe(ialu_reg);
6673 %}
6674
6675 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6676 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6677 ins_cost(140);
6678 size(4);
6679 format %{ "MOV$cmp $fcc,$src,$dst" %}
6680 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6681 ins_pipe(ialu_imm);
6682 %}
6683
6684 // Conditional move for RegN. Only cmov(reg,reg).
6685 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6686 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6687 ins_cost(150);
6688 format %{ "MOV$cmp $pcc,$src,$dst" %}
6689 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6690 ins_pipe(ialu_reg);
6691 %}
6692
6693 // This instruction also works with CmpN so we don't need cmovNN_reg.
6694 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6695 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6696 ins_cost(150);
6697 size(4);
6698 format %{ "MOV$cmp $icc,$src,$dst" %}
6699 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6700 ins_pipe(ialu_reg);
6701 %}
6702
6703 // This instruction also works with CmpN so we don't need cmovNN_reg.
6704 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6705 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6706 ins_cost(150);
6707 size(4);
6708 format %{ "MOV$cmp $icc,$src,$dst" %}
6709 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6710 ins_pipe(ialu_reg);
6711 %}
6712
6713 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6714 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6715 ins_cost(150);
6716 size(4);
6717 format %{ "MOV$cmp $fcc,$src,$dst" %}
6718 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6719 ins_pipe(ialu_reg);
6720 %}
6721
6722 // Conditional move
6723 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6724 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6725 ins_cost(150);
6726 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6727 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6728 ins_pipe(ialu_reg);
6729 %}
6730
6731 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6732 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6733 ins_cost(140);
6734 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6735 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6736 ins_pipe(ialu_imm);
6737 %}
6738
6739 // This instruction also works with CmpN so we don't need cmovPN_reg.
6740 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6741 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6742 ins_cost(150);
6743
6744 size(4);
6745 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6746 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6747 ins_pipe(ialu_reg);
6748 %}
6749
6750 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6751 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6752 ins_cost(150);
6753
6754 size(4);
6755 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6756 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6757 ins_pipe(ialu_reg);
6758 %}
6759
6760 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6761 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6762 ins_cost(140);
6763
6764 size(4);
6765 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6766 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6767 ins_pipe(ialu_imm);
6768 %}
6769
6770 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6771 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6772 ins_cost(140);
6773
6774 size(4);
6775 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6776 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6777 ins_pipe(ialu_imm);
6778 %}
6779
6780 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6781 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6782 ins_cost(150);
6783 size(4);
6784 format %{ "MOV$cmp $fcc,$src,$dst" %}
6785 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6786 ins_pipe(ialu_imm);
6787 %}
6788
6789 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6790 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6791 ins_cost(140);
6792 size(4);
6793 format %{ "MOV$cmp $fcc,$src,$dst" %}
6794 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6795 ins_pipe(ialu_imm);
6796 %}
6797
6798 // Conditional move
6799 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6800 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6801 ins_cost(150);
6802 opcode(0x101);
6803 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6804 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6805 ins_pipe(int_conditional_float_move);
6806 %}
6807
6808 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6809 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6810 ins_cost(150);
6811
6812 size(4);
6813 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6814 opcode(0x101);
6815 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6816 ins_pipe(int_conditional_float_move);
6817 %}
6818
6819 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6820 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6821 ins_cost(150);
6822
6823 size(4);
6824 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6825 opcode(0x101);
6826 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6827 ins_pipe(int_conditional_float_move);
6828 %}
6829
6830 // Conditional move,
6831 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6832 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6833 ins_cost(150);
6834 size(4);
6835 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6836 opcode(0x1);
6837 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6838 ins_pipe(int_conditional_double_move);
6839 %}
6840
6841 // Conditional move
6842 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6843 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6844 ins_cost(150);
6845 size(4);
6846 opcode(0x102);
6847 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6848 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6849 ins_pipe(int_conditional_double_move);
6850 %}
6851
6852 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6853 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6854 ins_cost(150);
6855
6856 size(4);
6857 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6858 opcode(0x102);
6859 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6860 ins_pipe(int_conditional_double_move);
6861 %}
6862
6863 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6864 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6865 ins_cost(150);
6866
6867 size(4);
6868 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6869 opcode(0x102);
6870 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6871 ins_pipe(int_conditional_double_move);
6872 %}
6873
6874 // Conditional move,
6875 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6876 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6877 ins_cost(150);
6878 size(4);
6879 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6880 opcode(0x2);
6881 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6882 ins_pipe(int_conditional_double_move);
6883 %}
6884
6885 // Conditional move
6886 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6887 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6888 ins_cost(150);
6889 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6890 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6891 ins_pipe(ialu_reg);
6892 %}
6893
6894 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6895 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6896 ins_cost(140);
6897 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6898 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6899 ins_pipe(ialu_imm);
6900 %}
6901
6902 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6903 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6904 ins_cost(150);
6905
6906 size(4);
6907 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6908 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6909 ins_pipe(ialu_reg);
6910 %}
6911
6912
6913 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
6914 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6915 ins_cost(150);
6916
6917 size(4);
6918 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6919 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6920 ins_pipe(ialu_reg);
6921 %}
6922
6923
6924 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6925 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6926 ins_cost(150);
6927
6928 size(4);
6929 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6930 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6931 ins_pipe(ialu_reg);
6932 %}
6933
6934
6935
6936 //----------OS and Locking Instructions----------------------------------------
6937
6938 // This name is KNOWN by the ADLC and cannot be changed.
6939 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6940 // for this guy.
6941 instruct tlsLoadP(g2RegP dst) %{
6942 match(Set dst (ThreadLocal));
6943
6944 size(0);
6945 ins_cost(0);
6946 format %{ "# TLS is in G2" %}
6947 ins_encode( /*empty encoding*/ );
6948 ins_pipe(ialu_none);
6949 %}
6950
6951 instruct checkCastPP( iRegP dst ) %{
6952 match(Set dst (CheckCastPP dst));
6953
6954 size(0);
6955 format %{ "# checkcastPP of $dst" %}
6956 ins_encode( /*empty encoding*/ );
6957 ins_pipe(empty);
6958 %}
6959
6960
6961 instruct castPP( iRegP dst ) %{
6962 match(Set dst (CastPP dst));
6963 format %{ "# castPP of $dst" %}
6964 ins_encode( /*empty encoding*/ );
6965 ins_pipe(empty);
6966 %}
6967
6968 instruct castII( iRegI dst ) %{
6969 match(Set dst (CastII dst));
6970 format %{ "# castII of $dst" %}
6971 ins_encode( /*empty encoding*/ );
6972 ins_cost(0);
6973 ins_pipe(empty);
6974 %}
6975
6976 //----------Arithmetic Instructions--------------------------------------------
6977 // Addition Instructions
6978 // Register Addition
6979 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6980 match(Set dst (AddI src1 src2));
6981
6982 size(4);
6983 format %{ "ADD $src1,$src2,$dst" %}
6984 ins_encode %{
6985 __ add($src1$$Register, $src2$$Register, $dst$$Register);
6986 %}
6987 ins_pipe(ialu_reg_reg);
6988 %}
6989
6990 // Immediate Addition
6991 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6992 match(Set dst (AddI src1 src2));
6993
6994 size(4);
6995 format %{ "ADD $src1,$src2,$dst" %}
6996 opcode(Assembler::add_op3, Assembler::arith_op);
6997 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6998 ins_pipe(ialu_reg_imm);
6999 %}
7000
7001 // Pointer Register Addition
7002 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7003 match(Set dst (AddP src1 src2));
7004
7005 size(4);
7006 format %{ "ADD $src1,$src2,$dst" %}
7007 opcode(Assembler::add_op3, Assembler::arith_op);
7008 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7009 ins_pipe(ialu_reg_reg);
7010 %}
7011
7012 // Pointer Immediate Addition
7013 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7014 match(Set dst (AddP src1 src2));
7015
7016 size(4);
7017 format %{ "ADD $src1,$src2,$dst" %}
7018 opcode(Assembler::add_op3, Assembler::arith_op);
7019 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7020 ins_pipe(ialu_reg_imm);
7021 %}
7022
7023 // Long Addition
7024 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7025 match(Set dst (AddL src1 src2));
7026
7027 size(4);
7028 format %{ "ADD $src1,$src2,$dst\t! long" %}
7029 opcode(Assembler::add_op3, Assembler::arith_op);
7030 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7031 ins_pipe(ialu_reg_reg);
7032 %}
7033
7034 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7035 match(Set dst (AddL src1 con));
7036
7037 size(4);
7038 format %{ "ADD $src1,$con,$dst" %}
7039 opcode(Assembler::add_op3, Assembler::arith_op);
7040 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7041 ins_pipe(ialu_reg_imm);
7042 %}
7043
7044 //----------Conditional_store--------------------------------------------------
7045 // Conditional-store of the updated heap-top.
7046 // Used during allocation of the shared heap.
7047 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7048
7049 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7050 instruct loadPLocked(iRegP dst, memory mem) %{
7051 match(Set dst (LoadPLocked mem));
7052 ins_cost(MEMORY_REF_COST);
7053
7054 #ifndef _LP64
7055 size(4);
7056 format %{ "LDUW $mem,$dst\t! ptr" %}
7057 opcode(Assembler::lduw_op3, 0, REGP_OP);
7058 #else
7059 format %{ "LDX $mem,$dst\t! ptr" %}
7060 opcode(Assembler::ldx_op3, 0, REGP_OP);
7061 #endif
7062 ins_encode( form3_mem_reg( mem, dst ) );
7063 ins_pipe(iload_mem);
7064 %}
7065
7066 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7067 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7068 effect( KILL newval );
7069 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7070 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7071 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7072 ins_pipe( long_memory_op );
7073 %}
7074
7075 // Conditional-store of an int value.
7076 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7077 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7078 effect( KILL newval );
7079 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7080 "CMP $oldval,$newval\t\t! See if we made progress" %}
7081 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7082 ins_pipe( long_memory_op );
7083 %}
7084
7085 // Conditional-store of a long value.
7086 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7087 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7088 effect( KILL newval );
7089 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7090 "CMP $oldval,$newval\t\t! See if we made progress" %}
7091 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7092 ins_pipe( long_memory_op );
7093 %}
7094
7095 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7096
7097 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7098 predicate(VM_Version::supports_cx8());
7099 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7100 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7101 format %{
7102 "MOV $newval,O7\n\t"
7103 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7104 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7105 "MOV 1,$res\n\t"
7106 "MOVne xcc,R_G0,$res"
7107 %}
7108 ins_encode( enc_casx(mem_ptr, oldval, newval),
7109 enc_lflags_ne_to_boolean(res) );
7110 ins_pipe( long_memory_op );
7111 %}
7112
7113
7114 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7115 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7116 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7117 format %{
7118 "MOV $newval,O7\n\t"
7119 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7120 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7121 "MOV 1,$res\n\t"
7122 "MOVne icc,R_G0,$res"
7123 %}
7124 ins_encode( enc_casi(mem_ptr, oldval, newval),
7125 enc_iflags_ne_to_boolean(res) );
7126 ins_pipe( long_memory_op );
7127 %}
7128
7129 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7130 #ifdef _LP64
7131 predicate(VM_Version::supports_cx8());
7132 #endif
7133 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7134 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7135 format %{
7136 "MOV $newval,O7\n\t"
7137 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7138 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7139 "MOV 1,$res\n\t"
7140 "MOVne xcc,R_G0,$res"
7141 %}
7142 #ifdef _LP64
7143 ins_encode( enc_casx(mem_ptr, oldval, newval),
7144 enc_lflags_ne_to_boolean(res) );
7145 #else
7146 ins_encode( enc_casi(mem_ptr, oldval, newval),
7147 enc_iflags_ne_to_boolean(res) );
7148 #endif
7149 ins_pipe( long_memory_op );
7150 %}
7151
7152 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7153 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7154 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7155 format %{
7156 "MOV $newval,O7\n\t"
7157 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7158 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7159 "MOV 1,$res\n\t"
7160 "MOVne icc,R_G0,$res"
7161 %}
7162 ins_encode( enc_casi(mem_ptr, oldval, newval),
7163 enc_iflags_ne_to_boolean(res) );
7164 ins_pipe( long_memory_op );
7165 %}
7166
7167 instruct xchgI( memory mem, iRegI newval) %{
7168 match(Set newval (GetAndSetI mem newval));
7169 format %{ "SWAP [$mem],$newval" %}
7170 size(4);
7171 ins_encode %{
7172 __ swap($mem$$Address, $newval$$Register);
7173 %}
7174 ins_pipe( long_memory_op );
7175 %}
7176
7177 #ifndef _LP64
7178 instruct xchgP( memory mem, iRegP newval) %{
7179 match(Set newval (GetAndSetP mem newval));
7180 format %{ "SWAP [$mem],$newval" %}
7181 size(4);
7182 ins_encode %{
7183 __ swap($mem$$Address, $newval$$Register);
7184 %}
7185 ins_pipe( long_memory_op );
7186 %}
7187 #endif
7188
7189 instruct xchgN( memory mem, iRegN newval) %{
7190 match(Set newval (GetAndSetN mem newval));
7191 format %{ "SWAP [$mem],$newval" %}
7192 size(4);
7193 ins_encode %{
7194 __ swap($mem$$Address, $newval$$Register);
7195 %}
7196 ins_pipe( long_memory_op );
7197 %}
7198
7199 //---------------------
7200 // Subtraction Instructions
7201 // Register Subtraction
7202 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7203 match(Set dst (SubI src1 src2));
7204
7205 size(4);
7206 format %{ "SUB $src1,$src2,$dst" %}
7207 opcode(Assembler::sub_op3, Assembler::arith_op);
7208 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7209 ins_pipe(ialu_reg_reg);
7210 %}
7211
7212 // Immediate Subtraction
7213 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7214 match(Set dst (SubI src1 src2));
7215
7216 size(4);
7217 format %{ "SUB $src1,$src2,$dst" %}
7218 opcode(Assembler::sub_op3, Assembler::arith_op);
7219 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7220 ins_pipe(ialu_reg_imm);
7221 %}
7222
7223 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7224 match(Set dst (SubI zero src2));
7225
7226 size(4);
7227 format %{ "NEG $src2,$dst" %}
7228 opcode(Assembler::sub_op3, Assembler::arith_op);
7229 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7230 ins_pipe(ialu_zero_reg);
7231 %}
7232
7233 // Long subtraction
7234 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7235 match(Set dst (SubL src1 src2));
7236
7237 size(4);
7238 format %{ "SUB $src1,$src2,$dst\t! long" %}
7239 opcode(Assembler::sub_op3, Assembler::arith_op);
7240 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7241 ins_pipe(ialu_reg_reg);
7242 %}
7243
7244 // Immediate Subtraction
7245 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7246 match(Set dst (SubL src1 con));
7247
7248 size(4);
7249 format %{ "SUB $src1,$con,$dst\t! long" %}
7250 opcode(Assembler::sub_op3, Assembler::arith_op);
7251 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7252 ins_pipe(ialu_reg_imm);
7253 %}
7254
7255 // Long negation
7256 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7257 match(Set dst (SubL zero src2));
7258
7259 size(4);
7260 format %{ "NEG $src2,$dst\t! long" %}
7261 opcode(Assembler::sub_op3, Assembler::arith_op);
7262 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7263 ins_pipe(ialu_zero_reg);
7264 %}
7265
7266 // Multiplication Instructions
7267 // Integer Multiplication
7268 // Register Multiplication
7269 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7270 match(Set dst (MulI src1 src2));
7271
7272 size(4);
7273 format %{ "MULX $src1,$src2,$dst" %}
7274 opcode(Assembler::mulx_op3, Assembler::arith_op);
7275 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7276 ins_pipe(imul_reg_reg);
7277 %}
7278
7279 // Immediate Multiplication
7280 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7281 match(Set dst (MulI src1 src2));
7282
7283 size(4);
7284 format %{ "MULX $src1,$src2,$dst" %}
7285 opcode(Assembler::mulx_op3, Assembler::arith_op);
7286 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7287 ins_pipe(imul_reg_imm);
7288 %}
7289
7290 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7291 match(Set dst (MulL src1 src2));
7292 ins_cost(DEFAULT_COST * 5);
7293 size(4);
7294 format %{ "MULX $src1,$src2,$dst\t! long" %}
7295 opcode(Assembler::mulx_op3, Assembler::arith_op);
7296 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7297 ins_pipe(mulL_reg_reg);
7298 %}
7299
7300 // Immediate Multiplication
7301 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7302 match(Set dst (MulL src1 src2));
7303 ins_cost(DEFAULT_COST * 5);
7304 size(4);
7305 format %{ "MULX $src1,$src2,$dst" %}
7306 opcode(Assembler::mulx_op3, Assembler::arith_op);
7307 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7308 ins_pipe(mulL_reg_imm);
7309 %}
7310
7311 // Integer Division
7312 // Register Division
7313 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7314 match(Set dst (DivI src1 src2));
7315 ins_cost((2+71)*DEFAULT_COST);
7316
7317 format %{ "SRA $src2,0,$src2\n\t"
7318 "SRA $src1,0,$src1\n\t"
7319 "SDIVX $src1,$src2,$dst" %}
7320 ins_encode( idiv_reg( src1, src2, dst ) );
7321 ins_pipe(sdiv_reg_reg);
7322 %}
7323
7324 // Immediate Division
7325 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7326 match(Set dst (DivI src1 src2));
7327 ins_cost((2+71)*DEFAULT_COST);
7328
7329 format %{ "SRA $src1,0,$src1\n\t"
7330 "SDIVX $src1,$src2,$dst" %}
7331 ins_encode( idiv_imm( src1, src2, dst ) );
7332 ins_pipe(sdiv_reg_imm);
7333 %}
7334
7335 //----------Div-By-10-Expansion------------------------------------------------
7336 // Extract hi bits of a 32x32->64 bit multiply.
7337 // Expand rule only, not matched
7338 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7339 effect( DEF dst, USE src1, USE src2 );
7340 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7341 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7342 ins_encode( enc_mul_hi(dst,src1,src2));
7343 ins_pipe(sdiv_reg_reg);
7344 %}
7345
7346 // Magic constant, reciprocal of 10
7347 instruct loadConI_x66666667(iRegIsafe dst) %{
7348 effect( DEF dst );
7349
7350 size(8);
7351 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7352 ins_encode( Set32(0x66666667, dst) );
7353 ins_pipe(ialu_hi_lo_reg);
7354 %}
7355
7356 // Register Shift Right Arithmetic Long by 32-63
7357 instruct sra_31( iRegI dst, iRegI src ) %{
7358 effect( DEF dst, USE src );
7359 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7360 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7361 ins_pipe(ialu_reg_reg);
7362 %}
7363
7364 // Arithmetic Shift Right by 8-bit immediate
7365 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7366 effect( DEF dst, USE src );
7367 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7368 opcode(Assembler::sra_op3, Assembler::arith_op);
7369 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7370 ins_pipe(ialu_reg_imm);
7371 %}
7372
7373 // Integer DIV with 10
7374 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7375 match(Set dst (DivI src div));
7376 ins_cost((6+6)*DEFAULT_COST);
7377 expand %{
7378 iRegIsafe tmp1; // Killed temps;
7379 iRegIsafe tmp2; // Killed temps;
7380 iRegI tmp3; // Killed temps;
7381 iRegI tmp4; // Killed temps;
7382 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7383 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7384 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7385 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7386 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7387 %}
7388 %}
7389
7390 // Register Long Division
7391 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7392 match(Set dst (DivL src1 src2));
7393 ins_cost(DEFAULT_COST*71);
7394 size(4);
7395 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7396 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7397 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7398 ins_pipe(divL_reg_reg);
7399 %}
7400
7401 // Register Long Division
7402 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7403 match(Set dst (DivL src1 src2));
7404 ins_cost(DEFAULT_COST*71);
7405 size(4);
7406 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7407 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7408 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7409 ins_pipe(divL_reg_imm);
7410 %}
7411
7412 // Integer Remainder
7413 // Register Remainder
7414 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7415 match(Set dst (ModI src1 src2));
7416 effect( KILL ccr, KILL temp);
7417
7418 format %{ "SREM $src1,$src2,$dst" %}
7419 ins_encode( irem_reg(src1, src2, dst, temp) );
7420 ins_pipe(sdiv_reg_reg);
7421 %}
7422
7423 // Immediate Remainder
7424 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7425 match(Set dst (ModI src1 src2));
7426 effect( KILL ccr, KILL temp);
7427
7428 format %{ "SREM $src1,$src2,$dst" %}
7429 ins_encode( irem_imm(src1, src2, dst, temp) );
7430 ins_pipe(sdiv_reg_imm);
7431 %}
7432
7433 // Register Long Remainder
7434 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7435 effect(DEF dst, USE src1, USE src2);
7436 size(4);
7437 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7438 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7439 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7440 ins_pipe(divL_reg_reg);
7441 %}
7442
7443 // Register Long Division
7444 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7445 effect(DEF dst, USE src1, USE src2);
7446 size(4);
7447 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7448 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7449 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7450 ins_pipe(divL_reg_imm);
7451 %}
7452
7453 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7454 effect(DEF dst, USE src1, USE src2);
7455 size(4);
7456 format %{ "MULX $src1,$src2,$dst\t! long" %}
7457 opcode(Assembler::mulx_op3, Assembler::arith_op);
7458 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7459 ins_pipe(mulL_reg_reg);
7460 %}
7461
7462 // Immediate Multiplication
7463 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7464 effect(DEF dst, USE src1, USE src2);
7465 size(4);
7466 format %{ "MULX $src1,$src2,$dst" %}
7467 opcode(Assembler::mulx_op3, Assembler::arith_op);
7468 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7469 ins_pipe(mulL_reg_imm);
7470 %}
7471
7472 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7473 effect(DEF dst, USE src1, USE src2);
7474 size(4);
7475 format %{ "SUB $src1,$src2,$dst\t! long" %}
7476 opcode(Assembler::sub_op3, Assembler::arith_op);
7477 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7478 ins_pipe(ialu_reg_reg);
7479 %}
7480
7481 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7482 effect(DEF dst, USE src1, USE src2);
7483 size(4);
7484 format %{ "SUB $src1,$src2,$dst\t! long" %}
7485 opcode(Assembler::sub_op3, Assembler::arith_op);
7486 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7487 ins_pipe(ialu_reg_reg);
7488 %}
7489
7490 // Register Long Remainder
7491 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7492 match(Set dst (ModL src1 src2));
7493 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7494 expand %{
7495 iRegL tmp1;
7496 iRegL tmp2;
7497 divL_reg_reg_1(tmp1, src1, src2);
7498 mulL_reg_reg_1(tmp2, tmp1, src2);
7499 subL_reg_reg_1(dst, src1, tmp2);
7500 %}
7501 %}
7502
7503 // Register Long Remainder
7504 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7505 match(Set dst (ModL src1 src2));
7506 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7507 expand %{
7508 iRegL tmp1;
7509 iRegL tmp2;
7510 divL_reg_imm13_1(tmp1, src1, src2);
7511 mulL_reg_imm13_1(tmp2, tmp1, src2);
7512 subL_reg_reg_2 (dst, src1, tmp2);
7513 %}
7514 %}
7515
7516 // Integer Shift Instructions
7517 // Register Shift Left
7518 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7519 match(Set dst (LShiftI src1 src2));
7520
7521 size(4);
7522 format %{ "SLL $src1,$src2,$dst" %}
7523 opcode(Assembler::sll_op3, Assembler::arith_op);
7524 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7525 ins_pipe(ialu_reg_reg);
7526 %}
7527
7528 // Register Shift Left Immediate
7529 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7530 match(Set dst (LShiftI src1 src2));
7531
7532 size(4);
7533 format %{ "SLL $src1,$src2,$dst" %}
7534 opcode(Assembler::sll_op3, Assembler::arith_op);
7535 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7536 ins_pipe(ialu_reg_imm);
7537 %}
7538
7539 // Register Shift Left
7540 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7541 match(Set dst (LShiftL src1 src2));
7542
7543 size(4);
7544 format %{ "SLLX $src1,$src2,$dst" %}
7545 opcode(Assembler::sllx_op3, Assembler::arith_op);
7546 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7547 ins_pipe(ialu_reg_reg);
7548 %}
7549
7550 // Register Shift Left Immediate
7551 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7552 match(Set dst (LShiftL src1 src2));
7553
7554 size(4);
7555 format %{ "SLLX $src1,$src2,$dst" %}
7556 opcode(Assembler::sllx_op3, Assembler::arith_op);
7557 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7558 ins_pipe(ialu_reg_imm);
7559 %}
7560
7561 // Register Arithmetic Shift Right
7562 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7563 match(Set dst (RShiftI src1 src2));
7564 size(4);
7565 format %{ "SRA $src1,$src2,$dst" %}
7566 opcode(Assembler::sra_op3, Assembler::arith_op);
7567 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7568 ins_pipe(ialu_reg_reg);
7569 %}
7570
7571 // Register Arithmetic Shift Right Immediate
7572 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7573 match(Set dst (RShiftI src1 src2));
7574
7575 size(4);
7576 format %{ "SRA $src1,$src2,$dst" %}
7577 opcode(Assembler::sra_op3, Assembler::arith_op);
7578 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7579 ins_pipe(ialu_reg_imm);
7580 %}
7581
7582 // Register Shift Right Arithmatic Long
7583 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7584 match(Set dst (RShiftL src1 src2));
7585
7586 size(4);
7587 format %{ "SRAX $src1,$src2,$dst" %}
7588 opcode(Assembler::srax_op3, Assembler::arith_op);
7589 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7590 ins_pipe(ialu_reg_reg);
7591 %}
7592
7593 // Register Shift Left Immediate
7594 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7595 match(Set dst (RShiftL src1 src2));
7596
7597 size(4);
7598 format %{ "SRAX $src1,$src2,$dst" %}
7599 opcode(Assembler::srax_op3, Assembler::arith_op);
7600 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7601 ins_pipe(ialu_reg_imm);
7602 %}
7603
7604 // Register Shift Right
7605 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7606 match(Set dst (URShiftI src1 src2));
7607
7608 size(4);
7609 format %{ "SRL $src1,$src2,$dst" %}
7610 opcode(Assembler::srl_op3, Assembler::arith_op);
7611 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7612 ins_pipe(ialu_reg_reg);
7613 %}
7614
7615 // Register Shift Right Immediate
7616 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7617 match(Set dst (URShiftI src1 src2));
7618
7619 size(4);
7620 format %{ "SRL $src1,$src2,$dst" %}
7621 opcode(Assembler::srl_op3, Assembler::arith_op);
7622 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7623 ins_pipe(ialu_reg_imm);
7624 %}
7625
7626 // Register Shift Right
7627 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7628 match(Set dst (URShiftL src1 src2));
7629
7630 size(4);
7631 format %{ "SRLX $src1,$src2,$dst" %}
7632 opcode(Assembler::srlx_op3, Assembler::arith_op);
7633 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7634 ins_pipe(ialu_reg_reg);
7635 %}
7636
7637 // Register Shift Right Immediate
7638 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7639 match(Set dst (URShiftL src1 src2));
7640
7641 size(4);
7642 format %{ "SRLX $src1,$src2,$dst" %}
7643 opcode(Assembler::srlx_op3, Assembler::arith_op);
7644 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7645 ins_pipe(ialu_reg_imm);
7646 %}
7647
7648 // Register Shift Right Immediate with a CastP2X
7649 #ifdef _LP64
7650 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7651 match(Set dst (URShiftL (CastP2X src1) src2));
7652 size(4);
7653 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7654 opcode(Assembler::srlx_op3, Assembler::arith_op);
7655 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7656 ins_pipe(ialu_reg_imm);
7657 %}
7658 #else
7659 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7660 match(Set dst (URShiftI (CastP2X src1) src2));
7661 size(4);
7662 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7663 opcode(Assembler::srl_op3, Assembler::arith_op);
7664 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7665 ins_pipe(ialu_reg_imm);
7666 %}
7667 #endif
7668
7669
7670 //----------Floating Point Arithmetic Instructions-----------------------------
7671
7672 // Add float single precision
7673 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7674 match(Set dst (AddF src1 src2));
7675
7676 size(4);
7677 format %{ "FADDS $src1,$src2,$dst" %}
7678 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7679 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7680 ins_pipe(faddF_reg_reg);
7681 %}
7682
7683 // Add float double precision
7684 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7685 match(Set dst (AddD src1 src2));
7686
7687 size(4);
7688 format %{ "FADDD $src1,$src2,$dst" %}
7689 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7690 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7691 ins_pipe(faddD_reg_reg);
7692 %}
7693
7694 // Sub float single precision
7695 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7696 match(Set dst (SubF src1 src2));
7697
7698 size(4);
7699 format %{ "FSUBS $src1,$src2,$dst" %}
7700 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7701 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7702 ins_pipe(faddF_reg_reg);
7703 %}
7704
7705 // Sub float double precision
7706 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7707 match(Set dst (SubD src1 src2));
7708
7709 size(4);
7710 format %{ "FSUBD $src1,$src2,$dst" %}
7711 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7712 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7713 ins_pipe(faddD_reg_reg);
7714 %}
7715
7716 // Mul float single precision
7717 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7718 match(Set dst (MulF src1 src2));
7719
7720 size(4);
7721 format %{ "FMULS $src1,$src2,$dst" %}
7722 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7723 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7724 ins_pipe(fmulF_reg_reg);
7725 %}
7726
7727 // Mul float double precision
7728 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7729 match(Set dst (MulD src1 src2));
7730
7731 size(4);
7732 format %{ "FMULD $src1,$src2,$dst" %}
7733 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7734 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7735 ins_pipe(fmulD_reg_reg);
7736 %}
7737
7738 // Div float single precision
7739 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7740 match(Set dst (DivF src1 src2));
7741
7742 size(4);
7743 format %{ "FDIVS $src1,$src2,$dst" %}
7744 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7745 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7746 ins_pipe(fdivF_reg_reg);
7747 %}
7748
7749 // Div float double precision
7750 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7751 match(Set dst (DivD src1 src2));
7752
7753 size(4);
7754 format %{ "FDIVD $src1,$src2,$dst" %}
7755 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7756 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7757 ins_pipe(fdivD_reg_reg);
7758 %}
7759
7760 // Absolute float double precision
7761 instruct absD_reg(regD dst, regD src) %{
7762 match(Set dst (AbsD src));
7763
7764 format %{ "FABSd $src,$dst" %}
7765 ins_encode(fabsd(dst, src));
7766 ins_pipe(faddD_reg);
7767 %}
7768
7769 // Absolute float single precision
7770 instruct absF_reg(regF dst, regF src) %{
7771 match(Set dst (AbsF src));
7772
7773 format %{ "FABSs $src,$dst" %}
7774 ins_encode(fabss(dst, src));
7775 ins_pipe(faddF_reg);
7776 %}
7777
7778 instruct negF_reg(regF dst, regF src) %{
7779 match(Set dst (NegF src));
7780
7781 size(4);
7782 format %{ "FNEGs $src,$dst" %}
7783 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7784 ins_encode(form3_opf_rs2F_rdF(src, dst));
7785 ins_pipe(faddF_reg);
7786 %}
7787
7788 instruct negD_reg(regD dst, regD src) %{
7789 match(Set dst (NegD src));
7790
7791 format %{ "FNEGd $src,$dst" %}
7792 ins_encode(fnegd(dst, src));
7793 ins_pipe(faddD_reg);
7794 %}
7795
7796 // Sqrt float double precision
7797 instruct sqrtF_reg_reg(regF dst, regF src) %{
7798 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7799
7800 size(4);
7801 format %{ "FSQRTS $src,$dst" %}
7802 ins_encode(fsqrts(dst, src));
7803 ins_pipe(fdivF_reg_reg);
7804 %}
7805
7806 // Sqrt float double precision
7807 instruct sqrtD_reg_reg(regD dst, regD src) %{
7808 match(Set dst (SqrtD src));
7809
7810 size(4);
7811 format %{ "FSQRTD $src,$dst" %}
7812 ins_encode(fsqrtd(dst, src));
7813 ins_pipe(fdivD_reg_reg);
7814 %}
7815
7816 //----------Logical Instructions-----------------------------------------------
7817 // And Instructions
7818 // Register And
7819 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7820 match(Set dst (AndI src1 src2));
7821
7822 size(4);
7823 format %{ "AND $src1,$src2,$dst" %}
7824 opcode(Assembler::and_op3, Assembler::arith_op);
7825 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7826 ins_pipe(ialu_reg_reg);
7827 %}
7828
7829 // Immediate And
7830 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7831 match(Set dst (AndI src1 src2));
7832
7833 size(4);
7834 format %{ "AND $src1,$src2,$dst" %}
7835 opcode(Assembler::and_op3, Assembler::arith_op);
7836 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7837 ins_pipe(ialu_reg_imm);
7838 %}
7839
7840 // Register And Long
7841 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7842 match(Set dst (AndL src1 src2));
7843
7844 ins_cost(DEFAULT_COST);
7845 size(4);
7846 format %{ "AND $src1,$src2,$dst\t! long" %}
7847 opcode(Assembler::and_op3, Assembler::arith_op);
7848 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7849 ins_pipe(ialu_reg_reg);
7850 %}
7851
7852 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7853 match(Set dst (AndL src1 con));
7854
7855 ins_cost(DEFAULT_COST);
7856 size(4);
7857 format %{ "AND $src1,$con,$dst\t! long" %}
7858 opcode(Assembler::and_op3, Assembler::arith_op);
7859 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7860 ins_pipe(ialu_reg_imm);
7861 %}
7862
7863 // Or Instructions
7864 // Register Or
7865 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7866 match(Set dst (OrI src1 src2));
7867
7868 size(4);
7869 format %{ "OR $src1,$src2,$dst" %}
7870 opcode(Assembler::or_op3, Assembler::arith_op);
7871 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7872 ins_pipe(ialu_reg_reg);
7873 %}
7874
7875 // Immediate Or
7876 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7877 match(Set dst (OrI src1 src2));
7878
7879 size(4);
7880 format %{ "OR $src1,$src2,$dst" %}
7881 opcode(Assembler::or_op3, Assembler::arith_op);
7882 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7883 ins_pipe(ialu_reg_imm);
7884 %}
7885
7886 // Register Or Long
7887 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7888 match(Set dst (OrL src1 src2));
7889
7890 ins_cost(DEFAULT_COST);
7891 size(4);
7892 format %{ "OR $src1,$src2,$dst\t! long" %}
7893 opcode(Assembler::or_op3, Assembler::arith_op);
7894 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7895 ins_pipe(ialu_reg_reg);
7896 %}
7897
7898 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7899 match(Set dst (OrL src1 con));
7900 ins_cost(DEFAULT_COST*2);
7901
7902 ins_cost(DEFAULT_COST);
7903 size(4);
7904 format %{ "OR $src1,$con,$dst\t! long" %}
7905 opcode(Assembler::or_op3, Assembler::arith_op);
7906 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7907 ins_pipe(ialu_reg_imm);
7908 %}
7909
7910 #ifndef _LP64
7911
7912 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
7913 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
7914 match(Set dst (OrI src1 (CastP2X src2)));
7915
7916 size(4);
7917 format %{ "OR $src1,$src2,$dst" %}
7918 opcode(Assembler::or_op3, Assembler::arith_op);
7919 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7920 ins_pipe(ialu_reg_reg);
7921 %}
7922
7923 #else
7924
7925 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
7926 match(Set dst (OrL src1 (CastP2X src2)));
7927
7928 ins_cost(DEFAULT_COST);
7929 size(4);
7930 format %{ "OR $src1,$src2,$dst\t! long" %}
7931 opcode(Assembler::or_op3, Assembler::arith_op);
7932 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7933 ins_pipe(ialu_reg_reg);
7934 %}
7935
7936 #endif
7937
7938 // Xor Instructions
7939 // Register Xor
7940 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7941 match(Set dst (XorI src1 src2));
7942
7943 size(4);
7944 format %{ "XOR $src1,$src2,$dst" %}
7945 opcode(Assembler::xor_op3, Assembler::arith_op);
7946 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7947 ins_pipe(ialu_reg_reg);
7948 %}
7949
7950 // Immediate Xor
7951 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7952 match(Set dst (XorI src1 src2));
7953
7954 size(4);
7955 format %{ "XOR $src1,$src2,$dst" %}
7956 opcode(Assembler::xor_op3, Assembler::arith_op);
7957 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7958 ins_pipe(ialu_reg_imm);
7959 %}
7960
7961 // Register Xor Long
7962 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7963 match(Set dst (XorL src1 src2));
7964
7965 ins_cost(DEFAULT_COST);
7966 size(4);
7967 format %{ "XOR $src1,$src2,$dst\t! long" %}
7968 opcode(Assembler::xor_op3, Assembler::arith_op);
7969 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7970 ins_pipe(ialu_reg_reg);
7971 %}
7972
7973 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7974 match(Set dst (XorL src1 con));
7975
7976 ins_cost(DEFAULT_COST);
7977 size(4);
7978 format %{ "XOR $src1,$con,$dst\t! long" %}
7979 opcode(Assembler::xor_op3, Assembler::arith_op);
7980 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7981 ins_pipe(ialu_reg_imm);
7982 %}
7983
7984 //----------Convert to Boolean-------------------------------------------------
7985 // Nice hack for 32-bit tests but doesn't work for
7986 // 64-bit pointers.
7987 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
7988 match(Set dst (Conv2B src));
7989 effect( KILL ccr );
7990 ins_cost(DEFAULT_COST*2);
7991 format %{ "CMP R_G0,$src\n\t"
7992 "ADDX R_G0,0,$dst" %}
7993 ins_encode( enc_to_bool( src, dst ) );
7994 ins_pipe(ialu_reg_ialu);
7995 %}
7996
7997 #ifndef _LP64
7998 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
7999 match(Set dst (Conv2B src));
8000 effect( KILL ccr );
8001 ins_cost(DEFAULT_COST*2);
8002 format %{ "CMP R_G0,$src\n\t"
8003 "ADDX R_G0,0,$dst" %}
8004 ins_encode( enc_to_bool( src, dst ) );
8005 ins_pipe(ialu_reg_ialu);
8006 %}
8007 #else
8008 instruct convP2B( iRegI dst, iRegP src ) %{
8009 match(Set dst (Conv2B src));
8010 ins_cost(DEFAULT_COST*2);
8011 format %{ "MOV $src,$dst\n\t"
8012 "MOVRNZ $src,1,$dst" %}
8013 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8014 ins_pipe(ialu_clr_and_mover);
8015 %}
8016 #endif
8017
8018 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8019 match(Set dst (CmpLTMask src zero));
8020 effect(KILL ccr);
8021 size(4);
8022 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8023 ins_encode %{
8024 __ sra($src$$Register, 31, $dst$$Register);
8025 %}
8026 ins_pipe(ialu_reg_imm);
8027 %}
8028
8029 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8030 match(Set dst (CmpLTMask p q));
8031 effect( KILL ccr );
8032 ins_cost(DEFAULT_COST*4);
8033 format %{ "CMP $p,$q\n\t"
8034 "MOV #0,$dst\n\t"
8035 "BLT,a .+8\n\t"
8036 "MOV #-1,$dst" %}
8037 ins_encode( enc_ltmask(p,q,dst) );
8038 ins_pipe(ialu_reg_reg_ialu);
8039 %}
8040
8041 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8042 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8043 effect(KILL ccr, TEMP tmp);
8044 ins_cost(DEFAULT_COST*3);
8045
8046 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8047 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8048 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8049 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8050 ins_pipe(cadd_cmpltmask);
8051 %}
8052
8053 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8054 match(Set p (AndI (CmpLTMask p q) y));
8055 effect(KILL ccr);
8056 ins_cost(DEFAULT_COST*3);
8057
8058 format %{ "CMP $p,$q\n\t"
8059 "MOV $y,$p\n\t"
8060 "MOVge G0,$p" %}
8061 ins_encode %{
8062 __ cmp($p$$Register, $q$$Register);
8063 __ mov($y$$Register, $p$$Register);
8064 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8065 %}
8066 ins_pipe(ialu_reg_reg_ialu);
8067 %}
8068
8069 //-----------------------------------------------------------------
8070 // Direct raw moves between float and general registers using VIS3.
8071
8072 // ins_pipe(faddF_reg);
8073 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8074 predicate(UseVIS >= 3);
8075 match(Set dst (MoveF2I src));
8076
8077 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8078 ins_encode %{
8079 __ movstouw($src$$FloatRegister, $dst$$Register);
8080 %}
8081 ins_pipe(ialu_reg_reg);
8082 %}
8083
8084 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8085 predicate(UseVIS >= 3);
8086 match(Set dst (MoveI2F src));
8087
8088 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8089 ins_encode %{
8090 __ movwtos($src$$Register, $dst$$FloatRegister);
8091 %}
8092 ins_pipe(ialu_reg_reg);
8093 %}
8094
8095 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8096 predicate(UseVIS >= 3);
8097 match(Set dst (MoveD2L src));
8098
8099 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8100 ins_encode %{
8101 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8102 %}
8103 ins_pipe(ialu_reg_reg);
8104 %}
8105
8106 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8107 predicate(UseVIS >= 3);
8108 match(Set dst (MoveL2D src));
8109
8110 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8111 ins_encode %{
8112 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8113 %}
8114 ins_pipe(ialu_reg_reg);
8115 %}
8116
8117
8118 // Raw moves between float and general registers using stack.
8119
8120 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8121 match(Set dst (MoveF2I src));
8122 effect(DEF dst, USE src);
8123 ins_cost(MEMORY_REF_COST);
8124
8125 size(4);
8126 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8127 opcode(Assembler::lduw_op3);
8128 ins_encode(simple_form3_mem_reg( src, dst ) );
8129 ins_pipe(iload_mem);
8130 %}
8131
8132 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8133 match(Set dst (MoveI2F src));
8134 effect(DEF dst, USE src);
8135 ins_cost(MEMORY_REF_COST);
8136
8137 size(4);
8138 format %{ "LDF $src,$dst\t! MoveI2F" %}
8139 opcode(Assembler::ldf_op3);
8140 ins_encode(simple_form3_mem_reg(src, dst));
8141 ins_pipe(floadF_stk);
8142 %}
8143
8144 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8145 match(Set dst (MoveD2L src));
8146 effect(DEF dst, USE src);
8147 ins_cost(MEMORY_REF_COST);
8148
8149 size(4);
8150 format %{ "LDX $src,$dst\t! MoveD2L" %}
8151 opcode(Assembler::ldx_op3);
8152 ins_encode(simple_form3_mem_reg( src, dst ) );
8153 ins_pipe(iload_mem);
8154 %}
8155
8156 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8157 match(Set dst (MoveL2D src));
8158 effect(DEF dst, USE src);
8159 ins_cost(MEMORY_REF_COST);
8160
8161 size(4);
8162 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8163 opcode(Assembler::lddf_op3);
8164 ins_encode(simple_form3_mem_reg(src, dst));
8165 ins_pipe(floadD_stk);
8166 %}
8167
8168 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8169 match(Set dst (MoveF2I src));
8170 effect(DEF dst, USE src);
8171 ins_cost(MEMORY_REF_COST);
8172
8173 size(4);
8174 format %{ "STF $src,$dst\t! MoveF2I" %}
8175 opcode(Assembler::stf_op3);
8176 ins_encode(simple_form3_mem_reg(dst, src));
8177 ins_pipe(fstoreF_stk_reg);
8178 %}
8179
8180 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8181 match(Set dst (MoveI2F src));
8182 effect(DEF dst, USE src);
8183 ins_cost(MEMORY_REF_COST);
8184
8185 size(4);
8186 format %{ "STW $src,$dst\t! MoveI2F" %}
8187 opcode(Assembler::stw_op3);
8188 ins_encode(simple_form3_mem_reg( dst, src ) );
8189 ins_pipe(istore_mem_reg);
8190 %}
8191
8192 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8193 match(Set dst (MoveD2L src));
8194 effect(DEF dst, USE src);
8195 ins_cost(MEMORY_REF_COST);
8196
8197 size(4);
8198 format %{ "STDF $src,$dst\t! MoveD2L" %}
8199 opcode(Assembler::stdf_op3);
8200 ins_encode(simple_form3_mem_reg(dst, src));
8201 ins_pipe(fstoreD_stk_reg);
8202 %}
8203
8204 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8205 match(Set dst (MoveL2D src));
8206 effect(DEF dst, USE src);
8207 ins_cost(MEMORY_REF_COST);
8208
8209 size(4);
8210 format %{ "STX $src,$dst\t! MoveL2D" %}
8211 opcode(Assembler::stx_op3);
8212 ins_encode(simple_form3_mem_reg( dst, src ) );
8213 ins_pipe(istore_mem_reg);
8214 %}
8215
8216
8217 //----------Arithmetic Conversion Instructions---------------------------------
8218 // The conversions operations are all Alpha sorted. Please keep it that way!
8219
8220 instruct convD2F_reg(regF dst, regD src) %{
8221 match(Set dst (ConvD2F src));
8222 size(4);
8223 format %{ "FDTOS $src,$dst" %}
8224 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8225 ins_encode(form3_opf_rs2D_rdF(src, dst));
8226 ins_pipe(fcvtD2F);
8227 %}
8228
8229
8230 // Convert a double to an int in a float register.
8231 // If the double is a NAN, stuff a zero in instead.
8232 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8233 effect(DEF dst, USE src, KILL fcc0);
8234 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8235 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8236 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8237 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8238 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8239 "skip:" %}
8240 ins_encode(form_d2i_helper(src,dst));
8241 ins_pipe(fcvtD2I);
8242 %}
8243
8244 instruct convD2I_stk(stackSlotI dst, regD src) %{
8245 match(Set dst (ConvD2I src));
8246 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8247 expand %{
8248 regF tmp;
8249 convD2I_helper(tmp, src);
8250 regF_to_stkI(dst, tmp);
8251 %}
8252 %}
8253
8254 instruct convD2I_reg(iRegI dst, regD src) %{
8255 predicate(UseVIS >= 3);
8256 match(Set dst (ConvD2I src));
8257 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8258 expand %{
8259 regF tmp;
8260 convD2I_helper(tmp, src);
8261 MoveF2I_reg_reg(dst, tmp);
8262 %}
8263 %}
8264
8265
8266 // Convert a double to a long in a double register.
8267 // If the double is a NAN, stuff a zero in instead.
8268 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8269 effect(DEF dst, USE src, KILL fcc0);
8270 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8271 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8272 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8273 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8274 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8275 "skip:" %}
8276 ins_encode(form_d2l_helper(src,dst));
8277 ins_pipe(fcvtD2L);
8278 %}
8279
8280 instruct convD2L_stk(stackSlotL dst, regD src) %{
8281 match(Set dst (ConvD2L src));
8282 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8283 expand %{
8284 regD tmp;
8285 convD2L_helper(tmp, src);
8286 regD_to_stkL(dst, tmp);
8287 %}
8288 %}
8289
8290 instruct convD2L_reg(iRegL dst, regD src) %{
8291 predicate(UseVIS >= 3);
8292 match(Set dst (ConvD2L src));
8293 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8294 expand %{
8295 regD tmp;
8296 convD2L_helper(tmp, src);
8297 MoveD2L_reg_reg(dst, tmp);
8298 %}
8299 %}
8300
8301
8302 instruct convF2D_reg(regD dst, regF src) %{
8303 match(Set dst (ConvF2D src));
8304 format %{ "FSTOD $src,$dst" %}
8305 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8306 ins_encode(form3_opf_rs2F_rdD(src, dst));
8307 ins_pipe(fcvtF2D);
8308 %}
8309
8310
8311 // Convert a float to an int in a float register.
8312 // If the float is a NAN, stuff a zero in instead.
8313 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8314 effect(DEF dst, USE src, KILL fcc0);
8315 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8316 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8317 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8318 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8319 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8320 "skip:" %}
8321 ins_encode(form_f2i_helper(src,dst));
8322 ins_pipe(fcvtF2I);
8323 %}
8324
8325 instruct convF2I_stk(stackSlotI dst, regF src) %{
8326 match(Set dst (ConvF2I src));
8327 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8328 expand %{
8329 regF tmp;
8330 convF2I_helper(tmp, src);
8331 regF_to_stkI(dst, tmp);
8332 %}
8333 %}
8334
8335 instruct convF2I_reg(iRegI dst, regF src) %{
8336 predicate(UseVIS >= 3);
8337 match(Set dst (ConvF2I src));
8338 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8339 expand %{
8340 regF tmp;
8341 convF2I_helper(tmp, src);
8342 MoveF2I_reg_reg(dst, tmp);
8343 %}
8344 %}
8345
8346
8347 // Convert a float to a long in a float register.
8348 // If the float is a NAN, stuff a zero in instead.
8349 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8350 effect(DEF dst, USE src, KILL fcc0);
8351 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8352 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8353 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8354 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8355 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8356 "skip:" %}
8357 ins_encode(form_f2l_helper(src,dst));
8358 ins_pipe(fcvtF2L);
8359 %}
8360
8361 instruct convF2L_stk(stackSlotL dst, regF src) %{
8362 match(Set dst (ConvF2L src));
8363 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8364 expand %{
8365 regD tmp;
8366 convF2L_helper(tmp, src);
8367 regD_to_stkL(dst, tmp);
8368 %}
8369 %}
8370
8371 instruct convF2L_reg(iRegL dst, regF src) %{
8372 predicate(UseVIS >= 3);
8373 match(Set dst (ConvF2L src));
8374 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8375 expand %{
8376 regD tmp;
8377 convF2L_helper(tmp, src);
8378 MoveD2L_reg_reg(dst, tmp);
8379 %}
8380 %}
8381
8382
8383 instruct convI2D_helper(regD dst, regF tmp) %{
8384 effect(USE tmp, DEF dst);
8385 format %{ "FITOD $tmp,$dst" %}
8386 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8387 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8388 ins_pipe(fcvtI2D);
8389 %}
8390
8391 instruct convI2D_stk(stackSlotI src, regD dst) %{
8392 match(Set dst (ConvI2D src));
8393 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8394 expand %{
8395 regF tmp;
8396 stkI_to_regF(tmp, src);
8397 convI2D_helper(dst, tmp);
8398 %}
8399 %}
8400
8401 instruct convI2D_reg(regD_low dst, iRegI src) %{
8402 predicate(UseVIS >= 3);
8403 match(Set dst (ConvI2D src));
8404 expand %{
8405 regF tmp;
8406 MoveI2F_reg_reg(tmp, src);
8407 convI2D_helper(dst, tmp);
8408 %}
8409 %}
8410
8411 instruct convI2D_mem(regD_low dst, memory mem) %{
8412 match(Set dst (ConvI2D (LoadI mem)));
8413 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8414 size(8);
8415 format %{ "LDF $mem,$dst\n\t"
8416 "FITOD $dst,$dst" %}
8417 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8418 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8419 ins_pipe(floadF_mem);
8420 %}
8421
8422
8423 instruct convI2F_helper(regF dst, regF tmp) %{
8424 effect(DEF dst, USE tmp);
8425 format %{ "FITOS $tmp,$dst" %}
8426 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8427 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8428 ins_pipe(fcvtI2F);
8429 %}
8430
8431 instruct convI2F_stk(regF dst, stackSlotI src) %{
8432 match(Set dst (ConvI2F src));
8433 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8434 expand %{
8435 regF tmp;
8436 stkI_to_regF(tmp,src);
8437 convI2F_helper(dst, tmp);
8438 %}
8439 %}
8440
8441 instruct convI2F_reg(regF dst, iRegI src) %{
8442 predicate(UseVIS >= 3);
8443 match(Set dst (ConvI2F src));
8444 ins_cost(DEFAULT_COST);
8445 expand %{
8446 regF tmp;
8447 MoveI2F_reg_reg(tmp, src);
8448 convI2F_helper(dst, tmp);
8449 %}
8450 %}
8451
8452 instruct convI2F_mem( regF dst, memory mem ) %{
8453 match(Set dst (ConvI2F (LoadI mem)));
8454 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8455 size(8);
8456 format %{ "LDF $mem,$dst\n\t"
8457 "FITOS $dst,$dst" %}
8458 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8459 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8460 ins_pipe(floadF_mem);
8461 %}
8462
8463
8464 instruct convI2L_reg(iRegL dst, iRegI src) %{
8465 match(Set dst (ConvI2L src));
8466 size(4);
8467 format %{ "SRA $src,0,$dst\t! int->long" %}
8468 opcode(Assembler::sra_op3, Assembler::arith_op);
8469 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8470 ins_pipe(ialu_reg_reg);
8471 %}
8472
8473 // Zero-extend convert int to long
8474 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8475 match(Set dst (AndL (ConvI2L src) mask) );
8476 size(4);
8477 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8478 opcode(Assembler::srl_op3, Assembler::arith_op);
8479 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8480 ins_pipe(ialu_reg_reg);
8481 %}
8482
8483 // Zero-extend long
8484 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8485 match(Set dst (AndL src mask) );
8486 size(4);
8487 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8488 opcode(Assembler::srl_op3, Assembler::arith_op);
8489 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8490 ins_pipe(ialu_reg_reg);
8491 %}
8492
8493
8494 //-----------
8495 // Long to Double conversion using V8 opcodes.
8496 // Still useful because cheetah traps and becomes
8497 // amazingly slow for some common numbers.
8498
8499 // Magic constant, 0x43300000
8500 instruct loadConI_x43300000(iRegI dst) %{
8501 effect(DEF dst);
8502 size(4);
8503 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8504 ins_encode(SetHi22(0x43300000, dst));
8505 ins_pipe(ialu_none);
8506 %}
8507
8508 // Magic constant, 0x41f00000
8509 instruct loadConI_x41f00000(iRegI dst) %{
8510 effect(DEF dst);
8511 size(4);
8512 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8513 ins_encode(SetHi22(0x41f00000, dst));
8514 ins_pipe(ialu_none);
8515 %}
8516
8517 // Construct a double from two float halves
8518 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8519 effect(DEF dst, USE src1, USE src2);
8520 size(8);
8521 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8522 "FMOVS $src2.lo,$dst.lo" %}
8523 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8524 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8525 ins_pipe(faddD_reg_reg);
8526 %}
8527
8528 // Convert integer in high half of a double register (in the lower half of
8529 // the double register file) to double
8530 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8531 effect(DEF dst, USE src);
8532 size(4);
8533 format %{ "FITOD $src,$dst" %}
8534 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8535 ins_encode(form3_opf_rs2D_rdD(src, dst));
8536 ins_pipe(fcvtLHi2D);
8537 %}
8538
8539 // Add float double precision
8540 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8541 effect(DEF dst, USE src1, USE src2);
8542 size(4);
8543 format %{ "FADDD $src1,$src2,$dst" %}
8544 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8545 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8546 ins_pipe(faddD_reg_reg);
8547 %}
8548
8549 // Sub float double precision
8550 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8551 effect(DEF dst, USE src1, USE src2);
8552 size(4);
8553 format %{ "FSUBD $src1,$src2,$dst" %}
8554 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8555 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8556 ins_pipe(faddD_reg_reg);
8557 %}
8558
8559 // Mul float double precision
8560 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8561 effect(DEF dst, USE src1, USE src2);
8562 size(4);
8563 format %{ "FMULD $src1,$src2,$dst" %}
8564 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8565 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8566 ins_pipe(fmulD_reg_reg);
8567 %}
8568
8569 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8570 match(Set dst (ConvL2D src));
8571 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8572
8573 expand %{
8574 regD_low tmpsrc;
8575 iRegI ix43300000;
8576 iRegI ix41f00000;
8577 stackSlotL lx43300000;
8578 stackSlotL lx41f00000;
8579 regD_low dx43300000;
8580 regD dx41f00000;
8581 regD tmp1;
8582 regD_low tmp2;
8583 regD tmp3;
8584 regD tmp4;
8585
8586 stkL_to_regD(tmpsrc, src);
8587
8588 loadConI_x43300000(ix43300000);
8589 loadConI_x41f00000(ix41f00000);
8590 regI_to_stkLHi(lx43300000, ix43300000);
8591 regI_to_stkLHi(lx41f00000, ix41f00000);
8592 stkL_to_regD(dx43300000, lx43300000);
8593 stkL_to_regD(dx41f00000, lx41f00000);
8594
8595 convI2D_regDHi_regD(tmp1, tmpsrc);
8596 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8597 subD_regD_regD(tmp3, tmp2, dx43300000);
8598 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8599 addD_regD_regD(dst, tmp3, tmp4);
8600 %}
8601 %}
8602
8603 // Long to Double conversion using fast fxtof
8604 instruct convL2D_helper(regD dst, regD tmp) %{
8605 effect(DEF dst, USE tmp);
8606 size(4);
8607 format %{ "FXTOD $tmp,$dst" %}
8608 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8609 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8610 ins_pipe(fcvtL2D);
8611 %}
8612
8613 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8614 predicate(VM_Version::has_fast_fxtof());
8615 match(Set dst (ConvL2D src));
8616 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8617 expand %{
8618 regD tmp;
8619 stkL_to_regD(tmp, src);
8620 convL2D_helper(dst, tmp);
8621 %}
8622 %}
8623
8624 instruct convL2D_reg(regD dst, iRegL src) %{
8625 predicate(UseVIS >= 3);
8626 match(Set dst (ConvL2D src));
8627 expand %{
8628 regD tmp;
8629 MoveL2D_reg_reg(tmp, src);
8630 convL2D_helper(dst, tmp);
8631 %}
8632 %}
8633
8634 // Long to Float conversion using fast fxtof
8635 instruct convL2F_helper(regF dst, regD tmp) %{
8636 effect(DEF dst, USE tmp);
8637 size(4);
8638 format %{ "FXTOS $tmp,$dst" %}
8639 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8640 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8641 ins_pipe(fcvtL2F);
8642 %}
8643
8644 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8645 match(Set dst (ConvL2F src));
8646 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8647 expand %{
8648 regD tmp;
8649 stkL_to_regD(tmp, src);
8650 convL2F_helper(dst, tmp);
8651 %}
8652 %}
8653
8654 instruct convL2F_reg(regF dst, iRegL src) %{
8655 predicate(UseVIS >= 3);
8656 match(Set dst (ConvL2F src));
8657 ins_cost(DEFAULT_COST);
8658 expand %{
8659 regD tmp;
8660 MoveL2D_reg_reg(tmp, src);
8661 convL2F_helper(dst, tmp);
8662 %}
8663 %}
8664
8665 //-----------
8666
8667 instruct convL2I_reg(iRegI dst, iRegL src) %{
8668 match(Set dst (ConvL2I src));
8669 #ifndef _LP64
8670 format %{ "MOV $src.lo,$dst\t! long->int" %}
8671 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8672 ins_pipe(ialu_move_reg_I_to_L);
8673 #else
8674 size(4);
8675 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8676 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8677 ins_pipe(ialu_reg);
8678 #endif
8679 %}
8680
8681 // Register Shift Right Immediate
8682 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8683 match(Set dst (ConvL2I (RShiftL src cnt)));
8684
8685 size(4);
8686 format %{ "SRAX $src,$cnt,$dst" %}
8687 opcode(Assembler::srax_op3, Assembler::arith_op);
8688 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8689 ins_pipe(ialu_reg_imm);
8690 %}
8691
8692 //----------Control Flow Instructions------------------------------------------
8693 // Compare Instructions
8694 // Compare Integers
8695 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8696 match(Set icc (CmpI op1 op2));
8697 effect( DEF icc, USE op1, USE op2 );
8698
8699 size(4);
8700 format %{ "CMP $op1,$op2" %}
8701 opcode(Assembler::subcc_op3, Assembler::arith_op);
8702 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8703 ins_pipe(ialu_cconly_reg_reg);
8704 %}
8705
8706 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8707 match(Set icc (CmpU op1 op2));
8708
8709 size(4);
8710 format %{ "CMP $op1,$op2\t! unsigned" %}
8711 opcode(Assembler::subcc_op3, Assembler::arith_op);
8712 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8713 ins_pipe(ialu_cconly_reg_reg);
8714 %}
8715
8716 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8717 match(Set icc (CmpI op1 op2));
8718 effect( DEF icc, USE op1 );
8719
8720 size(4);
8721 format %{ "CMP $op1,$op2" %}
8722 opcode(Assembler::subcc_op3, Assembler::arith_op);
8723 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8724 ins_pipe(ialu_cconly_reg_imm);
8725 %}
8726
8727 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8728 match(Set icc (CmpI (AndI op1 op2) zero));
8729
8730 size(4);
8731 format %{ "BTST $op2,$op1" %}
8732 opcode(Assembler::andcc_op3, Assembler::arith_op);
8733 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8734 ins_pipe(ialu_cconly_reg_reg_zero);
8735 %}
8736
8737 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8738 match(Set icc (CmpI (AndI op1 op2) zero));
8739
8740 size(4);
8741 format %{ "BTST $op2,$op1" %}
8742 opcode(Assembler::andcc_op3, Assembler::arith_op);
8743 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8744 ins_pipe(ialu_cconly_reg_imm_zero);
8745 %}
8746
8747 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8748 match(Set xcc (CmpL op1 op2));
8749 effect( DEF xcc, USE op1, USE op2 );
8750
8751 size(4);
8752 format %{ "CMP $op1,$op2\t\t! long" %}
8753 opcode(Assembler::subcc_op3, Assembler::arith_op);
8754 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8755 ins_pipe(ialu_cconly_reg_reg);
8756 %}
8757
8758 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8759 match(Set xcc (CmpL op1 con));
8760 effect( DEF xcc, USE op1, USE con );
8761
8762 size(4);
8763 format %{ "CMP $op1,$con\t\t! long" %}
8764 opcode(Assembler::subcc_op3, Assembler::arith_op);
8765 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8766 ins_pipe(ialu_cconly_reg_reg);
8767 %}
8768
8769 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8770 match(Set xcc (CmpL (AndL op1 op2) zero));
8771 effect( DEF xcc, USE op1, USE op2 );
8772
8773 size(4);
8774 format %{ "BTST $op1,$op2\t\t! long" %}
8775 opcode(Assembler::andcc_op3, Assembler::arith_op);
8776 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8777 ins_pipe(ialu_cconly_reg_reg);
8778 %}
8779
8780 // useful for checking the alignment of a pointer:
8781 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8782 match(Set xcc (CmpL (AndL op1 con) zero));
8783 effect( DEF xcc, USE op1, USE con );
8784
8785 size(4);
8786 format %{ "BTST $op1,$con\t\t! long" %}
8787 opcode(Assembler::andcc_op3, Assembler::arith_op);
8788 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8789 ins_pipe(ialu_cconly_reg_reg);
8790 %}
8791
8792 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
8793 match(Set icc (CmpU op1 op2));
8794
8795 size(4);
8796 format %{ "CMP $op1,$op2\t! unsigned" %}
8797 opcode(Assembler::subcc_op3, Assembler::arith_op);
8798 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8799 ins_pipe(ialu_cconly_reg_imm);
8800 %}
8801
8802 // Compare Pointers
8803 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8804 match(Set pcc (CmpP op1 op2));
8805
8806 size(4);
8807 format %{ "CMP $op1,$op2\t! ptr" %}
8808 opcode(Assembler::subcc_op3, Assembler::arith_op);
8809 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8810 ins_pipe(ialu_cconly_reg_reg);
8811 %}
8812
8813 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8814 match(Set pcc (CmpP op1 op2));
8815
8816 size(4);
8817 format %{ "CMP $op1,$op2\t! ptr" %}
8818 opcode(Assembler::subcc_op3, Assembler::arith_op);
8819 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8820 ins_pipe(ialu_cconly_reg_imm);
8821 %}
8822
8823 // Compare Narrow oops
8824 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8825 match(Set icc (CmpN op1 op2));
8826
8827 size(4);
8828 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8829 opcode(Assembler::subcc_op3, Assembler::arith_op);
8830 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8831 ins_pipe(ialu_cconly_reg_reg);
8832 %}
8833
8834 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8835 match(Set icc (CmpN op1 op2));
8836
8837 size(4);
8838 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8839 opcode(Assembler::subcc_op3, Assembler::arith_op);
8840 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8841 ins_pipe(ialu_cconly_reg_imm);
8842 %}
8843
8844 //----------Max and Min--------------------------------------------------------
8845 // Min Instructions
8846 // Conditional move for min
8847 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8848 effect( USE_DEF op2, USE op1, USE icc );
8849
8850 size(4);
8851 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8852 opcode(Assembler::less);
8853 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8854 ins_pipe(ialu_reg_flags);
8855 %}
8856
8857 // Min Register with Register.
8858 instruct minI_eReg(iRegI op1, iRegI op2) %{
8859 match(Set op2 (MinI op1 op2));
8860 ins_cost(DEFAULT_COST*2);
8861 expand %{
8862 flagsReg icc;
8863 compI_iReg(icc,op1,op2);
8864 cmovI_reg_lt(op2,op1,icc);
8865 %}
8866 %}
8867
8868 // Max Instructions
8869 // Conditional move for max
8870 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8871 effect( USE_DEF op2, USE op1, USE icc );
8872 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8873 opcode(Assembler::greater);
8874 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8875 ins_pipe(ialu_reg_flags);
8876 %}
8877
8878 // Max Register with Register
8879 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8880 match(Set op2 (MaxI op1 op2));
8881 ins_cost(DEFAULT_COST*2);
8882 expand %{
8883 flagsReg icc;
8884 compI_iReg(icc,op1,op2);
8885 cmovI_reg_gt(op2,op1,icc);
8886 %}
8887 %}
8888
8889
8890 //----------Float Compares----------------------------------------------------
8891 // Compare floating, generate condition code
8892 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8893 match(Set fcc (CmpF src1 src2));
8894
8895 size(4);
8896 format %{ "FCMPs $fcc,$src1,$src2" %}
8897 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8898 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8899 ins_pipe(faddF_fcc_reg_reg_zero);
8900 %}
8901
8902 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8903 match(Set fcc (CmpD src1 src2));
8904
8905 size(4);
8906 format %{ "FCMPd $fcc,$src1,$src2" %}
8907 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8908 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8909 ins_pipe(faddD_fcc_reg_reg_zero);
8910 %}
8911
8912
8913 // Compare floating, generate -1,0,1
8914 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8915 match(Set dst (CmpF3 src1 src2));
8916 effect(KILL fcc0);
8917 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8918 format %{ "fcmpl $dst,$src1,$src2" %}
8919 // Primary = float
8920 opcode( true );
8921 ins_encode( floating_cmp( dst, src1, src2 ) );
8922 ins_pipe( floating_cmp );
8923 %}
8924
8925 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8926 match(Set dst (CmpD3 src1 src2));
8927 effect(KILL fcc0);
8928 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8929 format %{ "dcmpl $dst,$src1,$src2" %}
8930 // Primary = double (not float)
8931 opcode( false );
8932 ins_encode( floating_cmp( dst, src1, src2 ) );
8933 ins_pipe( floating_cmp );
8934 %}
8935
8936 //----------Branches---------------------------------------------------------
8937 // Jump
8938 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8939 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8940 match(Jump switch_val);
8941 effect(TEMP table);
8942
8943 ins_cost(350);
8944
8945 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
8946 "LD [O7 + $switch_val], O7\n\t"
8947 "JUMP O7" %}
8948 ins_encode %{
8949 // Calculate table address into a register.
8950 Register table_reg;
8951 Register label_reg = O7;
8952 // If we are calculating the size of this instruction don't trust
8953 // zero offsets because they might change when
8954 // MachConstantBaseNode decides to optimize the constant table
8955 // base.
8956 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
8957 table_reg = $constanttablebase;
8958 } else {
8959 table_reg = O7;
8960 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
8961 __ add($constanttablebase, con_offset, table_reg);
8962 }
8963
8964 // Jump to base address + switch value
8965 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
8966 __ jmp(label_reg, G0);
8967 __ delayed()->nop();
8968 %}
8969 ins_pipe(ialu_reg_reg);
8970 %}
8971
8972 // Direct Branch. Use V8 version with longer range.
8973 instruct branch(label labl) %{
8974 match(Goto);
8975 effect(USE labl);
8976
8977 size(8);
8978 ins_cost(BRANCH_COST);
8979 format %{ "BA $labl" %}
8980 ins_encode %{
8981 Label* L = $labl$$label;
8982 __ ba(*L);
8983 __ delayed()->nop();
8984 %}
8985 ins_avoid_back_to_back(AVOID_BEFORE);
8986 ins_pipe(br);
8987 %}
8988
8989 // Direct Branch, short with no delay slot
8990 instruct branch_short(label labl) %{
8991 match(Goto);
8992 predicate(UseCBCond);
8993 effect(USE labl);
8994
8995 size(4);
8996 ins_cost(BRANCH_COST);
8997 format %{ "BA $labl\t! short branch" %}
8998 ins_encode %{
8999 Label* L = $labl$$label;
9000 assert(__ use_cbcond(*L), "back to back cbcond");
9001 __ ba_short(*L);
9002 %}
9003 ins_short_branch(1);
9004 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9005 ins_pipe(cbcond_reg_imm);
9006 %}
9007
9008 // Conditional Direct Branch
9009 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9010 match(If cmp icc);
9011 effect(USE labl);
9012
9013 size(8);
9014 ins_cost(BRANCH_COST);
9015 format %{ "BP$cmp $icc,$labl" %}
9016 // Prim = bits 24-22, Secnd = bits 31-30
9017 ins_encode( enc_bp( labl, cmp, icc ) );
9018 ins_avoid_back_to_back(AVOID_BEFORE);
9019 ins_pipe(br_cc);
9020 %}
9021
9022 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9023 match(If cmp icc);
9024 effect(USE labl);
9025
9026 ins_cost(BRANCH_COST);
9027 format %{ "BP$cmp $icc,$labl" %}
9028 // Prim = bits 24-22, Secnd = bits 31-30
9029 ins_encode( enc_bp( labl, cmp, icc ) );
9030 ins_avoid_back_to_back(AVOID_BEFORE);
9031 ins_pipe(br_cc);
9032 %}
9033
9034 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9035 match(If cmp pcc);
9036 effect(USE labl);
9037
9038 size(8);
9039 ins_cost(BRANCH_COST);
9040 format %{ "BP$cmp $pcc,$labl" %}
9041 ins_encode %{
9042 Label* L = $labl$$label;
9043 Assembler::Predict predict_taken =
9044 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9045
9046 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9047 __ delayed()->nop();
9048 %}
9049 ins_avoid_back_to_back(AVOID_BEFORE);
9050 ins_pipe(br_cc);
9051 %}
9052
9053 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9054 match(If cmp fcc);
9055 effect(USE labl);
9056
9057 size(8);
9058 ins_cost(BRANCH_COST);
9059 format %{ "FBP$cmp $fcc,$labl" %}
9060 ins_encode %{
9061 Label* L = $labl$$label;
9062 Assembler::Predict predict_taken =
9063 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9064
9065 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9066 __ delayed()->nop();
9067 %}
9068 ins_avoid_back_to_back(AVOID_BEFORE);
9069 ins_pipe(br_fcc);
9070 %}
9071
9072 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9073 match(CountedLoopEnd cmp icc);
9074 effect(USE labl);
9075
9076 size(8);
9077 ins_cost(BRANCH_COST);
9078 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9079 // Prim = bits 24-22, Secnd = bits 31-30
9080 ins_encode( enc_bp( labl, cmp, icc ) );
9081 ins_avoid_back_to_back(AVOID_BEFORE);
9082 ins_pipe(br_cc);
9083 %}
9084
9085 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9086 match(CountedLoopEnd cmp icc);
9087 effect(USE labl);
9088
9089 size(8);
9090 ins_cost(BRANCH_COST);
9091 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9092 // Prim = bits 24-22, Secnd = bits 31-30
9093 ins_encode( enc_bp( labl, cmp, icc ) );
9094 ins_avoid_back_to_back(AVOID_BEFORE);
9095 ins_pipe(br_cc);
9096 %}
9097
9098 // Compare and branch instructions
9099 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9100 match(If cmp (CmpI op1 op2));
9101 effect(USE labl, KILL icc);
9102
9103 size(12);
9104 ins_cost(BRANCH_COST);
9105 format %{ "CMP $op1,$op2\t! int\n\t"
9106 "BP$cmp $labl" %}
9107 ins_encode %{
9108 Label* L = $labl$$label;
9109 Assembler::Predict predict_taken =
9110 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9111 __ cmp($op1$$Register, $op2$$Register);
9112 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9113 __ delayed()->nop();
9114 %}
9115 ins_pipe(cmp_br_reg_reg);
9116 %}
9117
9118 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9119 match(If cmp (CmpI op1 op2));
9120 effect(USE labl, KILL icc);
9121
9122 size(12);
9123 ins_cost(BRANCH_COST);
9124 format %{ "CMP $op1,$op2\t! int\n\t"
9125 "BP$cmp $labl" %}
9126 ins_encode %{
9127 Label* L = $labl$$label;
9128 Assembler::Predict predict_taken =
9129 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9130 __ cmp($op1$$Register, $op2$$constant);
9131 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9132 __ delayed()->nop();
9133 %}
9134 ins_pipe(cmp_br_reg_imm);
9135 %}
9136
9137 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9138 match(If cmp (CmpU op1 op2));
9139 effect(USE labl, KILL icc);
9140
9141 size(12);
9142 ins_cost(BRANCH_COST);
9143 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9144 "BP$cmp $labl" %}
9145 ins_encode %{
9146 Label* L = $labl$$label;
9147 Assembler::Predict predict_taken =
9148 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9149 __ cmp($op1$$Register, $op2$$Register);
9150 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9151 __ delayed()->nop();
9152 %}
9153 ins_pipe(cmp_br_reg_reg);
9154 %}
9155
9156 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9157 match(If cmp (CmpU op1 op2));
9158 effect(USE labl, KILL icc);
9159
9160 size(12);
9161 ins_cost(BRANCH_COST);
9162 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9163 "BP$cmp $labl" %}
9164 ins_encode %{
9165 Label* L = $labl$$label;
9166 Assembler::Predict predict_taken =
9167 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9168 __ cmp($op1$$Register, $op2$$constant);
9169 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9170 __ delayed()->nop();
9171 %}
9172 ins_pipe(cmp_br_reg_imm);
9173 %}
9174
9175 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9176 match(If cmp (CmpL op1 op2));
9177 effect(USE labl, KILL xcc);
9178
9179 size(12);
9180 ins_cost(BRANCH_COST);
9181 format %{ "CMP $op1,$op2\t! long\n\t"
9182 "BP$cmp $labl" %}
9183 ins_encode %{
9184 Label* L = $labl$$label;
9185 Assembler::Predict predict_taken =
9186 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9187 __ cmp($op1$$Register, $op2$$Register);
9188 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9189 __ delayed()->nop();
9190 %}
9191 ins_pipe(cmp_br_reg_reg);
9192 %}
9193
9194 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9195 match(If cmp (CmpL op1 op2));
9196 effect(USE labl, KILL xcc);
9197
9198 size(12);
9199 ins_cost(BRANCH_COST);
9200 format %{ "CMP $op1,$op2\t! long\n\t"
9201 "BP$cmp $labl" %}
9202 ins_encode %{
9203 Label* L = $labl$$label;
9204 Assembler::Predict predict_taken =
9205 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9206 __ cmp($op1$$Register, $op2$$constant);
9207 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9208 __ delayed()->nop();
9209 %}
9210 ins_pipe(cmp_br_reg_imm);
9211 %}
9212
9213 // Compare Pointers and branch
9214 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9215 match(If cmp (CmpP op1 op2));
9216 effect(USE labl, KILL pcc);
9217
9218 size(12);
9219 ins_cost(BRANCH_COST);
9220 format %{ "CMP $op1,$op2\t! ptr\n\t"
9221 "B$cmp $labl" %}
9222 ins_encode %{
9223 Label* L = $labl$$label;
9224 Assembler::Predict predict_taken =
9225 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9226 __ cmp($op1$$Register, $op2$$Register);
9227 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9228 __ delayed()->nop();
9229 %}
9230 ins_pipe(cmp_br_reg_reg);
9231 %}
9232
9233 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9234 match(If cmp (CmpP op1 null));
9235 effect(USE labl, KILL pcc);
9236
9237 size(12);
9238 ins_cost(BRANCH_COST);
9239 format %{ "CMP $op1,0\t! ptr\n\t"
9240 "B$cmp $labl" %}
9241 ins_encode %{
9242 Label* L = $labl$$label;
9243 Assembler::Predict predict_taken =
9244 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9245 __ cmp($op1$$Register, G0);
9246 // bpr() is not used here since it has shorter distance.
9247 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9248 __ delayed()->nop();
9249 %}
9250 ins_pipe(cmp_br_reg_reg);
9251 %}
9252
9253 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9254 match(If cmp (CmpN op1 op2));
9255 effect(USE labl, KILL icc);
9256
9257 size(12);
9258 ins_cost(BRANCH_COST);
9259 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9260 "BP$cmp $labl" %}
9261 ins_encode %{
9262 Label* L = $labl$$label;
9263 Assembler::Predict predict_taken =
9264 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9265 __ cmp($op1$$Register, $op2$$Register);
9266 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9267 __ delayed()->nop();
9268 %}
9269 ins_pipe(cmp_br_reg_reg);
9270 %}
9271
9272 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9273 match(If cmp (CmpN op1 null));
9274 effect(USE labl, KILL icc);
9275
9276 size(12);
9277 ins_cost(BRANCH_COST);
9278 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9279 "BP$cmp $labl" %}
9280 ins_encode %{
9281 Label* L = $labl$$label;
9282 Assembler::Predict predict_taken =
9283 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9284 __ cmp($op1$$Register, G0);
9285 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9286 __ delayed()->nop();
9287 %}
9288 ins_pipe(cmp_br_reg_reg);
9289 %}
9290
9291 // Loop back branch
9292 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9293 match(CountedLoopEnd cmp (CmpI op1 op2));
9294 effect(USE labl, KILL icc);
9295
9296 size(12);
9297 ins_cost(BRANCH_COST);
9298 format %{ "CMP $op1,$op2\t! int\n\t"
9299 "BP$cmp $labl\t! Loop end" %}
9300 ins_encode %{
9301 Label* L = $labl$$label;
9302 Assembler::Predict predict_taken =
9303 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9304 __ cmp($op1$$Register, $op2$$Register);
9305 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9306 __ delayed()->nop();
9307 %}
9308 ins_pipe(cmp_br_reg_reg);
9309 %}
9310
9311 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9312 match(CountedLoopEnd cmp (CmpI op1 op2));
9313 effect(USE labl, KILL icc);
9314
9315 size(12);
9316 ins_cost(BRANCH_COST);
9317 format %{ "CMP $op1,$op2\t! int\n\t"
9318 "BP$cmp $labl\t! Loop end" %}
9319 ins_encode %{
9320 Label* L = $labl$$label;
9321 Assembler::Predict predict_taken =
9322 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9323 __ cmp($op1$$Register, $op2$$constant);
9324 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9325 __ delayed()->nop();
9326 %}
9327 ins_pipe(cmp_br_reg_imm);
9328 %}
9329
9330 // Short compare and branch instructions
9331 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9332 match(If cmp (CmpI op1 op2));
9333 predicate(UseCBCond);
9334 effect(USE labl, KILL icc);
9335
9336 size(4);
9337 ins_cost(BRANCH_COST);
9338 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9339 ins_encode %{
9340 Label* L = $labl$$label;
9341 assert(__ use_cbcond(*L), "back to back cbcond");
9342 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9343 %}
9344 ins_short_branch(1);
9345 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9346 ins_pipe(cbcond_reg_reg);
9347 %}
9348
9349 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9350 match(If cmp (CmpI op1 op2));
9351 predicate(UseCBCond);
9352 effect(USE labl, KILL icc);
9353
9354 size(4);
9355 ins_cost(BRANCH_COST);
9356 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9357 ins_encode %{
9358 Label* L = $labl$$label;
9359 assert(__ use_cbcond(*L), "back to back cbcond");
9360 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9361 %}
9362 ins_short_branch(1);
9363 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9364 ins_pipe(cbcond_reg_imm);
9365 %}
9366
9367 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9368 match(If cmp (CmpU op1 op2));
9369 predicate(UseCBCond);
9370 effect(USE labl, KILL icc);
9371
9372 size(4);
9373 ins_cost(BRANCH_COST);
9374 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9375 ins_encode %{
9376 Label* L = $labl$$label;
9377 assert(__ use_cbcond(*L), "back to back cbcond");
9378 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9379 %}
9380 ins_short_branch(1);
9381 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9382 ins_pipe(cbcond_reg_reg);
9383 %}
9384
9385 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9386 match(If cmp (CmpU op1 op2));
9387 predicate(UseCBCond);
9388 effect(USE labl, KILL icc);
9389
9390 size(4);
9391 ins_cost(BRANCH_COST);
9392 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9393 ins_encode %{
9394 Label* L = $labl$$label;
9395 assert(__ use_cbcond(*L), "back to back cbcond");
9396 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9397 %}
9398 ins_short_branch(1);
9399 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9400 ins_pipe(cbcond_reg_imm);
9401 %}
9402
9403 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9404 match(If cmp (CmpL op1 op2));
9405 predicate(UseCBCond);
9406 effect(USE labl, KILL xcc);
9407
9408 size(4);
9409 ins_cost(BRANCH_COST);
9410 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9411 ins_encode %{
9412 Label* L = $labl$$label;
9413 assert(__ use_cbcond(*L), "back to back cbcond");
9414 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9415 %}
9416 ins_short_branch(1);
9417 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9418 ins_pipe(cbcond_reg_reg);
9419 %}
9420
9421 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9422 match(If cmp (CmpL op1 op2));
9423 predicate(UseCBCond);
9424 effect(USE labl, KILL xcc);
9425
9426 size(4);
9427 ins_cost(BRANCH_COST);
9428 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9429 ins_encode %{
9430 Label* L = $labl$$label;
9431 assert(__ use_cbcond(*L), "back to back cbcond");
9432 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9433 %}
9434 ins_short_branch(1);
9435 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9436 ins_pipe(cbcond_reg_imm);
9437 %}
9438
9439 // Compare Pointers and branch
9440 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9441 match(If cmp (CmpP op1 op2));
9442 predicate(UseCBCond);
9443 effect(USE labl, KILL pcc);
9444
9445 size(4);
9446 ins_cost(BRANCH_COST);
9447 #ifdef _LP64
9448 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9449 #else
9450 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9451 #endif
9452 ins_encode %{
9453 Label* L = $labl$$label;
9454 assert(__ use_cbcond(*L), "back to back cbcond");
9455 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9456 %}
9457 ins_short_branch(1);
9458 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9459 ins_pipe(cbcond_reg_reg);
9460 %}
9461
9462 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9463 match(If cmp (CmpP op1 null));
9464 predicate(UseCBCond);
9465 effect(USE labl, KILL pcc);
9466
9467 size(4);
9468 ins_cost(BRANCH_COST);
9469 #ifdef _LP64
9470 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9471 #else
9472 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9473 #endif
9474 ins_encode %{
9475 Label* L = $labl$$label;
9476 assert(__ use_cbcond(*L), "back to back cbcond");
9477 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9478 %}
9479 ins_short_branch(1);
9480 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9481 ins_pipe(cbcond_reg_reg);
9482 %}
9483
9484 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9485 match(If cmp (CmpN op1 op2));
9486 predicate(UseCBCond);
9487 effect(USE labl, KILL icc);
9488
9489 size(4);
9490 ins_cost(BRANCH_COST);
9491 format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %}
9492 ins_encode %{
9493 Label* L = $labl$$label;
9494 assert(__ use_cbcond(*L), "back to back cbcond");
9495 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9496 %}
9497 ins_short_branch(1);
9498 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9499 ins_pipe(cbcond_reg_reg);
9500 %}
9501
9502 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9503 match(If cmp (CmpN op1 null));
9504 predicate(UseCBCond);
9505 effect(USE labl, KILL icc);
9506
9507 size(4);
9508 ins_cost(BRANCH_COST);
9509 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9510 ins_encode %{
9511 Label* L = $labl$$label;
9512 assert(__ use_cbcond(*L), "back to back cbcond");
9513 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9514 %}
9515 ins_short_branch(1);
9516 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9517 ins_pipe(cbcond_reg_reg);
9518 %}
9519
9520 // Loop back branch
9521 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9522 match(CountedLoopEnd cmp (CmpI op1 op2));
9523 predicate(UseCBCond);
9524 effect(USE labl, KILL icc);
9525
9526 size(4);
9527 ins_cost(BRANCH_COST);
9528 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9529 ins_encode %{
9530 Label* L = $labl$$label;
9531 assert(__ use_cbcond(*L), "back to back cbcond");
9532 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9533 %}
9534 ins_short_branch(1);
9535 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9536 ins_pipe(cbcond_reg_reg);
9537 %}
9538
9539 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9540 match(CountedLoopEnd cmp (CmpI op1 op2));
9541 predicate(UseCBCond);
9542 effect(USE labl, KILL icc);
9543
9544 size(4);
9545 ins_cost(BRANCH_COST);
9546 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9547 ins_encode %{
9548 Label* L = $labl$$label;
9549 assert(__ use_cbcond(*L), "back to back cbcond");
9550 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9551 %}
9552 ins_short_branch(1);
9553 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9554 ins_pipe(cbcond_reg_imm);
9555 %}
9556
9557 // Branch-on-register tests all 64 bits. We assume that values
9558 // in 64-bit registers always remains zero or sign extended
9559 // unless our code munges the high bits. Interrupts can chop
9560 // the high order bits to zero or sign at any time.
9561 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9562 match(If cmp (CmpI op1 zero));
9563 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9564 effect(USE labl);
9565
9566 size(8);
9567 ins_cost(BRANCH_COST);
9568 format %{ "BR$cmp $op1,$labl" %}
9569 ins_encode( enc_bpr( labl, cmp, op1 ) );
9570 ins_avoid_back_to_back(AVOID_BEFORE);
9571 ins_pipe(br_reg);
9572 %}
9573
9574 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9575 match(If cmp (CmpP op1 null));
9576 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9577 effect(USE labl);
9578
9579 size(8);
9580 ins_cost(BRANCH_COST);
9581 format %{ "BR$cmp $op1,$labl" %}
9582 ins_encode( enc_bpr( labl, cmp, op1 ) );
9583 ins_avoid_back_to_back(AVOID_BEFORE);
9584 ins_pipe(br_reg);
9585 %}
9586
9587 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9588 match(If cmp (CmpL op1 zero));
9589 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9590 effect(USE labl);
9591
9592 size(8);
9593 ins_cost(BRANCH_COST);
9594 format %{ "BR$cmp $op1,$labl" %}
9595 ins_encode( enc_bpr( labl, cmp, op1 ) );
9596 ins_avoid_back_to_back(AVOID_BEFORE);
9597 ins_pipe(br_reg);
9598 %}
9599
9600
9601 // ============================================================================
9602 // Long Compare
9603 //
9604 // Currently we hold longs in 2 registers. Comparing such values efficiently
9605 // is tricky. The flavor of compare used depends on whether we are testing
9606 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9607 // The GE test is the negated LT test. The LE test can be had by commuting
9608 // the operands (yielding a GE test) and then negating; negate again for the
9609 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9610 // NE test is negated from that.
9611
9612 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9613 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9614 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9615 // are collapsed internally in the ADLC's dfa-gen code. The match for
9616 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9617 // foo match ends up with the wrong leaf. One fix is to not match both
9618 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9619 // both forms beat the trinary form of long-compare and both are very useful
9620 // on Intel which has so few registers.
9621
9622 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9623 match(If cmp xcc);
9624 effect(USE labl);
9625
9626 size(8);
9627 ins_cost(BRANCH_COST);
9628 format %{ "BP$cmp $xcc,$labl" %}
9629 ins_encode %{
9630 Label* L = $labl$$label;
9631 Assembler::Predict predict_taken =
9632 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9633
9634 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9635 __ delayed()->nop();
9636 %}
9637 ins_avoid_back_to_back(AVOID_BEFORE);
9638 ins_pipe(br_cc);
9639 %}
9640
9641 // Manifest a CmpL3 result in an integer register. Very painful.
9642 // This is the test to avoid.
9643 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9644 match(Set dst (CmpL3 src1 src2) );
9645 effect( KILL ccr );
9646 ins_cost(6*DEFAULT_COST);
9647 size(24);
9648 format %{ "CMP $src1,$src2\t\t! long\n"
9649 "\tBLT,a,pn done\n"
9650 "\tMOV -1,$dst\t! delay slot\n"
9651 "\tBGT,a,pn done\n"
9652 "\tMOV 1,$dst\t! delay slot\n"
9653 "\tCLR $dst\n"
9654 "done:" %}
9655 ins_encode( cmpl_flag(src1,src2,dst) );
9656 ins_pipe(cmpL_reg);
9657 %}
9658
9659 // Conditional move
9660 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9661 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9662 ins_cost(150);
9663 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9664 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9665 ins_pipe(ialu_reg);
9666 %}
9667
9668 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9669 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9670 ins_cost(140);
9671 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9672 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9673 ins_pipe(ialu_imm);
9674 %}
9675
9676 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9677 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9678 ins_cost(150);
9679 format %{ "MOV$cmp $xcc,$src,$dst" %}
9680 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9681 ins_pipe(ialu_reg);
9682 %}
9683
9684 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9685 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9686 ins_cost(140);
9687 format %{ "MOV$cmp $xcc,$src,$dst" %}
9688 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9689 ins_pipe(ialu_imm);
9690 %}
9691
9692 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9693 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9694 ins_cost(150);
9695 format %{ "MOV$cmp $xcc,$src,$dst" %}
9696 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9697 ins_pipe(ialu_reg);
9698 %}
9699
9700 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9701 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9702 ins_cost(150);
9703 format %{ "MOV$cmp $xcc,$src,$dst" %}
9704 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9705 ins_pipe(ialu_reg);
9706 %}
9707
9708 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9709 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9710 ins_cost(140);
9711 format %{ "MOV$cmp $xcc,$src,$dst" %}
9712 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9713 ins_pipe(ialu_imm);
9714 %}
9715
9716 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9717 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9718 ins_cost(150);
9719 opcode(0x101);
9720 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9721 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9722 ins_pipe(int_conditional_float_move);
9723 %}
9724
9725 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9726 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9727 ins_cost(150);
9728 opcode(0x102);
9729 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9730 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9731 ins_pipe(int_conditional_float_move);
9732 %}
9733
9734 // ============================================================================
9735 // Safepoint Instruction
9736 instruct safePoint_poll(iRegP poll) %{
9737 match(SafePoint poll);
9738 effect(USE poll);
9739
9740 size(4);
9741 #ifdef _LP64
9742 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9743 #else
9744 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9745 #endif
9746 ins_encode %{
9747 __ relocate(relocInfo::poll_type);
9748 __ ld_ptr($poll$$Register, 0, G0);
9749 %}
9750 ins_pipe(loadPollP);
9751 %}
9752
9753 // ============================================================================
9754 // Call Instructions
9755 // Call Java Static Instruction
9756 instruct CallStaticJavaDirect( method meth ) %{
9757 match(CallStaticJava);
9758 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9759 effect(USE meth);
9760
9761 size(8);
9762 ins_cost(CALL_COST);
9763 format %{ "CALL,static ; NOP ==> " %}
9764 ins_encode( Java_Static_Call( meth ), call_epilog );
9765 ins_avoid_back_to_back(AVOID_BEFORE);
9766 ins_pipe(simple_call);
9767 %}
9768
9769 // Call Java Static Instruction (method handle version)
9770 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9771 match(CallStaticJava);
9772 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9773 effect(USE meth, KILL l7_mh_SP_save);
9774
9775 size(16);
9776 ins_cost(CALL_COST);
9777 format %{ "CALL,static/MethodHandle" %}
9778 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9779 ins_pipe(simple_call);
9780 %}
9781
9782 // Call Java Dynamic Instruction
9783 instruct CallDynamicJavaDirect( method meth ) %{
9784 match(CallDynamicJava);
9785 effect(USE meth);
9786
9787 ins_cost(CALL_COST);
9788 format %{ "SET (empty),R_G5\n\t"
9789 "CALL,dynamic ; NOP ==> " %}
9790 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9791 ins_pipe(call);
9792 %}
9793
9794 // Call Runtime Instruction
9795 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9796 match(CallRuntime);
9797 effect(USE meth, KILL l7);
9798 ins_cost(CALL_COST);
9799 format %{ "CALL,runtime" %}
9800 ins_encode( Java_To_Runtime( meth ),
9801 call_epilog, adjust_long_from_native_call );
9802 ins_avoid_back_to_back(AVOID_BEFORE);
9803 ins_pipe(simple_call);
9804 %}
9805
9806 // Call runtime without safepoint - same as CallRuntime
9807 instruct CallLeafDirect(method meth, l7RegP l7) %{
9808 match(CallLeaf);
9809 effect(USE meth, KILL l7);
9810 ins_cost(CALL_COST);
9811 format %{ "CALL,runtime leaf" %}
9812 ins_encode( Java_To_Runtime( meth ),
9813 call_epilog,
9814 adjust_long_from_native_call );
9815 ins_avoid_back_to_back(AVOID_BEFORE);
9816 ins_pipe(simple_call);
9817 %}
9818
9819 // Call runtime without safepoint - same as CallLeaf
9820 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9821 match(CallLeafNoFP);
9822 effect(USE meth, KILL l7);
9823 ins_cost(CALL_COST);
9824 format %{ "CALL,runtime leaf nofp" %}
9825 ins_encode( Java_To_Runtime( meth ),
9826 call_epilog,
9827 adjust_long_from_native_call );
9828 ins_avoid_back_to_back(AVOID_BEFORE);
9829 ins_pipe(simple_call);
9830 %}
9831
9832 // Tail Call; Jump from runtime stub to Java code.
9833 // Also known as an 'interprocedural jump'.
9834 // Target of jump will eventually return to caller.
9835 // TailJump below removes the return address.
9836 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9837 match(TailCall jump_target method_oop );
9838
9839 ins_cost(CALL_COST);
9840 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9841 ins_encode(form_jmpl(jump_target));
9842 ins_avoid_back_to_back(AVOID_BEFORE);
9843 ins_pipe(tail_call);
9844 %}
9845
9846
9847 // Return Instruction
9848 instruct Ret() %{
9849 match(Return);
9850
9851 // The epilogue node did the ret already.
9852 size(0);
9853 format %{ "! return" %}
9854 ins_encode();
9855 ins_pipe(empty);
9856 %}
9857
9858
9859 // Tail Jump; remove the return address; jump to target.
9860 // TailCall above leaves the return address around.
9861 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9862 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9863 // "restore" before this instruction (in Epilogue), we need to materialize it
9864 // in %i0.
9865 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9866 match( TailJump jump_target ex_oop );
9867 ins_cost(CALL_COST);
9868 format %{ "! discard R_O7\n\t"
9869 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9870 ins_encode(form_jmpl_set_exception_pc(jump_target));
9871 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9872 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9873 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9874 ins_avoid_back_to_back(AVOID_BEFORE);
9875 ins_pipe(tail_call);
9876 %}
9877
9878 // Create exception oop: created by stack-crawling runtime code.
9879 // Created exception is now available to this handler, and is setup
9880 // just prior to jumping to this handler. No code emitted.
9881 instruct CreateException( o0RegP ex_oop )
9882 %{
9883 match(Set ex_oop (CreateEx));
9884 ins_cost(0);
9885
9886 size(0);
9887 // use the following format syntax
9888 format %{ "! exception oop is in R_O0; no code emitted" %}
9889 ins_encode();
9890 ins_pipe(empty);
9891 %}
9892
9893
9894 // Rethrow exception:
9895 // The exception oop will come in the first argument position.
9896 // Then JUMP (not call) to the rethrow stub code.
9897 instruct RethrowException()
9898 %{
9899 match(Rethrow);
9900 ins_cost(CALL_COST);
9901
9902 // use the following format syntax
9903 format %{ "Jmp rethrow_stub" %}
9904 ins_encode(enc_rethrow);
9905 ins_avoid_back_to_back(AVOID_BEFORE);
9906 ins_pipe(tail_call);
9907 %}
9908
9909
9910 // Die now
9911 instruct ShouldNotReachHere( )
9912 %{
9913 match(Halt);
9914 ins_cost(CALL_COST);
9915
9916 size(4);
9917 // Use the following format syntax
9918 format %{ "ILLTRAP ; ShouldNotReachHere" %}
9919 ins_encode( form2_illtrap() );
9920 ins_pipe(tail_call);
9921 %}
9922
9923 // ============================================================================
9924 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9925 // array for an instance of the superklass. Set a hidden internal cache on a
9926 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9927 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9928 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9929 match(Set index (PartialSubtypeCheck sub super));
9930 effect( KILL pcc, KILL o7 );
9931 ins_cost(DEFAULT_COST*10);
9932 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
9933 ins_encode( enc_PartialSubtypeCheck() );
9934 ins_avoid_back_to_back(AVOID_BEFORE);
9935 ins_pipe(partial_subtype_check_pipe);
9936 %}
9937
9938 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9939 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9940 effect( KILL idx, KILL o7 );
9941 ins_cost(DEFAULT_COST*10);
9942 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9943 ins_encode( enc_PartialSubtypeCheck() );
9944 ins_avoid_back_to_back(AVOID_BEFORE);
9945 ins_pipe(partial_subtype_check_pipe);
9946 %}
9947
9948
9949 // ============================================================================
9950 // inlined locking and unlocking
9951
9952 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9953 match(Set pcc (FastLock object box));
9954
9955 effect(TEMP scratch2, USE_KILL box, KILL scratch);
9956 ins_cost(100);
9957
9958 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
9959 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9960 ins_pipe(long_memory_op);
9961 %}
9962
9963
9964 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9965 match(Set pcc (FastUnlock object box));
9966 effect(TEMP scratch2, USE_KILL box, KILL scratch);
9967 ins_cost(100);
9968
9969 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
9970 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9971 ins_pipe(long_memory_op);
9972 %}
9973
9974 // The encodings are generic.
9975 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9976 predicate(!use_block_zeroing(n->in(2)) );
9977 match(Set dummy (ClearArray cnt base));
9978 effect(TEMP temp, KILL ccr);
9979 ins_cost(300);
9980 format %{ "MOV $cnt,$temp\n"
9981 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
9982 " BRge loop\t\t! Clearing loop\n"
9983 " STX G0,[$base+$temp]\t! delay slot" %}
9984
9985 ins_encode %{
9986 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
9987 Register nof_bytes_arg = $cnt$$Register;
9988 Register nof_bytes_tmp = $temp$$Register;
9989 Register base_pointer_arg = $base$$Register;
9990
9991 Label loop;
9992 __ mov(nof_bytes_arg, nof_bytes_tmp);
9993
9994 // Loop and clear, walking backwards through the array.
9995 // nof_bytes_tmp (if >0) is always the number of bytes to zero
9996 __ bind(loop);
9997 __ deccc(nof_bytes_tmp, 8);
9998 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
9999 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10000 // %%%% this mini-loop must not cross a cache boundary!
10001 %}
10002 ins_pipe(long_memory_op);
10003 %}
10004
10005 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10006 predicate(use_block_zeroing(n->in(2)));
10007 match(Set dummy (ClearArray cnt base));
10008 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10009 ins_cost(300);
10010 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10011
10012 ins_encode %{
10013
10014 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10015 Register to = $base$$Register;
10016 Register count = $cnt$$Register;
10017
10018 Label Ldone;
10019 __ nop(); // Separate short branches
10020 // Use BIS for zeroing (temp is not used).
10021 __ bis_zeroing(to, count, G0, Ldone);
10022 __ bind(Ldone);
10023
10024 %}
10025 ins_pipe(long_memory_op);
10026 %}
10027
10028 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10029 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10030 match(Set dummy (ClearArray cnt base));
10031 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10032 ins_cost(300);
10033 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10034
10035 ins_encode %{
10036
10037 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10038 Register to = $base$$Register;
10039 Register count = $cnt$$Register;
10040 Register temp = $tmp$$Register;
10041
10042 Label Ldone;
10043 __ nop(); // Separate short branches
10044 // Use BIS for zeroing
10045 __ bis_zeroing(to, count, temp, Ldone);
10046 __ bind(Ldone);
10047
10048 %}
10049 ins_pipe(long_memory_op);
10050 %}
10051
10052 instruct string_compareL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10053 o7RegI tmp, flagsReg ccr) %{
10054 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10055 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10056 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10057 ins_cost(300);
10058 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10059 ins_encode %{
10060 __ string_compare($str1$$Register, $str2$$Register,
10061 $cnt1$$Register, $cnt2$$Register,
10062 $tmp$$Register, $tmp$$Register,
10063 $result$$Register, StrIntrinsicNode::LL);
10064 %}
10065 ins_pipe(long_memory_op);
10066 %}
10067
10068 instruct string_compareU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10069 o7RegI tmp, flagsReg ccr) %{
10070 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
10071 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10072 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10073 ins_cost(300);
10074 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10075 ins_encode %{
10076 __ string_compare($str1$$Register, $str2$$Register,
10077 $cnt1$$Register, $cnt2$$Register,
10078 $tmp$$Register, $tmp$$Register,
10079 $result$$Register, StrIntrinsicNode::UU);
10080 %}
10081 ins_pipe(long_memory_op);
10082 %}
10083
10084 instruct string_compareLU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10085 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10086 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10087 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10088 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10089 ins_cost(300);
10090 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %}
10091 ins_encode %{
10092 __ string_compare($str1$$Register, $str2$$Register,
10093 $cnt1$$Register, $cnt2$$Register,
10094 $tmp1$$Register, $tmp2$$Register,
10095 $result$$Register, StrIntrinsicNode::LU);
10096 %}
10097 ins_pipe(long_memory_op);
10098 %}
10099
10100 instruct string_compareUL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10101 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10102 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10103 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10104 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10105 ins_cost(300);
10106 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %}
10107 ins_encode %{
10108 __ string_compare($str2$$Register, $str1$$Register,
10109 $cnt2$$Register, $cnt1$$Register,
10110 $tmp1$$Register, $tmp2$$Register,
10111 $result$$Register, StrIntrinsicNode::UL);
10112 %}
10113 ins_pipe(long_memory_op);
10114 %}
10115
10116 instruct string_equalsL(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10117 o7RegI tmp, flagsReg ccr) %{
10118 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10119 match(Set result (StrEquals (Binary str1 str2) cnt));
10120 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10121 ins_cost(300);
10122 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result // KILL $tmp" %}
10123 ins_encode %{
10124 __ array_equals(false, $str1$$Register, $str2$$Register,
10125 $cnt$$Register, $tmp$$Register,
10126 $result$$Register, true /* byte */);
10127 %}
10128 ins_pipe(long_memory_op);
10129 %}
10130
10131 instruct string_equalsU(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10132 o7RegI tmp, flagsReg ccr) %{
10133 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
10134 match(Set result (StrEquals (Binary str1 str2) cnt));
10135 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10136 ins_cost(300);
10137 format %{ "String Equals char[] $str1,$str2,$cnt -> $result // KILL $tmp" %}
10138 ins_encode %{
10139 __ array_equals(false, $str1$$Register, $str2$$Register,
10140 $cnt$$Register, $tmp$$Register,
10141 $result$$Register, false /* byte */);
10142 %}
10143 ins_pipe(long_memory_op);
10144 %}
10145
10146 instruct array_equalsB(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10147 o7RegI tmp2, flagsReg ccr) %{
10148 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10149 match(Set result (AryEq ary1 ary2));
10150 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10151 ins_cost(300);
10152 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10153 ins_encode %{
10154 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10155 $tmp1$$Register, $tmp2$$Register,
10156 $result$$Register, true /* byte */);
10157 %}
10158 ins_pipe(long_memory_op);
10159 %}
10160
10161 instruct array_equalsC(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10162 o7RegI tmp2, flagsReg ccr) %{
10163 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10164 match(Set result (AryEq ary1 ary2));
10165 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10166 ins_cost(300);
10167 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10168 ins_encode %{
10169 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10170 $tmp1$$Register, $tmp2$$Register,
10171 $result$$Register, false /* byte */);
10172 %}
10173 ins_pipe(long_memory_op);
10174 %}
10175
10176 // char[] to byte[] compression
10177 instruct string_compress(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, iRegL tmp, flagsReg ccr) %{
10178 predicate(UseVIS < 3);
10179 match(Set result (StrCompressedCopy src (Binary dst len)));
10180 effect(TEMP result, TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10181 ins_cost(300);
10182 format %{ "String Compress $src,$dst,$len -> $result // KILL $tmp" %}
10183 ins_encode %{
10184 Label Ldone;
10185 __ signx($len$$Register);
10186 __ cmp_zero_and_br(Assembler::zero, $len$$Register, Ldone, false, Assembler::pn);
10187 __ delayed()->mov($len$$Register, $result$$Register); // copy count
10188 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp$$Register, Ldone);
10189 __ bind(Ldone);
10190 %}
10191 ins_pipe(long_memory_op);
10192 %}
10193
10194 // fast char[] to byte[] compression using VIS instructions
10195 instruct string_compress_fast(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result,
10196 iRegL tmp1, iRegL tmp2, iRegL tmp3, iRegL tmp4,
10197 regD ftmp1, regD ftmp2, regD ftmp3, flagsReg ccr) %{
10198 predicate(UseVIS >= 3);
10199 match(Set result (StrCompressedCopy src (Binary dst len)));
10200 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10201 ins_cost(300);
10202 format %{ "String Compress Fast $src,$dst,$len -> $result // KILL $tmp1,$tmp2,$tmp3,$tmp4,$ftmp1,$ftmp2,$ftmp3" %}
10203 ins_encode %{
10204 Label Ldone;
10205 __ signx($len$$Register);
10206 __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $result$$Register,
10207 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10208 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, Ldone);
10209 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10210 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp1$$Register, Ldone);
10211 __ bind(Ldone);
10212 %}
10213 ins_pipe(long_memory_op);
10214 %}
10215
10216 // byte[] to char[] inflation
10217 instruct string_inflate(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10218 iRegL tmp, flagsReg ccr) %{
10219 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10220 effect(TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10221 ins_cost(300);
10222 format %{ "String Inflate $src,$dst,$len // KILL $tmp" %}
10223 ins_encode %{
10224 Label Ldone;
10225 __ signx($len$$Register);
10226 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10227 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10228 __ bind(Ldone);
10229 %}
10230 ins_pipe(long_memory_op);
10231 %}
10232
10233 // fast byte[] to char[] inflation using VIS instructions
10234 instruct string_inflate_fast(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10235 iRegL tmp, regD ftmp1, regD ftmp2, regD ftmp3, regD ftmp4, flagsReg ccr) %{
10236 predicate(UseVIS >= 3);
10237 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10238 effect(TEMP tmp, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, TEMP ftmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10239 ins_cost(300);
10240 format %{ "String Inflate Fast $src,$dst,$len // KILL $tmp,$ftmp1,$ftmp2,$ftmp3,$ftmp4" %}
10241 ins_encode %{
10242 Label Ldone;
10243 __ signx($len$$Register);
10244 __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register,
10245 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, $ftmp4$$FloatRegister, Ldone);
10246 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10247 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10248 __ bind(Ldone);
10249 %}
10250 ins_pipe(long_memory_op);
10251 %}
10252
10253
10254 //---------- Zeros Count Instructions ------------------------------------------
10255
10256 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10257 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10258 match(Set dst (CountLeadingZerosI src));
10259 effect(TEMP dst, TEMP tmp, KILL cr);
10260
10261 // x |= (x >> 1);
10262 // x |= (x >> 2);
10263 // x |= (x >> 4);
10264 // x |= (x >> 8);
10265 // x |= (x >> 16);
10266 // return (WORDBITS - popc(x));
10267 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10268 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10269 "OR $dst,$tmp,$dst\n\t"
10270 "SRL $dst,2,$tmp\n\t"
10271 "OR $dst,$tmp,$dst\n\t"
10272 "SRL $dst,4,$tmp\n\t"
10273 "OR $dst,$tmp,$dst\n\t"
10274 "SRL $dst,8,$tmp\n\t"
10275 "OR $dst,$tmp,$dst\n\t"
10276 "SRL $dst,16,$tmp\n\t"
10277 "OR $dst,$tmp,$dst\n\t"
10278 "POPC $dst,$dst\n\t"
10279 "MOV 32,$tmp\n\t"
10280 "SUB $tmp,$dst,$dst" %}
10281 ins_encode %{
10282 Register Rdst = $dst$$Register;
10283 Register Rsrc = $src$$Register;
10284 Register Rtmp = $tmp$$Register;
10285 __ srl(Rsrc, 1, Rtmp);
10286 __ srl(Rsrc, 0, Rdst);
10287 __ or3(Rdst, Rtmp, Rdst);
10288 __ srl(Rdst, 2, Rtmp);
10289 __ or3(Rdst, Rtmp, Rdst);
10290 __ srl(Rdst, 4, Rtmp);
10291 __ or3(Rdst, Rtmp, Rdst);
10292 __ srl(Rdst, 8, Rtmp);
10293 __ or3(Rdst, Rtmp, Rdst);
10294 __ srl(Rdst, 16, Rtmp);
10295 __ or3(Rdst, Rtmp, Rdst);
10296 __ popc(Rdst, Rdst);
10297 __ mov(BitsPerInt, Rtmp);
10298 __ sub(Rtmp, Rdst, Rdst);
10299 %}
10300 ins_pipe(ialu_reg);
10301 %}
10302
10303 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10304 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10305 match(Set dst (CountLeadingZerosL src));
10306 effect(TEMP dst, TEMP tmp, KILL cr);
10307
10308 // x |= (x >> 1);
10309 // x |= (x >> 2);
10310 // x |= (x >> 4);
10311 // x |= (x >> 8);
10312 // x |= (x >> 16);
10313 // x |= (x >> 32);
10314 // return (WORDBITS - popc(x));
10315 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10316 "OR $src,$tmp,$dst\n\t"
10317 "SRLX $dst,2,$tmp\n\t"
10318 "OR $dst,$tmp,$dst\n\t"
10319 "SRLX $dst,4,$tmp\n\t"
10320 "OR $dst,$tmp,$dst\n\t"
10321 "SRLX $dst,8,$tmp\n\t"
10322 "OR $dst,$tmp,$dst\n\t"
10323 "SRLX $dst,16,$tmp\n\t"
10324 "OR $dst,$tmp,$dst\n\t"
10325 "SRLX $dst,32,$tmp\n\t"
10326 "OR $dst,$tmp,$dst\n\t"
10327 "POPC $dst,$dst\n\t"
10328 "MOV 64,$tmp\n\t"
10329 "SUB $tmp,$dst,$dst" %}
10330 ins_encode %{
10331 Register Rdst = $dst$$Register;
10332 Register Rsrc = $src$$Register;
10333 Register Rtmp = $tmp$$Register;
10334 __ srlx(Rsrc, 1, Rtmp);
10335 __ or3( Rsrc, Rtmp, Rdst);
10336 __ srlx(Rdst, 2, Rtmp);
10337 __ or3( Rdst, Rtmp, Rdst);
10338 __ srlx(Rdst, 4, Rtmp);
10339 __ or3( Rdst, Rtmp, Rdst);
10340 __ srlx(Rdst, 8, Rtmp);
10341 __ or3( Rdst, Rtmp, Rdst);
10342 __ srlx(Rdst, 16, Rtmp);
10343 __ or3( Rdst, Rtmp, Rdst);
10344 __ srlx(Rdst, 32, Rtmp);
10345 __ or3( Rdst, Rtmp, Rdst);
10346 __ popc(Rdst, Rdst);
10347 __ mov(BitsPerLong, Rtmp);
10348 __ sub(Rtmp, Rdst, Rdst);
10349 %}
10350 ins_pipe(ialu_reg);
10351 %}
10352
10353 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10354 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10355 match(Set dst (CountTrailingZerosI src));
10356 effect(TEMP dst, KILL cr);
10357
10358 // return popc(~x & (x - 1));
10359 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10360 "ANDN $dst,$src,$dst\n\t"
10361 "SRL $dst,R_G0,$dst\n\t"
10362 "POPC $dst,$dst" %}
10363 ins_encode %{
10364 Register Rdst = $dst$$Register;
10365 Register Rsrc = $src$$Register;
10366 __ sub(Rsrc, 1, Rdst);
10367 __ andn(Rdst, Rsrc, Rdst);
10368 __ srl(Rdst, G0, Rdst);
10369 __ popc(Rdst, Rdst);
10370 %}
10371 ins_pipe(ialu_reg);
10372 %}
10373
10374 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10375 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10376 match(Set dst (CountTrailingZerosL src));
10377 effect(TEMP dst, KILL cr);
10378
10379 // return popc(~x & (x - 1));
10380 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10381 "ANDN $dst,$src,$dst\n\t"
10382 "POPC $dst,$dst" %}
10383 ins_encode %{
10384 Register Rdst = $dst$$Register;
10385 Register Rsrc = $src$$Register;
10386 __ sub(Rsrc, 1, Rdst);
10387 __ andn(Rdst, Rsrc, Rdst);
10388 __ popc(Rdst, Rdst);
10389 %}
10390 ins_pipe(ialu_reg);
10391 %}
10392
10393
10394 //---------- Population Count Instructions -------------------------------------
10395
10396 instruct popCountI(iRegIsafe dst, iRegI src) %{
10397 predicate(UsePopCountInstruction);
10398 match(Set dst (PopCountI src));
10399
10400 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10401 "POPC $dst, $dst" %}
10402 ins_encode %{
10403 __ srl($src$$Register, G0, $dst$$Register);
10404 __ popc($dst$$Register, $dst$$Register);
10405 %}
10406 ins_pipe(ialu_reg);
10407 %}
10408
10409 // Note: Long.bitCount(long) returns an int.
10410 instruct popCountL(iRegIsafe dst, iRegL src) %{
10411 predicate(UsePopCountInstruction);
10412 match(Set dst (PopCountL src));
10413
10414 format %{ "POPC $src, $dst" %}
10415 ins_encode %{
10416 __ popc($src$$Register, $dst$$Register);
10417 %}
10418 ins_pipe(ialu_reg);
10419 %}
10420
10421
10422 // ============================================================================
10423 //------------Bytes reverse--------------------------------------------------
10424
10425 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10426 match(Set dst (ReverseBytesI src));
10427
10428 // Op cost is artificially doubled to make sure that load or store
10429 // instructions are preferred over this one which requires a spill
10430 // onto a stack slot.
10431 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10432 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10433
10434 ins_encode %{
10435 __ set($src$$disp + STACK_BIAS, O7);
10436 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10437 %}
10438 ins_pipe( iload_mem );
10439 %}
10440
10441 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10442 match(Set dst (ReverseBytesL src));
10443
10444 // Op cost is artificially doubled to make sure that load or store
10445 // instructions are preferred over this one which requires a spill
10446 // onto a stack slot.
10447 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10448 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10449
10450 ins_encode %{
10451 __ set($src$$disp + STACK_BIAS, O7);
10452 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10453 %}
10454 ins_pipe( iload_mem );
10455 %}
10456
10457 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10458 match(Set dst (ReverseBytesUS src));
10459
10460 // Op cost is artificially doubled to make sure that load or store
10461 // instructions are preferred over this one which requires a spill
10462 // onto a stack slot.
10463 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10464 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10465
10466 ins_encode %{
10467 // the value was spilled as an int so bias the load
10468 __ set($src$$disp + STACK_BIAS + 2, O7);
10469 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10470 %}
10471 ins_pipe( iload_mem );
10472 %}
10473
10474 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10475 match(Set dst (ReverseBytesS src));
10476
10477 // Op cost is artificially doubled to make sure that load or store
10478 // instructions are preferred over this one which requires a spill
10479 // onto a stack slot.
10480 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10481 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10482
10483 ins_encode %{
10484 // the value was spilled as an int so bias the load
10485 __ set($src$$disp + STACK_BIAS + 2, O7);
10486 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10487 %}
10488 ins_pipe( iload_mem );
10489 %}
10490
10491 // Load Integer reversed byte order
10492 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10493 match(Set dst (ReverseBytesI (LoadI src)));
10494
10495 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10496 size(4);
10497 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10498
10499 ins_encode %{
10500 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10501 %}
10502 ins_pipe(iload_mem);
10503 %}
10504
10505 // Load Long - aligned and reversed
10506 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10507 match(Set dst (ReverseBytesL (LoadL src)));
10508
10509 ins_cost(MEMORY_REF_COST);
10510 size(4);
10511 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10512
10513 ins_encode %{
10514 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10515 %}
10516 ins_pipe(iload_mem);
10517 %}
10518
10519 // Load unsigned short / char reversed byte order
10520 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10521 match(Set dst (ReverseBytesUS (LoadUS src)));
10522
10523 ins_cost(MEMORY_REF_COST);
10524 size(4);
10525 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10526
10527 ins_encode %{
10528 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10529 %}
10530 ins_pipe(iload_mem);
10531 %}
10532
10533 // Load short reversed byte order
10534 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10535 match(Set dst (ReverseBytesS (LoadS src)));
10536
10537 ins_cost(MEMORY_REF_COST);
10538 size(4);
10539 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10540
10541 ins_encode %{
10542 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10543 %}
10544 ins_pipe(iload_mem);
10545 %}
10546
10547 // Store Integer reversed byte order
10548 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10549 match(Set dst (StoreI dst (ReverseBytesI src)));
10550
10551 ins_cost(MEMORY_REF_COST);
10552 size(4);
10553 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10554
10555 ins_encode %{
10556 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10557 %}
10558 ins_pipe(istore_mem_reg);
10559 %}
10560
10561 // Store Long reversed byte order
10562 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10563 match(Set dst (StoreL dst (ReverseBytesL src)));
10564
10565 ins_cost(MEMORY_REF_COST);
10566 size(4);
10567 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10568
10569 ins_encode %{
10570 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10571 %}
10572 ins_pipe(istore_mem_reg);
10573 %}
10574
10575 // Store unsighed short/char reversed byte order
10576 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10577 match(Set dst (StoreC dst (ReverseBytesUS src)));
10578
10579 ins_cost(MEMORY_REF_COST);
10580 size(4);
10581 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10582
10583 ins_encode %{
10584 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10585 %}
10586 ins_pipe(istore_mem_reg);
10587 %}
10588
10589 // Store short reversed byte order
10590 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10591 match(Set dst (StoreC dst (ReverseBytesS src)));
10592
10593 ins_cost(MEMORY_REF_COST);
10594 size(4);
10595 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10596
10597 ins_encode %{
10598 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10599 %}
10600 ins_pipe(istore_mem_reg);
10601 %}
10602
10603 // ====================VECTOR INSTRUCTIONS=====================================
10604
10605 // Load Aligned Packed values into a Double Register
10606 instruct loadV8(regD dst, memory mem) %{
10607 predicate(n->as_LoadVector()->memory_size() == 8);
10608 match(Set dst (LoadVector mem));
10609 ins_cost(MEMORY_REF_COST);
10610 size(4);
10611 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10612 ins_encode %{
10613 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10614 %}
10615 ins_pipe(floadD_mem);
10616 %}
10617
10618 // Store Vector in Double register to memory
10619 instruct storeV8(memory mem, regD src) %{
10620 predicate(n->as_StoreVector()->memory_size() == 8);
10621 match(Set mem (StoreVector mem src));
10622 ins_cost(MEMORY_REF_COST);
10623 size(4);
10624 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10625 ins_encode %{
10626 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10627 %}
10628 ins_pipe(fstoreD_mem_reg);
10629 %}
10630
10631 // Store Zero into vector in memory
10632 instruct storeV8B_zero(memory mem, immI0 zero) %{
10633 predicate(n->as_StoreVector()->memory_size() == 8);
10634 match(Set mem (StoreVector mem (ReplicateB zero)));
10635 ins_cost(MEMORY_REF_COST);
10636 size(4);
10637 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10638 ins_encode %{
10639 __ stx(G0, $mem$$Address);
10640 %}
10641 ins_pipe(fstoreD_mem_zero);
10642 %}
10643
10644 instruct storeV4S_zero(memory mem, immI0 zero) %{
10645 predicate(n->as_StoreVector()->memory_size() == 8);
10646 match(Set mem (StoreVector mem (ReplicateS zero)));
10647 ins_cost(MEMORY_REF_COST);
10648 size(4);
10649 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10650 ins_encode %{
10651 __ stx(G0, $mem$$Address);
10652 %}
10653 ins_pipe(fstoreD_mem_zero);
10654 %}
10655
10656 instruct storeV2I_zero(memory mem, immI0 zero) %{
10657 predicate(n->as_StoreVector()->memory_size() == 8);
10658 match(Set mem (StoreVector mem (ReplicateI zero)));
10659 ins_cost(MEMORY_REF_COST);
10660 size(4);
10661 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10662 ins_encode %{
10663 __ stx(G0, $mem$$Address);
10664 %}
10665 ins_pipe(fstoreD_mem_zero);
10666 %}
10667
10668 instruct storeV2F_zero(memory mem, immF0 zero) %{
10669 predicate(n->as_StoreVector()->memory_size() == 8);
10670 match(Set mem (StoreVector mem (ReplicateF zero)));
10671 ins_cost(MEMORY_REF_COST);
10672 size(4);
10673 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10674 ins_encode %{
10675 __ stx(G0, $mem$$Address);
10676 %}
10677 ins_pipe(fstoreD_mem_zero);
10678 %}
10679
10680 // Replicate scalar to packed byte values into Double register
10681 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10682 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10683 match(Set dst (ReplicateB src));
10684 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10685 format %{ "SLLX $src,56,$tmp\n\t"
10686 "SRLX $tmp, 8,$tmp2\n\t"
10687 "OR $tmp,$tmp2,$tmp\n\t"
10688 "SRLX $tmp,16,$tmp2\n\t"
10689 "OR $tmp,$tmp2,$tmp\n\t"
10690 "SRLX $tmp,32,$tmp2\n\t"
10691 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10692 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10693 ins_encode %{
10694 Register Rsrc = $src$$Register;
10695 Register Rtmp = $tmp$$Register;
10696 Register Rtmp2 = $tmp2$$Register;
10697 __ sllx(Rsrc, 56, Rtmp);
10698 __ srlx(Rtmp, 8, Rtmp2);
10699 __ or3 (Rtmp, Rtmp2, Rtmp);
10700 __ srlx(Rtmp, 16, Rtmp2);
10701 __ or3 (Rtmp, Rtmp2, Rtmp);
10702 __ srlx(Rtmp, 32, Rtmp2);
10703 __ or3 (Rtmp, Rtmp2, Rtmp);
10704 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10705 %}
10706 ins_pipe(ialu_reg);
10707 %}
10708
10709 // Replicate scalar to packed byte values into Double stack
10710 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10711 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10712 match(Set dst (ReplicateB src));
10713 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10714 format %{ "SLLX $src,56,$tmp\n\t"
10715 "SRLX $tmp, 8,$tmp2\n\t"
10716 "OR $tmp,$tmp2,$tmp\n\t"
10717 "SRLX $tmp,16,$tmp2\n\t"
10718 "OR $tmp,$tmp2,$tmp\n\t"
10719 "SRLX $tmp,32,$tmp2\n\t"
10720 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10721 "STX $tmp,$dst\t! regL to stkD" %}
10722 ins_encode %{
10723 Register Rsrc = $src$$Register;
10724 Register Rtmp = $tmp$$Register;
10725 Register Rtmp2 = $tmp2$$Register;
10726 __ sllx(Rsrc, 56, Rtmp);
10727 __ srlx(Rtmp, 8, Rtmp2);
10728 __ or3 (Rtmp, Rtmp2, Rtmp);
10729 __ srlx(Rtmp, 16, Rtmp2);
10730 __ or3 (Rtmp, Rtmp2, Rtmp);
10731 __ srlx(Rtmp, 32, Rtmp2);
10732 __ or3 (Rtmp, Rtmp2, Rtmp);
10733 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10734 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10735 %}
10736 ins_pipe(ialu_reg);
10737 %}
10738
10739 // Replicate scalar constant to packed byte values in Double register
10740 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10741 predicate(n->as_Vector()->length() == 8);
10742 match(Set dst (ReplicateB con));
10743 effect(KILL tmp);
10744 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10745 ins_encode %{
10746 // XXX This is a quick fix for 6833573.
10747 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10748 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10749 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10750 %}
10751 ins_pipe(loadConFD);
10752 %}
10753
10754 // Replicate scalar to packed char/short values into Double register
10755 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10756 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10757 match(Set dst (ReplicateS src));
10758 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10759 format %{ "SLLX $src,48,$tmp\n\t"
10760 "SRLX $tmp,16,$tmp2\n\t"
10761 "OR $tmp,$tmp2,$tmp\n\t"
10762 "SRLX $tmp,32,$tmp2\n\t"
10763 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10764 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10765 ins_encode %{
10766 Register Rsrc = $src$$Register;
10767 Register Rtmp = $tmp$$Register;
10768 Register Rtmp2 = $tmp2$$Register;
10769 __ sllx(Rsrc, 48, Rtmp);
10770 __ srlx(Rtmp, 16, Rtmp2);
10771 __ or3 (Rtmp, Rtmp2, Rtmp);
10772 __ srlx(Rtmp, 32, Rtmp2);
10773 __ or3 (Rtmp, Rtmp2, Rtmp);
10774 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10775 %}
10776 ins_pipe(ialu_reg);
10777 %}
10778
10779 // Replicate scalar to packed char/short values into Double stack
10780 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10781 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10782 match(Set dst (ReplicateS src));
10783 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10784 format %{ "SLLX $src,48,$tmp\n\t"
10785 "SRLX $tmp,16,$tmp2\n\t"
10786 "OR $tmp,$tmp2,$tmp\n\t"
10787 "SRLX $tmp,32,$tmp2\n\t"
10788 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10789 "STX $tmp,$dst\t! regL to stkD" %}
10790 ins_encode %{
10791 Register Rsrc = $src$$Register;
10792 Register Rtmp = $tmp$$Register;
10793 Register Rtmp2 = $tmp2$$Register;
10794 __ sllx(Rsrc, 48, Rtmp);
10795 __ srlx(Rtmp, 16, Rtmp2);
10796 __ or3 (Rtmp, Rtmp2, Rtmp);
10797 __ srlx(Rtmp, 32, Rtmp2);
10798 __ or3 (Rtmp, Rtmp2, Rtmp);
10799 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10800 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10801 %}
10802 ins_pipe(ialu_reg);
10803 %}
10804
10805 // Replicate scalar constant to packed char/short values in Double register
10806 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10807 predicate(n->as_Vector()->length() == 4);
10808 match(Set dst (ReplicateS con));
10809 effect(KILL tmp);
10810 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10811 ins_encode %{
10812 // XXX This is a quick fix for 6833573.
10813 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10814 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10815 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10816 %}
10817 ins_pipe(loadConFD);
10818 %}
10819
10820 // Replicate scalar to packed int values into Double register
10821 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10822 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10823 match(Set dst (ReplicateI src));
10824 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10825 format %{ "SLLX $src,32,$tmp\n\t"
10826 "SRLX $tmp,32,$tmp2\n\t"
10827 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10828 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10829 ins_encode %{
10830 Register Rsrc = $src$$Register;
10831 Register Rtmp = $tmp$$Register;
10832 Register Rtmp2 = $tmp2$$Register;
10833 __ sllx(Rsrc, 32, Rtmp);
10834 __ srlx(Rtmp, 32, Rtmp2);
10835 __ or3 (Rtmp, Rtmp2, Rtmp);
10836 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10837 %}
10838 ins_pipe(ialu_reg);
10839 %}
10840
10841 // Replicate scalar to packed int values into Double stack
10842 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10843 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10844 match(Set dst (ReplicateI src));
10845 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10846 format %{ "SLLX $src,32,$tmp\n\t"
10847 "SRLX $tmp,32,$tmp2\n\t"
10848 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10849 "STX $tmp,$dst\t! regL to stkD" %}
10850 ins_encode %{
10851 Register Rsrc = $src$$Register;
10852 Register Rtmp = $tmp$$Register;
10853 Register Rtmp2 = $tmp2$$Register;
10854 __ sllx(Rsrc, 32, Rtmp);
10855 __ srlx(Rtmp, 32, Rtmp2);
10856 __ or3 (Rtmp, Rtmp2, Rtmp);
10857 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10858 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10859 %}
10860 ins_pipe(ialu_reg);
10861 %}
10862
10863 // Replicate scalar zero constant to packed int values in Double register
10864 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10865 predicate(n->as_Vector()->length() == 2);
10866 match(Set dst (ReplicateI con));
10867 effect(KILL tmp);
10868 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10869 ins_encode %{
10870 // XXX This is a quick fix for 6833573.
10871 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10872 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10873 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10874 %}
10875 ins_pipe(loadConFD);
10876 %}
10877
10878 // Replicate scalar to packed float values into Double stack
10879 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10880 predicate(n->as_Vector()->length() == 2);
10881 match(Set dst (ReplicateF src));
10882 ins_cost(MEMORY_REF_COST*2);
10883 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10884 "STF $src,$dst.lo" %}
10885 opcode(Assembler::stf_op3);
10886 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10887 ins_pipe(fstoreF_stk_reg);
10888 %}
10889
10890 // Replicate scalar zero constant to packed float values in Double register
10891 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10892 predicate(n->as_Vector()->length() == 2);
10893 match(Set dst (ReplicateF con));
10894 effect(KILL tmp);
10895 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10896 ins_encode %{
10897 // XXX This is a quick fix for 6833573.
10898 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10899 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10900 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10901 %}
10902 ins_pipe(loadConFD);
10903 %}
10904
10905 //----------PEEPHOLE RULES-----------------------------------------------------
10906 // These must follow all instruction definitions as they use the names
10907 // defined in the instructions definitions.
10908 //
10909 // peepmatch ( root_instr_name [preceding_instruction]* );
10910 //
10911 // peepconstraint %{
10912 // (instruction_number.operand_name relational_op instruction_number.operand_name
10913 // [, ...] );
10914 // // instruction numbers are zero-based using left to right order in peepmatch
10915 //
10916 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10917 // // provide an instruction_number.operand_name for each operand that appears
10918 // // in the replacement instruction's match rule
10919 //
10920 // ---------VM FLAGS---------------------------------------------------------
10921 //
10922 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10923 //
10924 // Each peephole rule is given an identifying number starting with zero and
10925 // increasing by one in the order seen by the parser. An individual peephole
10926 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10927 // on the command-line.
10928 //
10929 // ---------CURRENT LIMITATIONS----------------------------------------------
10930 //
10931 // Only match adjacent instructions in same basic block
10932 // Only equality constraints
10933 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10934 // Only one replacement instruction
10935 //
10936 // ---------EXAMPLE----------------------------------------------------------
10937 //
10938 // // pertinent parts of existing instructions in architecture description
10939 // instruct movI(eRegI dst, eRegI src) %{
10940 // match(Set dst (CopyI src));
10941 // %}
10942 //
10943 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10944 // match(Set dst (AddI dst src));
10945 // effect(KILL cr);
10946 // %}
10947 //
10948 // // Change (inc mov) to lea
10949 // peephole %{
10950 // // increment preceeded by register-register move
10951 // peepmatch ( incI_eReg movI );
10952 // // require that the destination register of the increment
10953 // // match the destination register of the move
10954 // peepconstraint ( 0.dst == 1.dst );
10955 // // construct a replacement instruction that sets
10956 // // the destination to ( move's source register + one )
10957 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10958 // %}
10959 //
10960
10961 // // Change load of spilled value to only a spill
10962 // instruct storeI(memory mem, eRegI src) %{
10963 // match(Set mem (StoreI mem src));
10964 // %}
10965 //
10966 // instruct loadI(eRegI dst, memory mem) %{
10967 // match(Set dst (LoadI mem));
10968 // %}
10969 //
10970 // peephole %{
10971 // peepmatch ( loadI storeI );
10972 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10973 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10974 // %}
10975
10976 //----------SMARTSPILL RULES---------------------------------------------------
10977 // These must follow all instruction definitions as they use the names
10978 // defined in the instructions definitions.
10979 //
10980 // SPARC will probably not have any of these rules due to RISC instruction set.
10981
10982 //----------PIPELINE-----------------------------------------------------------
10983 // Rules which define the behavior of the target architectures pipeline.