1 //
2 // Copyright (c) 1998, 2015, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Header information of the source block.
461 // Method declarations/definitions which are used outside
462 // the ad-scope can conveniently be defined here.
463 //
464 // To keep related declarations/definitions/uses close together,
465 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
466
467 // Must be visible to the DFA in dfa_sparc.cpp
468 extern bool can_branch_register( Node *bol, Node *cmp );
469
470 extern bool use_block_zeroing(Node* count);
471
472 // Macros to extract hi & lo halves from a long pair.
473 // G0 is not part of any long pair, so assert on that.
474 // Prevents accidentally using G1 instead of G0.
475 #define LONG_HI_REG(x) (x)
476 #define LONG_LO_REG(x) (x)
477
478 class CallStubImpl {
479
480 //--------------------------------------------------------------
481 //---< Used for optimization in Compile::Shorten_branches >---
482 //--------------------------------------------------------------
483
484 public:
485 // Size of call trampoline stub.
486 static uint size_call_trampoline() {
487 return 0; // no call trampolines on this platform
488 }
489
490 // number of relocations needed by a call trampoline stub
491 static uint reloc_call_trampoline() {
492 return 0; // no call trampolines on this platform
493 }
494 };
495
496 class HandlerImpl {
497
498 public:
499
500 static int emit_exception_handler(CodeBuffer &cbuf);
501 static int emit_deopt_handler(CodeBuffer& cbuf);
502
503 static uint size_exception_handler() {
504 if (TraceJumps) {
505 return (400); // just a guess
506 }
507 return ( NativeJump::instruction_size ); // sethi;jmp;nop
508 }
509
510 static uint size_deopt_handler() {
511 if (TraceJumps) {
512 return (400); // just a guess
513 }
514 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
515 }
516 };
517
518 %}
519
520 source %{
521 #define __ _masm.
522
523 // tertiary op of a LoadP or StoreP encoding
524 #define REGP_OP true
525
526 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
527 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
528 static Register reg_to_register_object(int register_encoding);
529
530 // Used by the DFA in dfa_sparc.cpp.
531 // Check for being able to use a V9 branch-on-register. Requires a
532 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
533 // extended. Doesn't work following an integer ADD, for example, because of
534 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
535 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
536 // replace them with zero, which could become sign-extension in a different OS
537 // release. There's no obvious reason why an interrupt will ever fill these
538 // bits with non-zero junk (the registers are reloaded with standard LD
539 // instructions which either zero-fill or sign-fill).
540 bool can_branch_register( Node *bol, Node *cmp ) {
541 if( !BranchOnRegister ) return false;
542 #ifdef _LP64
543 if( cmp->Opcode() == Op_CmpP )
544 return true; // No problems with pointer compares
545 #endif
546 if( cmp->Opcode() == Op_CmpL )
547 return true; // No problems with long compares
548
549 if( !SparcV9RegsHiBitsZero ) return false;
550 if( bol->as_Bool()->_test._test != BoolTest::ne &&
551 bol->as_Bool()->_test._test != BoolTest::eq )
552 return false;
553
554 // Check for comparing against a 'safe' value. Any operation which
555 // clears out the high word is safe. Thus, loads and certain shifts
556 // are safe, as are non-negative constants. Any operation which
557 // preserves zero bits in the high word is safe as long as each of its
558 // inputs are safe. Thus, phis and bitwise booleans are safe if their
559 // inputs are safe. At present, the only important case to recognize
560 // seems to be loads. Constants should fold away, and shifts &
561 // logicals can use the 'cc' forms.
562 Node *x = cmp->in(1);
563 if( x->is_Load() ) return true;
564 if( x->is_Phi() ) {
565 for( uint i = 1; i < x->req(); i++ )
566 if( !x->in(i)->is_Load() )
567 return false;
568 return true;
569 }
570 return false;
571 }
572
573 bool use_block_zeroing(Node* count) {
574 // Use BIS for zeroing if count is not constant
575 // or it is >= BlockZeroingLowLimit.
576 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
577 }
578
579 // ****************************************************************************
580
581 // REQUIRED FUNCTIONALITY
582
583 // !!!!! Special hack to get all type of calls to specify the byte offset
584 // from the start of the call to the point where the return address
585 // will point.
586 // The "return address" is the address of the call instruction, plus 8.
587
588 int MachCallStaticJavaNode::ret_addr_offset() {
589 int offset = NativeCall::instruction_size; // call; delay slot
590 if (_method_handle_invoke)
591 offset += 4; // restore SP
592 return offset;
593 }
594
595 int MachCallDynamicJavaNode::ret_addr_offset() {
596 int vtable_index = this->_vtable_index;
597 if (vtable_index < 0) {
598 // must be invalid_vtable_index, not nonvirtual_vtable_index
599 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
600 return (NativeMovConstReg::instruction_size +
601 NativeCall::instruction_size); // sethi; setlo; call; delay slot
602 } else {
603 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
604 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
605 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
606 int klass_load_size;
607 if (UseCompressedClassPointers) {
608 assert(Universe::heap() != NULL, "java heap should be initialized");
609 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
610 } else {
611 klass_load_size = 1*BytesPerInstWord;
612 }
613 if (Assembler::is_simm13(v_off)) {
614 return klass_load_size +
615 (2*BytesPerInstWord + // ld_ptr, ld_ptr
616 NativeCall::instruction_size); // call; delay slot
617 } else {
618 return klass_load_size +
619 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
620 NativeCall::instruction_size); // call; delay slot
621 }
622 }
623 }
624
625 int MachCallRuntimeNode::ret_addr_offset() {
626 #ifdef _LP64
627 if (MacroAssembler::is_far_target(entry_point())) {
628 return NativeFarCall::instruction_size;
629 } else {
630 return NativeCall::instruction_size;
631 }
632 #else
633 return NativeCall::instruction_size; // call; delay slot
634 #endif
635 }
636
637 // Indicate if the safepoint node needs the polling page as an input.
638 // Since Sparc does not have absolute addressing, it does.
639 bool SafePointNode::needs_polling_address_input() {
640 return true;
641 }
642
643 // emit an interrupt that is caught by the debugger (for debugging compiler)
644 void emit_break(CodeBuffer &cbuf) {
645 MacroAssembler _masm(&cbuf);
646 __ breakpoint_trap();
647 }
648
649 #ifndef PRODUCT
650 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
651 st->print("TA");
652 }
653 #endif
654
655 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
656 emit_break(cbuf);
657 }
658
659 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
660 return MachNode::size(ra_);
661 }
662
663 // Traceable jump
664 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
665 MacroAssembler _masm(&cbuf);
666 Register rdest = reg_to_register_object(jump_target);
667 __ JMP(rdest, 0);
668 __ delayed()->nop();
669 }
670
671 // Traceable jump and set exception pc
672 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
673 MacroAssembler _masm(&cbuf);
674 Register rdest = reg_to_register_object(jump_target);
675 __ JMP(rdest, 0);
676 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
677 }
678
679 void emit_nop(CodeBuffer &cbuf) {
680 MacroAssembler _masm(&cbuf);
681 __ nop();
682 }
683
684 void emit_illtrap(CodeBuffer &cbuf) {
685 MacroAssembler _masm(&cbuf);
686 __ illtrap(0);
687 }
688
689
690 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
691 assert(n->rule() != loadUB_rule, "");
692
693 intptr_t offset = 0;
694 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
695 const Node* addr = n->get_base_and_disp(offset, adr_type);
696 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
697 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
698 assert(addr->bottom_type()->isa_oopptr() == atype, "");
699 atype = atype->add_offset(offset);
700 assert(disp32 == offset, "wrong disp32");
701 return atype->_offset;
702 }
703
704
705 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
706 assert(n->rule() != loadUB_rule, "");
707
708 intptr_t offset = 0;
709 Node* addr = n->in(2);
710 assert(addr->bottom_type()->isa_oopptr() == atype, "");
711 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
712 Node* a = addr->in(2/*AddPNode::Address*/);
713 Node* o = addr->in(3/*AddPNode::Offset*/);
714 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
715 atype = a->bottom_type()->is_ptr()->add_offset(offset);
716 assert(atype->isa_oop_ptr(), "still an oop");
717 }
718 offset = atype->is_ptr()->_offset;
719 if (offset != Type::OffsetBot) offset += disp32;
720 return offset;
721 }
722
723 static inline jdouble replicate_immI(int con, int count, int width) {
724 // Load a constant replicated "count" times with width "width"
725 assert(count*width == 8 && width <= 4, "sanity");
726 int bit_width = width * 8;
727 jlong val = con;
728 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
729 for (int i = 0; i < count - 1; i++) {
730 val |= (val << bit_width);
731 }
732 jdouble dval = *((jdouble*) &val); // coerce to double type
733 return dval;
734 }
735
736 static inline jdouble replicate_immF(float con) {
737 // Replicate float con 2 times and pack into vector.
738 int val = *((int*)&con);
739 jlong lval = val;
740 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
741 jdouble dval = *((jdouble*) &lval); // coerce to double type
742 return dval;
743 }
744
745 // Standard Sparc opcode form2 field breakdown
746 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
747 f0 &= (1<<19)-1; // Mask displacement to 19 bits
748 int op = (f30 << 30) |
749 (f29 << 29) |
750 (f25 << 25) |
751 (f22 << 22) |
752 (f20 << 20) |
753 (f19 << 19) |
754 (f0 << 0);
755 cbuf.insts()->emit_int32(op);
756 }
757
758 // Standard Sparc opcode form2 field breakdown
759 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
760 f0 >>= 10; // Drop 10 bits
761 f0 &= (1<<22)-1; // Mask displacement to 22 bits
762 int op = (f30 << 30) |
763 (f25 << 25) |
764 (f22 << 22) |
765 (f0 << 0);
766 cbuf.insts()->emit_int32(op);
767 }
768
769 // Standard Sparc opcode form3 field breakdown
770 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
771 int op = (f30 << 30) |
772 (f25 << 25) |
773 (f19 << 19) |
774 (f14 << 14) |
775 (f5 << 5) |
776 (f0 << 0);
777 cbuf.insts()->emit_int32(op);
778 }
779
780 // Standard Sparc opcode form3 field breakdown
781 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
782 simm13 &= (1<<13)-1; // Mask to 13 bits
783 int op = (f30 << 30) |
784 (f25 << 25) |
785 (f19 << 19) |
786 (f14 << 14) |
787 (1 << 13) | // bit to indicate immediate-mode
788 (simm13<<0);
789 cbuf.insts()->emit_int32(op);
790 }
791
792 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
793 simm10 &= (1<<10)-1; // Mask to 10 bits
794 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
795 }
796
797 #ifdef ASSERT
798 // Helper function for VerifyOops in emit_form3_mem_reg
799 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
800 warning("VerifyOops encountered unexpected instruction:");
801 n->dump(2);
802 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
803 }
804 #endif
805
806
807 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
808 int src1_enc, int disp32, int src2_enc, int dst_enc) {
809
810 #ifdef ASSERT
811 // The following code implements the +VerifyOops feature.
812 // It verifies oop values which are loaded into or stored out of
813 // the current method activation. +VerifyOops complements techniques
814 // like ScavengeALot, because it eagerly inspects oops in transit,
815 // as they enter or leave the stack, as opposed to ScavengeALot,
816 // which inspects oops "at rest", in the stack or heap, at safepoints.
817 // For this reason, +VerifyOops can sometimes detect bugs very close
818 // to their point of creation. It can also serve as a cross-check
819 // on the validity of oop maps, when used toegether with ScavengeALot.
820
821 // It would be good to verify oops at other points, especially
822 // when an oop is used as a base pointer for a load or store.
823 // This is presently difficult, because it is hard to know when
824 // a base address is biased or not. (If we had such information,
825 // it would be easy and useful to make a two-argument version of
826 // verify_oop which unbiases the base, and performs verification.)
827
828 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
829 bool is_verified_oop_base = false;
830 bool is_verified_oop_load = false;
831 bool is_verified_oop_store = false;
832 int tmp_enc = -1;
833 if (VerifyOops && src1_enc != R_SP_enc) {
834 // classify the op, mainly for an assert check
835 int st_op = 0, ld_op = 0;
836 switch (primary) {
837 case Assembler::stb_op3: st_op = Op_StoreB; break;
838 case Assembler::sth_op3: st_op = Op_StoreC; break;
839 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
840 case Assembler::stw_op3: st_op = Op_StoreI; break;
841 case Assembler::std_op3: st_op = Op_StoreL; break;
842 case Assembler::stf_op3: st_op = Op_StoreF; break;
843 case Assembler::stdf_op3: st_op = Op_StoreD; break;
844
845 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
846 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
847 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
848 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
849 case Assembler::ldx_op3: // may become LoadP or stay LoadI
850 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
851 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
852 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
853 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
854 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
855 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
856
857 default: ShouldNotReachHere();
858 }
859 if (tertiary == REGP_OP) {
860 if (st_op == Op_StoreI) st_op = Op_StoreP;
861 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
862 else ShouldNotReachHere();
863 if (st_op) {
864 // a store
865 // inputs are (0:control, 1:memory, 2:address, 3:value)
866 Node* n2 = n->in(3);
867 if (n2 != NULL) {
868 const Type* t = n2->bottom_type();
869 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
870 }
871 } else {
872 // a load
873 const Type* t = n->bottom_type();
874 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
875 }
876 }
877
878 if (ld_op) {
879 // a Load
880 // inputs are (0:control, 1:memory, 2:address)
881 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
882 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
883 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
884 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
885 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
886 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
887 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
888 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
889 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
890 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
891 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
892 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
893 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
894 !(n->rule() == loadUB_rule)) {
895 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
896 }
897 } else if (st_op) {
898 // a Store
899 // inputs are (0:control, 1:memory, 2:address, 3:value)
900 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
901 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
902 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
903 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
904 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
905 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
906 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
907 verify_oops_warning(n, n->ideal_Opcode(), st_op);
908 }
909 }
910
911 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
912 Node* addr = n->in(2);
913 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
914 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
915 if (atype != NULL) {
916 intptr_t offset = get_offset_from_base(n, atype, disp32);
917 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
918 if (offset != offset_2) {
919 get_offset_from_base(n, atype, disp32);
920 get_offset_from_base_2(n, atype, disp32);
921 }
922 assert(offset == offset_2, "different offsets");
923 if (offset == disp32) {
924 // we now know that src1 is a true oop pointer
925 is_verified_oop_base = true;
926 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
927 if( primary == Assembler::ldd_op3 ) {
928 is_verified_oop_base = false; // Cannot 'ldd' into O7
929 } else {
930 tmp_enc = dst_enc;
931 dst_enc = R_O7_enc; // Load into O7; preserve source oop
932 assert(src1_enc != dst_enc, "");
933 }
934 }
935 }
936 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
937 || offset == oopDesc::mark_offset_in_bytes())) {
938 // loading the mark should not be allowed either, but
939 // we don't check this since it conflicts with InlineObjectHash
940 // usage of LoadINode to get the mark. We could keep the
941 // check if we create a new LoadMarkNode
942 // but do not verify the object before its header is initialized
943 ShouldNotReachHere();
944 }
945 }
946 }
947 }
948 }
949 #endif
950
951 uint instr;
952 instr = (Assembler::ldst_op << 30)
953 | (dst_enc << 25)
954 | (primary << 19)
955 | (src1_enc << 14);
956
957 uint index = src2_enc;
958 int disp = disp32;
959
960 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
961 disp += STACK_BIAS;
962 // Quick fix for JDK-8029668: check that stack offset fits, bailout if not
963 if (!Assembler::is_simm13(disp)) {
964 ra->C->record_method_not_compilable("unable to handle large constant offsets");
965 return;
966 }
967 }
968
969 // We should have a compiler bailout here rather than a guarantee.
970 // Better yet would be some mechanism to handle variable-size matches correctly.
971 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
972
973 if( disp == 0 ) {
974 // use reg-reg form
975 // bit 13 is already zero
976 instr |= index;
977 } else {
978 // use reg-imm form
979 instr |= 0x00002000; // set bit 13 to one
980 instr |= disp & 0x1FFF;
981 }
982
983 cbuf.insts()->emit_int32(instr);
984
985 #ifdef ASSERT
986 {
987 MacroAssembler _masm(&cbuf);
988 if (is_verified_oop_base) {
989 __ verify_oop(reg_to_register_object(src1_enc));
990 }
991 if (is_verified_oop_store) {
992 __ verify_oop(reg_to_register_object(dst_enc));
993 }
994 if (tmp_enc != -1) {
995 __ mov(O7, reg_to_register_object(tmp_enc));
996 }
997 if (is_verified_oop_load) {
998 __ verify_oop(reg_to_register_object(dst_enc));
999 }
1000 }
1001 #endif
1002 }
1003
1004 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
1005 // The method which records debug information at every safepoint
1006 // expects the call to be the first instruction in the snippet as
1007 // it creates a PcDesc structure which tracks the offset of a call
1008 // from the start of the codeBlob. This offset is computed as
1009 // code_end() - code_begin() of the code which has been emitted
1010 // so far.
1011 // In this particular case we have skirted around the problem by
1012 // putting the "mov" instruction in the delay slot but the problem
1013 // may bite us again at some other point and a cleaner/generic
1014 // solution using relocations would be needed.
1015 MacroAssembler _masm(&cbuf);
1016 __ set_inst_mark();
1017
1018 // We flush the current window just so that there is a valid stack copy
1019 // the fact that the current window becomes active again instantly is
1020 // not a problem there is nothing live in it.
1021
1022 #ifdef ASSERT
1023 int startpos = __ offset();
1024 #endif /* ASSERT */
1025
1026 __ call((address)entry_point, rtype);
1027
1028 if (preserve_g2) __ delayed()->mov(G2, L7);
1029 else __ delayed()->nop();
1030
1031 if (preserve_g2) __ mov(L7, G2);
1032
1033 #ifdef ASSERT
1034 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
1035 #ifdef _LP64
1036 // Trash argument dump slots.
1037 __ set(0xb0b8ac0db0b8ac0d, G1);
1038 __ mov(G1, G5);
1039 __ stx(G1, SP, STACK_BIAS + 0x80);
1040 __ stx(G1, SP, STACK_BIAS + 0x88);
1041 __ stx(G1, SP, STACK_BIAS + 0x90);
1042 __ stx(G1, SP, STACK_BIAS + 0x98);
1043 __ stx(G1, SP, STACK_BIAS + 0xA0);
1044 __ stx(G1, SP, STACK_BIAS + 0xA8);
1045 #else // _LP64
1046 // this is also a native call, so smash the first 7 stack locations,
1047 // and the various registers
1048
1049 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1050 // while [SP+0x44..0x58] are the argument dump slots.
1051 __ set((intptr_t)0xbaadf00d, G1);
1052 __ mov(G1, G5);
1053 __ sllx(G1, 32, G1);
1054 __ or3(G1, G5, G1);
1055 __ mov(G1, G5);
1056 __ stx(G1, SP, 0x40);
1057 __ stx(G1, SP, 0x48);
1058 __ stx(G1, SP, 0x50);
1059 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1060 #endif // _LP64
1061 }
1062 #endif /*ASSERT*/
1063 }
1064
1065 //=============================================================================
1066 // REQUIRED FUNCTIONALITY for encoding
1067 void emit_lo(CodeBuffer &cbuf, int val) { }
1068 void emit_hi(CodeBuffer &cbuf, int val) { }
1069
1070
1071 //=============================================================================
1072 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1073
1074 int Compile::ConstantTable::calculate_table_base_offset() const {
1075 if (UseRDPCForConstantTableBase) {
1076 // The table base offset might be less but then it fits into
1077 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1078 return Assembler::min_simm13();
1079 } else {
1080 int offset = -(size() / 2);
1081 if (!Assembler::is_simm13(offset)) {
1082 offset = Assembler::min_simm13();
1083 }
1084 return offset;
1085 }
1086 }
1087
1088 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1089 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1090 ShouldNotReachHere();
1091 }
1092
1093 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1094 Compile* C = ra_->C;
1095 Compile::ConstantTable& constant_table = C->constant_table();
1096 MacroAssembler _masm(&cbuf);
1097
1098 Register r = as_Register(ra_->get_encode(this));
1099 CodeSection* consts_section = __ code()->consts();
1100 int consts_size = consts_section->align_at_start(consts_section->size());
1101 assert(constant_table.size() == consts_size, "must be: %d == %d", constant_table.size(), consts_size);
1102
1103 if (UseRDPCForConstantTableBase) {
1104 // For the following RDPC logic to work correctly the consts
1105 // section must be allocated right before the insts section. This
1106 // assert checks for that. The layout and the SECT_* constants
1107 // are defined in src/share/vm/asm/codeBuffer.hpp.
1108 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1109 int insts_offset = __ offset();
1110
1111 // Layout:
1112 //
1113 // |----------- consts section ------------|----------- insts section -----------...
1114 // |------ constant table -----|- padding -|------------------x----
1115 // \ current PC (RDPC instruction)
1116 // |<------------- consts_size ----------->|<- insts_offset ->|
1117 // \ table base
1118 // The table base offset is later added to the load displacement
1119 // so it has to be negative.
1120 int table_base_offset = -(consts_size + insts_offset);
1121 int disp;
1122
1123 // If the displacement from the current PC to the constant table
1124 // base fits into simm13 we set the constant table base to the
1125 // current PC.
1126 if (Assembler::is_simm13(table_base_offset)) {
1127 constant_table.set_table_base_offset(table_base_offset);
1128 disp = 0;
1129 } else {
1130 // Otherwise we set the constant table base offset to the
1131 // maximum negative displacement of load instructions to keep
1132 // the disp as small as possible:
1133 //
1134 // |<------------- consts_size ----------->|<- insts_offset ->|
1135 // |<--------- min_simm13 --------->|<-------- disp --------->|
1136 // \ table base
1137 table_base_offset = Assembler::min_simm13();
1138 constant_table.set_table_base_offset(table_base_offset);
1139 disp = (consts_size + insts_offset) + table_base_offset;
1140 }
1141
1142 __ rdpc(r);
1143
1144 if (disp != 0) {
1145 assert(r != O7, "need temporary");
1146 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1147 }
1148 }
1149 else {
1150 // Materialize the constant table base.
1151 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1152 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1153 AddressLiteral base(baseaddr, rspec);
1154 __ set(base, r);
1155 }
1156 }
1157
1158 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1159 if (UseRDPCForConstantTableBase) {
1160 // This is really the worst case but generally it's only 1 instruction.
1161 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1162 } else {
1163 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1164 }
1165 }
1166
1167 #ifndef PRODUCT
1168 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1169 char reg[128];
1170 ra_->dump_register(this, reg);
1171 if (UseRDPCForConstantTableBase) {
1172 st->print("RDPC %s\t! constant table base", reg);
1173 } else {
1174 st->print("SET &constanttable,%s\t! constant table base", reg);
1175 }
1176 }
1177 #endif
1178
1179
1180 //=============================================================================
1181
1182 #ifndef PRODUCT
1183 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1184 Compile* C = ra_->C;
1185
1186 for (int i = 0; i < OptoPrologueNops; i++) {
1187 st->print_cr("NOP"); st->print("\t");
1188 }
1189
1190 if( VerifyThread ) {
1191 st->print_cr("Verify_Thread"); st->print("\t");
1192 }
1193
1194 size_t framesize = C->frame_size_in_bytes();
1195 int bangsize = C->bang_size_in_bytes();
1196
1197 // Calls to C2R adapters often do not accept exceptional returns.
1198 // We require that their callers must bang for them. But be careful, because
1199 // some VM calls (such as call site linkage) can use several kilobytes of
1200 // stack. But the stack safety zone should account for that.
1201 // See bugs 4446381, 4468289, 4497237.
1202 if (C->need_stack_bang(bangsize)) {
1203 st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t");
1204 }
1205
1206 if (Assembler::is_simm13(-framesize)) {
1207 st->print ("SAVE R_SP,-" SIZE_FORMAT ",R_SP",framesize);
1208 } else {
1209 st->print_cr("SETHI R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1210 st->print_cr("ADD R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1211 st->print ("SAVE R_SP,R_G3,R_SP");
1212 }
1213
1214 }
1215 #endif
1216
1217 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1218 Compile* C = ra_->C;
1219 MacroAssembler _masm(&cbuf);
1220
1221 for (int i = 0; i < OptoPrologueNops; i++) {
1222 __ nop();
1223 }
1224
1225 __ verify_thread();
1226
1227 size_t framesize = C->frame_size_in_bytes();
1228 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1229 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1230 int bangsize = C->bang_size_in_bytes();
1231
1232 // Calls to C2R adapters often do not accept exceptional returns.
1233 // We require that their callers must bang for them. But be careful, because
1234 // some VM calls (such as call site linkage) can use several kilobytes of
1235 // stack. But the stack safety zone should account for that.
1236 // See bugs 4446381, 4468289, 4497237.
1237 if (C->need_stack_bang(bangsize)) {
1238 __ generate_stack_overflow_check(bangsize);
1239 }
1240
1241 if (Assembler::is_simm13(-framesize)) {
1242 __ save(SP, -framesize, SP);
1243 } else {
1244 __ sethi(-framesize & ~0x3ff, G3);
1245 __ add(G3, -framesize & 0x3ff, G3);
1246 __ save(SP, G3, SP);
1247 }
1248 C->set_frame_complete( __ offset() );
1249
1250 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1251 // NOTE: We set the table base offset here because users might be
1252 // emitted before MachConstantBaseNode.
1253 Compile::ConstantTable& constant_table = C->constant_table();
1254 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1255 }
1256 }
1257
1258 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1259 return MachNode::size(ra_);
1260 }
1261
1262 int MachPrologNode::reloc() const {
1263 return 10; // a large enough number
1264 }
1265
1266 //=============================================================================
1267 #ifndef PRODUCT
1268 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1269 Compile* C = ra_->C;
1270
1271 if(do_polling() && ra_->C->is_method_compilation()) {
1272 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1273 #ifdef _LP64
1274 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1275 #else
1276 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1277 #endif
1278 }
1279
1280 if(do_polling()) {
1281 if (UseCBCond && !ra_->C->is_method_compilation()) {
1282 st->print("NOP\n\t");
1283 }
1284 st->print("RET\n\t");
1285 }
1286
1287 st->print("RESTORE");
1288 }
1289 #endif
1290
1291 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1292 MacroAssembler _masm(&cbuf);
1293 Compile* C = ra_->C;
1294
1295 __ verify_thread();
1296
1297 // If this does safepoint polling, then do it here
1298 if(do_polling() && ra_->C->is_method_compilation()) {
1299 AddressLiteral polling_page(os::get_polling_page());
1300 __ sethi(polling_page, L0);
1301 __ relocate(relocInfo::poll_return_type);
1302 __ ld_ptr(L0, 0, G0);
1303 }
1304
1305 // If this is a return, then stuff the restore in the delay slot
1306 if(do_polling()) {
1307 if (UseCBCond && !ra_->C->is_method_compilation()) {
1308 // Insert extra padding for the case when the epilogue is preceded by
1309 // a cbcond jump, which can't be followed by a CTI instruction
1310 __ nop();
1311 }
1312 __ ret();
1313 __ delayed()->restore();
1314 } else {
1315 __ restore();
1316 }
1317 }
1318
1319 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1320 return MachNode::size(ra_);
1321 }
1322
1323 int MachEpilogNode::reloc() const {
1324 return 16; // a large enough number
1325 }
1326
1327 const Pipeline * MachEpilogNode::pipeline() const {
1328 return MachNode::pipeline_class();
1329 }
1330
1331 int MachEpilogNode::safepoint_offset() const {
1332 assert( do_polling(), "no return for this epilog node");
1333 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1334 }
1335
1336 //=============================================================================
1337
1338 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1339 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1340 static enum RC rc_class( OptoReg::Name reg ) {
1341 if( !OptoReg::is_valid(reg) ) return rc_bad;
1342 if (OptoReg::is_stack(reg)) return rc_stack;
1343 VMReg r = OptoReg::as_VMReg(reg);
1344 if (r->is_Register()) return rc_int;
1345 assert(r->is_FloatRegister(), "must be");
1346 return rc_float;
1347 }
1348
1349 static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1350 if (cbuf) {
1351 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1352 }
1353 #ifndef PRODUCT
1354 else if (!do_size) {
1355 if (size != 0) st->print("\n\t");
1356 if (is_load) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1357 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1358 }
1359 #endif
1360 return size+4;
1361 }
1362
1363 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1364 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1365 #ifndef PRODUCT
1366 else if( !do_size ) {
1367 if( size != 0 ) st->print("\n\t");
1368 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1369 }
1370 #endif
1371 return size+4;
1372 }
1373
1374 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1375 PhaseRegAlloc *ra_,
1376 bool do_size,
1377 outputStream* st ) const {
1378 // Get registers to move
1379 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1380 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1381 OptoReg::Name dst_second = ra_->get_reg_second(this );
1382 OptoReg::Name dst_first = ra_->get_reg_first(this );
1383
1384 enum RC src_second_rc = rc_class(src_second);
1385 enum RC src_first_rc = rc_class(src_first);
1386 enum RC dst_second_rc = rc_class(dst_second);
1387 enum RC dst_first_rc = rc_class(dst_first);
1388
1389 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1390
1391 // Generate spill code!
1392 int size = 0;
1393
1394 if( src_first == dst_first && src_second == dst_second )
1395 return size; // Self copy, no move
1396
1397 // --------------------------------------
1398 // Check for mem-mem move. Load into unused float registers and fall into
1399 // the float-store case.
1400 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1401 int offset = ra_->reg2offset(src_first);
1402 // Further check for aligned-adjacent pair, so we can use a double load
1403 if( (src_first&1)==0 && src_first+1 == src_second ) {
1404 src_second = OptoReg::Name(R_F31_num);
1405 src_second_rc = rc_float;
1406 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1407 } else {
1408 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1409 }
1410 src_first = OptoReg::Name(R_F30_num);
1411 src_first_rc = rc_float;
1412 }
1413
1414 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1415 int offset = ra_->reg2offset(src_second);
1416 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1417 src_second = OptoReg::Name(R_F31_num);
1418 src_second_rc = rc_float;
1419 }
1420
1421 // --------------------------------------
1422 // Check for float->int copy; requires a trip through memory
1423 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1424 int offset = frame::register_save_words*wordSize;
1425 if (cbuf) {
1426 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1427 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1428 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1429 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1430 }
1431 #ifndef PRODUCT
1432 else if (!do_size) {
1433 if (size != 0) st->print("\n\t");
1434 st->print( "SUB R_SP,16,R_SP\n");
1435 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1436 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1437 st->print("\tADD R_SP,16,R_SP\n");
1438 }
1439 #endif
1440 size += 16;
1441 }
1442
1443 // Check for float->int copy on T4
1444 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1445 // Further check for aligned-adjacent pair, so we can use a double move
1446 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1447 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1448 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1449 }
1450 // Check for int->float copy on T4
1451 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1452 // Further check for aligned-adjacent pair, so we can use a double move
1453 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1454 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1455 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1456 }
1457
1458 // --------------------------------------
1459 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1460 // In such cases, I have to do the big-endian swap. For aligned targets, the
1461 // hardware does the flop for me. Doubles are always aligned, so no problem
1462 // there. Misaligned sources only come from native-long-returns (handled
1463 // special below).
1464 #ifndef _LP64
1465 if( src_first_rc == rc_int && // source is already big-endian
1466 src_second_rc != rc_bad && // 64-bit move
1467 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1468 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1469 // Do the big-endian flop.
1470 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1471 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1472 }
1473 #endif
1474
1475 // --------------------------------------
1476 // Check for integer reg-reg copy
1477 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1478 #ifndef _LP64
1479 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1480 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1481 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1482 // operand contains the least significant word of the 64-bit value and vice versa.
1483 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1484 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1485 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1486 if( cbuf ) {
1487 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1488 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1489 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1490 #ifndef PRODUCT
1491 } else if( !do_size ) {
1492 if( size != 0 ) st->print("\n\t");
1493 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1494 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1495 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1496 #endif
1497 }
1498 return size+12;
1499 }
1500 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1501 // returning a long value in I0/I1
1502 // a SpillCopy must be able to target a return instruction's reg_class
1503 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1504 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1505 // operand contains the least significant word of the 64-bit value and vice versa.
1506 OptoReg::Name tdest = dst_first;
1507
1508 if (src_first == dst_first) {
1509 tdest = OptoReg::Name(R_O7_num);
1510 size += 4;
1511 }
1512
1513 if( cbuf ) {
1514 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1515 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1516 // ShrL_reg_imm6
1517 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1518 // ShrR_reg_imm6 src, 0, dst
1519 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1520 if (tdest != dst_first) {
1521 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1522 }
1523 }
1524 #ifndef PRODUCT
1525 else if( !do_size ) {
1526 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1527 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1528 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1529 if (tdest != dst_first) {
1530 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1531 }
1532 }
1533 #endif // PRODUCT
1534 return size+8;
1535 }
1536 #endif // !_LP64
1537 // Else normal reg-reg copy
1538 assert( src_second != dst_first, "smashed second before evacuating it" );
1539 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1540 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1541 // This moves an aligned adjacent pair.
1542 // See if we are done.
1543 if( src_first+1 == src_second && dst_first+1 == dst_second )
1544 return size;
1545 }
1546
1547 // Check for integer store
1548 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1549 int offset = ra_->reg2offset(dst_first);
1550 // Further check for aligned-adjacent pair, so we can use a double store
1551 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1552 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1553 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1554 }
1555
1556 // Check for integer load
1557 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1558 int offset = ra_->reg2offset(src_first);
1559 // Further check for aligned-adjacent pair, so we can use a double load
1560 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1561 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1562 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1563 }
1564
1565 // Check for float reg-reg copy
1566 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1567 // Further check for aligned-adjacent pair, so we can use a double move
1568 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1569 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1570 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1571 }
1572
1573 // Check for float store
1574 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1575 int offset = ra_->reg2offset(dst_first);
1576 // Further check for aligned-adjacent pair, so we can use a double store
1577 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1578 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1579 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1580 }
1581
1582 // Check for float load
1583 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1584 int offset = ra_->reg2offset(src_first);
1585 // Further check for aligned-adjacent pair, so we can use a double load
1586 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1587 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1588 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1589 }
1590
1591 // --------------------------------------------------------------------
1592 // Check for hi bits still needing moving. Only happens for misaligned
1593 // arguments to native calls.
1594 if( src_second == dst_second )
1595 return size; // Self copy; no move
1596 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1597
1598 #ifndef _LP64
1599 // In the LP64 build, all registers can be moved as aligned/adjacent
1600 // pairs, so there's never any need to move the high bits separately.
1601 // The 32-bit builds have to deal with the 32-bit ABI which can force
1602 // all sorts of silly alignment problems.
1603
1604 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1605 // 32-bits of a 64-bit register, but are needed in low bits of another
1606 // register (else it's a hi-bits-to-hi-bits copy which should have
1607 // happened already as part of a 64-bit move)
1608 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1609 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1610 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1611 // Shift src_second down to dst_second's low bits.
1612 if( cbuf ) {
1613 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1614 #ifndef PRODUCT
1615 } else if( !do_size ) {
1616 if( size != 0 ) st->print("\n\t");
1617 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1618 #endif
1619 }
1620 return size+4;
1621 }
1622
1623 // Check for high word integer store. Must down-shift the hi bits
1624 // into a temp register, then fall into the case of storing int bits.
1625 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1626 // Shift src_second down to dst_second's low bits.
1627 if( cbuf ) {
1628 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1629 #ifndef PRODUCT
1630 } else if( !do_size ) {
1631 if( size != 0 ) st->print("\n\t");
1632 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1633 #endif
1634 }
1635 size+=4;
1636 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1637 }
1638
1639 // Check for high word integer load
1640 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1641 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1642
1643 // Check for high word integer store
1644 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1645 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1646
1647 // Check for high word float store
1648 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1649 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1650
1651 #endif // !_LP64
1652
1653 Unimplemented();
1654 }
1655
1656 #ifndef PRODUCT
1657 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1658 implementation( NULL, ra_, false, st );
1659 }
1660 #endif
1661
1662 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1663 implementation( &cbuf, ra_, false, NULL );
1664 }
1665
1666 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1667 return implementation( NULL, ra_, true, NULL );
1668 }
1669
1670 //=============================================================================
1671 #ifndef PRODUCT
1672 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1673 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1674 }
1675 #endif
1676
1677 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1678 MacroAssembler _masm(&cbuf);
1679 for(int i = 0; i < _count; i += 1) {
1680 __ nop();
1681 }
1682 }
1683
1684 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1685 return 4 * _count;
1686 }
1687
1688
1689 //=============================================================================
1690 #ifndef PRODUCT
1691 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1692 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1693 int reg = ra_->get_reg_first(this);
1694 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1695 }
1696 #endif
1697
1698 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1699 MacroAssembler _masm(&cbuf);
1700 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1701 int reg = ra_->get_encode(this);
1702
1703 if (Assembler::is_simm13(offset)) {
1704 __ add(SP, offset, reg_to_register_object(reg));
1705 } else {
1706 __ set(offset, O7);
1707 __ add(SP, O7, reg_to_register_object(reg));
1708 }
1709 }
1710
1711 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1712 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1713 assert(ra_ == ra_->C->regalloc(), "sanity");
1714 return ra_->C->scratch_emit_size(this);
1715 }
1716
1717 //=============================================================================
1718 #ifndef PRODUCT
1719 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1720 st->print_cr("\nUEP:");
1721 #ifdef _LP64
1722 if (UseCompressedClassPointers) {
1723 assert(Universe::heap() != NULL, "java heap should be initialized");
1724 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1725 if (Universe::narrow_klass_base() != 0) {
1726 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base");
1727 if (Universe::narrow_klass_shift() != 0) {
1728 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1729 }
1730 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1731 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base");
1732 } else {
1733 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1734 }
1735 } else {
1736 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1737 }
1738 st->print_cr("\tCMP R_G5,R_G3" );
1739 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1740 #else // _LP64
1741 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1742 st->print_cr("\tCMP R_G5,R_G3" );
1743 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1744 #endif // _LP64
1745 }
1746 #endif
1747
1748 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1749 MacroAssembler _masm(&cbuf);
1750 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1751 Register temp_reg = G3;
1752 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1753
1754 // Load klass from receiver
1755 __ load_klass(O0, temp_reg);
1756 // Compare against expected klass
1757 __ cmp(temp_reg, G5_ic_reg);
1758 // Branch to miss code, checks xcc or icc depending
1759 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1760 }
1761
1762 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1763 return MachNode::size(ra_);
1764 }
1765
1766
1767 //=============================================================================
1768
1769
1770 // Emit exception handler code.
1771 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
1772 Register temp_reg = G3;
1773 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1774 MacroAssembler _masm(&cbuf);
1775
1776 address base = __ start_a_stub(size_exception_handler());
1777 if (base == NULL) {
1778 ciEnv::current()->record_failure("CodeCache is full");
1779 return 0; // CodeBuffer::expand failed
1780 }
1781
1782 int offset = __ offset();
1783
1784 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1785 __ delayed()->nop();
1786
1787 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1788
1789 __ end_a_stub();
1790
1791 return offset;
1792 }
1793
1794 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1795 // Can't use any of the current frame's registers as we may have deopted
1796 // at a poll and everything (including G3) can be live.
1797 Register temp_reg = L0;
1798 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1799 MacroAssembler _masm(&cbuf);
1800
1801 address base = __ start_a_stub(size_deopt_handler());
1802 if (base == NULL) {
1803 ciEnv::current()->record_failure("CodeCache is full");
1804 return 0; // CodeBuffer::expand failed
1805 }
1806
1807 int offset = __ offset();
1808 __ save_frame(0);
1809 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1810 __ delayed()->restore();
1811
1812 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1813
1814 __ end_a_stub();
1815 return offset;
1816
1817 }
1818
1819 // Given a register encoding, produce a Integer Register object
1820 static Register reg_to_register_object(int register_encoding) {
1821 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1822 return as_Register(register_encoding);
1823 }
1824
1825 // Given a register encoding, produce a single-precision Float Register object
1826 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1827 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1828 return as_SingleFloatRegister(register_encoding);
1829 }
1830
1831 // Given a register encoding, produce a double-precision Float Register object
1832 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1833 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1834 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1835 return as_DoubleFloatRegister(register_encoding);
1836 }
1837
1838 const bool Matcher::match_rule_supported(int opcode) {
1839 if (!has_match_rule(opcode))
1840 return false;
1841
1842 switch (opcode) {
1843 case Op_CountLeadingZerosI:
1844 case Op_CountLeadingZerosL:
1845 case Op_CountTrailingZerosI:
1846 case Op_CountTrailingZerosL:
1847 case Op_PopCountI:
1848 case Op_PopCountL:
1849 if (!UsePopCountInstruction)
1850 return false;
1851 case Op_CompareAndSwapL:
1852 #ifdef _LP64
1853 case Op_CompareAndSwapP:
1854 #endif
1855 if (!VM_Version::supports_cx8())
1856 return false;
1857 break;
1858 }
1859
1860 return true; // Per default match rules are supported.
1861 }
1862
1863 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
1864
1865 // TODO
1866 // identify extra cases that we might want to provide match rules for
1867 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
1868 bool ret_value = match_rule_supported(opcode);
1869 // Add rules here.
1870
1871 return ret_value; // Per default match rules are supported.
1872 }
1873
1874 const int Matcher::float_pressure(int default_pressure_threshold) {
1875 return default_pressure_threshold;
1876 }
1877
1878 int Matcher::regnum_to_fpu_offset(int regnum) {
1879 return regnum - 32; // The FP registers are in the second chunk
1880 }
1881
1882 #ifdef ASSERT
1883 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1884 #endif
1885
1886 // Vector width in bytes
1887 const int Matcher::vector_width_in_bytes(BasicType bt) {
1888 assert(MaxVectorSize == 8, "");
1889 return 8;
1890 }
1891
1892 // Vector ideal reg
1893 const int Matcher::vector_ideal_reg(int size) {
1894 assert(MaxVectorSize == 8, "");
1895 return Op_RegD;
1896 }
1897
1898 const int Matcher::vector_shift_count_ideal_reg(int size) {
1899 fatal("vector shift is not supported");
1900 return Node::NotAMachineReg;
1901 }
1902
1903 // Limits on vector size (number of elements) loaded into vector.
1904 const int Matcher::max_vector_size(const BasicType bt) {
1905 assert(is_java_primitive(bt), "only primitive type vectors");
1906 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1907 }
1908
1909 const int Matcher::min_vector_size(const BasicType bt) {
1910 return max_vector_size(bt); // Same as max.
1911 }
1912
1913 // SPARC doesn't support misaligned vectors store/load.
1914 const bool Matcher::misaligned_vectors_ok() {
1915 return false;
1916 }
1917
1918 // Current (2013) SPARC platforms need to read original key
1919 // to construct decryption expanded key
1920 const bool Matcher::pass_original_key_for_aes() {
1921 return true;
1922 }
1923
1924 // USII supports fxtof through the whole range of number, USIII doesn't
1925 const bool Matcher::convL2FSupported(void) {
1926 return VM_Version::has_fast_fxtof();
1927 }
1928
1929 // Is this branch offset short enough that a short branch can be used?
1930 //
1931 // NOTE: If the platform does not provide any short branch variants, then
1932 // this method should return false for offset 0.
1933 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1934 // The passed offset is relative to address of the branch.
1935 // Don't need to adjust the offset.
1936 return UseCBCond && Assembler::is_simm12(offset);
1937 }
1938
1939 const bool Matcher::isSimpleConstant64(jlong value) {
1940 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1941 // Depends on optimizations in MacroAssembler::setx.
1942 int hi = (int)(value >> 32);
1943 int lo = (int)(value & ~0);
1944 return (hi == 0) || (hi == -1) || (lo == 0);
1945 }
1946
1947 // No scaling for the parameter the ClearArray node.
1948 const bool Matcher::init_array_count_is_in_bytes = true;
1949
1950 // Threshold size for cleararray.
1951 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1952
1953 // No additional cost for CMOVL.
1954 const int Matcher::long_cmove_cost() { return 0; }
1955
1956 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1957 const int Matcher::float_cmove_cost() {
1958 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1959 }
1960
1961 // Does the CPU require late expand (see block.cpp for description of late expand)?
1962 const bool Matcher::require_postalloc_expand = false;
1963
1964 // Should the Matcher clone shifts on addressing modes, expecting them to
1965 // be subsumed into complex addressing expressions or compute them into
1966 // registers? True for Intel but false for most RISCs
1967 const bool Matcher::clone_shift_expressions = false;
1968
1969 // Do we need to mask the count passed to shift instructions or does
1970 // the cpu only look at the lower 5/6 bits anyway?
1971 const bool Matcher::need_masked_shift_count = false;
1972
1973 bool Matcher::narrow_oop_use_complex_address() {
1974 NOT_LP64(ShouldNotCallThis());
1975 assert(UseCompressedOops, "only for compressed oops code");
1976 return false;
1977 }
1978
1979 bool Matcher::narrow_klass_use_complex_address() {
1980 NOT_LP64(ShouldNotCallThis());
1981 assert(UseCompressedClassPointers, "only for compressed klass code");
1982 return false;
1983 }
1984
1985 // Is it better to copy float constants, or load them directly from memory?
1986 // Intel can load a float constant from a direct address, requiring no
1987 // extra registers. Most RISCs will have to materialize an address into a
1988 // register first, so they would do better to copy the constant from stack.
1989 const bool Matcher::rematerialize_float_constants = false;
1990
1991 // If CPU can load and store mis-aligned doubles directly then no fixup is
1992 // needed. Else we split the double into 2 integer pieces and move it
1993 // piece-by-piece. Only happens when passing doubles into C code as the
1994 // Java calling convention forces doubles to be aligned.
1995 #ifdef _LP64
1996 const bool Matcher::misaligned_doubles_ok = true;
1997 #else
1998 const bool Matcher::misaligned_doubles_ok = false;
1999 #endif
2000
2001 // No-op on SPARC.
2002 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2003 }
2004
2005 // Advertise here if the CPU requires explicit rounding operations
2006 // to implement the UseStrictFP mode.
2007 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2008
2009 // Are floats converted to double when stored to stack during deoptimization?
2010 // Sparc does not handle callee-save floats.
2011 bool Matcher::float_in_double() { return false; }
2012
2013 // Do ints take an entire long register or just half?
2014 // Note that we if-def off of _LP64.
2015 // The relevant question is how the int is callee-saved. In _LP64
2016 // the whole long is written but de-opt'ing will have to extract
2017 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
2018 #ifdef _LP64
2019 const bool Matcher::int_in_long = true;
2020 #else
2021 const bool Matcher::int_in_long = false;
2022 #endif
2023
2024 // Return whether or not this register is ever used as an argument. This
2025 // function is used on startup to build the trampoline stubs in generateOptoStub.
2026 // Registers not mentioned will be killed by the VM call in the trampoline, and
2027 // arguments in those registers not be available to the callee.
2028 bool Matcher::can_be_java_arg( int reg ) {
2029 // Standard sparc 6 args in registers
2030 if( reg == R_I0_num ||
2031 reg == R_I1_num ||
2032 reg == R_I2_num ||
2033 reg == R_I3_num ||
2034 reg == R_I4_num ||
2035 reg == R_I5_num ) return true;
2036 #ifdef _LP64
2037 // 64-bit builds can pass 64-bit pointers and longs in
2038 // the high I registers
2039 if( reg == R_I0H_num ||
2040 reg == R_I1H_num ||
2041 reg == R_I2H_num ||
2042 reg == R_I3H_num ||
2043 reg == R_I4H_num ||
2044 reg == R_I5H_num ) return true;
2045
2046 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
2047 return true;
2048 }
2049
2050 #else
2051 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
2052 // Longs cannot be passed in O regs, because O regs become I regs
2053 // after a 'save' and I regs get their high bits chopped off on
2054 // interrupt.
2055 if( reg == R_G1H_num || reg == R_G1_num ) return true;
2056 if( reg == R_G4H_num || reg == R_G4_num ) return true;
2057 #endif
2058 // A few float args in registers
2059 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
2060
2061 return false;
2062 }
2063
2064 bool Matcher::is_spillable_arg( int reg ) {
2065 return can_be_java_arg(reg);
2066 }
2067
2068 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
2069 // Use hardware SDIVX instruction when it is
2070 // faster than a code which use multiply.
2071 return VM_Version::has_fast_idiv();
2072 }
2073
2074 // Register for DIVI projection of divmodI
2075 RegMask Matcher::divI_proj_mask() {
2076 ShouldNotReachHere();
2077 return RegMask();
2078 }
2079
2080 // Register for MODI projection of divmodI
2081 RegMask Matcher::modI_proj_mask() {
2082 ShouldNotReachHere();
2083 return RegMask();
2084 }
2085
2086 // Register for DIVL projection of divmodL
2087 RegMask Matcher::divL_proj_mask() {
2088 ShouldNotReachHere();
2089 return RegMask();
2090 }
2091
2092 // Register for MODL projection of divmodL
2093 RegMask Matcher::modL_proj_mask() {
2094 ShouldNotReachHere();
2095 return RegMask();
2096 }
2097
2098 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2099 return L7_REGP_mask();
2100 }
2101
2102 %}
2103
2104
2105 // The intptr_t operand types, defined by textual substitution.
2106 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2107 #ifdef _LP64
2108 #define immX immL
2109 #define immX13 immL13
2110 #define immX13m7 immL13m7
2111 #define iRegX iRegL
2112 #define g1RegX g1RegL
2113 #else
2114 #define immX immI
2115 #define immX13 immI13
2116 #define immX13m7 immI13m7
2117 #define iRegX iRegI
2118 #define g1RegX g1RegI
2119 #endif
2120
2121 //----------ENCODING BLOCK-----------------------------------------------------
2122 // This block specifies the encoding classes used by the compiler to output
2123 // byte streams. Encoding classes are parameterized macros used by
2124 // Machine Instruction Nodes in order to generate the bit encoding of the
2125 // instruction. Operands specify their base encoding interface with the
2126 // interface keyword. There are currently supported four interfaces,
2127 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2128 // operand to generate a function which returns its register number when
2129 // queried. CONST_INTER causes an operand to generate a function which
2130 // returns the value of the constant when queried. MEMORY_INTER causes an
2131 // operand to generate four functions which return the Base Register, the
2132 // Index Register, the Scale Value, and the Offset Value of the operand when
2133 // queried. COND_INTER causes an operand to generate six functions which
2134 // return the encoding code (ie - encoding bits for the instruction)
2135 // associated with each basic boolean condition for a conditional instruction.
2136 //
2137 // Instructions specify two basic values for encoding. Again, a function
2138 // is available to check if the constant displacement is an oop. They use the
2139 // ins_encode keyword to specify their encoding classes (which must be
2140 // a sequence of enc_class names, and their parameters, specified in
2141 // the encoding block), and they use the
2142 // opcode keyword to specify, in order, their primary, secondary, and
2143 // tertiary opcode. Only the opcode sections which a particular instruction
2144 // needs for encoding need to be specified.
2145 encode %{
2146 enc_class enc_untested %{
2147 #ifdef ASSERT
2148 MacroAssembler _masm(&cbuf);
2149 __ untested("encoding");
2150 #endif
2151 %}
2152
2153 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2154 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
2155 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2156 %}
2157
2158 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2159 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2160 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2161 %}
2162
2163 enc_class form3_mem_prefetch_read( memory mem ) %{
2164 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2165 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2166 %}
2167
2168 enc_class form3_mem_prefetch_write( memory mem ) %{
2169 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2170 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2171 %}
2172
2173 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2174 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2175 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2176 guarantee($mem$$index == R_G0_enc, "double index?");
2177 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2178 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2179 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2180 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2181 %}
2182
2183 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2184 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2185 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2186 guarantee($mem$$index == R_G0_enc, "double index?");
2187 // Load long with 2 instructions
2188 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2189 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2190 %}
2191
2192 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2193 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2194 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2195 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2196 %}
2197
2198 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2199 // Encode a reg-reg copy. If it is useless, then empty encoding.
2200 if( $rs2$$reg != $rd$$reg )
2201 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2202 %}
2203
2204 // Target lo half of long
2205 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2206 // Encode a reg-reg copy. If it is useless, then empty encoding.
2207 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2208 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2209 %}
2210
2211 // Source lo half of long
2212 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2213 // Encode a reg-reg copy. If it is useless, then empty encoding.
2214 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2215 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2216 %}
2217
2218 // Target hi half of long
2219 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2220 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2221 %}
2222
2223 // Source lo half of long, and leave it sign extended.
2224 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2225 // Sign extend low half
2226 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2227 %}
2228
2229 // Source hi half of long, and leave it sign extended.
2230 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2231 // Shift high half to low half
2232 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2233 %}
2234
2235 // Source hi half of long
2236 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2237 // Encode a reg-reg copy. If it is useless, then empty encoding.
2238 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2239 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2240 %}
2241
2242 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2243 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2244 %}
2245
2246 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2247 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2248 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2249 %}
2250
2251 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2252 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2253 // clear if nothing else is happening
2254 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2255 // blt,a,pn done
2256 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2257 // mov dst,-1 in delay slot
2258 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2259 %}
2260
2261 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2262 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2263 %}
2264
2265 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2266 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2267 %}
2268
2269 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2270 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2271 %}
2272
2273 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2274 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2275 %}
2276
2277 enc_class move_return_pc_to_o1() %{
2278 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2279 %}
2280
2281 #ifdef _LP64
2282 /* %%% merge with enc_to_bool */
2283 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2284 MacroAssembler _masm(&cbuf);
2285
2286 Register src_reg = reg_to_register_object($src$$reg);
2287 Register dst_reg = reg_to_register_object($dst$$reg);
2288 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2289 %}
2290 #endif
2291
2292 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2293 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2294 MacroAssembler _masm(&cbuf);
2295
2296 Register p_reg = reg_to_register_object($p$$reg);
2297 Register q_reg = reg_to_register_object($q$$reg);
2298 Register y_reg = reg_to_register_object($y$$reg);
2299 Register tmp_reg = reg_to_register_object($tmp$$reg);
2300
2301 __ subcc( p_reg, q_reg, p_reg );
2302 __ add ( p_reg, y_reg, tmp_reg );
2303 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2304 %}
2305
2306 enc_class form_d2i_helper(regD src, regF dst) %{
2307 // fcmp %fcc0,$src,$src
2308 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2309 // branch %fcc0 not-nan, predict taken
2310 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2311 // fdtoi $src,$dst
2312 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2313 // fitos $dst,$dst (if nan)
2314 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2315 // clear $dst (if nan)
2316 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2317 // carry on here...
2318 %}
2319
2320 enc_class form_d2l_helper(regD src, regD dst) %{
2321 // fcmp %fcc0,$src,$src check for NAN
2322 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2323 // branch %fcc0 not-nan, predict taken
2324 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2325 // fdtox $src,$dst convert in delay slot
2326 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2327 // fxtod $dst,$dst (if nan)
2328 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2329 // clear $dst (if nan)
2330 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2331 // carry on here...
2332 %}
2333
2334 enc_class form_f2i_helper(regF src, regF dst) %{
2335 // fcmps %fcc0,$src,$src
2336 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2337 // branch %fcc0 not-nan, predict taken
2338 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2339 // fstoi $src,$dst
2340 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2341 // fitos $dst,$dst (if nan)
2342 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2343 // clear $dst (if nan)
2344 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2345 // carry on here...
2346 %}
2347
2348 enc_class form_f2l_helper(regF src, regD dst) %{
2349 // fcmps %fcc0,$src,$src
2350 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2351 // branch %fcc0 not-nan, predict taken
2352 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2353 // fstox $src,$dst
2354 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2355 // fxtod $dst,$dst (if nan)
2356 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2357 // clear $dst (if nan)
2358 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2359 // carry on here...
2360 %}
2361
2362 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2363 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2364 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2365 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2366
2367 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2368
2369 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2370 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2371
2372 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2373 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2374 %}
2375
2376 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2377 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2378 %}
2379
2380 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2381 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2382 %}
2383
2384 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2385 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2386 %}
2387
2388 enc_class form3_convI2F(regF rs2, regF rd) %{
2389 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2390 %}
2391
2392 // Encloding class for traceable jumps
2393 enc_class form_jmpl(g3RegP dest) %{
2394 emit_jmpl(cbuf, $dest$$reg);
2395 %}
2396
2397 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2398 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2399 %}
2400
2401 enc_class form2_nop() %{
2402 emit_nop(cbuf);
2403 %}
2404
2405 enc_class form2_illtrap() %{
2406 emit_illtrap(cbuf);
2407 %}
2408
2409
2410 // Compare longs and convert into -1, 0, 1.
2411 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2412 // CMP $src1,$src2
2413 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2414 // blt,a,pn done
2415 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2416 // mov dst,-1 in delay slot
2417 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2418 // bgt,a,pn done
2419 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2420 // mov dst,1 in delay slot
2421 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2422 // CLR $dst
2423 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2424 %}
2425
2426 enc_class enc_PartialSubtypeCheck() %{
2427 MacroAssembler _masm(&cbuf);
2428 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2429 __ delayed()->nop();
2430 %}
2431
2432 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2433 MacroAssembler _masm(&cbuf);
2434 Label* L = $labl$$label;
2435 Assembler::Predict predict_taken =
2436 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2437
2438 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2439 __ delayed()->nop();
2440 %}
2441
2442 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2443 MacroAssembler _masm(&cbuf);
2444 Label* L = $labl$$label;
2445 Assembler::Predict predict_taken =
2446 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2447
2448 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2449 __ delayed()->nop();
2450 %}
2451
2452 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2453 int op = (Assembler::arith_op << 30) |
2454 ($dst$$reg << 25) |
2455 (Assembler::movcc_op3 << 19) |
2456 (1 << 18) | // cc2 bit for 'icc'
2457 ($cmp$$cmpcode << 14) |
2458 (0 << 13) | // select register move
2459 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2460 ($src$$reg << 0);
2461 cbuf.insts()->emit_int32(op);
2462 %}
2463
2464 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2465 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2466 int op = (Assembler::arith_op << 30) |
2467 ($dst$$reg << 25) |
2468 (Assembler::movcc_op3 << 19) |
2469 (1 << 18) | // cc2 bit for 'icc'
2470 ($cmp$$cmpcode << 14) |
2471 (1 << 13) | // select immediate move
2472 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2473 (simm11 << 0);
2474 cbuf.insts()->emit_int32(op);
2475 %}
2476
2477 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2478 int op = (Assembler::arith_op << 30) |
2479 ($dst$$reg << 25) |
2480 (Assembler::movcc_op3 << 19) |
2481 (0 << 18) | // cc2 bit for 'fccX'
2482 ($cmp$$cmpcode << 14) |
2483 (0 << 13) | // select register move
2484 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2485 ($src$$reg << 0);
2486 cbuf.insts()->emit_int32(op);
2487 %}
2488
2489 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2490 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2491 int op = (Assembler::arith_op << 30) |
2492 ($dst$$reg << 25) |
2493 (Assembler::movcc_op3 << 19) |
2494 (0 << 18) | // cc2 bit for 'fccX'
2495 ($cmp$$cmpcode << 14) |
2496 (1 << 13) | // select immediate move
2497 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2498 (simm11 << 0);
2499 cbuf.insts()->emit_int32(op);
2500 %}
2501
2502 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2503 int op = (Assembler::arith_op << 30) |
2504 ($dst$$reg << 25) |
2505 (Assembler::fpop2_op3 << 19) |
2506 (0 << 18) |
2507 ($cmp$$cmpcode << 14) |
2508 (1 << 13) | // select register move
2509 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2510 ($primary << 5) | // select single, double or quad
2511 ($src$$reg << 0);
2512 cbuf.insts()->emit_int32(op);
2513 %}
2514
2515 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2516 int op = (Assembler::arith_op << 30) |
2517 ($dst$$reg << 25) |
2518 (Assembler::fpop2_op3 << 19) |
2519 (0 << 18) |
2520 ($cmp$$cmpcode << 14) |
2521 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2522 ($primary << 5) | // select single, double or quad
2523 ($src$$reg << 0);
2524 cbuf.insts()->emit_int32(op);
2525 %}
2526
2527 // Used by the MIN/MAX encodings. Same as a CMOV, but
2528 // the condition comes from opcode-field instead of an argument.
2529 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2530 int op = (Assembler::arith_op << 30) |
2531 ($dst$$reg << 25) |
2532 (Assembler::movcc_op3 << 19) |
2533 (1 << 18) | // cc2 bit for 'icc'
2534 ($primary << 14) |
2535 (0 << 13) | // select register move
2536 (0 << 11) | // cc1, cc0 bits for 'icc'
2537 ($src$$reg << 0);
2538 cbuf.insts()->emit_int32(op);
2539 %}
2540
2541 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2542 int op = (Assembler::arith_op << 30) |
2543 ($dst$$reg << 25) |
2544 (Assembler::movcc_op3 << 19) |
2545 (6 << 16) | // cc2 bit for 'xcc'
2546 ($primary << 14) |
2547 (0 << 13) | // select register move
2548 (0 << 11) | // cc1, cc0 bits for 'icc'
2549 ($src$$reg << 0);
2550 cbuf.insts()->emit_int32(op);
2551 %}
2552
2553 enc_class Set13( immI13 src, iRegI rd ) %{
2554 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2555 %}
2556
2557 enc_class SetHi22( immI src, iRegI rd ) %{
2558 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2559 %}
2560
2561 enc_class Set32( immI src, iRegI rd ) %{
2562 MacroAssembler _masm(&cbuf);
2563 __ set($src$$constant, reg_to_register_object($rd$$reg));
2564 %}
2565
2566 enc_class call_epilog %{
2567 if( VerifyStackAtCalls ) {
2568 MacroAssembler _masm(&cbuf);
2569 int framesize = ra_->C->frame_size_in_bytes();
2570 Register temp_reg = G3;
2571 __ add(SP, framesize, temp_reg);
2572 __ cmp(temp_reg, FP);
2573 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2574 }
2575 %}
2576
2577 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2578 // to G1 so the register allocator will not have to deal with the misaligned register
2579 // pair.
2580 enc_class adjust_long_from_native_call %{
2581 #ifndef _LP64
2582 if (returns_long()) {
2583 // sllx O0,32,O0
2584 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2585 // srl O1,0,O1
2586 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2587 // or O0,O1,G1
2588 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2589 }
2590 #endif
2591 %}
2592
2593 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2594 // CALL directly to the runtime
2595 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2596 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2597 /*preserve_g2=*/true);
2598 %}
2599
2600 enc_class preserve_SP %{
2601 MacroAssembler _masm(&cbuf);
2602 __ mov(SP, L7_mh_SP_save);
2603 %}
2604
2605 enc_class restore_SP %{
2606 MacroAssembler _masm(&cbuf);
2607 __ mov(L7_mh_SP_save, SP);
2608 %}
2609
2610 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2611 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2612 // who we intended to call.
2613 if (!_method) {
2614 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2615 } else if (_optimized_virtual) {
2616 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2617 } else {
2618 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2619 }
2620 if (_method) { // Emit stub for static call.
2621 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
2622 // Stub does not fit into scratch buffer if TraceJumps is enabled
2623 if (stub == NULL && !(TraceJumps && Compile::current()->in_scratch_emit_size())) {
2624 ciEnv::current()->record_failure("CodeCache is full");
2625 return;
2626 }
2627 }
2628 %}
2629
2630 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2631 MacroAssembler _masm(&cbuf);
2632 __ set_inst_mark();
2633 int vtable_index = this->_vtable_index;
2634 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2635 if (vtable_index < 0) {
2636 // must be invalid_vtable_index, not nonvirtual_vtable_index
2637 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2638 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2639 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2640 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2641 __ ic_call((address)$meth$$method);
2642 } else {
2643 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2644 // Just go thru the vtable
2645 // get receiver klass (receiver already checked for non-null)
2646 // If we end up going thru a c2i adapter interpreter expects method in G5
2647 int off = __ offset();
2648 __ load_klass(O0, G3_scratch);
2649 int klass_load_size;
2650 if (UseCompressedClassPointers) {
2651 assert(Universe::heap() != NULL, "java heap should be initialized");
2652 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2653 } else {
2654 klass_load_size = 1*BytesPerInstWord;
2655 }
2656 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2657 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2658 if (Assembler::is_simm13(v_off)) {
2659 __ ld_ptr(G3, v_off, G5_method);
2660 } else {
2661 // Generate 2 instructions
2662 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2663 __ or3(G5_method, v_off & 0x3ff, G5_method);
2664 // ld_ptr, set_hi, set
2665 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2666 "Unexpected instruction size(s)");
2667 __ ld_ptr(G3, G5_method, G5_method);
2668 }
2669 // NOTE: for vtable dispatches, the vtable entry will never be null.
2670 // However it may very well end up in handle_wrong_method if the
2671 // method is abstract for the particular class.
2672 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2673 // jump to target (either compiled code or c2iadapter)
2674 __ jmpl(G3_scratch, G0, O7);
2675 __ delayed()->nop();
2676 }
2677 %}
2678
2679 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2680 MacroAssembler _masm(&cbuf);
2681
2682 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2683 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2684 // we might be calling a C2I adapter which needs it.
2685
2686 assert(temp_reg != G5_ic_reg, "conflicting registers");
2687 // Load nmethod
2688 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2689
2690 // CALL to compiled java, indirect the contents of G3
2691 __ set_inst_mark();
2692 __ callr(temp_reg, G0);
2693 __ delayed()->nop();
2694 %}
2695
2696 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2697 MacroAssembler _masm(&cbuf);
2698 Register Rdividend = reg_to_register_object($src1$$reg);
2699 Register Rdivisor = reg_to_register_object($src2$$reg);
2700 Register Rresult = reg_to_register_object($dst$$reg);
2701
2702 __ sra(Rdivisor, 0, Rdivisor);
2703 __ sra(Rdividend, 0, Rdividend);
2704 __ sdivx(Rdividend, Rdivisor, Rresult);
2705 %}
2706
2707 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2708 MacroAssembler _masm(&cbuf);
2709
2710 Register Rdividend = reg_to_register_object($src1$$reg);
2711 int divisor = $imm$$constant;
2712 Register Rresult = reg_to_register_object($dst$$reg);
2713
2714 __ sra(Rdividend, 0, Rdividend);
2715 __ sdivx(Rdividend, divisor, Rresult);
2716 %}
2717
2718 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2719 MacroAssembler _masm(&cbuf);
2720 Register Rsrc1 = reg_to_register_object($src1$$reg);
2721 Register Rsrc2 = reg_to_register_object($src2$$reg);
2722 Register Rdst = reg_to_register_object($dst$$reg);
2723
2724 __ sra( Rsrc1, 0, Rsrc1 );
2725 __ sra( Rsrc2, 0, Rsrc2 );
2726 __ mulx( Rsrc1, Rsrc2, Rdst );
2727 __ srlx( Rdst, 32, Rdst );
2728 %}
2729
2730 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2731 MacroAssembler _masm(&cbuf);
2732 Register Rdividend = reg_to_register_object($src1$$reg);
2733 Register Rdivisor = reg_to_register_object($src2$$reg);
2734 Register Rresult = reg_to_register_object($dst$$reg);
2735 Register Rscratch = reg_to_register_object($scratch$$reg);
2736
2737 assert(Rdividend != Rscratch, "");
2738 assert(Rdivisor != Rscratch, "");
2739
2740 __ sra(Rdividend, 0, Rdividend);
2741 __ sra(Rdivisor, 0, Rdivisor);
2742 __ sdivx(Rdividend, Rdivisor, Rscratch);
2743 __ mulx(Rscratch, Rdivisor, Rscratch);
2744 __ sub(Rdividend, Rscratch, Rresult);
2745 %}
2746
2747 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2748 MacroAssembler _masm(&cbuf);
2749
2750 Register Rdividend = reg_to_register_object($src1$$reg);
2751 int divisor = $imm$$constant;
2752 Register Rresult = reg_to_register_object($dst$$reg);
2753 Register Rscratch = reg_to_register_object($scratch$$reg);
2754
2755 assert(Rdividend != Rscratch, "");
2756
2757 __ sra(Rdividend, 0, Rdividend);
2758 __ sdivx(Rdividend, divisor, Rscratch);
2759 __ mulx(Rscratch, divisor, Rscratch);
2760 __ sub(Rdividend, Rscratch, Rresult);
2761 %}
2762
2763 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2764 MacroAssembler _masm(&cbuf);
2765
2766 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2767 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2768
2769 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2770 %}
2771
2772 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2773 MacroAssembler _masm(&cbuf);
2774
2775 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2776 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2777
2778 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2779 %}
2780
2781 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2782 MacroAssembler _masm(&cbuf);
2783
2784 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2785 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2786
2787 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2788 %}
2789
2790 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2791 MacroAssembler _masm(&cbuf);
2792
2793 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2794 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2795
2796 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2797 %}
2798
2799 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2800 MacroAssembler _masm(&cbuf);
2801
2802 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2803 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2804
2805 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2806 %}
2807
2808 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2809 MacroAssembler _masm(&cbuf);
2810
2811 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2812 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2813
2814 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2815 %}
2816
2817 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2818 MacroAssembler _masm(&cbuf);
2819
2820 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2821 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2822
2823 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2824 %}
2825
2826 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2827 MacroAssembler _masm(&cbuf);
2828
2829 Register Roop = reg_to_register_object($oop$$reg);
2830 Register Rbox = reg_to_register_object($box$$reg);
2831 Register Rscratch = reg_to_register_object($scratch$$reg);
2832 Register Rmark = reg_to_register_object($scratch2$$reg);
2833
2834 assert(Roop != Rscratch, "");
2835 assert(Roop != Rmark, "");
2836 assert(Rbox != Rscratch, "");
2837 assert(Rbox != Rmark, "");
2838
2839 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2840 %}
2841
2842 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2843 MacroAssembler _masm(&cbuf);
2844
2845 Register Roop = reg_to_register_object($oop$$reg);
2846 Register Rbox = reg_to_register_object($box$$reg);
2847 Register Rscratch = reg_to_register_object($scratch$$reg);
2848 Register Rmark = reg_to_register_object($scratch2$$reg);
2849
2850 assert(Roop != Rscratch, "");
2851 assert(Roop != Rmark, "");
2852 assert(Rbox != Rscratch, "");
2853 assert(Rbox != Rmark, "");
2854
2855 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2856 %}
2857
2858 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2859 MacroAssembler _masm(&cbuf);
2860 Register Rmem = reg_to_register_object($mem$$reg);
2861 Register Rold = reg_to_register_object($old$$reg);
2862 Register Rnew = reg_to_register_object($new$$reg);
2863
2864 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2865 __ cmp( Rold, Rnew );
2866 %}
2867
2868 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2869 Register Rmem = reg_to_register_object($mem$$reg);
2870 Register Rold = reg_to_register_object($old$$reg);
2871 Register Rnew = reg_to_register_object($new$$reg);
2872
2873 MacroAssembler _masm(&cbuf);
2874 __ mov(Rnew, O7);
2875 __ casx(Rmem, Rold, O7);
2876 __ cmp( Rold, O7 );
2877 %}
2878
2879 // raw int cas, used for compareAndSwap
2880 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2881 Register Rmem = reg_to_register_object($mem$$reg);
2882 Register Rold = reg_to_register_object($old$$reg);
2883 Register Rnew = reg_to_register_object($new$$reg);
2884
2885 MacroAssembler _masm(&cbuf);
2886 __ mov(Rnew, O7);
2887 __ cas(Rmem, Rold, O7);
2888 __ cmp( Rold, O7 );
2889 %}
2890
2891 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2892 Register Rres = reg_to_register_object($res$$reg);
2893
2894 MacroAssembler _masm(&cbuf);
2895 __ mov(1, Rres);
2896 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2897 %}
2898
2899 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2900 Register Rres = reg_to_register_object($res$$reg);
2901
2902 MacroAssembler _masm(&cbuf);
2903 __ mov(1, Rres);
2904 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2905 %}
2906
2907 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2908 MacroAssembler _masm(&cbuf);
2909 Register Rdst = reg_to_register_object($dst$$reg);
2910 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2911 : reg_to_DoubleFloatRegister_object($src1$$reg);
2912 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2913 : reg_to_DoubleFloatRegister_object($src2$$reg);
2914
2915 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2916 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2917 %}
2918
2919 enc_class enc_rethrow() %{
2920 cbuf.set_insts_mark();
2921 Register temp_reg = G3;
2922 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
2923 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
2924 MacroAssembler _masm(&cbuf);
2925 #ifdef ASSERT
2926 __ save_frame(0);
2927 AddressLiteral last_rethrow_addrlit(&last_rethrow);
2928 __ sethi(last_rethrow_addrlit, L1);
2929 Address addr(L1, last_rethrow_addrlit.low10());
2930 __ rdpc(L2);
2931 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
2932 __ st_ptr(L2, addr);
2933 __ restore();
2934 #endif
2935 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
2936 __ delayed()->nop();
2937 %}
2938
2939 enc_class emit_mem_nop() %{
2940 // Generates the instruction LDUXA [o6,g0],#0x82,g0
2941 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
2942 %}
2943
2944 enc_class emit_fadd_nop() %{
2945 // Generates the instruction FMOVS f31,f31
2946 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
2947 %}
2948
2949 enc_class emit_br_nop() %{
2950 // Generates the instruction BPN,PN .
2951 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
2952 %}
2953
2954 enc_class enc_membar_acquire %{
2955 MacroAssembler _masm(&cbuf);
2956 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
2957 %}
2958
2959 enc_class enc_membar_release %{
2960 MacroAssembler _masm(&cbuf);
2961 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
2962 %}
2963
2964 enc_class enc_membar_volatile %{
2965 MacroAssembler _masm(&cbuf);
2966 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
2967 %}
2968
2969 %}
2970
2971 //----------FRAME--------------------------------------------------------------
2972 // Definition of frame structure and management information.
2973 //
2974 // S T A C K L A Y O U T Allocators stack-slot number
2975 // | (to get allocators register number
2976 // G Owned by | | v add VMRegImpl::stack0)
2977 // r CALLER | |
2978 // o | +--------+ pad to even-align allocators stack-slot
2979 // w V | pad0 | numbers; owned by CALLER
2980 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2981 // h ^ | in | 5
2982 // | | args | 4 Holes in incoming args owned by SELF
2983 // | | | | 3
2984 // | | +--------+
2985 // V | | old out| Empty on Intel, window on Sparc
2986 // | old |preserve| Must be even aligned.
2987 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
2988 // | | in | 3 area for Intel ret address
2989 // Owned by |preserve| Empty on Sparc.
2990 // SELF +--------+
2991 // | | pad2 | 2 pad to align old SP
2992 // | +--------+ 1
2993 // | | locks | 0
2994 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
2995 // | | pad1 | 11 pad to align new SP
2996 // | +--------+
2997 // | | | 10
2998 // | | spills | 9 spills
2999 // V | | 8 (pad0 slot for callee)
3000 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3001 // ^ | out | 7
3002 // | | args | 6 Holes in outgoing args owned by CALLEE
3003 // Owned by +--------+
3004 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3005 // | new |preserve| Must be even-aligned.
3006 // | SP-+--------+----> Matcher::_new_SP, even aligned
3007 // | | |
3008 //
3009 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3010 // known from SELF's arguments and the Java calling convention.
3011 // Region 6-7 is determined per call site.
3012 // Note 2: If the calling convention leaves holes in the incoming argument
3013 // area, those holes are owned by SELF. Holes in the outgoing area
3014 // are owned by the CALLEE. Holes should not be nessecary in the
3015 // incoming area, as the Java calling convention is completely under
3016 // the control of the AD file. Doubles can be sorted and packed to
3017 // avoid holes. Holes in the outgoing arguments may be necessary for
3018 // varargs C calling conventions.
3019 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3020 // even aligned with pad0 as needed.
3021 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3022 // region 6-11 is even aligned; it may be padded out more so that
3023 // the region from SP to FP meets the minimum stack alignment.
3024
3025 frame %{
3026 // What direction does stack grow in (assumed to be same for native & Java)
3027 stack_direction(TOWARDS_LOW);
3028
3029 // These two registers define part of the calling convention
3030 // between compiled code and the interpreter.
3031 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
3032 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3033
3034 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3035 cisc_spilling_operand_name(indOffset);
3036
3037 // Number of stack slots consumed by a Monitor enter
3038 #ifdef _LP64
3039 sync_stack_slots(2);
3040 #else
3041 sync_stack_slots(1);
3042 #endif
3043
3044 // Compiled code's Frame Pointer
3045 frame_pointer(R_SP);
3046
3047 // Stack alignment requirement
3048 stack_alignment(StackAlignmentInBytes);
3049 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3050 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3051
3052 // Number of stack slots between incoming argument block and the start of
3053 // a new frame. The PROLOG must add this many slots to the stack. The
3054 // EPILOG must remove this many slots.
3055 in_preserve_stack_slots(0);
3056
3057 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3058 // for calls to C. Supports the var-args backing area for register parms.
3059 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3060 #ifdef _LP64
3061 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3062 varargs_C_out_slots_killed(12);
3063 #else
3064 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3065 varargs_C_out_slots_killed( 7);
3066 #endif
3067
3068 // The after-PROLOG location of the return address. Location of
3069 // return address specifies a type (REG or STACK) and a number
3070 // representing the register number (i.e. - use a register name) or
3071 // stack slot.
3072 return_addr(REG R_I7); // Ret Addr is in register I7
3073
3074 // Body of function which returns an OptoRegs array locating
3075 // arguments either in registers or in stack slots for calling
3076 // java
3077 calling_convention %{
3078 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3079
3080 %}
3081
3082 // Body of function which returns an OptoRegs array locating
3083 // arguments either in registers or in stack slots for calling
3084 // C.
3085 c_calling_convention %{
3086 // This is obviously always outgoing
3087 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3088 %}
3089
3090 // Location of native (C/C++) and interpreter return values. This is specified to
3091 // be the same as Java. In the 32-bit VM, long values are actually returned from
3092 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3093 // to and from the register pairs is done by the appropriate call and epilog
3094 // opcodes. This simplifies the register allocator.
3095 c_return_value %{
3096 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3097 #ifdef _LP64
3098 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3099 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3100 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3101 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3102 #else // !_LP64
3103 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3104 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3105 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3106 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3107 #endif
3108 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3109 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3110 %}
3111
3112 // Location of compiled Java return values. Same as C
3113 return_value %{
3114 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3115 #ifdef _LP64
3116 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3117 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3118 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3119 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3120 #else // !_LP64
3121 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3122 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3123 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3124 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3125 #endif
3126 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3127 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3128 %}
3129
3130 %}
3131
3132
3133 //----------ATTRIBUTES---------------------------------------------------------
3134 //----------Operand Attributes-------------------------------------------------
3135 op_attrib op_cost(1); // Required cost attribute
3136
3137 //----------Instruction Attributes---------------------------------------------
3138 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3139 ins_attrib ins_size(32); // Required size attribute (in bits)
3140
3141 // avoid_back_to_back attribute is an expression that must return
3142 // one of the following values defined in MachNode:
3143 // AVOID_NONE - instruction can be placed anywhere
3144 // AVOID_BEFORE - instruction cannot be placed after an
3145 // instruction with MachNode::AVOID_AFTER
3146 // AVOID_AFTER - the next instruction cannot be the one
3147 // with MachNode::AVOID_BEFORE
3148 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at
3149 // the same time
3150 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE);
3151
3152 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3153 // non-matching short branch variant of some
3154 // long branch?
3155
3156 //----------OPERANDS-----------------------------------------------------------
3157 // Operand definitions must precede instruction definitions for correct parsing
3158 // in the ADLC because operands constitute user defined types which are used in
3159 // instruction definitions.
3160
3161 //----------Simple Operands----------------------------------------------------
3162 // Immediate Operands
3163 // Integer Immediate: 32-bit
3164 operand immI() %{
3165 match(ConI);
3166
3167 op_cost(0);
3168 // formats are generated automatically for constants and base registers
3169 format %{ %}
3170 interface(CONST_INTER);
3171 %}
3172
3173 // Integer Immediate: 0-bit
3174 operand immI0() %{
3175 predicate(n->get_int() == 0);
3176 match(ConI);
3177 op_cost(0);
3178
3179 format %{ %}
3180 interface(CONST_INTER);
3181 %}
3182
3183 // Integer Immediate: 5-bit
3184 operand immI5() %{
3185 predicate(Assembler::is_simm5(n->get_int()));
3186 match(ConI);
3187 op_cost(0);
3188 format %{ %}
3189 interface(CONST_INTER);
3190 %}
3191
3192 // Integer Immediate: 8-bit
3193 operand immI8() %{
3194 predicate(Assembler::is_simm8(n->get_int()));
3195 match(ConI);
3196 op_cost(0);
3197 format %{ %}
3198 interface(CONST_INTER);
3199 %}
3200
3201 // Integer Immediate: the value 10
3202 operand immI10() %{
3203 predicate(n->get_int() == 10);
3204 match(ConI);
3205 op_cost(0);
3206
3207 format %{ %}
3208 interface(CONST_INTER);
3209 %}
3210
3211 // Integer Immediate: 11-bit
3212 operand immI11() %{
3213 predicate(Assembler::is_simm11(n->get_int()));
3214 match(ConI);
3215 op_cost(0);
3216 format %{ %}
3217 interface(CONST_INTER);
3218 %}
3219
3220 // Integer Immediate: 13-bit
3221 operand immI13() %{
3222 predicate(Assembler::is_simm13(n->get_int()));
3223 match(ConI);
3224 op_cost(0);
3225
3226 format %{ %}
3227 interface(CONST_INTER);
3228 %}
3229
3230 // Integer Immediate: 13-bit minus 7
3231 operand immI13m7() %{
3232 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3233 match(ConI);
3234 op_cost(0);
3235
3236 format %{ %}
3237 interface(CONST_INTER);
3238 %}
3239
3240 // Integer Immediate: 16-bit
3241 operand immI16() %{
3242 predicate(Assembler::is_simm16(n->get_int()));
3243 match(ConI);
3244 op_cost(0);
3245 format %{ %}
3246 interface(CONST_INTER);
3247 %}
3248
3249 // Integer Immediate: the values 1-31
3250 operand immI_1_31() %{
3251 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3252 match(ConI);
3253 op_cost(0);
3254
3255 format %{ %}
3256 interface(CONST_INTER);
3257 %}
3258
3259 // Integer Immediate: the values 32-63
3260 operand immI_32_63() %{
3261 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3262 match(ConI);
3263 op_cost(0);
3264
3265 format %{ %}
3266 interface(CONST_INTER);
3267 %}
3268
3269 // Immediates for special shifts (sign extend)
3270
3271 // Integer Immediate: the value 16
3272 operand immI_16() %{
3273 predicate(n->get_int() == 16);
3274 match(ConI);
3275 op_cost(0);
3276
3277 format %{ %}
3278 interface(CONST_INTER);
3279 %}
3280
3281 // Integer Immediate: the value 24
3282 operand immI_24() %{
3283 predicate(n->get_int() == 24);
3284 match(ConI);
3285 op_cost(0);
3286
3287 format %{ %}
3288 interface(CONST_INTER);
3289 %}
3290 // Integer Immediate: the value 255
3291 operand immI_255() %{
3292 predicate( n->get_int() == 255 );
3293 match(ConI);
3294 op_cost(0);
3295
3296 format %{ %}
3297 interface(CONST_INTER);
3298 %}
3299
3300 // Integer Immediate: the value 65535
3301 operand immI_65535() %{
3302 predicate(n->get_int() == 65535);
3303 match(ConI);
3304 op_cost(0);
3305
3306 format %{ %}
3307 interface(CONST_INTER);
3308 %}
3309
3310 // Integer Immediate: the values 0-31
3311 operand immU5() %{
3312 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3313 match(ConI);
3314 op_cost(0);
3315
3316 format %{ %}
3317 interface(CONST_INTER);
3318 %}
3319
3320 // Integer Immediate: 6-bit
3321 operand immU6() %{
3322 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3323 match(ConI);
3324 op_cost(0);
3325 format %{ %}
3326 interface(CONST_INTER);
3327 %}
3328
3329 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3330 operand immU12() %{
3331 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3332 match(ConI);
3333 op_cost(0);
3334
3335 format %{ %}
3336 interface(CONST_INTER);
3337 %}
3338
3339 // Integer Immediate non-negative
3340 operand immU31()
3341 %{
3342 predicate(n->get_int() >= 0);
3343 match(ConI);
3344
3345 op_cost(0);
3346 format %{ %}
3347 interface(CONST_INTER);
3348 %}
3349
3350 // Long Immediate: the value FF
3351 operand immL_FF() %{
3352 predicate( n->get_long() == 0xFFL );
3353 match(ConL);
3354 op_cost(0);
3355
3356 format %{ %}
3357 interface(CONST_INTER);
3358 %}
3359
3360 // Long Immediate: the value FFFF
3361 operand immL_FFFF() %{
3362 predicate( n->get_long() == 0xFFFFL );
3363 match(ConL);
3364 op_cost(0);
3365
3366 format %{ %}
3367 interface(CONST_INTER);
3368 %}
3369
3370 // Pointer Immediate: 32 or 64-bit
3371 operand immP() %{
3372 match(ConP);
3373
3374 op_cost(5);
3375 // formats are generated automatically for constants and base registers
3376 format %{ %}
3377 interface(CONST_INTER);
3378 %}
3379
3380 #ifdef _LP64
3381 // Pointer Immediate: 64-bit
3382 operand immP_set() %{
3383 predicate(!VM_Version::is_niagara_plus());
3384 match(ConP);
3385
3386 op_cost(5);
3387 // formats are generated automatically for constants and base registers
3388 format %{ %}
3389 interface(CONST_INTER);
3390 %}
3391
3392 // Pointer Immediate: 64-bit
3393 // From Niagara2 processors on a load should be better than materializing.
3394 operand immP_load() %{
3395 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3396 match(ConP);
3397
3398 op_cost(5);
3399 // formats are generated automatically for constants and base registers
3400 format %{ %}
3401 interface(CONST_INTER);
3402 %}
3403
3404 // Pointer Immediate: 64-bit
3405 operand immP_no_oop_cheap() %{
3406 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3407 match(ConP);
3408
3409 op_cost(5);
3410 // formats are generated automatically for constants and base registers
3411 format %{ %}
3412 interface(CONST_INTER);
3413 %}
3414 #endif
3415
3416 operand immP13() %{
3417 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3418 match(ConP);
3419 op_cost(0);
3420
3421 format %{ %}
3422 interface(CONST_INTER);
3423 %}
3424
3425 operand immP0() %{
3426 predicate(n->get_ptr() == 0);
3427 match(ConP);
3428 op_cost(0);
3429
3430 format %{ %}
3431 interface(CONST_INTER);
3432 %}
3433
3434 operand immP_poll() %{
3435 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3436 match(ConP);
3437
3438 // formats are generated automatically for constants and base registers
3439 format %{ %}
3440 interface(CONST_INTER);
3441 %}
3442
3443 // Pointer Immediate
3444 operand immN()
3445 %{
3446 match(ConN);
3447
3448 op_cost(10);
3449 format %{ %}
3450 interface(CONST_INTER);
3451 %}
3452
3453 operand immNKlass()
3454 %{
3455 match(ConNKlass);
3456
3457 op_cost(10);
3458 format %{ %}
3459 interface(CONST_INTER);
3460 %}
3461
3462 // NULL Pointer Immediate
3463 operand immN0()
3464 %{
3465 predicate(n->get_narrowcon() == 0);
3466 match(ConN);
3467
3468 op_cost(0);
3469 format %{ %}
3470 interface(CONST_INTER);
3471 %}
3472
3473 operand immL() %{
3474 match(ConL);
3475 op_cost(40);
3476 // formats are generated automatically for constants and base registers
3477 format %{ %}
3478 interface(CONST_INTER);
3479 %}
3480
3481 operand immL0() %{
3482 predicate(n->get_long() == 0L);
3483 match(ConL);
3484 op_cost(0);
3485 // formats are generated automatically for constants and base registers
3486 format %{ %}
3487 interface(CONST_INTER);
3488 %}
3489
3490 // Integer Immediate: 5-bit
3491 operand immL5() %{
3492 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3493 match(ConL);
3494 op_cost(0);
3495 format %{ %}
3496 interface(CONST_INTER);
3497 %}
3498
3499 // Long Immediate: 13-bit
3500 operand immL13() %{
3501 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3502 match(ConL);
3503 op_cost(0);
3504
3505 format %{ %}
3506 interface(CONST_INTER);
3507 %}
3508
3509 // Long Immediate: 13-bit minus 7
3510 operand immL13m7() %{
3511 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3512 match(ConL);
3513 op_cost(0);
3514
3515 format %{ %}
3516 interface(CONST_INTER);
3517 %}
3518
3519 // Long Immediate: low 32-bit mask
3520 operand immL_32bits() %{
3521 predicate(n->get_long() == 0xFFFFFFFFL);
3522 match(ConL);
3523 op_cost(0);
3524
3525 format %{ %}
3526 interface(CONST_INTER);
3527 %}
3528
3529 // Long Immediate: cheap (materialize in <= 3 instructions)
3530 operand immL_cheap() %{
3531 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3532 match(ConL);
3533 op_cost(0);
3534
3535 format %{ %}
3536 interface(CONST_INTER);
3537 %}
3538
3539 // Long Immediate: expensive (materialize in > 3 instructions)
3540 operand immL_expensive() %{
3541 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3542 match(ConL);
3543 op_cost(0);
3544
3545 format %{ %}
3546 interface(CONST_INTER);
3547 %}
3548
3549 // Double Immediate
3550 operand immD() %{
3551 match(ConD);
3552
3553 op_cost(40);
3554 format %{ %}
3555 interface(CONST_INTER);
3556 %}
3557
3558 // Double Immediate: +0.0d
3559 operand immD0() %{
3560 predicate(jlong_cast(n->getd()) == 0);
3561 match(ConD);
3562
3563 op_cost(0);
3564 format %{ %}
3565 interface(CONST_INTER);
3566 %}
3567
3568 // Float Immediate
3569 operand immF() %{
3570 match(ConF);
3571
3572 op_cost(20);
3573 format %{ %}
3574 interface(CONST_INTER);
3575 %}
3576
3577 // Float Immediate: +0.0f
3578 operand immF0() %{
3579 predicate(jint_cast(n->getf()) == 0);
3580 match(ConF);
3581
3582 op_cost(0);
3583 format %{ %}
3584 interface(CONST_INTER);
3585 %}
3586
3587 // Integer Register Operands
3588 // Integer Register
3589 operand iRegI() %{
3590 constraint(ALLOC_IN_RC(int_reg));
3591 match(RegI);
3592
3593 match(notemp_iRegI);
3594 match(g1RegI);
3595 match(o0RegI);
3596 match(iRegIsafe);
3597
3598 format %{ %}
3599 interface(REG_INTER);
3600 %}
3601
3602 operand notemp_iRegI() %{
3603 constraint(ALLOC_IN_RC(notemp_int_reg));
3604 match(RegI);
3605
3606 match(o0RegI);
3607
3608 format %{ %}
3609 interface(REG_INTER);
3610 %}
3611
3612 operand o0RegI() %{
3613 constraint(ALLOC_IN_RC(o0_regI));
3614 match(iRegI);
3615
3616 format %{ %}
3617 interface(REG_INTER);
3618 %}
3619
3620 // Pointer Register
3621 operand iRegP() %{
3622 constraint(ALLOC_IN_RC(ptr_reg));
3623 match(RegP);
3624
3625 match(lock_ptr_RegP);
3626 match(g1RegP);
3627 match(g2RegP);
3628 match(g3RegP);
3629 match(g4RegP);
3630 match(i0RegP);
3631 match(o0RegP);
3632 match(o1RegP);
3633 match(l7RegP);
3634
3635 format %{ %}
3636 interface(REG_INTER);
3637 %}
3638
3639 operand sp_ptr_RegP() %{
3640 constraint(ALLOC_IN_RC(sp_ptr_reg));
3641 match(RegP);
3642 match(iRegP);
3643
3644 format %{ %}
3645 interface(REG_INTER);
3646 %}
3647
3648 operand lock_ptr_RegP() %{
3649 constraint(ALLOC_IN_RC(lock_ptr_reg));
3650 match(RegP);
3651 match(i0RegP);
3652 match(o0RegP);
3653 match(o1RegP);
3654 match(l7RegP);
3655
3656 format %{ %}
3657 interface(REG_INTER);
3658 %}
3659
3660 operand g1RegP() %{
3661 constraint(ALLOC_IN_RC(g1_regP));
3662 match(iRegP);
3663
3664 format %{ %}
3665 interface(REG_INTER);
3666 %}
3667
3668 operand g2RegP() %{
3669 constraint(ALLOC_IN_RC(g2_regP));
3670 match(iRegP);
3671
3672 format %{ %}
3673 interface(REG_INTER);
3674 %}
3675
3676 operand g3RegP() %{
3677 constraint(ALLOC_IN_RC(g3_regP));
3678 match(iRegP);
3679
3680 format %{ %}
3681 interface(REG_INTER);
3682 %}
3683
3684 operand g1RegI() %{
3685 constraint(ALLOC_IN_RC(g1_regI));
3686 match(iRegI);
3687
3688 format %{ %}
3689 interface(REG_INTER);
3690 %}
3691
3692 operand g3RegI() %{
3693 constraint(ALLOC_IN_RC(g3_regI));
3694 match(iRegI);
3695
3696 format %{ %}
3697 interface(REG_INTER);
3698 %}
3699
3700 operand g4RegI() %{
3701 constraint(ALLOC_IN_RC(g4_regI));
3702 match(iRegI);
3703
3704 format %{ %}
3705 interface(REG_INTER);
3706 %}
3707
3708 operand g4RegP() %{
3709 constraint(ALLOC_IN_RC(g4_regP));
3710 match(iRegP);
3711
3712 format %{ %}
3713 interface(REG_INTER);
3714 %}
3715
3716 operand i0RegP() %{
3717 constraint(ALLOC_IN_RC(i0_regP));
3718 match(iRegP);
3719
3720 format %{ %}
3721 interface(REG_INTER);
3722 %}
3723
3724 operand o0RegP() %{
3725 constraint(ALLOC_IN_RC(o0_regP));
3726 match(iRegP);
3727
3728 format %{ %}
3729 interface(REG_INTER);
3730 %}
3731
3732 operand o1RegP() %{
3733 constraint(ALLOC_IN_RC(o1_regP));
3734 match(iRegP);
3735
3736 format %{ %}
3737 interface(REG_INTER);
3738 %}
3739
3740 operand o2RegP() %{
3741 constraint(ALLOC_IN_RC(o2_regP));
3742 match(iRegP);
3743
3744 format %{ %}
3745 interface(REG_INTER);
3746 %}
3747
3748 operand o7RegP() %{
3749 constraint(ALLOC_IN_RC(o7_regP));
3750 match(iRegP);
3751
3752 format %{ %}
3753 interface(REG_INTER);
3754 %}
3755
3756 operand l7RegP() %{
3757 constraint(ALLOC_IN_RC(l7_regP));
3758 match(iRegP);
3759
3760 format %{ %}
3761 interface(REG_INTER);
3762 %}
3763
3764 operand o7RegI() %{
3765 constraint(ALLOC_IN_RC(o7_regI));
3766 match(iRegI);
3767
3768 format %{ %}
3769 interface(REG_INTER);
3770 %}
3771
3772 operand iRegN() %{
3773 constraint(ALLOC_IN_RC(int_reg));
3774 match(RegN);
3775
3776 format %{ %}
3777 interface(REG_INTER);
3778 %}
3779
3780 // Long Register
3781 operand iRegL() %{
3782 constraint(ALLOC_IN_RC(long_reg));
3783 match(RegL);
3784
3785 format %{ %}
3786 interface(REG_INTER);
3787 %}
3788
3789 operand o2RegL() %{
3790 constraint(ALLOC_IN_RC(o2_regL));
3791 match(iRegL);
3792
3793 format %{ %}
3794 interface(REG_INTER);
3795 %}
3796
3797 operand o7RegL() %{
3798 constraint(ALLOC_IN_RC(o7_regL));
3799 match(iRegL);
3800
3801 format %{ %}
3802 interface(REG_INTER);
3803 %}
3804
3805 operand g1RegL() %{
3806 constraint(ALLOC_IN_RC(g1_regL));
3807 match(iRegL);
3808
3809 format %{ %}
3810 interface(REG_INTER);
3811 %}
3812
3813 operand g3RegL() %{
3814 constraint(ALLOC_IN_RC(g3_regL));
3815 match(iRegL);
3816
3817 format %{ %}
3818 interface(REG_INTER);
3819 %}
3820
3821 // Int Register safe
3822 // This is 64bit safe
3823 operand iRegIsafe() %{
3824 constraint(ALLOC_IN_RC(long_reg));
3825
3826 match(iRegI);
3827
3828 format %{ %}
3829 interface(REG_INTER);
3830 %}
3831
3832 // Condition Code Flag Register
3833 operand flagsReg() %{
3834 constraint(ALLOC_IN_RC(int_flags));
3835 match(RegFlags);
3836
3837 format %{ "ccr" %} // both ICC and XCC
3838 interface(REG_INTER);
3839 %}
3840
3841 // Condition Code Register, unsigned comparisons.
3842 operand flagsRegU() %{
3843 constraint(ALLOC_IN_RC(int_flags));
3844 match(RegFlags);
3845
3846 format %{ "icc_U" %}
3847 interface(REG_INTER);
3848 %}
3849
3850 // Condition Code Register, pointer comparisons.
3851 operand flagsRegP() %{
3852 constraint(ALLOC_IN_RC(int_flags));
3853 match(RegFlags);
3854
3855 #ifdef _LP64
3856 format %{ "xcc_P" %}
3857 #else
3858 format %{ "icc_P" %}
3859 #endif
3860 interface(REG_INTER);
3861 %}
3862
3863 // Condition Code Register, long comparisons.
3864 operand flagsRegL() %{
3865 constraint(ALLOC_IN_RC(int_flags));
3866 match(RegFlags);
3867
3868 format %{ "xcc_L" %}
3869 interface(REG_INTER);
3870 %}
3871
3872 // Condition Code Register, floating comparisons, unordered same as "less".
3873 operand flagsRegF() %{
3874 constraint(ALLOC_IN_RC(float_flags));
3875 match(RegFlags);
3876 match(flagsRegF0);
3877
3878 format %{ %}
3879 interface(REG_INTER);
3880 %}
3881
3882 operand flagsRegF0() %{
3883 constraint(ALLOC_IN_RC(float_flag0));
3884 match(RegFlags);
3885
3886 format %{ %}
3887 interface(REG_INTER);
3888 %}
3889
3890
3891 // Condition Code Flag Register used by long compare
3892 operand flagsReg_long_LTGE() %{
3893 constraint(ALLOC_IN_RC(int_flags));
3894 match(RegFlags);
3895 format %{ "icc_LTGE" %}
3896 interface(REG_INTER);
3897 %}
3898 operand flagsReg_long_EQNE() %{
3899 constraint(ALLOC_IN_RC(int_flags));
3900 match(RegFlags);
3901 format %{ "icc_EQNE" %}
3902 interface(REG_INTER);
3903 %}
3904 operand flagsReg_long_LEGT() %{
3905 constraint(ALLOC_IN_RC(int_flags));
3906 match(RegFlags);
3907 format %{ "icc_LEGT" %}
3908 interface(REG_INTER);
3909 %}
3910
3911
3912 operand regD() %{
3913 constraint(ALLOC_IN_RC(dflt_reg));
3914 match(RegD);
3915
3916 match(regD_low);
3917
3918 format %{ %}
3919 interface(REG_INTER);
3920 %}
3921
3922 operand regF() %{
3923 constraint(ALLOC_IN_RC(sflt_reg));
3924 match(RegF);
3925
3926 format %{ %}
3927 interface(REG_INTER);
3928 %}
3929
3930 operand regD_low() %{
3931 constraint(ALLOC_IN_RC(dflt_low_reg));
3932 match(regD);
3933
3934 format %{ %}
3935 interface(REG_INTER);
3936 %}
3937
3938 // Special Registers
3939
3940 // Method Register
3941 operand inline_cache_regP(iRegP reg) %{
3942 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
3943 match(reg);
3944 format %{ %}
3945 interface(REG_INTER);
3946 %}
3947
3948 operand interpreter_method_oop_regP(iRegP reg) %{
3949 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
3950 match(reg);
3951 format %{ %}
3952 interface(REG_INTER);
3953 %}
3954
3955
3956 //----------Complex Operands---------------------------------------------------
3957 // Indirect Memory Reference
3958 operand indirect(sp_ptr_RegP reg) %{
3959 constraint(ALLOC_IN_RC(sp_ptr_reg));
3960 match(reg);
3961
3962 op_cost(100);
3963 format %{ "[$reg]" %}
3964 interface(MEMORY_INTER) %{
3965 base($reg);
3966 index(0x0);
3967 scale(0x0);
3968 disp(0x0);
3969 %}
3970 %}
3971
3972 // Indirect with simm13 Offset
3973 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
3974 constraint(ALLOC_IN_RC(sp_ptr_reg));
3975 match(AddP reg offset);
3976
3977 op_cost(100);
3978 format %{ "[$reg + $offset]" %}
3979 interface(MEMORY_INTER) %{
3980 base($reg);
3981 index(0x0);
3982 scale(0x0);
3983 disp($offset);
3984 %}
3985 %}
3986
3987 // Indirect with simm13 Offset minus 7
3988 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
3989 constraint(ALLOC_IN_RC(sp_ptr_reg));
3990 match(AddP reg offset);
3991
3992 op_cost(100);
3993 format %{ "[$reg + $offset]" %}
3994 interface(MEMORY_INTER) %{
3995 base($reg);
3996 index(0x0);
3997 scale(0x0);
3998 disp($offset);
3999 %}
4000 %}
4001
4002 // Note: Intel has a swapped version also, like this:
4003 //operand indOffsetX(iRegI reg, immP offset) %{
4004 // constraint(ALLOC_IN_RC(int_reg));
4005 // match(AddP offset reg);
4006 //
4007 // op_cost(100);
4008 // format %{ "[$reg + $offset]" %}
4009 // interface(MEMORY_INTER) %{
4010 // base($reg);
4011 // index(0x0);
4012 // scale(0x0);
4013 // disp($offset);
4014 // %}
4015 //%}
4016 //// However, it doesn't make sense for SPARC, since
4017 // we have no particularly good way to embed oops in
4018 // single instructions.
4019
4020 // Indirect with Register Index
4021 operand indIndex(iRegP addr, iRegX index) %{
4022 constraint(ALLOC_IN_RC(ptr_reg));
4023 match(AddP addr index);
4024
4025 op_cost(100);
4026 format %{ "[$addr + $index]" %}
4027 interface(MEMORY_INTER) %{
4028 base($addr);
4029 index($index);
4030 scale(0x0);
4031 disp(0x0);
4032 %}
4033 %}
4034
4035 //----------Special Memory Operands--------------------------------------------
4036 // Stack Slot Operand - This operand is used for loading and storing temporary
4037 // values on the stack where a match requires a value to
4038 // flow through memory.
4039 operand stackSlotI(sRegI reg) %{
4040 constraint(ALLOC_IN_RC(stack_slots));
4041 op_cost(100);
4042 //match(RegI);
4043 format %{ "[$reg]" %}
4044 interface(MEMORY_INTER) %{
4045 base(0xE); // R_SP
4046 index(0x0);
4047 scale(0x0);
4048 disp($reg); // Stack Offset
4049 %}
4050 %}
4051
4052 operand stackSlotP(sRegP reg) %{
4053 constraint(ALLOC_IN_RC(stack_slots));
4054 op_cost(100);
4055 //match(RegP);
4056 format %{ "[$reg]" %}
4057 interface(MEMORY_INTER) %{
4058 base(0xE); // R_SP
4059 index(0x0);
4060 scale(0x0);
4061 disp($reg); // Stack Offset
4062 %}
4063 %}
4064
4065 operand stackSlotF(sRegF reg) %{
4066 constraint(ALLOC_IN_RC(stack_slots));
4067 op_cost(100);
4068 //match(RegF);
4069 format %{ "[$reg]" %}
4070 interface(MEMORY_INTER) %{
4071 base(0xE); // R_SP
4072 index(0x0);
4073 scale(0x0);
4074 disp($reg); // Stack Offset
4075 %}
4076 %}
4077 operand stackSlotD(sRegD reg) %{
4078 constraint(ALLOC_IN_RC(stack_slots));
4079 op_cost(100);
4080 //match(RegD);
4081 format %{ "[$reg]" %}
4082 interface(MEMORY_INTER) %{
4083 base(0xE); // R_SP
4084 index(0x0);
4085 scale(0x0);
4086 disp($reg); // Stack Offset
4087 %}
4088 %}
4089 operand stackSlotL(sRegL reg) %{
4090 constraint(ALLOC_IN_RC(stack_slots));
4091 op_cost(100);
4092 //match(RegL);
4093 format %{ "[$reg]" %}
4094 interface(MEMORY_INTER) %{
4095 base(0xE); // R_SP
4096 index(0x0);
4097 scale(0x0);
4098 disp($reg); // Stack Offset
4099 %}
4100 %}
4101
4102 // Operands for expressing Control Flow
4103 // NOTE: Label is a predefined operand which should not be redefined in
4104 // the AD file. It is generically handled within the ADLC.
4105
4106 //----------Conditional Branch Operands----------------------------------------
4107 // Comparison Op - This is the operation of the comparison, and is limited to
4108 // the following set of codes:
4109 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4110 //
4111 // Other attributes of the comparison, such as unsignedness, are specified
4112 // by the comparison instruction that sets a condition code flags register.
4113 // That result is represented by a flags operand whose subtype is appropriate
4114 // to the unsignedness (etc.) of the comparison.
4115 //
4116 // Later, the instruction which matches both the Comparison Op (a Bool) and
4117 // the flags (produced by the Cmp) specifies the coding of the comparison op
4118 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4119
4120 operand cmpOp() %{
4121 match(Bool);
4122
4123 format %{ "" %}
4124 interface(COND_INTER) %{
4125 equal(0x1);
4126 not_equal(0x9);
4127 less(0x3);
4128 greater_equal(0xB);
4129 less_equal(0x2);
4130 greater(0xA);
4131 overflow(0x7);
4132 no_overflow(0xF);
4133 %}
4134 %}
4135
4136 // Comparison Op, unsigned
4137 operand cmpOpU() %{
4138 match(Bool);
4139 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4140 n->as_Bool()->_test._test != BoolTest::no_overflow);
4141
4142 format %{ "u" %}
4143 interface(COND_INTER) %{
4144 equal(0x1);
4145 not_equal(0x9);
4146 less(0x5);
4147 greater_equal(0xD);
4148 less_equal(0x4);
4149 greater(0xC);
4150 overflow(0x7);
4151 no_overflow(0xF);
4152 %}
4153 %}
4154
4155 // Comparison Op, pointer (same as unsigned)
4156 operand cmpOpP() %{
4157 match(Bool);
4158 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4159 n->as_Bool()->_test._test != BoolTest::no_overflow);
4160
4161 format %{ "p" %}
4162 interface(COND_INTER) %{
4163 equal(0x1);
4164 not_equal(0x9);
4165 less(0x5);
4166 greater_equal(0xD);
4167 less_equal(0x4);
4168 greater(0xC);
4169 overflow(0x7);
4170 no_overflow(0xF);
4171 %}
4172 %}
4173
4174 // Comparison Op, branch-register encoding
4175 operand cmpOp_reg() %{
4176 match(Bool);
4177 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4178 n->as_Bool()->_test._test != BoolTest::no_overflow);
4179
4180 format %{ "" %}
4181 interface(COND_INTER) %{
4182 equal (0x1);
4183 not_equal (0x5);
4184 less (0x3);
4185 greater_equal(0x7);
4186 less_equal (0x2);
4187 greater (0x6);
4188 overflow(0x7); // not supported
4189 no_overflow(0xF); // not supported
4190 %}
4191 %}
4192
4193 // Comparison Code, floating, unordered same as less
4194 operand cmpOpF() %{
4195 match(Bool);
4196 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4197 n->as_Bool()->_test._test != BoolTest::no_overflow);
4198
4199 format %{ "fl" %}
4200 interface(COND_INTER) %{
4201 equal(0x9);
4202 not_equal(0x1);
4203 less(0x3);
4204 greater_equal(0xB);
4205 less_equal(0xE);
4206 greater(0x6);
4207
4208 overflow(0x7); // not supported
4209 no_overflow(0xF); // not supported
4210 %}
4211 %}
4212
4213 // Used by long compare
4214 operand cmpOp_commute() %{
4215 match(Bool);
4216 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4217 n->as_Bool()->_test._test != BoolTest::no_overflow);
4218
4219 format %{ "" %}
4220 interface(COND_INTER) %{
4221 equal(0x1);
4222 not_equal(0x9);
4223 less(0xA);
4224 greater_equal(0x2);
4225 less_equal(0xB);
4226 greater(0x3);
4227 overflow(0x7);
4228 no_overflow(0xF);
4229 %}
4230 %}
4231
4232 //----------OPERAND CLASSES----------------------------------------------------
4233 // Operand Classes are groups of operands that are used to simplify
4234 // instruction definitions by not requiring the AD writer to specify separate
4235 // instructions for every form of operand when the instruction accepts
4236 // multiple operand types with the same basic encoding and format. The classic
4237 // case of this is memory operands.
4238 opclass memory( indirect, indOffset13, indIndex );
4239 opclass indIndexMemory( indIndex );
4240
4241 //----------PIPELINE-----------------------------------------------------------
4242 pipeline %{
4243
4244 //----------ATTRIBUTES---------------------------------------------------------
4245 attributes %{
4246 fixed_size_instructions; // Fixed size instructions
4247 branch_has_delay_slot; // Branch has delay slot following
4248 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4249 instruction_unit_size = 4; // An instruction is 4 bytes long
4250 instruction_fetch_unit_size = 16; // The processor fetches one line
4251 instruction_fetch_units = 1; // of 16 bytes
4252
4253 // List of nop instructions
4254 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4255 %}
4256
4257 //----------RESOURCES----------------------------------------------------------
4258 // Resources are the functional units available to the machine
4259 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4260
4261 //----------PIPELINE DESCRIPTION-----------------------------------------------
4262 // Pipeline Description specifies the stages in the machine's pipeline
4263
4264 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4265
4266 //----------PIPELINE CLASSES---------------------------------------------------
4267 // Pipeline Classes describe the stages in which input and output are
4268 // referenced by the hardware pipeline.
4269
4270 // Integer ALU reg-reg operation
4271 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4272 single_instruction;
4273 dst : E(write);
4274 src1 : R(read);
4275 src2 : R(read);
4276 IALU : R;
4277 %}
4278
4279 // Integer ALU reg-reg long operation
4280 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4281 instruction_count(2);
4282 dst : E(write);
4283 src1 : R(read);
4284 src2 : R(read);
4285 IALU : R;
4286 IALU : R;
4287 %}
4288
4289 // Integer ALU reg-reg long dependent operation
4290 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4291 instruction_count(1); multiple_bundles;
4292 dst : E(write);
4293 src1 : R(read);
4294 src2 : R(read);
4295 cr : E(write);
4296 IALU : R(2);
4297 %}
4298
4299 // Integer ALU reg-imm operaion
4300 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4301 single_instruction;
4302 dst : E(write);
4303 src1 : R(read);
4304 IALU : R;
4305 %}
4306
4307 // Integer ALU reg-reg operation with condition code
4308 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4309 single_instruction;
4310 dst : E(write);
4311 cr : E(write);
4312 src1 : R(read);
4313 src2 : R(read);
4314 IALU : R;
4315 %}
4316
4317 // Integer ALU reg-imm operation with condition code
4318 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4319 single_instruction;
4320 dst : E(write);
4321 cr : E(write);
4322 src1 : R(read);
4323 IALU : R;
4324 %}
4325
4326 // Integer ALU zero-reg operation
4327 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4328 single_instruction;
4329 dst : E(write);
4330 src2 : R(read);
4331 IALU : R;
4332 %}
4333
4334 // Integer ALU zero-reg operation with condition code only
4335 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4336 single_instruction;
4337 cr : E(write);
4338 src : R(read);
4339 IALU : R;
4340 %}
4341
4342 // Integer ALU reg-reg operation with condition code only
4343 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4344 single_instruction;
4345 cr : E(write);
4346 src1 : R(read);
4347 src2 : R(read);
4348 IALU : R;
4349 %}
4350
4351 // Integer ALU reg-imm operation with condition code only
4352 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4353 single_instruction;
4354 cr : E(write);
4355 src1 : R(read);
4356 IALU : R;
4357 %}
4358
4359 // Integer ALU reg-reg-zero operation with condition code only
4360 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4361 single_instruction;
4362 cr : E(write);
4363 src1 : R(read);
4364 src2 : R(read);
4365 IALU : R;
4366 %}
4367
4368 // Integer ALU reg-imm-zero operation with condition code only
4369 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4370 single_instruction;
4371 cr : E(write);
4372 src1 : R(read);
4373 IALU : R;
4374 %}
4375
4376 // Integer ALU reg-reg operation with condition code, src1 modified
4377 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4378 single_instruction;
4379 cr : E(write);
4380 src1 : E(write);
4381 src1 : R(read);
4382 src2 : R(read);
4383 IALU : R;
4384 %}
4385
4386 // Integer ALU reg-imm operation with condition code, src1 modified
4387 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4388 single_instruction;
4389 cr : E(write);
4390 src1 : E(write);
4391 src1 : R(read);
4392 IALU : R;
4393 %}
4394
4395 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4396 multiple_bundles;
4397 dst : E(write)+4;
4398 cr : E(write);
4399 src1 : R(read);
4400 src2 : R(read);
4401 IALU : R(3);
4402 BR : R(2);
4403 %}
4404
4405 // Integer ALU operation
4406 pipe_class ialu_none(iRegI dst) %{
4407 single_instruction;
4408 dst : E(write);
4409 IALU : R;
4410 %}
4411
4412 // Integer ALU reg operation
4413 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4414 single_instruction; may_have_no_code;
4415 dst : E(write);
4416 src : R(read);
4417 IALU : R;
4418 %}
4419
4420 // Integer ALU reg conditional operation
4421 // This instruction has a 1 cycle stall, and cannot execute
4422 // in the same cycle as the instruction setting the condition
4423 // code. We kludge this by pretending to read the condition code
4424 // 1 cycle earlier, and by marking the functional units as busy
4425 // for 2 cycles with the result available 1 cycle later than
4426 // is really the case.
4427 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4428 single_instruction;
4429 op2_out : C(write);
4430 op1 : R(read);
4431 cr : R(read); // This is really E, with a 1 cycle stall
4432 BR : R(2);
4433 MS : R(2);
4434 %}
4435
4436 #ifdef _LP64
4437 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4438 instruction_count(1); multiple_bundles;
4439 dst : C(write)+1;
4440 src : R(read)+1;
4441 IALU : R(1);
4442 BR : E(2);
4443 MS : E(2);
4444 %}
4445 #endif
4446
4447 // Integer ALU reg operation
4448 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4449 single_instruction; may_have_no_code;
4450 dst : E(write);
4451 src : R(read);
4452 IALU : R;
4453 %}
4454 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4455 single_instruction; may_have_no_code;
4456 dst : E(write);
4457 src : R(read);
4458 IALU : R;
4459 %}
4460
4461 // Two integer ALU reg operations
4462 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4463 instruction_count(2);
4464 dst : E(write);
4465 src : R(read);
4466 A0 : R;
4467 A1 : R;
4468 %}
4469
4470 // Two integer ALU reg operations
4471 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4472 instruction_count(2); may_have_no_code;
4473 dst : E(write);
4474 src : R(read);
4475 A0 : R;
4476 A1 : R;
4477 %}
4478
4479 // Integer ALU imm operation
4480 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4481 single_instruction;
4482 dst : E(write);
4483 IALU : R;
4484 %}
4485
4486 // Integer ALU reg-reg with carry operation
4487 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4488 single_instruction;
4489 dst : E(write);
4490 src1 : R(read);
4491 src2 : R(read);
4492 IALU : R;
4493 %}
4494
4495 // Integer ALU cc operation
4496 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4497 single_instruction;
4498 dst : E(write);
4499 cc : R(read);
4500 IALU : R;
4501 %}
4502
4503 // Integer ALU cc / second IALU operation
4504 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4505 instruction_count(1); multiple_bundles;
4506 dst : E(write)+1;
4507 src : R(read);
4508 IALU : R;
4509 %}
4510
4511 // Integer ALU cc / second IALU operation
4512 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4513 instruction_count(1); multiple_bundles;
4514 dst : E(write)+1;
4515 p : R(read);
4516 q : R(read);
4517 IALU : R;
4518 %}
4519
4520 // Integer ALU hi-lo-reg operation
4521 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4522 instruction_count(1); multiple_bundles;
4523 dst : E(write)+1;
4524 IALU : R(2);
4525 %}
4526
4527 // Float ALU hi-lo-reg operation (with temp)
4528 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4529 instruction_count(1); multiple_bundles;
4530 dst : E(write)+1;
4531 IALU : R(2);
4532 %}
4533
4534 // Long Constant
4535 pipe_class loadConL( iRegL dst, immL src ) %{
4536 instruction_count(2); multiple_bundles;
4537 dst : E(write)+1;
4538 IALU : R(2);
4539 IALU : R(2);
4540 %}
4541
4542 // Pointer Constant
4543 pipe_class loadConP( iRegP dst, immP src ) %{
4544 instruction_count(0); multiple_bundles;
4545 fixed_latency(6);
4546 %}
4547
4548 // Polling Address
4549 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4550 #ifdef _LP64
4551 instruction_count(0); multiple_bundles;
4552 fixed_latency(6);
4553 #else
4554 dst : E(write);
4555 IALU : R;
4556 #endif
4557 %}
4558
4559 // Long Constant small
4560 pipe_class loadConLlo( iRegL dst, immL src ) %{
4561 instruction_count(2);
4562 dst : E(write);
4563 IALU : R;
4564 IALU : R;
4565 %}
4566
4567 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4568 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4569 instruction_count(1); multiple_bundles;
4570 src : R(read);
4571 dst : M(write)+1;
4572 IALU : R;
4573 MS : E;
4574 %}
4575
4576 // Integer ALU nop operation
4577 pipe_class ialu_nop() %{
4578 single_instruction;
4579 IALU : R;
4580 %}
4581
4582 // Integer ALU nop operation
4583 pipe_class ialu_nop_A0() %{
4584 single_instruction;
4585 A0 : R;
4586 %}
4587
4588 // Integer ALU nop operation
4589 pipe_class ialu_nop_A1() %{
4590 single_instruction;
4591 A1 : R;
4592 %}
4593
4594 // Integer Multiply reg-reg operation
4595 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4596 single_instruction;
4597 dst : E(write);
4598 src1 : R(read);
4599 src2 : R(read);
4600 MS : R(5);
4601 %}
4602
4603 // Integer Multiply reg-imm operation
4604 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4605 single_instruction;
4606 dst : E(write);
4607 src1 : R(read);
4608 MS : R(5);
4609 %}
4610
4611 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4612 single_instruction;
4613 dst : E(write)+4;
4614 src1 : R(read);
4615 src2 : R(read);
4616 MS : R(6);
4617 %}
4618
4619 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4620 single_instruction;
4621 dst : E(write)+4;
4622 src1 : R(read);
4623 MS : R(6);
4624 %}
4625
4626 // Integer Divide reg-reg
4627 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4628 instruction_count(1); multiple_bundles;
4629 dst : E(write);
4630 temp : E(write);
4631 src1 : R(read);
4632 src2 : R(read);
4633 temp : R(read);
4634 MS : R(38);
4635 %}
4636
4637 // Integer Divide reg-imm
4638 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4639 instruction_count(1); multiple_bundles;
4640 dst : E(write);
4641 temp : E(write);
4642 src1 : R(read);
4643 temp : R(read);
4644 MS : R(38);
4645 %}
4646
4647 // Long Divide
4648 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4649 dst : E(write)+71;
4650 src1 : R(read);
4651 src2 : R(read)+1;
4652 MS : R(70);
4653 %}
4654
4655 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4656 dst : E(write)+71;
4657 src1 : R(read);
4658 MS : R(70);
4659 %}
4660
4661 // Floating Point Add Float
4662 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4663 single_instruction;
4664 dst : X(write);
4665 src1 : E(read);
4666 src2 : E(read);
4667 FA : R;
4668 %}
4669
4670 // Floating Point Add Double
4671 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4672 single_instruction;
4673 dst : X(write);
4674 src1 : E(read);
4675 src2 : E(read);
4676 FA : R;
4677 %}
4678
4679 // Floating Point Conditional Move based on integer flags
4680 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4681 single_instruction;
4682 dst : X(write);
4683 src : E(read);
4684 cr : R(read);
4685 FA : R(2);
4686 BR : R(2);
4687 %}
4688
4689 // Floating Point Conditional Move based on integer flags
4690 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4691 single_instruction;
4692 dst : X(write);
4693 src : E(read);
4694 cr : R(read);
4695 FA : R(2);
4696 BR : R(2);
4697 %}
4698
4699 // Floating Point Multiply Float
4700 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4701 single_instruction;
4702 dst : X(write);
4703 src1 : E(read);
4704 src2 : E(read);
4705 FM : R;
4706 %}
4707
4708 // Floating Point Multiply Double
4709 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4710 single_instruction;
4711 dst : X(write);
4712 src1 : E(read);
4713 src2 : E(read);
4714 FM : R;
4715 %}
4716
4717 // Floating Point Divide Float
4718 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4719 single_instruction;
4720 dst : X(write);
4721 src1 : E(read);
4722 src2 : E(read);
4723 FM : R;
4724 FDIV : C(14);
4725 %}
4726
4727 // Floating Point Divide Double
4728 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4729 single_instruction;
4730 dst : X(write);
4731 src1 : E(read);
4732 src2 : E(read);
4733 FM : R;
4734 FDIV : C(17);
4735 %}
4736
4737 // Floating Point Move/Negate/Abs Float
4738 pipe_class faddF_reg(regF dst, regF src) %{
4739 single_instruction;
4740 dst : W(write);
4741 src : E(read);
4742 FA : R(1);
4743 %}
4744
4745 // Floating Point Move/Negate/Abs Double
4746 pipe_class faddD_reg(regD dst, regD src) %{
4747 single_instruction;
4748 dst : W(write);
4749 src : E(read);
4750 FA : R;
4751 %}
4752
4753 // Floating Point Convert F->D
4754 pipe_class fcvtF2D(regD dst, regF src) %{
4755 single_instruction;
4756 dst : X(write);
4757 src : E(read);
4758 FA : R;
4759 %}
4760
4761 // Floating Point Convert I->D
4762 pipe_class fcvtI2D(regD dst, regF src) %{
4763 single_instruction;
4764 dst : X(write);
4765 src : E(read);
4766 FA : R;
4767 %}
4768
4769 // Floating Point Convert LHi->D
4770 pipe_class fcvtLHi2D(regD dst, regD src) %{
4771 single_instruction;
4772 dst : X(write);
4773 src : E(read);
4774 FA : R;
4775 %}
4776
4777 // Floating Point Convert L->D
4778 pipe_class fcvtL2D(regD dst, regF src) %{
4779 single_instruction;
4780 dst : X(write);
4781 src : E(read);
4782 FA : R;
4783 %}
4784
4785 // Floating Point Convert L->F
4786 pipe_class fcvtL2F(regD dst, regF src) %{
4787 single_instruction;
4788 dst : X(write);
4789 src : E(read);
4790 FA : R;
4791 %}
4792
4793 // Floating Point Convert D->F
4794 pipe_class fcvtD2F(regD dst, regF src) %{
4795 single_instruction;
4796 dst : X(write);
4797 src : E(read);
4798 FA : R;
4799 %}
4800
4801 // Floating Point Convert I->L
4802 pipe_class fcvtI2L(regD dst, regF src) %{
4803 single_instruction;
4804 dst : X(write);
4805 src : E(read);
4806 FA : R;
4807 %}
4808
4809 // Floating Point Convert D->F
4810 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4811 instruction_count(1); multiple_bundles;
4812 dst : X(write)+6;
4813 src : E(read);
4814 FA : R;
4815 %}
4816
4817 // Floating Point Convert D->L
4818 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4819 instruction_count(1); multiple_bundles;
4820 dst : X(write)+6;
4821 src : E(read);
4822 FA : R;
4823 %}
4824
4825 // Floating Point Convert F->I
4826 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4827 instruction_count(1); multiple_bundles;
4828 dst : X(write)+6;
4829 src : E(read);
4830 FA : R;
4831 %}
4832
4833 // Floating Point Convert F->L
4834 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4835 instruction_count(1); multiple_bundles;
4836 dst : X(write)+6;
4837 src : E(read);
4838 FA : R;
4839 %}
4840
4841 // Floating Point Convert I->F
4842 pipe_class fcvtI2F(regF dst, regF src) %{
4843 single_instruction;
4844 dst : X(write);
4845 src : E(read);
4846 FA : R;
4847 %}
4848
4849 // Floating Point Compare
4850 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4851 single_instruction;
4852 cr : X(write);
4853 src1 : E(read);
4854 src2 : E(read);
4855 FA : R;
4856 %}
4857
4858 // Floating Point Compare
4859 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4860 single_instruction;
4861 cr : X(write);
4862 src1 : E(read);
4863 src2 : E(read);
4864 FA : R;
4865 %}
4866
4867 // Floating Add Nop
4868 pipe_class fadd_nop() %{
4869 single_instruction;
4870 FA : R;
4871 %}
4872
4873 // Integer Store to Memory
4874 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4875 single_instruction;
4876 mem : R(read);
4877 src : C(read);
4878 MS : R;
4879 %}
4880
4881 // Integer Store to Memory
4882 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4883 single_instruction;
4884 mem : R(read);
4885 src : C(read);
4886 MS : R;
4887 %}
4888
4889 // Integer Store Zero to Memory
4890 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4891 single_instruction;
4892 mem : R(read);
4893 MS : R;
4894 %}
4895
4896 // Special Stack Slot Store
4897 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4898 single_instruction;
4899 stkSlot : R(read);
4900 src : C(read);
4901 MS : R;
4902 %}
4903
4904 // Special Stack Slot Store
4905 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4906 instruction_count(2); multiple_bundles;
4907 stkSlot : R(read);
4908 src : C(read);
4909 MS : R(2);
4910 %}
4911
4912 // Float Store
4913 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4914 single_instruction;
4915 mem : R(read);
4916 src : C(read);
4917 MS : R;
4918 %}
4919
4920 // Float Store
4921 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4922 single_instruction;
4923 mem : R(read);
4924 MS : R;
4925 %}
4926
4927 // Double Store
4928 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
4929 instruction_count(1);
4930 mem : R(read);
4931 src : C(read);
4932 MS : R;
4933 %}
4934
4935 // Double Store
4936 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
4937 single_instruction;
4938 mem : R(read);
4939 MS : R;
4940 %}
4941
4942 // Special Stack Slot Float Store
4943 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
4944 single_instruction;
4945 stkSlot : R(read);
4946 src : C(read);
4947 MS : R;
4948 %}
4949
4950 // Special Stack Slot Double Store
4951 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
4952 single_instruction;
4953 stkSlot : R(read);
4954 src : C(read);
4955 MS : R;
4956 %}
4957
4958 // Integer Load (when sign bit propagation not needed)
4959 pipe_class iload_mem(iRegI dst, memory mem) %{
4960 single_instruction;
4961 mem : R(read);
4962 dst : C(write);
4963 MS : R;
4964 %}
4965
4966 // Integer Load from stack operand
4967 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
4968 single_instruction;
4969 mem : R(read);
4970 dst : C(write);
4971 MS : R;
4972 %}
4973
4974 // Integer Load (when sign bit propagation or masking is needed)
4975 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
4976 single_instruction;
4977 mem : R(read);
4978 dst : M(write);
4979 MS : R;
4980 %}
4981
4982 // Float Load
4983 pipe_class floadF_mem(regF dst, memory mem) %{
4984 single_instruction;
4985 mem : R(read);
4986 dst : M(write);
4987 MS : R;
4988 %}
4989
4990 // Float Load
4991 pipe_class floadD_mem(regD dst, memory mem) %{
4992 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
4993 mem : R(read);
4994 dst : M(write);
4995 MS : R;
4996 %}
4997
4998 // Float Load
4999 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5000 single_instruction;
5001 stkSlot : R(read);
5002 dst : M(write);
5003 MS : R;
5004 %}
5005
5006 // Float Load
5007 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5008 single_instruction;
5009 stkSlot : R(read);
5010 dst : M(write);
5011 MS : R;
5012 %}
5013
5014 // Memory Nop
5015 pipe_class mem_nop() %{
5016 single_instruction;
5017 MS : R;
5018 %}
5019
5020 pipe_class sethi(iRegP dst, immI src) %{
5021 single_instruction;
5022 dst : E(write);
5023 IALU : R;
5024 %}
5025
5026 pipe_class loadPollP(iRegP poll) %{
5027 single_instruction;
5028 poll : R(read);
5029 MS : R;
5030 %}
5031
5032 pipe_class br(Universe br, label labl) %{
5033 single_instruction_with_delay_slot;
5034 BR : R;
5035 %}
5036
5037 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5038 single_instruction_with_delay_slot;
5039 cr : E(read);
5040 BR : R;
5041 %}
5042
5043 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5044 single_instruction_with_delay_slot;
5045 op1 : E(read);
5046 BR : R;
5047 MS : R;
5048 %}
5049
5050 // Compare and branch
5051 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5052 instruction_count(2); has_delay_slot;
5053 cr : E(write);
5054 src1 : R(read);
5055 src2 : R(read);
5056 IALU : R;
5057 BR : R;
5058 %}
5059
5060 // Compare and branch
5061 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5062 instruction_count(2); has_delay_slot;
5063 cr : E(write);
5064 src1 : R(read);
5065 IALU : R;
5066 BR : R;
5067 %}
5068
5069 // Compare and branch using cbcond
5070 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5071 single_instruction;
5072 src1 : E(read);
5073 src2 : E(read);
5074 IALU : R;
5075 BR : R;
5076 %}
5077
5078 // Compare and branch using cbcond
5079 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5080 single_instruction;
5081 src1 : E(read);
5082 IALU : R;
5083 BR : R;
5084 %}
5085
5086 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5087 single_instruction_with_delay_slot;
5088 cr : E(read);
5089 BR : R;
5090 %}
5091
5092 pipe_class br_nop() %{
5093 single_instruction;
5094 BR : R;
5095 %}
5096
5097 pipe_class simple_call(method meth) %{
5098 instruction_count(2); multiple_bundles; force_serialization;
5099 fixed_latency(100);
5100 BR : R(1);
5101 MS : R(1);
5102 A0 : R(1);
5103 %}
5104
5105 pipe_class compiled_call(method meth) %{
5106 instruction_count(1); multiple_bundles; force_serialization;
5107 fixed_latency(100);
5108 MS : R(1);
5109 %}
5110
5111 pipe_class call(method meth) %{
5112 instruction_count(0); multiple_bundles; force_serialization;
5113 fixed_latency(100);
5114 %}
5115
5116 pipe_class tail_call(Universe ignore, label labl) %{
5117 single_instruction; has_delay_slot;
5118 fixed_latency(100);
5119 BR : R(1);
5120 MS : R(1);
5121 %}
5122
5123 pipe_class ret(Universe ignore) %{
5124 single_instruction; has_delay_slot;
5125 BR : R(1);
5126 MS : R(1);
5127 %}
5128
5129 pipe_class ret_poll(g3RegP poll) %{
5130 instruction_count(3); has_delay_slot;
5131 poll : E(read);
5132 MS : R;
5133 %}
5134
5135 // The real do-nothing guy
5136 pipe_class empty( ) %{
5137 instruction_count(0);
5138 %}
5139
5140 pipe_class long_memory_op() %{
5141 instruction_count(0); multiple_bundles; force_serialization;
5142 fixed_latency(25);
5143 MS : R(1);
5144 %}
5145
5146 // Check-cast
5147 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5148 array : R(read);
5149 match : R(read);
5150 IALU : R(2);
5151 BR : R(2);
5152 MS : R;
5153 %}
5154
5155 // Convert FPU flags into +1,0,-1
5156 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5157 src1 : E(read);
5158 src2 : E(read);
5159 dst : E(write);
5160 FA : R;
5161 MS : R(2);
5162 BR : R(2);
5163 %}
5164
5165 // Compare for p < q, and conditionally add y
5166 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5167 p : E(read);
5168 q : E(read);
5169 y : E(read);
5170 IALU : R(3)
5171 %}
5172
5173 // Perform a compare, then move conditionally in a branch delay slot.
5174 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5175 src2 : E(read);
5176 srcdst : E(read);
5177 IALU : R;
5178 BR : R;
5179 %}
5180
5181 // Define the class for the Nop node
5182 define %{
5183 MachNop = ialu_nop;
5184 %}
5185
5186 %}
5187
5188 //----------INSTRUCTIONS-------------------------------------------------------
5189
5190 //------------Special Stack Slot instructions - no match rules-----------------
5191 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5192 // No match rule to avoid chain rule match.
5193 effect(DEF dst, USE src);
5194 ins_cost(MEMORY_REF_COST);
5195 size(4);
5196 format %{ "LDF $src,$dst\t! stkI to regF" %}
5197 opcode(Assembler::ldf_op3);
5198 ins_encode(simple_form3_mem_reg(src, dst));
5199 ins_pipe(floadF_stk);
5200 %}
5201
5202 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5203 // No match rule to avoid chain rule match.
5204 effect(DEF dst, USE src);
5205 ins_cost(MEMORY_REF_COST);
5206 size(4);
5207 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5208 opcode(Assembler::lddf_op3);
5209 ins_encode(simple_form3_mem_reg(src, dst));
5210 ins_pipe(floadD_stk);
5211 %}
5212
5213 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5214 // No match rule to avoid chain rule match.
5215 effect(DEF dst, USE src);
5216 ins_cost(MEMORY_REF_COST);
5217 size(4);
5218 format %{ "STF $src,$dst\t! regF to stkI" %}
5219 opcode(Assembler::stf_op3);
5220 ins_encode(simple_form3_mem_reg(dst, src));
5221 ins_pipe(fstoreF_stk_reg);
5222 %}
5223
5224 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5225 // No match rule to avoid chain rule match.
5226 effect(DEF dst, USE src);
5227 ins_cost(MEMORY_REF_COST);
5228 size(4);
5229 format %{ "STDF $src,$dst\t! regD to stkL" %}
5230 opcode(Assembler::stdf_op3);
5231 ins_encode(simple_form3_mem_reg(dst, src));
5232 ins_pipe(fstoreD_stk_reg);
5233 %}
5234
5235 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5236 effect(DEF dst, USE src);
5237 ins_cost(MEMORY_REF_COST*2);
5238 size(8);
5239 format %{ "STW $src,$dst.hi\t! long\n\t"
5240 "STW R_G0,$dst.lo" %}
5241 opcode(Assembler::stw_op3);
5242 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5243 ins_pipe(lstoreI_stk_reg);
5244 %}
5245
5246 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5247 // No match rule to avoid chain rule match.
5248 effect(DEF dst, USE src);
5249 ins_cost(MEMORY_REF_COST);
5250 size(4);
5251 format %{ "STX $src,$dst\t! regL to stkD" %}
5252 opcode(Assembler::stx_op3);
5253 ins_encode(simple_form3_mem_reg( dst, src ) );
5254 ins_pipe(istore_stk_reg);
5255 %}
5256
5257 //---------- Chain stack slots between similar types --------
5258
5259 // Load integer from stack slot
5260 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5261 match(Set dst src);
5262 ins_cost(MEMORY_REF_COST);
5263
5264 size(4);
5265 format %{ "LDUW $src,$dst\t!stk" %}
5266 opcode(Assembler::lduw_op3);
5267 ins_encode(simple_form3_mem_reg( src, dst ) );
5268 ins_pipe(iload_mem);
5269 %}
5270
5271 // Store integer to stack slot
5272 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5273 match(Set dst src);
5274 ins_cost(MEMORY_REF_COST);
5275
5276 size(4);
5277 format %{ "STW $src,$dst\t!stk" %}
5278 opcode(Assembler::stw_op3);
5279 ins_encode(simple_form3_mem_reg( dst, src ) );
5280 ins_pipe(istore_mem_reg);
5281 %}
5282
5283 // Load long from stack slot
5284 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5285 match(Set dst src);
5286
5287 ins_cost(MEMORY_REF_COST);
5288 size(4);
5289 format %{ "LDX $src,$dst\t! long" %}
5290 opcode(Assembler::ldx_op3);
5291 ins_encode(simple_form3_mem_reg( src, dst ) );
5292 ins_pipe(iload_mem);
5293 %}
5294
5295 // Store long to stack slot
5296 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5297 match(Set dst src);
5298
5299 ins_cost(MEMORY_REF_COST);
5300 size(4);
5301 format %{ "STX $src,$dst\t! long" %}
5302 opcode(Assembler::stx_op3);
5303 ins_encode(simple_form3_mem_reg( dst, src ) );
5304 ins_pipe(istore_mem_reg);
5305 %}
5306
5307 #ifdef _LP64
5308 // Load pointer from stack slot, 64-bit encoding
5309 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5310 match(Set dst src);
5311 ins_cost(MEMORY_REF_COST);
5312 size(4);
5313 format %{ "LDX $src,$dst\t!ptr" %}
5314 opcode(Assembler::ldx_op3);
5315 ins_encode(simple_form3_mem_reg( src, dst ) );
5316 ins_pipe(iload_mem);
5317 %}
5318
5319 // Store pointer to stack slot
5320 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5321 match(Set dst src);
5322 ins_cost(MEMORY_REF_COST);
5323 size(4);
5324 format %{ "STX $src,$dst\t!ptr" %}
5325 opcode(Assembler::stx_op3);
5326 ins_encode(simple_form3_mem_reg( dst, src ) );
5327 ins_pipe(istore_mem_reg);
5328 %}
5329 #else // _LP64
5330 // Load pointer from stack slot, 32-bit encoding
5331 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5332 match(Set dst src);
5333 ins_cost(MEMORY_REF_COST);
5334 format %{ "LDUW $src,$dst\t!ptr" %}
5335 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5336 ins_encode(simple_form3_mem_reg( src, dst ) );
5337 ins_pipe(iload_mem);
5338 %}
5339
5340 // Store pointer to stack slot
5341 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5342 match(Set dst src);
5343 ins_cost(MEMORY_REF_COST);
5344 format %{ "STW $src,$dst\t!ptr" %}
5345 opcode(Assembler::stw_op3, Assembler::ldst_op);
5346 ins_encode(simple_form3_mem_reg( dst, src ) );
5347 ins_pipe(istore_mem_reg);
5348 %}
5349 #endif // _LP64
5350
5351 //------------Special Nop instructions for bundling - no match rules-----------
5352 // Nop using the A0 functional unit
5353 instruct Nop_A0() %{
5354 ins_cost(0);
5355
5356 format %{ "NOP ! Alu Pipeline" %}
5357 opcode(Assembler::or_op3, Assembler::arith_op);
5358 ins_encode( form2_nop() );
5359 ins_pipe(ialu_nop_A0);
5360 %}
5361
5362 // Nop using the A1 functional unit
5363 instruct Nop_A1( ) %{
5364 ins_cost(0);
5365
5366 format %{ "NOP ! Alu Pipeline" %}
5367 opcode(Assembler::or_op3, Assembler::arith_op);
5368 ins_encode( form2_nop() );
5369 ins_pipe(ialu_nop_A1);
5370 %}
5371
5372 // Nop using the memory functional unit
5373 instruct Nop_MS( ) %{
5374 ins_cost(0);
5375
5376 format %{ "NOP ! Memory Pipeline" %}
5377 ins_encode( emit_mem_nop );
5378 ins_pipe(mem_nop);
5379 %}
5380
5381 // Nop using the floating add functional unit
5382 instruct Nop_FA( ) %{
5383 ins_cost(0);
5384
5385 format %{ "NOP ! Floating Add Pipeline" %}
5386 ins_encode( emit_fadd_nop );
5387 ins_pipe(fadd_nop);
5388 %}
5389
5390 // Nop using the branch functional unit
5391 instruct Nop_BR( ) %{
5392 ins_cost(0);
5393
5394 format %{ "NOP ! Branch Pipeline" %}
5395 ins_encode( emit_br_nop );
5396 ins_pipe(br_nop);
5397 %}
5398
5399 //----------Load/Store/Move Instructions---------------------------------------
5400 //----------Load Instructions--------------------------------------------------
5401 // Load Byte (8bit signed)
5402 instruct loadB(iRegI dst, memory mem) %{
5403 match(Set dst (LoadB mem));
5404 ins_cost(MEMORY_REF_COST);
5405
5406 size(4);
5407 format %{ "LDSB $mem,$dst\t! byte" %}
5408 ins_encode %{
5409 __ ldsb($mem$$Address, $dst$$Register);
5410 %}
5411 ins_pipe(iload_mask_mem);
5412 %}
5413
5414 // Load Byte (8bit signed) into a Long Register
5415 instruct loadB2L(iRegL dst, memory mem) %{
5416 match(Set dst (ConvI2L (LoadB mem)));
5417 ins_cost(MEMORY_REF_COST);
5418
5419 size(4);
5420 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5421 ins_encode %{
5422 __ ldsb($mem$$Address, $dst$$Register);
5423 %}
5424 ins_pipe(iload_mask_mem);
5425 %}
5426
5427 // Load Unsigned Byte (8bit UNsigned) into an int reg
5428 instruct loadUB(iRegI dst, memory mem) %{
5429 match(Set dst (LoadUB mem));
5430 ins_cost(MEMORY_REF_COST);
5431
5432 size(4);
5433 format %{ "LDUB $mem,$dst\t! ubyte" %}
5434 ins_encode %{
5435 __ ldub($mem$$Address, $dst$$Register);
5436 %}
5437 ins_pipe(iload_mem);
5438 %}
5439
5440 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5441 instruct loadUB2L(iRegL dst, memory mem) %{
5442 match(Set dst (ConvI2L (LoadUB mem)));
5443 ins_cost(MEMORY_REF_COST);
5444
5445 size(4);
5446 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5447 ins_encode %{
5448 __ ldub($mem$$Address, $dst$$Register);
5449 %}
5450 ins_pipe(iload_mem);
5451 %}
5452
5453 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5454 instruct loadUB2L_immI(iRegL dst, memory mem, immI mask) %{
5455 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5456 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5457
5458 size(2*4);
5459 format %{ "LDUB $mem,$dst\t# ubyte & 32-bit mask -> long\n\t"
5460 "AND $dst,right_n_bits($mask, 8),$dst" %}
5461 ins_encode %{
5462 __ ldub($mem$$Address, $dst$$Register);
5463 __ and3($dst$$Register, $mask$$constant & right_n_bits(8), $dst$$Register);
5464 %}
5465 ins_pipe(iload_mem);
5466 %}
5467
5468 // Load Short (16bit signed)
5469 instruct loadS(iRegI dst, memory mem) %{
5470 match(Set dst (LoadS mem));
5471 ins_cost(MEMORY_REF_COST);
5472
5473 size(4);
5474 format %{ "LDSH $mem,$dst\t! short" %}
5475 ins_encode %{
5476 __ ldsh($mem$$Address, $dst$$Register);
5477 %}
5478 ins_pipe(iload_mask_mem);
5479 %}
5480
5481 // Load Short (16 bit signed) to Byte (8 bit signed)
5482 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5483 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5484 ins_cost(MEMORY_REF_COST);
5485
5486 size(4);
5487
5488 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5489 ins_encode %{
5490 __ ldsb($mem$$Address, $dst$$Register, 1);
5491 %}
5492 ins_pipe(iload_mask_mem);
5493 %}
5494
5495 // Load Short (16bit signed) into a Long Register
5496 instruct loadS2L(iRegL dst, memory mem) %{
5497 match(Set dst (ConvI2L (LoadS mem)));
5498 ins_cost(MEMORY_REF_COST);
5499
5500 size(4);
5501 format %{ "LDSH $mem,$dst\t! short -> long" %}
5502 ins_encode %{
5503 __ ldsh($mem$$Address, $dst$$Register);
5504 %}
5505 ins_pipe(iload_mask_mem);
5506 %}
5507
5508 // Load Unsigned Short/Char (16bit UNsigned)
5509 instruct loadUS(iRegI dst, memory mem) %{
5510 match(Set dst (LoadUS mem));
5511 ins_cost(MEMORY_REF_COST);
5512
5513 size(4);
5514 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5515 ins_encode %{
5516 __ lduh($mem$$Address, $dst$$Register);
5517 %}
5518 ins_pipe(iload_mem);
5519 %}
5520
5521 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5522 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5523 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5524 ins_cost(MEMORY_REF_COST);
5525
5526 size(4);
5527 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5528 ins_encode %{
5529 __ ldsb($mem$$Address, $dst$$Register, 1);
5530 %}
5531 ins_pipe(iload_mask_mem);
5532 %}
5533
5534 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5535 instruct loadUS2L(iRegL dst, memory mem) %{
5536 match(Set dst (ConvI2L (LoadUS mem)));
5537 ins_cost(MEMORY_REF_COST);
5538
5539 size(4);
5540 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5541 ins_encode %{
5542 __ lduh($mem$$Address, $dst$$Register);
5543 %}
5544 ins_pipe(iload_mem);
5545 %}
5546
5547 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5548 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5549 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5550 ins_cost(MEMORY_REF_COST);
5551
5552 size(4);
5553 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5554 ins_encode %{
5555 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5556 %}
5557 ins_pipe(iload_mem);
5558 %}
5559
5560 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5561 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5562 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5563 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5564
5565 size(2*4);
5566 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5567 "AND $dst,$mask,$dst" %}
5568 ins_encode %{
5569 Register Rdst = $dst$$Register;
5570 __ lduh($mem$$Address, Rdst);
5571 __ and3(Rdst, $mask$$constant, Rdst);
5572 %}
5573 ins_pipe(iload_mem);
5574 %}
5575
5576 // Load Unsigned Short/Char (16bit UNsigned) with a 32-bit mask into a Long Register
5577 instruct loadUS2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5578 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5579 effect(TEMP dst, TEMP tmp);
5580 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5581
5582 format %{ "LDUH $mem,$dst\t! ushort/char & 32-bit mask -> long\n\t"
5583 "SET right_n_bits($mask, 16),$tmp\n\t"
5584 "AND $dst,$tmp,$dst" %}
5585 ins_encode %{
5586 Register Rdst = $dst$$Register;
5587 Register Rtmp = $tmp$$Register;
5588 __ lduh($mem$$Address, Rdst);
5589 __ set($mask$$constant & right_n_bits(16), Rtmp);
5590 __ and3(Rdst, Rtmp, Rdst);
5591 %}
5592 ins_pipe(iload_mem);
5593 %}
5594
5595 // Load Integer
5596 instruct loadI(iRegI dst, memory mem) %{
5597 match(Set dst (LoadI mem));
5598 ins_cost(MEMORY_REF_COST);
5599
5600 size(4);
5601 format %{ "LDUW $mem,$dst\t! int" %}
5602 ins_encode %{
5603 __ lduw($mem$$Address, $dst$$Register);
5604 %}
5605 ins_pipe(iload_mem);
5606 %}
5607
5608 // Load Integer to Byte (8 bit signed)
5609 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5610 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5611 ins_cost(MEMORY_REF_COST);
5612
5613 size(4);
5614
5615 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5616 ins_encode %{
5617 __ ldsb($mem$$Address, $dst$$Register, 3);
5618 %}
5619 ins_pipe(iload_mask_mem);
5620 %}
5621
5622 // Load Integer to Unsigned Byte (8 bit UNsigned)
5623 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5624 match(Set dst (AndI (LoadI mem) mask));
5625 ins_cost(MEMORY_REF_COST);
5626
5627 size(4);
5628
5629 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5630 ins_encode %{
5631 __ ldub($mem$$Address, $dst$$Register, 3);
5632 %}
5633 ins_pipe(iload_mask_mem);
5634 %}
5635
5636 // Load Integer to Short (16 bit signed)
5637 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5638 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5639 ins_cost(MEMORY_REF_COST);
5640
5641 size(4);
5642
5643 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5644 ins_encode %{
5645 __ ldsh($mem$$Address, $dst$$Register, 2);
5646 %}
5647 ins_pipe(iload_mask_mem);
5648 %}
5649
5650 // Load Integer to Unsigned Short (16 bit UNsigned)
5651 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5652 match(Set dst (AndI (LoadI mem) mask));
5653 ins_cost(MEMORY_REF_COST);
5654
5655 size(4);
5656
5657 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5658 ins_encode %{
5659 __ lduh($mem$$Address, $dst$$Register, 2);
5660 %}
5661 ins_pipe(iload_mask_mem);
5662 %}
5663
5664 // Load Integer into a Long Register
5665 instruct loadI2L(iRegL dst, memory mem) %{
5666 match(Set dst (ConvI2L (LoadI mem)));
5667 ins_cost(MEMORY_REF_COST);
5668
5669 size(4);
5670 format %{ "LDSW $mem,$dst\t! int -> long" %}
5671 ins_encode %{
5672 __ ldsw($mem$$Address, $dst$$Register);
5673 %}
5674 ins_pipe(iload_mask_mem);
5675 %}
5676
5677 // Load Integer with mask 0xFF into a Long Register
5678 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5679 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5680 ins_cost(MEMORY_REF_COST);
5681
5682 size(4);
5683 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5684 ins_encode %{
5685 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5686 %}
5687 ins_pipe(iload_mem);
5688 %}
5689
5690 // Load Integer with mask 0xFFFF into a Long Register
5691 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5692 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5693 ins_cost(MEMORY_REF_COST);
5694
5695 size(4);
5696 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5697 ins_encode %{
5698 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5699 %}
5700 ins_pipe(iload_mem);
5701 %}
5702
5703 // Load Integer with a 12-bit mask into a Long Register
5704 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5705 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5706 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5707
5708 size(2*4);
5709 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t"
5710 "AND $dst,$mask,$dst" %}
5711 ins_encode %{
5712 Register Rdst = $dst$$Register;
5713 __ lduw($mem$$Address, Rdst);
5714 __ and3(Rdst, $mask$$constant, Rdst);
5715 %}
5716 ins_pipe(iload_mem);
5717 %}
5718
5719 // Load Integer with a 31-bit mask into a Long Register
5720 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5721 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5722 effect(TEMP dst, TEMP tmp);
5723 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5724
5725 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t"
5726 "SET $mask,$tmp\n\t"
5727 "AND $dst,$tmp,$dst" %}
5728 ins_encode %{
5729 Register Rdst = $dst$$Register;
5730 Register Rtmp = $tmp$$Register;
5731 __ lduw($mem$$Address, Rdst);
5732 __ set($mask$$constant, Rtmp);
5733 __ and3(Rdst, Rtmp, Rdst);
5734 %}
5735 ins_pipe(iload_mem);
5736 %}
5737
5738 // Load Unsigned Integer into a Long Register
5739 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5740 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5741 ins_cost(MEMORY_REF_COST);
5742
5743 size(4);
5744 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5745 ins_encode %{
5746 __ lduw($mem$$Address, $dst$$Register);
5747 %}
5748 ins_pipe(iload_mem);
5749 %}
5750
5751 // Load Long - aligned
5752 instruct loadL(iRegL dst, memory mem ) %{
5753 match(Set dst (LoadL mem));
5754 ins_cost(MEMORY_REF_COST);
5755
5756 size(4);
5757 format %{ "LDX $mem,$dst\t! long" %}
5758 ins_encode %{
5759 __ ldx($mem$$Address, $dst$$Register);
5760 %}
5761 ins_pipe(iload_mem);
5762 %}
5763
5764 // Load Long - UNaligned
5765 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5766 match(Set dst (LoadL_unaligned mem));
5767 effect(KILL tmp);
5768 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5769 size(16);
5770 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5771 "\tLDUW $mem ,$dst\n"
5772 "\tSLLX #32, $dst, $dst\n"
5773 "\tOR $dst, R_O7, $dst" %}
5774 opcode(Assembler::lduw_op3);
5775 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5776 ins_pipe(iload_mem);
5777 %}
5778
5779 // Load Range
5780 instruct loadRange(iRegI dst, memory mem) %{
5781 match(Set dst (LoadRange mem));
5782 ins_cost(MEMORY_REF_COST);
5783
5784 size(4);
5785 format %{ "LDUW $mem,$dst\t! range" %}
5786 opcode(Assembler::lduw_op3);
5787 ins_encode(simple_form3_mem_reg( mem, dst ) );
5788 ins_pipe(iload_mem);
5789 %}
5790
5791 // Load Integer into %f register (for fitos/fitod)
5792 instruct loadI_freg(regF dst, memory mem) %{
5793 match(Set dst (LoadI mem));
5794 ins_cost(MEMORY_REF_COST);
5795 size(4);
5796
5797 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5798 opcode(Assembler::ldf_op3);
5799 ins_encode(simple_form3_mem_reg( mem, dst ) );
5800 ins_pipe(floadF_mem);
5801 %}
5802
5803 // Load Pointer
5804 instruct loadP(iRegP dst, memory mem) %{
5805 match(Set dst (LoadP mem));
5806 ins_cost(MEMORY_REF_COST);
5807 size(4);
5808
5809 #ifndef _LP64
5810 format %{ "LDUW $mem,$dst\t! ptr" %}
5811 ins_encode %{
5812 __ lduw($mem$$Address, $dst$$Register);
5813 %}
5814 #else
5815 format %{ "LDX $mem,$dst\t! ptr" %}
5816 ins_encode %{
5817 __ ldx($mem$$Address, $dst$$Register);
5818 %}
5819 #endif
5820 ins_pipe(iload_mem);
5821 %}
5822
5823 // Load Compressed Pointer
5824 instruct loadN(iRegN dst, memory mem) %{
5825 match(Set dst (LoadN mem));
5826 ins_cost(MEMORY_REF_COST);
5827 size(4);
5828
5829 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5830 ins_encode %{
5831 __ lduw($mem$$Address, $dst$$Register);
5832 %}
5833 ins_pipe(iload_mem);
5834 %}
5835
5836 // Load Klass Pointer
5837 instruct loadKlass(iRegP dst, memory mem) %{
5838 match(Set dst (LoadKlass mem));
5839 ins_cost(MEMORY_REF_COST);
5840 size(4);
5841
5842 #ifndef _LP64
5843 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5844 ins_encode %{
5845 __ lduw($mem$$Address, $dst$$Register);
5846 %}
5847 #else
5848 format %{ "LDX $mem,$dst\t! klass ptr" %}
5849 ins_encode %{
5850 __ ldx($mem$$Address, $dst$$Register);
5851 %}
5852 #endif
5853 ins_pipe(iload_mem);
5854 %}
5855
5856 // Load narrow Klass Pointer
5857 instruct loadNKlass(iRegN dst, memory mem) %{
5858 match(Set dst (LoadNKlass mem));
5859 ins_cost(MEMORY_REF_COST);
5860 size(4);
5861
5862 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5863 ins_encode %{
5864 __ lduw($mem$$Address, $dst$$Register);
5865 %}
5866 ins_pipe(iload_mem);
5867 %}
5868
5869 // Load Double
5870 instruct loadD(regD dst, memory mem) %{
5871 match(Set dst (LoadD mem));
5872 ins_cost(MEMORY_REF_COST);
5873
5874 size(4);
5875 format %{ "LDDF $mem,$dst" %}
5876 opcode(Assembler::lddf_op3);
5877 ins_encode(simple_form3_mem_reg( mem, dst ) );
5878 ins_pipe(floadD_mem);
5879 %}
5880
5881 // Load Double - UNaligned
5882 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5883 match(Set dst (LoadD_unaligned mem));
5884 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5885 size(8);
5886 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5887 "\tLDF $mem+4,$dst.lo\t!" %}
5888 opcode(Assembler::ldf_op3);
5889 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5890 ins_pipe(iload_mem);
5891 %}
5892
5893 // Load Float
5894 instruct loadF(regF dst, memory mem) %{
5895 match(Set dst (LoadF mem));
5896 ins_cost(MEMORY_REF_COST);
5897
5898 size(4);
5899 format %{ "LDF $mem,$dst" %}
5900 opcode(Assembler::ldf_op3);
5901 ins_encode(simple_form3_mem_reg( mem, dst ) );
5902 ins_pipe(floadF_mem);
5903 %}
5904
5905 // Load Constant
5906 instruct loadConI( iRegI dst, immI src ) %{
5907 match(Set dst src);
5908 ins_cost(DEFAULT_COST * 3/2);
5909 format %{ "SET $src,$dst" %}
5910 ins_encode( Set32(src, dst) );
5911 ins_pipe(ialu_hi_lo_reg);
5912 %}
5913
5914 instruct loadConI13( iRegI dst, immI13 src ) %{
5915 match(Set dst src);
5916
5917 size(4);
5918 format %{ "MOV $src,$dst" %}
5919 ins_encode( Set13( src, dst ) );
5920 ins_pipe(ialu_imm);
5921 %}
5922
5923 #ifndef _LP64
5924 instruct loadConP(iRegP dst, immP con) %{
5925 match(Set dst con);
5926 ins_cost(DEFAULT_COST * 3/2);
5927 format %{ "SET $con,$dst\t!ptr" %}
5928 ins_encode %{
5929 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5930 intptr_t val = $con$$constant;
5931 if (constant_reloc == relocInfo::oop_type) {
5932 __ set_oop_constant((jobject) val, $dst$$Register);
5933 } else if (constant_reloc == relocInfo::metadata_type) {
5934 __ set_metadata_constant((Metadata*)val, $dst$$Register);
5935 } else { // non-oop pointers, e.g. card mark base, heap top
5936 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5937 __ set(val, $dst$$Register);
5938 }
5939 %}
5940 ins_pipe(loadConP);
5941 %}
5942 #else
5943 instruct loadConP_set(iRegP dst, immP_set con) %{
5944 match(Set dst con);
5945 ins_cost(DEFAULT_COST * 3/2);
5946 format %{ "SET $con,$dst\t! ptr" %}
5947 ins_encode %{
5948 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5949 intptr_t val = $con$$constant;
5950 if (constant_reloc == relocInfo::oop_type) {
5951 __ set_oop_constant((jobject) val, $dst$$Register);
5952 } else if (constant_reloc == relocInfo::metadata_type) {
5953 __ set_metadata_constant((Metadata*)val, $dst$$Register);
5954 } else { // non-oop pointers, e.g. card mark base, heap top
5955 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5956 __ set(val, $dst$$Register);
5957 }
5958 %}
5959 ins_pipe(loadConP);
5960 %}
5961
5962 instruct loadConP_load(iRegP dst, immP_load con) %{
5963 match(Set dst con);
5964 ins_cost(MEMORY_REF_COST);
5965 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
5966 ins_encode %{
5967 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
5968 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
5969 %}
5970 ins_pipe(loadConP);
5971 %}
5972
5973 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
5974 match(Set dst con);
5975 ins_cost(DEFAULT_COST * 3/2);
5976 format %{ "SET $con,$dst\t! non-oop ptr" %}
5977 ins_encode %{
5978 if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) {
5979 __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register);
5980 } else {
5981 __ set($con$$constant, $dst$$Register);
5982 }
5983 %}
5984 ins_pipe(loadConP);
5985 %}
5986 #endif // _LP64
5987
5988 instruct loadConP0(iRegP dst, immP0 src) %{
5989 match(Set dst src);
5990
5991 size(4);
5992 format %{ "CLR $dst\t!ptr" %}
5993 ins_encode %{
5994 __ clr($dst$$Register);
5995 %}
5996 ins_pipe(ialu_imm);
5997 %}
5998
5999 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6000 match(Set dst src);
6001 ins_cost(DEFAULT_COST);
6002 format %{ "SET $src,$dst\t!ptr" %}
6003 ins_encode %{
6004 AddressLiteral polling_page(os::get_polling_page());
6005 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6006 %}
6007 ins_pipe(loadConP_poll);
6008 %}
6009
6010 instruct loadConN0(iRegN dst, immN0 src) %{
6011 match(Set dst src);
6012
6013 size(4);
6014 format %{ "CLR $dst\t! compressed NULL ptr" %}
6015 ins_encode %{
6016 __ clr($dst$$Register);
6017 %}
6018 ins_pipe(ialu_imm);
6019 %}
6020
6021 instruct loadConN(iRegN dst, immN src) %{
6022 match(Set dst src);
6023 ins_cost(DEFAULT_COST * 3/2);
6024 format %{ "SET $src,$dst\t! compressed ptr" %}
6025 ins_encode %{
6026 Register dst = $dst$$Register;
6027 __ set_narrow_oop((jobject)$src$$constant, dst);
6028 %}
6029 ins_pipe(ialu_hi_lo_reg);
6030 %}
6031
6032 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6033 match(Set dst src);
6034 ins_cost(DEFAULT_COST * 3/2);
6035 format %{ "SET $src,$dst\t! compressed klass ptr" %}
6036 ins_encode %{
6037 Register dst = $dst$$Register;
6038 __ set_narrow_klass((Klass*)$src$$constant, dst);
6039 %}
6040 ins_pipe(ialu_hi_lo_reg);
6041 %}
6042
6043 // Materialize long value (predicated by immL_cheap).
6044 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6045 match(Set dst con);
6046 effect(KILL tmp);
6047 ins_cost(DEFAULT_COST * 3);
6048 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6049 ins_encode %{
6050 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6051 %}
6052 ins_pipe(loadConL);
6053 %}
6054
6055 // Load long value from constant table (predicated by immL_expensive).
6056 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6057 match(Set dst con);
6058 ins_cost(MEMORY_REF_COST);
6059 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6060 ins_encode %{
6061 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6062 __ ldx($constanttablebase, con_offset, $dst$$Register);
6063 %}
6064 ins_pipe(loadConL);
6065 %}
6066
6067 instruct loadConL0( iRegL dst, immL0 src ) %{
6068 match(Set dst src);
6069 ins_cost(DEFAULT_COST);
6070 size(4);
6071 format %{ "CLR $dst\t! long" %}
6072 ins_encode( Set13( src, dst ) );
6073 ins_pipe(ialu_imm);
6074 %}
6075
6076 instruct loadConL13( iRegL dst, immL13 src ) %{
6077 match(Set dst src);
6078 ins_cost(DEFAULT_COST * 2);
6079
6080 size(4);
6081 format %{ "MOV $src,$dst\t! long" %}
6082 ins_encode( Set13( src, dst ) );
6083 ins_pipe(ialu_imm);
6084 %}
6085
6086 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6087 match(Set dst con);
6088 effect(KILL tmp);
6089 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6090 ins_encode %{
6091 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6092 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6093 %}
6094 ins_pipe(loadConFD);
6095 %}
6096
6097 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6098 match(Set dst con);
6099 effect(KILL tmp);
6100 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6101 ins_encode %{
6102 // XXX This is a quick fix for 6833573.
6103 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6104 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6105 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6106 %}
6107 ins_pipe(loadConFD);
6108 %}
6109
6110 // Prefetch instructions for allocation.
6111 // Must be safe to execute with invalid address (cannot fault).
6112
6113 instruct prefetchAlloc( memory mem ) %{
6114 predicate(AllocatePrefetchInstr == 0);
6115 match( PrefetchAllocation mem );
6116 ins_cost(MEMORY_REF_COST);
6117 size(4);
6118
6119 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6120 opcode(Assembler::prefetch_op3);
6121 ins_encode( form3_mem_prefetch_write( mem ) );
6122 ins_pipe(iload_mem);
6123 %}
6124
6125 // Use BIS instruction to prefetch for allocation.
6126 // Could fault, need space at the end of TLAB.
6127 instruct prefetchAlloc_bis( iRegP dst ) %{
6128 predicate(AllocatePrefetchInstr == 1);
6129 match( PrefetchAllocation dst );
6130 ins_cost(MEMORY_REF_COST);
6131 size(4);
6132
6133 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6134 ins_encode %{
6135 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6136 %}
6137 ins_pipe(istore_mem_reg);
6138 %}
6139
6140 // Next code is used for finding next cache line address to prefetch.
6141 #ifndef _LP64
6142 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6143 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6144 ins_cost(DEFAULT_COST);
6145 size(4);
6146
6147 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6148 ins_encode %{
6149 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6150 %}
6151 ins_pipe(ialu_reg_imm);
6152 %}
6153 #else
6154 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6155 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6156 ins_cost(DEFAULT_COST);
6157 size(4);
6158
6159 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6160 ins_encode %{
6161 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6162 %}
6163 ins_pipe(ialu_reg_imm);
6164 %}
6165 #endif
6166
6167 //----------Store Instructions-------------------------------------------------
6168 // Store Byte
6169 instruct storeB(memory mem, iRegI src) %{
6170 match(Set mem (StoreB mem src));
6171 ins_cost(MEMORY_REF_COST);
6172
6173 size(4);
6174 format %{ "STB $src,$mem\t! byte" %}
6175 opcode(Assembler::stb_op3);
6176 ins_encode(simple_form3_mem_reg( mem, src ) );
6177 ins_pipe(istore_mem_reg);
6178 %}
6179
6180 instruct storeB0(memory mem, immI0 src) %{
6181 match(Set mem (StoreB mem src));
6182 ins_cost(MEMORY_REF_COST);
6183
6184 size(4);
6185 format %{ "STB $src,$mem\t! byte" %}
6186 opcode(Assembler::stb_op3);
6187 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6188 ins_pipe(istore_mem_zero);
6189 %}
6190
6191 instruct storeCM0(memory mem, immI0 src) %{
6192 match(Set mem (StoreCM mem src));
6193 ins_cost(MEMORY_REF_COST);
6194
6195 size(4);
6196 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6197 opcode(Assembler::stb_op3);
6198 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6199 ins_pipe(istore_mem_zero);
6200 %}
6201
6202 // Store Char/Short
6203 instruct storeC(memory mem, iRegI src) %{
6204 match(Set mem (StoreC mem src));
6205 ins_cost(MEMORY_REF_COST);
6206
6207 size(4);
6208 format %{ "STH $src,$mem\t! short" %}
6209 opcode(Assembler::sth_op3);
6210 ins_encode(simple_form3_mem_reg( mem, src ) );
6211 ins_pipe(istore_mem_reg);
6212 %}
6213
6214 instruct storeC0(memory mem, immI0 src) %{
6215 match(Set mem (StoreC mem src));
6216 ins_cost(MEMORY_REF_COST);
6217
6218 size(4);
6219 format %{ "STH $src,$mem\t! short" %}
6220 opcode(Assembler::sth_op3);
6221 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6222 ins_pipe(istore_mem_zero);
6223 %}
6224
6225 // Store Integer
6226 instruct storeI(memory mem, iRegI src) %{
6227 match(Set mem (StoreI mem src));
6228 ins_cost(MEMORY_REF_COST);
6229
6230 size(4);
6231 format %{ "STW $src,$mem" %}
6232 opcode(Assembler::stw_op3);
6233 ins_encode(simple_form3_mem_reg( mem, src ) );
6234 ins_pipe(istore_mem_reg);
6235 %}
6236
6237 // Store Long
6238 instruct storeL(memory mem, iRegL src) %{
6239 match(Set mem (StoreL mem src));
6240 ins_cost(MEMORY_REF_COST);
6241 size(4);
6242 format %{ "STX $src,$mem\t! long" %}
6243 opcode(Assembler::stx_op3);
6244 ins_encode(simple_form3_mem_reg( mem, src ) );
6245 ins_pipe(istore_mem_reg);
6246 %}
6247
6248 instruct storeI0(memory mem, immI0 src) %{
6249 match(Set mem (StoreI mem src));
6250 ins_cost(MEMORY_REF_COST);
6251
6252 size(4);
6253 format %{ "STW $src,$mem" %}
6254 opcode(Assembler::stw_op3);
6255 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6256 ins_pipe(istore_mem_zero);
6257 %}
6258
6259 instruct storeL0(memory mem, immL0 src) %{
6260 match(Set mem (StoreL mem src));
6261 ins_cost(MEMORY_REF_COST);
6262
6263 size(4);
6264 format %{ "STX $src,$mem" %}
6265 opcode(Assembler::stx_op3);
6266 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6267 ins_pipe(istore_mem_zero);
6268 %}
6269
6270 // Store Integer from float register (used after fstoi)
6271 instruct storeI_Freg(memory mem, regF src) %{
6272 match(Set mem (StoreI mem src));
6273 ins_cost(MEMORY_REF_COST);
6274
6275 size(4);
6276 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6277 opcode(Assembler::stf_op3);
6278 ins_encode(simple_form3_mem_reg( mem, src ) );
6279 ins_pipe(fstoreF_mem_reg);
6280 %}
6281
6282 // Store Pointer
6283 instruct storeP(memory dst, sp_ptr_RegP src) %{
6284 match(Set dst (StoreP dst src));
6285 ins_cost(MEMORY_REF_COST);
6286 size(4);
6287
6288 #ifndef _LP64
6289 format %{ "STW $src,$dst\t! ptr" %}
6290 opcode(Assembler::stw_op3, 0, REGP_OP);
6291 #else
6292 format %{ "STX $src,$dst\t! ptr" %}
6293 opcode(Assembler::stx_op3, 0, REGP_OP);
6294 #endif
6295 ins_encode( form3_mem_reg( dst, src ) );
6296 ins_pipe(istore_mem_spORreg);
6297 %}
6298
6299 instruct storeP0(memory dst, immP0 src) %{
6300 match(Set dst (StoreP dst src));
6301 ins_cost(MEMORY_REF_COST);
6302 size(4);
6303
6304 #ifndef _LP64
6305 format %{ "STW $src,$dst\t! ptr" %}
6306 opcode(Assembler::stw_op3, 0, REGP_OP);
6307 #else
6308 format %{ "STX $src,$dst\t! ptr" %}
6309 opcode(Assembler::stx_op3, 0, REGP_OP);
6310 #endif
6311 ins_encode( form3_mem_reg( dst, R_G0 ) );
6312 ins_pipe(istore_mem_zero);
6313 %}
6314
6315 // Store Compressed Pointer
6316 instruct storeN(memory dst, iRegN src) %{
6317 match(Set dst (StoreN dst src));
6318 ins_cost(MEMORY_REF_COST);
6319 size(4);
6320
6321 format %{ "STW $src,$dst\t! compressed ptr" %}
6322 ins_encode %{
6323 Register base = as_Register($dst$$base);
6324 Register index = as_Register($dst$$index);
6325 Register src = $src$$Register;
6326 if (index != G0) {
6327 __ stw(src, base, index);
6328 } else {
6329 __ stw(src, base, $dst$$disp);
6330 }
6331 %}
6332 ins_pipe(istore_mem_spORreg);
6333 %}
6334
6335 instruct storeNKlass(memory dst, iRegN src) %{
6336 match(Set dst (StoreNKlass dst src));
6337 ins_cost(MEMORY_REF_COST);
6338 size(4);
6339
6340 format %{ "STW $src,$dst\t! compressed klass ptr" %}
6341 ins_encode %{
6342 Register base = as_Register($dst$$base);
6343 Register index = as_Register($dst$$index);
6344 Register src = $src$$Register;
6345 if (index != G0) {
6346 __ stw(src, base, index);
6347 } else {
6348 __ stw(src, base, $dst$$disp);
6349 }
6350 %}
6351 ins_pipe(istore_mem_spORreg);
6352 %}
6353
6354 instruct storeN0(memory dst, immN0 src) %{
6355 match(Set dst (StoreN dst src));
6356 ins_cost(MEMORY_REF_COST);
6357 size(4);
6358
6359 format %{ "STW $src,$dst\t! compressed ptr" %}
6360 ins_encode %{
6361 Register base = as_Register($dst$$base);
6362 Register index = as_Register($dst$$index);
6363 if (index != G0) {
6364 __ stw(0, base, index);
6365 } else {
6366 __ stw(0, base, $dst$$disp);
6367 }
6368 %}
6369 ins_pipe(istore_mem_zero);
6370 %}
6371
6372 // Store Double
6373 instruct storeD( memory mem, regD src) %{
6374 match(Set mem (StoreD mem src));
6375 ins_cost(MEMORY_REF_COST);
6376
6377 size(4);
6378 format %{ "STDF $src,$mem" %}
6379 opcode(Assembler::stdf_op3);
6380 ins_encode(simple_form3_mem_reg( mem, src ) );
6381 ins_pipe(fstoreD_mem_reg);
6382 %}
6383
6384 instruct storeD0( memory mem, immD0 src) %{
6385 match(Set mem (StoreD mem src));
6386 ins_cost(MEMORY_REF_COST);
6387
6388 size(4);
6389 format %{ "STX $src,$mem" %}
6390 opcode(Assembler::stx_op3);
6391 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6392 ins_pipe(fstoreD_mem_zero);
6393 %}
6394
6395 // Store Float
6396 instruct storeF( memory mem, regF src) %{
6397 match(Set mem (StoreF mem src));
6398 ins_cost(MEMORY_REF_COST);
6399
6400 size(4);
6401 format %{ "STF $src,$mem" %}
6402 opcode(Assembler::stf_op3);
6403 ins_encode(simple_form3_mem_reg( mem, src ) );
6404 ins_pipe(fstoreF_mem_reg);
6405 %}
6406
6407 instruct storeF0( memory mem, immF0 src) %{
6408 match(Set mem (StoreF mem src));
6409 ins_cost(MEMORY_REF_COST);
6410
6411 size(4);
6412 format %{ "STW $src,$mem\t! storeF0" %}
6413 opcode(Assembler::stw_op3);
6414 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6415 ins_pipe(fstoreF_mem_zero);
6416 %}
6417
6418 // Convert oop pointer into compressed form
6419 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6420 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6421 match(Set dst (EncodeP src));
6422 format %{ "encode_heap_oop $src, $dst" %}
6423 ins_encode %{
6424 __ encode_heap_oop($src$$Register, $dst$$Register);
6425 %}
6426 ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE);
6427 ins_pipe(ialu_reg);
6428 %}
6429
6430 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6431 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6432 match(Set dst (EncodeP src));
6433 format %{ "encode_heap_oop_not_null $src, $dst" %}
6434 ins_encode %{
6435 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6436 %}
6437 ins_pipe(ialu_reg);
6438 %}
6439
6440 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6441 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6442 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6443 match(Set dst (DecodeN src));
6444 format %{ "decode_heap_oop $src, $dst" %}
6445 ins_encode %{
6446 __ decode_heap_oop($src$$Register, $dst$$Register);
6447 %}
6448 ins_pipe(ialu_reg);
6449 %}
6450
6451 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6452 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6453 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6454 match(Set dst (DecodeN src));
6455 format %{ "decode_heap_oop_not_null $src, $dst" %}
6456 ins_encode %{
6457 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6458 %}
6459 ins_pipe(ialu_reg);
6460 %}
6461
6462 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6463 match(Set dst (EncodePKlass src));
6464 format %{ "encode_klass_not_null $src, $dst" %}
6465 ins_encode %{
6466 __ encode_klass_not_null($src$$Register, $dst$$Register);
6467 %}
6468 ins_pipe(ialu_reg);
6469 %}
6470
6471 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6472 match(Set dst (DecodeNKlass src));
6473 format %{ "decode_klass_not_null $src, $dst" %}
6474 ins_encode %{
6475 __ decode_klass_not_null($src$$Register, $dst$$Register);
6476 %}
6477 ins_pipe(ialu_reg);
6478 %}
6479
6480 //----------MemBar Instructions-----------------------------------------------
6481 // Memory barrier flavors
6482
6483 instruct membar_acquire() %{
6484 match(MemBarAcquire);
6485 match(LoadFence);
6486 ins_cost(4*MEMORY_REF_COST);
6487
6488 size(0);
6489 format %{ "MEMBAR-acquire" %}
6490 ins_encode( enc_membar_acquire );
6491 ins_pipe(long_memory_op);
6492 %}
6493
6494 instruct membar_acquire_lock() %{
6495 match(MemBarAcquireLock);
6496 ins_cost(0);
6497
6498 size(0);
6499 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6500 ins_encode( );
6501 ins_pipe(empty);
6502 %}
6503
6504 instruct membar_release() %{
6505 match(MemBarRelease);
6506 match(StoreFence);
6507 ins_cost(4*MEMORY_REF_COST);
6508
6509 size(0);
6510 format %{ "MEMBAR-release" %}
6511 ins_encode( enc_membar_release );
6512 ins_pipe(long_memory_op);
6513 %}
6514
6515 instruct membar_release_lock() %{
6516 match(MemBarReleaseLock);
6517 ins_cost(0);
6518
6519 size(0);
6520 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6521 ins_encode( );
6522 ins_pipe(empty);
6523 %}
6524
6525 instruct membar_volatile() %{
6526 match(MemBarVolatile);
6527 ins_cost(4*MEMORY_REF_COST);
6528
6529 size(4);
6530 format %{ "MEMBAR-volatile" %}
6531 ins_encode( enc_membar_volatile );
6532 ins_pipe(long_memory_op);
6533 %}
6534
6535 instruct unnecessary_membar_volatile() %{
6536 match(MemBarVolatile);
6537 predicate(Matcher::post_store_load_barrier(n));
6538 ins_cost(0);
6539
6540 size(0);
6541 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6542 ins_encode( );
6543 ins_pipe(empty);
6544 %}
6545
6546 instruct membar_storestore() %{
6547 match(MemBarStoreStore);
6548 ins_cost(0);
6549
6550 size(0);
6551 format %{ "!MEMBAR-storestore (empty encoding)" %}
6552 ins_encode( );
6553 ins_pipe(empty);
6554 %}
6555
6556 //----------Register Move Instructions-----------------------------------------
6557 instruct roundDouble_nop(regD dst) %{
6558 match(Set dst (RoundDouble dst));
6559 ins_cost(0);
6560 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6561 ins_encode( );
6562 ins_pipe(empty);
6563 %}
6564
6565
6566 instruct roundFloat_nop(regF dst) %{
6567 match(Set dst (RoundFloat dst));
6568 ins_cost(0);
6569 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6570 ins_encode( );
6571 ins_pipe(empty);
6572 %}
6573
6574
6575 // Cast Index to Pointer for unsafe natives
6576 instruct castX2P(iRegX src, iRegP dst) %{
6577 match(Set dst (CastX2P src));
6578
6579 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6580 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6581 ins_pipe(ialu_reg);
6582 %}
6583
6584 // Cast Pointer to Index for unsafe natives
6585 instruct castP2X(iRegP src, iRegX dst) %{
6586 match(Set dst (CastP2X src));
6587
6588 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6589 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6590 ins_pipe(ialu_reg);
6591 %}
6592
6593 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6594 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6595 match(Set stkSlot src); // chain rule
6596 ins_cost(MEMORY_REF_COST);
6597 format %{ "STDF $src,$stkSlot\t!stk" %}
6598 opcode(Assembler::stdf_op3);
6599 ins_encode(simple_form3_mem_reg(stkSlot, src));
6600 ins_pipe(fstoreD_stk_reg);
6601 %}
6602
6603 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6604 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6605 match(Set dst stkSlot); // chain rule
6606 ins_cost(MEMORY_REF_COST);
6607 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6608 opcode(Assembler::lddf_op3);
6609 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6610 ins_pipe(floadD_stk);
6611 %}
6612
6613 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6614 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6615 match(Set stkSlot src); // chain rule
6616 ins_cost(MEMORY_REF_COST);
6617 format %{ "STF $src,$stkSlot\t!stk" %}
6618 opcode(Assembler::stf_op3);
6619 ins_encode(simple_form3_mem_reg(stkSlot, src));
6620 ins_pipe(fstoreF_stk_reg);
6621 %}
6622
6623 //----------Conditional Move---------------------------------------------------
6624 // Conditional move
6625 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6626 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6627 ins_cost(150);
6628 format %{ "MOV$cmp $pcc,$src,$dst" %}
6629 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6630 ins_pipe(ialu_reg);
6631 %}
6632
6633 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6634 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6635 ins_cost(140);
6636 format %{ "MOV$cmp $pcc,$src,$dst" %}
6637 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6638 ins_pipe(ialu_imm);
6639 %}
6640
6641 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6642 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6643 ins_cost(150);
6644 size(4);
6645 format %{ "MOV$cmp $icc,$src,$dst" %}
6646 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6647 ins_pipe(ialu_reg);
6648 %}
6649
6650 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6651 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6652 ins_cost(140);
6653 size(4);
6654 format %{ "MOV$cmp $icc,$src,$dst" %}
6655 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6656 ins_pipe(ialu_imm);
6657 %}
6658
6659 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6660 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6661 ins_cost(150);
6662 size(4);
6663 format %{ "MOV$cmp $icc,$src,$dst" %}
6664 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6665 ins_pipe(ialu_reg);
6666 %}
6667
6668 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6669 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6670 ins_cost(140);
6671 size(4);
6672 format %{ "MOV$cmp $icc,$src,$dst" %}
6673 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6674 ins_pipe(ialu_imm);
6675 %}
6676
6677 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6678 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6679 ins_cost(150);
6680 size(4);
6681 format %{ "MOV$cmp $fcc,$src,$dst" %}
6682 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6683 ins_pipe(ialu_reg);
6684 %}
6685
6686 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6687 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6688 ins_cost(140);
6689 size(4);
6690 format %{ "MOV$cmp $fcc,$src,$dst" %}
6691 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6692 ins_pipe(ialu_imm);
6693 %}
6694
6695 // Conditional move for RegN. Only cmov(reg,reg).
6696 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6697 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6698 ins_cost(150);
6699 format %{ "MOV$cmp $pcc,$src,$dst" %}
6700 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6701 ins_pipe(ialu_reg);
6702 %}
6703
6704 // This instruction also works with CmpN so we don't need cmovNN_reg.
6705 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6706 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6707 ins_cost(150);
6708 size(4);
6709 format %{ "MOV$cmp $icc,$src,$dst" %}
6710 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6711 ins_pipe(ialu_reg);
6712 %}
6713
6714 // This instruction also works with CmpN so we don't need cmovNN_reg.
6715 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6716 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6717 ins_cost(150);
6718 size(4);
6719 format %{ "MOV$cmp $icc,$src,$dst" %}
6720 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6721 ins_pipe(ialu_reg);
6722 %}
6723
6724 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6725 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6726 ins_cost(150);
6727 size(4);
6728 format %{ "MOV$cmp $fcc,$src,$dst" %}
6729 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6730 ins_pipe(ialu_reg);
6731 %}
6732
6733 // Conditional move
6734 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6735 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6736 ins_cost(150);
6737 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6738 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6739 ins_pipe(ialu_reg);
6740 %}
6741
6742 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6743 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6744 ins_cost(140);
6745 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6746 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6747 ins_pipe(ialu_imm);
6748 %}
6749
6750 // This instruction also works with CmpN so we don't need cmovPN_reg.
6751 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6752 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6753 ins_cost(150);
6754
6755 size(4);
6756 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6757 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6758 ins_pipe(ialu_reg);
6759 %}
6760
6761 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6762 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6763 ins_cost(150);
6764
6765 size(4);
6766 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6767 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6768 ins_pipe(ialu_reg);
6769 %}
6770
6771 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6772 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6773 ins_cost(140);
6774
6775 size(4);
6776 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6777 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6778 ins_pipe(ialu_imm);
6779 %}
6780
6781 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6782 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6783 ins_cost(140);
6784
6785 size(4);
6786 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6787 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6788 ins_pipe(ialu_imm);
6789 %}
6790
6791 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6792 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6793 ins_cost(150);
6794 size(4);
6795 format %{ "MOV$cmp $fcc,$src,$dst" %}
6796 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6797 ins_pipe(ialu_imm);
6798 %}
6799
6800 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6801 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6802 ins_cost(140);
6803 size(4);
6804 format %{ "MOV$cmp $fcc,$src,$dst" %}
6805 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6806 ins_pipe(ialu_imm);
6807 %}
6808
6809 // Conditional move
6810 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6811 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6812 ins_cost(150);
6813 opcode(0x101);
6814 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6815 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6816 ins_pipe(int_conditional_float_move);
6817 %}
6818
6819 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6820 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6821 ins_cost(150);
6822
6823 size(4);
6824 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6825 opcode(0x101);
6826 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6827 ins_pipe(int_conditional_float_move);
6828 %}
6829
6830 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6831 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6832 ins_cost(150);
6833
6834 size(4);
6835 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6836 opcode(0x101);
6837 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6838 ins_pipe(int_conditional_float_move);
6839 %}
6840
6841 // Conditional move,
6842 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6843 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6844 ins_cost(150);
6845 size(4);
6846 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6847 opcode(0x1);
6848 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6849 ins_pipe(int_conditional_double_move);
6850 %}
6851
6852 // Conditional move
6853 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6854 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6855 ins_cost(150);
6856 size(4);
6857 opcode(0x102);
6858 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6859 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6860 ins_pipe(int_conditional_double_move);
6861 %}
6862
6863 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6864 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6865 ins_cost(150);
6866
6867 size(4);
6868 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6869 opcode(0x102);
6870 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6871 ins_pipe(int_conditional_double_move);
6872 %}
6873
6874 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6875 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6876 ins_cost(150);
6877
6878 size(4);
6879 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6880 opcode(0x102);
6881 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6882 ins_pipe(int_conditional_double_move);
6883 %}
6884
6885 // Conditional move,
6886 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6887 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6888 ins_cost(150);
6889 size(4);
6890 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6891 opcode(0x2);
6892 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6893 ins_pipe(int_conditional_double_move);
6894 %}
6895
6896 // Conditional move
6897 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6898 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6899 ins_cost(150);
6900 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6901 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6902 ins_pipe(ialu_reg);
6903 %}
6904
6905 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6906 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6907 ins_cost(140);
6908 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6909 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6910 ins_pipe(ialu_imm);
6911 %}
6912
6913 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6914 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6915 ins_cost(150);
6916
6917 size(4);
6918 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6919 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6920 ins_pipe(ialu_reg);
6921 %}
6922
6923
6924 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
6925 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6926 ins_cost(150);
6927
6928 size(4);
6929 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6930 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6931 ins_pipe(ialu_reg);
6932 %}
6933
6934
6935 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6936 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6937 ins_cost(150);
6938
6939 size(4);
6940 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6941 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6942 ins_pipe(ialu_reg);
6943 %}
6944
6945
6946
6947 //----------OS and Locking Instructions----------------------------------------
6948
6949 // This name is KNOWN by the ADLC and cannot be changed.
6950 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6951 // for this guy.
6952 instruct tlsLoadP(g2RegP dst) %{
6953 match(Set dst (ThreadLocal));
6954
6955 size(0);
6956 ins_cost(0);
6957 format %{ "# TLS is in G2" %}
6958 ins_encode( /*empty encoding*/ );
6959 ins_pipe(ialu_none);
6960 %}
6961
6962 instruct checkCastPP( iRegP dst ) %{
6963 match(Set dst (CheckCastPP dst));
6964
6965 size(0);
6966 format %{ "# checkcastPP of $dst" %}
6967 ins_encode( /*empty encoding*/ );
6968 ins_pipe(empty);
6969 %}
6970
6971
6972 instruct castPP( iRegP dst ) %{
6973 match(Set dst (CastPP dst));
6974 format %{ "# castPP of $dst" %}
6975 ins_encode( /*empty encoding*/ );
6976 ins_pipe(empty);
6977 %}
6978
6979 instruct castII( iRegI dst ) %{
6980 match(Set dst (CastII dst));
6981 format %{ "# castII of $dst" %}
6982 ins_encode( /*empty encoding*/ );
6983 ins_cost(0);
6984 ins_pipe(empty);
6985 %}
6986
6987 //----------Arithmetic Instructions--------------------------------------------
6988 // Addition Instructions
6989 // Register Addition
6990 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6991 match(Set dst (AddI src1 src2));
6992
6993 size(4);
6994 format %{ "ADD $src1,$src2,$dst" %}
6995 ins_encode %{
6996 __ add($src1$$Register, $src2$$Register, $dst$$Register);
6997 %}
6998 ins_pipe(ialu_reg_reg);
6999 %}
7000
7001 // Immediate Addition
7002 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7003 match(Set dst (AddI src1 src2));
7004
7005 size(4);
7006 format %{ "ADD $src1,$src2,$dst" %}
7007 opcode(Assembler::add_op3, Assembler::arith_op);
7008 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7009 ins_pipe(ialu_reg_imm);
7010 %}
7011
7012 // Pointer Register Addition
7013 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7014 match(Set dst (AddP src1 src2));
7015
7016 size(4);
7017 format %{ "ADD $src1,$src2,$dst" %}
7018 opcode(Assembler::add_op3, Assembler::arith_op);
7019 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7020 ins_pipe(ialu_reg_reg);
7021 %}
7022
7023 // Pointer Immediate Addition
7024 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7025 match(Set dst (AddP src1 src2));
7026
7027 size(4);
7028 format %{ "ADD $src1,$src2,$dst" %}
7029 opcode(Assembler::add_op3, Assembler::arith_op);
7030 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7031 ins_pipe(ialu_reg_imm);
7032 %}
7033
7034 // Long Addition
7035 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7036 match(Set dst (AddL src1 src2));
7037
7038 size(4);
7039 format %{ "ADD $src1,$src2,$dst\t! long" %}
7040 opcode(Assembler::add_op3, Assembler::arith_op);
7041 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7042 ins_pipe(ialu_reg_reg);
7043 %}
7044
7045 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7046 match(Set dst (AddL src1 con));
7047
7048 size(4);
7049 format %{ "ADD $src1,$con,$dst" %}
7050 opcode(Assembler::add_op3, Assembler::arith_op);
7051 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7052 ins_pipe(ialu_reg_imm);
7053 %}
7054
7055 //----------Conditional_store--------------------------------------------------
7056 // Conditional-store of the updated heap-top.
7057 // Used during allocation of the shared heap.
7058 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7059
7060 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7061 instruct loadPLocked(iRegP dst, memory mem) %{
7062 match(Set dst (LoadPLocked mem));
7063 ins_cost(MEMORY_REF_COST);
7064
7065 #ifndef _LP64
7066 size(4);
7067 format %{ "LDUW $mem,$dst\t! ptr" %}
7068 opcode(Assembler::lduw_op3, 0, REGP_OP);
7069 #else
7070 format %{ "LDX $mem,$dst\t! ptr" %}
7071 opcode(Assembler::ldx_op3, 0, REGP_OP);
7072 #endif
7073 ins_encode( form3_mem_reg( mem, dst ) );
7074 ins_pipe(iload_mem);
7075 %}
7076
7077 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7078 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7079 effect( KILL newval );
7080 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7081 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7082 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7083 ins_pipe( long_memory_op );
7084 %}
7085
7086 // Conditional-store of an int value.
7087 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7088 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7089 effect( KILL newval );
7090 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7091 "CMP $oldval,$newval\t\t! See if we made progress" %}
7092 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7093 ins_pipe( long_memory_op );
7094 %}
7095
7096 // Conditional-store of a long value.
7097 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7098 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7099 effect( KILL newval );
7100 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7101 "CMP $oldval,$newval\t\t! See if we made progress" %}
7102 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7103 ins_pipe( long_memory_op );
7104 %}
7105
7106 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7107
7108 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7109 predicate(VM_Version::supports_cx8());
7110 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7111 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7112 format %{
7113 "MOV $newval,O7\n\t"
7114 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7115 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7116 "MOV 1,$res\n\t"
7117 "MOVne xcc,R_G0,$res"
7118 %}
7119 ins_encode( enc_casx(mem_ptr, oldval, newval),
7120 enc_lflags_ne_to_boolean(res) );
7121 ins_pipe( long_memory_op );
7122 %}
7123
7124
7125 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7126 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7127 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7128 format %{
7129 "MOV $newval,O7\n\t"
7130 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7131 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7132 "MOV 1,$res\n\t"
7133 "MOVne icc,R_G0,$res"
7134 %}
7135 ins_encode( enc_casi(mem_ptr, oldval, newval),
7136 enc_iflags_ne_to_boolean(res) );
7137 ins_pipe( long_memory_op );
7138 %}
7139
7140 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7141 #ifdef _LP64
7142 predicate(VM_Version::supports_cx8());
7143 #endif
7144 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7145 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7146 format %{
7147 "MOV $newval,O7\n\t"
7148 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7149 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7150 "MOV 1,$res\n\t"
7151 "MOVne xcc,R_G0,$res"
7152 %}
7153 #ifdef _LP64
7154 ins_encode( enc_casx(mem_ptr, oldval, newval),
7155 enc_lflags_ne_to_boolean(res) );
7156 #else
7157 ins_encode( enc_casi(mem_ptr, oldval, newval),
7158 enc_iflags_ne_to_boolean(res) );
7159 #endif
7160 ins_pipe( long_memory_op );
7161 %}
7162
7163 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7164 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7165 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7166 format %{
7167 "MOV $newval,O7\n\t"
7168 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7169 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7170 "MOV 1,$res\n\t"
7171 "MOVne icc,R_G0,$res"
7172 %}
7173 ins_encode( enc_casi(mem_ptr, oldval, newval),
7174 enc_iflags_ne_to_boolean(res) );
7175 ins_pipe( long_memory_op );
7176 %}
7177
7178 instruct xchgI( memory mem, iRegI newval) %{
7179 match(Set newval (GetAndSetI mem newval));
7180 format %{ "SWAP [$mem],$newval" %}
7181 size(4);
7182 ins_encode %{
7183 __ swap($mem$$Address, $newval$$Register);
7184 %}
7185 ins_pipe( long_memory_op );
7186 %}
7187
7188 #ifndef _LP64
7189 instruct xchgP( memory mem, iRegP newval) %{
7190 match(Set newval (GetAndSetP mem newval));
7191 format %{ "SWAP [$mem],$newval" %}
7192 size(4);
7193 ins_encode %{
7194 __ swap($mem$$Address, $newval$$Register);
7195 %}
7196 ins_pipe( long_memory_op );
7197 %}
7198 #endif
7199
7200 instruct xchgN( memory mem, iRegN newval) %{
7201 match(Set newval (GetAndSetN mem newval));
7202 format %{ "SWAP [$mem],$newval" %}
7203 size(4);
7204 ins_encode %{
7205 __ swap($mem$$Address, $newval$$Register);
7206 %}
7207 ins_pipe( long_memory_op );
7208 %}
7209
7210 //---------------------
7211 // Subtraction Instructions
7212 // Register Subtraction
7213 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7214 match(Set dst (SubI src1 src2));
7215
7216 size(4);
7217 format %{ "SUB $src1,$src2,$dst" %}
7218 opcode(Assembler::sub_op3, Assembler::arith_op);
7219 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7220 ins_pipe(ialu_reg_reg);
7221 %}
7222
7223 // Immediate Subtraction
7224 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7225 match(Set dst (SubI src1 src2));
7226
7227 size(4);
7228 format %{ "SUB $src1,$src2,$dst" %}
7229 opcode(Assembler::sub_op3, Assembler::arith_op);
7230 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7231 ins_pipe(ialu_reg_imm);
7232 %}
7233
7234 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7235 match(Set dst (SubI zero src2));
7236
7237 size(4);
7238 format %{ "NEG $src2,$dst" %}
7239 opcode(Assembler::sub_op3, Assembler::arith_op);
7240 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7241 ins_pipe(ialu_zero_reg);
7242 %}
7243
7244 // Long subtraction
7245 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7246 match(Set dst (SubL src1 src2));
7247
7248 size(4);
7249 format %{ "SUB $src1,$src2,$dst\t! long" %}
7250 opcode(Assembler::sub_op3, Assembler::arith_op);
7251 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7252 ins_pipe(ialu_reg_reg);
7253 %}
7254
7255 // Immediate Subtraction
7256 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7257 match(Set dst (SubL src1 con));
7258
7259 size(4);
7260 format %{ "SUB $src1,$con,$dst\t! long" %}
7261 opcode(Assembler::sub_op3, Assembler::arith_op);
7262 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7263 ins_pipe(ialu_reg_imm);
7264 %}
7265
7266 // Long negation
7267 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7268 match(Set dst (SubL zero src2));
7269
7270 size(4);
7271 format %{ "NEG $src2,$dst\t! long" %}
7272 opcode(Assembler::sub_op3, Assembler::arith_op);
7273 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7274 ins_pipe(ialu_zero_reg);
7275 %}
7276
7277 // Multiplication Instructions
7278 // Integer Multiplication
7279 // Register Multiplication
7280 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7281 match(Set dst (MulI src1 src2));
7282
7283 size(4);
7284 format %{ "MULX $src1,$src2,$dst" %}
7285 opcode(Assembler::mulx_op3, Assembler::arith_op);
7286 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7287 ins_pipe(imul_reg_reg);
7288 %}
7289
7290 // Immediate Multiplication
7291 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7292 match(Set dst (MulI src1 src2));
7293
7294 size(4);
7295 format %{ "MULX $src1,$src2,$dst" %}
7296 opcode(Assembler::mulx_op3, Assembler::arith_op);
7297 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7298 ins_pipe(imul_reg_imm);
7299 %}
7300
7301 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7302 match(Set dst (MulL src1 src2));
7303 ins_cost(DEFAULT_COST * 5);
7304 size(4);
7305 format %{ "MULX $src1,$src2,$dst\t! long" %}
7306 opcode(Assembler::mulx_op3, Assembler::arith_op);
7307 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7308 ins_pipe(mulL_reg_reg);
7309 %}
7310
7311 // Immediate Multiplication
7312 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7313 match(Set dst (MulL src1 src2));
7314 ins_cost(DEFAULT_COST * 5);
7315 size(4);
7316 format %{ "MULX $src1,$src2,$dst" %}
7317 opcode(Assembler::mulx_op3, Assembler::arith_op);
7318 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7319 ins_pipe(mulL_reg_imm);
7320 %}
7321
7322 // Integer Division
7323 // Register Division
7324 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7325 match(Set dst (DivI src1 src2));
7326 ins_cost((2+71)*DEFAULT_COST);
7327
7328 format %{ "SRA $src2,0,$src2\n\t"
7329 "SRA $src1,0,$src1\n\t"
7330 "SDIVX $src1,$src2,$dst" %}
7331 ins_encode( idiv_reg( src1, src2, dst ) );
7332 ins_pipe(sdiv_reg_reg);
7333 %}
7334
7335 // Immediate Division
7336 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7337 match(Set dst (DivI src1 src2));
7338 ins_cost((2+71)*DEFAULT_COST);
7339
7340 format %{ "SRA $src1,0,$src1\n\t"
7341 "SDIVX $src1,$src2,$dst" %}
7342 ins_encode( idiv_imm( src1, src2, dst ) );
7343 ins_pipe(sdiv_reg_imm);
7344 %}
7345
7346 //----------Div-By-10-Expansion------------------------------------------------
7347 // Extract hi bits of a 32x32->64 bit multiply.
7348 // Expand rule only, not matched
7349 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7350 effect( DEF dst, USE src1, USE src2 );
7351 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7352 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7353 ins_encode( enc_mul_hi(dst,src1,src2));
7354 ins_pipe(sdiv_reg_reg);
7355 %}
7356
7357 // Magic constant, reciprocal of 10
7358 instruct loadConI_x66666667(iRegIsafe dst) %{
7359 effect( DEF dst );
7360
7361 size(8);
7362 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7363 ins_encode( Set32(0x66666667, dst) );
7364 ins_pipe(ialu_hi_lo_reg);
7365 %}
7366
7367 // Register Shift Right Arithmetic Long by 32-63
7368 instruct sra_31( iRegI dst, iRegI src ) %{
7369 effect( DEF dst, USE src );
7370 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7371 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7372 ins_pipe(ialu_reg_reg);
7373 %}
7374
7375 // Arithmetic Shift Right by 8-bit immediate
7376 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7377 effect( DEF dst, USE src );
7378 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7379 opcode(Assembler::sra_op3, Assembler::arith_op);
7380 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7381 ins_pipe(ialu_reg_imm);
7382 %}
7383
7384 // Integer DIV with 10
7385 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7386 match(Set dst (DivI src div));
7387 ins_cost((6+6)*DEFAULT_COST);
7388 expand %{
7389 iRegIsafe tmp1; // Killed temps;
7390 iRegIsafe tmp2; // Killed temps;
7391 iRegI tmp3; // Killed temps;
7392 iRegI tmp4; // Killed temps;
7393 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7394 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7395 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7396 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7397 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7398 %}
7399 %}
7400
7401 // Register Long Division
7402 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7403 match(Set dst (DivL src1 src2));
7404 ins_cost(DEFAULT_COST*71);
7405 size(4);
7406 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7407 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7408 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7409 ins_pipe(divL_reg_reg);
7410 %}
7411
7412 // Register Long Division
7413 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7414 match(Set dst (DivL src1 src2));
7415 ins_cost(DEFAULT_COST*71);
7416 size(4);
7417 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7418 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7419 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7420 ins_pipe(divL_reg_imm);
7421 %}
7422
7423 // Integer Remainder
7424 // Register Remainder
7425 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7426 match(Set dst (ModI src1 src2));
7427 effect( KILL ccr, KILL temp);
7428
7429 format %{ "SREM $src1,$src2,$dst" %}
7430 ins_encode( irem_reg(src1, src2, dst, temp) );
7431 ins_pipe(sdiv_reg_reg);
7432 %}
7433
7434 // Immediate Remainder
7435 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7436 match(Set dst (ModI src1 src2));
7437 effect( KILL ccr, KILL temp);
7438
7439 format %{ "SREM $src1,$src2,$dst" %}
7440 ins_encode( irem_imm(src1, src2, dst, temp) );
7441 ins_pipe(sdiv_reg_imm);
7442 %}
7443
7444 // Register Long Remainder
7445 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7446 effect(DEF dst, USE src1, USE src2);
7447 size(4);
7448 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7449 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7450 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7451 ins_pipe(divL_reg_reg);
7452 %}
7453
7454 // Register Long Division
7455 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7456 effect(DEF dst, USE src1, USE src2);
7457 size(4);
7458 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7459 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7460 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7461 ins_pipe(divL_reg_imm);
7462 %}
7463
7464 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7465 effect(DEF dst, USE src1, USE src2);
7466 size(4);
7467 format %{ "MULX $src1,$src2,$dst\t! long" %}
7468 opcode(Assembler::mulx_op3, Assembler::arith_op);
7469 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7470 ins_pipe(mulL_reg_reg);
7471 %}
7472
7473 // Immediate Multiplication
7474 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7475 effect(DEF dst, USE src1, USE src2);
7476 size(4);
7477 format %{ "MULX $src1,$src2,$dst" %}
7478 opcode(Assembler::mulx_op3, Assembler::arith_op);
7479 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7480 ins_pipe(mulL_reg_imm);
7481 %}
7482
7483 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7484 effect(DEF dst, USE src1, USE src2);
7485 size(4);
7486 format %{ "SUB $src1,$src2,$dst\t! long" %}
7487 opcode(Assembler::sub_op3, Assembler::arith_op);
7488 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7489 ins_pipe(ialu_reg_reg);
7490 %}
7491
7492 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7493 effect(DEF dst, USE src1, USE src2);
7494 size(4);
7495 format %{ "SUB $src1,$src2,$dst\t! long" %}
7496 opcode(Assembler::sub_op3, Assembler::arith_op);
7497 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7498 ins_pipe(ialu_reg_reg);
7499 %}
7500
7501 // Register Long Remainder
7502 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7503 match(Set dst (ModL src1 src2));
7504 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7505 expand %{
7506 iRegL tmp1;
7507 iRegL tmp2;
7508 divL_reg_reg_1(tmp1, src1, src2);
7509 mulL_reg_reg_1(tmp2, tmp1, src2);
7510 subL_reg_reg_1(dst, src1, tmp2);
7511 %}
7512 %}
7513
7514 // Register Long Remainder
7515 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7516 match(Set dst (ModL src1 src2));
7517 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7518 expand %{
7519 iRegL tmp1;
7520 iRegL tmp2;
7521 divL_reg_imm13_1(tmp1, src1, src2);
7522 mulL_reg_imm13_1(tmp2, tmp1, src2);
7523 subL_reg_reg_2 (dst, src1, tmp2);
7524 %}
7525 %}
7526
7527 // Integer Shift Instructions
7528 // Register Shift Left
7529 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7530 match(Set dst (LShiftI src1 src2));
7531
7532 size(4);
7533 format %{ "SLL $src1,$src2,$dst" %}
7534 opcode(Assembler::sll_op3, Assembler::arith_op);
7535 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7536 ins_pipe(ialu_reg_reg);
7537 %}
7538
7539 // Register Shift Left Immediate
7540 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7541 match(Set dst (LShiftI src1 src2));
7542
7543 size(4);
7544 format %{ "SLL $src1,$src2,$dst" %}
7545 opcode(Assembler::sll_op3, Assembler::arith_op);
7546 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7547 ins_pipe(ialu_reg_imm);
7548 %}
7549
7550 // Register Shift Left
7551 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7552 match(Set dst (LShiftL src1 src2));
7553
7554 size(4);
7555 format %{ "SLLX $src1,$src2,$dst" %}
7556 opcode(Assembler::sllx_op3, Assembler::arith_op);
7557 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7558 ins_pipe(ialu_reg_reg);
7559 %}
7560
7561 // Register Shift Left Immediate
7562 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7563 match(Set dst (LShiftL src1 src2));
7564
7565 size(4);
7566 format %{ "SLLX $src1,$src2,$dst" %}
7567 opcode(Assembler::sllx_op3, Assembler::arith_op);
7568 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7569 ins_pipe(ialu_reg_imm);
7570 %}
7571
7572 // Register Arithmetic Shift Right
7573 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7574 match(Set dst (RShiftI src1 src2));
7575 size(4);
7576 format %{ "SRA $src1,$src2,$dst" %}
7577 opcode(Assembler::sra_op3, Assembler::arith_op);
7578 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7579 ins_pipe(ialu_reg_reg);
7580 %}
7581
7582 // Register Arithmetic Shift Right Immediate
7583 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7584 match(Set dst (RShiftI src1 src2));
7585
7586 size(4);
7587 format %{ "SRA $src1,$src2,$dst" %}
7588 opcode(Assembler::sra_op3, Assembler::arith_op);
7589 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7590 ins_pipe(ialu_reg_imm);
7591 %}
7592
7593 // Register Shift Right Arithmatic Long
7594 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7595 match(Set dst (RShiftL src1 src2));
7596
7597 size(4);
7598 format %{ "SRAX $src1,$src2,$dst" %}
7599 opcode(Assembler::srax_op3, Assembler::arith_op);
7600 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7601 ins_pipe(ialu_reg_reg);
7602 %}
7603
7604 // Register Shift Left Immediate
7605 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7606 match(Set dst (RShiftL src1 src2));
7607
7608 size(4);
7609 format %{ "SRAX $src1,$src2,$dst" %}
7610 opcode(Assembler::srax_op3, Assembler::arith_op);
7611 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7612 ins_pipe(ialu_reg_imm);
7613 %}
7614
7615 // Register Shift Right
7616 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7617 match(Set dst (URShiftI src1 src2));
7618
7619 size(4);
7620 format %{ "SRL $src1,$src2,$dst" %}
7621 opcode(Assembler::srl_op3, Assembler::arith_op);
7622 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7623 ins_pipe(ialu_reg_reg);
7624 %}
7625
7626 // Register Shift Right Immediate
7627 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7628 match(Set dst (URShiftI src1 src2));
7629
7630 size(4);
7631 format %{ "SRL $src1,$src2,$dst" %}
7632 opcode(Assembler::srl_op3, Assembler::arith_op);
7633 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7634 ins_pipe(ialu_reg_imm);
7635 %}
7636
7637 // Register Shift Right
7638 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7639 match(Set dst (URShiftL src1 src2));
7640
7641 size(4);
7642 format %{ "SRLX $src1,$src2,$dst" %}
7643 opcode(Assembler::srlx_op3, Assembler::arith_op);
7644 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7645 ins_pipe(ialu_reg_reg);
7646 %}
7647
7648 // Register Shift Right Immediate
7649 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7650 match(Set dst (URShiftL src1 src2));
7651
7652 size(4);
7653 format %{ "SRLX $src1,$src2,$dst" %}
7654 opcode(Assembler::srlx_op3, Assembler::arith_op);
7655 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7656 ins_pipe(ialu_reg_imm);
7657 %}
7658
7659 // Register Shift Right Immediate with a CastP2X
7660 #ifdef _LP64
7661 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7662 match(Set dst (URShiftL (CastP2X src1) src2));
7663 size(4);
7664 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7665 opcode(Assembler::srlx_op3, Assembler::arith_op);
7666 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7667 ins_pipe(ialu_reg_imm);
7668 %}
7669 #else
7670 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7671 match(Set dst (URShiftI (CastP2X src1) src2));
7672 size(4);
7673 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7674 opcode(Assembler::srl_op3, Assembler::arith_op);
7675 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7676 ins_pipe(ialu_reg_imm);
7677 %}
7678 #endif
7679
7680
7681 //----------Floating Point Arithmetic Instructions-----------------------------
7682
7683 // Add float single precision
7684 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7685 match(Set dst (AddF src1 src2));
7686
7687 size(4);
7688 format %{ "FADDS $src1,$src2,$dst" %}
7689 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7690 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7691 ins_pipe(faddF_reg_reg);
7692 %}
7693
7694 // Add float double precision
7695 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7696 match(Set dst (AddD src1 src2));
7697
7698 size(4);
7699 format %{ "FADDD $src1,$src2,$dst" %}
7700 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7701 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7702 ins_pipe(faddD_reg_reg);
7703 %}
7704
7705 // Sub float single precision
7706 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7707 match(Set dst (SubF src1 src2));
7708
7709 size(4);
7710 format %{ "FSUBS $src1,$src2,$dst" %}
7711 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7712 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7713 ins_pipe(faddF_reg_reg);
7714 %}
7715
7716 // Sub float double precision
7717 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7718 match(Set dst (SubD src1 src2));
7719
7720 size(4);
7721 format %{ "FSUBD $src1,$src2,$dst" %}
7722 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7723 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7724 ins_pipe(faddD_reg_reg);
7725 %}
7726
7727 // Mul float single precision
7728 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7729 match(Set dst (MulF src1 src2));
7730
7731 size(4);
7732 format %{ "FMULS $src1,$src2,$dst" %}
7733 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7734 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7735 ins_pipe(fmulF_reg_reg);
7736 %}
7737
7738 // Mul float double precision
7739 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7740 match(Set dst (MulD src1 src2));
7741
7742 size(4);
7743 format %{ "FMULD $src1,$src2,$dst" %}
7744 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7745 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7746 ins_pipe(fmulD_reg_reg);
7747 %}
7748
7749 // Div float single precision
7750 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7751 match(Set dst (DivF src1 src2));
7752
7753 size(4);
7754 format %{ "FDIVS $src1,$src2,$dst" %}
7755 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7756 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7757 ins_pipe(fdivF_reg_reg);
7758 %}
7759
7760 // Div float double precision
7761 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7762 match(Set dst (DivD src1 src2));
7763
7764 size(4);
7765 format %{ "FDIVD $src1,$src2,$dst" %}
7766 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7767 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7768 ins_pipe(fdivD_reg_reg);
7769 %}
7770
7771 // Absolute float double precision
7772 instruct absD_reg(regD dst, regD src) %{
7773 match(Set dst (AbsD src));
7774
7775 format %{ "FABSd $src,$dst" %}
7776 ins_encode(fabsd(dst, src));
7777 ins_pipe(faddD_reg);
7778 %}
7779
7780 // Absolute float single precision
7781 instruct absF_reg(regF dst, regF src) %{
7782 match(Set dst (AbsF src));
7783
7784 format %{ "FABSs $src,$dst" %}
7785 ins_encode(fabss(dst, src));
7786 ins_pipe(faddF_reg);
7787 %}
7788
7789 instruct negF_reg(regF dst, regF src) %{
7790 match(Set dst (NegF src));
7791
7792 size(4);
7793 format %{ "FNEGs $src,$dst" %}
7794 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7795 ins_encode(form3_opf_rs2F_rdF(src, dst));
7796 ins_pipe(faddF_reg);
7797 %}
7798
7799 instruct negD_reg(regD dst, regD src) %{
7800 match(Set dst (NegD src));
7801
7802 format %{ "FNEGd $src,$dst" %}
7803 ins_encode(fnegd(dst, src));
7804 ins_pipe(faddD_reg);
7805 %}
7806
7807 // Sqrt float double precision
7808 instruct sqrtF_reg_reg(regF dst, regF src) %{
7809 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7810
7811 size(4);
7812 format %{ "FSQRTS $src,$dst" %}
7813 ins_encode(fsqrts(dst, src));
7814 ins_pipe(fdivF_reg_reg);
7815 %}
7816
7817 // Sqrt float double precision
7818 instruct sqrtD_reg_reg(regD dst, regD src) %{
7819 match(Set dst (SqrtD src));
7820
7821 size(4);
7822 format %{ "FSQRTD $src,$dst" %}
7823 ins_encode(fsqrtd(dst, src));
7824 ins_pipe(fdivD_reg_reg);
7825 %}
7826
7827 //----------Logical Instructions-----------------------------------------------
7828 // And Instructions
7829 // Register And
7830 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7831 match(Set dst (AndI src1 src2));
7832
7833 size(4);
7834 format %{ "AND $src1,$src2,$dst" %}
7835 opcode(Assembler::and_op3, Assembler::arith_op);
7836 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7837 ins_pipe(ialu_reg_reg);
7838 %}
7839
7840 // Immediate And
7841 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7842 match(Set dst (AndI src1 src2));
7843
7844 size(4);
7845 format %{ "AND $src1,$src2,$dst" %}
7846 opcode(Assembler::and_op3, Assembler::arith_op);
7847 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7848 ins_pipe(ialu_reg_imm);
7849 %}
7850
7851 // Register And Long
7852 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7853 match(Set dst (AndL src1 src2));
7854
7855 ins_cost(DEFAULT_COST);
7856 size(4);
7857 format %{ "AND $src1,$src2,$dst\t! long" %}
7858 opcode(Assembler::and_op3, Assembler::arith_op);
7859 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7860 ins_pipe(ialu_reg_reg);
7861 %}
7862
7863 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7864 match(Set dst (AndL src1 con));
7865
7866 ins_cost(DEFAULT_COST);
7867 size(4);
7868 format %{ "AND $src1,$con,$dst\t! long" %}
7869 opcode(Assembler::and_op3, Assembler::arith_op);
7870 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7871 ins_pipe(ialu_reg_imm);
7872 %}
7873
7874 // Or Instructions
7875 // Register Or
7876 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7877 match(Set dst (OrI src1 src2));
7878
7879 size(4);
7880 format %{ "OR $src1,$src2,$dst" %}
7881 opcode(Assembler::or_op3, Assembler::arith_op);
7882 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7883 ins_pipe(ialu_reg_reg);
7884 %}
7885
7886 // Immediate Or
7887 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7888 match(Set dst (OrI src1 src2));
7889
7890 size(4);
7891 format %{ "OR $src1,$src2,$dst" %}
7892 opcode(Assembler::or_op3, Assembler::arith_op);
7893 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7894 ins_pipe(ialu_reg_imm);
7895 %}
7896
7897 // Register Or Long
7898 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7899 match(Set dst (OrL src1 src2));
7900
7901 ins_cost(DEFAULT_COST);
7902 size(4);
7903 format %{ "OR $src1,$src2,$dst\t! long" %}
7904 opcode(Assembler::or_op3, Assembler::arith_op);
7905 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7906 ins_pipe(ialu_reg_reg);
7907 %}
7908
7909 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7910 match(Set dst (OrL src1 con));
7911 ins_cost(DEFAULT_COST*2);
7912
7913 ins_cost(DEFAULT_COST);
7914 size(4);
7915 format %{ "OR $src1,$con,$dst\t! long" %}
7916 opcode(Assembler::or_op3, Assembler::arith_op);
7917 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7918 ins_pipe(ialu_reg_imm);
7919 %}
7920
7921 #ifndef _LP64
7922
7923 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
7924 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
7925 match(Set dst (OrI src1 (CastP2X src2)));
7926
7927 size(4);
7928 format %{ "OR $src1,$src2,$dst" %}
7929 opcode(Assembler::or_op3, Assembler::arith_op);
7930 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7931 ins_pipe(ialu_reg_reg);
7932 %}
7933
7934 #else
7935
7936 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
7937 match(Set dst (OrL src1 (CastP2X src2)));
7938
7939 ins_cost(DEFAULT_COST);
7940 size(4);
7941 format %{ "OR $src1,$src2,$dst\t! long" %}
7942 opcode(Assembler::or_op3, Assembler::arith_op);
7943 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7944 ins_pipe(ialu_reg_reg);
7945 %}
7946
7947 #endif
7948
7949 // Xor Instructions
7950 // Register Xor
7951 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7952 match(Set dst (XorI src1 src2));
7953
7954 size(4);
7955 format %{ "XOR $src1,$src2,$dst" %}
7956 opcode(Assembler::xor_op3, Assembler::arith_op);
7957 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7958 ins_pipe(ialu_reg_reg);
7959 %}
7960
7961 // Immediate Xor
7962 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7963 match(Set dst (XorI src1 src2));
7964
7965 size(4);
7966 format %{ "XOR $src1,$src2,$dst" %}
7967 opcode(Assembler::xor_op3, Assembler::arith_op);
7968 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7969 ins_pipe(ialu_reg_imm);
7970 %}
7971
7972 // Register Xor Long
7973 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7974 match(Set dst (XorL src1 src2));
7975
7976 ins_cost(DEFAULT_COST);
7977 size(4);
7978 format %{ "XOR $src1,$src2,$dst\t! long" %}
7979 opcode(Assembler::xor_op3, Assembler::arith_op);
7980 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7981 ins_pipe(ialu_reg_reg);
7982 %}
7983
7984 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7985 match(Set dst (XorL src1 con));
7986
7987 ins_cost(DEFAULT_COST);
7988 size(4);
7989 format %{ "XOR $src1,$con,$dst\t! long" %}
7990 opcode(Assembler::xor_op3, Assembler::arith_op);
7991 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7992 ins_pipe(ialu_reg_imm);
7993 %}
7994
7995 //----------Convert to Boolean-------------------------------------------------
7996 // Nice hack for 32-bit tests but doesn't work for
7997 // 64-bit pointers.
7998 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
7999 match(Set dst (Conv2B src));
8000 effect( KILL ccr );
8001 ins_cost(DEFAULT_COST*2);
8002 format %{ "CMP R_G0,$src\n\t"
8003 "ADDX R_G0,0,$dst" %}
8004 ins_encode( enc_to_bool( src, dst ) );
8005 ins_pipe(ialu_reg_ialu);
8006 %}
8007
8008 #ifndef _LP64
8009 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8010 match(Set dst (Conv2B src));
8011 effect( KILL ccr );
8012 ins_cost(DEFAULT_COST*2);
8013 format %{ "CMP R_G0,$src\n\t"
8014 "ADDX R_G0,0,$dst" %}
8015 ins_encode( enc_to_bool( src, dst ) );
8016 ins_pipe(ialu_reg_ialu);
8017 %}
8018 #else
8019 instruct convP2B( iRegI dst, iRegP src ) %{
8020 match(Set dst (Conv2B src));
8021 ins_cost(DEFAULT_COST*2);
8022 format %{ "MOV $src,$dst\n\t"
8023 "MOVRNZ $src,1,$dst" %}
8024 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8025 ins_pipe(ialu_clr_and_mover);
8026 %}
8027 #endif
8028
8029 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8030 match(Set dst (CmpLTMask src zero));
8031 effect(KILL ccr);
8032 size(4);
8033 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8034 ins_encode %{
8035 __ sra($src$$Register, 31, $dst$$Register);
8036 %}
8037 ins_pipe(ialu_reg_imm);
8038 %}
8039
8040 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8041 match(Set dst (CmpLTMask p q));
8042 effect( KILL ccr );
8043 ins_cost(DEFAULT_COST*4);
8044 format %{ "CMP $p,$q\n\t"
8045 "MOV #0,$dst\n\t"
8046 "BLT,a .+8\n\t"
8047 "MOV #-1,$dst" %}
8048 ins_encode( enc_ltmask(p,q,dst) );
8049 ins_pipe(ialu_reg_reg_ialu);
8050 %}
8051
8052 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8053 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8054 effect(KILL ccr, TEMP tmp);
8055 ins_cost(DEFAULT_COST*3);
8056
8057 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8058 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8059 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8060 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8061 ins_pipe(cadd_cmpltmask);
8062 %}
8063
8064 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8065 match(Set p (AndI (CmpLTMask p q) y));
8066 effect(KILL ccr);
8067 ins_cost(DEFAULT_COST*3);
8068
8069 format %{ "CMP $p,$q\n\t"
8070 "MOV $y,$p\n\t"
8071 "MOVge G0,$p" %}
8072 ins_encode %{
8073 __ cmp($p$$Register, $q$$Register);
8074 __ mov($y$$Register, $p$$Register);
8075 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8076 %}
8077 ins_pipe(ialu_reg_reg_ialu);
8078 %}
8079
8080 //-----------------------------------------------------------------
8081 // Direct raw moves between float and general registers using VIS3.
8082
8083 // ins_pipe(faddF_reg);
8084 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8085 predicate(UseVIS >= 3);
8086 match(Set dst (MoveF2I src));
8087
8088 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8089 ins_encode %{
8090 __ movstouw($src$$FloatRegister, $dst$$Register);
8091 %}
8092 ins_pipe(ialu_reg_reg);
8093 %}
8094
8095 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8096 predicate(UseVIS >= 3);
8097 match(Set dst (MoveI2F src));
8098
8099 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8100 ins_encode %{
8101 __ movwtos($src$$Register, $dst$$FloatRegister);
8102 %}
8103 ins_pipe(ialu_reg_reg);
8104 %}
8105
8106 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8107 predicate(UseVIS >= 3);
8108 match(Set dst (MoveD2L src));
8109
8110 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8111 ins_encode %{
8112 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8113 %}
8114 ins_pipe(ialu_reg_reg);
8115 %}
8116
8117 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8118 predicate(UseVIS >= 3);
8119 match(Set dst (MoveL2D src));
8120
8121 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8122 ins_encode %{
8123 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8124 %}
8125 ins_pipe(ialu_reg_reg);
8126 %}
8127
8128
8129 // Raw moves between float and general registers using stack.
8130
8131 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8132 match(Set dst (MoveF2I src));
8133 effect(DEF dst, USE src);
8134 ins_cost(MEMORY_REF_COST);
8135
8136 size(4);
8137 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8138 opcode(Assembler::lduw_op3);
8139 ins_encode(simple_form3_mem_reg( src, dst ) );
8140 ins_pipe(iload_mem);
8141 %}
8142
8143 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8144 match(Set dst (MoveI2F src));
8145 effect(DEF dst, USE src);
8146 ins_cost(MEMORY_REF_COST);
8147
8148 size(4);
8149 format %{ "LDF $src,$dst\t! MoveI2F" %}
8150 opcode(Assembler::ldf_op3);
8151 ins_encode(simple_form3_mem_reg(src, dst));
8152 ins_pipe(floadF_stk);
8153 %}
8154
8155 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8156 match(Set dst (MoveD2L src));
8157 effect(DEF dst, USE src);
8158 ins_cost(MEMORY_REF_COST);
8159
8160 size(4);
8161 format %{ "LDX $src,$dst\t! MoveD2L" %}
8162 opcode(Assembler::ldx_op3);
8163 ins_encode(simple_form3_mem_reg( src, dst ) );
8164 ins_pipe(iload_mem);
8165 %}
8166
8167 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8168 match(Set dst (MoveL2D src));
8169 effect(DEF dst, USE src);
8170 ins_cost(MEMORY_REF_COST);
8171
8172 size(4);
8173 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8174 opcode(Assembler::lddf_op3);
8175 ins_encode(simple_form3_mem_reg(src, dst));
8176 ins_pipe(floadD_stk);
8177 %}
8178
8179 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8180 match(Set dst (MoveF2I src));
8181 effect(DEF dst, USE src);
8182 ins_cost(MEMORY_REF_COST);
8183
8184 size(4);
8185 format %{ "STF $src,$dst\t! MoveF2I" %}
8186 opcode(Assembler::stf_op3);
8187 ins_encode(simple_form3_mem_reg(dst, src));
8188 ins_pipe(fstoreF_stk_reg);
8189 %}
8190
8191 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8192 match(Set dst (MoveI2F src));
8193 effect(DEF dst, USE src);
8194 ins_cost(MEMORY_REF_COST);
8195
8196 size(4);
8197 format %{ "STW $src,$dst\t! MoveI2F" %}
8198 opcode(Assembler::stw_op3);
8199 ins_encode(simple_form3_mem_reg( dst, src ) );
8200 ins_pipe(istore_mem_reg);
8201 %}
8202
8203 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8204 match(Set dst (MoveD2L src));
8205 effect(DEF dst, USE src);
8206 ins_cost(MEMORY_REF_COST);
8207
8208 size(4);
8209 format %{ "STDF $src,$dst\t! MoveD2L" %}
8210 opcode(Assembler::stdf_op3);
8211 ins_encode(simple_form3_mem_reg(dst, src));
8212 ins_pipe(fstoreD_stk_reg);
8213 %}
8214
8215 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8216 match(Set dst (MoveL2D src));
8217 effect(DEF dst, USE src);
8218 ins_cost(MEMORY_REF_COST);
8219
8220 size(4);
8221 format %{ "STX $src,$dst\t! MoveL2D" %}
8222 opcode(Assembler::stx_op3);
8223 ins_encode(simple_form3_mem_reg( dst, src ) );
8224 ins_pipe(istore_mem_reg);
8225 %}
8226
8227
8228 //----------Arithmetic Conversion Instructions---------------------------------
8229 // The conversions operations are all Alpha sorted. Please keep it that way!
8230
8231 instruct convD2F_reg(regF dst, regD src) %{
8232 match(Set dst (ConvD2F src));
8233 size(4);
8234 format %{ "FDTOS $src,$dst" %}
8235 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8236 ins_encode(form3_opf_rs2D_rdF(src, dst));
8237 ins_pipe(fcvtD2F);
8238 %}
8239
8240
8241 // Convert a double to an int in a float register.
8242 // If the double is a NAN, stuff a zero in instead.
8243 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8244 effect(DEF dst, USE src, KILL fcc0);
8245 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8246 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8247 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8248 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8249 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8250 "skip:" %}
8251 ins_encode(form_d2i_helper(src,dst));
8252 ins_pipe(fcvtD2I);
8253 %}
8254
8255 instruct convD2I_stk(stackSlotI dst, regD src) %{
8256 match(Set dst (ConvD2I src));
8257 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8258 expand %{
8259 regF tmp;
8260 convD2I_helper(tmp, src);
8261 regF_to_stkI(dst, tmp);
8262 %}
8263 %}
8264
8265 instruct convD2I_reg(iRegI dst, regD src) %{
8266 predicate(UseVIS >= 3);
8267 match(Set dst (ConvD2I src));
8268 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8269 expand %{
8270 regF tmp;
8271 convD2I_helper(tmp, src);
8272 MoveF2I_reg_reg(dst, tmp);
8273 %}
8274 %}
8275
8276
8277 // Convert a double to a long in a double register.
8278 // If the double is a NAN, stuff a zero in instead.
8279 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8280 effect(DEF dst, USE src, KILL fcc0);
8281 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8282 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8283 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8284 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8285 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8286 "skip:" %}
8287 ins_encode(form_d2l_helper(src,dst));
8288 ins_pipe(fcvtD2L);
8289 %}
8290
8291 instruct convD2L_stk(stackSlotL dst, regD src) %{
8292 match(Set dst (ConvD2L src));
8293 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8294 expand %{
8295 regD tmp;
8296 convD2L_helper(tmp, src);
8297 regD_to_stkL(dst, tmp);
8298 %}
8299 %}
8300
8301 instruct convD2L_reg(iRegL dst, regD src) %{
8302 predicate(UseVIS >= 3);
8303 match(Set dst (ConvD2L src));
8304 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8305 expand %{
8306 regD tmp;
8307 convD2L_helper(tmp, src);
8308 MoveD2L_reg_reg(dst, tmp);
8309 %}
8310 %}
8311
8312
8313 instruct convF2D_reg(regD dst, regF src) %{
8314 match(Set dst (ConvF2D src));
8315 format %{ "FSTOD $src,$dst" %}
8316 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8317 ins_encode(form3_opf_rs2F_rdD(src, dst));
8318 ins_pipe(fcvtF2D);
8319 %}
8320
8321
8322 // Convert a float to an int in a float register.
8323 // If the float is a NAN, stuff a zero in instead.
8324 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8325 effect(DEF dst, USE src, KILL fcc0);
8326 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8327 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8328 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8329 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8330 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8331 "skip:" %}
8332 ins_encode(form_f2i_helper(src,dst));
8333 ins_pipe(fcvtF2I);
8334 %}
8335
8336 instruct convF2I_stk(stackSlotI dst, regF src) %{
8337 match(Set dst (ConvF2I src));
8338 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8339 expand %{
8340 regF tmp;
8341 convF2I_helper(tmp, src);
8342 regF_to_stkI(dst, tmp);
8343 %}
8344 %}
8345
8346 instruct convF2I_reg(iRegI dst, regF src) %{
8347 predicate(UseVIS >= 3);
8348 match(Set dst (ConvF2I src));
8349 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8350 expand %{
8351 regF tmp;
8352 convF2I_helper(tmp, src);
8353 MoveF2I_reg_reg(dst, tmp);
8354 %}
8355 %}
8356
8357
8358 // Convert a float to a long in a float register.
8359 // If the float is a NAN, stuff a zero in instead.
8360 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8361 effect(DEF dst, USE src, KILL fcc0);
8362 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8363 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8364 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8365 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8366 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8367 "skip:" %}
8368 ins_encode(form_f2l_helper(src,dst));
8369 ins_pipe(fcvtF2L);
8370 %}
8371
8372 instruct convF2L_stk(stackSlotL dst, regF src) %{
8373 match(Set dst (ConvF2L src));
8374 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8375 expand %{
8376 regD tmp;
8377 convF2L_helper(tmp, src);
8378 regD_to_stkL(dst, tmp);
8379 %}
8380 %}
8381
8382 instruct convF2L_reg(iRegL dst, regF src) %{
8383 predicate(UseVIS >= 3);
8384 match(Set dst (ConvF2L src));
8385 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8386 expand %{
8387 regD tmp;
8388 convF2L_helper(tmp, src);
8389 MoveD2L_reg_reg(dst, tmp);
8390 %}
8391 %}
8392
8393
8394 instruct convI2D_helper(regD dst, regF tmp) %{
8395 effect(USE tmp, DEF dst);
8396 format %{ "FITOD $tmp,$dst" %}
8397 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8398 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8399 ins_pipe(fcvtI2D);
8400 %}
8401
8402 instruct convI2D_stk(stackSlotI src, regD dst) %{
8403 match(Set dst (ConvI2D src));
8404 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8405 expand %{
8406 regF tmp;
8407 stkI_to_regF(tmp, src);
8408 convI2D_helper(dst, tmp);
8409 %}
8410 %}
8411
8412 instruct convI2D_reg(regD_low dst, iRegI src) %{
8413 predicate(UseVIS >= 3);
8414 match(Set dst (ConvI2D src));
8415 expand %{
8416 regF tmp;
8417 MoveI2F_reg_reg(tmp, src);
8418 convI2D_helper(dst, tmp);
8419 %}
8420 %}
8421
8422 instruct convI2D_mem(regD_low dst, memory mem) %{
8423 match(Set dst (ConvI2D (LoadI mem)));
8424 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8425 size(8);
8426 format %{ "LDF $mem,$dst\n\t"
8427 "FITOD $dst,$dst" %}
8428 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8429 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8430 ins_pipe(floadF_mem);
8431 %}
8432
8433
8434 instruct convI2F_helper(regF dst, regF tmp) %{
8435 effect(DEF dst, USE tmp);
8436 format %{ "FITOS $tmp,$dst" %}
8437 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8438 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8439 ins_pipe(fcvtI2F);
8440 %}
8441
8442 instruct convI2F_stk(regF dst, stackSlotI src) %{
8443 match(Set dst (ConvI2F src));
8444 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8445 expand %{
8446 regF tmp;
8447 stkI_to_regF(tmp,src);
8448 convI2F_helper(dst, tmp);
8449 %}
8450 %}
8451
8452 instruct convI2F_reg(regF dst, iRegI src) %{
8453 predicate(UseVIS >= 3);
8454 match(Set dst (ConvI2F src));
8455 ins_cost(DEFAULT_COST);
8456 expand %{
8457 regF tmp;
8458 MoveI2F_reg_reg(tmp, src);
8459 convI2F_helper(dst, tmp);
8460 %}
8461 %}
8462
8463 instruct convI2F_mem( regF dst, memory mem ) %{
8464 match(Set dst (ConvI2F (LoadI mem)));
8465 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8466 size(8);
8467 format %{ "LDF $mem,$dst\n\t"
8468 "FITOS $dst,$dst" %}
8469 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8470 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8471 ins_pipe(floadF_mem);
8472 %}
8473
8474
8475 instruct convI2L_reg(iRegL dst, iRegI src) %{
8476 match(Set dst (ConvI2L src));
8477 size(4);
8478 format %{ "SRA $src,0,$dst\t! int->long" %}
8479 opcode(Assembler::sra_op3, Assembler::arith_op);
8480 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8481 ins_pipe(ialu_reg_reg);
8482 %}
8483
8484 // Zero-extend convert int to long
8485 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8486 match(Set dst (AndL (ConvI2L src) mask) );
8487 size(4);
8488 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8489 opcode(Assembler::srl_op3, Assembler::arith_op);
8490 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8491 ins_pipe(ialu_reg_reg);
8492 %}
8493
8494 // Zero-extend long
8495 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8496 match(Set dst (AndL src mask) );
8497 size(4);
8498 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8499 opcode(Assembler::srl_op3, Assembler::arith_op);
8500 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8501 ins_pipe(ialu_reg_reg);
8502 %}
8503
8504
8505 //-----------
8506 // Long to Double conversion using V8 opcodes.
8507 // Still useful because cheetah traps and becomes
8508 // amazingly slow for some common numbers.
8509
8510 // Magic constant, 0x43300000
8511 instruct loadConI_x43300000(iRegI dst) %{
8512 effect(DEF dst);
8513 size(4);
8514 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8515 ins_encode(SetHi22(0x43300000, dst));
8516 ins_pipe(ialu_none);
8517 %}
8518
8519 // Magic constant, 0x41f00000
8520 instruct loadConI_x41f00000(iRegI dst) %{
8521 effect(DEF dst);
8522 size(4);
8523 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8524 ins_encode(SetHi22(0x41f00000, dst));
8525 ins_pipe(ialu_none);
8526 %}
8527
8528 // Construct a double from two float halves
8529 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8530 effect(DEF dst, USE src1, USE src2);
8531 size(8);
8532 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8533 "FMOVS $src2.lo,$dst.lo" %}
8534 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8535 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8536 ins_pipe(faddD_reg_reg);
8537 %}
8538
8539 // Convert integer in high half of a double register (in the lower half of
8540 // the double register file) to double
8541 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8542 effect(DEF dst, USE src);
8543 size(4);
8544 format %{ "FITOD $src,$dst" %}
8545 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8546 ins_encode(form3_opf_rs2D_rdD(src, dst));
8547 ins_pipe(fcvtLHi2D);
8548 %}
8549
8550 // Add float double precision
8551 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8552 effect(DEF dst, USE src1, USE src2);
8553 size(4);
8554 format %{ "FADDD $src1,$src2,$dst" %}
8555 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8556 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8557 ins_pipe(faddD_reg_reg);
8558 %}
8559
8560 // Sub float double precision
8561 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8562 effect(DEF dst, USE src1, USE src2);
8563 size(4);
8564 format %{ "FSUBD $src1,$src2,$dst" %}
8565 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8566 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8567 ins_pipe(faddD_reg_reg);
8568 %}
8569
8570 // Mul float double precision
8571 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8572 effect(DEF dst, USE src1, USE src2);
8573 size(4);
8574 format %{ "FMULD $src1,$src2,$dst" %}
8575 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8576 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8577 ins_pipe(fmulD_reg_reg);
8578 %}
8579
8580 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8581 match(Set dst (ConvL2D src));
8582 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8583
8584 expand %{
8585 regD_low tmpsrc;
8586 iRegI ix43300000;
8587 iRegI ix41f00000;
8588 stackSlotL lx43300000;
8589 stackSlotL lx41f00000;
8590 regD_low dx43300000;
8591 regD dx41f00000;
8592 regD tmp1;
8593 regD_low tmp2;
8594 regD tmp3;
8595 regD tmp4;
8596
8597 stkL_to_regD(tmpsrc, src);
8598
8599 loadConI_x43300000(ix43300000);
8600 loadConI_x41f00000(ix41f00000);
8601 regI_to_stkLHi(lx43300000, ix43300000);
8602 regI_to_stkLHi(lx41f00000, ix41f00000);
8603 stkL_to_regD(dx43300000, lx43300000);
8604 stkL_to_regD(dx41f00000, lx41f00000);
8605
8606 convI2D_regDHi_regD(tmp1, tmpsrc);
8607 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8608 subD_regD_regD(tmp3, tmp2, dx43300000);
8609 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8610 addD_regD_regD(dst, tmp3, tmp4);
8611 %}
8612 %}
8613
8614 // Long to Double conversion using fast fxtof
8615 instruct convL2D_helper(regD dst, regD tmp) %{
8616 effect(DEF dst, USE tmp);
8617 size(4);
8618 format %{ "FXTOD $tmp,$dst" %}
8619 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8620 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8621 ins_pipe(fcvtL2D);
8622 %}
8623
8624 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8625 predicate(VM_Version::has_fast_fxtof());
8626 match(Set dst (ConvL2D src));
8627 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8628 expand %{
8629 regD tmp;
8630 stkL_to_regD(tmp, src);
8631 convL2D_helper(dst, tmp);
8632 %}
8633 %}
8634
8635 instruct convL2D_reg(regD dst, iRegL src) %{
8636 predicate(UseVIS >= 3);
8637 match(Set dst (ConvL2D src));
8638 expand %{
8639 regD tmp;
8640 MoveL2D_reg_reg(tmp, src);
8641 convL2D_helper(dst, tmp);
8642 %}
8643 %}
8644
8645 // Long to Float conversion using fast fxtof
8646 instruct convL2F_helper(regF dst, regD tmp) %{
8647 effect(DEF dst, USE tmp);
8648 size(4);
8649 format %{ "FXTOS $tmp,$dst" %}
8650 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8651 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8652 ins_pipe(fcvtL2F);
8653 %}
8654
8655 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8656 match(Set dst (ConvL2F src));
8657 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8658 expand %{
8659 regD tmp;
8660 stkL_to_regD(tmp, src);
8661 convL2F_helper(dst, tmp);
8662 %}
8663 %}
8664
8665 instruct convL2F_reg(regF dst, iRegL src) %{
8666 predicate(UseVIS >= 3);
8667 match(Set dst (ConvL2F src));
8668 ins_cost(DEFAULT_COST);
8669 expand %{
8670 regD tmp;
8671 MoveL2D_reg_reg(tmp, src);
8672 convL2F_helper(dst, tmp);
8673 %}
8674 %}
8675
8676 //-----------
8677
8678 instruct convL2I_reg(iRegI dst, iRegL src) %{
8679 match(Set dst (ConvL2I src));
8680 #ifndef _LP64
8681 format %{ "MOV $src.lo,$dst\t! long->int" %}
8682 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8683 ins_pipe(ialu_move_reg_I_to_L);
8684 #else
8685 size(4);
8686 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8687 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8688 ins_pipe(ialu_reg);
8689 #endif
8690 %}
8691
8692 // Register Shift Right Immediate
8693 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8694 match(Set dst (ConvL2I (RShiftL src cnt)));
8695
8696 size(4);
8697 format %{ "SRAX $src,$cnt,$dst" %}
8698 opcode(Assembler::srax_op3, Assembler::arith_op);
8699 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8700 ins_pipe(ialu_reg_imm);
8701 %}
8702
8703 //----------Control Flow Instructions------------------------------------------
8704 // Compare Instructions
8705 // Compare Integers
8706 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8707 match(Set icc (CmpI op1 op2));
8708 effect( DEF icc, USE op1, USE op2 );
8709
8710 size(4);
8711 format %{ "CMP $op1,$op2" %}
8712 opcode(Assembler::subcc_op3, Assembler::arith_op);
8713 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8714 ins_pipe(ialu_cconly_reg_reg);
8715 %}
8716
8717 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8718 match(Set icc (CmpU op1 op2));
8719
8720 size(4);
8721 format %{ "CMP $op1,$op2\t! unsigned" %}
8722 opcode(Assembler::subcc_op3, Assembler::arith_op);
8723 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8724 ins_pipe(ialu_cconly_reg_reg);
8725 %}
8726
8727 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8728 match(Set icc (CmpI op1 op2));
8729 effect( DEF icc, USE op1 );
8730
8731 size(4);
8732 format %{ "CMP $op1,$op2" %}
8733 opcode(Assembler::subcc_op3, Assembler::arith_op);
8734 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8735 ins_pipe(ialu_cconly_reg_imm);
8736 %}
8737
8738 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8739 match(Set icc (CmpI (AndI op1 op2) zero));
8740
8741 size(4);
8742 format %{ "BTST $op2,$op1" %}
8743 opcode(Assembler::andcc_op3, Assembler::arith_op);
8744 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8745 ins_pipe(ialu_cconly_reg_reg_zero);
8746 %}
8747
8748 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8749 match(Set icc (CmpI (AndI op1 op2) zero));
8750
8751 size(4);
8752 format %{ "BTST $op2,$op1" %}
8753 opcode(Assembler::andcc_op3, Assembler::arith_op);
8754 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8755 ins_pipe(ialu_cconly_reg_imm_zero);
8756 %}
8757
8758 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8759 match(Set xcc (CmpL op1 op2));
8760 effect( DEF xcc, USE op1, USE op2 );
8761
8762 size(4);
8763 format %{ "CMP $op1,$op2\t\t! long" %}
8764 opcode(Assembler::subcc_op3, Assembler::arith_op);
8765 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8766 ins_pipe(ialu_cconly_reg_reg);
8767 %}
8768
8769 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8770 match(Set xcc (CmpL op1 con));
8771 effect( DEF xcc, USE op1, USE con );
8772
8773 size(4);
8774 format %{ "CMP $op1,$con\t\t! long" %}
8775 opcode(Assembler::subcc_op3, Assembler::arith_op);
8776 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8777 ins_pipe(ialu_cconly_reg_reg);
8778 %}
8779
8780 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8781 match(Set xcc (CmpL (AndL op1 op2) zero));
8782 effect( DEF xcc, USE op1, USE op2 );
8783
8784 size(4);
8785 format %{ "BTST $op1,$op2\t\t! long" %}
8786 opcode(Assembler::andcc_op3, Assembler::arith_op);
8787 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8788 ins_pipe(ialu_cconly_reg_reg);
8789 %}
8790
8791 // useful for checking the alignment of a pointer:
8792 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8793 match(Set xcc (CmpL (AndL op1 con) zero));
8794 effect( DEF xcc, USE op1, USE con );
8795
8796 size(4);
8797 format %{ "BTST $op1,$con\t\t! long" %}
8798 opcode(Assembler::andcc_op3, Assembler::arith_op);
8799 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8800 ins_pipe(ialu_cconly_reg_reg);
8801 %}
8802
8803 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
8804 match(Set icc (CmpU op1 op2));
8805
8806 size(4);
8807 format %{ "CMP $op1,$op2\t! unsigned" %}
8808 opcode(Assembler::subcc_op3, Assembler::arith_op);
8809 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8810 ins_pipe(ialu_cconly_reg_imm);
8811 %}
8812
8813 // Compare Pointers
8814 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8815 match(Set pcc (CmpP op1 op2));
8816
8817 size(4);
8818 format %{ "CMP $op1,$op2\t! ptr" %}
8819 opcode(Assembler::subcc_op3, Assembler::arith_op);
8820 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8821 ins_pipe(ialu_cconly_reg_reg);
8822 %}
8823
8824 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8825 match(Set pcc (CmpP op1 op2));
8826
8827 size(4);
8828 format %{ "CMP $op1,$op2\t! ptr" %}
8829 opcode(Assembler::subcc_op3, Assembler::arith_op);
8830 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8831 ins_pipe(ialu_cconly_reg_imm);
8832 %}
8833
8834 // Compare Narrow oops
8835 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8836 match(Set icc (CmpN op1 op2));
8837
8838 size(4);
8839 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8840 opcode(Assembler::subcc_op3, Assembler::arith_op);
8841 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8842 ins_pipe(ialu_cconly_reg_reg);
8843 %}
8844
8845 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8846 match(Set icc (CmpN op1 op2));
8847
8848 size(4);
8849 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8850 opcode(Assembler::subcc_op3, Assembler::arith_op);
8851 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8852 ins_pipe(ialu_cconly_reg_imm);
8853 %}
8854
8855 //----------Max and Min--------------------------------------------------------
8856 // Min Instructions
8857 // Conditional move for min
8858 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8859 effect( USE_DEF op2, USE op1, USE icc );
8860
8861 size(4);
8862 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8863 opcode(Assembler::less);
8864 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8865 ins_pipe(ialu_reg_flags);
8866 %}
8867
8868 // Min Register with Register.
8869 instruct minI_eReg(iRegI op1, iRegI op2) %{
8870 match(Set op2 (MinI op1 op2));
8871 ins_cost(DEFAULT_COST*2);
8872 expand %{
8873 flagsReg icc;
8874 compI_iReg(icc,op1,op2);
8875 cmovI_reg_lt(op2,op1,icc);
8876 %}
8877 %}
8878
8879 // Max Instructions
8880 // Conditional move for max
8881 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8882 effect( USE_DEF op2, USE op1, USE icc );
8883 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8884 opcode(Assembler::greater);
8885 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8886 ins_pipe(ialu_reg_flags);
8887 %}
8888
8889 // Max Register with Register
8890 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8891 match(Set op2 (MaxI op1 op2));
8892 ins_cost(DEFAULT_COST*2);
8893 expand %{
8894 flagsReg icc;
8895 compI_iReg(icc,op1,op2);
8896 cmovI_reg_gt(op2,op1,icc);
8897 %}
8898 %}
8899
8900
8901 //----------Float Compares----------------------------------------------------
8902 // Compare floating, generate condition code
8903 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8904 match(Set fcc (CmpF src1 src2));
8905
8906 size(4);
8907 format %{ "FCMPs $fcc,$src1,$src2" %}
8908 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8909 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8910 ins_pipe(faddF_fcc_reg_reg_zero);
8911 %}
8912
8913 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8914 match(Set fcc (CmpD src1 src2));
8915
8916 size(4);
8917 format %{ "FCMPd $fcc,$src1,$src2" %}
8918 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8919 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8920 ins_pipe(faddD_fcc_reg_reg_zero);
8921 %}
8922
8923
8924 // Compare floating, generate -1,0,1
8925 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8926 match(Set dst (CmpF3 src1 src2));
8927 effect(KILL fcc0);
8928 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8929 format %{ "fcmpl $dst,$src1,$src2" %}
8930 // Primary = float
8931 opcode( true );
8932 ins_encode( floating_cmp( dst, src1, src2 ) );
8933 ins_pipe( floating_cmp );
8934 %}
8935
8936 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8937 match(Set dst (CmpD3 src1 src2));
8938 effect(KILL fcc0);
8939 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8940 format %{ "dcmpl $dst,$src1,$src2" %}
8941 // Primary = double (not float)
8942 opcode( false );
8943 ins_encode( floating_cmp( dst, src1, src2 ) );
8944 ins_pipe( floating_cmp );
8945 %}
8946
8947 //----------Branches---------------------------------------------------------
8948 // Jump
8949 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8950 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8951 match(Jump switch_val);
8952 effect(TEMP table);
8953
8954 ins_cost(350);
8955
8956 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
8957 "LD [O7 + $switch_val], O7\n\t"
8958 "JUMP O7" %}
8959 ins_encode %{
8960 // Calculate table address into a register.
8961 Register table_reg;
8962 Register label_reg = O7;
8963 // If we are calculating the size of this instruction don't trust
8964 // zero offsets because they might change when
8965 // MachConstantBaseNode decides to optimize the constant table
8966 // base.
8967 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
8968 table_reg = $constanttablebase;
8969 } else {
8970 table_reg = O7;
8971 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
8972 __ add($constanttablebase, con_offset, table_reg);
8973 }
8974
8975 // Jump to base address + switch value
8976 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
8977 __ jmp(label_reg, G0);
8978 __ delayed()->nop();
8979 %}
8980 ins_pipe(ialu_reg_reg);
8981 %}
8982
8983 // Direct Branch. Use V8 version with longer range.
8984 instruct branch(label labl) %{
8985 match(Goto);
8986 effect(USE labl);
8987
8988 size(8);
8989 ins_cost(BRANCH_COST);
8990 format %{ "BA $labl" %}
8991 ins_encode %{
8992 Label* L = $labl$$label;
8993 __ ba(*L);
8994 __ delayed()->nop();
8995 %}
8996 ins_avoid_back_to_back(AVOID_BEFORE);
8997 ins_pipe(br);
8998 %}
8999
9000 // Direct Branch, short with no delay slot
9001 instruct branch_short(label labl) %{
9002 match(Goto);
9003 predicate(UseCBCond);
9004 effect(USE labl);
9005
9006 size(4);
9007 ins_cost(BRANCH_COST);
9008 format %{ "BA $labl\t! short branch" %}
9009 ins_encode %{
9010 Label* L = $labl$$label;
9011 assert(__ use_cbcond(*L), "back to back cbcond");
9012 __ ba_short(*L);
9013 %}
9014 ins_short_branch(1);
9015 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9016 ins_pipe(cbcond_reg_imm);
9017 %}
9018
9019 // Conditional Direct Branch
9020 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9021 match(If cmp icc);
9022 effect(USE labl);
9023
9024 size(8);
9025 ins_cost(BRANCH_COST);
9026 format %{ "BP$cmp $icc,$labl" %}
9027 // Prim = bits 24-22, Secnd = bits 31-30
9028 ins_encode( enc_bp( labl, cmp, icc ) );
9029 ins_avoid_back_to_back(AVOID_BEFORE);
9030 ins_pipe(br_cc);
9031 %}
9032
9033 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9034 match(If cmp icc);
9035 effect(USE labl);
9036
9037 ins_cost(BRANCH_COST);
9038 format %{ "BP$cmp $icc,$labl" %}
9039 // Prim = bits 24-22, Secnd = bits 31-30
9040 ins_encode( enc_bp( labl, cmp, icc ) );
9041 ins_avoid_back_to_back(AVOID_BEFORE);
9042 ins_pipe(br_cc);
9043 %}
9044
9045 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9046 match(If cmp pcc);
9047 effect(USE labl);
9048
9049 size(8);
9050 ins_cost(BRANCH_COST);
9051 format %{ "BP$cmp $pcc,$labl" %}
9052 ins_encode %{
9053 Label* L = $labl$$label;
9054 Assembler::Predict predict_taken =
9055 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9056
9057 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9058 __ delayed()->nop();
9059 %}
9060 ins_avoid_back_to_back(AVOID_BEFORE);
9061 ins_pipe(br_cc);
9062 %}
9063
9064 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9065 match(If cmp fcc);
9066 effect(USE labl);
9067
9068 size(8);
9069 ins_cost(BRANCH_COST);
9070 format %{ "FBP$cmp $fcc,$labl" %}
9071 ins_encode %{
9072 Label* L = $labl$$label;
9073 Assembler::Predict predict_taken =
9074 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9075
9076 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9077 __ delayed()->nop();
9078 %}
9079 ins_avoid_back_to_back(AVOID_BEFORE);
9080 ins_pipe(br_fcc);
9081 %}
9082
9083 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9084 match(CountedLoopEnd cmp icc);
9085 effect(USE labl);
9086
9087 size(8);
9088 ins_cost(BRANCH_COST);
9089 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9090 // Prim = bits 24-22, Secnd = bits 31-30
9091 ins_encode( enc_bp( labl, cmp, icc ) );
9092 ins_avoid_back_to_back(AVOID_BEFORE);
9093 ins_pipe(br_cc);
9094 %}
9095
9096 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9097 match(CountedLoopEnd cmp icc);
9098 effect(USE labl);
9099
9100 size(8);
9101 ins_cost(BRANCH_COST);
9102 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9103 // Prim = bits 24-22, Secnd = bits 31-30
9104 ins_encode( enc_bp( labl, cmp, icc ) );
9105 ins_avoid_back_to_back(AVOID_BEFORE);
9106 ins_pipe(br_cc);
9107 %}
9108
9109 // Compare and branch instructions
9110 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9111 match(If cmp (CmpI op1 op2));
9112 effect(USE labl, KILL icc);
9113
9114 size(12);
9115 ins_cost(BRANCH_COST);
9116 format %{ "CMP $op1,$op2\t! int\n\t"
9117 "BP$cmp $labl" %}
9118 ins_encode %{
9119 Label* L = $labl$$label;
9120 Assembler::Predict predict_taken =
9121 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9122 __ cmp($op1$$Register, $op2$$Register);
9123 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9124 __ delayed()->nop();
9125 %}
9126 ins_pipe(cmp_br_reg_reg);
9127 %}
9128
9129 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9130 match(If cmp (CmpI op1 op2));
9131 effect(USE labl, KILL icc);
9132
9133 size(12);
9134 ins_cost(BRANCH_COST);
9135 format %{ "CMP $op1,$op2\t! int\n\t"
9136 "BP$cmp $labl" %}
9137 ins_encode %{
9138 Label* L = $labl$$label;
9139 Assembler::Predict predict_taken =
9140 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9141 __ cmp($op1$$Register, $op2$$constant);
9142 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9143 __ delayed()->nop();
9144 %}
9145 ins_pipe(cmp_br_reg_imm);
9146 %}
9147
9148 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9149 match(If cmp (CmpU op1 op2));
9150 effect(USE labl, KILL icc);
9151
9152 size(12);
9153 ins_cost(BRANCH_COST);
9154 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9155 "BP$cmp $labl" %}
9156 ins_encode %{
9157 Label* L = $labl$$label;
9158 Assembler::Predict predict_taken =
9159 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9160 __ cmp($op1$$Register, $op2$$Register);
9161 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9162 __ delayed()->nop();
9163 %}
9164 ins_pipe(cmp_br_reg_reg);
9165 %}
9166
9167 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9168 match(If cmp (CmpU op1 op2));
9169 effect(USE labl, KILL icc);
9170
9171 size(12);
9172 ins_cost(BRANCH_COST);
9173 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9174 "BP$cmp $labl" %}
9175 ins_encode %{
9176 Label* L = $labl$$label;
9177 Assembler::Predict predict_taken =
9178 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9179 __ cmp($op1$$Register, $op2$$constant);
9180 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9181 __ delayed()->nop();
9182 %}
9183 ins_pipe(cmp_br_reg_imm);
9184 %}
9185
9186 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9187 match(If cmp (CmpL op1 op2));
9188 effect(USE labl, KILL xcc);
9189
9190 size(12);
9191 ins_cost(BRANCH_COST);
9192 format %{ "CMP $op1,$op2\t! long\n\t"
9193 "BP$cmp $labl" %}
9194 ins_encode %{
9195 Label* L = $labl$$label;
9196 Assembler::Predict predict_taken =
9197 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9198 __ cmp($op1$$Register, $op2$$Register);
9199 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9200 __ delayed()->nop();
9201 %}
9202 ins_pipe(cmp_br_reg_reg);
9203 %}
9204
9205 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9206 match(If cmp (CmpL op1 op2));
9207 effect(USE labl, KILL xcc);
9208
9209 size(12);
9210 ins_cost(BRANCH_COST);
9211 format %{ "CMP $op1,$op2\t! long\n\t"
9212 "BP$cmp $labl" %}
9213 ins_encode %{
9214 Label* L = $labl$$label;
9215 Assembler::Predict predict_taken =
9216 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9217 __ cmp($op1$$Register, $op2$$constant);
9218 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9219 __ delayed()->nop();
9220 %}
9221 ins_pipe(cmp_br_reg_imm);
9222 %}
9223
9224 // Compare Pointers and branch
9225 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9226 match(If cmp (CmpP op1 op2));
9227 effect(USE labl, KILL pcc);
9228
9229 size(12);
9230 ins_cost(BRANCH_COST);
9231 format %{ "CMP $op1,$op2\t! ptr\n\t"
9232 "B$cmp $labl" %}
9233 ins_encode %{
9234 Label* L = $labl$$label;
9235 Assembler::Predict predict_taken =
9236 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9237 __ cmp($op1$$Register, $op2$$Register);
9238 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9239 __ delayed()->nop();
9240 %}
9241 ins_pipe(cmp_br_reg_reg);
9242 %}
9243
9244 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9245 match(If cmp (CmpP op1 null));
9246 effect(USE labl, KILL pcc);
9247
9248 size(12);
9249 ins_cost(BRANCH_COST);
9250 format %{ "CMP $op1,0\t! ptr\n\t"
9251 "B$cmp $labl" %}
9252 ins_encode %{
9253 Label* L = $labl$$label;
9254 Assembler::Predict predict_taken =
9255 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9256 __ cmp($op1$$Register, G0);
9257 // bpr() is not used here since it has shorter distance.
9258 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9259 __ delayed()->nop();
9260 %}
9261 ins_pipe(cmp_br_reg_reg);
9262 %}
9263
9264 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9265 match(If cmp (CmpN op1 op2));
9266 effect(USE labl, KILL icc);
9267
9268 size(12);
9269 ins_cost(BRANCH_COST);
9270 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9271 "BP$cmp $labl" %}
9272 ins_encode %{
9273 Label* L = $labl$$label;
9274 Assembler::Predict predict_taken =
9275 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9276 __ cmp($op1$$Register, $op2$$Register);
9277 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9278 __ delayed()->nop();
9279 %}
9280 ins_pipe(cmp_br_reg_reg);
9281 %}
9282
9283 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9284 match(If cmp (CmpN op1 null));
9285 effect(USE labl, KILL icc);
9286
9287 size(12);
9288 ins_cost(BRANCH_COST);
9289 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9290 "BP$cmp $labl" %}
9291 ins_encode %{
9292 Label* L = $labl$$label;
9293 Assembler::Predict predict_taken =
9294 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9295 __ cmp($op1$$Register, G0);
9296 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9297 __ delayed()->nop();
9298 %}
9299 ins_pipe(cmp_br_reg_reg);
9300 %}
9301
9302 // Loop back branch
9303 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9304 match(CountedLoopEnd cmp (CmpI op1 op2));
9305 effect(USE labl, KILL icc);
9306
9307 size(12);
9308 ins_cost(BRANCH_COST);
9309 format %{ "CMP $op1,$op2\t! int\n\t"
9310 "BP$cmp $labl\t! Loop end" %}
9311 ins_encode %{
9312 Label* L = $labl$$label;
9313 Assembler::Predict predict_taken =
9314 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9315 __ cmp($op1$$Register, $op2$$Register);
9316 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9317 __ delayed()->nop();
9318 %}
9319 ins_pipe(cmp_br_reg_reg);
9320 %}
9321
9322 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9323 match(CountedLoopEnd cmp (CmpI op1 op2));
9324 effect(USE labl, KILL icc);
9325
9326 size(12);
9327 ins_cost(BRANCH_COST);
9328 format %{ "CMP $op1,$op2\t! int\n\t"
9329 "BP$cmp $labl\t! Loop end" %}
9330 ins_encode %{
9331 Label* L = $labl$$label;
9332 Assembler::Predict predict_taken =
9333 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9334 __ cmp($op1$$Register, $op2$$constant);
9335 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9336 __ delayed()->nop();
9337 %}
9338 ins_pipe(cmp_br_reg_imm);
9339 %}
9340
9341 // Short compare and branch instructions
9342 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9343 match(If cmp (CmpI op1 op2));
9344 predicate(UseCBCond);
9345 effect(USE labl, KILL icc);
9346
9347 size(4);
9348 ins_cost(BRANCH_COST);
9349 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9350 ins_encode %{
9351 Label* L = $labl$$label;
9352 assert(__ use_cbcond(*L), "back to back cbcond");
9353 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9354 %}
9355 ins_short_branch(1);
9356 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9357 ins_pipe(cbcond_reg_reg);
9358 %}
9359
9360 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9361 match(If cmp (CmpI op1 op2));
9362 predicate(UseCBCond);
9363 effect(USE labl, KILL icc);
9364
9365 size(4);
9366 ins_cost(BRANCH_COST);
9367 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9368 ins_encode %{
9369 Label* L = $labl$$label;
9370 assert(__ use_cbcond(*L), "back to back cbcond");
9371 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9372 %}
9373 ins_short_branch(1);
9374 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9375 ins_pipe(cbcond_reg_imm);
9376 %}
9377
9378 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9379 match(If cmp (CmpU op1 op2));
9380 predicate(UseCBCond);
9381 effect(USE labl, KILL icc);
9382
9383 size(4);
9384 ins_cost(BRANCH_COST);
9385 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9386 ins_encode %{
9387 Label* L = $labl$$label;
9388 assert(__ use_cbcond(*L), "back to back cbcond");
9389 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9390 %}
9391 ins_short_branch(1);
9392 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9393 ins_pipe(cbcond_reg_reg);
9394 %}
9395
9396 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9397 match(If cmp (CmpU op1 op2));
9398 predicate(UseCBCond);
9399 effect(USE labl, KILL icc);
9400
9401 size(4);
9402 ins_cost(BRANCH_COST);
9403 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9404 ins_encode %{
9405 Label* L = $labl$$label;
9406 assert(__ use_cbcond(*L), "back to back cbcond");
9407 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9408 %}
9409 ins_short_branch(1);
9410 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9411 ins_pipe(cbcond_reg_imm);
9412 %}
9413
9414 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9415 match(If cmp (CmpL op1 op2));
9416 predicate(UseCBCond);
9417 effect(USE labl, KILL xcc);
9418
9419 size(4);
9420 ins_cost(BRANCH_COST);
9421 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9422 ins_encode %{
9423 Label* L = $labl$$label;
9424 assert(__ use_cbcond(*L), "back to back cbcond");
9425 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9426 %}
9427 ins_short_branch(1);
9428 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9429 ins_pipe(cbcond_reg_reg);
9430 %}
9431
9432 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9433 match(If cmp (CmpL op1 op2));
9434 predicate(UseCBCond);
9435 effect(USE labl, KILL xcc);
9436
9437 size(4);
9438 ins_cost(BRANCH_COST);
9439 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9440 ins_encode %{
9441 Label* L = $labl$$label;
9442 assert(__ use_cbcond(*L), "back to back cbcond");
9443 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9444 %}
9445 ins_short_branch(1);
9446 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9447 ins_pipe(cbcond_reg_imm);
9448 %}
9449
9450 // Compare Pointers and branch
9451 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9452 match(If cmp (CmpP op1 op2));
9453 predicate(UseCBCond);
9454 effect(USE labl, KILL pcc);
9455
9456 size(4);
9457 ins_cost(BRANCH_COST);
9458 #ifdef _LP64
9459 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9460 #else
9461 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9462 #endif
9463 ins_encode %{
9464 Label* L = $labl$$label;
9465 assert(__ use_cbcond(*L), "back to back cbcond");
9466 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9467 %}
9468 ins_short_branch(1);
9469 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9470 ins_pipe(cbcond_reg_reg);
9471 %}
9472
9473 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9474 match(If cmp (CmpP op1 null));
9475 predicate(UseCBCond);
9476 effect(USE labl, KILL pcc);
9477
9478 size(4);
9479 ins_cost(BRANCH_COST);
9480 #ifdef _LP64
9481 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9482 #else
9483 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9484 #endif
9485 ins_encode %{
9486 Label* L = $labl$$label;
9487 assert(__ use_cbcond(*L), "back to back cbcond");
9488 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9489 %}
9490 ins_short_branch(1);
9491 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9492 ins_pipe(cbcond_reg_reg);
9493 %}
9494
9495 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9496 match(If cmp (CmpN op1 op2));
9497 predicate(UseCBCond);
9498 effect(USE labl, KILL icc);
9499
9500 size(4);
9501 ins_cost(BRANCH_COST);
9502 format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %}
9503 ins_encode %{
9504 Label* L = $labl$$label;
9505 assert(__ use_cbcond(*L), "back to back cbcond");
9506 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9507 %}
9508 ins_short_branch(1);
9509 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9510 ins_pipe(cbcond_reg_reg);
9511 %}
9512
9513 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9514 match(If cmp (CmpN op1 null));
9515 predicate(UseCBCond);
9516 effect(USE labl, KILL icc);
9517
9518 size(4);
9519 ins_cost(BRANCH_COST);
9520 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9521 ins_encode %{
9522 Label* L = $labl$$label;
9523 assert(__ use_cbcond(*L), "back to back cbcond");
9524 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9525 %}
9526 ins_short_branch(1);
9527 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9528 ins_pipe(cbcond_reg_reg);
9529 %}
9530
9531 // Loop back branch
9532 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9533 match(CountedLoopEnd cmp (CmpI op1 op2));
9534 predicate(UseCBCond);
9535 effect(USE labl, KILL icc);
9536
9537 size(4);
9538 ins_cost(BRANCH_COST);
9539 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9540 ins_encode %{
9541 Label* L = $labl$$label;
9542 assert(__ use_cbcond(*L), "back to back cbcond");
9543 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9544 %}
9545 ins_short_branch(1);
9546 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9547 ins_pipe(cbcond_reg_reg);
9548 %}
9549
9550 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9551 match(CountedLoopEnd cmp (CmpI op1 op2));
9552 predicate(UseCBCond);
9553 effect(USE labl, KILL icc);
9554
9555 size(4);
9556 ins_cost(BRANCH_COST);
9557 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9558 ins_encode %{
9559 Label* L = $labl$$label;
9560 assert(__ use_cbcond(*L), "back to back cbcond");
9561 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9562 %}
9563 ins_short_branch(1);
9564 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9565 ins_pipe(cbcond_reg_imm);
9566 %}
9567
9568 // Branch-on-register tests all 64 bits. We assume that values
9569 // in 64-bit registers always remains zero or sign extended
9570 // unless our code munges the high bits. Interrupts can chop
9571 // the high order bits to zero or sign at any time.
9572 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9573 match(If cmp (CmpI op1 zero));
9574 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9575 effect(USE labl);
9576
9577 size(8);
9578 ins_cost(BRANCH_COST);
9579 format %{ "BR$cmp $op1,$labl" %}
9580 ins_encode( enc_bpr( labl, cmp, op1 ) );
9581 ins_avoid_back_to_back(AVOID_BEFORE);
9582 ins_pipe(br_reg);
9583 %}
9584
9585 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9586 match(If cmp (CmpP op1 null));
9587 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9588 effect(USE labl);
9589
9590 size(8);
9591 ins_cost(BRANCH_COST);
9592 format %{ "BR$cmp $op1,$labl" %}
9593 ins_encode( enc_bpr( labl, cmp, op1 ) );
9594 ins_avoid_back_to_back(AVOID_BEFORE);
9595 ins_pipe(br_reg);
9596 %}
9597
9598 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9599 match(If cmp (CmpL op1 zero));
9600 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9601 effect(USE labl);
9602
9603 size(8);
9604 ins_cost(BRANCH_COST);
9605 format %{ "BR$cmp $op1,$labl" %}
9606 ins_encode( enc_bpr( labl, cmp, op1 ) );
9607 ins_avoid_back_to_back(AVOID_BEFORE);
9608 ins_pipe(br_reg);
9609 %}
9610
9611
9612 // ============================================================================
9613 // Long Compare
9614 //
9615 // Currently we hold longs in 2 registers. Comparing such values efficiently
9616 // is tricky. The flavor of compare used depends on whether we are testing
9617 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9618 // The GE test is the negated LT test. The LE test can be had by commuting
9619 // the operands (yielding a GE test) and then negating; negate again for the
9620 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9621 // NE test is negated from that.
9622
9623 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9624 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9625 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9626 // are collapsed internally in the ADLC's dfa-gen code. The match for
9627 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9628 // foo match ends up with the wrong leaf. One fix is to not match both
9629 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9630 // both forms beat the trinary form of long-compare and both are very useful
9631 // on Intel which has so few registers.
9632
9633 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9634 match(If cmp xcc);
9635 effect(USE labl);
9636
9637 size(8);
9638 ins_cost(BRANCH_COST);
9639 format %{ "BP$cmp $xcc,$labl" %}
9640 ins_encode %{
9641 Label* L = $labl$$label;
9642 Assembler::Predict predict_taken =
9643 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9644
9645 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9646 __ delayed()->nop();
9647 %}
9648 ins_avoid_back_to_back(AVOID_BEFORE);
9649 ins_pipe(br_cc);
9650 %}
9651
9652 // Manifest a CmpL3 result in an integer register. Very painful.
9653 // This is the test to avoid.
9654 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9655 match(Set dst (CmpL3 src1 src2) );
9656 effect( KILL ccr );
9657 ins_cost(6*DEFAULT_COST);
9658 size(24);
9659 format %{ "CMP $src1,$src2\t\t! long\n"
9660 "\tBLT,a,pn done\n"
9661 "\tMOV -1,$dst\t! delay slot\n"
9662 "\tBGT,a,pn done\n"
9663 "\tMOV 1,$dst\t! delay slot\n"
9664 "\tCLR $dst\n"
9665 "done:" %}
9666 ins_encode( cmpl_flag(src1,src2,dst) );
9667 ins_pipe(cmpL_reg);
9668 %}
9669
9670 // Conditional move
9671 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9672 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9673 ins_cost(150);
9674 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9675 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9676 ins_pipe(ialu_reg);
9677 %}
9678
9679 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9680 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9681 ins_cost(140);
9682 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9683 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9684 ins_pipe(ialu_imm);
9685 %}
9686
9687 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9688 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9689 ins_cost(150);
9690 format %{ "MOV$cmp $xcc,$src,$dst" %}
9691 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9692 ins_pipe(ialu_reg);
9693 %}
9694
9695 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9696 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9697 ins_cost(140);
9698 format %{ "MOV$cmp $xcc,$src,$dst" %}
9699 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9700 ins_pipe(ialu_imm);
9701 %}
9702
9703 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9704 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9705 ins_cost(150);
9706 format %{ "MOV$cmp $xcc,$src,$dst" %}
9707 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9708 ins_pipe(ialu_reg);
9709 %}
9710
9711 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9712 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9713 ins_cost(150);
9714 format %{ "MOV$cmp $xcc,$src,$dst" %}
9715 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9716 ins_pipe(ialu_reg);
9717 %}
9718
9719 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9720 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9721 ins_cost(140);
9722 format %{ "MOV$cmp $xcc,$src,$dst" %}
9723 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9724 ins_pipe(ialu_imm);
9725 %}
9726
9727 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9728 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9729 ins_cost(150);
9730 opcode(0x101);
9731 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9732 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9733 ins_pipe(int_conditional_float_move);
9734 %}
9735
9736 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9737 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9738 ins_cost(150);
9739 opcode(0x102);
9740 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9741 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9742 ins_pipe(int_conditional_float_move);
9743 %}
9744
9745 // ============================================================================
9746 // Safepoint Instruction
9747 instruct safePoint_poll(iRegP poll) %{
9748 match(SafePoint poll);
9749 effect(USE poll);
9750
9751 size(4);
9752 #ifdef _LP64
9753 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9754 #else
9755 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9756 #endif
9757 ins_encode %{
9758 __ relocate(relocInfo::poll_type);
9759 __ ld_ptr($poll$$Register, 0, G0);
9760 %}
9761 ins_pipe(loadPollP);
9762 %}
9763
9764 // ============================================================================
9765 // Call Instructions
9766 // Call Java Static Instruction
9767 instruct CallStaticJavaDirect( method meth ) %{
9768 match(CallStaticJava);
9769 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9770 effect(USE meth);
9771
9772 size(8);
9773 ins_cost(CALL_COST);
9774 format %{ "CALL,static ; NOP ==> " %}
9775 ins_encode( Java_Static_Call( meth ), call_epilog );
9776 ins_avoid_back_to_back(AVOID_BEFORE);
9777 ins_pipe(simple_call);
9778 %}
9779
9780 // Call Java Static Instruction (method handle version)
9781 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9782 match(CallStaticJava);
9783 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9784 effect(USE meth, KILL l7_mh_SP_save);
9785
9786 size(16);
9787 ins_cost(CALL_COST);
9788 format %{ "CALL,static/MethodHandle" %}
9789 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9790 ins_pipe(simple_call);
9791 %}
9792
9793 // Call Java Dynamic Instruction
9794 instruct CallDynamicJavaDirect( method meth ) %{
9795 match(CallDynamicJava);
9796 effect(USE meth);
9797
9798 ins_cost(CALL_COST);
9799 format %{ "SET (empty),R_G5\n\t"
9800 "CALL,dynamic ; NOP ==> " %}
9801 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9802 ins_pipe(call);
9803 %}
9804
9805 // Call Runtime Instruction
9806 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9807 match(CallRuntime);
9808 effect(USE meth, KILL l7);
9809 ins_cost(CALL_COST);
9810 format %{ "CALL,runtime" %}
9811 ins_encode( Java_To_Runtime( meth ),
9812 call_epilog, adjust_long_from_native_call );
9813 ins_avoid_back_to_back(AVOID_BEFORE);
9814 ins_pipe(simple_call);
9815 %}
9816
9817 // Call runtime without safepoint - same as CallRuntime
9818 instruct CallLeafDirect(method meth, l7RegP l7) %{
9819 match(CallLeaf);
9820 effect(USE meth, KILL l7);
9821 ins_cost(CALL_COST);
9822 format %{ "CALL,runtime leaf" %}
9823 ins_encode( Java_To_Runtime( meth ),
9824 call_epilog,
9825 adjust_long_from_native_call );
9826 ins_avoid_back_to_back(AVOID_BEFORE);
9827 ins_pipe(simple_call);
9828 %}
9829
9830 // Call runtime without safepoint - same as CallLeaf
9831 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9832 match(CallLeafNoFP);
9833 effect(USE meth, KILL l7);
9834 ins_cost(CALL_COST);
9835 format %{ "CALL,runtime leaf nofp" %}
9836 ins_encode( Java_To_Runtime( meth ),
9837 call_epilog,
9838 adjust_long_from_native_call );
9839 ins_avoid_back_to_back(AVOID_BEFORE);
9840 ins_pipe(simple_call);
9841 %}
9842
9843 // Tail Call; Jump from runtime stub to Java code.
9844 // Also known as an 'interprocedural jump'.
9845 // Target of jump will eventually return to caller.
9846 // TailJump below removes the return address.
9847 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9848 match(TailCall jump_target method_oop );
9849
9850 ins_cost(CALL_COST);
9851 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9852 ins_encode(form_jmpl(jump_target));
9853 ins_avoid_back_to_back(AVOID_BEFORE);
9854 ins_pipe(tail_call);
9855 %}
9856
9857
9858 // Return Instruction
9859 instruct Ret() %{
9860 match(Return);
9861
9862 // The epilogue node did the ret already.
9863 size(0);
9864 format %{ "! return" %}
9865 ins_encode();
9866 ins_pipe(empty);
9867 %}
9868
9869
9870 // Tail Jump; remove the return address; jump to target.
9871 // TailCall above leaves the return address around.
9872 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9873 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9874 // "restore" before this instruction (in Epilogue), we need to materialize it
9875 // in %i0.
9876 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9877 match( TailJump jump_target ex_oop );
9878 ins_cost(CALL_COST);
9879 format %{ "! discard R_O7\n\t"
9880 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9881 ins_encode(form_jmpl_set_exception_pc(jump_target));
9882 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9883 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9884 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9885 ins_avoid_back_to_back(AVOID_BEFORE);
9886 ins_pipe(tail_call);
9887 %}
9888
9889 // Create exception oop: created by stack-crawling runtime code.
9890 // Created exception is now available to this handler, and is setup
9891 // just prior to jumping to this handler. No code emitted.
9892 instruct CreateException( o0RegP ex_oop )
9893 %{
9894 match(Set ex_oop (CreateEx));
9895 ins_cost(0);
9896
9897 size(0);
9898 // use the following format syntax
9899 format %{ "! exception oop is in R_O0; no code emitted" %}
9900 ins_encode();
9901 ins_pipe(empty);
9902 %}
9903
9904
9905 // Rethrow exception:
9906 // The exception oop will come in the first argument position.
9907 // Then JUMP (not call) to the rethrow stub code.
9908 instruct RethrowException()
9909 %{
9910 match(Rethrow);
9911 ins_cost(CALL_COST);
9912
9913 // use the following format syntax
9914 format %{ "Jmp rethrow_stub" %}
9915 ins_encode(enc_rethrow);
9916 ins_avoid_back_to_back(AVOID_BEFORE);
9917 ins_pipe(tail_call);
9918 %}
9919
9920
9921 // Die now
9922 instruct ShouldNotReachHere( )
9923 %{
9924 match(Halt);
9925 ins_cost(CALL_COST);
9926
9927 size(4);
9928 // Use the following format syntax
9929 format %{ "ILLTRAP ; ShouldNotReachHere" %}
9930 ins_encode( form2_illtrap() );
9931 ins_pipe(tail_call);
9932 %}
9933
9934 // ============================================================================
9935 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9936 // array for an instance of the superklass. Set a hidden internal cache on a
9937 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9938 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9939 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9940 match(Set index (PartialSubtypeCheck sub super));
9941 effect( KILL pcc, KILL o7 );
9942 ins_cost(DEFAULT_COST*10);
9943 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
9944 ins_encode( enc_PartialSubtypeCheck() );
9945 ins_avoid_back_to_back(AVOID_BEFORE);
9946 ins_pipe(partial_subtype_check_pipe);
9947 %}
9948
9949 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9950 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9951 effect( KILL idx, KILL o7 );
9952 ins_cost(DEFAULT_COST*10);
9953 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9954 ins_encode( enc_PartialSubtypeCheck() );
9955 ins_avoid_back_to_back(AVOID_BEFORE);
9956 ins_pipe(partial_subtype_check_pipe);
9957 %}
9958
9959
9960 // ============================================================================
9961 // inlined locking and unlocking
9962
9963 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9964 match(Set pcc (FastLock object box));
9965
9966 effect(TEMP scratch2, USE_KILL box, KILL scratch);
9967 ins_cost(100);
9968
9969 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
9970 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9971 ins_pipe(long_memory_op);
9972 %}
9973
9974
9975 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9976 match(Set pcc (FastUnlock object box));
9977 effect(TEMP scratch2, USE_KILL box, KILL scratch);
9978 ins_cost(100);
9979
9980 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
9981 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9982 ins_pipe(long_memory_op);
9983 %}
9984
9985 // The encodings are generic.
9986 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9987 predicate(!use_block_zeroing(n->in(2)) );
9988 match(Set dummy (ClearArray cnt base));
9989 effect(TEMP temp, KILL ccr);
9990 ins_cost(300);
9991 format %{ "MOV $cnt,$temp\n"
9992 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
9993 " BRge loop\t\t! Clearing loop\n"
9994 " STX G0,[$base+$temp]\t! delay slot" %}
9995
9996 ins_encode %{
9997 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
9998 Register nof_bytes_arg = $cnt$$Register;
9999 Register nof_bytes_tmp = $temp$$Register;
10000 Register base_pointer_arg = $base$$Register;
10001
10002 Label loop;
10003 __ mov(nof_bytes_arg, nof_bytes_tmp);
10004
10005 // Loop and clear, walking backwards through the array.
10006 // nof_bytes_tmp (if >0) is always the number of bytes to zero
10007 __ bind(loop);
10008 __ deccc(nof_bytes_tmp, 8);
10009 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10010 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10011 // %%%% this mini-loop must not cross a cache boundary!
10012 %}
10013 ins_pipe(long_memory_op);
10014 %}
10015
10016 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10017 predicate(use_block_zeroing(n->in(2)));
10018 match(Set dummy (ClearArray cnt base));
10019 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10020 ins_cost(300);
10021 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10022
10023 ins_encode %{
10024
10025 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10026 Register to = $base$$Register;
10027 Register count = $cnt$$Register;
10028
10029 Label Ldone;
10030 __ nop(); // Separate short branches
10031 // Use BIS for zeroing (temp is not used).
10032 __ bis_zeroing(to, count, G0, Ldone);
10033 __ bind(Ldone);
10034
10035 %}
10036 ins_pipe(long_memory_op);
10037 %}
10038
10039 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10040 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10041 match(Set dummy (ClearArray cnt base));
10042 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10043 ins_cost(300);
10044 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10045
10046 ins_encode %{
10047
10048 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10049 Register to = $base$$Register;
10050 Register count = $cnt$$Register;
10051 Register temp = $tmp$$Register;
10052
10053 Label Ldone;
10054 __ nop(); // Separate short branches
10055 // Use BIS for zeroing
10056 __ bis_zeroing(to, count, temp, Ldone);
10057 __ bind(Ldone);
10058
10059 %}
10060 ins_pipe(long_memory_op);
10061 %}
10062
10063 instruct string_compareL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10064 o7RegI tmp, flagsReg ccr) %{
10065 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10066 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10067 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10068 ins_cost(300);
10069 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10070 ins_encode %{
10071 __ string_compare($str1$$Register, $str2$$Register,
10072 $cnt1$$Register, $cnt2$$Register,
10073 $tmp$$Register, $tmp$$Register,
10074 $result$$Register, StrIntrinsicNode::LL);
10075 %}
10076 ins_pipe(long_memory_op);
10077 %}
10078
10079 instruct string_compareU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10080 o7RegI tmp, flagsReg ccr) %{
10081 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
10082 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10083 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10084 ins_cost(300);
10085 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10086 ins_encode %{
10087 __ string_compare($str1$$Register, $str2$$Register,
10088 $cnt1$$Register, $cnt2$$Register,
10089 $tmp$$Register, $tmp$$Register,
10090 $result$$Register, StrIntrinsicNode::UU);
10091 %}
10092 ins_pipe(long_memory_op);
10093 %}
10094
10095 instruct string_compareLU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10096 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10097 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10098 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10099 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10100 ins_cost(300);
10101 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %}
10102 ins_encode %{
10103 __ string_compare($str1$$Register, $str2$$Register,
10104 $cnt1$$Register, $cnt2$$Register,
10105 $tmp1$$Register, $tmp2$$Register,
10106 $result$$Register, StrIntrinsicNode::LU);
10107 %}
10108 ins_pipe(long_memory_op);
10109 %}
10110
10111 instruct string_compareUL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10112 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10113 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10114 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10115 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10116 ins_cost(300);
10117 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %}
10118 ins_encode %{
10119 __ string_compare($str2$$Register, $str1$$Register,
10120 $cnt2$$Register, $cnt1$$Register,
10121 $tmp1$$Register, $tmp2$$Register,
10122 $result$$Register, StrIntrinsicNode::UL);
10123 %}
10124 ins_pipe(long_memory_op);
10125 %}
10126
10127 instruct string_equalsL(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10128 o7RegI tmp, flagsReg ccr) %{
10129 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10130 match(Set result (StrEquals (Binary str1 str2) cnt));
10131 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10132 ins_cost(300);
10133 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result // KILL $tmp" %}
10134 ins_encode %{
10135 __ array_equals(false, $str1$$Register, $str2$$Register,
10136 $cnt$$Register, $tmp$$Register,
10137 $result$$Register, true /* byte */);
10138 %}
10139 ins_pipe(long_memory_op);
10140 %}
10141
10142 instruct string_equalsU(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10143 o7RegI tmp, flagsReg ccr) %{
10144 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
10145 match(Set result (StrEquals (Binary str1 str2) cnt));
10146 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10147 ins_cost(300);
10148 format %{ "String Equals char[] $str1,$str2,$cnt -> $result // KILL $tmp" %}
10149 ins_encode %{
10150 __ array_equals(false, $str1$$Register, $str2$$Register,
10151 $cnt$$Register, $tmp$$Register,
10152 $result$$Register, false /* byte */);
10153 %}
10154 ins_pipe(long_memory_op);
10155 %}
10156
10157 instruct array_equalsB(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10158 o7RegI tmp2, flagsReg ccr) %{
10159 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10160 match(Set result (AryEq ary1 ary2));
10161 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10162 ins_cost(300);
10163 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10164 ins_encode %{
10165 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10166 $tmp1$$Register, $tmp2$$Register,
10167 $result$$Register, true /* byte */);
10168 %}
10169 ins_pipe(long_memory_op);
10170 %}
10171
10172 instruct array_equalsC(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10173 o7RegI tmp2, flagsReg ccr) %{
10174 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10175 match(Set result (AryEq ary1 ary2));
10176 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10177 ins_cost(300);
10178 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10179 ins_encode %{
10180 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10181 $tmp1$$Register, $tmp2$$Register,
10182 $result$$Register, false /* byte */);
10183 %}
10184 ins_pipe(long_memory_op);
10185 %}
10186
10187 // char[] to byte[] compression
10188 instruct string_compress(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, iRegL tmp, flagsReg ccr) %{
10189 predicate(UseVIS < 3);
10190 match(Set result (StrCompressedCopy src (Binary dst len)));
10191 effect(TEMP result, TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10192 ins_cost(300);
10193 format %{ "String Compress $src,$dst,$len -> $result // KILL $tmp" %}
10194 ins_encode %{
10195 Label Ldone;
10196 __ signx($len$$Register);
10197 __ cmp_zero_and_br(Assembler::zero, $len$$Register, Ldone, false, Assembler::pn);
10198 __ delayed()->mov($len$$Register, $result$$Register); // copy count
10199 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp$$Register, Ldone);
10200 __ bind(Ldone);
10201 %}
10202 ins_pipe(long_memory_op);
10203 %}
10204
10205 // fast char[] to byte[] compression using VIS instructions
10206 instruct string_compress_fast(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result,
10207 iRegL tmp1, iRegL tmp2, iRegL tmp3, iRegL tmp4,
10208 regD ftmp1, regD ftmp2, regD ftmp3, flagsReg ccr) %{
10209 predicate(UseVIS >= 3);
10210 match(Set result (StrCompressedCopy src (Binary dst len)));
10211 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10212 ins_cost(300);
10213 format %{ "String Compress Fast $src,$dst,$len -> $result // KILL $tmp1,$tmp2,$tmp3,$tmp4,$ftmp1,$ftmp2,$ftmp3" %}
10214 ins_encode %{
10215 Label Ldone;
10216 __ signx($len$$Register);
10217 __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $result$$Register,
10218 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10219 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, Ldone);
10220 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10221 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp1$$Register, Ldone);
10222 __ bind(Ldone);
10223 %}
10224 ins_pipe(long_memory_op);
10225 %}
10226
10227 // byte[] to char[] inflation
10228 instruct string_inflate(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10229 iRegL tmp, flagsReg ccr) %{
10230 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10231 effect(TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10232 ins_cost(300);
10233 format %{ "String Inflate $src,$dst,$len // KILL $tmp" %}
10234 ins_encode %{
10235 Label Ldone;
10236 __ signx($len$$Register);
10237 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10238 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10239 __ bind(Ldone);
10240 %}
10241 ins_pipe(long_memory_op);
10242 %}
10243
10244 // fast byte[] to char[] inflation using VIS instructions
10245 instruct string_inflate_fast(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10246 iRegL tmp, regD ftmp1, regD ftmp2, regD ftmp3, regD ftmp4, flagsReg ccr) %{
10247 predicate(UseVIS >= 3);
10248 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10249 effect(TEMP tmp, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, TEMP ftmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10250 ins_cost(300);
10251 format %{ "String Inflate Fast $src,$dst,$len // KILL $tmp,$ftmp1,$ftmp2,$ftmp3,$ftmp4" %}
10252 ins_encode %{
10253 Label Ldone;
10254 __ signx($len$$Register);
10255 __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register,
10256 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, $ftmp4$$FloatRegister, Ldone);
10257 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10258 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10259 __ bind(Ldone);
10260 %}
10261 ins_pipe(long_memory_op);
10262 %}
10263
10264
10265 //---------- Zeros Count Instructions ------------------------------------------
10266
10267 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10268 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10269 match(Set dst (CountLeadingZerosI src));
10270 effect(TEMP dst, TEMP tmp, KILL cr);
10271
10272 // x |= (x >> 1);
10273 // x |= (x >> 2);
10274 // x |= (x >> 4);
10275 // x |= (x >> 8);
10276 // x |= (x >> 16);
10277 // return (WORDBITS - popc(x));
10278 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10279 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10280 "OR $dst,$tmp,$dst\n\t"
10281 "SRL $dst,2,$tmp\n\t"
10282 "OR $dst,$tmp,$dst\n\t"
10283 "SRL $dst,4,$tmp\n\t"
10284 "OR $dst,$tmp,$dst\n\t"
10285 "SRL $dst,8,$tmp\n\t"
10286 "OR $dst,$tmp,$dst\n\t"
10287 "SRL $dst,16,$tmp\n\t"
10288 "OR $dst,$tmp,$dst\n\t"
10289 "POPC $dst,$dst\n\t"
10290 "MOV 32,$tmp\n\t"
10291 "SUB $tmp,$dst,$dst" %}
10292 ins_encode %{
10293 Register Rdst = $dst$$Register;
10294 Register Rsrc = $src$$Register;
10295 Register Rtmp = $tmp$$Register;
10296 __ srl(Rsrc, 1, Rtmp);
10297 __ srl(Rsrc, 0, Rdst);
10298 __ or3(Rdst, Rtmp, Rdst);
10299 __ srl(Rdst, 2, Rtmp);
10300 __ or3(Rdst, Rtmp, Rdst);
10301 __ srl(Rdst, 4, Rtmp);
10302 __ or3(Rdst, Rtmp, Rdst);
10303 __ srl(Rdst, 8, Rtmp);
10304 __ or3(Rdst, Rtmp, Rdst);
10305 __ srl(Rdst, 16, Rtmp);
10306 __ or3(Rdst, Rtmp, Rdst);
10307 __ popc(Rdst, Rdst);
10308 __ mov(BitsPerInt, Rtmp);
10309 __ sub(Rtmp, Rdst, Rdst);
10310 %}
10311 ins_pipe(ialu_reg);
10312 %}
10313
10314 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10315 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10316 match(Set dst (CountLeadingZerosL src));
10317 effect(TEMP dst, TEMP tmp, KILL cr);
10318
10319 // x |= (x >> 1);
10320 // x |= (x >> 2);
10321 // x |= (x >> 4);
10322 // x |= (x >> 8);
10323 // x |= (x >> 16);
10324 // x |= (x >> 32);
10325 // return (WORDBITS - popc(x));
10326 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10327 "OR $src,$tmp,$dst\n\t"
10328 "SRLX $dst,2,$tmp\n\t"
10329 "OR $dst,$tmp,$dst\n\t"
10330 "SRLX $dst,4,$tmp\n\t"
10331 "OR $dst,$tmp,$dst\n\t"
10332 "SRLX $dst,8,$tmp\n\t"
10333 "OR $dst,$tmp,$dst\n\t"
10334 "SRLX $dst,16,$tmp\n\t"
10335 "OR $dst,$tmp,$dst\n\t"
10336 "SRLX $dst,32,$tmp\n\t"
10337 "OR $dst,$tmp,$dst\n\t"
10338 "POPC $dst,$dst\n\t"
10339 "MOV 64,$tmp\n\t"
10340 "SUB $tmp,$dst,$dst" %}
10341 ins_encode %{
10342 Register Rdst = $dst$$Register;
10343 Register Rsrc = $src$$Register;
10344 Register Rtmp = $tmp$$Register;
10345 __ srlx(Rsrc, 1, Rtmp);
10346 __ or3( Rsrc, Rtmp, Rdst);
10347 __ srlx(Rdst, 2, Rtmp);
10348 __ or3( Rdst, Rtmp, Rdst);
10349 __ srlx(Rdst, 4, Rtmp);
10350 __ or3( Rdst, Rtmp, Rdst);
10351 __ srlx(Rdst, 8, Rtmp);
10352 __ or3( Rdst, Rtmp, Rdst);
10353 __ srlx(Rdst, 16, Rtmp);
10354 __ or3( Rdst, Rtmp, Rdst);
10355 __ srlx(Rdst, 32, Rtmp);
10356 __ or3( Rdst, Rtmp, Rdst);
10357 __ popc(Rdst, Rdst);
10358 __ mov(BitsPerLong, Rtmp);
10359 __ sub(Rtmp, Rdst, Rdst);
10360 %}
10361 ins_pipe(ialu_reg);
10362 %}
10363
10364 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10365 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10366 match(Set dst (CountTrailingZerosI src));
10367 effect(TEMP dst, KILL cr);
10368
10369 // return popc(~x & (x - 1));
10370 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10371 "ANDN $dst,$src,$dst\n\t"
10372 "SRL $dst,R_G0,$dst\n\t"
10373 "POPC $dst,$dst" %}
10374 ins_encode %{
10375 Register Rdst = $dst$$Register;
10376 Register Rsrc = $src$$Register;
10377 __ sub(Rsrc, 1, Rdst);
10378 __ andn(Rdst, Rsrc, Rdst);
10379 __ srl(Rdst, G0, Rdst);
10380 __ popc(Rdst, Rdst);
10381 %}
10382 ins_pipe(ialu_reg);
10383 %}
10384
10385 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10386 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10387 match(Set dst (CountTrailingZerosL src));
10388 effect(TEMP dst, KILL cr);
10389
10390 // return popc(~x & (x - 1));
10391 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10392 "ANDN $dst,$src,$dst\n\t"
10393 "POPC $dst,$dst" %}
10394 ins_encode %{
10395 Register Rdst = $dst$$Register;
10396 Register Rsrc = $src$$Register;
10397 __ sub(Rsrc, 1, Rdst);
10398 __ andn(Rdst, Rsrc, Rdst);
10399 __ popc(Rdst, Rdst);
10400 %}
10401 ins_pipe(ialu_reg);
10402 %}
10403
10404
10405 //---------- Population Count Instructions -------------------------------------
10406
10407 instruct popCountI(iRegIsafe dst, iRegI src) %{
10408 predicate(UsePopCountInstruction);
10409 match(Set dst (PopCountI src));
10410
10411 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10412 "POPC $dst, $dst" %}
10413 ins_encode %{
10414 __ srl($src$$Register, G0, $dst$$Register);
10415 __ popc($dst$$Register, $dst$$Register);
10416 %}
10417 ins_pipe(ialu_reg);
10418 %}
10419
10420 // Note: Long.bitCount(long) returns an int.
10421 instruct popCountL(iRegIsafe dst, iRegL src) %{
10422 predicate(UsePopCountInstruction);
10423 match(Set dst (PopCountL src));
10424
10425 format %{ "POPC $src, $dst" %}
10426 ins_encode %{
10427 __ popc($src$$Register, $dst$$Register);
10428 %}
10429 ins_pipe(ialu_reg);
10430 %}
10431
10432
10433 // ============================================================================
10434 //------------Bytes reverse--------------------------------------------------
10435
10436 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10437 match(Set dst (ReverseBytesI src));
10438
10439 // Op cost is artificially doubled to make sure that load or store
10440 // instructions are preferred over this one which requires a spill
10441 // onto a stack slot.
10442 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10443 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10444
10445 ins_encode %{
10446 __ set($src$$disp + STACK_BIAS, O7);
10447 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10448 %}
10449 ins_pipe( iload_mem );
10450 %}
10451
10452 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10453 match(Set dst (ReverseBytesL src));
10454
10455 // Op cost is artificially doubled to make sure that load or store
10456 // instructions are preferred over this one which requires a spill
10457 // onto a stack slot.
10458 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10459 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10460
10461 ins_encode %{
10462 __ set($src$$disp + STACK_BIAS, O7);
10463 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10464 %}
10465 ins_pipe( iload_mem );
10466 %}
10467
10468 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10469 match(Set dst (ReverseBytesUS src));
10470
10471 // Op cost is artificially doubled to make sure that load or store
10472 // instructions are preferred over this one which requires a spill
10473 // onto a stack slot.
10474 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10475 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10476
10477 ins_encode %{
10478 // the value was spilled as an int so bias the load
10479 __ set($src$$disp + STACK_BIAS + 2, O7);
10480 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10481 %}
10482 ins_pipe( iload_mem );
10483 %}
10484
10485 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10486 match(Set dst (ReverseBytesS src));
10487
10488 // Op cost is artificially doubled to make sure that load or store
10489 // instructions are preferred over this one which requires a spill
10490 // onto a stack slot.
10491 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10492 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10493
10494 ins_encode %{
10495 // the value was spilled as an int so bias the load
10496 __ set($src$$disp + STACK_BIAS + 2, O7);
10497 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10498 %}
10499 ins_pipe( iload_mem );
10500 %}
10501
10502 // Load Integer reversed byte order
10503 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10504 match(Set dst (ReverseBytesI (LoadI src)));
10505
10506 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10507 size(4);
10508 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10509
10510 ins_encode %{
10511 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10512 %}
10513 ins_pipe(iload_mem);
10514 %}
10515
10516 // Load Long - aligned and reversed
10517 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10518 match(Set dst (ReverseBytesL (LoadL src)));
10519
10520 ins_cost(MEMORY_REF_COST);
10521 size(4);
10522 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10523
10524 ins_encode %{
10525 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10526 %}
10527 ins_pipe(iload_mem);
10528 %}
10529
10530 // Load unsigned short / char reversed byte order
10531 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10532 match(Set dst (ReverseBytesUS (LoadUS src)));
10533
10534 ins_cost(MEMORY_REF_COST);
10535 size(4);
10536 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10537
10538 ins_encode %{
10539 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10540 %}
10541 ins_pipe(iload_mem);
10542 %}
10543
10544 // Load short reversed byte order
10545 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10546 match(Set dst (ReverseBytesS (LoadS src)));
10547
10548 ins_cost(MEMORY_REF_COST);
10549 size(4);
10550 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10551
10552 ins_encode %{
10553 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10554 %}
10555 ins_pipe(iload_mem);
10556 %}
10557
10558 // Store Integer reversed byte order
10559 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10560 match(Set dst (StoreI dst (ReverseBytesI src)));
10561
10562 ins_cost(MEMORY_REF_COST);
10563 size(4);
10564 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10565
10566 ins_encode %{
10567 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10568 %}
10569 ins_pipe(istore_mem_reg);
10570 %}
10571
10572 // Store Long reversed byte order
10573 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10574 match(Set dst (StoreL dst (ReverseBytesL src)));
10575
10576 ins_cost(MEMORY_REF_COST);
10577 size(4);
10578 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10579
10580 ins_encode %{
10581 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10582 %}
10583 ins_pipe(istore_mem_reg);
10584 %}
10585
10586 // Store unsighed short/char reversed byte order
10587 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10588 match(Set dst (StoreC dst (ReverseBytesUS src)));
10589
10590 ins_cost(MEMORY_REF_COST);
10591 size(4);
10592 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10593
10594 ins_encode %{
10595 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10596 %}
10597 ins_pipe(istore_mem_reg);
10598 %}
10599
10600 // Store short reversed byte order
10601 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10602 match(Set dst (StoreC dst (ReverseBytesS src)));
10603
10604 ins_cost(MEMORY_REF_COST);
10605 size(4);
10606 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10607
10608 ins_encode %{
10609 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10610 %}
10611 ins_pipe(istore_mem_reg);
10612 %}
10613
10614 // ====================VECTOR INSTRUCTIONS=====================================
10615
10616 // Load Aligned Packed values into a Double Register
10617 instruct loadV8(regD dst, memory mem) %{
10618 predicate(n->as_LoadVector()->memory_size() == 8);
10619 match(Set dst (LoadVector mem));
10620 ins_cost(MEMORY_REF_COST);
10621 size(4);
10622 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10623 ins_encode %{
10624 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10625 %}
10626 ins_pipe(floadD_mem);
10627 %}
10628
10629 // Store Vector in Double register to memory
10630 instruct storeV8(memory mem, regD src) %{
10631 predicate(n->as_StoreVector()->memory_size() == 8);
10632 match(Set mem (StoreVector mem src));
10633 ins_cost(MEMORY_REF_COST);
10634 size(4);
10635 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10636 ins_encode %{
10637 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10638 %}
10639 ins_pipe(fstoreD_mem_reg);
10640 %}
10641
10642 // Store Zero into vector in memory
10643 instruct storeV8B_zero(memory mem, immI0 zero) %{
10644 predicate(n->as_StoreVector()->memory_size() == 8);
10645 match(Set mem (StoreVector mem (ReplicateB zero)));
10646 ins_cost(MEMORY_REF_COST);
10647 size(4);
10648 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10649 ins_encode %{
10650 __ stx(G0, $mem$$Address);
10651 %}
10652 ins_pipe(fstoreD_mem_zero);
10653 %}
10654
10655 instruct storeV4S_zero(memory mem, immI0 zero) %{
10656 predicate(n->as_StoreVector()->memory_size() == 8);
10657 match(Set mem (StoreVector mem (ReplicateS zero)));
10658 ins_cost(MEMORY_REF_COST);
10659 size(4);
10660 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10661 ins_encode %{
10662 __ stx(G0, $mem$$Address);
10663 %}
10664 ins_pipe(fstoreD_mem_zero);
10665 %}
10666
10667 instruct storeV2I_zero(memory mem, immI0 zero) %{
10668 predicate(n->as_StoreVector()->memory_size() == 8);
10669 match(Set mem (StoreVector mem (ReplicateI zero)));
10670 ins_cost(MEMORY_REF_COST);
10671 size(4);
10672 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10673 ins_encode %{
10674 __ stx(G0, $mem$$Address);
10675 %}
10676 ins_pipe(fstoreD_mem_zero);
10677 %}
10678
10679 instruct storeV2F_zero(memory mem, immF0 zero) %{
10680 predicate(n->as_StoreVector()->memory_size() == 8);
10681 match(Set mem (StoreVector mem (ReplicateF zero)));
10682 ins_cost(MEMORY_REF_COST);
10683 size(4);
10684 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10685 ins_encode %{
10686 __ stx(G0, $mem$$Address);
10687 %}
10688 ins_pipe(fstoreD_mem_zero);
10689 %}
10690
10691 // Replicate scalar to packed byte values into Double register
10692 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10693 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10694 match(Set dst (ReplicateB src));
10695 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10696 format %{ "SLLX $src,56,$tmp\n\t"
10697 "SRLX $tmp, 8,$tmp2\n\t"
10698 "OR $tmp,$tmp2,$tmp\n\t"
10699 "SRLX $tmp,16,$tmp2\n\t"
10700 "OR $tmp,$tmp2,$tmp\n\t"
10701 "SRLX $tmp,32,$tmp2\n\t"
10702 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10703 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10704 ins_encode %{
10705 Register Rsrc = $src$$Register;
10706 Register Rtmp = $tmp$$Register;
10707 Register Rtmp2 = $tmp2$$Register;
10708 __ sllx(Rsrc, 56, Rtmp);
10709 __ srlx(Rtmp, 8, Rtmp2);
10710 __ or3 (Rtmp, Rtmp2, Rtmp);
10711 __ srlx(Rtmp, 16, Rtmp2);
10712 __ or3 (Rtmp, Rtmp2, Rtmp);
10713 __ srlx(Rtmp, 32, Rtmp2);
10714 __ or3 (Rtmp, Rtmp2, Rtmp);
10715 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10716 %}
10717 ins_pipe(ialu_reg);
10718 %}
10719
10720 // Replicate scalar to packed byte values into Double stack
10721 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10722 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10723 match(Set dst (ReplicateB src));
10724 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10725 format %{ "SLLX $src,56,$tmp\n\t"
10726 "SRLX $tmp, 8,$tmp2\n\t"
10727 "OR $tmp,$tmp2,$tmp\n\t"
10728 "SRLX $tmp,16,$tmp2\n\t"
10729 "OR $tmp,$tmp2,$tmp\n\t"
10730 "SRLX $tmp,32,$tmp2\n\t"
10731 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10732 "STX $tmp,$dst\t! regL to stkD" %}
10733 ins_encode %{
10734 Register Rsrc = $src$$Register;
10735 Register Rtmp = $tmp$$Register;
10736 Register Rtmp2 = $tmp2$$Register;
10737 __ sllx(Rsrc, 56, Rtmp);
10738 __ srlx(Rtmp, 8, Rtmp2);
10739 __ or3 (Rtmp, Rtmp2, Rtmp);
10740 __ srlx(Rtmp, 16, Rtmp2);
10741 __ or3 (Rtmp, Rtmp2, Rtmp);
10742 __ srlx(Rtmp, 32, Rtmp2);
10743 __ or3 (Rtmp, Rtmp2, Rtmp);
10744 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10745 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10746 %}
10747 ins_pipe(ialu_reg);
10748 %}
10749
10750 // Replicate scalar constant to packed byte values in Double register
10751 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10752 predicate(n->as_Vector()->length() == 8);
10753 match(Set dst (ReplicateB con));
10754 effect(KILL tmp);
10755 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10756 ins_encode %{
10757 // XXX This is a quick fix for 6833573.
10758 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10759 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10760 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10761 %}
10762 ins_pipe(loadConFD);
10763 %}
10764
10765 // Replicate scalar to packed char/short values into Double register
10766 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10767 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10768 match(Set dst (ReplicateS src));
10769 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10770 format %{ "SLLX $src,48,$tmp\n\t"
10771 "SRLX $tmp,16,$tmp2\n\t"
10772 "OR $tmp,$tmp2,$tmp\n\t"
10773 "SRLX $tmp,32,$tmp2\n\t"
10774 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10775 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10776 ins_encode %{
10777 Register Rsrc = $src$$Register;
10778 Register Rtmp = $tmp$$Register;
10779 Register Rtmp2 = $tmp2$$Register;
10780 __ sllx(Rsrc, 48, Rtmp);
10781 __ srlx(Rtmp, 16, Rtmp2);
10782 __ or3 (Rtmp, Rtmp2, Rtmp);
10783 __ srlx(Rtmp, 32, Rtmp2);
10784 __ or3 (Rtmp, Rtmp2, Rtmp);
10785 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10786 %}
10787 ins_pipe(ialu_reg);
10788 %}
10789
10790 // Replicate scalar to packed char/short values into Double stack
10791 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10792 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10793 match(Set dst (ReplicateS src));
10794 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10795 format %{ "SLLX $src,48,$tmp\n\t"
10796 "SRLX $tmp,16,$tmp2\n\t"
10797 "OR $tmp,$tmp2,$tmp\n\t"
10798 "SRLX $tmp,32,$tmp2\n\t"
10799 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10800 "STX $tmp,$dst\t! regL to stkD" %}
10801 ins_encode %{
10802 Register Rsrc = $src$$Register;
10803 Register Rtmp = $tmp$$Register;
10804 Register Rtmp2 = $tmp2$$Register;
10805 __ sllx(Rsrc, 48, Rtmp);
10806 __ srlx(Rtmp, 16, Rtmp2);
10807 __ or3 (Rtmp, Rtmp2, Rtmp);
10808 __ srlx(Rtmp, 32, Rtmp2);
10809 __ or3 (Rtmp, Rtmp2, Rtmp);
10810 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10811 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10812 %}
10813 ins_pipe(ialu_reg);
10814 %}
10815
10816 // Replicate scalar constant to packed char/short values in Double register
10817 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10818 predicate(n->as_Vector()->length() == 4);
10819 match(Set dst (ReplicateS con));
10820 effect(KILL tmp);
10821 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10822 ins_encode %{
10823 // XXX This is a quick fix for 6833573.
10824 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10825 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10826 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10827 %}
10828 ins_pipe(loadConFD);
10829 %}
10830
10831 // Replicate scalar to packed int values into Double register
10832 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10833 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10834 match(Set dst (ReplicateI src));
10835 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10836 format %{ "SLLX $src,32,$tmp\n\t"
10837 "SRLX $tmp,32,$tmp2\n\t"
10838 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10839 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10840 ins_encode %{
10841 Register Rsrc = $src$$Register;
10842 Register Rtmp = $tmp$$Register;
10843 Register Rtmp2 = $tmp2$$Register;
10844 __ sllx(Rsrc, 32, Rtmp);
10845 __ srlx(Rtmp, 32, Rtmp2);
10846 __ or3 (Rtmp, Rtmp2, Rtmp);
10847 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10848 %}
10849 ins_pipe(ialu_reg);
10850 %}
10851
10852 // Replicate scalar to packed int values into Double stack
10853 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10854 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10855 match(Set dst (ReplicateI src));
10856 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10857 format %{ "SLLX $src,32,$tmp\n\t"
10858 "SRLX $tmp,32,$tmp2\n\t"
10859 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10860 "STX $tmp,$dst\t! regL to stkD" %}
10861 ins_encode %{
10862 Register Rsrc = $src$$Register;
10863 Register Rtmp = $tmp$$Register;
10864 Register Rtmp2 = $tmp2$$Register;
10865 __ sllx(Rsrc, 32, Rtmp);
10866 __ srlx(Rtmp, 32, Rtmp2);
10867 __ or3 (Rtmp, Rtmp2, Rtmp);
10868 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10869 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10870 %}
10871 ins_pipe(ialu_reg);
10872 %}
10873
10874 // Replicate scalar zero constant to packed int values in Double register
10875 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10876 predicate(n->as_Vector()->length() == 2);
10877 match(Set dst (ReplicateI con));
10878 effect(KILL tmp);
10879 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10880 ins_encode %{
10881 // XXX This is a quick fix for 6833573.
10882 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10883 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10884 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10885 %}
10886 ins_pipe(loadConFD);
10887 %}
10888
10889 // Replicate scalar to packed float values into Double stack
10890 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10891 predicate(n->as_Vector()->length() == 2);
10892 match(Set dst (ReplicateF src));
10893 ins_cost(MEMORY_REF_COST*2);
10894 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10895 "STF $src,$dst.lo" %}
10896 opcode(Assembler::stf_op3);
10897 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10898 ins_pipe(fstoreF_stk_reg);
10899 %}
10900
10901 // Replicate scalar zero constant to packed float values in Double register
10902 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10903 predicate(n->as_Vector()->length() == 2);
10904 match(Set dst (ReplicateF con));
10905 effect(KILL tmp);
10906 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10907 ins_encode %{
10908 // XXX This is a quick fix for 6833573.
10909 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10910 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10911 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10912 %}
10913 ins_pipe(loadConFD);
10914 %}
10915
10916 //----------PEEPHOLE RULES-----------------------------------------------------
10917 // These must follow all instruction definitions as they use the names
10918 // defined in the instructions definitions.
10919 //
10920 // peepmatch ( root_instr_name [preceding_instruction]* );
10921 //
10922 // peepconstraint %{
10923 // (instruction_number.operand_name relational_op instruction_number.operand_name
10924 // [, ...] );
10925 // // instruction numbers are zero-based using left to right order in peepmatch
10926 //
10927 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10928 // // provide an instruction_number.operand_name for each operand that appears
10929 // // in the replacement instruction's match rule
10930 //
10931 // ---------VM FLAGS---------------------------------------------------------
10932 //
10933 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10934 //
10935 // Each peephole rule is given an identifying number starting with zero and
10936 // increasing by one in the order seen by the parser. An individual peephole
10937 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10938 // on the command-line.
10939 //
10940 // ---------CURRENT LIMITATIONS----------------------------------------------
10941 //
10942 // Only match adjacent instructions in same basic block
10943 // Only equality constraints
10944 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10945 // Only one replacement instruction
10946 //
10947 // ---------EXAMPLE----------------------------------------------------------
10948 //
10949 // // pertinent parts of existing instructions in architecture description
10950 // instruct movI(eRegI dst, eRegI src) %{
10951 // match(Set dst (CopyI src));
10952 // %}
10953 //
10954 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10955 // match(Set dst (AddI dst src));
10956 // effect(KILL cr);
10957 // %}
10958 //
10959 // // Change (inc mov) to lea
10960 // peephole %{
10961 // // increment preceeded by register-register move
10962 // peepmatch ( incI_eReg movI );
10963 // // require that the destination register of the increment
10964 // // match the destination register of the move
10965 // peepconstraint ( 0.dst == 1.dst );
10966 // // construct a replacement instruction that sets
10967 // // the destination to ( move's source register + one )
10968 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10969 // %}
10970 //
10971
10972 // // Change load of spilled value to only a spill
10973 // instruct storeI(memory mem, eRegI src) %{
10974 // match(Set mem (StoreI mem src));
10975 // %}
10976 //
10977 // instruct loadI(eRegI dst, memory mem) %{
10978 // match(Set dst (LoadI mem));
10979 // %}
10980 //
10981 // peephole %{
10982 // peepmatch ( loadI storeI );
10983 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10984 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10985 // %}
10986
10987 //----------SMARTSPILL RULES---------------------------------------------------
10988 // These must follow all instruction definitions as they use the names
10989 // defined in the instructions definitions.
10990 //
10991 // SPARC will probably not have any of these rules due to RISC instruction set.
10992
10993 //----------PIPELINE-----------------------------------------------------------
10994 // Rules which define the behavior of the target architectures pipeline.