1843 case Op_CountLeadingZerosI:
1844 case Op_CountLeadingZerosL:
1845 case Op_CountTrailingZerosI:
1846 case Op_CountTrailingZerosL:
1847 case Op_PopCountI:
1848 case Op_PopCountL:
1849 if (!UsePopCountInstruction)
1850 return false;
1851 case Op_CompareAndSwapL:
1852 #ifdef _LP64
1853 case Op_CompareAndSwapP:
1854 #endif
1855 if (!VM_Version::supports_cx8())
1856 return false;
1857 break;
1858 }
1859
1860 return true; // Per default match rules are supported.
1861 }
1862
1863 const int Matcher::float_pressure(int default_pressure_threshold) {
1864 return default_pressure_threshold;
1865 }
1866
1867 int Matcher::regnum_to_fpu_offset(int regnum) {
1868 return regnum - 32; // The FP registers are in the second chunk
1869 }
1870
1871 #ifdef ASSERT
1872 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1873 #endif
1874
1875 // Vector width in bytes
1876 const int Matcher::vector_width_in_bytes(BasicType bt) {
1877 assert(MaxVectorSize == 8, "");
1878 return 8;
1879 }
1880
1881 // Vector ideal reg
1882 const int Matcher::vector_ideal_reg(int size) {
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1843 case Op_CountLeadingZerosI:
1844 case Op_CountLeadingZerosL:
1845 case Op_CountTrailingZerosI:
1846 case Op_CountTrailingZerosL:
1847 case Op_PopCountI:
1848 case Op_PopCountL:
1849 if (!UsePopCountInstruction)
1850 return false;
1851 case Op_CompareAndSwapL:
1852 #ifdef _LP64
1853 case Op_CompareAndSwapP:
1854 #endif
1855 if (!VM_Version::supports_cx8())
1856 return false;
1857 break;
1858 }
1859
1860 return true; // Per default match rules are supported.
1861 }
1862
1863 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
1864
1865 // TODO
1866 // identify extra cases that we might want to provide match rules for
1867 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
1868 bool ret_value = match_rule_supported(opcode);
1869 // Add rules here.
1870
1871 return ret_value; // Per default match rules are supported.
1872 }
1873
1874 const int Matcher::float_pressure(int default_pressure_threshold) {
1875 return default_pressure_threshold;
1876 }
1877
1878 int Matcher::regnum_to_fpu_offset(int regnum) {
1879 return regnum - 32; // The FP registers are in the second chunk
1880 }
1881
1882 #ifdef ASSERT
1883 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1884 #endif
1885
1886 // Vector width in bytes
1887 const int Matcher::vector_width_in_bytes(BasicType bt) {
1888 assert(MaxVectorSize == 8, "");
1889 return 8;
1890 }
1891
1892 // Vector ideal reg
1893 const int Matcher::vector_ideal_reg(int size) {
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